1 /******************************************************************************
2  *
3  * Copyright(c) 2009-2012  Realtek Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * The full GNU General Public License is included in this distribution in the
15  * file called LICENSE.
16  *
17  * Contact Information:
18  * wlanfae <wlanfae@realtek.com>
19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20  * Hsinchu 300, Taiwan.
21  *
22  * Larry Finger <Larry.Finger@lwfinger.net>
23  *
24  *****************************************************************************/
25 
26 #ifndef __RTL92C_DEF_H__
27 #define __RTL92C_DEF_H__
28 
29 #define	PHY_RSSI_SLID_WIN_MAX				100
30 #define	PHY_LINKQUALITY_SLID_WIN_MAX			20
31 #define	PHY_BEACON_RSSI_SLID_WIN_MAX			10
32 
33 #define RX_SMOOTH_FACTOR				20
34 
35 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE			0
36 #define HAL_PRIME_CHNL_OFFSET_LOWER			1
37 #define HAL_PRIME_CHNL_OFFSET_UPPER			2
38 
39 #define RX_MPDU_QUEUE					0
40 #define RX_CMD_QUEUE					1
41 
42 #define	C2H_RX_CMD_HDR_LEN				8
43 #define	GET_C2H_CMD_CMD_LEN(__prxhdr)		\
44 	LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
45 #define	GET_C2H_CMD_ELEMENT_ID(__prxhdr)	\
46 	LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
47 #define	GET_C2H_CMD_CMD_SEQ(__prxhdr)		\
48 	LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
49 #define	GET_C2H_CMD_CONTINUE(__prxhdr)		\
50 	LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
51 #define	GET_C2H_CMD_CONTENT(__prxhdr)		\
52 	((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
53 
54 #define	GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr)	\
55 	LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
56 #define	GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr)	\
57 	LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
58 #define	GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr)	\
59 	LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
60 #define	GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr)	\
61 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
62 #define	GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr)	\
63 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
64 #define	GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr)	\
65 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
66 #define	GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr)	\
67 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
68 #define	GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr)	\
69 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
70 #define	GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr)	\
71 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
72 #define GET_RX_STATUS_DESC_BUFF_ADDR(__pdesc)			\
73 	SHIFT_AND_MASK_LE(__pdesc + 24, 0, 32)
74 
75 #define CHIP_VER_B			BIT(4)
76 #define CHIP_BONDING_IDENTIFIER(_value) (((_value) >> 22) & 0x3)
77 #define CHIP_BONDING_92C_1T2R		0x1
78 #define RF_TYPE_1T2R			BIT(1)
79 #define CHIP_92C_BITMASK		BIT(0)
80 #define CHIP_UNKNOWN			BIT(7)
81 #define CHIP_92C_1T2R			0x03
82 #define CHIP_92C			0x01
83 #define CHIP_88C			0x00
84 
85 enum version_8192c {
86 	VERSION_A_CHIP_92C = 0x01,
87 	VERSION_A_CHIP_88C = 0x00,
88 	VERSION_B_CHIP_92C = 0x11,
89 	VERSION_B_CHIP_88C = 0x10,
90 	VERSION_TEST_CHIP_88C = 0x00,
91 	VERSION_TEST_CHIP_92C = 0x01,
92 	VERSION_NORMAL_TSMC_CHIP_88C = 0x10,
93 	VERSION_NORMAL_TSMC_CHIP_92C = 0x11,
94 	VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13,
95 	VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30,
96 	VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31,
97 	VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33,
98 	VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34,
99 	VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c,
100 	VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70,
101 	VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71,
102 	VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73,
103 	VERSION_UNKNOWN = 0x88,
104 };
105 
106 enum rtl819x_loopback_e {
107 	RTL819X_NO_LOOPBACK = 0,
108 	RTL819X_MAC_LOOPBACK = 1,
109 	RTL819X_DMA_LOOPBACK = 2,
110 	RTL819X_CCK_LOOPBACK = 3,
111 };
112 
113 enum rf_optype {
114 	RF_OP_BY_SW_3WIRE = 0,
115 	RF_OP_BY_FW,
116 	RF_OP_MAX
117 };
118 
119 enum rf_power_state {
120 	RF_ON,
121 	RF_OFF,
122 	RF_SLEEP,
123 	RF_SHUT_DOWN,
124 };
125 
126 enum power_save_mode {
127 	POWER_SAVE_MODE_ACTIVE,
128 	POWER_SAVE_MODE_SAVE,
129 };
130 
131 enum power_polocy_config {
132 	POWERCFG_MAX_POWER_SAVINGS,
133 	POWERCFG_GLOBAL_POWER_SAVINGS,
134 	POWERCFG_LOCAL_POWER_SAVINGS,
135 	POWERCFG_LENOVO,
136 };
137 
138 enum interface_select_pci {
139 	INTF_SEL1_MINICARD = 0,
140 	INTF_SEL0_PCIE = 1,
141 	INTF_SEL2_RSV = 2,
142 	INTF_SEL3_RSV = 3,
143 };
144 
145 enum rtl_desc_qsel {
146 	QSLT_BK = 0x2,
147 	QSLT_BE = 0x0,
148 	QSLT_VI = 0x5,
149 	QSLT_VO = 0x7,
150 	QSLT_BEACON = 0x10,
151 	QSLT_HIGH = 0x11,
152 	QSLT_MGNT = 0x12,
153 	QSLT_CMD = 0x13,
154 };
155 
156 struct phy_sts_cck_8192s_t {
157 	u8 adc_pwdb_X[4];
158 	u8 sq_rpt;
159 	u8 cck_agc_rpt;
160 };
161 
162 struct h2c_cmd_8192c {
163 	u8 element_id;
164 	u32 cmd_len;
165 	u8 *p_cmdbuffer;
166 };
167 
168 #endif
169