1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #ifndef __RTL92C_DEF_H__
5 #define __RTL92C_DEF_H__
6 
7 #define	PHY_RSSI_SLID_WIN_MAX				100
8 #define	PHY_LINKQUALITY_SLID_WIN_MAX			20
9 #define	PHY_BEACON_RSSI_SLID_WIN_MAX			10
10 
11 #define RX_SMOOTH_FACTOR				20
12 
13 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE			0
14 #define HAL_PRIME_CHNL_OFFSET_LOWER			1
15 #define HAL_PRIME_CHNL_OFFSET_UPPER			2
16 
17 #define RX_MPDU_QUEUE					0
18 #define RX_CMD_QUEUE					1
19 
20 #define	C2H_RX_CMD_HDR_LEN				8
21 #define	GET_C2H_CMD_CMD_LEN(__prxhdr)		\
22 	LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
23 #define	GET_C2H_CMD_ELEMENT_ID(__prxhdr)	\
24 	LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
25 #define	GET_C2H_CMD_CMD_SEQ(__prxhdr)		\
26 	LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
27 #define	GET_C2H_CMD_CONTINUE(__prxhdr)		\
28 	LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
29 #define	GET_C2H_CMD_CONTENT(__prxhdr)		\
30 	((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
31 
32 #define	GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr)	\
33 	LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
34 #define	GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr)	\
35 	LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
36 #define	GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr)	\
37 	LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
38 #define	GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr)	\
39 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
40 #define	GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr)	\
41 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
42 #define	GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr)	\
43 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
44 #define	GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr)	\
45 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
46 #define	GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr)	\
47 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
48 #define	GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr)	\
49 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
50 #define GET_RX_STATUS_DESC_BUFF_ADDR(__pdesc)			\
51 	SHIFT_AND_MASK_LE(__pdesc + 24, 0, 32)
52 
53 #define CHIP_VER_B			BIT(4)
54 #define CHIP_BONDING_IDENTIFIER(_value) (((_value) >> 22) & 0x3)
55 #define CHIP_BONDING_92C_1T2R		0x1
56 #define RF_TYPE_1T2R			BIT(1)
57 #define CHIP_92C_BITMASK		BIT(0)
58 #define CHIP_UNKNOWN			BIT(7)
59 #define CHIP_92C_1T2R			0x03
60 #define CHIP_92C			0x01
61 #define CHIP_88C			0x00
62 
63 enum version_8192c {
64 	VERSION_A_CHIP_92C = 0x01,
65 	VERSION_A_CHIP_88C = 0x00,
66 	VERSION_B_CHIP_92C = 0x11,
67 	VERSION_B_CHIP_88C = 0x10,
68 	VERSION_TEST_CHIP_88C = 0x00,
69 	VERSION_TEST_CHIP_92C = 0x01,
70 	VERSION_NORMAL_TSMC_CHIP_88C = 0x10,
71 	VERSION_NORMAL_TSMC_CHIP_92C = 0x11,
72 	VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13,
73 	VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30,
74 	VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31,
75 	VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33,
76 	VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34,
77 	VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c,
78 	VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70,
79 	VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71,
80 	VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73,
81 	VERSION_UNKNOWN = 0x88,
82 };
83 
84 enum rtl819x_loopback_e {
85 	RTL819X_NO_LOOPBACK = 0,
86 	RTL819X_MAC_LOOPBACK = 1,
87 	RTL819X_DMA_LOOPBACK = 2,
88 	RTL819X_CCK_LOOPBACK = 3,
89 };
90 
91 enum rf_optype {
92 	RF_OP_BY_SW_3WIRE = 0,
93 	RF_OP_BY_FW,
94 	RF_OP_MAX
95 };
96 
97 enum rf_power_state {
98 	RF_ON,
99 	RF_OFF,
100 	RF_SLEEP,
101 	RF_SHUT_DOWN,
102 };
103 
104 enum power_save_mode {
105 	POWER_SAVE_MODE_ACTIVE,
106 	POWER_SAVE_MODE_SAVE,
107 };
108 
109 enum power_polocy_config {
110 	POWERCFG_MAX_POWER_SAVINGS,
111 	POWERCFG_GLOBAL_POWER_SAVINGS,
112 	POWERCFG_LOCAL_POWER_SAVINGS,
113 	POWERCFG_LENOVO,
114 };
115 
116 enum interface_select_pci {
117 	INTF_SEL1_MINICARD = 0,
118 	INTF_SEL0_PCIE = 1,
119 	INTF_SEL2_RSV = 2,
120 	INTF_SEL3_RSV = 3,
121 };
122 
123 enum rtl_desc_qsel {
124 	QSLT_BK = 0x2,
125 	QSLT_BE = 0x0,
126 	QSLT_VI = 0x5,
127 	QSLT_VO = 0x7,
128 	QSLT_BEACON = 0x10,
129 	QSLT_HIGH = 0x11,
130 	QSLT_MGNT = 0x12,
131 	QSLT_CMD = 0x13,
132 };
133 
134 struct phy_sts_cck_8192s_t {
135 	u8 adc_pwdb_X[4];
136 	u8 sq_rpt;
137 	u8 cck_agc_rpt;
138 };
139 
140 struct h2c_cmd_8192c {
141 	u8 element_id;
142 	u32 cmd_len;
143 	u8 *p_cmdbuffer;
144 };
145 
146 #endif
147