1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include <linux/export.h> 27 #include "dm_common.h" 28 #include "phy_common.h" 29 #include "../pci.h" 30 #include "../base.h" 31 #include "../core.h" 32 33 #define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1) 34 #define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1) 35 #define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1) 36 #define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1) 37 #define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1) 38 #define BT_MASK 0x00ffffff 39 40 #define RTLPRIV (struct rtl_priv *) 41 #define GET_UNDECORATED_AVERAGE_RSSI(_priv) \ 42 ((RTLPRIV(_priv))->mac80211.opmode == \ 43 NL80211_IFTYPE_ADHOC) ? \ 44 ((RTLPRIV(_priv))->dm.entry_min_undec_sm_pwdb) : \ 45 ((RTLPRIV(_priv))->dm.undec_sm_pwdb) 46 47 static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = { 48 0x7f8001fe, 49 0x788001e2, 50 0x71c001c7, 51 0x6b8001ae, 52 0x65400195, 53 0x5fc0017f, 54 0x5a400169, 55 0x55400155, 56 0x50800142, 57 0x4c000130, 58 0x47c0011f, 59 0x43c0010f, 60 0x40000100, 61 0x3c8000f2, 62 0x390000e4, 63 0x35c000d7, 64 0x32c000cb, 65 0x300000c0, 66 0x2d4000b5, 67 0x2ac000ab, 68 0x288000a2, 69 0x26000098, 70 0x24000090, 71 0x22000088, 72 0x20000080, 73 0x1e400079, 74 0x1c800072, 75 0x1b00006c, 76 0x19800066, 77 0x18000060, 78 0x16c0005b, 79 0x15800056, 80 0x14400051, 81 0x1300004c, 82 0x12000048, 83 0x11000044, 84 0x10000040, 85 }; 86 87 static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = { 88 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, 89 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, 90 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, 91 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, 92 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, 93 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, 94 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, 95 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, 96 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, 97 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, 98 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, 99 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, 100 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, 101 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, 102 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, 103 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, 104 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, 105 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, 106 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, 107 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, 108 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, 109 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, 110 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, 111 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, 112 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, 113 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, 114 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, 115 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, 116 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, 117 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, 118 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, 119 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, 120 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} 121 }; 122 123 static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = { 124 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, 125 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, 126 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, 127 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, 128 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, 129 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, 130 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, 131 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, 132 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, 133 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, 134 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, 135 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, 136 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, 137 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, 138 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, 139 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, 140 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, 141 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, 142 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, 143 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, 144 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, 145 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, 146 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, 147 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, 148 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, 149 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, 150 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, 151 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, 152 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, 153 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, 154 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, 155 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, 156 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} 157 }; 158 159 static u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; 160 161 void dm_restorepowerindex(struct ieee80211_hw *hw) 162 { 163 struct rtl_priv *rtlpriv = rtl_priv(hw); 164 u8 index; 165 166 for (index = 0; index < 6; index++) 167 rtl_write_byte(rtlpriv, power_index_reg[index], 168 rtlpriv->dm.powerindex_backup[index]); 169 } 170 EXPORT_SYMBOL_GPL(dm_restorepowerindex); 171 172 void dm_writepowerindex(struct ieee80211_hw *hw, u8 value) 173 { 174 struct rtl_priv *rtlpriv = rtl_priv(hw); 175 u8 index; 176 177 for (index = 0; index < 6; index++) 178 rtl_write_byte(rtlpriv, power_index_reg[index], value); 179 } 180 EXPORT_SYMBOL_GPL(dm_writepowerindex); 181 182 void dm_savepowerindex(struct ieee80211_hw *hw) 183 { 184 struct rtl_priv *rtlpriv = rtl_priv(hw); 185 u8 index; 186 u8 tmp; 187 188 for (index = 0; index < 6; index++) { 189 tmp = rtl_read_byte(rtlpriv, power_index_reg[index]); 190 rtlpriv->dm.powerindex_backup[index] = tmp; 191 } 192 } 193 EXPORT_SYMBOL_GPL(dm_savepowerindex); 194 195 static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw) 196 { 197 struct rtl_priv *rtlpriv = rtl_priv(hw); 198 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 199 long rssi_val_min = 0; 200 201 if ((dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) && 202 (dm_digtable->cursta_cstate == DIG_STA_CONNECT)) { 203 if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0) 204 rssi_val_min = 205 (rtlpriv->dm.entry_min_undec_sm_pwdb > 206 rtlpriv->dm.undec_sm_pwdb) ? 207 rtlpriv->dm.undec_sm_pwdb : 208 rtlpriv->dm.entry_min_undec_sm_pwdb; 209 else 210 rssi_val_min = rtlpriv->dm.undec_sm_pwdb; 211 } else if (dm_digtable->cursta_cstate == DIG_STA_CONNECT || 212 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT) { 213 rssi_val_min = rtlpriv->dm.undec_sm_pwdb; 214 } else if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) { 215 rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb; 216 } 217 218 if (rssi_val_min > 100) 219 rssi_val_min = 100; 220 return (u8)rssi_val_min; 221 } 222 223 static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) 224 { 225 u32 ret_value; 226 struct rtl_priv *rtlpriv = rtl_priv(hw); 227 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt); 228 229 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); 230 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); 231 232 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); 233 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); 234 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); 235 236 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); 237 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); 238 239 ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD); 240 falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff); 241 falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); 242 243 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail + 244 falsealm_cnt->cnt_rate_illegal + 245 falsealm_cnt->cnt_crc8_fail + 246 falsealm_cnt->cnt_mcs_fail + 247 falsealm_cnt->cnt_fast_fsync_fail + 248 falsealm_cnt->cnt_sb_search_fail; 249 250 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1); 251 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0); 252 falsealm_cnt->cnt_cck_fail = ret_value; 253 254 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3); 255 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8; 256 falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail + 257 falsealm_cnt->cnt_rate_illegal + 258 falsealm_cnt->cnt_crc8_fail + 259 falsealm_cnt->cnt_mcs_fail + 260 falsealm_cnt->cnt_cck_fail); 261 262 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1); 263 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0); 264 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0); 265 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2); 266 267 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 268 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n", 269 falsealm_cnt->cnt_parity_fail, 270 falsealm_cnt->cnt_rate_illegal, 271 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail); 272 273 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 274 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n", 275 falsealm_cnt->cnt_ofdm_fail, 276 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all); 277 } 278 279 static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw) 280 { 281 struct rtl_priv *rtlpriv = rtl_priv(hw); 282 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 283 u8 value_igi = dm_digtable->cur_igvalue; 284 285 if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0) 286 value_igi--; 287 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1) 288 value_igi += 0; 289 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2) 290 value_igi++; 291 else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2) 292 value_igi += 2; 293 294 if (value_igi > DM_DIG_FA_UPPER) 295 value_igi = DM_DIG_FA_UPPER; 296 else if (value_igi < DM_DIG_FA_LOWER) 297 value_igi = DM_DIG_FA_LOWER; 298 299 if (rtlpriv->falsealm_cnt.cnt_all > 10000) 300 value_igi = DM_DIG_FA_UPPER; 301 302 dm_digtable->cur_igvalue = value_igi; 303 rtl92c_dm_write_dig(hw); 304 } 305 306 static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw) 307 { 308 struct rtl_priv *rtlpriv = rtl_priv(hw); 309 struct dig_t *digtable = &rtlpriv->dm_digtable; 310 u32 isbt; 311 312 /* modify DIG lower bound, deal with abnormally large false alarm */ 313 if (rtlpriv->falsealm_cnt.cnt_all > 10000) { 314 digtable->large_fa_hit++; 315 if (digtable->forbidden_igi < digtable->cur_igvalue) { 316 digtable->forbidden_igi = digtable->cur_igvalue; 317 digtable->large_fa_hit = 1; 318 } 319 320 if (digtable->large_fa_hit >= 3) { 321 if ((digtable->forbidden_igi + 1) > 322 digtable->rx_gain_max) 323 digtable->rx_gain_min = digtable->rx_gain_max; 324 else 325 digtable->rx_gain_min = (digtable->forbidden_igi + 1); 326 digtable->recover_cnt = 3600; /* 3600=2hr */ 327 } 328 } else { 329 /* Recovery mechanism for IGI lower bound */ 330 if (digtable->recover_cnt != 0) { 331 digtable->recover_cnt--; 332 } else { 333 if (digtable->large_fa_hit == 0) { 334 if ((digtable->forbidden_igi-1) < DM_DIG_MIN) { 335 digtable->forbidden_igi = DM_DIG_MIN; 336 digtable->rx_gain_min = DM_DIG_MIN; 337 } else { 338 digtable->forbidden_igi--; 339 digtable->rx_gain_min = digtable->forbidden_igi + 1; 340 } 341 } else if (digtable->large_fa_hit == 3) { 342 digtable->large_fa_hit = 0; 343 } 344 } 345 } 346 if (rtlpriv->falsealm_cnt.cnt_all < 250) { 347 isbt = rtl_read_byte(rtlpriv, 0x4fd) & 0x01; 348 349 if (!isbt) { 350 if (rtlpriv->falsealm_cnt.cnt_all > 351 digtable->fa_lowthresh) { 352 if ((digtable->back_val - 2) < 353 digtable->back_range_min) 354 digtable->back_val = digtable->back_range_min; 355 else 356 digtable->back_val -= 2; 357 } else if (rtlpriv->falsealm_cnt.cnt_all < 358 digtable->fa_lowthresh) { 359 if ((digtable->back_val + 2) > 360 digtable->back_range_max) 361 digtable->back_val = digtable->back_range_max; 362 else 363 digtable->back_val += 2; 364 } 365 } else { 366 digtable->back_val = DM_DIG_BACKOFF_DEFAULT; 367 } 368 } else { 369 /* Adjust initial gain by false alarm */ 370 if (rtlpriv->falsealm_cnt.cnt_all > 1000) 371 digtable->cur_igvalue = digtable->pre_igvalue + 2; 372 else if (rtlpriv->falsealm_cnt.cnt_all > 750) 373 digtable->cur_igvalue = digtable->pre_igvalue + 1; 374 else if (rtlpriv->falsealm_cnt.cnt_all < 500) 375 digtable->cur_igvalue = digtable->pre_igvalue - 1; 376 } 377 378 /* Check initial gain by upper/lower bound */ 379 if (digtable->cur_igvalue > digtable->rx_gain_max) 380 digtable->cur_igvalue = digtable->rx_gain_max; 381 382 if (digtable->cur_igvalue < digtable->rx_gain_min) 383 digtable->cur_igvalue = digtable->rx_gain_min; 384 385 rtl92c_dm_write_dig(hw); 386 } 387 388 static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw) 389 { 390 static u8 initialized; /* initialized to false */ 391 struct rtl_priv *rtlpriv = rtl_priv(hw); 392 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 393 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 394 long rssi_strength = rtlpriv->dm.entry_min_undec_sm_pwdb; 395 bool multi_sta = false; 396 397 if (mac->opmode == NL80211_IFTYPE_ADHOC) 398 multi_sta = true; 399 400 if (!multi_sta || 401 dm_digtable->cursta_cstate == DIG_STA_DISCONNECT) { 402 initialized = false; 403 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX; 404 return; 405 } else if (initialized == false) { 406 initialized = true; 407 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0; 408 dm_digtable->cur_igvalue = 0x20; 409 rtl92c_dm_write_dig(hw); 410 } 411 412 if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) { 413 if ((rssi_strength < dm_digtable->rssi_lowthresh) && 414 (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) { 415 416 if (dm_digtable->dig_ext_port_stage == 417 DIG_EXT_PORT_STAGE_2) { 418 dm_digtable->cur_igvalue = 0x20; 419 rtl92c_dm_write_dig(hw); 420 } 421 422 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1; 423 } else if (rssi_strength > dm_digtable->rssi_highthresh) { 424 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_2; 425 rtl92c_dm_ctrl_initgain_by_fa(hw); 426 } 427 } else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) { 428 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0; 429 dm_digtable->cur_igvalue = 0x20; 430 rtl92c_dm_write_dig(hw); 431 } 432 433 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 434 "curmultista_cstate = %x dig_ext_port_stage %x\n", 435 dm_digtable->curmultista_cstate, 436 dm_digtable->dig_ext_port_stage); 437 } 438 439 static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw) 440 { 441 struct rtl_priv *rtlpriv = rtl_priv(hw); 442 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 443 444 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 445 "presta_cstate = %x, cursta_cstate = %x\n", 446 dm_digtable->presta_cstate, dm_digtable->cursta_cstate); 447 if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate || 448 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT || 449 dm_digtable->cursta_cstate == DIG_STA_CONNECT) { 450 451 if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) { 452 dm_digtable->rssi_val_min = 453 rtl92c_dm_initial_gain_min_pwdb(hw); 454 if (dm_digtable->rssi_val_min > 100) 455 dm_digtable->rssi_val_min = 100; 456 rtl92c_dm_ctrl_initgain_by_rssi(hw); 457 } 458 } else { 459 dm_digtable->rssi_val_min = 0; 460 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX; 461 dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT; 462 dm_digtable->cur_igvalue = 0x20; 463 dm_digtable->pre_igvalue = 0; 464 rtl92c_dm_write_dig(hw); 465 } 466 } 467 468 static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) 469 { 470 struct rtl_priv *rtlpriv = rtl_priv(hw); 471 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 472 473 if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) { 474 dm_digtable->rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw); 475 if (dm_digtable->rssi_val_min > 100) 476 dm_digtable->rssi_val_min = 100; 477 478 if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { 479 if (dm_digtable->rssi_val_min <= 25) 480 dm_digtable->cur_cck_pd_state = 481 CCK_PD_STAGE_LOWRSSI; 482 else 483 dm_digtable->cur_cck_pd_state = 484 CCK_PD_STAGE_HIGHRSSI; 485 } else { 486 if (dm_digtable->rssi_val_min <= 20) 487 dm_digtable->cur_cck_pd_state = 488 CCK_PD_STAGE_LOWRSSI; 489 else 490 dm_digtable->cur_cck_pd_state = 491 CCK_PD_STAGE_HIGHRSSI; 492 } 493 } else { 494 dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX; 495 } 496 497 if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) { 498 if ((dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) || 499 (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_MAX)) 500 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83); 501 else 502 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); 503 504 dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state; 505 } 506 } 507 508 static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw) 509 { 510 struct rtl_priv *rtlpriv = rtl_priv(hw); 511 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 512 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 513 514 if (mac->act_scanning) 515 return; 516 517 if (mac->link_state >= MAC80211_LINKED) 518 dm_digtable->cursta_cstate = DIG_STA_CONNECT; 519 else 520 dm_digtable->cursta_cstate = DIG_STA_DISCONNECT; 521 522 dm_digtable->curmultista_cstate = DIG_MULTISTA_DISCONNECT; 523 524 rtl92c_dm_initial_gain_sta(hw); 525 rtl92c_dm_initial_gain_multi_sta(hw); 526 rtl92c_dm_cck_packet_detection_thresh(hw); 527 528 dm_digtable->presta_cstate = dm_digtable->cursta_cstate; 529 530 } 531 532 static void rtl92c_dm_dig(struct ieee80211_hw *hw) 533 { 534 struct rtl_priv *rtlpriv = rtl_priv(hw); 535 536 if (rtlpriv->dm.dm_initialgain_enable == false) 537 return; 538 if (!(rtlpriv->dm.dm_flag & DYNAMIC_FUNC_DIG)) 539 return; 540 541 rtl92c_dm_ctrl_initgain_by_twoport(hw); 542 } 543 544 static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw) 545 { 546 struct rtl_priv *rtlpriv = rtl_priv(hw); 547 548 if (rtlpriv->rtlhal.interface == INTF_USB && 549 rtlpriv->rtlhal.board_type & 0x1) { 550 dm_savepowerindex(hw); 551 rtlpriv->dm.dynamic_txpower_enable = true; 552 } else { 553 rtlpriv->dm.dynamic_txpower_enable = false; 554 } 555 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL; 556 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 557 } 558 559 void rtl92c_dm_write_dig(struct ieee80211_hw *hw) 560 { 561 struct rtl_priv *rtlpriv = rtl_priv(hw); 562 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 563 564 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, 565 "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n", 566 dm_digtable->cur_igvalue, dm_digtable->pre_igvalue, 567 dm_digtable->back_val); 568 569 if (rtlpriv->rtlhal.interface == INTF_USB && 570 !dm_digtable->dig_enable_flag) { 571 dm_digtable->pre_igvalue = 0x17; 572 return; 573 } 574 dm_digtable->cur_igvalue -= 1; 575 if (dm_digtable->cur_igvalue < DM_DIG_MIN) 576 dm_digtable->cur_igvalue = DM_DIG_MIN; 577 578 if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) { 579 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, 580 dm_digtable->cur_igvalue); 581 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, 582 dm_digtable->cur_igvalue); 583 584 dm_digtable->pre_igvalue = dm_digtable->cur_igvalue; 585 } 586 RT_TRACE(rtlpriv, COMP_DIG, DBG_WARNING, 587 "dig values 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 588 dm_digtable->cur_igvalue, dm_digtable->pre_igvalue, 589 dm_digtable->rssi_val_min, dm_digtable->back_val, 590 dm_digtable->rx_gain_max, dm_digtable->rx_gain_min, 591 dm_digtable->large_fa_hit, dm_digtable->forbidden_igi); 592 } 593 EXPORT_SYMBOL(rtl92c_dm_write_dig); 594 595 static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw) 596 { 597 struct rtl_priv *rtlpriv = rtl_priv(hw); 598 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 599 long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff; 600 601 if (mac->link_state != MAC80211_LINKED) 602 return; 603 604 if (mac->opmode == NL80211_IFTYPE_ADHOC || 605 mac->opmode == NL80211_IFTYPE_AP) { 606 /* TODO: Handle ADHOC and AP Mode */ 607 } 608 609 if (tmpentry_max_pwdb != 0) 610 rtlpriv->dm.entry_max_undec_sm_pwdb = tmpentry_max_pwdb; 611 else 612 rtlpriv->dm.entry_max_undec_sm_pwdb = 0; 613 614 if (tmpentry_min_pwdb != 0xff) 615 rtlpriv->dm.entry_min_undec_sm_pwdb = tmpentry_min_pwdb; 616 else 617 rtlpriv->dm.entry_min_undec_sm_pwdb = 0; 618 619 /* TODO: 620 * if (mac->opmode == NL80211_IFTYPE_STATION) { 621 * if (rtlpriv->rtlhal.fw_ready) { 622 * u32 param = (u32)(rtlpriv->dm.undec_sm_pwdb << 16); 623 * rtl8192c_set_rssi_cmd(hw, param); 624 * } 625 * } 626 */ 627 } 628 629 void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw) 630 { 631 struct rtl_priv *rtlpriv = rtl_priv(hw); 632 rtlpriv->dm.current_turbo_edca = false; 633 rtlpriv->dm.is_any_nonbepkts = false; 634 rtlpriv->dm.is_cur_rdlstate = false; 635 } 636 EXPORT_SYMBOL(rtl92c_dm_init_edca_turbo); 637 638 static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw) 639 { 640 struct rtl_priv *rtlpriv = rtl_priv(hw); 641 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 642 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 643 644 static u64 last_txok_cnt; 645 static u64 last_rxok_cnt; 646 static u32 last_bt_edca_ul; 647 static u32 last_bt_edca_dl; 648 u64 cur_txok_cnt = 0; 649 u64 cur_rxok_cnt = 0; 650 u32 edca_be_ul = 0x5ea42b; 651 u32 edca_be_dl = 0x5ea42b; 652 bool bt_change_edca = false; 653 654 if ((last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) || 655 (last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) { 656 rtlpriv->dm.current_turbo_edca = false; 657 last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul; 658 last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl; 659 } 660 661 if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) { 662 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul; 663 bt_change_edca = true; 664 } 665 666 if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) { 667 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl; 668 bt_change_edca = true; 669 } 670 671 if (mac->link_state != MAC80211_LINKED) { 672 rtlpriv->dm.current_turbo_edca = false; 673 return; 674 } 675 676 if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) { 677 if (!(edca_be_ul & 0xffff0000)) 678 edca_be_ul |= 0x005e0000; 679 680 if (!(edca_be_dl & 0xffff0000)) 681 edca_be_dl |= 0x005e0000; 682 } 683 684 if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) && 685 (!rtlpriv->dm.disable_framebursting))) { 686 687 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt; 688 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt; 689 690 if (cur_rxok_cnt > 4 * cur_txok_cnt) { 691 if (!rtlpriv->dm.is_cur_rdlstate || 692 !rtlpriv->dm.current_turbo_edca) { 693 rtl_write_dword(rtlpriv, 694 REG_EDCA_BE_PARAM, 695 edca_be_dl); 696 rtlpriv->dm.is_cur_rdlstate = true; 697 } 698 } else { 699 if (rtlpriv->dm.is_cur_rdlstate || 700 !rtlpriv->dm.current_turbo_edca) { 701 rtl_write_dword(rtlpriv, 702 REG_EDCA_BE_PARAM, 703 edca_be_ul); 704 rtlpriv->dm.is_cur_rdlstate = false; 705 } 706 } 707 rtlpriv->dm.current_turbo_edca = true; 708 } else { 709 if (rtlpriv->dm.current_turbo_edca) { 710 u8 tmp = AC0_BE; 711 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, 712 &tmp); 713 rtlpriv->dm.current_turbo_edca = false; 714 } 715 } 716 717 rtlpriv->dm.is_any_nonbepkts = false; 718 last_txok_cnt = rtlpriv->stats.txbytesunicast; 719 last_rxok_cnt = rtlpriv->stats.rxbytesunicast; 720 } 721 722 static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw 723 *hw) 724 { 725 struct rtl_priv *rtlpriv = rtl_priv(hw); 726 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 727 struct rtl_phy *rtlphy = &(rtlpriv->phy); 728 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 729 u8 thermalvalue, delta, delta_lck, delta_iqk; 730 long ele_a, ele_d, temp_cck, val_x, value32; 731 long val_y, ele_c = 0; 732 u8 ofdm_index[2], ofdm_index_old[2] = {0, 0}, cck_index_old = 0; 733 s8 cck_index = 0; 734 int i; 735 bool is2t = IS_92C_SERIAL(rtlhal->version); 736 s8 txpwr_level[3] = {0, 0, 0}; 737 u8 ofdm_min_index = 6, rf; 738 739 rtlpriv->dm.txpower_trackinginit = true; 740 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 741 "rtl92c_dm_txpower_tracking_callback_thermalmeter\n"); 742 743 thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f); 744 745 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 746 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n", 747 thermalvalue, rtlpriv->dm.thermalvalue, 748 rtlefuse->eeprom_thermalmeter); 749 750 rtl92c_phy_ap_calibrate(hw, (thermalvalue - 751 rtlefuse->eeprom_thermalmeter)); 752 if (is2t) 753 rf = 2; 754 else 755 rf = 1; 756 757 if (thermalvalue) { 758 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 759 MASKDWORD) & MASKOFDM_D; 760 761 for (i = 0; i < OFDM_TABLE_LENGTH; i++) { 762 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) { 763 ofdm_index_old[0] = (u8) i; 764 765 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 766 "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n", 767 ROFDM0_XATXIQIMBALANCE, 768 ele_d, ofdm_index_old[0]); 769 break; 770 } 771 } 772 773 if (is2t) { 774 ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 775 MASKDWORD) & MASKOFDM_D; 776 777 for (i = 0; i < OFDM_TABLE_LENGTH; i++) { 778 if (ele_d == (ofdmswing_table[i] & 779 MASKOFDM_D)) { 780 ofdm_index_old[1] = (u8) i; 781 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, 782 DBG_LOUD, 783 "Initial pathB ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n", 784 ROFDM0_XBTXIQIMBALANCE, ele_d, 785 ofdm_index_old[1]); 786 break; 787 } 788 } 789 } 790 791 temp_cck = 792 rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK; 793 794 for (i = 0; i < CCK_TABLE_LENGTH; i++) { 795 if (rtlpriv->dm.cck_inch14) { 796 if (memcmp((void *)&temp_cck, 797 (void *)&cckswing_table_ch14[i][2], 798 4) == 0) { 799 cck_index_old = (u8) i; 800 801 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, 802 DBG_LOUD, 803 "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch 14 %d\n", 804 RCCK0_TXFILTER2, temp_cck, 805 cck_index_old, 806 rtlpriv->dm.cck_inch14); 807 break; 808 } 809 } else { 810 if (memcmp((void *)&temp_cck, 811 (void *) 812 &cckswing_table_ch1ch13[i][2], 813 4) == 0) { 814 cck_index_old = (u8) i; 815 816 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, 817 DBG_LOUD, 818 "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch14 %d\n", 819 RCCK0_TXFILTER2, temp_cck, 820 cck_index_old, 821 rtlpriv->dm.cck_inch14); 822 break; 823 } 824 } 825 } 826 827 if (!rtlpriv->dm.thermalvalue) { 828 rtlpriv->dm.thermalvalue = 829 rtlefuse->eeprom_thermalmeter; 830 rtlpriv->dm.thermalvalue_lck = thermalvalue; 831 rtlpriv->dm.thermalvalue_iqk = thermalvalue; 832 for (i = 0; i < rf; i++) 833 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; 834 rtlpriv->dm.cck_index = cck_index_old; 835 } 836 /* Handle USB High PA boards */ 837 838 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ? 839 (thermalvalue - rtlpriv->dm.thermalvalue) : 840 (rtlpriv->dm.thermalvalue - thermalvalue); 841 842 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ? 843 (thermalvalue - rtlpriv->dm.thermalvalue_lck) : 844 (rtlpriv->dm.thermalvalue_lck - thermalvalue); 845 846 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ? 847 (thermalvalue - rtlpriv->dm.thermalvalue_iqk) : 848 (rtlpriv->dm.thermalvalue_iqk - thermalvalue); 849 850 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 851 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n", 852 thermalvalue, rtlpriv->dm.thermalvalue, 853 rtlefuse->eeprom_thermalmeter, delta, delta_lck, 854 delta_iqk); 855 856 if (delta_lck > 1) { 857 rtlpriv->dm.thermalvalue_lck = thermalvalue; 858 rtl92c_phy_lc_calibrate(hw); 859 } 860 861 if (delta > 0 && rtlpriv->dm.txpower_track_control) { 862 if (thermalvalue > rtlpriv->dm.thermalvalue) { 863 for (i = 0; i < rf; i++) 864 rtlpriv->dm.ofdm_index[i] -= delta; 865 rtlpriv->dm.cck_index -= delta; 866 } else { 867 for (i = 0; i < rf; i++) 868 rtlpriv->dm.ofdm_index[i] += delta; 869 rtlpriv->dm.cck_index += delta; 870 } 871 872 if (is2t) { 873 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 874 "temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n", 875 rtlpriv->dm.ofdm_index[0], 876 rtlpriv->dm.ofdm_index[1], 877 rtlpriv->dm.cck_index); 878 } else { 879 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 880 "temp OFDM_A_index=0x%x, cck_index=0x%x\n", 881 rtlpriv->dm.ofdm_index[0], 882 rtlpriv->dm.cck_index); 883 } 884 885 if (thermalvalue > rtlefuse->eeprom_thermalmeter) { 886 for (i = 0; i < rf; i++) 887 ofdm_index[i] = 888 rtlpriv->dm.ofdm_index[i] 889 + 1; 890 cck_index = rtlpriv->dm.cck_index + 1; 891 } else { 892 for (i = 0; i < rf; i++) 893 ofdm_index[i] = 894 rtlpriv->dm.ofdm_index[i]; 895 cck_index = rtlpriv->dm.cck_index; 896 } 897 898 for (i = 0; i < rf; i++) { 899 if (txpwr_level[i] >= 0 && 900 txpwr_level[i] <= 26) { 901 if (thermalvalue > 902 rtlefuse->eeprom_thermalmeter) { 903 if (delta < 5) 904 ofdm_index[i] -= 1; 905 906 else 907 ofdm_index[i] -= 2; 908 } else if (delta > 5 && thermalvalue < 909 rtlefuse-> 910 eeprom_thermalmeter) { 911 ofdm_index[i] += 1; 912 } 913 } else if (txpwr_level[i] >= 27 && 914 txpwr_level[i] <= 32 915 && thermalvalue > 916 rtlefuse->eeprom_thermalmeter) { 917 if (delta < 5) 918 ofdm_index[i] -= 1; 919 920 else 921 ofdm_index[i] -= 2; 922 } else if (txpwr_level[i] >= 32 && 923 txpwr_level[i] <= 38 && 924 thermalvalue > 925 rtlefuse->eeprom_thermalmeter 926 && delta > 5) { 927 ofdm_index[i] -= 1; 928 } 929 } 930 931 if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) { 932 if (thermalvalue > 933 rtlefuse->eeprom_thermalmeter) { 934 if (delta < 5) 935 cck_index -= 1; 936 937 else 938 cck_index -= 2; 939 } else if (delta > 5 && thermalvalue < 940 rtlefuse->eeprom_thermalmeter) { 941 cck_index += 1; 942 } 943 } else if (txpwr_level[i] >= 27 && 944 txpwr_level[i] <= 32 && 945 thermalvalue > 946 rtlefuse->eeprom_thermalmeter) { 947 if (delta < 5) 948 cck_index -= 1; 949 950 else 951 cck_index -= 2; 952 } else if (txpwr_level[i] >= 32 && 953 txpwr_level[i] <= 38 && 954 thermalvalue > rtlefuse->eeprom_thermalmeter 955 && delta > 5) { 956 cck_index -= 1; 957 } 958 959 for (i = 0; i < rf; i++) { 960 if (ofdm_index[i] > OFDM_TABLE_SIZE - 1) 961 ofdm_index[i] = OFDM_TABLE_SIZE - 1; 962 963 else if (ofdm_index[i] < ofdm_min_index) 964 ofdm_index[i] = ofdm_min_index; 965 } 966 967 if (cck_index > CCK_TABLE_SIZE - 1) 968 cck_index = CCK_TABLE_SIZE - 1; 969 else if (cck_index < 0) 970 cck_index = 0; 971 972 if (is2t) { 973 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 974 "new OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n", 975 ofdm_index[0], ofdm_index[1], 976 cck_index); 977 } else { 978 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 979 "new OFDM_A_index=0x%x, cck_index=0x%x\n", 980 ofdm_index[0], cck_index); 981 } 982 } 983 984 if (rtlpriv->dm.txpower_track_control && delta != 0) { 985 ele_d = 986 (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22; 987 val_x = rtlphy->reg_e94; 988 val_y = rtlphy->reg_e9c; 989 990 if (val_x != 0) { 991 if ((val_x & 0x00000200) != 0) 992 val_x = val_x | 0xFFFFFC00; 993 ele_a = ((val_x * ele_d) >> 8) & 0x000003FF; 994 995 if ((val_y & 0x00000200) != 0) 996 val_y = val_y | 0xFFFFFC00; 997 ele_c = ((val_y * ele_d) >> 8) & 0x000003FF; 998 999 value32 = (ele_d << 22) | 1000 ((ele_c & 0x3F) << 16) | ele_a; 1001 1002 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 1003 MASKDWORD, value32); 1004 1005 value32 = (ele_c & 0x000003C0) >> 6; 1006 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, 1007 value32); 1008 1009 value32 = ((val_x * ele_d) >> 7) & 0x01; 1010 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1011 BIT(31), value32); 1012 1013 value32 = ((val_y * ele_d) >> 7) & 0x01; 1014 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1015 BIT(29), value32); 1016 } else { 1017 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 1018 MASKDWORD, 1019 ofdmswing_table[ofdm_index[0]]); 1020 1021 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, 1022 0x00); 1023 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1024 BIT(31) | BIT(29), 0x00); 1025 } 1026 1027 if (!rtlpriv->dm.cck_inch14) { 1028 rtl_write_byte(rtlpriv, 0xa22, 1029 cckswing_table_ch1ch13[cck_index] 1030 [0]); 1031 rtl_write_byte(rtlpriv, 0xa23, 1032 cckswing_table_ch1ch13[cck_index] 1033 [1]); 1034 rtl_write_byte(rtlpriv, 0xa24, 1035 cckswing_table_ch1ch13[cck_index] 1036 [2]); 1037 rtl_write_byte(rtlpriv, 0xa25, 1038 cckswing_table_ch1ch13[cck_index] 1039 [3]); 1040 rtl_write_byte(rtlpriv, 0xa26, 1041 cckswing_table_ch1ch13[cck_index] 1042 [4]); 1043 rtl_write_byte(rtlpriv, 0xa27, 1044 cckswing_table_ch1ch13[cck_index] 1045 [5]); 1046 rtl_write_byte(rtlpriv, 0xa28, 1047 cckswing_table_ch1ch13[cck_index] 1048 [6]); 1049 rtl_write_byte(rtlpriv, 0xa29, 1050 cckswing_table_ch1ch13[cck_index] 1051 [7]); 1052 } else { 1053 rtl_write_byte(rtlpriv, 0xa22, 1054 cckswing_table_ch14[cck_index] 1055 [0]); 1056 rtl_write_byte(rtlpriv, 0xa23, 1057 cckswing_table_ch14[cck_index] 1058 [1]); 1059 rtl_write_byte(rtlpriv, 0xa24, 1060 cckswing_table_ch14[cck_index] 1061 [2]); 1062 rtl_write_byte(rtlpriv, 0xa25, 1063 cckswing_table_ch14[cck_index] 1064 [3]); 1065 rtl_write_byte(rtlpriv, 0xa26, 1066 cckswing_table_ch14[cck_index] 1067 [4]); 1068 rtl_write_byte(rtlpriv, 0xa27, 1069 cckswing_table_ch14[cck_index] 1070 [5]); 1071 rtl_write_byte(rtlpriv, 0xa28, 1072 cckswing_table_ch14[cck_index] 1073 [6]); 1074 rtl_write_byte(rtlpriv, 0xa29, 1075 cckswing_table_ch14[cck_index] 1076 [7]); 1077 } 1078 1079 if (is2t) { 1080 ele_d = (ofdmswing_table[ofdm_index[1]] & 1081 0xFFC00000) >> 22; 1082 1083 val_x = rtlphy->reg_eb4; 1084 val_y = rtlphy->reg_ebc; 1085 1086 if (val_x != 0) { 1087 if ((val_x & 0x00000200) != 0) 1088 val_x = val_x | 0xFFFFFC00; 1089 ele_a = ((val_x * ele_d) >> 8) & 1090 0x000003FF; 1091 1092 if ((val_y & 0x00000200) != 0) 1093 val_y = val_y | 0xFFFFFC00; 1094 ele_c = ((val_y * ele_d) >> 8) & 1095 0x00003FF; 1096 1097 value32 = (ele_d << 22) | 1098 ((ele_c & 0x3F) << 16) | ele_a; 1099 rtl_set_bbreg(hw, 1100 ROFDM0_XBTXIQIMBALANCE, 1101 MASKDWORD, value32); 1102 1103 value32 = (ele_c & 0x000003C0) >> 6; 1104 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 1105 MASKH4BITS, value32); 1106 1107 value32 = ((val_x * ele_d) >> 7) & 0x01; 1108 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1109 BIT(27), value32); 1110 1111 value32 = ((val_y * ele_d) >> 7) & 0x01; 1112 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1113 BIT(25), value32); 1114 } else { 1115 rtl_set_bbreg(hw, 1116 ROFDM0_XBTXIQIMBALANCE, 1117 MASKDWORD, 1118 ofdmswing_table[ofdm_index 1119 [1]]); 1120 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 1121 MASKH4BITS, 0x00); 1122 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1123 BIT(27) | BIT(25), 0x00); 1124 } 1125 1126 } 1127 } 1128 1129 if (delta_iqk > 3) { 1130 rtlpriv->dm.thermalvalue_iqk = thermalvalue; 1131 rtl92c_phy_iq_calibrate(hw, false); 1132 } 1133 1134 if (rtlpriv->dm.txpower_track_control) 1135 rtlpriv->dm.thermalvalue = thermalvalue; 1136 } 1137 1138 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n"); 1139 1140 } 1141 1142 static void rtl92c_dm_initialize_txpower_tracking_thermalmeter( 1143 struct ieee80211_hw *hw) 1144 { 1145 struct rtl_priv *rtlpriv = rtl_priv(hw); 1146 1147 rtlpriv->dm.txpower_tracking = true; 1148 rtlpriv->dm.txpower_trackinginit = false; 1149 1150 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1151 "pMgntInfo->txpower_tracking = %d\n", 1152 rtlpriv->dm.txpower_tracking); 1153 } 1154 1155 static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw) 1156 { 1157 rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw); 1158 } 1159 1160 static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw) 1161 { 1162 rtl92c_dm_txpower_tracking_callback_thermalmeter(hw); 1163 } 1164 1165 static void rtl92c_dm_check_txpower_tracking_thermal_meter( 1166 struct ieee80211_hw *hw) 1167 { 1168 struct rtl_priv *rtlpriv = rtl_priv(hw); 1169 1170 if (!rtlpriv->dm.txpower_tracking) 1171 return; 1172 1173 if (!rtlpriv->dm.tm_trigger) { 1174 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK, 1175 0x60); 1176 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1177 "Trigger 92S Thermal Meter!!\n"); 1178 rtlpriv->dm.tm_trigger = 1; 1179 return; 1180 } else { 1181 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1182 "Schedule TxPowerTracking direct call!!\n"); 1183 rtl92c_dm_txpower_tracking_directcall(hw); 1184 rtlpriv->dm.tm_trigger = 0; 1185 } 1186 } 1187 1188 void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw) 1189 { 1190 rtl92c_dm_check_txpower_tracking_thermal_meter(hw); 1191 } 1192 EXPORT_SYMBOL(rtl92c_dm_check_txpower_tracking); 1193 1194 void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw) 1195 { 1196 struct rtl_priv *rtlpriv = rtl_priv(hw); 1197 struct rate_adaptive *p_ra = &(rtlpriv->ra); 1198 1199 p_ra->ratr_state = DM_RATR_STA_INIT; 1200 p_ra->pre_ratr_state = DM_RATR_STA_INIT; 1201 1202 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) 1203 rtlpriv->dm.useramask = true; 1204 else 1205 rtlpriv->dm.useramask = false; 1206 1207 } 1208 EXPORT_SYMBOL(rtl92c_dm_init_rate_adaptive_mask); 1209 1210 static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw) 1211 { 1212 struct rtl_priv *rtlpriv = rtl_priv(hw); 1213 struct ps_t *dm_pstable = &rtlpriv->dm_pstable; 1214 1215 dm_pstable->pre_ccastate = CCA_MAX; 1216 dm_pstable->cur_ccasate = CCA_MAX; 1217 dm_pstable->pre_rfstate = RF_MAX; 1218 dm_pstable->cur_rfstate = RF_MAX; 1219 dm_pstable->rssi_val_min = 0; 1220 } 1221 1222 void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal) 1223 { 1224 struct rtl_priv *rtlpriv = rtl_priv(hw); 1225 struct ps_t *dm_pstable = &rtlpriv->dm_pstable; 1226 1227 if (!rtlpriv->reg_init) { 1228 rtlpriv->reg_874 = (rtl_get_bbreg(hw, 1229 RFPGA0_XCD_RFINTERFACESW, 1230 MASKDWORD) & 0x1CC000) >> 14; 1231 1232 rtlpriv->reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1, 1233 MASKDWORD) & BIT(3)) >> 3; 1234 1235 rtlpriv->reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 1236 MASKDWORD) & 0xFF000000) >> 24; 1237 1238 rtlpriv->reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 1239 0xF000) >> 12; 1240 1241 rtlpriv->reg_init = true; 1242 } 1243 1244 if (!bforce_in_normal) { 1245 if (dm_pstable->rssi_val_min != 0) { 1246 if (dm_pstable->pre_rfstate == RF_NORMAL) { 1247 if (dm_pstable->rssi_val_min >= 30) 1248 dm_pstable->cur_rfstate = RF_SAVE; 1249 else 1250 dm_pstable->cur_rfstate = RF_NORMAL; 1251 } else { 1252 if (dm_pstable->rssi_val_min <= 25) 1253 dm_pstable->cur_rfstate = RF_NORMAL; 1254 else 1255 dm_pstable->cur_rfstate = RF_SAVE; 1256 } 1257 } else { 1258 dm_pstable->cur_rfstate = RF_MAX; 1259 } 1260 } else { 1261 dm_pstable->cur_rfstate = RF_NORMAL; 1262 } 1263 1264 if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) { 1265 if (dm_pstable->cur_rfstate == RF_SAVE) { 1266 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 1267 0x1C0000, 0x2); 1268 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0); 1269 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 1270 0xFF000000, 0x63); 1271 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 1272 0xC000, 0x2); 1273 rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3); 1274 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); 1275 rtl_set_bbreg(hw, 0x818, BIT(28), 0x1); 1276 } else { 1277 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 1278 0x1CC000, rtlpriv->reg_874); 1279 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 1280 rtlpriv->reg_c70); 1281 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000, 1282 rtlpriv->reg_85c); 1283 rtl_set_bbreg(hw, 0xa74, 0xF000, rtlpriv->reg_a74); 1284 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); 1285 } 1286 1287 dm_pstable->pre_rfstate = dm_pstable->cur_rfstate; 1288 } 1289 } 1290 EXPORT_SYMBOL(rtl92c_dm_rf_saving); 1291 1292 static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw) 1293 { 1294 struct rtl_priv *rtlpriv = rtl_priv(hw); 1295 struct ps_t *dm_pstable = &rtlpriv->dm_pstable; 1296 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1297 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1298 1299 /* Determine the minimum RSSI */ 1300 if (((mac->link_state == MAC80211_NOLINK)) && 1301 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) { 1302 dm_pstable->rssi_val_min = 0; 1303 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, "Not connected to any\n"); 1304 } 1305 1306 if (mac->link_state == MAC80211_LINKED) { 1307 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 1308 dm_pstable->rssi_val_min = 1309 rtlpriv->dm.entry_min_undec_sm_pwdb; 1310 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, 1311 "AP Client PWDB = 0x%lx\n", 1312 dm_pstable->rssi_val_min); 1313 } else { 1314 dm_pstable->rssi_val_min = rtlpriv->dm.undec_sm_pwdb; 1315 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, 1316 "STA Default Port PWDB = 0x%lx\n", 1317 dm_pstable->rssi_val_min); 1318 } 1319 } else { 1320 dm_pstable->rssi_val_min = 1321 rtlpriv->dm.entry_min_undec_sm_pwdb; 1322 1323 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, 1324 "AP Ext Port PWDB = 0x%lx\n", 1325 dm_pstable->rssi_val_min); 1326 } 1327 1328 /* Power Saving for 92C */ 1329 if (IS_92C_SERIAL(rtlhal->version)) 1330 ;/* rtl92c_dm_1r_cca(hw); */ 1331 else 1332 rtl92c_dm_rf_saving(hw, false); 1333 } 1334 1335 void rtl92c_dm_init(struct ieee80211_hw *hw) 1336 { 1337 struct rtl_priv *rtlpriv = rtl_priv(hw); 1338 1339 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER; 1340 rtlpriv->dm.dm_flag = DYNAMIC_FUNC_DISABLE | DYNAMIC_FUNC_DIG; 1341 rtlpriv->dm.undec_sm_pwdb = -1; 1342 rtlpriv->dm.undec_sm_cck = -1; 1343 rtlpriv->dm.dm_initialgain_enable = true; 1344 rtl_dm_diginit(hw, 0x20); 1345 1346 rtlpriv->dm.dm_flag |= HAL_DM_HIPWR_DISABLE; 1347 rtl92c_dm_init_dynamic_txpower(hw); 1348 1349 rtl92c_dm_init_edca_turbo(hw); 1350 rtl92c_dm_init_rate_adaptive_mask(hw); 1351 rtlpriv->dm.dm_flag |= DYNAMIC_FUNC_SS; 1352 rtl92c_dm_initialize_txpower_tracking(hw); 1353 rtl92c_dm_init_dynamic_bb_powersaving(hw); 1354 1355 rtlpriv->dm.ofdm_pkt_cnt = 0; 1356 rtlpriv->dm.dm_rssi_sel = RSSI_DEFAULT; 1357 } 1358 EXPORT_SYMBOL(rtl92c_dm_init); 1359 1360 void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw) 1361 { 1362 struct rtl_priv *rtlpriv = rtl_priv(hw); 1363 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1364 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1365 long undec_sm_pwdb; 1366 1367 if (!rtlpriv->dm.dynamic_txpower_enable) 1368 return; 1369 1370 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) { 1371 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 1372 return; 1373 } 1374 1375 if ((mac->link_state < MAC80211_LINKED) && 1376 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) { 1377 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 1378 "Not connected to any\n"); 1379 1380 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 1381 1382 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL; 1383 return; 1384 } 1385 1386 if (mac->link_state >= MAC80211_LINKED) { 1387 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 1388 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb; 1389 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1390 "AP Client PWDB = 0x%lx\n", 1391 undec_sm_pwdb); 1392 } else { 1393 undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb; 1394 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1395 "STA Default Port PWDB = 0x%lx\n", 1396 undec_sm_pwdb); 1397 } 1398 } else { 1399 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb; 1400 1401 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1402 "AP Ext Port PWDB = 0x%lx\n", 1403 undec_sm_pwdb); 1404 } 1405 1406 if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { 1407 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL2; 1408 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1409 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n"); 1410 } else if ((undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) && 1411 (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) { 1412 1413 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1; 1414 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1415 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n"); 1416 } else if (undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) { 1417 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 1418 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1419 "TXHIGHPWRLEVEL_NORMAL\n"); 1420 } 1421 1422 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) { 1423 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1424 "PHY_SetTxPowerLevel8192S() Channel = %d\n", 1425 rtlphy->current_channel); 1426 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel); 1427 if (rtlpriv->dm.dynamic_txhighpower_lvl == 1428 TXHIGHPWRLEVEL_NORMAL) 1429 dm_restorepowerindex(hw); 1430 else if (rtlpriv->dm.dynamic_txhighpower_lvl == 1431 TXHIGHPWRLEVEL_LEVEL1) 1432 dm_writepowerindex(hw, 0x14); 1433 else if (rtlpriv->dm.dynamic_txhighpower_lvl == 1434 TXHIGHPWRLEVEL_LEVEL2) 1435 dm_writepowerindex(hw, 0x10); 1436 } 1437 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl; 1438 } 1439 1440 void rtl92c_dm_watchdog(struct ieee80211_hw *hw) 1441 { 1442 struct rtl_priv *rtlpriv = rtl_priv(hw); 1443 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1444 bool fw_current_inpsmode = false; 1445 bool fw_ps_awake = true; 1446 1447 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 1448 (u8 *) (&fw_current_inpsmode)); 1449 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON, 1450 (u8 *) (&fw_ps_awake)); 1451 1452 if (ppsc->p2p_ps_info.p2p_ps_mode) 1453 fw_ps_awake = false; 1454 1455 if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) && 1456 fw_ps_awake) 1457 && (!ppsc->rfchange_inprogress)) { 1458 rtl92c_dm_pwdb_monitor(hw); 1459 rtl92c_dm_dig(hw); 1460 rtl92c_dm_false_alarm_counter_statistics(hw); 1461 rtl92c_dm_dynamic_bb_powersaving(hw); 1462 rtl92c_dm_dynamic_txpower(hw); 1463 rtl92c_dm_check_txpower_tracking(hw); 1464 /* rtl92c_dm_refresh_rate_adaptive_mask(hw); */ 1465 rtl92c_dm_bt_coexist(hw); 1466 rtl92c_dm_check_edca_turbo(hw); 1467 } 1468 } 1469 EXPORT_SYMBOL(rtl92c_dm_watchdog); 1470 1471 u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw) 1472 { 1473 struct rtl_priv *rtlpriv = rtl_priv(hw); 1474 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1475 long undec_sm_pwdb; 1476 u8 curr_bt_rssi_state = 0x00; 1477 1478 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1479 undec_sm_pwdb = GET_UNDECORATED_AVERAGE_RSSI(rtlpriv); 1480 } else { 1481 if (rtlpriv->dm.entry_min_undec_sm_pwdb == 0) 1482 undec_sm_pwdb = 100; 1483 else 1484 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb; 1485 } 1486 1487 /* Check RSSI to determine HighPower/NormalPower state for 1488 * BT coexistence. */ 1489 if (undec_sm_pwdb >= 67) 1490 curr_bt_rssi_state &= (~BT_RSSI_STATE_NORMAL_POWER); 1491 else if (undec_sm_pwdb < 62) 1492 curr_bt_rssi_state |= BT_RSSI_STATE_NORMAL_POWER; 1493 1494 /* Check RSSI to determine AMPDU setting for BT coexistence. */ 1495 if (undec_sm_pwdb >= 40) 1496 curr_bt_rssi_state &= (~BT_RSSI_STATE_AMDPU_OFF); 1497 else if (undec_sm_pwdb <= 32) 1498 curr_bt_rssi_state |= BT_RSSI_STATE_AMDPU_OFF; 1499 1500 /* Marked RSSI state. It will be used to determine BT coexistence 1501 * setting later. */ 1502 if (undec_sm_pwdb < 35) 1503 curr_bt_rssi_state |= BT_RSSI_STATE_SPECIAL_LOW; 1504 else 1505 curr_bt_rssi_state &= (~BT_RSSI_STATE_SPECIAL_LOW); 1506 1507 /* Check BT state related to BT_Idle in B/G mode. */ 1508 if (undec_sm_pwdb < 15) 1509 curr_bt_rssi_state |= BT_RSSI_STATE_BG_EDCA_LOW; 1510 else 1511 curr_bt_rssi_state &= (~BT_RSSI_STATE_BG_EDCA_LOW); 1512 1513 if (curr_bt_rssi_state != rtlpcipriv->bt_coexist.bt_rssi_state) { 1514 rtlpcipriv->bt_coexist.bt_rssi_state = curr_bt_rssi_state; 1515 return true; 1516 } else { 1517 return false; 1518 } 1519 } 1520 EXPORT_SYMBOL(rtl92c_bt_rssi_state_change); 1521 1522 static bool rtl92c_bt_state_change(struct ieee80211_hw *hw) 1523 { 1524 struct rtl_priv *rtlpriv = rtl_priv(hw); 1525 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1526 1527 u32 polling, ratio_tx, ratio_pri; 1528 u32 bt_tx, bt_pri; 1529 u8 bt_state; 1530 u8 cur_service_type; 1531 1532 if (rtlpriv->mac80211.link_state < MAC80211_LINKED) 1533 return false; 1534 1535 bt_state = rtl_read_byte(rtlpriv, 0x4fd); 1536 bt_tx = rtl_read_dword(rtlpriv, 0x488) & BT_MASK; 1537 bt_pri = rtl_read_dword(rtlpriv, 0x48c) & BT_MASK; 1538 polling = rtl_read_dword(rtlpriv, 0x490); 1539 1540 if (bt_tx == BT_MASK && bt_pri == BT_MASK && 1541 polling == 0xffffffff && bt_state == 0xff) 1542 return false; 1543 1544 bt_state &= BIT_OFFSET_LEN_MASK_32(0, 1); 1545 if (bt_state != rtlpcipriv->bt_coexist.bt_cur_state) { 1546 rtlpcipriv->bt_coexist.bt_cur_state = bt_state; 1547 1548 if (rtlpcipriv->bt_coexist.reg_bt_sco == 3) { 1549 rtlpcipriv->bt_coexist.bt_service = BT_IDLE; 1550 1551 bt_state = bt_state | 1552 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ? 1553 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) | 1554 BIT_OFFSET_LEN_MASK_32(2, 1); 1555 rtl_write_byte(rtlpriv, 0x4fd, bt_state); 1556 } 1557 return true; 1558 } 1559 1560 ratio_tx = bt_tx * 1000 / polling; 1561 ratio_pri = bt_pri * 1000 / polling; 1562 rtlpcipriv->bt_coexist.ratio_tx = ratio_tx; 1563 rtlpcipriv->bt_coexist.ratio_pri = ratio_pri; 1564 1565 if (bt_state && rtlpcipriv->bt_coexist.reg_bt_sco == 3) { 1566 1567 if ((ratio_tx < 30) && (ratio_pri < 30)) 1568 cur_service_type = BT_IDLE; 1569 else if ((ratio_pri > 110) && (ratio_pri < 250)) 1570 cur_service_type = BT_SCO; 1571 else if ((ratio_tx >= 200) && (ratio_pri >= 200)) 1572 cur_service_type = BT_BUSY; 1573 else if ((ratio_tx >= 350) && (ratio_tx < 500)) 1574 cur_service_type = BT_OTHERBUSY; 1575 else if (ratio_tx >= 500) 1576 cur_service_type = BT_PAN; 1577 else 1578 cur_service_type = BT_OTHER_ACTION; 1579 1580 if (cur_service_type != rtlpcipriv->bt_coexist.bt_service) { 1581 rtlpcipriv->bt_coexist.bt_service = cur_service_type; 1582 bt_state = bt_state | 1583 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ? 1584 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) | 1585 ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) ? 1586 0 : BIT_OFFSET_LEN_MASK_32(2, 1)); 1587 1588 /* Add interrupt migration when bt is not ini 1589 * idle state (no traffic). */ 1590 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) { 1591 rtl_write_word(rtlpriv, 0x504, 0x0ccc); 1592 rtl_write_byte(rtlpriv, 0x506, 0x54); 1593 rtl_write_byte(rtlpriv, 0x507, 0x54); 1594 } else { 1595 rtl_write_byte(rtlpriv, 0x506, 0x00); 1596 rtl_write_byte(rtlpriv, 0x507, 0x00); 1597 } 1598 1599 rtl_write_byte(rtlpriv, 0x4fd, bt_state); 1600 return true; 1601 } 1602 } 1603 1604 return false; 1605 1606 } 1607 1608 static bool rtl92c_bt_wifi_connect_change(struct ieee80211_hw *hw) 1609 { 1610 struct rtl_priv *rtlpriv = rtl_priv(hw); 1611 static bool media_connect; 1612 1613 if (rtlpriv->mac80211.link_state < MAC80211_LINKED) { 1614 media_connect = false; 1615 } else { 1616 if (!media_connect) { 1617 media_connect = true; 1618 return true; 1619 } 1620 media_connect = true; 1621 } 1622 1623 return false; 1624 } 1625 1626 static void rtl92c_bt_set_normal(struct ieee80211_hw *hw) 1627 { 1628 struct rtl_priv *rtlpriv = rtl_priv(hw); 1629 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1630 1631 1632 if (rtlpcipriv->bt_coexist.bt_service == BT_OTHERBUSY) { 1633 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72b; 1634 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72b; 1635 } else if (rtlpcipriv->bt_coexist.bt_service == BT_BUSY) { 1636 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82f; 1637 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82f; 1638 } else if (rtlpcipriv->bt_coexist.bt_service == BT_SCO) { 1639 if (rtlpcipriv->bt_coexist.ratio_tx > 160) { 1640 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72f; 1641 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72f; 1642 } else { 1643 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea32b; 1644 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea42b; 1645 } 1646 } else { 1647 rtlpcipriv->bt_coexist.bt_edca_ul = 0; 1648 rtlpcipriv->bt_coexist.bt_edca_dl = 0; 1649 } 1650 1651 if ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) && 1652 (rtlpriv->mac80211.mode == WIRELESS_MODE_G || 1653 (rtlpriv->mac80211.mode == (WIRELESS_MODE_G | WIRELESS_MODE_B))) && 1654 (rtlpcipriv->bt_coexist.bt_rssi_state & 1655 BT_RSSI_STATE_BG_EDCA_LOW)) { 1656 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82b; 1657 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82b; 1658 } 1659 } 1660 1661 static void rtl92c_bt_ant_isolation(struct ieee80211_hw *hw, u8 tmp1byte) 1662 { 1663 struct rtl_priv *rtlpriv = rtl_priv(hw); 1664 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1665 1666 1667 /* Only enable HW BT coexist when BT in "Busy" state. */ 1668 if (rtlpriv->mac80211.vendor == PEER_CISCO && 1669 rtlpcipriv->bt_coexist.bt_service == BT_OTHER_ACTION) { 1670 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0); 1671 } else { 1672 if ((rtlpcipriv->bt_coexist.bt_service == BT_BUSY) && 1673 (rtlpcipriv->bt_coexist.bt_rssi_state & 1674 BT_RSSI_STATE_NORMAL_POWER)) { 1675 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0); 1676 } else if ((rtlpcipriv->bt_coexist.bt_service == 1677 BT_OTHER_ACTION) && (rtlpriv->mac80211.mode < 1678 WIRELESS_MODE_N_24G) && 1679 (rtlpcipriv->bt_coexist.bt_rssi_state & 1680 BT_RSSI_STATE_SPECIAL_LOW)) { 1681 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0); 1682 } else if (rtlpcipriv->bt_coexist.bt_service == BT_PAN) { 1683 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte); 1684 } else { 1685 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte); 1686 } 1687 } 1688 1689 if (rtlpcipriv->bt_coexist.bt_service == BT_PAN) 1690 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x10100); 1691 else 1692 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x0); 1693 1694 if (rtlpcipriv->bt_coexist.bt_rssi_state & 1695 BT_RSSI_STATE_NORMAL_POWER) { 1696 rtl92c_bt_set_normal(hw); 1697 } else { 1698 rtlpcipriv->bt_coexist.bt_edca_ul = 0; 1699 rtlpcipriv->bt_coexist.bt_edca_dl = 0; 1700 } 1701 1702 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) { 1703 rtlpriv->cfg->ops->set_rfreg(hw, 1704 RF90_PATH_A, 1705 0x1e, 1706 0xf0, 0xf); 1707 } else { 1708 rtlpriv->cfg->ops->set_rfreg(hw, 1709 RF90_PATH_A, 0x1e, 0xf0, 1710 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e); 1711 } 1712 1713 if (!rtlpriv->dm.dynamic_txpower_enable) { 1714 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) { 1715 if (rtlpcipriv->bt_coexist.bt_rssi_state & 1716 BT_RSSI_STATE_TXPOWER_LOW) { 1717 rtlpriv->dm.dynamic_txhighpower_lvl = 1718 TXHIGHPWRLEVEL_BT2; 1719 } else { 1720 rtlpriv->dm.dynamic_txhighpower_lvl = 1721 TXHIGHPWRLEVEL_BT1; 1722 } 1723 } else { 1724 rtlpriv->dm.dynamic_txhighpower_lvl = 1725 TXHIGHPWRLEVEL_NORMAL; 1726 } 1727 rtl92c_phy_set_txpower_level(hw, 1728 rtlpriv->phy.current_channel); 1729 } 1730 } 1731 1732 static void rtl92c_check_bt_change(struct ieee80211_hw *hw) 1733 { 1734 struct rtl_priv *rtlpriv = rtl_priv(hw); 1735 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1736 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1737 u8 tmp1byte = 0; 1738 1739 if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version) && 1740 rtlpcipriv->bt_coexist.bt_coexistence) 1741 tmp1byte |= BIT(5); 1742 if (rtlpcipriv->bt_coexist.bt_cur_state) { 1743 if (rtlpcipriv->bt_coexist.bt_ant_isolation) 1744 rtl92c_bt_ant_isolation(hw, tmp1byte); 1745 } else { 1746 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte); 1747 rtlpriv->cfg->ops->set_rfreg(hw, RF90_PATH_A, 0x1e, 0xf0, 1748 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e); 1749 1750 rtlpcipriv->bt_coexist.bt_edca_ul = 0; 1751 rtlpcipriv->bt_coexist.bt_edca_dl = 0; 1752 } 1753 } 1754 1755 void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw) 1756 { 1757 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1758 1759 bool wifi_connect_change; 1760 bool bt_state_change; 1761 bool rssi_state_change; 1762 1763 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 1764 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) { 1765 1766 wifi_connect_change = rtl92c_bt_wifi_connect_change(hw); 1767 bt_state_change = rtl92c_bt_state_change(hw); 1768 rssi_state_change = rtl92c_bt_rssi_state_change(hw); 1769 1770 if (wifi_connect_change || bt_state_change || rssi_state_change) 1771 rtl92c_check_bt_change(hw); 1772 } 1773 } 1774 EXPORT_SYMBOL(rtl92c_dm_bt_coexist); 1775