1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2013 Realtek Corporation.*/ 3 4 #include "../wifi.h" 5 #include "../core.h" 6 #include "../pci.h" 7 #include "reg.h" 8 #include "def.h" 9 #include "phy.h" 10 #include "dm.h" 11 #include "hw.h" 12 #include "sw.h" 13 #include "trx.h" 14 #include "led.h" 15 #include "table.h" 16 17 #include <linux/vmalloc.h> 18 #include <linux/module.h> 19 20 static void rtl88e_init_aspm_vars(struct ieee80211_hw *hw) 21 { 22 struct rtl_priv *rtlpriv = rtl_priv(hw); 23 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 24 25 /*close ASPM for AMD defaultly */ 26 rtlpci->const_amdpci_aspm = 0; 27 28 /* ASPM PS mode. 29 * 0 - Disable ASPM, 30 * 1 - Enable ASPM without Clock Req, 31 * 2 - Enable ASPM with Clock Req, 32 * 3 - Alwyas Enable ASPM with Clock Req, 33 * 4 - Always Enable ASPM without Clock Req. 34 * set defult to RTL8192CE:3 RTL8192E:2 35 */ 36 rtlpci->const_pci_aspm = 3; 37 38 /*Setting for PCI-E device */ 39 rtlpci->const_devicepci_aspm_setting = 0x03; 40 41 /*Setting for PCI-E bridge */ 42 rtlpci->const_hostpci_aspm_setting = 0x02; 43 44 /* In Hw/Sw Radio Off situation. 45 * 0 - Default, 46 * 1 - From ASPM setting without low Mac Pwr, 47 * 2 - From ASPM setting with low Mac Pwr, 48 * 3 - Bus D3 49 * set default to RTL8192CE:0 RTL8192SE:2 50 */ 51 rtlpci->const_hwsw_rfoff_d3 = 0; 52 53 /* This setting works for those device with 54 * backdoor ASPM setting such as EPHY setting. 55 * 0 - Not support ASPM, 56 * 1 - Support ASPM, 57 * 2 - According to chipset. 58 */ 59 rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support; 60 } 61 62 int rtl88e_init_sw_vars(struct ieee80211_hw *hw) 63 { 64 int err = 0; 65 struct rtl_priv *rtlpriv = rtl_priv(hw); 66 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 67 u8 tid; 68 char *fw_name; 69 70 rtl8188ee_bt_reg_init(hw); 71 rtlpriv->dm.dm_initialgain_enable = 1; 72 rtlpriv->dm.dm_flag = 0; 73 rtlpriv->dm.disable_framebursting = 0; 74 rtlpriv->dm.thermalvalue = 0; 75 rtlpci->transmit_config = CFENDFORM | BIT(15); 76 77 /* compatible 5G band 88ce just 2.4G band & smsp */ 78 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G; 79 rtlpriv->rtlhal.bandset = BAND_ON_2_4G; 80 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY; 81 82 rtlpci->receive_config = (RCR_APPFCS | 83 RCR_APP_MIC | 84 RCR_APP_ICV | 85 RCR_APP_PHYST_RXFF | 86 RCR_HTC_LOC_CTRL | 87 RCR_AMF | 88 RCR_ACF | 89 RCR_ADF | 90 RCR_AICV | 91 RCR_ACRC32 | 92 RCR_AB | 93 RCR_AM | 94 RCR_APM | 95 0); 96 97 rtlpci->irq_mask[0] = 98 (u32)(IMR_PSTIMEOUT | 99 IMR_HSISR_IND_ON_INT | 100 IMR_C2HCMD | 101 IMR_HIGHDOK | 102 IMR_MGNTDOK | 103 IMR_BKDOK | 104 IMR_BEDOK | 105 IMR_VIDOK | 106 IMR_VODOK | 107 IMR_RDU | 108 IMR_ROK | 109 0); 110 rtlpci->irq_mask[1] = (u32) (IMR_RXFOVW | 0); 111 rtlpci->sys_irq_mask = (u32) (HSIMR_PDN_INT_EN | HSIMR_RON_INT_EN); 112 113 /* for LPS & IPS */ 114 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; 115 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; 116 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; 117 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support; 118 rtlpriv->cfg->mod_params->sw_crypto = 119 rtlpriv->cfg->mod_params->sw_crypto; 120 rtlpriv->cfg->mod_params->disable_watchdog = 121 rtlpriv->cfg->mod_params->disable_watchdog; 122 if (rtlpriv->cfg->mod_params->disable_watchdog) 123 pr_info("watchdog disabled\n"); 124 if (!rtlpriv->psc.inactiveps) 125 pr_info("rtl8188ee: Power Save off (module option)\n"); 126 if (!rtlpriv->psc.fwctrl_lps) 127 pr_info("rtl8188ee: FW Power Save off (module option)\n"); 128 rtlpriv->psc.reg_fwctrl_lps = 3; 129 rtlpriv->psc.reg_max_lps_awakeintvl = 5; 130 /* for ASPM, you can close aspm through 131 * set const_support_pciaspm = 0 132 */ 133 rtl88e_init_aspm_vars(hw); 134 135 if (rtlpriv->psc.reg_fwctrl_lps == 1) 136 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE; 137 else if (rtlpriv->psc.reg_fwctrl_lps == 2) 138 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE; 139 else if (rtlpriv->psc.reg_fwctrl_lps == 3) 140 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE; 141 142 /* for firmware buf */ 143 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000); 144 if (!rtlpriv->rtlhal.pfirmware) { 145 pr_info("Can't alloc buffer for fw.\n"); 146 return 1; 147 } 148 149 fw_name = "rtlwifi/rtl8188efw.bin"; 150 rtlpriv->max_fw_size = 0x8000; 151 pr_info("Using firmware %s\n", fw_name); 152 err = request_firmware_nowait(THIS_MODULE, 1, fw_name, 153 rtlpriv->io.dev, GFP_KERNEL, hw, 154 rtl_fw_cb); 155 if (err) { 156 pr_info("Failed to request firmware!\n"); 157 vfree(rtlpriv->rtlhal.pfirmware); 158 rtlpriv->rtlhal.pfirmware = NULL; 159 return 1; 160 } 161 162 /* for early mode */ 163 rtlpriv->rtlhal.earlymode_enable = false; 164 rtlpriv->rtlhal.max_earlymode_num = 10; 165 for (tid = 0; tid < 8; tid++) 166 skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]); 167 168 /*low power */ 169 rtlpriv->psc.low_power_enable = false; 170 if (rtlpriv->psc.low_power_enable) { 171 timer_setup(&rtlpriv->works.fw_clockoff_timer, 172 rtl88ee_fw_clk_off_timer_callback, 0); 173 } 174 175 timer_setup(&rtlpriv->works.fast_antenna_training_timer, 176 rtl88e_dm_fast_antenna_training_callback, 0); 177 return err; 178 } 179 180 void rtl88e_deinit_sw_vars(struct ieee80211_hw *hw) 181 { 182 struct rtl_priv *rtlpriv = rtl_priv(hw); 183 184 if (rtlpriv->rtlhal.pfirmware) { 185 vfree(rtlpriv->rtlhal.pfirmware); 186 rtlpriv->rtlhal.pfirmware = NULL; 187 } 188 189 if (rtlpriv->psc.low_power_enable) 190 del_timer_sync(&rtlpriv->works.fw_clockoff_timer); 191 192 del_timer_sync(&rtlpriv->works.fast_antenna_training_timer); 193 } 194 195 /* get bt coexist status */ 196 bool rtl88e_get_btc_status(void) 197 { 198 return false; 199 } 200 201 static struct rtl_hal_ops rtl8188ee_hal_ops = { 202 .init_sw_vars = rtl88e_init_sw_vars, 203 .deinit_sw_vars = rtl88e_deinit_sw_vars, 204 .read_eeprom_info = rtl88ee_read_eeprom_info, 205 .interrupt_recognized = rtl88ee_interrupt_recognized,/*need check*/ 206 .hw_init = rtl88ee_hw_init, 207 .hw_disable = rtl88ee_card_disable, 208 .hw_suspend = rtl88ee_suspend, 209 .hw_resume = rtl88ee_resume, 210 .enable_interrupt = rtl88ee_enable_interrupt, 211 .disable_interrupt = rtl88ee_disable_interrupt, 212 .set_network_type = rtl88ee_set_network_type, 213 .set_chk_bssid = rtl88ee_set_check_bssid, 214 .set_qos = rtl88ee_set_qos, 215 .set_bcn_reg = rtl88ee_set_beacon_related_registers, 216 .set_bcn_intv = rtl88ee_set_beacon_interval, 217 .update_interrupt_mask = rtl88ee_update_interrupt_mask, 218 .get_hw_reg = rtl88ee_get_hw_reg, 219 .set_hw_reg = rtl88ee_set_hw_reg, 220 .update_rate_tbl = rtl88ee_update_hal_rate_tbl, 221 .fill_tx_desc = rtl88ee_tx_fill_desc, 222 .fill_tx_cmddesc = rtl88ee_tx_fill_cmddesc, 223 .query_rx_desc = rtl88ee_rx_query_desc, 224 .set_channel_access = rtl88ee_update_channel_access_setting, 225 .radio_onoff_checking = rtl88ee_gpio_radio_on_off_checking, 226 .set_bw_mode = rtl88e_phy_set_bw_mode, 227 .switch_channel = rtl88e_phy_sw_chnl, 228 .dm_watchdog = rtl88e_dm_watchdog, 229 .scan_operation_backup = rtl88e_phy_scan_operation_backup, 230 .set_rf_power_state = rtl88e_phy_set_rf_power_state, 231 .led_control = rtl88ee_led_control, 232 .set_desc = rtl88ee_set_desc, 233 .get_desc = rtl88ee_get_desc, 234 .is_tx_desc_closed = rtl88ee_is_tx_desc_closed, 235 .tx_polling = rtl88ee_tx_polling, 236 .enable_hw_sec = rtl88ee_enable_hw_security_config, 237 .set_key = rtl88ee_set_key, 238 .init_sw_leds = rtl88ee_init_sw_leds, 239 .get_bbreg = rtl88e_phy_query_bb_reg, 240 .set_bbreg = rtl88e_phy_set_bb_reg, 241 .get_rfreg = rtl88e_phy_query_rf_reg, 242 .set_rfreg = rtl88e_phy_set_rf_reg, 243 .get_btc_status = rtl88e_get_btc_status, 244 }; 245 246 static struct rtl_mod_params rtl88ee_mod_params = { 247 .sw_crypto = false, 248 .inactiveps = true, 249 .swctrl_lps = false, 250 .fwctrl_lps = false, 251 .msi_support = true, 252 .aspm_support = 1, 253 .debug_level = 0, 254 .debug_mask = 0, 255 }; 256 257 static const struct rtl_hal_cfg rtl88ee_hal_cfg = { 258 .bar_id = 2, 259 .write_readback = true, 260 .name = "rtl88e_pci", 261 .ops = &rtl8188ee_hal_ops, 262 .mod_params = &rtl88ee_mod_params, 263 264 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, 265 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, 266 .maps[SYS_CLK] = REG_SYS_CLKR, 267 .maps[MAC_RCR_AM] = AM, 268 .maps[MAC_RCR_AB] = AB, 269 .maps[MAC_RCR_ACRC32] = ACRC32, 270 .maps[MAC_RCR_ACF] = ACF, 271 .maps[MAC_RCR_AAP] = AAP, 272 .maps[MAC_HIMR] = REG_HIMR, 273 .maps[MAC_HIMRE] = REG_HIMRE, 274 .maps[MAC_HSISR] = REG_HSISR, 275 276 .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS, 277 278 .maps[EFUSE_TEST] = REG_EFUSE_TEST, 279 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, 280 .maps[EFUSE_CLK] = 0, 281 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, 282 .maps[EFUSE_PWC_EV12V] = PWC_EV12V, 283 .maps[EFUSE_FEN_ELDR] = FEN_ELDR, 284 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN, 285 .maps[EFUSE_ANA8M] = ANA8M, 286 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE, 287 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION, 288 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN, 289 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES, 290 291 .maps[RWCAM] = REG_CAMCMD, 292 .maps[WCAMI] = REG_CAMWRITE, 293 .maps[RCAMO] = REG_CAMREAD, 294 .maps[CAMDBG] = REG_CAMDBG, 295 .maps[SECR] = REG_SECCFG, 296 .maps[SEC_CAM_NONE] = CAM_NONE, 297 .maps[SEC_CAM_WEP40] = CAM_WEP40, 298 .maps[SEC_CAM_TKIP] = CAM_TKIP, 299 .maps[SEC_CAM_AES] = CAM_AES, 300 .maps[SEC_CAM_WEP104] = CAM_WEP104, 301 302 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, 303 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, 304 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, 305 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, 306 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, 307 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, 308 /* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, */ /*need check*/ 309 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, 310 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, 311 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, 312 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, 313 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, 314 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, 315 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, 316 /* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/ 317 /* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/ 318 319 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, 320 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, 321 .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0, 322 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW, 323 .maps[RTL_IMR_RDU] = IMR_RDU, 324 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND, 325 .maps[RTL_IMR_BDOK] = IMR_BCNDOK0, 326 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK, 327 .maps[RTL_IMR_TBDER] = IMR_TBDER, 328 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK, 329 .maps[RTL_IMR_TBDOK] = IMR_TBDOK, 330 .maps[RTL_IMR_BKDOK] = IMR_BKDOK, 331 .maps[RTL_IMR_BEDOK] = IMR_BEDOK, 332 .maps[RTL_IMR_VIDOK] = IMR_VIDOK, 333 .maps[RTL_IMR_VODOK] = IMR_VODOK, 334 .maps[RTL_IMR_ROK] = IMR_ROK, 335 .maps[RTL_IMR_HSISR_IND] = IMR_HSISR_IND_ON_INT, 336 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER), 337 338 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M, 339 .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M, 340 .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M, 341 .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M, 342 .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M, 343 .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M, 344 .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M, 345 .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M, 346 .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M, 347 .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M, 348 .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M, 349 .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M, 350 351 .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7, 352 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15, 353 }; 354 355 static const struct pci_device_id rtl88ee_pci_ids[] = { 356 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8179, rtl88ee_hal_cfg)}, 357 {}, 358 }; 359 360 MODULE_DEVICE_TABLE(pci, rtl88ee_pci_ids); 361 362 MODULE_AUTHOR("zhiyuan_yang <zhiyuan_yang@realsil.com.cn>"); 363 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 364 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>"); 365 MODULE_LICENSE("GPL"); 366 MODULE_DESCRIPTION("Realtek 8188E 802.11n PCI wireless"); 367 MODULE_FIRMWARE("rtlwifi/rtl8188efw.bin"); 368 369 module_param_named(swenc, rtl88ee_mod_params.sw_crypto, bool, 0444); 370 module_param_named(debug_level, rtl88ee_mod_params.debug_level, int, 0644); 371 module_param_named(debug_mask, rtl88ee_mod_params.debug_mask, ullong, 0644); 372 module_param_named(ips, rtl88ee_mod_params.inactiveps, bool, 0444); 373 module_param_named(swlps, rtl88ee_mod_params.swctrl_lps, bool, 0444); 374 module_param_named(fwlps, rtl88ee_mod_params.fwctrl_lps, bool, 0444); 375 module_param_named(msi, rtl88ee_mod_params.msi_support, bool, 0444); 376 module_param_named(aspm, rtl88ee_mod_params.aspm_support, int, 0444); 377 module_param_named(disable_watchdog, rtl88ee_mod_params.disable_watchdog, 378 bool, 0444); 379 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n"); 380 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n"); 381 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n"); 382 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n"); 383 MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n"); 384 MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n"); 385 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)"); 386 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)"); 387 MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n"); 388 389 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume); 390 391 static struct pci_driver rtl88ee_driver = { 392 .name = KBUILD_MODNAME, 393 .id_table = rtl88ee_pci_ids, 394 .probe = rtl_pci_probe, 395 .remove = rtl_pci_disconnect, 396 .driver.pm = &rtlwifi_pm_ops, 397 }; 398 399 module_pci_driver(rtl88ee_driver); 400