1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2013 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../core.h" 28 #include "../pci.h" 29 #include "reg.h" 30 #include "def.h" 31 #include "phy.h" 32 #include "dm.h" 33 #include "hw.h" 34 #include "sw.h" 35 #include "trx.h" 36 #include "led.h" 37 #include "table.h" 38 39 #include <linux/vmalloc.h> 40 #include <linux/module.h> 41 42 static void rtl88e_init_aspm_vars(struct ieee80211_hw *hw) 43 { 44 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 45 46 /*close ASPM for AMD defaultly */ 47 rtlpci->const_amdpci_aspm = 0; 48 49 /* ASPM PS mode. 50 * 0 - Disable ASPM, 51 * 1 - Enable ASPM without Clock Req, 52 * 2 - Enable ASPM with Clock Req, 53 * 3 - Alwyas Enable ASPM with Clock Req, 54 * 4 - Always Enable ASPM without Clock Req. 55 * set defult to RTL8192CE:3 RTL8192E:2 56 */ 57 rtlpci->const_pci_aspm = 3; 58 59 /*Setting for PCI-E device */ 60 rtlpci->const_devicepci_aspm_setting = 0x03; 61 62 /*Setting for PCI-E bridge */ 63 rtlpci->const_hostpci_aspm_setting = 0x02; 64 65 /* In Hw/Sw Radio Off situation. 66 * 0 - Default, 67 * 1 - From ASPM setting without low Mac Pwr, 68 * 2 - From ASPM setting with low Mac Pwr, 69 * 3 - Bus D3 70 * set default to RTL8192CE:0 RTL8192SE:2 71 */ 72 rtlpci->const_hwsw_rfoff_d3 = 0; 73 74 /* This setting works for those device with 75 * backdoor ASPM setting such as EPHY setting. 76 * 0 - Not support ASPM, 77 * 1 - Support ASPM, 78 * 2 - According to chipset. 79 */ 80 rtlpci->const_support_pciaspm = 1; 81 } 82 83 int rtl88e_init_sw_vars(struct ieee80211_hw *hw) 84 { 85 int err = 0; 86 struct rtl_priv *rtlpriv = rtl_priv(hw); 87 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 88 u8 tid; 89 char *fw_name; 90 91 rtl8188ee_bt_reg_init(hw); 92 rtlpriv->dm.dm_initialgain_enable = 1; 93 rtlpriv->dm.dm_flag = 0; 94 rtlpriv->dm.disable_framebursting = 0; 95 rtlpriv->dm.thermalvalue = 0; 96 rtlpci->transmit_config = CFENDFORM | BIT(15); 97 98 /* compatible 5G band 88ce just 2.4G band & smsp */ 99 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G; 100 rtlpriv->rtlhal.bandset = BAND_ON_2_4G; 101 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY; 102 103 rtlpci->receive_config = (RCR_APPFCS | 104 RCR_APP_MIC | 105 RCR_APP_ICV | 106 RCR_APP_PHYST_RXFF | 107 RCR_HTC_LOC_CTRL | 108 RCR_AMF | 109 RCR_ACF | 110 RCR_ADF | 111 RCR_AICV | 112 RCR_ACRC32 | 113 RCR_AB | 114 RCR_AM | 115 RCR_APM | 116 0); 117 118 rtlpci->irq_mask[0] = 119 (u32)(IMR_PSTIMEOUT | 120 IMR_HSISR_IND_ON_INT | 121 IMR_C2HCMD | 122 IMR_HIGHDOK | 123 IMR_MGNTDOK | 124 IMR_BKDOK | 125 IMR_BEDOK | 126 IMR_VIDOK | 127 IMR_VODOK | 128 IMR_RDU | 129 IMR_ROK | 130 0); 131 rtlpci->irq_mask[1] = (u32) (IMR_RXFOVW | 0); 132 rtlpci->sys_irq_mask = (u32) (HSIMR_PDN_INT_EN | HSIMR_RON_INT_EN); 133 134 /* for LPS & IPS */ 135 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; 136 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; 137 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; 138 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support; 139 rtlpriv->cfg->mod_params->sw_crypto = 140 rtlpriv->cfg->mod_params->sw_crypto; 141 rtlpriv->cfg->mod_params->disable_watchdog = 142 rtlpriv->cfg->mod_params->disable_watchdog; 143 if (rtlpriv->cfg->mod_params->disable_watchdog) 144 pr_info("watchdog disabled\n"); 145 if (!rtlpriv->psc.inactiveps) 146 pr_info("rtl8188ee: Power Save off (module option)\n"); 147 if (!rtlpriv->psc.fwctrl_lps) 148 pr_info("rtl8188ee: FW Power Save off (module option)\n"); 149 rtlpriv->psc.reg_fwctrl_lps = 3; 150 rtlpriv->psc.reg_max_lps_awakeintvl = 5; 151 /* for ASPM, you can close aspm through 152 * set const_support_pciaspm = 0 153 */ 154 rtl88e_init_aspm_vars(hw); 155 156 if (rtlpriv->psc.reg_fwctrl_lps == 1) 157 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE; 158 else if (rtlpriv->psc.reg_fwctrl_lps == 2) 159 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE; 160 else if (rtlpriv->psc.reg_fwctrl_lps == 3) 161 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE; 162 163 /* for firmware buf */ 164 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000); 165 if (!rtlpriv->rtlhal.pfirmware) { 166 pr_info("Can't alloc buffer for fw.\n"); 167 return 1; 168 } 169 170 fw_name = "rtlwifi/rtl8188efw.bin"; 171 rtlpriv->max_fw_size = 0x8000; 172 pr_info("Using firmware %s\n", fw_name); 173 err = request_firmware_nowait(THIS_MODULE, 1, fw_name, 174 rtlpriv->io.dev, GFP_KERNEL, hw, 175 rtl_fw_cb); 176 if (err) { 177 pr_info("Failed to request firmware!\n"); 178 vfree(rtlpriv->rtlhal.pfirmware); 179 rtlpriv->rtlhal.pfirmware = NULL; 180 return 1; 181 } 182 183 /* for early mode */ 184 rtlpriv->rtlhal.earlymode_enable = false; 185 rtlpriv->rtlhal.max_earlymode_num = 10; 186 for (tid = 0; tid < 8; tid++) 187 skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]); 188 189 /*low power */ 190 rtlpriv->psc.low_power_enable = false; 191 if (rtlpriv->psc.low_power_enable) { 192 init_timer(&rtlpriv->works.fw_clockoff_timer); 193 setup_timer(&rtlpriv->works.fw_clockoff_timer, 194 rtl88ee_fw_clk_off_timer_callback, 195 (unsigned long)hw); 196 } 197 198 init_timer(&rtlpriv->works.fast_antenna_training_timer); 199 setup_timer(&rtlpriv->works.fast_antenna_training_timer, 200 rtl88e_dm_fast_antenna_training_callback, 201 (unsigned long)hw); 202 return err; 203 } 204 205 void rtl88e_deinit_sw_vars(struct ieee80211_hw *hw) 206 { 207 struct rtl_priv *rtlpriv = rtl_priv(hw); 208 209 if (rtlpriv->rtlhal.pfirmware) { 210 vfree(rtlpriv->rtlhal.pfirmware); 211 rtlpriv->rtlhal.pfirmware = NULL; 212 } 213 214 if (rtlpriv->psc.low_power_enable) 215 del_timer_sync(&rtlpriv->works.fw_clockoff_timer); 216 217 del_timer_sync(&rtlpriv->works.fast_antenna_training_timer); 218 } 219 220 /* get bt coexist status */ 221 bool rtl88e_get_btc_status(void) 222 { 223 return false; 224 } 225 226 static struct rtl_hal_ops rtl8188ee_hal_ops = { 227 .init_sw_vars = rtl88e_init_sw_vars, 228 .deinit_sw_vars = rtl88e_deinit_sw_vars, 229 .read_eeprom_info = rtl88ee_read_eeprom_info, 230 .interrupt_recognized = rtl88ee_interrupt_recognized,/*need check*/ 231 .hw_init = rtl88ee_hw_init, 232 .hw_disable = rtl88ee_card_disable, 233 .hw_suspend = rtl88ee_suspend, 234 .hw_resume = rtl88ee_resume, 235 .enable_interrupt = rtl88ee_enable_interrupt, 236 .disable_interrupt = rtl88ee_disable_interrupt, 237 .set_network_type = rtl88ee_set_network_type, 238 .set_chk_bssid = rtl88ee_set_check_bssid, 239 .set_qos = rtl88ee_set_qos, 240 .set_bcn_reg = rtl88ee_set_beacon_related_registers, 241 .set_bcn_intv = rtl88ee_set_beacon_interval, 242 .update_interrupt_mask = rtl88ee_update_interrupt_mask, 243 .get_hw_reg = rtl88ee_get_hw_reg, 244 .set_hw_reg = rtl88ee_set_hw_reg, 245 .update_rate_tbl = rtl88ee_update_hal_rate_tbl, 246 .fill_tx_desc = rtl88ee_tx_fill_desc, 247 .fill_tx_cmddesc = rtl88ee_tx_fill_cmddesc, 248 .query_rx_desc = rtl88ee_rx_query_desc, 249 .set_channel_access = rtl88ee_update_channel_access_setting, 250 .radio_onoff_checking = rtl88ee_gpio_radio_on_off_checking, 251 .set_bw_mode = rtl88e_phy_set_bw_mode, 252 .switch_channel = rtl88e_phy_sw_chnl, 253 .dm_watchdog = rtl88e_dm_watchdog, 254 .scan_operation_backup = rtl88e_phy_scan_operation_backup, 255 .set_rf_power_state = rtl88e_phy_set_rf_power_state, 256 .led_control = rtl88ee_led_control, 257 .set_desc = rtl88ee_set_desc, 258 .get_desc = rtl88ee_get_desc, 259 .is_tx_desc_closed = rtl88ee_is_tx_desc_closed, 260 .tx_polling = rtl88ee_tx_polling, 261 .enable_hw_sec = rtl88ee_enable_hw_security_config, 262 .set_key = rtl88ee_set_key, 263 .init_sw_leds = rtl88ee_init_sw_leds, 264 .get_bbreg = rtl88e_phy_query_bb_reg, 265 .set_bbreg = rtl88e_phy_set_bb_reg, 266 .get_rfreg = rtl88e_phy_query_rf_reg, 267 .set_rfreg = rtl88e_phy_set_rf_reg, 268 .get_btc_status = rtl88e_get_btc_status, 269 .rx_command_packet = rtl88ee_rx_command_packet, 270 271 }; 272 273 static struct rtl_mod_params rtl88ee_mod_params = { 274 .sw_crypto = false, 275 .inactiveps = true, 276 .swctrl_lps = false, 277 .fwctrl_lps = false, 278 .msi_support = true, 279 .debug_level = 0, 280 .debug_mask = 0, 281 }; 282 283 static const struct rtl_hal_cfg rtl88ee_hal_cfg = { 284 .bar_id = 2, 285 .write_readback = true, 286 .name = "rtl88e_pci", 287 .ops = &rtl8188ee_hal_ops, 288 .mod_params = &rtl88ee_mod_params, 289 290 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, 291 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, 292 .maps[SYS_CLK] = REG_SYS_CLKR, 293 .maps[MAC_RCR_AM] = AM, 294 .maps[MAC_RCR_AB] = AB, 295 .maps[MAC_RCR_ACRC32] = ACRC32, 296 .maps[MAC_RCR_ACF] = ACF, 297 .maps[MAC_RCR_AAP] = AAP, 298 .maps[MAC_HIMR] = REG_HIMR, 299 .maps[MAC_HIMRE] = REG_HIMRE, 300 .maps[MAC_HSISR] = REG_HSISR, 301 302 .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS, 303 304 .maps[EFUSE_TEST] = REG_EFUSE_TEST, 305 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, 306 .maps[EFUSE_CLK] = 0, 307 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, 308 .maps[EFUSE_PWC_EV12V] = PWC_EV12V, 309 .maps[EFUSE_FEN_ELDR] = FEN_ELDR, 310 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN, 311 .maps[EFUSE_ANA8M] = ANA8M, 312 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE, 313 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION, 314 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN, 315 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES, 316 317 .maps[RWCAM] = REG_CAMCMD, 318 .maps[WCAMI] = REG_CAMWRITE, 319 .maps[RCAMO] = REG_CAMREAD, 320 .maps[CAMDBG] = REG_CAMDBG, 321 .maps[SECR] = REG_SECCFG, 322 .maps[SEC_CAM_NONE] = CAM_NONE, 323 .maps[SEC_CAM_WEP40] = CAM_WEP40, 324 .maps[SEC_CAM_TKIP] = CAM_TKIP, 325 .maps[SEC_CAM_AES] = CAM_AES, 326 .maps[SEC_CAM_WEP104] = CAM_WEP104, 327 328 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, 329 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, 330 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, 331 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, 332 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, 333 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, 334 /* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, */ /*need check*/ 335 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, 336 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, 337 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, 338 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, 339 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, 340 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, 341 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, 342 /* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/ 343 /* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/ 344 345 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, 346 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, 347 .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0, 348 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW, 349 .maps[RTL_IMR_RDU] = IMR_RDU, 350 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND, 351 .maps[RTL_IMR_BDOK] = IMR_BCNDOK0, 352 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK, 353 .maps[RTL_IMR_TBDER] = IMR_TBDER, 354 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK, 355 .maps[RTL_IMR_TBDOK] = IMR_TBDOK, 356 .maps[RTL_IMR_BKDOK] = IMR_BKDOK, 357 .maps[RTL_IMR_BEDOK] = IMR_BEDOK, 358 .maps[RTL_IMR_VIDOK] = IMR_VIDOK, 359 .maps[RTL_IMR_VODOK] = IMR_VODOK, 360 .maps[RTL_IMR_ROK] = IMR_ROK, 361 .maps[RTL_IMR_HSISR_IND] = IMR_HSISR_IND_ON_INT, 362 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER), 363 364 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M, 365 .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M, 366 .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M, 367 .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M, 368 .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M, 369 .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M, 370 .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M, 371 .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M, 372 .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M, 373 .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M, 374 .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M, 375 .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M, 376 377 .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7, 378 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15, 379 }; 380 381 static const struct pci_device_id rtl88ee_pci_ids[] = { 382 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8179, rtl88ee_hal_cfg)}, 383 {}, 384 }; 385 386 MODULE_DEVICE_TABLE(pci, rtl88ee_pci_ids); 387 388 MODULE_AUTHOR("zhiyuan_yang <zhiyuan_yang@realsil.com.cn>"); 389 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 390 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>"); 391 MODULE_LICENSE("GPL"); 392 MODULE_DESCRIPTION("Realtek 8188E 802.11n PCI wireless"); 393 MODULE_FIRMWARE("rtlwifi/rtl8188efw.bin"); 394 395 module_param_named(swenc, rtl88ee_mod_params.sw_crypto, bool, 0444); 396 module_param_named(debug_level, rtl88ee_mod_params.debug_level, int, 0644); 397 module_param_named(debug_mask, rtl88ee_mod_params.debug_mask, ullong, 0644); 398 module_param_named(ips, rtl88ee_mod_params.inactiveps, bool, 0444); 399 module_param_named(swlps, rtl88ee_mod_params.swctrl_lps, bool, 0444); 400 module_param_named(fwlps, rtl88ee_mod_params.fwctrl_lps, bool, 0444); 401 module_param_named(msi, rtl88ee_mod_params.msi_support, bool, 0444); 402 module_param_named(disable_watchdog, rtl88ee_mod_params.disable_watchdog, 403 bool, 0444); 404 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n"); 405 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n"); 406 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n"); 407 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n"); 408 MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n"); 409 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)"); 410 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)"); 411 MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n"); 412 413 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume); 414 415 static struct pci_driver rtl88ee_driver = { 416 .name = KBUILD_MODNAME, 417 .id_table = rtl88ee_pci_ids, 418 .probe = rtl_pci_probe, 419 .remove = rtl_pci_disconnect, 420 .driver.pm = &rtlwifi_pm_ops, 421 }; 422 423 module_pci_driver(rtl88ee_driver); 424