1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2013  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../core.h"
6 #include "../pci.h"
7 #include "reg.h"
8 #include "def.h"
9 #include "phy.h"
10 #include "dm.h"
11 #include "hw.h"
12 #include "trx.h"
13 #include "led.h"
14 #include "table.h"
15 
16 #include <linux/vmalloc.h>
17 #include <linux/module.h>
18 
19 static void rtl88e_init_aspm_vars(struct ieee80211_hw *hw)
20 {
21 	struct rtl_priv *rtlpriv = rtl_priv(hw);
22 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
23 
24 	/*close ASPM for AMD defaultly */
25 	rtlpci->const_amdpci_aspm = 0;
26 
27 	/* ASPM PS mode.
28 	 * 0 - Disable ASPM,
29 	 * 1 - Enable ASPM without Clock Req,
30 	 * 2 - Enable ASPM with Clock Req,
31 	 * 3 - Alwyas Enable ASPM with Clock Req,
32 	 * 4 - Always Enable ASPM without Clock Req.
33 	 * set defult to RTL8192CE:3 RTL8192E:2
34 	 */
35 	rtlpci->const_pci_aspm = 3;
36 
37 	/*Setting for PCI-E device */
38 	rtlpci->const_devicepci_aspm_setting = 0x03;
39 
40 	/*Setting for PCI-E bridge */
41 	rtlpci->const_hostpci_aspm_setting = 0x02;
42 
43 	/* In Hw/Sw Radio Off situation.
44 	 * 0 - Default,
45 	 * 1 - From ASPM setting without low Mac Pwr,
46 	 * 2 - From ASPM setting with low Mac Pwr,
47 	 * 3 - Bus D3
48 	 * set default to RTL8192CE:0 RTL8192SE:2
49 	 */
50 	rtlpci->const_hwsw_rfoff_d3 = 0;
51 
52 	/* This setting works for those device with
53 	 * backdoor ASPM setting such as EPHY setting.
54 	 * 0 - Not support ASPM,
55 	 * 1 - Support ASPM,
56 	 * 2 - According to chipset.
57 	 */
58 	rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
59 }
60 
61 static int rtl88e_init_sw_vars(struct ieee80211_hw *hw)
62 {
63 	int err = 0;
64 	struct rtl_priv *rtlpriv = rtl_priv(hw);
65 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
66 	u8 tid;
67 	char *fw_name;
68 
69 	rtl8188ee_bt_reg_init(hw);
70 	rtlpriv->dm.dm_initialgain_enable = true;
71 	rtlpriv->dm.dm_flag = 0;
72 	rtlpriv->dm.disable_framebursting = false;
73 	rtlpriv->dm.thermalvalue = 0;
74 	rtlpci->transmit_config = CFENDFORM | BIT(15);
75 
76 	/* compatible 5G band 88ce just 2.4G band & smsp */
77 	rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
78 	rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
79 	rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
80 
81 	rtlpci->receive_config = (RCR_APPFCS |
82 				  RCR_APP_MIC |
83 				  RCR_APP_ICV |
84 				  RCR_APP_PHYST_RXFF |
85 				  RCR_HTC_LOC_CTRL |
86 				  RCR_AMF |
87 				  RCR_ACF |
88 				  RCR_ADF |
89 				  RCR_AICV |
90 				  RCR_ACRC32 |
91 				  RCR_AB |
92 				  RCR_AM |
93 				  RCR_APM |
94 				  0);
95 
96 	rtlpci->irq_mask[0] =
97 				(u32)(IMR_PSTIMEOUT	|
98 				IMR_HSISR_IND_ON_INT	|
99 				IMR_C2HCMD		|
100 				IMR_HIGHDOK		|
101 				IMR_MGNTDOK		|
102 				IMR_BKDOK		|
103 				IMR_BEDOK		|
104 				IMR_VIDOK		|
105 				IMR_VODOK		|
106 				IMR_RDU			|
107 				IMR_ROK			|
108 				0);
109 	rtlpci->irq_mask[1] = (u32) (IMR_RXFOVW | 0);
110 	rtlpci->sys_irq_mask = (u32) (HSIMR_PDN_INT_EN | HSIMR_RON_INT_EN);
111 
112 	/* for LPS & IPS */
113 	rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
114 	rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
115 	rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
116 	rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
117 	if (rtlpriv->cfg->mod_params->disable_watchdog)
118 		pr_info("watchdog disabled\n");
119 	if (!rtlpriv->psc.inactiveps)
120 		pr_info("rtl8188ee: Power Save off (module option)\n");
121 	if (!rtlpriv->psc.fwctrl_lps)
122 		pr_info("rtl8188ee: FW Power Save off (module option)\n");
123 	rtlpriv->psc.reg_fwctrl_lps = 3;
124 	rtlpriv->psc.reg_max_lps_awakeintvl = 5;
125 	/* for ASPM, you can close aspm through
126 	 * set const_support_pciaspm = 0
127 	 */
128 	rtl88e_init_aspm_vars(hw);
129 
130 	if (rtlpriv->psc.reg_fwctrl_lps == 1)
131 		rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
132 	else if (rtlpriv->psc.reg_fwctrl_lps == 2)
133 		rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
134 	else if (rtlpriv->psc.reg_fwctrl_lps == 3)
135 		rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
136 
137 	/* for firmware buf */
138 	rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
139 	if (!rtlpriv->rtlhal.pfirmware) {
140 		pr_info("Can't alloc buffer for fw.\n");
141 		return 1;
142 	}
143 
144 	fw_name = "rtlwifi/rtl8188efw.bin";
145 	rtlpriv->max_fw_size = 0x8000;
146 	pr_info("Using firmware %s\n", fw_name);
147 	err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
148 				      rtlpriv->io.dev, GFP_KERNEL, hw,
149 				      rtl_fw_cb);
150 	if (err) {
151 		pr_info("Failed to request firmware!\n");
152 		vfree(rtlpriv->rtlhal.pfirmware);
153 		rtlpriv->rtlhal.pfirmware = NULL;
154 		return 1;
155 	}
156 
157 	/* for early mode */
158 	rtlpriv->rtlhal.earlymode_enable = false;
159 	rtlpriv->rtlhal.max_earlymode_num = 10;
160 	for (tid = 0; tid < 8; tid++)
161 		skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
162 
163 	/*low power */
164 	rtlpriv->psc.low_power_enable = false;
165 	if (rtlpriv->psc.low_power_enable) {
166 		timer_setup(&rtlpriv->works.fw_clockoff_timer,
167 			    rtl88ee_fw_clk_off_timer_callback, 0);
168 	}
169 
170 	timer_setup(&rtlpriv->works.fast_antenna_training_timer,
171 		    rtl88e_dm_fast_antenna_training_callback, 0);
172 	return err;
173 }
174 
175 static void rtl88e_deinit_sw_vars(struct ieee80211_hw *hw)
176 {
177 	struct rtl_priv *rtlpriv = rtl_priv(hw);
178 
179 	if (rtlpriv->rtlhal.pfirmware) {
180 		vfree(rtlpriv->rtlhal.pfirmware);
181 		rtlpriv->rtlhal.pfirmware = NULL;
182 	}
183 
184 	if (rtlpriv->psc.low_power_enable)
185 		del_timer_sync(&rtlpriv->works.fw_clockoff_timer);
186 
187 	del_timer_sync(&rtlpriv->works.fast_antenna_training_timer);
188 }
189 
190 /* get bt coexist status */
191 static bool rtl88e_get_btc_status(void)
192 {
193 	return false;
194 }
195 
196 static struct rtl_hal_ops rtl8188ee_hal_ops = {
197 	.init_sw_vars = rtl88e_init_sw_vars,
198 	.deinit_sw_vars = rtl88e_deinit_sw_vars,
199 	.read_eeprom_info = rtl88ee_read_eeprom_info,
200 	.interrupt_recognized = rtl88ee_interrupt_recognized,/*need check*/
201 	.hw_init = rtl88ee_hw_init,
202 	.hw_disable = rtl88ee_card_disable,
203 	.hw_suspend = rtl88ee_suspend,
204 	.hw_resume = rtl88ee_resume,
205 	.enable_interrupt = rtl88ee_enable_interrupt,
206 	.disable_interrupt = rtl88ee_disable_interrupt,
207 	.set_network_type = rtl88ee_set_network_type,
208 	.set_chk_bssid = rtl88ee_set_check_bssid,
209 	.set_qos = rtl88ee_set_qos,
210 	.set_bcn_reg = rtl88ee_set_beacon_related_registers,
211 	.set_bcn_intv = rtl88ee_set_beacon_interval,
212 	.update_interrupt_mask = rtl88ee_update_interrupt_mask,
213 	.get_hw_reg = rtl88ee_get_hw_reg,
214 	.set_hw_reg = rtl88ee_set_hw_reg,
215 	.update_rate_tbl = rtl88ee_update_hal_rate_tbl,
216 	.fill_tx_desc = rtl88ee_tx_fill_desc,
217 	.fill_tx_cmddesc = rtl88ee_tx_fill_cmddesc,
218 	.query_rx_desc = rtl88ee_rx_query_desc,
219 	.set_channel_access = rtl88ee_update_channel_access_setting,
220 	.radio_onoff_checking = rtl88ee_gpio_radio_on_off_checking,
221 	.set_bw_mode = rtl88e_phy_set_bw_mode,
222 	.switch_channel = rtl88e_phy_sw_chnl,
223 	.dm_watchdog = rtl88e_dm_watchdog,
224 	.scan_operation_backup = rtl88e_phy_scan_operation_backup,
225 	.set_rf_power_state = rtl88e_phy_set_rf_power_state,
226 	.led_control = rtl88ee_led_control,
227 	.set_desc = rtl88ee_set_desc,
228 	.get_desc = rtl88ee_get_desc,
229 	.is_tx_desc_closed = rtl88ee_is_tx_desc_closed,
230 	.tx_polling = rtl88ee_tx_polling,
231 	.enable_hw_sec = rtl88ee_enable_hw_security_config,
232 	.set_key = rtl88ee_set_key,
233 	.get_bbreg = rtl88e_phy_query_bb_reg,
234 	.set_bbreg = rtl88e_phy_set_bb_reg,
235 	.get_rfreg = rtl88e_phy_query_rf_reg,
236 	.set_rfreg = rtl88e_phy_set_rf_reg,
237 	.get_btc_status = rtl88e_get_btc_status,
238 };
239 
240 static struct rtl_mod_params rtl88ee_mod_params = {
241 	.sw_crypto = false,
242 	.inactiveps = true,
243 	.swctrl_lps = false,
244 	.fwctrl_lps = false,
245 	.msi_support = true,
246 	.aspm_support = 1,
247 	.debug_level = 0,
248 	.debug_mask = 0,
249 };
250 
251 static const struct rtl_hal_cfg rtl88ee_hal_cfg = {
252 	.bar_id = 2,
253 	.write_readback = true,
254 	.name = "rtl88e_pci",
255 	.ops = &rtl8188ee_hal_ops,
256 	.mod_params = &rtl88ee_mod_params,
257 
258 	.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
259 	.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
260 	.maps[SYS_CLK] = REG_SYS_CLKR,
261 	.maps[MAC_RCR_AM] = AM,
262 	.maps[MAC_RCR_AB] = AB,
263 	.maps[MAC_RCR_ACRC32] = ACRC32,
264 	.maps[MAC_RCR_ACF] = ACF,
265 	.maps[MAC_RCR_AAP] = AAP,
266 	.maps[MAC_HIMR] = REG_HIMR,
267 	.maps[MAC_HIMRE] = REG_HIMRE,
268 	.maps[MAC_HSISR] = REG_HSISR,
269 
270 	.maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
271 
272 	.maps[EFUSE_TEST] = REG_EFUSE_TEST,
273 	.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
274 	.maps[EFUSE_CLK] = 0,
275 	.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
276 	.maps[EFUSE_PWC_EV12V] = PWC_EV12V,
277 	.maps[EFUSE_FEN_ELDR] = FEN_ELDR,
278 	.maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
279 	.maps[EFUSE_ANA8M] = ANA8M,
280 	.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
281 	.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
282 	.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
283 	.maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
284 
285 	.maps[RWCAM] = REG_CAMCMD,
286 	.maps[WCAMI] = REG_CAMWRITE,
287 	.maps[RCAMO] = REG_CAMREAD,
288 	.maps[CAMDBG] = REG_CAMDBG,
289 	.maps[SECR] = REG_SECCFG,
290 	.maps[SEC_CAM_NONE] = CAM_NONE,
291 	.maps[SEC_CAM_WEP40] = CAM_WEP40,
292 	.maps[SEC_CAM_TKIP] = CAM_TKIP,
293 	.maps[SEC_CAM_AES] = CAM_AES,
294 	.maps[SEC_CAM_WEP104] = CAM_WEP104,
295 
296 	.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
297 	.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
298 	.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
299 	.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
300 	.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
301 	.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
302 /*	.maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,     */   /*need check*/
303 	.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
304 	.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
305 	.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
306 	.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
307 	.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
308 	.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
309 	.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
310 /*	.maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
311 /*	.maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
312 
313 	.maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
314 	.maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
315 	.maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
316 	.maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
317 	.maps[RTL_IMR_RDU] = IMR_RDU,
318 	.maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
319 	.maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
320 	.maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
321 	.maps[RTL_IMR_TBDER] = IMR_TBDER,
322 	.maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
323 	.maps[RTL_IMR_TBDOK] = IMR_TBDOK,
324 	.maps[RTL_IMR_BKDOK] = IMR_BKDOK,
325 	.maps[RTL_IMR_BEDOK] = IMR_BEDOK,
326 	.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
327 	.maps[RTL_IMR_VODOK] = IMR_VODOK,
328 	.maps[RTL_IMR_ROK] = IMR_ROK,
329 	.maps[RTL_IMR_HSISR_IND] = IMR_HSISR_IND_ON_INT,
330 	.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
331 
332 	.maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
333 	.maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
334 	.maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
335 	.maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
336 	.maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
337 	.maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
338 	.maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
339 	.maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
340 	.maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
341 	.maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
342 	.maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
343 	.maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
344 
345 	.maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
346 	.maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
347 };
348 
349 static const struct pci_device_id rtl88ee_pci_ids[] = {
350 	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8179, rtl88ee_hal_cfg)},
351 	{},
352 };
353 
354 MODULE_DEVICE_TABLE(pci, rtl88ee_pci_ids);
355 
356 MODULE_AUTHOR("zhiyuan_yang	<zhiyuan_yang@realsil.com.cn>");
357 MODULE_AUTHOR("Realtek WlanFAE	<wlanfae@realtek.com>");
358 MODULE_AUTHOR("Larry Finger	<Larry.Finger@lwfinger.net>");
359 MODULE_LICENSE("GPL");
360 MODULE_DESCRIPTION("Realtek 8188E 802.11n PCI wireless");
361 MODULE_FIRMWARE("rtlwifi/rtl8188efw.bin");
362 
363 module_param_named(swenc, rtl88ee_mod_params.sw_crypto, bool, 0444);
364 module_param_named(debug_level, rtl88ee_mod_params.debug_level, int, 0644);
365 module_param_named(debug_mask, rtl88ee_mod_params.debug_mask, ullong, 0644);
366 module_param_named(ips, rtl88ee_mod_params.inactiveps, bool, 0444);
367 module_param_named(swlps, rtl88ee_mod_params.swctrl_lps, bool, 0444);
368 module_param_named(fwlps, rtl88ee_mod_params.fwctrl_lps, bool, 0444);
369 module_param_named(msi, rtl88ee_mod_params.msi_support, bool, 0444);
370 module_param_named(aspm, rtl88ee_mod_params.aspm_support, int, 0444);
371 module_param_named(disable_watchdog, rtl88ee_mod_params.disable_watchdog,
372 		   bool, 0444);
373 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
374 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
375 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
376 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
377 MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
378 MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
379 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
380 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
381 MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
382 
383 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
384 
385 static struct pci_driver rtl88ee_driver = {
386 	.name = KBUILD_MODNAME,
387 	.id_table = rtl88ee_pci_ids,
388 	.probe = rtl_pci_probe,
389 	.remove = rtl_pci_disconnect,
390 	.driver.pm = &rtlwifi_pm_ops,
391 };
392 
393 module_pci_driver(rtl88ee_driver);
394