1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2013 Realtek Corporation.*/ 3 4 #include "../wifi.h" 5 #include "../pci.h" 6 #include "../ps.h" 7 #include "reg.h" 8 #include "def.h" 9 #include "phy.h" 10 #include "rf.h" 11 #include "dm.h" 12 #include "table.h" 13 14 static u32 _rtl88e_phy_rf_serial_read(struct ieee80211_hw *hw, 15 enum radio_path rfpath, u32 offset); 16 static void _rtl88e_phy_rf_serial_write(struct ieee80211_hw *hw, 17 enum radio_path rfpath, u32 offset, 18 u32 data); 19 static u32 _rtl88e_phy_calculate_bit_shift(u32 bitmask); 20 static bool _rtl88e_phy_bb8188e_config_parafile(struct ieee80211_hw *hw); 21 static bool _rtl88e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw); 22 static bool phy_config_bb_with_headerfile(struct ieee80211_hw *hw, 23 u8 configtype); 24 static bool phy_config_bb_with_pghdr(struct ieee80211_hw *hw, 25 u8 configtype); 26 static void _rtl88e_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw); 27 static bool _rtl88e_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, 28 u32 cmdtableidx, u32 cmdtablesz, 29 enum swchnlcmd_id cmdid, u32 para1, 30 u32 para2, u32 msdelay); 31 static bool _rtl88e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, 32 u8 channel, u8 *stage, u8 *step, 33 u32 *delay); 34 35 static long _rtl88e_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, 36 enum wireless_mode wirelessmode, 37 u8 txpwridx); 38 static void rtl88ee_phy_set_rf_on(struct ieee80211_hw *hw); 39 static void rtl88e_phy_set_io(struct ieee80211_hw *hw); 40 41 u32 rtl88e_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) 42 { 43 struct rtl_priv *rtlpriv = rtl_priv(hw); 44 u32 returnvalue, originalvalue, bitshift; 45 46 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 47 "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask); 48 originalvalue = rtl_read_dword(rtlpriv, regaddr); 49 bitshift = _rtl88e_phy_calculate_bit_shift(bitmask); 50 returnvalue = (originalvalue & bitmask) >> bitshift; 51 52 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 53 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask, 54 regaddr, originalvalue); 55 56 return returnvalue; 57 58 } 59 60 void rtl88e_phy_set_bb_reg(struct ieee80211_hw *hw, 61 u32 regaddr, u32 bitmask, u32 data) 62 { 63 struct rtl_priv *rtlpriv = rtl_priv(hw); 64 u32 originalvalue, bitshift; 65 66 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 67 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 68 regaddr, bitmask, data); 69 70 if (bitmask != MASKDWORD) { 71 originalvalue = rtl_read_dword(rtlpriv, regaddr); 72 bitshift = _rtl88e_phy_calculate_bit_shift(bitmask); 73 data = ((originalvalue & (~bitmask)) | (data << bitshift)); 74 } 75 76 rtl_write_dword(rtlpriv, regaddr, data); 77 78 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 79 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 80 regaddr, bitmask, data); 81 } 82 83 u32 rtl88e_phy_query_rf_reg(struct ieee80211_hw *hw, 84 enum radio_path rfpath, u32 regaddr, u32 bitmask) 85 { 86 struct rtl_priv *rtlpriv = rtl_priv(hw); 87 u32 original_value, readback_value, bitshift; 88 unsigned long flags; 89 90 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 91 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", 92 regaddr, rfpath, bitmask); 93 94 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 95 96 97 original_value = _rtl88e_phy_rf_serial_read(hw, rfpath, regaddr); 98 bitshift = _rtl88e_phy_calculate_bit_shift(bitmask); 99 readback_value = (original_value & bitmask) >> bitshift; 100 101 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 102 103 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 104 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", 105 regaddr, rfpath, bitmask, original_value); 106 return readback_value; 107 } 108 109 void rtl88e_phy_set_rf_reg(struct ieee80211_hw *hw, 110 enum radio_path rfpath, 111 u32 regaddr, u32 bitmask, u32 data) 112 { 113 struct rtl_priv *rtlpriv = rtl_priv(hw); 114 u32 original_value, bitshift; 115 unsigned long flags; 116 117 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 118 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 119 regaddr, bitmask, data, rfpath); 120 121 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 122 123 if (bitmask != RFREG_OFFSET_MASK) { 124 original_value = _rtl88e_phy_rf_serial_read(hw, 125 rfpath, 126 regaddr); 127 bitshift = _rtl88e_phy_calculate_bit_shift(bitmask); 128 data = 129 ((original_value & (~bitmask)) | 130 (data << bitshift)); 131 } 132 133 _rtl88e_phy_rf_serial_write(hw, rfpath, regaddr, data); 134 135 136 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 137 138 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 139 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 140 regaddr, bitmask, data, rfpath); 141 } 142 143 static u32 _rtl88e_phy_rf_serial_read(struct ieee80211_hw *hw, 144 enum radio_path rfpath, u32 offset) 145 { 146 struct rtl_priv *rtlpriv = rtl_priv(hw); 147 struct rtl_phy *rtlphy = &rtlpriv->phy; 148 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 149 u32 newoffset; 150 u32 tmplong, tmplong2; 151 u8 rfpi_enable = 0; 152 u32 retvalue; 153 154 offset &= 0xff; 155 newoffset = offset; 156 if (RT_CANNOT_IO(hw)) { 157 pr_err("return all one\n"); 158 return 0xFFFFFFFF; 159 } 160 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); 161 if (rfpath == RF90_PATH_A) 162 tmplong2 = tmplong; 163 else 164 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); 165 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) | 166 (newoffset << 23) | BLSSIREADEDGE; 167 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, 168 tmplong & (~BLSSIREADEDGE)); 169 mdelay(1); 170 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); 171 mdelay(2); 172 if (rfpath == RF90_PATH_A) 173 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, 174 BIT(8)); 175 else if (rfpath == RF90_PATH_B) 176 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, 177 BIT(8)); 178 if (rfpi_enable) 179 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, 180 BLSSIREADBACKDATA); 181 else 182 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, 183 BLSSIREADBACKDATA); 184 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 185 "RFR-%d Addr[0x%x]=0x%x\n", 186 rfpath, pphyreg->rf_rb, retvalue); 187 return retvalue; 188 } 189 190 static void _rtl88e_phy_rf_serial_write(struct ieee80211_hw *hw, 191 enum radio_path rfpath, u32 offset, 192 u32 data) 193 { 194 u32 data_and_addr; 195 u32 newoffset; 196 struct rtl_priv *rtlpriv = rtl_priv(hw); 197 struct rtl_phy *rtlphy = &rtlpriv->phy; 198 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 199 200 if (RT_CANNOT_IO(hw)) { 201 pr_err("stop\n"); 202 return; 203 } 204 offset &= 0xff; 205 newoffset = offset; 206 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 207 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); 208 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 209 "RFW-%d Addr[0x%x]=0x%x\n", 210 rfpath, pphyreg->rf3wire_offset, data_and_addr); 211 } 212 213 static u32 _rtl88e_phy_calculate_bit_shift(u32 bitmask) 214 { 215 u32 i; 216 217 for (i = 0; i <= 31; i++) { 218 if (((bitmask >> i) & 0x1) == 1) 219 break; 220 } 221 return i; 222 } 223 224 bool rtl88e_phy_mac_config(struct ieee80211_hw *hw) 225 { 226 struct rtl_priv *rtlpriv = rtl_priv(hw); 227 bool rtstatus = _rtl88e_phy_config_mac_with_headerfile(hw); 228 229 rtl_write_byte(rtlpriv, 0x04CA, 0x0B); 230 return rtstatus; 231 } 232 233 bool rtl88e_phy_bb_config(struct ieee80211_hw *hw) 234 { 235 bool rtstatus = true; 236 struct rtl_priv *rtlpriv = rtl_priv(hw); 237 u16 regval; 238 u8 b_reg_hwparafile = 1; 239 u32 tmp; 240 _rtl88e_phy_init_bb_rf_register_definition(hw); 241 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 242 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, 243 regval | BIT(13) | BIT(0) | BIT(1)); 244 245 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB); 246 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 247 FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE | 248 FEN_BB_GLB_RSTN | FEN_BBRSTB); 249 tmp = rtl_read_dword(rtlpriv, 0x4c); 250 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23)); 251 if (b_reg_hwparafile == 1) 252 rtstatus = _rtl88e_phy_bb8188e_config_parafile(hw); 253 return rtstatus; 254 } 255 256 bool rtl88e_phy_rf_config(struct ieee80211_hw *hw) 257 { 258 return rtl88e_phy_rf6052_config(hw); 259 } 260 261 static bool _rtl88e_check_condition(struct ieee80211_hw *hw, 262 const u32 condition) 263 { 264 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 265 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 266 u32 _board = rtlefuse->board_type; /*need efuse define*/ 267 u32 _interface = rtlhal->interface; 268 u32 _platform = 0x08;/*SupportPlatform */ 269 u32 cond = condition; 270 271 if (condition == 0xCDCDCDCD) 272 return true; 273 274 cond = condition & 0xFF; 275 if ((_board & cond) == 0 && cond != 0x1F) 276 return false; 277 278 cond = condition & 0xFF00; 279 cond = cond >> 8; 280 if ((_interface & cond) == 0 && cond != 0x07) 281 return false; 282 283 cond = condition & 0xFF0000; 284 cond = cond >> 16; 285 if ((_platform & cond) == 0 && cond != 0x0F) 286 return false; 287 return true; 288 } 289 290 static void _rtl8188e_config_rf_reg(struct ieee80211_hw *hw, u32 addr, 291 u32 data, enum radio_path rfpath, 292 u32 regaddr) 293 { 294 if (addr == 0xffe) { 295 mdelay(50); 296 } else if (addr == 0xfd) { 297 mdelay(5); 298 } else if (addr == 0xfc) { 299 mdelay(1); 300 } else if (addr == 0xfb) { 301 udelay(50); 302 } else if (addr == 0xfa) { 303 udelay(5); 304 } else if (addr == 0xf9) { 305 udelay(1); 306 } else { 307 rtl_set_rfreg(hw, rfpath, regaddr, 308 RFREG_OFFSET_MASK, 309 data); 310 udelay(1); 311 } 312 } 313 314 static void _rtl8188e_config_rf_radio_a(struct ieee80211_hw *hw, 315 u32 addr, u32 data) 316 { 317 u32 content = 0x1000; /*RF Content: radio_a_txt*/ 318 u32 maskforphyset = (u32)(content & 0xE000); 319 320 _rtl8188e_config_rf_reg(hw, addr, data, RF90_PATH_A, 321 addr | maskforphyset); 322 } 323 324 static void _rtl8188e_config_bb_reg(struct ieee80211_hw *hw, 325 u32 addr, u32 data) 326 { 327 if (addr == 0xfe) { 328 mdelay(50); 329 } else if (addr == 0xfd) { 330 mdelay(5); 331 } else if (addr == 0xfc) { 332 mdelay(1); 333 } else if (addr == 0xfb) { 334 udelay(50); 335 } else if (addr == 0xfa) { 336 udelay(5); 337 } else if (addr == 0xf9) { 338 udelay(1); 339 } else { 340 rtl_set_bbreg(hw, addr, MASKDWORD, data); 341 udelay(1); 342 } 343 } 344 345 static bool _rtl88e_phy_bb8188e_config_parafile(struct ieee80211_hw *hw) 346 { 347 struct rtl_priv *rtlpriv = rtl_priv(hw); 348 struct rtl_phy *rtlphy = &rtlpriv->phy; 349 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 350 bool rtstatus; 351 352 rtstatus = phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_PHY_REG); 353 if (!rtstatus) { 354 pr_err("Write BB Reg Fail!!\n"); 355 return false; 356 } 357 358 if (!rtlefuse->autoload_failflag) { 359 rtlphy->pwrgroup_cnt = 0; 360 rtstatus = 361 phy_config_bb_with_pghdr(hw, BASEBAND_CONFIG_PHY_REG); 362 } 363 if (!rtstatus) { 364 pr_err("BB_PG Reg Fail!!\n"); 365 return false; 366 } 367 rtstatus = 368 phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_AGC_TAB); 369 if (!rtstatus) { 370 pr_err("AGC Table Fail\n"); 371 return false; 372 } 373 rtlphy->cck_high_power = 374 (bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200)); 375 376 return true; 377 } 378 379 static bool _rtl88e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw) 380 { 381 struct rtl_priv *rtlpriv = rtl_priv(hw); 382 u32 i; 383 u32 arraylength; 384 u32 *ptrarray; 385 386 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl8188EMACPHY_Array\n"); 387 arraylength = RTL8188EEMAC_1T_ARRAYLEN; 388 ptrarray = RTL8188EEMAC_1T_ARRAY; 389 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 390 "Img:RTL8188EEMAC_1T_ARRAY LEN %d\n", arraylength); 391 for (i = 0; i < arraylength; i = i + 2) 392 rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]); 393 return true; 394 } 395 396 #define READ_NEXT_PAIR(v1, v2, i) \ 397 do { \ 398 i += 2; v1 = array_table[i]; \ 399 v2 = array_table[i+1]; \ 400 } while (0) 401 402 static void handle_branch1(struct ieee80211_hw *hw, u16 arraylen, 403 u32 *array_table) 404 { 405 u32 v1; 406 u32 v2; 407 int i; 408 409 for (i = 0; i < arraylen; i = i + 2) { 410 v1 = array_table[i]; 411 v2 = array_table[i+1]; 412 if (v1 < 0xcdcdcdcd) { 413 _rtl8188e_config_bb_reg(hw, v1, v2); 414 } else { /*This line is the start line of branch.*/ 415 /* to protect READ_NEXT_PAIR not overrun */ 416 if (i >= arraylen - 2) 417 break; 418 419 if (!_rtl88e_check_condition(hw, array_table[i])) { 420 /*Discard the following (offset, data) pairs*/ 421 READ_NEXT_PAIR(v1, v2, i); 422 while (v2 != 0xDEAD && 423 v2 != 0xCDEF && 424 v2 != 0xCDCD && i < arraylen - 2) 425 READ_NEXT_PAIR(v1, v2, i); 426 i -= 2; /* prevent from for-loop += 2*/ 427 } else { /* Configure matched pairs and skip 428 * to end of if-else. 429 */ 430 READ_NEXT_PAIR(v1, v2, i); 431 while (v2 != 0xDEAD && 432 v2 != 0xCDEF && 433 v2 != 0xCDCD && i < arraylen - 2) { 434 _rtl8188e_config_bb_reg(hw, v1, v2); 435 READ_NEXT_PAIR(v1, v2, i); 436 } 437 438 while (v2 != 0xDEAD && i < arraylen - 2) 439 READ_NEXT_PAIR(v1, v2, i); 440 } 441 } 442 } 443 } 444 445 static void handle_branch2(struct ieee80211_hw *hw, u16 arraylen, 446 u32 *array_table) 447 { 448 struct rtl_priv *rtlpriv = rtl_priv(hw); 449 u32 v1; 450 u32 v2; 451 int i; 452 453 for (i = 0; i < arraylen; i = i + 2) { 454 v1 = array_table[i]; 455 v2 = array_table[i+1]; 456 if (v1 < 0xCDCDCDCD) { 457 rtl_set_bbreg(hw, array_table[i], MASKDWORD, 458 array_table[i + 1]); 459 udelay(1); 460 continue; 461 } else { /*This line is the start line of branch.*/ 462 /* to protect READ_NEXT_PAIR not overrun */ 463 if (i >= arraylen - 2) 464 break; 465 466 if (!_rtl88e_check_condition(hw, array_table[i])) { 467 /*Discard the following (offset, data) pairs*/ 468 READ_NEXT_PAIR(v1, v2, i); 469 while (v2 != 0xDEAD && 470 v2 != 0xCDEF && 471 v2 != 0xCDCD && i < arraylen - 2) 472 READ_NEXT_PAIR(v1, v2, i); 473 i -= 2; /* prevent from for-loop += 2*/ 474 } else { /* Configure matched pairs and skip 475 * to end of if-else. 476 */ 477 READ_NEXT_PAIR(v1, v2, i); 478 while (v2 != 0xDEAD && 479 v2 != 0xCDEF && 480 v2 != 0xCDCD && i < arraylen - 2) { 481 rtl_set_bbreg(hw, array_table[i], 482 MASKDWORD, 483 array_table[i + 1]); 484 udelay(1); 485 READ_NEXT_PAIR(v1, v2, i); 486 } 487 488 while (v2 != 0xDEAD && i < arraylen - 2) 489 READ_NEXT_PAIR(v1, v2, i); 490 } 491 } 492 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 493 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n", 494 array_table[i], array_table[i + 1]); 495 } 496 } 497 498 static bool phy_config_bb_with_headerfile(struct ieee80211_hw *hw, 499 u8 configtype) 500 { 501 u32 *array_table; 502 u16 arraylen; 503 504 if (configtype == BASEBAND_CONFIG_PHY_REG) { 505 arraylen = RTL8188EEPHY_REG_1TARRAYLEN; 506 array_table = RTL8188EEPHY_REG_1TARRAY; 507 handle_branch1(hw, arraylen, array_table); 508 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { 509 arraylen = RTL8188EEAGCTAB_1TARRAYLEN; 510 array_table = RTL8188EEAGCTAB_1TARRAY; 511 handle_branch2(hw, arraylen, array_table); 512 } 513 return true; 514 } 515 516 static void store_pwrindex_rate_offset(struct ieee80211_hw *hw, 517 u32 regaddr, u32 bitmask, 518 u32 data) 519 { 520 struct rtl_priv *rtlpriv = rtl_priv(hw); 521 struct rtl_phy *rtlphy = &rtlpriv->phy; 522 int count = rtlphy->pwrgroup_cnt; 523 524 if (regaddr == RTXAGC_A_RATE18_06) { 525 rtlphy->mcs_txpwrlevel_origoffset[count][0] = data; 526 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 527 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n", 528 count, 529 rtlphy->mcs_txpwrlevel_origoffset[count][0]); 530 } 531 if (regaddr == RTXAGC_A_RATE54_24) { 532 rtlphy->mcs_txpwrlevel_origoffset[count][1] = data; 533 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 534 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n", 535 count, 536 rtlphy->mcs_txpwrlevel_origoffset[count][1]); 537 } 538 if (regaddr == RTXAGC_A_CCK1_MCS32) { 539 rtlphy->mcs_txpwrlevel_origoffset[count][6] = data; 540 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 541 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n", 542 count, 543 rtlphy->mcs_txpwrlevel_origoffset[count][6]); 544 } 545 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) { 546 rtlphy->mcs_txpwrlevel_origoffset[count][7] = data; 547 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 548 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n", 549 count, 550 rtlphy->mcs_txpwrlevel_origoffset[count][7]); 551 } 552 if (regaddr == RTXAGC_A_MCS03_MCS00) { 553 rtlphy->mcs_txpwrlevel_origoffset[count][2] = data; 554 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 555 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n", 556 count, 557 rtlphy->mcs_txpwrlevel_origoffset[count][2]); 558 } 559 if (regaddr == RTXAGC_A_MCS07_MCS04) { 560 rtlphy->mcs_txpwrlevel_origoffset[count][3] = data; 561 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 562 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n", 563 count, 564 rtlphy->mcs_txpwrlevel_origoffset[count][3]); 565 } 566 if (regaddr == RTXAGC_A_MCS11_MCS08) { 567 rtlphy->mcs_txpwrlevel_origoffset[count][4] = data; 568 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 569 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n", 570 count, 571 rtlphy->mcs_txpwrlevel_origoffset[count][4]); 572 } 573 if (regaddr == RTXAGC_A_MCS15_MCS12) { 574 rtlphy->mcs_txpwrlevel_origoffset[count][5] = data; 575 if (get_rf_type(rtlphy) == RF_1T1R) { 576 count++; 577 rtlphy->pwrgroup_cnt = count; 578 } 579 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 580 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n", 581 count, 582 rtlphy->mcs_txpwrlevel_origoffset[count][5]); 583 } 584 if (regaddr == RTXAGC_B_RATE18_06) { 585 rtlphy->mcs_txpwrlevel_origoffset[count][8] = data; 586 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 587 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n", 588 count, 589 rtlphy->mcs_txpwrlevel_origoffset[count][8]); 590 } 591 if (regaddr == RTXAGC_B_RATE54_24) { 592 rtlphy->mcs_txpwrlevel_origoffset[count][9] = data; 593 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 594 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n", 595 count, 596 rtlphy->mcs_txpwrlevel_origoffset[count][9]); 597 } 598 if (regaddr == RTXAGC_B_CCK1_55_MCS32) { 599 rtlphy->mcs_txpwrlevel_origoffset[count][14] = data; 600 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 601 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n", 602 count, 603 rtlphy->mcs_txpwrlevel_origoffset[count][14]); 604 } 605 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) { 606 rtlphy->mcs_txpwrlevel_origoffset[count][15] = data; 607 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 608 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n", 609 count, 610 rtlphy->mcs_txpwrlevel_origoffset[count][15]); 611 } 612 if (regaddr == RTXAGC_B_MCS03_MCS00) { 613 rtlphy->mcs_txpwrlevel_origoffset[count][10] = data; 614 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 615 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n", 616 count, 617 rtlphy->mcs_txpwrlevel_origoffset[count][10]); 618 } 619 if (regaddr == RTXAGC_B_MCS07_MCS04) { 620 rtlphy->mcs_txpwrlevel_origoffset[count][11] = data; 621 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 622 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n", 623 count, 624 rtlphy->mcs_txpwrlevel_origoffset[count][11]); 625 } 626 if (regaddr == RTXAGC_B_MCS11_MCS08) { 627 rtlphy->mcs_txpwrlevel_origoffset[count][12] = data; 628 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 629 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n", 630 count, 631 rtlphy->mcs_txpwrlevel_origoffset[count][12]); 632 } 633 if (regaddr == RTXAGC_B_MCS15_MCS12) { 634 rtlphy->mcs_txpwrlevel_origoffset[count][13] = data; 635 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 636 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n", 637 count, 638 rtlphy->mcs_txpwrlevel_origoffset[count][13]); 639 if (get_rf_type(rtlphy) != RF_1T1R) { 640 count++; 641 rtlphy->pwrgroup_cnt = count; 642 } 643 } 644 } 645 646 static bool phy_config_bb_with_pghdr(struct ieee80211_hw *hw, u8 configtype) 647 { 648 struct rtl_priv *rtlpriv = rtl_priv(hw); 649 int i; 650 u32 *phy_reg_page; 651 u16 phy_reg_page_len; 652 u32 v1 = 0, v2 = 0; 653 654 phy_reg_page_len = RTL8188EEPHY_REG_ARRAY_PGLEN; 655 phy_reg_page = RTL8188EEPHY_REG_ARRAY_PG; 656 657 if (configtype == BASEBAND_CONFIG_PHY_REG) { 658 for (i = 0; i < phy_reg_page_len; i = i + 3) { 659 v1 = phy_reg_page[i]; 660 v2 = phy_reg_page[i+1]; 661 662 if (v1 < 0xcdcdcdcd) { 663 if (phy_reg_page[i] == 0xfe) 664 mdelay(50); 665 else if (phy_reg_page[i] == 0xfd) 666 mdelay(5); 667 else if (phy_reg_page[i] == 0xfc) 668 mdelay(1); 669 else if (phy_reg_page[i] == 0xfb) 670 udelay(50); 671 else if (phy_reg_page[i] == 0xfa) 672 udelay(5); 673 else if (phy_reg_page[i] == 0xf9) 674 udelay(1); 675 676 store_pwrindex_rate_offset(hw, phy_reg_page[i], 677 phy_reg_page[i + 1], 678 phy_reg_page[i + 2]); 679 continue; 680 } else { 681 if (!_rtl88e_check_condition(hw, 682 phy_reg_page[i])) { 683 /*don't need the hw_body*/ 684 i += 2; /* skip the pair of expression*/ 685 /* to protect 'i+1' 'i+2' not overrun */ 686 if (i >= phy_reg_page_len - 2) 687 break; 688 689 v1 = phy_reg_page[i]; 690 v2 = phy_reg_page[i+1]; 691 while (v2 != 0xDEAD && 692 i < phy_reg_page_len - 5) { 693 i += 3; 694 v1 = phy_reg_page[i]; 695 v2 = phy_reg_page[i+1]; 696 } 697 } 698 } 699 } 700 } else { 701 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, 702 "configtype != BaseBand_Config_PHY_REG\n"); 703 } 704 return true; 705 } 706 707 #define READ_NEXT_RF_PAIR(v1, v2, i) \ 708 do { \ 709 i += 2; \ 710 v1 = radioa_array_table[i]; \ 711 v2 = radioa_array_table[i+1]; \ 712 } while (0) 713 714 static void process_path_a(struct ieee80211_hw *hw, 715 u16 radioa_arraylen, 716 u32 *radioa_array_table) 717 { 718 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 719 u32 v1, v2; 720 int i; 721 722 for (i = 0; i < radioa_arraylen; i = i + 2) { 723 v1 = radioa_array_table[i]; 724 v2 = radioa_array_table[i+1]; 725 if (v1 < 0xcdcdcdcd) { 726 _rtl8188e_config_rf_radio_a(hw, v1, v2); 727 } else { /*This line is the start line of branch.*/ 728 /* to protect READ_NEXT_PAIR not overrun */ 729 if (i >= radioa_arraylen - 2) 730 break; 731 732 if (!_rtl88e_check_condition(hw, radioa_array_table[i])) { 733 /*Discard the following (offset, data) pairs*/ 734 READ_NEXT_RF_PAIR(v1, v2, i); 735 while (v2 != 0xDEAD && 736 v2 != 0xCDEF && 737 v2 != 0xCDCD && 738 i < radioa_arraylen - 2) { 739 READ_NEXT_RF_PAIR(v1, v2, i); 740 } 741 i -= 2; /* prevent from for-loop += 2*/ 742 } else { /* Configure matched pairs and 743 * skip to end of if-else. 744 */ 745 READ_NEXT_RF_PAIR(v1, v2, i); 746 while (v2 != 0xDEAD && 747 v2 != 0xCDEF && 748 v2 != 0xCDCD && 749 i < radioa_arraylen - 2) { 750 _rtl8188e_config_rf_radio_a(hw, v1, v2); 751 READ_NEXT_RF_PAIR(v1, v2, i); 752 } 753 754 while (v2 != 0xDEAD && 755 i < radioa_arraylen - 2) 756 READ_NEXT_RF_PAIR(v1, v2, i); 757 } 758 } 759 } 760 761 if (rtlhal->oem_id == RT_CID_819X_HP) 762 _rtl8188e_config_rf_radio_a(hw, 0x52, 0x7E4BD); 763 } 764 765 bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 766 enum radio_path rfpath) 767 { 768 struct rtl_priv *rtlpriv = rtl_priv(hw); 769 u32 *radioa_array_table; 770 u16 radioa_arraylen; 771 772 radioa_arraylen = RTL8188EE_RADIOA_1TARRAYLEN; 773 radioa_array_table = RTL8188EE_RADIOA_1TARRAY; 774 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 775 "Radio_A:RTL8188EE_RADIOA_1TARRAY %d\n", radioa_arraylen); 776 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath); 777 switch (rfpath) { 778 case RF90_PATH_A: 779 process_path_a(hw, radioa_arraylen, radioa_array_table); 780 break; 781 case RF90_PATH_B: 782 case RF90_PATH_C: 783 case RF90_PATH_D: 784 break; 785 } 786 return true; 787 } 788 789 void rtl88e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) 790 { 791 struct rtl_priv *rtlpriv = rtl_priv(hw); 792 struct rtl_phy *rtlphy = &rtlpriv->phy; 793 794 rtlphy->default_initialgain[0] = 795 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); 796 rtlphy->default_initialgain[1] = 797 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); 798 rtlphy->default_initialgain[2] = 799 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); 800 rtlphy->default_initialgain[3] = 801 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); 802 803 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 804 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", 805 rtlphy->default_initialgain[0], 806 rtlphy->default_initialgain[1], 807 rtlphy->default_initialgain[2], 808 rtlphy->default_initialgain[3]); 809 810 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, 811 MASKBYTE0); 812 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, 813 MASKDWORD); 814 815 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 816 "Default framesync (0x%x) = 0x%x\n", 817 ROFDM0_RXDETECTOR3, rtlphy->framesync); 818 } 819 820 static void _rtl88e_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) 821 { 822 struct rtl_priv *rtlpriv = rtl_priv(hw); 823 struct rtl_phy *rtlphy = &rtlpriv->phy; 824 825 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; 826 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; 827 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; 828 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; 829 830 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; 831 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; 832 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; 833 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; 834 835 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; 836 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; 837 838 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; 839 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; 840 841 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = 842 RFPGA0_XA_LSSIPARAMETER; 843 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = 844 RFPGA0_XB_LSSIPARAMETER; 845 846 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; 847 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; 848 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; 849 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; 850 851 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; 852 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; 853 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; 854 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; 855 856 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; 857 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; 858 859 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; 860 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; 861 862 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = 863 RFPGA0_XAB_SWITCHCONTROL; 864 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = 865 RFPGA0_XAB_SWITCHCONTROL; 866 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = 867 RFPGA0_XCD_SWITCHCONTROL; 868 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = 869 RFPGA0_XCD_SWITCHCONTROL; 870 871 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; 872 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; 873 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; 874 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; 875 876 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; 877 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; 878 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; 879 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; 880 881 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; 882 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; 883 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE; 884 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; 885 886 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; 887 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; 888 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; 889 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; 890 891 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; 892 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE; 893 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE; 894 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; 895 896 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; 897 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE; 898 899 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; 900 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; 901 902 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK; 903 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK; 904 } 905 906 void rtl88e_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel) 907 { 908 struct rtl_priv *rtlpriv = rtl_priv(hw); 909 struct rtl_phy *rtlphy = &rtlpriv->phy; 910 u8 txpwr_level; 911 long txpwr_dbm; 912 913 txpwr_level = rtlphy->cur_cck_txpwridx; 914 txpwr_dbm = _rtl88e_phy_txpwr_idx_to_dbm(hw, 915 WIRELESS_MODE_B, txpwr_level); 916 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; 917 if (_rtl88e_phy_txpwr_idx_to_dbm(hw, 918 WIRELESS_MODE_G, 919 txpwr_level) > txpwr_dbm) 920 txpwr_dbm = 921 _rtl88e_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, 922 txpwr_level); 923 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; 924 if (_rtl88e_phy_txpwr_idx_to_dbm(hw, 925 WIRELESS_MODE_N_24G, 926 txpwr_level) > txpwr_dbm) 927 txpwr_dbm = 928 _rtl88e_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, 929 txpwr_level); 930 *powerlevel = txpwr_dbm; 931 } 932 933 static void handle_path_a(struct rtl_efuse *rtlefuse, u8 index, 934 u8 *cckpowerlevel, u8 *ofdmpowerlevel, 935 u8 *bw20powerlevel, u8 *bw40powerlevel) 936 { 937 cckpowerlevel[RF90_PATH_A] = 938 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index]; 939 /*-8~7 */ 940 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][index] > 0x0f) 941 bw20powerlevel[RF90_PATH_A] = 942 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] - 943 (~(rtlefuse->txpwr_ht20diff[RF90_PATH_A][index]) + 1); 944 else 945 bw20powerlevel[RF90_PATH_A] = 946 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] + 947 rtlefuse->txpwr_ht20diff[RF90_PATH_A][index]; 948 if (rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index] > 0xf) 949 ofdmpowerlevel[RF90_PATH_A] = 950 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] - 951 (~(rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index])+1); 952 else 953 ofdmpowerlevel[RF90_PATH_A] = 954 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] + 955 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index]; 956 bw40powerlevel[RF90_PATH_A] = 957 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index]; 958 } 959 960 static void _rtl88e_get_txpower_index(struct ieee80211_hw *hw, u8 channel, 961 u8 *cckpowerlevel, u8 *ofdmpowerlevel, 962 u8 *bw20powerlevel, u8 *bw40powerlevel) 963 { 964 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 965 u8 index = (channel - 1); 966 u8 rf_path = 0; 967 968 for (rf_path = 0; rf_path < 2; rf_path++) { 969 if (rf_path == RF90_PATH_A) { 970 handle_path_a(rtlefuse, index, cckpowerlevel, 971 ofdmpowerlevel, bw20powerlevel, 972 bw40powerlevel); 973 } else if (rf_path == RF90_PATH_B) { 974 cckpowerlevel[RF90_PATH_B] = 975 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index]; 976 bw20powerlevel[RF90_PATH_B] = 977 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index] + 978 rtlefuse->txpwr_ht20diff[RF90_PATH_B][index]; 979 ofdmpowerlevel[RF90_PATH_B] = 980 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index] + 981 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][index]; 982 bw40powerlevel[RF90_PATH_B] = 983 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index]; 984 } 985 } 986 987 } 988 989 static void _rtl88e_ccxpower_index_check(struct ieee80211_hw *hw, 990 u8 channel, u8 *cckpowerlevel, 991 u8 *ofdmpowerlevel, u8 *bw20powerlevel, 992 u8 *bw40powerlevel) 993 { 994 struct rtl_priv *rtlpriv = rtl_priv(hw); 995 struct rtl_phy *rtlphy = &rtlpriv->phy; 996 997 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; 998 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; 999 rtlphy->cur_bw20_txpwridx = bw20powerlevel[0]; 1000 rtlphy->cur_bw40_txpwridx = bw40powerlevel[0]; 1001 1002 } 1003 1004 void rtl88e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) 1005 { 1006 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1007 u8 cckpowerlevel[MAX_TX_COUNT] = {0}; 1008 u8 ofdmpowerlevel[MAX_TX_COUNT] = {0}; 1009 u8 bw20powerlevel[MAX_TX_COUNT] = {0}; 1010 u8 bw40powerlevel[MAX_TX_COUNT] = {0}; 1011 1012 if (!rtlefuse->txpwr_fromeprom) 1013 return; 1014 _rtl88e_get_txpower_index(hw, channel, 1015 &cckpowerlevel[0], &ofdmpowerlevel[0], 1016 &bw20powerlevel[0], &bw40powerlevel[0]); 1017 _rtl88e_ccxpower_index_check(hw, channel, 1018 &cckpowerlevel[0], &ofdmpowerlevel[0], 1019 &bw20powerlevel[0], &bw40powerlevel[0]); 1020 rtl88e_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); 1021 rtl88e_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], 1022 &bw20powerlevel[0], 1023 &bw40powerlevel[0], channel); 1024 } 1025 1026 static long _rtl88e_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, 1027 enum wireless_mode wirelessmode, 1028 u8 txpwridx) 1029 { 1030 long offset; 1031 long pwrout_dbm; 1032 1033 switch (wirelessmode) { 1034 case WIRELESS_MODE_B: 1035 offset = -7; 1036 break; 1037 case WIRELESS_MODE_G: 1038 case WIRELESS_MODE_N_24G: 1039 offset = -8; 1040 break; 1041 default: 1042 offset = -8; 1043 break; 1044 } 1045 pwrout_dbm = txpwridx / 2 + offset; 1046 return pwrout_dbm; 1047 } 1048 1049 void rtl88e_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation) 1050 { 1051 struct rtl_priv *rtlpriv = rtl_priv(hw); 1052 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1053 enum io_type iotype; 1054 1055 if (!is_hal_stop(rtlhal)) { 1056 switch (operation) { 1057 case SCAN_OPT_BACKUP_BAND0: 1058 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN; 1059 rtlpriv->cfg->ops->set_hw_reg(hw, 1060 HW_VAR_IO_CMD, 1061 (u8 *)&iotype); 1062 1063 break; 1064 case SCAN_OPT_RESTORE: 1065 iotype = IO_CMD_RESUME_DM_BY_SCAN; 1066 rtlpriv->cfg->ops->set_hw_reg(hw, 1067 HW_VAR_IO_CMD, 1068 (u8 *)&iotype); 1069 break; 1070 default: 1071 pr_err("Unknown Scan Backup operation.\n"); 1072 break; 1073 } 1074 } 1075 } 1076 1077 void rtl88e_phy_set_bw_mode_callback(struct ieee80211_hw *hw) 1078 { 1079 struct rtl_priv *rtlpriv = rtl_priv(hw); 1080 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1081 struct rtl_phy *rtlphy = &rtlpriv->phy; 1082 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1083 u8 reg_bw_opmode; 1084 u8 reg_prsr_rsc; 1085 1086 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, 1087 "Switch to %s bandwidth\n", 1088 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 1089 "20MHz" : "40MHz"); 1090 1091 if (is_hal_stop(rtlhal)) { 1092 rtlphy->set_bwmode_inprogress = false; 1093 return; 1094 } 1095 1096 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE); 1097 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2); 1098 1099 switch (rtlphy->current_chan_bw) { 1100 case HT_CHANNEL_WIDTH_20: 1101 reg_bw_opmode |= BW_OPMODE_20MHZ; 1102 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 1103 break; 1104 case HT_CHANNEL_WIDTH_20_40: 1105 reg_bw_opmode &= ~BW_OPMODE_20MHZ; 1106 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 1107 reg_prsr_rsc = 1108 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5); 1109 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc); 1110 break; 1111 default: 1112 pr_err("unknown bandwidth: %#X\n", 1113 rtlphy->current_chan_bw); 1114 break; 1115 } 1116 1117 switch (rtlphy->current_chan_bw) { 1118 case HT_CHANNEL_WIDTH_20: 1119 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); 1120 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); 1121 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);*/ 1122 break; 1123 case HT_CHANNEL_WIDTH_20_40: 1124 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); 1125 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); 1126 1127 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, 1128 (mac->cur_40_prime_sc >> 1)); 1129 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); 1130 /*rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);*/ 1131 1132 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), 1133 (mac->cur_40_prime_sc == 1134 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); 1135 break; 1136 default: 1137 pr_err("unknown bandwidth: %#X\n", 1138 rtlphy->current_chan_bw); 1139 break; 1140 } 1141 rtl88e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 1142 rtlphy->set_bwmode_inprogress = false; 1143 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, "\n"); 1144 } 1145 1146 void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw, 1147 enum nl80211_channel_type ch_type) 1148 { 1149 struct rtl_priv *rtlpriv = rtl_priv(hw); 1150 struct rtl_phy *rtlphy = &rtlpriv->phy; 1151 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1152 u8 tmp_bw = rtlphy->current_chan_bw; 1153 1154 if (rtlphy->set_bwmode_inprogress) 1155 return; 1156 rtlphy->set_bwmode_inprogress = true; 1157 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { 1158 rtl88e_phy_set_bw_mode_callback(hw); 1159 } else { 1160 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1161 "false driver sleep or unload\n"); 1162 rtlphy->set_bwmode_inprogress = false; 1163 rtlphy->current_chan_bw = tmp_bw; 1164 } 1165 } 1166 1167 void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw) 1168 { 1169 struct rtl_priv *rtlpriv = rtl_priv(hw); 1170 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1171 struct rtl_phy *rtlphy = &rtlpriv->phy; 1172 u32 delay; 1173 1174 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, 1175 "switch to channel%d\n", rtlphy->current_channel); 1176 if (is_hal_stop(rtlhal)) 1177 return; 1178 do { 1179 if (!rtlphy->sw_chnl_inprogress) 1180 break; 1181 if (!_rtl88e_phy_sw_chnl_step_by_step 1182 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage, 1183 &rtlphy->sw_chnl_step, &delay)) { 1184 if (delay > 0) 1185 mdelay(delay); 1186 else 1187 continue; 1188 } else { 1189 rtlphy->sw_chnl_inprogress = false; 1190 } 1191 break; 1192 } while (true); 1193 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n"); 1194 } 1195 1196 u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw) 1197 { 1198 struct rtl_priv *rtlpriv = rtl_priv(hw); 1199 struct rtl_phy *rtlphy = &rtlpriv->phy; 1200 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1201 1202 if (rtlphy->sw_chnl_inprogress) 1203 return 0; 1204 if (rtlphy->set_bwmode_inprogress) 1205 return 0; 1206 WARN_ONCE((rtlphy->current_channel > 14), 1207 "rtl8188ee: WIRELESS_MODE_G but channel>14"); 1208 rtlphy->sw_chnl_inprogress = true; 1209 rtlphy->sw_chnl_stage = 0; 1210 rtlphy->sw_chnl_step = 0; 1211 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { 1212 rtl88e_phy_sw_chnl_callback(hw); 1213 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, 1214 "sw_chnl_inprogress false schedule workitem current channel %d\n", 1215 rtlphy->current_channel); 1216 rtlphy->sw_chnl_inprogress = false; 1217 } else { 1218 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, 1219 "sw_chnl_inprogress false driver sleep or unload\n"); 1220 rtlphy->sw_chnl_inprogress = false; 1221 } 1222 return 1; 1223 } 1224 1225 static bool _rtl88e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, 1226 u8 channel, u8 *stage, u8 *step, 1227 u32 *delay) 1228 { 1229 struct rtl_priv *rtlpriv = rtl_priv(hw); 1230 struct rtl_phy *rtlphy = &rtlpriv->phy; 1231 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT]; 1232 u32 precommoncmdcnt; 1233 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT]; 1234 u32 postcommoncmdcnt; 1235 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT]; 1236 u32 rfdependcmdcnt; 1237 struct swchnlcmd *currentcmd = NULL; 1238 u8 rfpath; 1239 u8 num_total_rfpath = rtlphy->num_total_rfpath; 1240 1241 precommoncmdcnt = 0; 1242 _rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 1243 MAX_PRECMD_CNT, 1244 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); 1245 _rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 1246 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); 1247 1248 postcommoncmdcnt = 0; 1249 1250 _rtl88e_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, 1251 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); 1252 1253 rfdependcmdcnt = 0; 1254 1255 WARN_ONCE((channel < 1 || channel > 14), 1256 "rtl8188ee: illegal channel for Zebra: %d\n", channel); 1257 1258 _rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 1259 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG, 1260 RF_CHNLBW, channel, 10); 1261 1262 _rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 1263 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 1264 0); 1265 1266 do { 1267 switch (*stage) { 1268 case 0: 1269 currentcmd = &precommoncmd[*step]; 1270 break; 1271 case 1: 1272 currentcmd = &rfdependcmd[*step]; 1273 break; 1274 case 2: 1275 currentcmd = &postcommoncmd[*step]; 1276 break; 1277 default: 1278 pr_err("Invalid 'stage' = %d, Check it!\n", 1279 *stage); 1280 return true; 1281 } 1282 1283 if (currentcmd->cmdid == CMDID_END) { 1284 if ((*stage) == 2) 1285 return true; 1286 (*stage)++; 1287 (*step) = 0; 1288 continue; 1289 } 1290 1291 switch (currentcmd->cmdid) { 1292 case CMDID_SET_TXPOWEROWER_LEVEL: 1293 rtl88e_phy_set_txpower_level(hw, channel); 1294 break; 1295 case CMDID_WRITEPORT_ULONG: 1296 rtl_write_dword(rtlpriv, currentcmd->para1, 1297 currentcmd->para2); 1298 break; 1299 case CMDID_WRITEPORT_USHORT: 1300 rtl_write_word(rtlpriv, currentcmd->para1, 1301 (u16)currentcmd->para2); 1302 break; 1303 case CMDID_WRITEPORT_UCHAR: 1304 rtl_write_byte(rtlpriv, currentcmd->para1, 1305 (u8)currentcmd->para2); 1306 break; 1307 case CMDID_RF_WRITEREG: 1308 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { 1309 rtlphy->rfreg_chnlval[rfpath] = 1310 ((rtlphy->rfreg_chnlval[rfpath] & 1311 0xfffffc00) | currentcmd->para2); 1312 1313 rtl_set_rfreg(hw, (enum radio_path)rfpath, 1314 currentcmd->para1, 1315 RFREG_OFFSET_MASK, 1316 rtlphy->rfreg_chnlval[rfpath]); 1317 } 1318 break; 1319 default: 1320 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 1321 "switch case %#x not processed\n", 1322 currentcmd->cmdid); 1323 break; 1324 } 1325 1326 break; 1327 } while (true); 1328 1329 (*delay) = currentcmd->msdelay; 1330 (*step)++; 1331 return false; 1332 } 1333 1334 static bool _rtl88e_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, 1335 u32 cmdtableidx, u32 cmdtablesz, 1336 enum swchnlcmd_id cmdid, 1337 u32 para1, u32 para2, u32 msdelay) 1338 { 1339 struct swchnlcmd *pcmd; 1340 1341 if (cmdtable == NULL) { 1342 WARN_ONCE(true, "rtl8188ee: cmdtable cannot be NULL.\n"); 1343 return false; 1344 } 1345 1346 if (cmdtableidx >= cmdtablesz) 1347 return false; 1348 1349 pcmd = cmdtable + cmdtableidx; 1350 pcmd->cmdid = cmdid; 1351 pcmd->para1 = para1; 1352 pcmd->para2 = para2; 1353 pcmd->msdelay = msdelay; 1354 return true; 1355 } 1356 1357 static u8 _rtl88e_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb) 1358 { 1359 u32 reg_eac, reg_e94, reg_e9c, reg_ea4; 1360 u8 result = 0x00; 1361 1362 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1c); 1363 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x30008c1c); 1364 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x8214032a); 1365 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160000); 1366 1367 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); 1368 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); 1369 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); 1370 1371 mdelay(IQK_DELAY_TIME); 1372 1373 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1374 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); 1375 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); 1376 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); 1377 1378 if (!(reg_eac & BIT(28)) && 1379 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && 1380 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) 1381 result |= 0x01; 1382 return result; 1383 } 1384 1385 static u8 _rtl88e_phy_path_b_iqk(struct ieee80211_hw *hw) 1386 { 1387 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; 1388 u8 result = 0x00; 1389 1390 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); 1391 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); 1392 mdelay(IQK_DELAY_TIME); 1393 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1394 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); 1395 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); 1396 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); 1397 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); 1398 1399 if (!(reg_eac & BIT(31)) && 1400 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) && 1401 (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) 1402 result |= 0x01; 1403 else 1404 return result; 1405 if (!(reg_eac & BIT(30)) && 1406 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) && 1407 (((reg_ecc & 0x03FF0000) >> 16) != 0x36)) 1408 result |= 0x02; 1409 return result; 1410 } 1411 1412 static u8 _rtl88e_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb) 1413 { 1414 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u32temp; 1415 u8 result = 0x00; 1416 1417 /*Get TXIMR Setting*/ 1418 /*Modify RX IQK mode table*/ 1419 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); 1420 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); 1421 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); 1422 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); 1423 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); 1424 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); 1425 1426 /*IQK Setting*/ 1427 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); 1428 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x81004800); 1429 1430 /*path a IQK setting*/ 1431 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1c); 1432 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x30008c1c); 1433 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160804); 1434 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000); 1435 1436 /*LO calibration Setting*/ 1437 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); 1438 /*one shot,path A LOK & iqk*/ 1439 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); 1440 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); 1441 1442 mdelay(IQK_DELAY_TIME); 1443 1444 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); 1445 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); 1446 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); 1447 1448 1449 if (!(reg_eac & BIT(28)) && 1450 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && 1451 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) 1452 result |= 0x01; 1453 else 1454 return result; 1455 1456 u32temp = 0x80007C00 | (reg_e94&0x3FF0000) | 1457 ((reg_e9c&0x3FF0000) >> 16); 1458 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); 1459 /*RX IQK*/ 1460 /*Modify RX IQK mode table*/ 1461 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); 1462 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); 1463 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); 1464 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); 1465 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); 1466 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); 1467 1468 /*IQK Setting*/ 1469 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); 1470 1471 /*path a IQK setting*/ 1472 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x30008c1c); 1473 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1c); 1474 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c05); 1475 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c05); 1476 1477 /*LO calibration Setting*/ 1478 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); 1479 /*one shot,path A LOK & iqk*/ 1480 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); 1481 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); 1482 1483 mdelay(IQK_DELAY_TIME); 1484 1485 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); 1486 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); 1487 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); 1488 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); 1489 1490 if (!(reg_eac & BIT(27)) && 1491 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) && 1492 (((reg_eac & 0x03FF0000) >> 16) != 0x36)) 1493 result |= 0x02; 1494 return result; 1495 } 1496 1497 static void _rtl88e_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw, 1498 bool iqk_ok, long result[][8], 1499 u8 final_candidate, bool btxonly) 1500 { 1501 u32 oldval_0, x, tx0_a, reg; 1502 long y, tx0_c; 1503 1504 if (final_candidate == 0xFF) { 1505 return; 1506 } else if (iqk_ok) { 1507 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 1508 MASKDWORD) >> 22) & 0x3FF; 1509 x = result[final_candidate][0]; 1510 if ((x & 0x00000200) != 0) 1511 x = x | 0xFFFFFC00; 1512 tx0_a = (x * oldval_0) >> 8; 1513 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); 1514 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), 1515 ((x * oldval_0 >> 7) & 0x1)); 1516 y = result[final_candidate][1]; 1517 if ((y & 0x00000200) != 0) 1518 y = y | 0xFFFFFC00; 1519 tx0_c = (y * oldval_0) >> 8; 1520 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 1521 ((tx0_c & 0x3C0) >> 6)); 1522 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, 1523 (tx0_c & 0x3F)); 1524 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), 1525 ((y * oldval_0 >> 7) & 0x1)); 1526 if (btxonly) 1527 return; 1528 reg = result[final_candidate][2]; 1529 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); 1530 reg = result[final_candidate][3] & 0x3F; 1531 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); 1532 reg = (result[final_candidate][3] >> 6) & 0xF; 1533 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); 1534 } 1535 } 1536 1537 static void _rtl88e_phy_save_adda_registers(struct ieee80211_hw *hw, 1538 u32 *addareg, u32 *addabackup, 1539 u32 registernum) 1540 { 1541 u32 i; 1542 1543 for (i = 0; i < registernum; i++) 1544 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD); 1545 } 1546 1547 static void _rtl88e_phy_save_mac_registers(struct ieee80211_hw *hw, 1548 u32 *macreg, u32 *macbackup) 1549 { 1550 struct rtl_priv *rtlpriv = rtl_priv(hw); 1551 u32 i; 1552 1553 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 1554 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]); 1555 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]); 1556 } 1557 1558 static void _rtl88e_phy_reload_adda_registers(struct ieee80211_hw *hw, 1559 u32 *addareg, u32 *addabackup, 1560 u32 regiesternum) 1561 { 1562 u32 i; 1563 1564 for (i = 0; i < regiesternum; i++) 1565 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); 1566 } 1567 1568 static void _rtl88e_phy_reload_mac_registers(struct ieee80211_hw *hw, 1569 u32 *macreg, u32 *macbackup) 1570 { 1571 struct rtl_priv *rtlpriv = rtl_priv(hw); 1572 u32 i; 1573 1574 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 1575 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]); 1576 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]); 1577 } 1578 1579 static void _rtl88e_phy_path_adda_on(struct ieee80211_hw *hw, 1580 u32 *addareg, bool is_patha_on, bool is2t) 1581 { 1582 u32 pathon; 1583 u32 i; 1584 1585 pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4; 1586 if (false == is2t) { 1587 pathon = 0x0bdb25a0; 1588 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); 1589 } else { 1590 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); 1591 } 1592 1593 for (i = 1; i < IQK_ADDA_REG_NUM; i++) 1594 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon); 1595 } 1596 1597 static void _rtl88e_phy_mac_setting_calibration(struct ieee80211_hw *hw, 1598 u32 *macreg, u32 *macbackup) 1599 { 1600 struct rtl_priv *rtlpriv = rtl_priv(hw); 1601 u32 i = 0; 1602 1603 rtl_write_byte(rtlpriv, macreg[i], 0x3F); 1604 1605 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) 1606 rtl_write_byte(rtlpriv, macreg[i], 1607 (u8) (macbackup[i] & (~BIT(3)))); 1608 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5)))); 1609 } 1610 1611 static void _rtl88e_phy_path_a_standby(struct ieee80211_hw *hw) 1612 { 1613 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); 1614 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); 1615 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 1616 } 1617 1618 static void _rtl88e_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode) 1619 { 1620 u32 mode; 1621 1622 mode = pi_mode ? 0x01000100 : 0x01000000; 1623 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); 1624 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); 1625 } 1626 1627 static bool _rtl88e_phy_simularity_compare(struct ieee80211_hw *hw, 1628 long result[][8], u8 c1, u8 c2) 1629 { 1630 u32 i, j, diff, simularity_bitmap, bound; 1631 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1632 1633 u8 final_candidate[2] = { 0xFF, 0xFF }; 1634 bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version); 1635 1636 if (is2t) 1637 bound = 8; 1638 else 1639 bound = 4; 1640 1641 simularity_bitmap = 0; 1642 1643 for (i = 0; i < bound; i++) { 1644 diff = (result[c1][i] > result[c2][i]) ? 1645 (result[c1][i] - result[c2][i]) : 1646 (result[c2][i] - result[c1][i]); 1647 1648 if (diff > MAX_TOLERANCE) { 1649 if ((i == 2 || i == 6) && !simularity_bitmap) { 1650 if (result[c1][i] + result[c1][i + 1] == 0) 1651 final_candidate[(i / 4)] = c2; 1652 else if (result[c2][i] + result[c2][i + 1] == 0) 1653 final_candidate[(i / 4)] = c1; 1654 else 1655 simularity_bitmap = simularity_bitmap | 1656 (1 << i); 1657 } else 1658 simularity_bitmap = 1659 simularity_bitmap | (1 << i); 1660 } 1661 } 1662 1663 if (simularity_bitmap == 0) { 1664 for (i = 0; i < (bound / 4); i++) { 1665 if (final_candidate[i] != 0xFF) { 1666 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 1667 result[3][j] = 1668 result[final_candidate[i]][j]; 1669 bresult = false; 1670 } 1671 } 1672 return bresult; 1673 } else if (!(simularity_bitmap & 0x0F)) { 1674 for (i = 0; i < 4; i++) 1675 result[3][i] = result[c1][i]; 1676 return false; 1677 } else if (!(simularity_bitmap & 0xF0) && is2t) { 1678 for (i = 4; i < 8; i++) 1679 result[3][i] = result[c1][i]; 1680 return false; 1681 } else { 1682 return false; 1683 } 1684 1685 } 1686 1687 static void _rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, 1688 long result[][8], u8 t, bool is2t) 1689 { 1690 struct rtl_priv *rtlpriv = rtl_priv(hw); 1691 struct rtl_phy *rtlphy = &rtlpriv->phy; 1692 u32 i; 1693 u8 patha_ok, pathb_ok; 1694 u32 adda_reg[IQK_ADDA_REG_NUM] = { 1695 0x85c, 0xe6c, 0xe70, 0xe74, 1696 0xe78, 0xe7c, 0xe80, 0xe84, 1697 0xe88, 0xe8c, 0xed0, 0xed4, 1698 0xed8, 0xedc, 0xee0, 0xeec 1699 }; 1700 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { 1701 0x522, 0x550, 0x551, 0x040 1702 }; 1703 u32 iqk_bb_reg[IQK_BB_REG_NUM] = { 1704 ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR, 1705 RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c, 1706 0x870, 0x860, 0x864, 0x800 1707 }; 1708 const u32 retrycount = 2; 1709 1710 if (t == 0) { 1711 _rtl88e_phy_save_adda_registers(hw, adda_reg, 1712 rtlphy->adda_backup, 16); 1713 _rtl88e_phy_save_mac_registers(hw, iqk_mac_reg, 1714 rtlphy->iqk_mac_backup); 1715 _rtl88e_phy_save_adda_registers(hw, iqk_bb_reg, 1716 rtlphy->iqk_bb_backup, 1717 IQK_BB_REG_NUM); 1718 } 1719 _rtl88e_phy_path_adda_on(hw, adda_reg, true, is2t); 1720 if (t == 0) { 1721 rtlphy->rfpi_enable = 1722 (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, BIT(8)); 1723 } 1724 1725 if (!rtlphy->rfpi_enable) 1726 _rtl88e_phy_pi_mode_switch(hw, true); 1727 /*BB Setting*/ 1728 rtl_set_bbreg(hw, 0x800, BIT(24), 0x00); 1729 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); 1730 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); 1731 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); 1732 1733 rtl_set_bbreg(hw, 0x870, BIT(10), 0x01); 1734 rtl_set_bbreg(hw, 0x870, BIT(26), 0x01); 1735 rtl_set_bbreg(hw, 0x860, BIT(10), 0x00); 1736 rtl_set_bbreg(hw, 0x864, BIT(10), 0x00); 1737 1738 if (is2t) { 1739 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); 1740 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); 1741 } 1742 _rtl88e_phy_mac_setting_calibration(hw, iqk_mac_reg, 1743 rtlphy->iqk_mac_backup); 1744 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); 1745 if (is2t) 1746 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); 1747 1748 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 1749 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); 1750 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x81004800); 1751 for (i = 0; i < retrycount; i++) { 1752 patha_ok = _rtl88e_phy_path_a_iqk(hw, is2t); 1753 if (patha_ok == 0x01) { 1754 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1755 "Path A Tx IQK Success!!\n"); 1756 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 1757 0x3FF0000) >> 16; 1758 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 1759 0x3FF0000) >> 16; 1760 break; 1761 } 1762 } 1763 1764 for (i = 0; i < retrycount; i++) { 1765 patha_ok = _rtl88e_phy_path_a_rx_iqk(hw, is2t); 1766 if (patha_ok == 0x03) { 1767 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1768 "Path A Rx IQK Success!!\n"); 1769 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & 1770 0x3FF0000) >> 16; 1771 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & 1772 0x3FF0000) >> 16; 1773 break; 1774 } else { 1775 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1776 "Path a RX iqk fail!!!\n"); 1777 } 1778 } 1779 1780 if (0 == patha_ok) 1781 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1782 "Path A IQK Success!!\n"); 1783 if (is2t) { 1784 _rtl88e_phy_path_a_standby(hw); 1785 _rtl88e_phy_path_adda_on(hw, adda_reg, false, is2t); 1786 for (i = 0; i < retrycount; i++) { 1787 pathb_ok = _rtl88e_phy_path_b_iqk(hw); 1788 if (pathb_ok == 0x03) { 1789 result[t][4] = (rtl_get_bbreg(hw, 1790 0xeb4, 1791 MASKDWORD) & 1792 0x3FF0000) >> 16; 1793 result[t][5] = 1794 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 1795 0x3FF0000) >> 16; 1796 result[t][6] = 1797 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & 1798 0x3FF0000) >> 16; 1799 result[t][7] = 1800 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & 1801 0x3FF0000) >> 16; 1802 break; 1803 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { 1804 result[t][4] = (rtl_get_bbreg(hw, 1805 0xeb4, 1806 MASKDWORD) & 1807 0x3FF0000) >> 16; 1808 } 1809 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 1810 0x3FF0000) >> 16; 1811 } 1812 } 1813 1814 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); 1815 1816 if (t != 0) { 1817 if (!rtlphy->rfpi_enable) 1818 _rtl88e_phy_pi_mode_switch(hw, false); 1819 _rtl88e_phy_reload_adda_registers(hw, adda_reg, 1820 rtlphy->adda_backup, 16); 1821 _rtl88e_phy_reload_mac_registers(hw, iqk_mac_reg, 1822 rtlphy->iqk_mac_backup); 1823 _rtl88e_phy_reload_adda_registers(hw, iqk_bb_reg, 1824 rtlphy->iqk_bb_backup, 1825 IQK_BB_REG_NUM); 1826 1827 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3); 1828 if (is2t) 1829 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); 1830 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); 1831 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); 1832 } 1833 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "88ee IQK Finish!!\n"); 1834 } 1835 1836 static void _rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) 1837 { 1838 u8 tmpreg; 1839 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal; 1840 struct rtl_priv *rtlpriv = rtl_priv(hw); 1841 1842 tmpreg = rtl_read_byte(rtlpriv, 0xd03); 1843 1844 if ((tmpreg & 0x70) != 0) 1845 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); 1846 else 1847 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1848 1849 if ((tmpreg & 0x70) != 0) { 1850 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); 1851 1852 if (is2t) 1853 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, 1854 MASK12BITS); 1855 1856 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, 1857 (rf_a_mode & 0x8FFFF) | 0x10000); 1858 1859 if (is2t) 1860 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, 1861 (rf_b_mode & 0x8FFFF) | 0x10000); 1862 } 1863 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); 1864 1865 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); 1866 1867 mdelay(100); 1868 1869 if ((tmpreg & 0x70) != 0) { 1870 rtl_write_byte(rtlpriv, 0xd03, tmpreg); 1871 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); 1872 1873 if (is2t) 1874 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, 1875 rf_b_mode); 1876 } else { 1877 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 1878 } 1879 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n"); 1880 } 1881 1882 static void _rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, 1883 bool bmain, bool is2t) 1884 { 1885 struct rtl_priv *rtlpriv = rtl_priv(hw); 1886 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1887 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1888 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n"); 1889 1890 if (is_hal_stop(rtlhal)) { 1891 u8 u1btmp; 1892 u1btmp = rtl_read_byte(rtlpriv, REG_LEDCFG0); 1893 rtl_write_byte(rtlpriv, REG_LEDCFG0, u1btmp | BIT(7)); 1894 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); 1895 } 1896 if (is2t) { 1897 if (bmain) 1898 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 1899 BIT(5) | BIT(6), 0x1); 1900 else 1901 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 1902 BIT(5) | BIT(6), 0x2); 1903 } else { 1904 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0); 1905 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201); 1906 1907 /* We use the RF definition of MAIN and AUX, 1908 * left antenna and right antenna repectively. 1909 * Default output at AUX. 1910 */ 1911 if (bmain) { 1912 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 1913 BIT(14) | BIT(13) | BIT(12), 0); 1914 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 1915 BIT(5) | BIT(4) | BIT(3), 0); 1916 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) 1917 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0); 1918 } else { 1919 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 1920 BIT(14) | BIT(13) | BIT(12), 1); 1921 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 1922 BIT(5) | BIT(4) | BIT(3), 1); 1923 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) 1924 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1); 1925 } 1926 } 1927 } 1928 1929 #undef IQK_ADDA_REG_NUM 1930 #undef IQK_DELAY_TIME 1931 1932 void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery) 1933 { 1934 struct rtl_priv *rtlpriv = rtl_priv(hw); 1935 struct rtl_phy *rtlphy = &rtlpriv->phy; 1936 long result[4][8]; 1937 u8 i, final_candidate; 1938 bool b_patha_ok; 1939 long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, 1940 reg_tmp = 0; 1941 bool is12simular, is13simular, is23simular; 1942 u32 iqk_bb_reg[9] = { 1943 ROFDM0_XARXIQIMBALANCE, 1944 ROFDM0_XBRXIQIMBALANCE, 1945 ROFDM0_ECCATHRESHOLD, 1946 ROFDM0_AGCRSSITABLE, 1947 ROFDM0_XATXIQIMBALANCE, 1948 ROFDM0_XBTXIQIMBALANCE, 1949 ROFDM0_XCTXAFE, 1950 ROFDM0_XDTXAFE, 1951 ROFDM0_RXIQEXTANTA 1952 }; 1953 1954 if (b_recovery) { 1955 _rtl88e_phy_reload_adda_registers(hw, 1956 iqk_bb_reg, 1957 rtlphy->iqk_bb_backup, 9); 1958 return; 1959 } 1960 1961 for (i = 0; i < 8; i++) { 1962 result[0][i] = 0; 1963 result[1][i] = 0; 1964 result[2][i] = 0; 1965 result[3][i] = 0; 1966 } 1967 final_candidate = 0xff; 1968 b_patha_ok = false; 1969 is12simular = false; 1970 is23simular = false; 1971 is13simular = false; 1972 for (i = 0; i < 3; i++) { 1973 if (get_rf_type(rtlphy) == RF_2T2R) 1974 _rtl88e_phy_iq_calibrate(hw, result, i, true); 1975 else 1976 _rtl88e_phy_iq_calibrate(hw, result, i, false); 1977 if (i == 1) { 1978 is12simular = 1979 _rtl88e_phy_simularity_compare(hw, result, 0, 1); 1980 if (is12simular) { 1981 final_candidate = 0; 1982 break; 1983 } 1984 } 1985 if (i == 2) { 1986 is13simular = 1987 _rtl88e_phy_simularity_compare(hw, result, 0, 2); 1988 if (is13simular) { 1989 final_candidate = 0; 1990 break; 1991 } 1992 is23simular = 1993 _rtl88e_phy_simularity_compare(hw, result, 1, 2); 1994 if (is23simular) { 1995 final_candidate = 1; 1996 } else { 1997 for (i = 0; i < 8; i++) 1998 reg_tmp += result[3][i]; 1999 2000 if (reg_tmp != 0) 2001 final_candidate = 3; 2002 else 2003 final_candidate = 0xFF; 2004 } 2005 } 2006 } 2007 for (i = 0; i < 4; i++) { 2008 reg_e94 = result[i][0]; 2009 reg_e9c = result[i][1]; 2010 reg_ea4 = result[i][2]; 2011 reg_eb4 = result[i][4]; 2012 reg_ebc = result[i][5]; 2013 } 2014 if (final_candidate != 0xff) { 2015 reg_e94 = result[final_candidate][0]; 2016 reg_e9c = result[final_candidate][1]; 2017 reg_ea4 = result[final_candidate][2]; 2018 reg_eb4 = result[final_candidate][4]; 2019 reg_ebc = result[final_candidate][5]; 2020 rtlphy->reg_eb4 = reg_eb4; 2021 rtlphy->reg_ebc = reg_ebc; 2022 rtlphy->reg_e94 = reg_e94; 2023 rtlphy->reg_e9c = reg_e9c; 2024 b_patha_ok = true; 2025 } else { 2026 rtlphy->reg_e94 = 0x100; 2027 rtlphy->reg_eb4 = 0x100; 2028 rtlphy->reg_e9c = 0x0; 2029 rtlphy->reg_ebc = 0x0; 2030 } 2031 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */ 2032 _rtl88e_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result, 2033 final_candidate, 2034 (reg_ea4 == 0)); 2035 if (final_candidate != 0xFF) { 2036 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) 2037 rtlphy->iqk_matrix[0].value[0][i] = 2038 result[final_candidate][i]; 2039 rtlphy->iqk_matrix[0].iqk_done = true; 2040 2041 } 2042 _rtl88e_phy_save_adda_registers(hw, iqk_bb_reg, 2043 rtlphy->iqk_bb_backup, 9); 2044 } 2045 2046 void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw) 2047 { 2048 struct rtl_priv *rtlpriv = rtl_priv(hw); 2049 struct rtl_phy *rtlphy = &rtlpriv->phy; 2050 struct rtl_hal *rtlhal = &rtlpriv->rtlhal; 2051 u32 timeout = 2000, timecount = 0; 2052 2053 while (rtlpriv->mac80211.act_scanning && timecount < timeout) { 2054 udelay(50); 2055 timecount += 50; 2056 } 2057 2058 rtlphy->lck_inprogress = true; 2059 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2060 "LCK:Start!!! currentband %x delay %d ms\n", 2061 rtlhal->current_bandtype, timecount); 2062 2063 _rtl88e_phy_lc_calibrate(hw, false); 2064 2065 rtlphy->lck_inprogress = false; 2066 } 2067 2068 void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain) 2069 { 2070 _rtl88e_phy_set_rfpath_switch(hw, bmain, false); 2071 } 2072 2073 bool rtl88e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) 2074 { 2075 struct rtl_priv *rtlpriv = rtl_priv(hw); 2076 struct rtl_phy *rtlphy = &rtlpriv->phy; 2077 bool postprocessing = false; 2078 2079 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2080 "-->IO Cmd(%#x), set_io_inprogress(%d)\n", 2081 iotype, rtlphy->set_io_inprogress); 2082 do { 2083 switch (iotype) { 2084 case IO_CMD_RESUME_DM_BY_SCAN: 2085 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2086 "[IO CMD] Resume DM after scan.\n"); 2087 postprocessing = true; 2088 break; 2089 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN: 2090 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2091 "[IO CMD] Pause DM before scan.\n"); 2092 postprocessing = true; 2093 break; 2094 default: 2095 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 2096 "switch case %#x not processed\n", iotype); 2097 break; 2098 } 2099 } while (false); 2100 if (postprocessing && !rtlphy->set_io_inprogress) { 2101 rtlphy->set_io_inprogress = true; 2102 rtlphy->current_io_type = iotype; 2103 } else { 2104 return false; 2105 } 2106 rtl88e_phy_set_io(hw); 2107 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype); 2108 return true; 2109 } 2110 2111 static void rtl88e_phy_set_io(struct ieee80211_hw *hw) 2112 { 2113 struct rtl_priv *rtlpriv = rtl_priv(hw); 2114 struct rtl_phy *rtlphy = &rtlpriv->phy; 2115 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 2116 2117 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2118 "--->Cmd(%#x), set_io_inprogress(%d)\n", 2119 rtlphy->current_io_type, rtlphy->set_io_inprogress); 2120 switch (rtlphy->current_io_type) { 2121 case IO_CMD_RESUME_DM_BY_SCAN: 2122 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; 2123 /*rtl92c_dm_write_dig(hw);*/ 2124 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel); 2125 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83); 2126 break; 2127 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN: 2128 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue; 2129 dm_digtable->cur_igvalue = 0x17; 2130 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40); 2131 break; 2132 default: 2133 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 2134 "switch case %#x not processed\n", 2135 rtlphy->current_io_type); 2136 break; 2137 } 2138 rtlphy->set_io_inprogress = false; 2139 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2140 "(%#x)\n", rtlphy->current_io_type); 2141 } 2142 2143 static void rtl88ee_phy_set_rf_on(struct ieee80211_hw *hw) 2144 { 2145 struct rtl_priv *rtlpriv = rtl_priv(hw); 2146 2147 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 2148 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 2149 /*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);*/ 2150 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 2151 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 2152 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 2153 } 2154 2155 static void _rtl88ee_phy_set_rf_sleep(struct ieee80211_hw *hw) 2156 { 2157 struct rtl_priv *rtlpriv = rtl_priv(hw); 2158 2159 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 2160 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 2161 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 2162 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); 2163 } 2164 2165 static bool _rtl88ee_phy_set_rf_power_state(struct ieee80211_hw *hw, 2166 enum rf_pwrstate rfpwr_state) 2167 { 2168 struct rtl_priv *rtlpriv = rtl_priv(hw); 2169 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2170 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2171 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2172 bool bresult = true; 2173 u8 i, queue_id; 2174 struct rtl8192_tx_ring *ring = NULL; 2175 2176 switch (rfpwr_state) { 2177 case ERFON: 2178 if ((ppsc->rfpwr_state == ERFOFF) && 2179 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 2180 bool rtstatus; 2181 u32 initializecount = 0; 2182 2183 do { 2184 initializecount++; 2185 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2186 "IPS Set eRf nic enable\n"); 2187 rtstatus = rtl_ps_enable_nic(hw); 2188 } while (!rtstatus && 2189 (initializecount < 10)); 2190 RT_CLEAR_PS_LEVEL(ppsc, 2191 RT_RF_OFF_LEVL_HALT_NIC); 2192 } else { 2193 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2194 "Set ERFON sleeped:%d ms\n", 2195 jiffies_to_msecs(jiffies - 2196 ppsc-> 2197 last_sleep_jiffies)); 2198 ppsc->last_awake_jiffies = jiffies; 2199 rtl88ee_phy_set_rf_on(hw); 2200 } 2201 if (mac->link_state == MAC80211_LINKED) { 2202 rtlpriv->cfg->ops->led_control(hw, 2203 LED_CTL_LINK); 2204 } else { 2205 rtlpriv->cfg->ops->led_control(hw, 2206 LED_CTL_NO_LINK); 2207 } 2208 break; 2209 case ERFOFF: 2210 for (queue_id = 0, i = 0; 2211 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 2212 ring = &pcipriv->dev.tx_ring[queue_id]; 2213 if (queue_id == BEACON_QUEUE || 2214 skb_queue_len(&ring->queue) == 0) { 2215 queue_id++; 2216 continue; 2217 } else { 2218 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2219 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n", 2220 (i + 1), queue_id, 2221 skb_queue_len(&ring->queue)); 2222 2223 udelay(10); 2224 i++; 2225 } 2226 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 2227 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2228 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n", 2229 MAX_DOZE_WAITING_TIMES_9x, 2230 queue_id, 2231 skb_queue_len(&ring->queue)); 2232 break; 2233 } 2234 } 2235 2236 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { 2237 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2238 "IPS Set eRf nic disable\n"); 2239 rtl_ps_disable_nic(hw); 2240 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2241 } else { 2242 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) { 2243 rtlpriv->cfg->ops->led_control(hw, 2244 LED_CTL_NO_LINK); 2245 } else { 2246 rtlpriv->cfg->ops->led_control(hw, 2247 LED_CTL_POWER_OFF); 2248 } 2249 } 2250 break; 2251 case ERFSLEEP:{ 2252 if (ppsc->rfpwr_state == ERFOFF) 2253 break; 2254 for (queue_id = 0, i = 0; 2255 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 2256 ring = &pcipriv->dev.tx_ring[queue_id]; 2257 if (skb_queue_len(&ring->queue) == 0) { 2258 queue_id++; 2259 continue; 2260 } else { 2261 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2262 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n", 2263 (i + 1), queue_id, 2264 skb_queue_len(&ring->queue)); 2265 2266 udelay(10); 2267 i++; 2268 } 2269 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 2270 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2271 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n", 2272 MAX_DOZE_WAITING_TIMES_9x, 2273 queue_id, 2274 skb_queue_len(&ring->queue)); 2275 break; 2276 } 2277 } 2278 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2279 "Set ERFSLEEP awaked:%d ms\n", 2280 jiffies_to_msecs(jiffies - 2281 ppsc->last_awake_jiffies)); 2282 ppsc->last_sleep_jiffies = jiffies; 2283 _rtl88ee_phy_set_rf_sleep(hw); 2284 break; 2285 } 2286 default: 2287 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 2288 "switch case %#x not processed\n", rfpwr_state); 2289 bresult = false; 2290 break; 2291 } 2292 if (bresult) 2293 ppsc->rfpwr_state = rfpwr_state; 2294 return bresult; 2295 } 2296 2297 bool rtl88e_phy_set_rf_power_state(struct ieee80211_hw *hw, 2298 enum rf_pwrstate rfpwr_state) 2299 { 2300 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2301 2302 bool bresult = false; 2303 2304 if (rfpwr_state == ppsc->rfpwr_state) 2305 return bresult; 2306 bresult = _rtl88ee_phy_set_rf_power_state(hw, rfpwr_state); 2307 return bresult; 2308 } 2309