1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2013 Realtek Corporation.*/ 3 4 #include "../wifi.h" 5 #include "../efuse.h" 6 #include "../base.h" 7 #include "../regd.h" 8 #include "../cam.h" 9 #include "../ps.h" 10 #include "../pci.h" 11 #include "../pwrseqcmd.h" 12 #include "reg.h" 13 #include "def.h" 14 #include "phy.h" 15 #include "dm.h" 16 #include "fw.h" 17 #include "led.h" 18 #include "hw.h" 19 #include "pwrseq.h" 20 21 #define LLT_CONFIG 5 22 23 static void _rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 24 u8 set_bits, u8 clear_bits) 25 { 26 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 27 struct rtl_priv *rtlpriv = rtl_priv(hw); 28 29 rtlpci->reg_bcn_ctrl_val |= set_bits; 30 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 31 32 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); 33 } 34 35 static void _rtl88ee_stop_tx_beacon(struct ieee80211_hw *hw) 36 { 37 struct rtl_priv *rtlpriv = rtl_priv(hw); 38 u8 tmp1byte; 39 40 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 41 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); 42 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 43 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 44 tmp1byte &= ~(BIT(0)); 45 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 46 } 47 48 static void _rtl88ee_resume_tx_beacon(struct ieee80211_hw *hw) 49 { 50 struct rtl_priv *rtlpriv = rtl_priv(hw); 51 u8 tmp1byte; 52 53 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 54 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); 55 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 56 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 57 tmp1byte |= BIT(0); 58 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 59 } 60 61 static void _rtl88ee_enable_bcn_sub_func(struct ieee80211_hw *hw) 62 { 63 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1)); 64 } 65 66 static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw) 67 { 68 struct rtl_priv *rtlpriv = rtl_priv(hw); 69 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 70 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE]; 71 unsigned long flags; 72 73 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 74 while (skb_queue_len(&ring->queue)) { 75 struct rtl_tx_desc *entry = &ring->desc[ring->idx]; 76 struct sk_buff *skb = __skb_dequeue(&ring->queue); 77 78 dma_unmap_single(&rtlpci->pdev->dev, 79 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 80 true, HW_DESC_TXBUFF_ADDR), 81 skb->len, DMA_TO_DEVICE); 82 kfree_skb(skb); 83 ring->idx = (ring->idx + 1) % ring->entries; 84 } 85 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 86 } 87 88 static void _rtl88ee_disable_bcn_sub_func(struct ieee80211_hw *hw) 89 { 90 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0); 91 } 92 93 static void _rtl88ee_set_fw_clock_on(struct ieee80211_hw *hw, 94 u8 rpwm_val, bool b_need_turn_off_ckk) 95 { 96 struct rtl_priv *rtlpriv = rtl_priv(hw); 97 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 98 bool b_support_remote_wake_up; 99 u32 count = 0, isr_regaddr, content; 100 bool schedule_timer = b_need_turn_off_ckk; 101 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 102 (u8 *)(&b_support_remote_wake_up)); 103 104 if (!rtlhal->fw_ready) 105 return; 106 if (!rtlpriv->psc.fw_current_inpsmode) 107 return; 108 109 while (1) { 110 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 111 if (rtlhal->fw_clk_change_in_progress) { 112 while (rtlhal->fw_clk_change_in_progress) { 113 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 114 count++; 115 udelay(100); 116 if (count > 1000) 117 return; 118 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 119 } 120 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 121 } else { 122 rtlhal->fw_clk_change_in_progress = false; 123 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 124 break; 125 } 126 } 127 128 if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) { 129 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val); 130 if (FW_PS_IS_ACK(rpwm_val)) { 131 isr_regaddr = REG_HISR; 132 content = rtl_read_dword(rtlpriv, isr_regaddr); 133 while (!(content & IMR_CPWM) && (count < 500)) { 134 udelay(50); 135 count++; 136 content = rtl_read_dword(rtlpriv, isr_regaddr); 137 } 138 139 if (content & IMR_CPWM) { 140 rtl_write_word(rtlpriv, isr_regaddr, 0x0100); 141 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E; 142 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 143 "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n", 144 rtlhal->fw_ps_state); 145 } 146 } 147 148 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 149 rtlhal->fw_clk_change_in_progress = false; 150 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 151 if (schedule_timer) { 152 mod_timer(&rtlpriv->works.fw_clockoff_timer, 153 jiffies + MSECS(10)); 154 } 155 156 } else { 157 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 158 rtlhal->fw_clk_change_in_progress = false; 159 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 160 } 161 } 162 163 static void _rtl88ee_set_fw_clock_off(struct ieee80211_hw *hw, 164 u8 rpwm_val) 165 { 166 struct rtl_priv *rtlpriv = rtl_priv(hw); 167 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 168 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 169 struct rtl8192_tx_ring *ring; 170 enum rf_pwrstate rtstate; 171 bool schedule_timer = false; 172 u8 queue; 173 174 if (!rtlhal->fw_ready) 175 return; 176 if (!rtlpriv->psc.fw_current_inpsmode) 177 return; 178 if (!rtlhal->allow_sw_to_change_hwclc) 179 return; 180 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate)); 181 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF) 182 return; 183 184 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) { 185 ring = &rtlpci->tx_ring[queue]; 186 if (skb_queue_len(&ring->queue)) { 187 schedule_timer = true; 188 break; 189 } 190 } 191 192 if (schedule_timer) { 193 mod_timer(&rtlpriv->works.fw_clockoff_timer, 194 jiffies + MSECS(10)); 195 return; 196 } 197 198 if (FW_PS_STATE(rtlhal->fw_ps_state) != 199 FW_PS_STATE_RF_OFF_LOW_PWR_88E) { 200 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 201 if (!rtlhal->fw_clk_change_in_progress) { 202 rtlhal->fw_clk_change_in_progress = true; 203 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 204 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val); 205 rtl_write_word(rtlpriv, REG_HISR, 0x0100); 206 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 207 &rpwm_val); 208 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 209 rtlhal->fw_clk_change_in_progress = false; 210 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 211 } else { 212 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 213 mod_timer(&rtlpriv->works.fw_clockoff_timer, 214 jiffies + MSECS(10)); 215 } 216 } 217 } 218 219 static void _rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw *hw) 220 { 221 u8 rpwm_val = 0; 222 223 rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK); 224 _rtl88ee_set_fw_clock_on(hw, rpwm_val, true); 225 } 226 227 static void _rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw) 228 { 229 u8 rpwm_val = 0; 230 rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR_88E; 231 _rtl88ee_set_fw_clock_off(hw, rpwm_val); 232 } 233 234 void rtl88ee_fw_clk_off_timer_callback(struct timer_list *t) 235 { 236 struct rtl_priv *rtlpriv = from_timer(rtlpriv, t, 237 works.fw_clockoff_timer); 238 struct ieee80211_hw *hw = rtlpriv->hw; 239 240 _rtl88ee_set_fw_ps_rf_off_low_power(hw); 241 } 242 243 static void _rtl88ee_fwlps_leave(struct ieee80211_hw *hw) 244 { 245 struct rtl_priv *rtlpriv = rtl_priv(hw); 246 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 247 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 248 bool fw_current_inps = false; 249 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE; 250 251 if (ppsc->low_power_enable) { 252 rpwm_val = (FW_PS_STATE_ALL_ON_88E|FW_PS_ACK);/* RF on */ 253 _rtl88ee_set_fw_clock_on(hw, rpwm_val, false); 254 rtlhal->allow_sw_to_change_hwclc = false; 255 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 256 &fw_pwrmode); 257 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 258 (u8 *)(&fw_current_inps)); 259 } else { 260 rpwm_val = FW_PS_STATE_ALL_ON_88E; /* RF on */ 261 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val); 262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 263 &fw_pwrmode); 264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 265 (u8 *)(&fw_current_inps)); 266 } 267 } 268 269 static void _rtl88ee_fwlps_enter(struct ieee80211_hw *hw) 270 { 271 struct rtl_priv *rtlpriv = rtl_priv(hw); 272 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 273 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 274 bool fw_current_inps = true; 275 u8 rpwm_val; 276 277 if (ppsc->low_power_enable) { 278 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E; /* RF off */ 279 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 280 (u8 *)(&fw_current_inps)); 281 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 282 &ppsc->fwctrl_psmode); 283 rtlhal->allow_sw_to_change_hwclc = true; 284 _rtl88ee_set_fw_clock_off(hw, rpwm_val); 285 } else { 286 rpwm_val = FW_PS_STATE_RF_OFF_88E; /* RF off */ 287 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 288 (u8 *)(&fw_current_inps)); 289 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 290 &ppsc->fwctrl_psmode); 291 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val); 292 } 293 } 294 295 void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 296 { 297 struct rtl_priv *rtlpriv = rtl_priv(hw); 298 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 299 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 300 301 switch (variable) { 302 case HW_VAR_RCR: 303 *((u32 *)(val)) = rtlpci->receive_config; 304 break; 305 case HW_VAR_RF_STATE: 306 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 307 break; 308 case HW_VAR_FWLPS_RF_ON:{ 309 enum rf_pwrstate rfstate; 310 u32 val_rcr; 311 312 rtlpriv->cfg->ops->get_hw_reg(hw, 313 HW_VAR_RF_STATE, 314 (u8 *)(&rfstate)); 315 if (rfstate == ERFOFF) { 316 *((bool *)(val)) = true; 317 } else { 318 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 319 val_rcr &= 0x00070000; 320 if (val_rcr) 321 *((bool *)(val)) = false; 322 else 323 *((bool *)(val)) = true; 324 } 325 break; } 326 case HW_VAR_FW_PSMODE_STATUS: 327 *((bool *)(val)) = ppsc->fw_current_inpsmode; 328 break; 329 case HW_VAR_CORRECT_TSF:{ 330 u64 tsf; 331 u32 *ptsf_low = (u32 *)&tsf; 332 u32 *ptsf_high = ((u32 *)&tsf) + 1; 333 334 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 335 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 336 337 *((u64 *)(val)) = tsf; 338 break; } 339 case HAL_DEF_WOWLAN: 340 break; 341 default: 342 pr_err("switch case %#x not processed\n", variable); 343 break; 344 } 345 } 346 347 void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 348 { 349 struct rtl_priv *rtlpriv = rtl_priv(hw); 350 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 351 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 352 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 353 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 354 u8 idx; 355 356 switch (variable) { 357 case HW_VAR_ETHER_ADDR: 358 for (idx = 0; idx < ETH_ALEN; idx++) { 359 rtl_write_byte(rtlpriv, (REG_MACID + idx), 360 val[idx]); 361 } 362 break; 363 case HW_VAR_BASIC_RATE:{ 364 u16 b_rate_cfg = ((u16 *)val)[0]; 365 u8 rate_index = 0; 366 b_rate_cfg = b_rate_cfg & 0x15f; 367 b_rate_cfg |= 0x01; 368 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff); 369 rtl_write_byte(rtlpriv, REG_RRSR + 1, 370 (b_rate_cfg >> 8) & 0xff); 371 while (b_rate_cfg > 0x1) { 372 b_rate_cfg = (b_rate_cfg >> 1); 373 rate_index++; 374 } 375 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 376 rate_index); 377 break; 378 } 379 case HW_VAR_BSSID: 380 for (idx = 0; idx < ETH_ALEN; idx++) { 381 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 382 val[idx]); 383 } 384 break; 385 case HW_VAR_SIFS: 386 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 387 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); 388 389 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 390 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 391 392 if (!mac->ht_enable) 393 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 394 0x0e0e); 395 else 396 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 397 *((u16 *)val)); 398 break; 399 case HW_VAR_SLOT_TIME:{ 400 u8 e_aci; 401 402 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 403 "HW_VAR_SLOT_TIME %x\n", val[0]); 404 405 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 406 407 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 408 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, 409 &e_aci); 410 } 411 break; 412 } 413 case HW_VAR_ACK_PREAMBLE:{ 414 u8 reg_tmp; 415 u8 short_preamble = (bool)*val; 416 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2); 417 if (short_preamble) { 418 reg_tmp |= 0x02; 419 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 420 2, reg_tmp); 421 } else { 422 reg_tmp |= 0xFD; 423 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 424 2, reg_tmp); 425 } 426 break; } 427 case HW_VAR_WPA_CONFIG: 428 rtl_write_byte(rtlpriv, REG_SECCFG, *val); 429 break; 430 case HW_VAR_AMPDU_MIN_SPACE:{ 431 u8 min_spacing_to_set; 432 u8 sec_min_space; 433 434 min_spacing_to_set = *val; 435 if (min_spacing_to_set <= 7) { 436 sec_min_space = 0; 437 438 if (min_spacing_to_set < sec_min_space) 439 min_spacing_to_set = sec_min_space; 440 441 mac->min_space_cfg = ((mac->min_space_cfg & 442 0xf8) | 443 min_spacing_to_set); 444 445 *val = min_spacing_to_set; 446 447 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 448 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 449 mac->min_space_cfg); 450 451 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 452 mac->min_space_cfg); 453 } 454 break; } 455 case HW_VAR_SHORTGI_DENSITY:{ 456 u8 density_to_set; 457 458 density_to_set = *val; 459 mac->min_space_cfg |= (density_to_set << 3); 460 461 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 462 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 463 mac->min_space_cfg); 464 465 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 466 mac->min_space_cfg); 467 break; 468 } 469 case HW_VAR_AMPDU_FACTOR:{ 470 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 }; 471 u8 factor_toset; 472 u8 *p_regtoset = NULL; 473 u8 index = 0; 474 475 p_regtoset = regtoset_normal; 476 477 factor_toset = *val; 478 if (factor_toset <= 3) { 479 factor_toset = (1 << (factor_toset + 2)); 480 if (factor_toset > 0xf) 481 factor_toset = 0xf; 482 483 for (index = 0; index < 4; index++) { 484 if ((p_regtoset[index] & 0xf0) > 485 (factor_toset << 4)) 486 p_regtoset[index] = 487 (p_regtoset[index] & 0x0f) | 488 (factor_toset << 4); 489 490 if ((p_regtoset[index] & 0x0f) > 491 factor_toset) 492 p_regtoset[index] = 493 (p_regtoset[index] & 0xf0) | 494 (factor_toset); 495 496 rtl_write_byte(rtlpriv, 497 (REG_AGGLEN_LMT + index), 498 p_regtoset[index]); 499 500 } 501 502 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 503 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 504 factor_toset); 505 } 506 break; } 507 case HW_VAR_AC_PARAM:{ 508 u8 e_aci = *val; 509 rtl88e_dm_init_edca_turbo(hw); 510 511 if (rtlpci->acm_method != EACMWAY2_SW) 512 rtlpriv->cfg->ops->set_hw_reg(hw, 513 HW_VAR_ACM_CTRL, 514 &e_aci); 515 break; } 516 case HW_VAR_ACM_CTRL:{ 517 u8 e_aci = *val; 518 union aci_aifsn *p_aci_aifsn = 519 (union aci_aifsn *)(&(mac->ac[0].aifs)); 520 u8 acm = p_aci_aifsn->f.acm; 521 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 522 523 acm_ctrl = acm_ctrl | 524 ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 525 526 if (acm) { 527 switch (e_aci) { 528 case AC0_BE: 529 acm_ctrl |= ACMHW_BEQEN; 530 break; 531 case AC2_VI: 532 acm_ctrl |= ACMHW_VIQEN; 533 break; 534 case AC3_VO: 535 acm_ctrl |= ACMHW_VOQEN; 536 break; 537 default: 538 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 539 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 540 acm); 541 break; 542 } 543 } else { 544 switch (e_aci) { 545 case AC0_BE: 546 acm_ctrl &= (~ACMHW_BEQEN); 547 break; 548 case AC2_VI: 549 acm_ctrl &= (~ACMHW_VIQEN); 550 break; 551 case AC3_VO: 552 acm_ctrl &= (~ACMHW_VOQEN); 553 break; 554 default: 555 pr_err("switch case %#x not processed\n", 556 e_aci); 557 break; 558 } 559 } 560 561 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE, 562 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 563 acm_ctrl); 564 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 565 break; } 566 case HW_VAR_RCR: 567 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); 568 rtlpci->receive_config = ((u32 *)(val))[0]; 569 break; 570 case HW_VAR_RETRY_LIMIT:{ 571 u8 retry_limit = *val; 572 573 rtl_write_word(rtlpriv, REG_RL, 574 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 575 retry_limit << RETRY_LIMIT_LONG_SHIFT); 576 break; } 577 case HW_VAR_DUAL_TSF_RST: 578 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 579 break; 580 case HW_VAR_EFUSE_BYTES: 581 rtlefuse->efuse_usedbytes = *((u16 *)val); 582 break; 583 case HW_VAR_EFUSE_USAGE: 584 rtlefuse->efuse_usedpercentage = *val; 585 break; 586 case HW_VAR_IO_CMD: 587 rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val)); 588 break; 589 case HW_VAR_SET_RPWM:{ 590 u8 rpwm_val; 591 592 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 593 udelay(1); 594 595 if (rpwm_val & BIT(7)) { 596 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val); 597 } else { 598 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7)); 599 } 600 break; } 601 case HW_VAR_H2C_FW_PWRMODE: 602 rtl88e_set_fw_pwrmode_cmd(hw, *val); 603 break; 604 case HW_VAR_FW_PSMODE_STATUS: 605 ppsc->fw_current_inpsmode = *((bool *)val); 606 break; 607 case HW_VAR_RESUME_CLK_ON: 608 _rtl88ee_set_fw_ps_rf_on(hw); 609 break; 610 case HW_VAR_FW_LPS_ACTION:{ 611 bool enter_fwlps = *((bool *)val); 612 613 if (enter_fwlps) 614 _rtl88ee_fwlps_enter(hw); 615 else 616 _rtl88ee_fwlps_leave(hw); 617 618 break; } 619 case HW_VAR_H2C_FW_JOINBSSRPT:{ 620 u8 mstatus = *val; 621 u8 tmp_regcr, tmp_reg422, bcnvalid_reg; 622 u8 count = 0, dlbcn_count = 0; 623 bool b_recover = false; 624 625 if (mstatus == RT_MEDIA_CONNECT) { 626 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, 627 NULL); 628 629 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 630 rtl_write_byte(rtlpriv, REG_CR + 1, 631 (tmp_regcr | BIT(0))); 632 633 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); 634 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0); 635 636 tmp_reg422 = 637 rtl_read_byte(rtlpriv, 638 REG_FWHW_TXQ_CTRL + 2); 639 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 640 tmp_reg422 & (~BIT(6))); 641 if (tmp_reg422 & BIT(6)) 642 b_recover = true; 643 644 do { 645 bcnvalid_reg = rtl_read_byte(rtlpriv, 646 REG_TDECTRL+2); 647 rtl_write_byte(rtlpriv, REG_TDECTRL+2, 648 (bcnvalid_reg | BIT(0))); 649 _rtl88ee_return_beacon_queue_skb(hw); 650 651 rtl88e_set_fw_rsvdpagepkt(hw, 0); 652 bcnvalid_reg = rtl_read_byte(rtlpriv, 653 REG_TDECTRL+2); 654 count = 0; 655 while (!(bcnvalid_reg & BIT(0)) && count < 20) { 656 count++; 657 udelay(10); 658 bcnvalid_reg = 659 rtl_read_byte(rtlpriv, REG_TDECTRL+2); 660 } 661 dlbcn_count++; 662 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); 663 664 if (bcnvalid_reg & BIT(0)) 665 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0)); 666 667 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0); 668 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); 669 670 if (b_recover) { 671 rtl_write_byte(rtlpriv, 672 REG_FWHW_TXQ_CTRL + 2, 673 tmp_reg422); 674 } 675 676 rtl_write_byte(rtlpriv, REG_CR + 1, 677 (tmp_regcr & ~(BIT(0)))); 678 } 679 rtl88e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val)); 680 break; } 681 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: 682 rtl88e_set_p2p_ps_offload_cmd(hw, *val); 683 break; 684 case HW_VAR_AID:{ 685 u16 u2btmp; 686 687 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 688 u2btmp &= 0xC000; 689 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | 690 mac->assoc_id)); 691 break; } 692 case HW_VAR_CORRECT_TSF:{ 693 u8 btype_ibss = *val; 694 695 if (btype_ibss) 696 _rtl88ee_stop_tx_beacon(hw); 697 698 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); 699 700 rtl_write_dword(rtlpriv, REG_TSFTR, 701 (u32)(mac->tsf & 0xffffffff)); 702 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 703 (u32)((mac->tsf >> 32) & 0xffffffff)); 704 705 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0); 706 707 if (btype_ibss) 708 _rtl88ee_resume_tx_beacon(hw); 709 break; } 710 case HW_VAR_KEEP_ALIVE: { 711 u8 array[2]; 712 713 array[0] = 0xff; 714 array[1] = *((u8 *)val); 715 rtl88e_fill_h2c_cmd(hw, H2C_88E_KEEP_ALIVE_CTRL, 716 2, array); 717 break; } 718 default: 719 pr_err("switch case %#x not processed\n", variable); 720 break; 721 } 722 } 723 724 static bool _rtl88ee_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 725 { 726 struct rtl_priv *rtlpriv = rtl_priv(hw); 727 bool status = true; 728 long count = 0; 729 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | 730 _LLT_OP(_LLT_WRITE_ACCESS); 731 732 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 733 734 do { 735 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 736 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 737 break; 738 739 if (count > POLLING_LLT_THRESHOLD) { 740 pr_err("Failed to polling write LLT done at address %d!\n", 741 address); 742 status = false; 743 break; 744 } 745 } while (++count); 746 747 return status; 748 } 749 750 static bool _rtl88ee_llt_table_init(struct ieee80211_hw *hw) 751 { 752 struct rtl_priv *rtlpriv = rtl_priv(hw); 753 unsigned short i; 754 u8 txpktbuf_bndy; 755 u8 maxpage; 756 bool status; 757 758 maxpage = 0xAF; 759 txpktbuf_bndy = 0xAB; 760 761 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x01); 762 rtl_write_dword(rtlpriv, REG_RQPN, 0x80730d29); 763 764 /*0x2600 MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */ 765 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x25FF0000 | txpktbuf_bndy)); 766 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 767 768 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 769 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 770 771 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); 772 rtl_write_byte(rtlpriv, REG_PBP, 0x11); 773 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 774 775 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 776 status = _rtl88ee_llt_write(hw, i, i + 1); 777 if (!status) 778 return status; 779 } 780 781 status = _rtl88ee_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 782 if (!status) 783 return status; 784 785 for (i = txpktbuf_bndy; i < maxpage; i++) { 786 status = _rtl88ee_llt_write(hw, i, (i + 1)); 787 if (!status) 788 return status; 789 } 790 791 status = _rtl88ee_llt_write(hw, maxpage, txpktbuf_bndy); 792 if (!status) 793 return status; 794 795 return true; 796 } 797 798 static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw) 799 { 800 struct rtl_priv *rtlpriv = rtl_priv(hw); 801 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 802 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0; 803 804 if (rtlpriv->rtlhal.up_first_time) 805 return; 806 807 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 808 rtl88ee_sw_led_on(hw, pled0); 809 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 810 rtl88ee_sw_led_on(hw, pled0); 811 else 812 rtl88ee_sw_led_off(hw, pled0); 813 } 814 815 static bool _rtl88ee_init_mac(struct ieee80211_hw *hw) 816 { 817 struct rtl_priv *rtlpriv = rtl_priv(hw); 818 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 819 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 820 821 u8 bytetmp; 822 u16 wordtmp; 823 824 /*Disable XTAL OUTPUT for power saving. YJ,add,111206. */ 825 bytetmp = rtl_read_byte(rtlpriv, REG_XCK_OUT_CTRL) & (~BIT(0)); 826 rtl_write_byte(rtlpriv, REG_XCK_OUT_CTRL, bytetmp); 827 /*Auto Power Down to CHIP-off State*/ 828 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7)); 829 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); 830 831 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 832 /* HW Power on sequence */ 833 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, 834 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 835 RTL8188EE_NIC_ENABLE_FLOW)) { 836 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 837 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n"); 838 return false; 839 } 840 841 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4); 842 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp); 843 844 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2); 845 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp|BIT(2)); 846 847 bytetmp = rtl_read_byte(rtlpriv, REG_WATCH_DOG+1); 848 rtl_write_byte(rtlpriv, REG_WATCH_DOG+1, bytetmp|BIT(7)); 849 850 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1); 851 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1, bytetmp|BIT(1)); 852 853 bytetmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL); 854 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, bytetmp|BIT(1)|BIT(0)); 855 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL+1, 2); 856 rtl_write_word(rtlpriv, REG_TX_RPT_TIME, 0xcdf0); 857 858 /*Add for wake up online*/ 859 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR); 860 861 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp|BIT(3)); 862 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG+1); 863 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+1, (bytetmp & (~BIT(4)))); 864 rtl_write_byte(rtlpriv, 0x367, 0x80); 865 866 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 867 rtl_write_byte(rtlpriv, REG_CR+1, 0x06); 868 rtl_write_byte(rtlpriv, MSR, 0x00); 869 870 if (!rtlhal->mac_func_enable) { 871 if (!_rtl88ee_llt_table_init(hw)) { 872 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 873 "LLT table init fail\n"); 874 return false; 875 } 876 } 877 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 878 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff); 879 880 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 881 wordtmp &= 0xf; 882 wordtmp |= 0xE771; 883 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 884 885 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 886 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff); 887 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); 888 889 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 890 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) & 891 DMA_BIT_MASK(32)); 892 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 893 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma & 894 DMA_BIT_MASK(32)); 895 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 896 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 897 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 898 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 899 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 900 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 901 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 902 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 903 rtl_write_dword(rtlpriv, REG_HQ_DESA, 904 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma & 905 DMA_BIT_MASK(32)); 906 rtl_write_dword(rtlpriv, REG_RX_DESA, 907 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma & 908 DMA_BIT_MASK(32)); 909 910 /* if we want to support 64 bit DMA, we should set it here, 911 * but now we do not support 64 bit DMA 912 */ 913 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 914 915 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); 916 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0);/*Enable RX DMA */ 917 918 if (rtlhal->earlymode_enable) {/*Early mode enable*/ 919 bytetmp = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL); 920 bytetmp |= 0x1f; 921 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, bytetmp); 922 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL+3, 0x81); 923 } 924 _rtl88ee_gen_refresh_led_state(hw); 925 return true; 926 } 927 928 static void _rtl88ee_hw_configure(struct ieee80211_hw *hw) 929 { 930 struct rtl_priv *rtlpriv = rtl_priv(hw); 931 u32 reg_prsr; 932 933 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 934 935 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr); 936 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 937 } 938 939 static void _rtl88ee_enable_aspm_back_door(struct ieee80211_hw *hw) 940 { 941 struct rtl_priv *rtlpriv = rtl_priv(hw); 942 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 943 u8 tmp1byte = 0; 944 u32 tmp4byte = 0, count = 0; 945 946 rtl_write_word(rtlpriv, 0x354, 0x8104); 947 rtl_write_word(rtlpriv, 0x358, 0x24); 948 949 rtl_write_word(rtlpriv, 0x350, 0x70c); 950 rtl_write_byte(rtlpriv, 0x352, 0x2); 951 tmp1byte = rtl_read_byte(rtlpriv, 0x352); 952 count = 0; 953 while (tmp1byte && count < 20) { 954 udelay(10); 955 tmp1byte = rtl_read_byte(rtlpriv, 0x352); 956 count++; 957 } 958 if (0 == tmp1byte) { 959 tmp4byte = rtl_read_dword(rtlpriv, 0x34c); 960 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(31)); 961 rtl_write_word(rtlpriv, 0x350, 0xf70c); 962 rtl_write_byte(rtlpriv, 0x352, 0x1); 963 } 964 965 tmp1byte = rtl_read_byte(rtlpriv, 0x352); 966 count = 0; 967 while (tmp1byte && count < 20) { 968 udelay(10); 969 tmp1byte = rtl_read_byte(rtlpriv, 0x352); 970 count++; 971 } 972 973 rtl_write_word(rtlpriv, 0x350, 0x718); 974 rtl_write_byte(rtlpriv, 0x352, 0x2); 975 tmp1byte = rtl_read_byte(rtlpriv, 0x352); 976 count = 0; 977 while (tmp1byte && count < 20) { 978 udelay(10); 979 tmp1byte = rtl_read_byte(rtlpriv, 0x352); 980 count++; 981 } 982 983 if (ppsc->support_backdoor || (0 == tmp1byte)) { 984 tmp4byte = rtl_read_dword(rtlpriv, 0x34c); 985 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(11)|BIT(12)); 986 rtl_write_word(rtlpriv, 0x350, 0xf718); 987 rtl_write_byte(rtlpriv, 0x352, 0x1); 988 } 989 990 tmp1byte = rtl_read_byte(rtlpriv, 0x352); 991 count = 0; 992 while (tmp1byte && count < 20) { 993 udelay(10); 994 tmp1byte = rtl_read_byte(rtlpriv, 0x352); 995 count++; 996 } 997 } 998 999 void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw) 1000 { 1001 struct rtl_priv *rtlpriv = rtl_priv(hw); 1002 u8 sec_reg_value; 1003 1004 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1005 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 1006 rtlpriv->sec.pairwise_enc_algorithm, 1007 rtlpriv->sec.group_enc_algorithm); 1008 1009 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 1010 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 1011 "not open hw encryption\n"); 1012 return; 1013 } 1014 1015 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE; 1016 1017 if (rtlpriv->sec.use_defaultkey) { 1018 sec_reg_value |= SCR_TXUSEDK; 1019 sec_reg_value |= SCR_RXUSEDK; 1020 } 1021 1022 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 1023 1024 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 1025 1026 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 1027 "The SECR-value %x\n", sec_reg_value); 1028 1029 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 1030 } 1031 1032 int rtl88ee_hw_init(struct ieee80211_hw *hw) 1033 { 1034 struct rtl_priv *rtlpriv = rtl_priv(hw); 1035 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1036 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1037 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1038 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1039 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1040 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1041 bool rtstatus; 1042 int err = 0; 1043 u8 tmp_u1b, u1byte; 1044 unsigned long flags; 1045 1046 rtlpriv->rtlhal.being_init_adapter = true; 1047 /* As this function can take a very long time (up to 350 ms) 1048 * and can be called with irqs disabled, reenable the irqs 1049 * to let the other devices continue being serviced. 1050 * 1051 * It is safe doing so since our own interrupts will only be enabled 1052 * in a subsequent step. 1053 */ 1054 local_save_flags(flags); 1055 local_irq_enable(); 1056 rtlhal->fw_ready = false; 1057 1058 rtlpriv->intf_ops->disable_aspm(hw); 1059 1060 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1); 1061 u1byte = rtl_read_byte(rtlpriv, REG_CR); 1062 if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) { 1063 rtlhal->mac_func_enable = true; 1064 } else { 1065 rtlhal->mac_func_enable = false; 1066 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E; 1067 } 1068 1069 rtstatus = _rtl88ee_init_mac(hw); 1070 if (!rtstatus) { 1071 pr_info("Init MAC failed\n"); 1072 err = 1; 1073 goto exit; 1074 } 1075 1076 err = rtl88e_download_fw(hw, false); 1077 if (err) { 1078 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1079 "Failed to download FW. Init HW without FW now..\n"); 1080 err = 1; 1081 goto exit; 1082 } 1083 rtlhal->fw_ready = true; 1084 /*fw related variable initialize */ 1085 rtlhal->last_hmeboxnum = 0; 1086 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E; 1087 rtlhal->fw_clk_change_in_progress = false; 1088 rtlhal->allow_sw_to_change_hwclc = false; 1089 ppsc->fw_current_inpsmode = false; 1090 1091 rtl88e_phy_mac_config(hw); 1092 /* because last function modify RCR, so we update 1093 * rcr var here, or TP will unstable for receive_config 1094 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx 1095 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 1096 */ 1097 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 1098 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 1099 1100 rtl88e_phy_bb_config(hw); 1101 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1102 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1103 1104 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 1105 rtl88e_phy_rf_config(hw); 1106 1107 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 1108 RF_CHNLBW, RFREG_OFFSET_MASK); 1109 rtlphy->rfreg_chnlval[0] = rtlphy->rfreg_chnlval[0] & 0xfff00fff; 1110 1111 _rtl88ee_hw_configure(hw); 1112 rtl_cam_reset_all_entry(hw); 1113 rtl88ee_enable_hw_security_config(hw); 1114 1115 rtlhal->mac_func_enable = true; 1116 ppsc->rfpwr_state = ERFON; 1117 1118 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1119 _rtl88ee_enable_aspm_back_door(hw); 1120 rtlpriv->intf_ops->enable_aspm(hw); 1121 1122 if (ppsc->rfpwr_state == ERFON) { 1123 if ((rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) || 1124 ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) && 1125 (rtlhal->oem_id == RT_CID_819X_HP))) { 1126 rtl88e_phy_set_rfpath_switch(hw, true); 1127 rtlpriv->dm.fat_table.rx_idle_ant = MAIN_ANT; 1128 } else { 1129 rtl88e_phy_set_rfpath_switch(hw, false); 1130 rtlpriv->dm.fat_table.rx_idle_ant = AUX_ANT; 1131 } 1132 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "rx idle ant %s\n", 1133 (rtlpriv->dm.fat_table.rx_idle_ant == MAIN_ANT) ? 1134 ("MAIN_ANT") : ("AUX_ANT")); 1135 1136 if (rtlphy->iqk_initialized) { 1137 rtl88e_phy_iq_calibrate(hw, true); 1138 } else { 1139 rtl88e_phy_iq_calibrate(hw, false); 1140 rtlphy->iqk_initialized = true; 1141 } 1142 1143 rtl88e_dm_check_txpower_tracking(hw); 1144 rtl88e_phy_lc_calibrate(hw); 1145 } 1146 1147 tmp_u1b = efuse_read_1byte(hw, 0x1FA); 1148 if (!(tmp_u1b & BIT(0))) { 1149 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); 1150 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n"); 1151 } 1152 1153 if (!(tmp_u1b & BIT(4))) { 1154 tmp_u1b = rtl_read_byte(rtlpriv, 0x16); 1155 tmp_u1b &= 0x0F; 1156 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80); 1157 udelay(10); 1158 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90); 1159 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "under 1.5V\n"); 1160 } 1161 rtl_write_byte(rtlpriv, REG_NAV_CTRL+2, ((30000+127)/128)); 1162 rtl88e_dm_init(hw); 1163 exit: 1164 local_irq_restore(flags); 1165 rtlpriv->rtlhal.being_init_adapter = false; 1166 return err; 1167 } 1168 1169 static enum version_8188e _rtl88ee_read_chip_version(struct ieee80211_hw *hw) 1170 { 1171 struct rtl_priv *rtlpriv = rtl_priv(hw); 1172 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1173 enum version_8188e version = VERSION_UNKNOWN; 1174 u32 value32; 1175 1176 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 1177 if (value32 & TRP_VAUX_EN) { 1178 version = (enum version_8188e) VERSION_TEST_CHIP_88E; 1179 } else { 1180 version = NORMAL_CHIP; 1181 version = version | ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0); 1182 version = version | ((value32 & VENDOR_ID) ? 1183 CHIP_VENDOR_UMC : 0); 1184 } 1185 1186 rtlphy->rf_type = RF_1T1R; 1187 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1188 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ? 1189 "RF_2T2R" : "RF_1T1R"); 1190 1191 return version; 1192 } 1193 1194 static int _rtl88ee_set_media_status(struct ieee80211_hw *hw, 1195 enum nl80211_iftype type) 1196 { 1197 struct rtl_priv *rtlpriv = rtl_priv(hw); 1198 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc; 1199 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1200 u8 mode = MSR_NOLINK; 1201 1202 switch (type) { 1203 case NL80211_IFTYPE_UNSPECIFIED: 1204 mode = MSR_NOLINK; 1205 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1206 "Set Network type to NO LINK!\n"); 1207 break; 1208 case NL80211_IFTYPE_ADHOC: 1209 case NL80211_IFTYPE_MESH_POINT: 1210 mode = MSR_ADHOC; 1211 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1212 "Set Network type to Ad Hoc!\n"); 1213 break; 1214 case NL80211_IFTYPE_STATION: 1215 mode = MSR_INFRA; 1216 ledaction = LED_CTL_LINK; 1217 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1218 "Set Network type to STA!\n"); 1219 break; 1220 case NL80211_IFTYPE_AP: 1221 mode = MSR_AP; 1222 ledaction = LED_CTL_LINK; 1223 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1224 "Set Network type to AP!\n"); 1225 break; 1226 default: 1227 pr_err("Network type %d not support!\n", type); 1228 return 1; 1229 } 1230 1231 /* MSR_INFRA == Link in infrastructure network; 1232 * MSR_ADHOC == Link in ad hoc network; 1233 * Therefore, check link state is necessary. 1234 * 1235 * MSR_AP == AP mode; link state is not cared here. 1236 */ 1237 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) { 1238 mode = MSR_NOLINK; 1239 ledaction = LED_CTL_NO_LINK; 1240 } 1241 1242 if (mode == MSR_NOLINK || mode == MSR_INFRA) { 1243 _rtl88ee_stop_tx_beacon(hw); 1244 _rtl88ee_enable_bcn_sub_func(hw); 1245 } else if (mode == MSR_ADHOC || mode == MSR_AP) { 1246 _rtl88ee_resume_tx_beacon(hw); 1247 _rtl88ee_disable_bcn_sub_func(hw); 1248 } else { 1249 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1250 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", 1251 mode); 1252 } 1253 1254 rtl_write_byte(rtlpriv, MSR, bt_msr | mode); 1255 rtlpriv->cfg->ops->led_control(hw, ledaction); 1256 if (mode == MSR_AP) 1257 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1258 else 1259 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1260 return 0; 1261 } 1262 1263 void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1264 { 1265 struct rtl_priv *rtlpriv = rtl_priv(hw); 1266 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1267 u32 reg_rcr = rtlpci->receive_config; 1268 1269 if (rtlpriv->psc.rfpwr_state != ERFON) 1270 return; 1271 1272 if (check_bssid) { 1273 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1274 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1275 (u8 *)(®_rcr)); 1276 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1277 } else if (!check_bssid) { 1278 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1279 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0); 1280 rtlpriv->cfg->ops->set_hw_reg(hw, 1281 HW_VAR_RCR, (u8 *)(®_rcr)); 1282 } 1283 1284 } 1285 1286 int rtl88ee_set_network_type(struct ieee80211_hw *hw, 1287 enum nl80211_iftype type) 1288 { 1289 struct rtl_priv *rtlpriv = rtl_priv(hw); 1290 1291 if (_rtl88ee_set_media_status(hw, type)) 1292 return -EOPNOTSUPP; 1293 1294 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1295 if (type != NL80211_IFTYPE_AP && 1296 type != NL80211_IFTYPE_MESH_POINT) 1297 rtl88ee_set_check_bssid(hw, true); 1298 } else { 1299 rtl88ee_set_check_bssid(hw, false); 1300 } 1301 1302 return 0; 1303 } 1304 1305 /* don't set REG_EDCA_BE_PARAM here 1306 * because mac80211 will send pkt when scan 1307 */ 1308 void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci) 1309 { 1310 struct rtl_priv *rtlpriv = rtl_priv(hw); 1311 rtl88e_dm_init_edca_turbo(hw); 1312 switch (aci) { 1313 case AC1_BK: 1314 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 1315 break; 1316 case AC0_BE: 1317 break; 1318 case AC2_VI: 1319 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 1320 break; 1321 case AC3_VO: 1322 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); 1323 break; 1324 default: 1325 WARN_ONCE(true, "rtl8188ee: invalid aci: %d !\n", aci); 1326 break; 1327 } 1328 } 1329 1330 void rtl88ee_enable_interrupt(struct ieee80211_hw *hw) 1331 { 1332 struct rtl_priv *rtlpriv = rtl_priv(hw); 1333 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1334 1335 rtl_write_dword(rtlpriv, REG_HIMR, 1336 rtlpci->irq_mask[0] & 0xFFFFFFFF); 1337 rtl_write_dword(rtlpriv, REG_HIMRE, 1338 rtlpci->irq_mask[1] & 0xFFFFFFFF); 1339 rtlpci->irq_enabled = true; 1340 /* there are some C2H CMDs have been sent 1341 * before system interrupt is enabled, e.g., C2H, CPWM. 1342 * So we need to clear all C2H events that FW has notified, 1343 * otherwise FW won't schedule any commands anymore. 1344 */ 1345 rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); 1346 /*enable system interrupt*/ 1347 rtl_write_dword(rtlpriv, REG_HSIMR, 1348 rtlpci->sys_irq_mask & 0xFFFFFFFF); 1349 } 1350 1351 void rtl88ee_disable_interrupt(struct ieee80211_hw *hw) 1352 { 1353 struct rtl_priv *rtlpriv = rtl_priv(hw); 1354 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1355 1356 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED); 1357 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED); 1358 rtlpci->irq_enabled = false; 1359 /*synchronize_irq(rtlpci->pdev->irq);*/ 1360 } 1361 1362 static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw) 1363 { 1364 struct rtl_priv *rtlpriv = rtl_priv(hw); 1365 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1366 u8 u1b_tmp; 1367 u32 count = 0; 1368 rtlhal->mac_func_enable = false; 1369 rtlpriv->intf_ops->enable_aspm(hw); 1370 1371 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n"); 1372 u1b_tmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL); 1373 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, u1b_tmp & (~BIT(1))); 1374 1375 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1376 while (!(u1b_tmp & BIT(1)) && (count++ < 100)) { 1377 udelay(10); 1378 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1379 count++; 1380 } 1381 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF); 1382 1383 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1384 PWR_INTF_PCI_MSK, 1385 RTL8188EE_NIC_LPS_ENTER_FLOW); 1386 1387 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); 1388 1389 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready) 1390 rtl88e_firmware_selfreset(hw); 1391 1392 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1); 1393 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2)))); 1394 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1395 1396 u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL); 1397 rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0)))); 1398 1399 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1400 PWR_INTF_PCI_MSK, RTL8188EE_NIC_DISABLE_FLOW); 1401 1402 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1); 1403 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3)))); 1404 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1); 1405 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3))); 1406 1407 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E); 1408 1409 u1b_tmp = rtl_read_byte(rtlpriv, GPIO_IN); 1410 rtl_write_byte(rtlpriv, GPIO_OUT, u1b_tmp); 1411 rtl_write_byte(rtlpriv, GPIO_IO_SEL, 0x7F); 1412 1413 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); 1414 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL, (u1b_tmp << 4) | u1b_tmp); 1415 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL+1); 1416 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL+1, u1b_tmp | 0x0F); 1417 1418 rtl_write_dword(rtlpriv, REG_GPIO_IO_SEL_2+2, 0x00080808); 1419 } 1420 1421 void rtl88ee_card_disable(struct ieee80211_hw *hw) 1422 { 1423 struct rtl_priv *rtlpriv = rtl_priv(hw); 1424 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1425 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1426 enum nl80211_iftype opmode; 1427 1428 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8188ee card disable\n"); 1429 1430 mac->link_state = MAC80211_NOLINK; 1431 opmode = NL80211_IFTYPE_UNSPECIFIED; 1432 1433 _rtl88ee_set_media_status(hw, opmode); 1434 1435 if (rtlpriv->rtlhal.driver_is_goingto_unload || 1436 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1437 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1438 1439 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1440 _rtl88ee_poweroff_adapter(hw); 1441 1442 /* after power off we should do iqk again */ 1443 rtlpriv->phy.iqk_initialized = false; 1444 } 1445 1446 void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw, 1447 struct rtl_int *intvec) 1448 { 1449 struct rtl_priv *rtlpriv = rtl_priv(hw); 1450 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1451 1452 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 1453 rtl_write_dword(rtlpriv, ISR, intvec->inta); 1454 1455 intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; 1456 rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb); 1457 1458 } 1459 1460 void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw) 1461 { 1462 struct rtl_priv *rtlpriv = rtl_priv(hw); 1463 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1464 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1465 u16 bcn_interval, atim_window; 1466 1467 bcn_interval = mac->beacon_interval; 1468 atim_window = 2; /*FIX MERGE */ 1469 rtl88ee_disable_interrupt(hw); 1470 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1471 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1472 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 1473 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 1474 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 1475 rtl_write_byte(rtlpriv, 0x606, 0x30); 1476 rtlpci->reg_bcn_ctrl_val |= BIT(3); 1477 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); 1478 /*rtl88ee_enable_interrupt(hw);*/ 1479 } 1480 1481 void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw) 1482 { 1483 struct rtl_priv *rtlpriv = rtl_priv(hw); 1484 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1485 u16 bcn_interval = mac->beacon_interval; 1486 1487 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG, 1488 "beacon_interval:%d\n", bcn_interval); 1489 /*rtl88ee_disable_interrupt(hw);*/ 1490 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1491 /*rtl88ee_enable_interrupt(hw);*/ 1492 } 1493 1494 void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw, 1495 u32 add_msr, u32 rm_msr) 1496 { 1497 struct rtl_priv *rtlpriv = rtl_priv(hw); 1498 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1499 1500 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, 1501 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr); 1502 1503 if (add_msr) 1504 rtlpci->irq_mask[0] |= add_msr; 1505 if (rm_msr) 1506 rtlpci->irq_mask[0] &= (~rm_msr); 1507 rtl88ee_disable_interrupt(hw); 1508 rtl88ee_enable_interrupt(hw); 1509 } 1510 1511 static u8 _rtl88e_get_chnl_group(u8 chnl) 1512 { 1513 u8 group = 0; 1514 1515 if (chnl < 3) 1516 group = 0; 1517 else if (chnl < 6) 1518 group = 1; 1519 else if (chnl < 9) 1520 group = 2; 1521 else if (chnl < 12) 1522 group = 3; 1523 else if (chnl < 14) 1524 group = 4; 1525 else if (chnl == 14) 1526 group = 5; 1527 1528 return group; 1529 } 1530 1531 static void set_24g_base(struct txpower_info_2g *pwrinfo24g, u32 rfpath) 1532 { 1533 int group, txcnt; 1534 1535 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 1536 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D; 1537 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D; 1538 } 1539 for (txcnt = 0; txcnt < MAX_TX_COUNT; txcnt++) { 1540 if (txcnt == 0) { 1541 pwrinfo24g->bw20_diff[rfpath][0] = 0x02; 1542 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04; 1543 } else { 1544 pwrinfo24g->bw20_diff[rfpath][txcnt] = 0xFE; 1545 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE; 1546 pwrinfo24g->cck_diff[rfpath][txcnt] = 0xFE; 1547 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE; 1548 } 1549 } 1550 } 1551 1552 static void read_power_value_fromprom(struct ieee80211_hw *hw, 1553 struct txpower_info_2g *pwrinfo24g, 1554 struct txpower_info_5g *pwrinfo5g, 1555 bool autoload_fail, u8 *hwinfo) 1556 { 1557 struct rtl_priv *rtlpriv = rtl_priv(hw); 1558 u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcnt = 0; 1559 1560 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1561 "hal_ReadPowerValueFromPROM88E():PROMContent[0x%x]=0x%x\n", 1562 (eeaddr + 1), hwinfo[eeaddr + 1]); 1563 if (0xFF == hwinfo[eeaddr+1]) /*YJ,add,120316*/ 1564 autoload_fail = true; 1565 1566 if (autoload_fail) { 1567 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1568 "auto load fail : Use Default value!\n"); 1569 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) { 1570 /* 2.4G default value */ 1571 set_24g_base(pwrinfo24g, rfpath); 1572 } 1573 return; 1574 } 1575 1576 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) { 1577 /*2.4G default value*/ 1578 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 1579 pwrinfo24g->index_cck_base[rfpath][group] = 1580 hwinfo[eeaddr++]; 1581 if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF) 1582 pwrinfo24g->index_cck_base[rfpath][group] = 1583 0x2D; 1584 } 1585 for (group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++) { 1586 pwrinfo24g->index_bw40_base[rfpath][group] = 1587 hwinfo[eeaddr++]; 1588 if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF) 1589 pwrinfo24g->index_bw40_base[rfpath][group] = 1590 0x2D; 1591 } 1592 pwrinfo24g->bw40_diff[rfpath][0] = 0; 1593 if (hwinfo[eeaddr] == 0xFF) { 1594 pwrinfo24g->bw20_diff[rfpath][0] = 0x02; 1595 } else { 1596 pwrinfo24g->bw20_diff[rfpath][0] = 1597 (hwinfo[eeaddr]&0xf0)>>4; 1598 /*bit sign number to 8 bit sign number*/ 1599 if (pwrinfo24g->bw20_diff[rfpath][0] & BIT(3)) 1600 pwrinfo24g->bw20_diff[rfpath][0] |= 0xF0; 1601 } 1602 1603 if (hwinfo[eeaddr] == 0xFF) { 1604 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04; 1605 } else { 1606 pwrinfo24g->ofdm_diff[rfpath][0] = 1607 (hwinfo[eeaddr]&0x0f); 1608 /*bit sign number to 8 bit sign number*/ 1609 if (pwrinfo24g->ofdm_diff[rfpath][0] & BIT(3)) 1610 pwrinfo24g->ofdm_diff[rfpath][0] |= 0xF0; 1611 } 1612 pwrinfo24g->cck_diff[rfpath][0] = 0; 1613 eeaddr++; 1614 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) { 1615 if (hwinfo[eeaddr] == 0xFF) { 1616 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE; 1617 } else { 1618 pwrinfo24g->bw40_diff[rfpath][txcnt] = 1619 (hwinfo[eeaddr]&0xf0)>>4; 1620 if (pwrinfo24g->bw40_diff[rfpath][txcnt] & 1621 BIT(3)) 1622 pwrinfo24g->bw40_diff[rfpath][txcnt] |= 1623 0xF0; 1624 } 1625 1626 if (hwinfo[eeaddr] == 0xFF) { 1627 pwrinfo24g->bw20_diff[rfpath][txcnt] = 1628 0xFE; 1629 } else { 1630 pwrinfo24g->bw20_diff[rfpath][txcnt] = 1631 (hwinfo[eeaddr]&0x0f); 1632 if (pwrinfo24g->bw20_diff[rfpath][txcnt] & 1633 BIT(3)) 1634 pwrinfo24g->bw20_diff[rfpath][txcnt] |= 1635 0xF0; 1636 } 1637 eeaddr++; 1638 1639 if (hwinfo[eeaddr] == 0xFF) { 1640 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE; 1641 } else { 1642 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 1643 (hwinfo[eeaddr]&0xf0)>>4; 1644 if (pwrinfo24g->ofdm_diff[rfpath][txcnt] & 1645 BIT(3)) 1646 pwrinfo24g->ofdm_diff[rfpath][txcnt] |= 1647 0xF0; 1648 } 1649 1650 if (hwinfo[eeaddr] == 0xFF) { 1651 pwrinfo24g->cck_diff[rfpath][txcnt] = 0xFE; 1652 } else { 1653 pwrinfo24g->cck_diff[rfpath][txcnt] = 1654 (hwinfo[eeaddr]&0x0f); 1655 if (pwrinfo24g->cck_diff[rfpath][txcnt] & 1656 BIT(3)) 1657 pwrinfo24g->cck_diff[rfpath][txcnt] |= 1658 0xF0; 1659 } 1660 eeaddr++; 1661 } 1662 1663 /*5G default value*/ 1664 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) { 1665 pwrinfo5g->index_bw40_base[rfpath][group] = 1666 hwinfo[eeaddr++]; 1667 if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF) 1668 pwrinfo5g->index_bw40_base[rfpath][group] = 1669 0xFE; 1670 } 1671 1672 pwrinfo5g->bw40_diff[rfpath][0] = 0; 1673 1674 if (hwinfo[eeaddr] == 0xFF) { 1675 pwrinfo5g->bw20_diff[rfpath][0] = 0; 1676 } else { 1677 pwrinfo5g->bw20_diff[rfpath][0] = 1678 (hwinfo[eeaddr]&0xf0)>>4; 1679 if (pwrinfo5g->bw20_diff[rfpath][0] & BIT(3)) 1680 pwrinfo5g->bw20_diff[rfpath][0] |= 0xF0; 1681 } 1682 1683 if (hwinfo[eeaddr] == 0xFF) { 1684 pwrinfo5g->ofdm_diff[rfpath][0] = 0x04; 1685 } else { 1686 pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr]&0x0f); 1687 if (pwrinfo5g->ofdm_diff[rfpath][0] & BIT(3)) 1688 pwrinfo5g->ofdm_diff[rfpath][0] |= 0xF0; 1689 } 1690 eeaddr++; 1691 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) { 1692 if (hwinfo[eeaddr] == 0xFF) { 1693 pwrinfo5g->bw40_diff[rfpath][txcnt] = 0xFE; 1694 } else { 1695 pwrinfo5g->bw40_diff[rfpath][txcnt] = 1696 (hwinfo[eeaddr]&0xf0)>>4; 1697 if (pwrinfo5g->bw40_diff[rfpath][txcnt] & 1698 BIT(3)) 1699 pwrinfo5g->bw40_diff[rfpath][txcnt] |= 1700 0xF0; 1701 } 1702 1703 if (hwinfo[eeaddr] == 0xFF) { 1704 pwrinfo5g->bw20_diff[rfpath][txcnt] = 0xFE; 1705 } else { 1706 pwrinfo5g->bw20_diff[rfpath][txcnt] = 1707 (hwinfo[eeaddr]&0x0f); 1708 if (pwrinfo5g->bw20_diff[rfpath][txcnt] & 1709 BIT(3)) 1710 pwrinfo5g->bw20_diff[rfpath][txcnt] |= 1711 0xF0; 1712 } 1713 eeaddr++; 1714 } 1715 1716 if (hwinfo[eeaddr] == 0xFF) { 1717 pwrinfo5g->ofdm_diff[rfpath][1] = 0xFE; 1718 pwrinfo5g->ofdm_diff[rfpath][2] = 0xFE; 1719 } else { 1720 pwrinfo5g->ofdm_diff[rfpath][1] = 1721 (hwinfo[eeaddr]&0xf0)>>4; 1722 pwrinfo5g->ofdm_diff[rfpath][2] = 1723 (hwinfo[eeaddr]&0x0f); 1724 } 1725 eeaddr++; 1726 1727 if (hwinfo[eeaddr] == 0xFF) 1728 pwrinfo5g->ofdm_diff[rfpath][3] = 0xFE; 1729 else 1730 pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr]&0x0f); 1731 eeaddr++; 1732 1733 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) { 1734 if (pwrinfo5g->ofdm_diff[rfpath][txcnt] == 0xFF) 1735 pwrinfo5g->ofdm_diff[rfpath][txcnt] = 0xFE; 1736 else if (pwrinfo5g->ofdm_diff[rfpath][txcnt] & BIT(3)) 1737 pwrinfo5g->ofdm_diff[rfpath][txcnt] |= 0xF0; 1738 } 1739 } 1740 } 1741 1742 static void _rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 1743 bool autoload_fail, 1744 u8 *hwinfo) 1745 { 1746 struct rtl_priv *rtlpriv = rtl_priv(hw); 1747 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1748 struct txpower_info_2g pwrinfo24g; 1749 struct txpower_info_5g pwrinfo5g; 1750 u8 rf_path, index; 1751 u8 i; 1752 1753 read_power_value_fromprom(hw, &pwrinfo24g, 1754 &pwrinfo5g, autoload_fail, hwinfo); 1755 1756 for (rf_path = 0; rf_path < 2; rf_path++) { 1757 for (i = 0; i < 14; i++) { 1758 index = _rtl88e_get_chnl_group(i+1); 1759 1760 rtlefuse->txpwrlevel_cck[rf_path][i] = 1761 pwrinfo24g.index_cck_base[rf_path][index]; 1762 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 1763 pwrinfo24g.index_bw40_base[rf_path][index]; 1764 rtlefuse->txpwr_ht20diff[rf_path][i] = 1765 pwrinfo24g.bw20_diff[rf_path][0]; 1766 rtlefuse->txpwr_legacyhtdiff[rf_path][i] = 1767 pwrinfo24g.ofdm_diff[rf_path][0]; 1768 } 1769 1770 for (i = 0; i < 14; i++) { 1771 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1772 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n", 1773 rf_path, i, 1774 rtlefuse->txpwrlevel_cck[rf_path][i], 1775 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]); 1776 } 1777 } 1778 1779 if (!autoload_fail) 1780 rtlefuse->eeprom_thermalmeter = 1781 hwinfo[EEPROM_THERMAL_METER_88E]; 1782 else 1783 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; 1784 1785 if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) { 1786 rtlefuse->apk_thermalmeterignore = true; 1787 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; 1788 } 1789 1790 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 1791 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1792 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 1793 1794 if (!autoload_fail) { 1795 rtlefuse->eeprom_regulatory = 1796 hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/ 1797 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF) 1798 rtlefuse->eeprom_regulatory = 0; 1799 } else { 1800 rtlefuse->eeprom_regulatory = 0; 1801 } 1802 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1803 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 1804 } 1805 1806 static void _rtl88ee_read_adapter_info(struct ieee80211_hw *hw) 1807 { 1808 struct rtl_priv *rtlpriv = rtl_priv(hw); 1809 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1810 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1811 int params[] = {RTL8188E_EEPROM_ID, EEPROM_VID, EEPROM_DID, 1812 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 1813 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 1814 COUNTRY_CODE_WORLD_WIDE_13}; 1815 u8 *hwinfo; 1816 1817 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 1818 if (!hwinfo) 1819 return; 1820 1821 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 1822 goto exit; 1823 1824 if (rtlefuse->eeprom_oemid == 0xFF) 1825 rtlefuse->eeprom_oemid = 0; 1826 1827 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1828 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid); 1829 /* set channel plan from efuse */ 1830 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan; 1831 /*tx power*/ 1832 _rtl88ee_read_txpower_info_from_hwpg(hw, 1833 rtlefuse->autoload_failflag, 1834 hwinfo); 1835 rtlefuse->txpwr_fromeprom = true; 1836 1837 rtl8188ee_read_bt_coexist_info_from_hwpg(hw, 1838 rtlefuse->autoload_failflag, 1839 hwinfo); 1840 1841 /*board type*/ 1842 rtlefuse->board_type = 1843 ((hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0xE0) >> 5); 1844 rtlhal->board_type = rtlefuse->board_type; 1845 /*Wake on wlan*/ 1846 rtlefuse->wowlan_enable = 1847 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0x40) >> 6); 1848 /*parse xtal*/ 1849 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_88E]; 1850 if (hwinfo[EEPROM_XTAL_88E]) 1851 rtlefuse->crystalcap = 0x20; 1852 /*antenna diversity*/ 1853 rtlefuse->antenna_div_cfg = 1854 (hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x18) >> 3; 1855 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF) 1856 rtlefuse->antenna_div_cfg = 0; 1857 if (rtlpriv->btcoexist.eeprom_bt_coexist != 0 && 1858 rtlpriv->btcoexist.eeprom_bt_ant_num == ANT_X1) 1859 rtlefuse->antenna_div_cfg = 0; 1860 1861 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E]; 1862 if (rtlefuse->antenna_div_type == 0xFF) 1863 rtlefuse->antenna_div_type = 0x01; 1864 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV || 1865 rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) 1866 rtlefuse->antenna_div_cfg = 1; 1867 1868 if (rtlhal->oem_id == RT_CID_DEFAULT) { 1869 switch (rtlefuse->eeprom_oemid) { 1870 case EEPROM_CID_DEFAULT: 1871 if (rtlefuse->eeprom_did == 0x8179) { 1872 if (rtlefuse->eeprom_svid == 0x1025) { 1873 rtlhal->oem_id = RT_CID_819X_ACER; 1874 } else if ((rtlefuse->eeprom_svid == 0x10EC && 1875 rtlefuse->eeprom_smid == 0x0179) || 1876 (rtlefuse->eeprom_svid == 0x17AA && 1877 rtlefuse->eeprom_smid == 0x0179)) { 1878 rtlhal->oem_id = RT_CID_819X_LENOVO; 1879 } else if (rtlefuse->eeprom_svid == 0x103c && 1880 rtlefuse->eeprom_smid == 0x197d) { 1881 rtlhal->oem_id = RT_CID_819X_HP; 1882 } else { 1883 rtlhal->oem_id = RT_CID_DEFAULT; 1884 } 1885 } else { 1886 rtlhal->oem_id = RT_CID_DEFAULT; 1887 } 1888 break; 1889 case EEPROM_CID_TOSHIBA: 1890 rtlhal->oem_id = RT_CID_TOSHIBA; 1891 break; 1892 case EEPROM_CID_QMI: 1893 rtlhal->oem_id = RT_CID_819X_QMI; 1894 break; 1895 case EEPROM_CID_WHQL: 1896 default: 1897 rtlhal->oem_id = RT_CID_DEFAULT; 1898 break; 1899 1900 } 1901 } 1902 exit: 1903 kfree(hwinfo); 1904 } 1905 1906 static void _rtl88ee_hal_customized_behavior(struct ieee80211_hw *hw) 1907 { 1908 struct rtl_priv *rtlpriv = rtl_priv(hw); 1909 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1910 1911 rtlpriv->ledctl.led_opendrain = true; 1912 1913 switch (rtlhal->oem_id) { 1914 case RT_CID_819X_HP: 1915 rtlpriv->ledctl.led_opendrain = true; 1916 break; 1917 case RT_CID_819X_LENOVO: 1918 case RT_CID_DEFAULT: 1919 case RT_CID_TOSHIBA: 1920 case RT_CID_CCX: 1921 case RT_CID_819X_ACER: 1922 case RT_CID_WHQL: 1923 default: 1924 break; 1925 } 1926 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1927 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 1928 } 1929 1930 void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw) 1931 { 1932 struct rtl_priv *rtlpriv = rtl_priv(hw); 1933 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1934 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1935 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1936 u8 tmp_u1b; 1937 1938 rtlhal->version = _rtl88ee_read_chip_version(hw); 1939 if (get_rf_type(rtlphy) == RF_1T1R) 1940 rtlpriv->dm.rfpath_rxenable[0] = true; 1941 else 1942 rtlpriv->dm.rfpath_rxenable[0] = 1943 rtlpriv->dm.rfpath_rxenable[1] = true; 1944 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 1945 rtlhal->version); 1946 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 1947 if (tmp_u1b & BIT(4)) { 1948 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 1949 rtlefuse->epromtype = EEPROM_93C46; 1950 } else { 1951 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 1952 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 1953 } 1954 if (tmp_u1b & BIT(5)) { 1955 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 1956 rtlefuse->autoload_failflag = false; 1957 _rtl88ee_read_adapter_info(hw); 1958 } else { 1959 pr_err("Autoload ERR!!\n"); 1960 } 1961 _rtl88ee_hal_customized_behavior(hw); 1962 } 1963 1964 static void rtl88ee_update_hal_rate_table(struct ieee80211_hw *hw, 1965 struct ieee80211_sta *sta) 1966 { 1967 struct rtl_priv *rtlpriv = rtl_priv(hw); 1968 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1969 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1970 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1971 u32 ratr_value; 1972 u8 ratr_index = 0; 1973 u8 b_nmode = mac->ht_enable; 1974 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/ 1975 u16 shortgi_rate; 1976 u32 tmp_ratr_value; 1977 u8 curtxbw_40mhz = mac->bw_40; 1978 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1979 1 : 0; 1980 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1981 1 : 0; 1982 enum wireless_mode wirelessmode = mac->mode; 1983 u32 ratr_mask; 1984 1985 if (rtlhal->current_bandtype == BAND_ON_5G) 1986 ratr_value = sta->deflink.supp_rates[1] << 4; 1987 else 1988 ratr_value = sta->deflink.supp_rates[0]; 1989 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1990 ratr_value = 0xfff; 1991 ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | 1992 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 1993 switch (wirelessmode) { 1994 case WIRELESS_MODE_B: 1995 if (ratr_value & 0x0000000c) 1996 ratr_value &= 0x0000000d; 1997 else 1998 ratr_value &= 0x0000000f; 1999 break; 2000 case WIRELESS_MODE_G: 2001 ratr_value &= 0x00000FF5; 2002 break; 2003 case WIRELESS_MODE_N_24G: 2004 case WIRELESS_MODE_N_5G: 2005 b_nmode = 1; 2006 if (get_rf_type(rtlphy) == RF_1T2R || 2007 get_rf_type(rtlphy) == RF_1T1R) 2008 ratr_mask = 0x000ff005; 2009 else 2010 ratr_mask = 0x0f0ff005; 2011 2012 ratr_value &= ratr_mask; 2013 break; 2014 default: 2015 if (rtlphy->rf_type == RF_1T2R) 2016 ratr_value &= 0x000ff0ff; 2017 else 2018 ratr_value &= 0x0f0ff0ff; 2019 2020 break; 2021 } 2022 2023 if ((rtlpriv->btcoexist.bt_coexistence) && 2024 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) && 2025 (rtlpriv->btcoexist.bt_cur_state) && 2026 (rtlpriv->btcoexist.bt_ant_isolation) && 2027 ((rtlpriv->btcoexist.bt_service == BT_SCO) || 2028 (rtlpriv->btcoexist.bt_service == BT_BUSY))) 2029 ratr_value &= 0x0fffcfc0; 2030 else 2031 ratr_value &= 0x0FFFFFFF; 2032 2033 if (b_nmode && 2034 ((curtxbw_40mhz && curshortgi_40mhz) || 2035 (!curtxbw_40mhz && curshortgi_20mhz))) { 2036 ratr_value |= 0x10000000; 2037 tmp_ratr_value = (ratr_value >> 12); 2038 2039 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 2040 if ((1 << shortgi_rate) & tmp_ratr_value) 2041 break; 2042 } 2043 2044 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 2045 (shortgi_rate << 4) | (shortgi_rate); 2046 } 2047 2048 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 2049 2050 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, 2051 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)); 2052 } 2053 2054 static void rtl88ee_update_hal_rate_mask(struct ieee80211_hw *hw, 2055 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) 2056 { 2057 struct rtl_priv *rtlpriv = rtl_priv(hw); 2058 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2059 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2060 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2061 struct rtl_sta_info *sta_entry = NULL; 2062 u32 ratr_bitmap; 2063 u8 ratr_index; 2064 u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) 2065 ? 1 : 0; 2066 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2067 1 : 0; 2068 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2069 1 : 0; 2070 enum wireless_mode wirelessmode = 0; 2071 bool b_shortgi = false; 2072 u8 rate_mask[5]; 2073 u8 macid = 0; 2074 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/ 2075 2076 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 2077 wirelessmode = sta_entry->wireless_mode; 2078 if (mac->opmode == NL80211_IFTYPE_STATION || 2079 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2080 curtxbw_40mhz = mac->bw_40; 2081 else if (mac->opmode == NL80211_IFTYPE_AP || 2082 mac->opmode == NL80211_IFTYPE_ADHOC) 2083 macid = sta->aid + 1; 2084 2085 if (rtlhal->current_bandtype == BAND_ON_5G) 2086 ratr_bitmap = sta->deflink.supp_rates[1] << 4; 2087 else 2088 ratr_bitmap = sta->deflink.supp_rates[0]; 2089 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2090 ratr_bitmap = 0xfff; 2091 ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | 2092 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 2093 switch (wirelessmode) { 2094 case WIRELESS_MODE_B: 2095 ratr_index = RATR_INX_WIRELESS_B; 2096 if (ratr_bitmap & 0x0000000c) 2097 ratr_bitmap &= 0x0000000d; 2098 else 2099 ratr_bitmap &= 0x0000000f; 2100 break; 2101 case WIRELESS_MODE_G: 2102 ratr_index = RATR_INX_WIRELESS_GB; 2103 2104 if (rssi_level == 1) 2105 ratr_bitmap &= 0x00000f00; 2106 else if (rssi_level == 2) 2107 ratr_bitmap &= 0x00000ff0; 2108 else 2109 ratr_bitmap &= 0x00000ff5; 2110 break; 2111 case WIRELESS_MODE_N_24G: 2112 case WIRELESS_MODE_N_5G: 2113 ratr_index = RATR_INX_WIRELESS_NGB; 2114 if (rtlphy->rf_type == RF_1T2R || 2115 rtlphy->rf_type == RF_1T1R) { 2116 if (curtxbw_40mhz) { 2117 if (rssi_level == 1) 2118 ratr_bitmap &= 0x000f0000; 2119 else if (rssi_level == 2) 2120 ratr_bitmap &= 0x000ff000; 2121 else 2122 ratr_bitmap &= 0x000ff015; 2123 } else { 2124 if (rssi_level == 1) 2125 ratr_bitmap &= 0x000f0000; 2126 else if (rssi_level == 2) 2127 ratr_bitmap &= 0x000ff000; 2128 else 2129 ratr_bitmap &= 0x000ff005; 2130 } 2131 } else { 2132 if (curtxbw_40mhz) { 2133 if (rssi_level == 1) 2134 ratr_bitmap &= 0x0f8f0000; 2135 else if (rssi_level == 2) 2136 ratr_bitmap &= 0x0f8ff000; 2137 else 2138 ratr_bitmap &= 0x0f8ff015; 2139 } else { 2140 if (rssi_level == 1) 2141 ratr_bitmap &= 0x0f8f0000; 2142 else if (rssi_level == 2) 2143 ratr_bitmap &= 0x0f8ff000; 2144 else 2145 ratr_bitmap &= 0x0f8ff005; 2146 } 2147 } 2148 /*}*/ 2149 2150 if ((curtxbw_40mhz && curshortgi_40mhz) || 2151 (!curtxbw_40mhz && curshortgi_20mhz)) { 2152 2153 if (macid == 0) 2154 b_shortgi = true; 2155 else if (macid == 1) 2156 b_shortgi = false; 2157 } 2158 break; 2159 default: 2160 ratr_index = RATR_INX_WIRELESS_NGB; 2161 2162 if (rtlphy->rf_type == RF_1T2R) 2163 ratr_bitmap &= 0x000ff0ff; 2164 else 2165 ratr_bitmap &= 0x0f0ff0ff; 2166 break; 2167 } 2168 sta_entry->ratr_index = ratr_index; 2169 2170 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, 2171 "ratr_bitmap :%x\n", ratr_bitmap); 2172 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 2173 (ratr_index << 28); 2174 rate_mask[4] = macid | (b_shortgi ? 0x20 : 0x00) | 0x80; 2175 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, 2176 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n", 2177 ratr_index, ratr_bitmap, 2178 rate_mask[0], rate_mask[1], 2179 rate_mask[2], rate_mask[3], 2180 rate_mask[4]); 2181 rtl88e_fill_h2c_cmd(hw, H2C_88E_RA_MASK, 5, rate_mask); 2182 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0); 2183 } 2184 2185 void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw, 2186 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) 2187 { 2188 struct rtl_priv *rtlpriv = rtl_priv(hw); 2189 2190 if (rtlpriv->dm.useramask) 2191 rtl88ee_update_hal_rate_mask(hw, sta, rssi_level, update_bw); 2192 else 2193 rtl88ee_update_hal_rate_table(hw, sta); 2194 } 2195 2196 void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw) 2197 { 2198 struct rtl_priv *rtlpriv = rtl_priv(hw); 2199 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2200 u16 sifs_timer; 2201 2202 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time); 2203 if (!mac->ht_enable) 2204 sifs_timer = 0x0a0a; 2205 else 2206 sifs_timer = 0x0e0e; 2207 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2208 } 2209 2210 bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2211 { 2212 struct rtl_priv *rtlpriv = rtl_priv(hw); 2213 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2214 enum rf_pwrstate e_rfpowerstate_toset; 2215 u32 u4tmp; 2216 bool b_actuallyset = false; 2217 2218 if (rtlpriv->rtlhal.being_init_adapter) 2219 return false; 2220 2221 if (ppsc->swrf_processing) 2222 return false; 2223 2224 spin_lock(&rtlpriv->locks.rf_ps_lock); 2225 if (ppsc->rfchange_inprogress) { 2226 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2227 return false; 2228 } else { 2229 ppsc->rfchange_inprogress = true; 2230 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2231 } 2232 2233 u4tmp = rtl_read_dword(rtlpriv, REG_GPIO_OUTPUT); 2234 e_rfpowerstate_toset = (u4tmp & BIT(31)) ? ERFON : ERFOFF; 2235 2236 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) { 2237 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 2238 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2239 2240 e_rfpowerstate_toset = ERFON; 2241 ppsc->hwradiooff = false; 2242 b_actuallyset = true; 2243 } else if ((!ppsc->hwradiooff) && 2244 (e_rfpowerstate_toset == ERFOFF)) { 2245 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 2246 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 2247 2248 e_rfpowerstate_toset = ERFOFF; 2249 ppsc->hwradiooff = true; 2250 b_actuallyset = true; 2251 } 2252 2253 if (b_actuallyset) { 2254 spin_lock(&rtlpriv->locks.rf_ps_lock); 2255 ppsc->rfchange_inprogress = false; 2256 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2257 } else { 2258 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) 2259 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2260 2261 spin_lock(&rtlpriv->locks.rf_ps_lock); 2262 ppsc->rfchange_inprogress = false; 2263 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2264 } 2265 2266 *valid = 1; 2267 return !ppsc->hwradiooff; 2268 2269 } 2270 2271 void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key_index, 2272 u8 *p_macaddr, bool is_group, u8 enc_algo, 2273 bool is_wepkey, bool clear_all) 2274 { 2275 struct rtl_priv *rtlpriv = rtl_priv(hw); 2276 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2277 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2278 u8 *macaddr = p_macaddr; 2279 u32 entry_id = 0; 2280 bool is_pairwise = false; 2281 static u8 cam_const_addr[4][6] = { 2282 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2283 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2284 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2285 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2286 }; 2287 static u8 cam_const_broad[] = { 2288 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2289 }; 2290 2291 if (clear_all) { 2292 u8 idx = 0; 2293 u8 cam_offset = 0; 2294 u8 clear_number = 5; 2295 2296 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2297 2298 for (idx = 0; idx < clear_number; idx++) { 2299 rtl_cam_mark_invalid(hw, cam_offset + idx); 2300 rtl_cam_empty_entry(hw, cam_offset + idx); 2301 2302 if (idx < 5) { 2303 memset(rtlpriv->sec.key_buf[idx], 0, 2304 MAX_KEY_LEN); 2305 rtlpriv->sec.key_len[idx] = 0; 2306 } 2307 } 2308 2309 } else { 2310 switch (enc_algo) { 2311 case WEP40_ENCRYPTION: 2312 enc_algo = CAM_WEP40; 2313 break; 2314 case WEP104_ENCRYPTION: 2315 enc_algo = CAM_WEP104; 2316 break; 2317 case TKIP_ENCRYPTION: 2318 enc_algo = CAM_TKIP; 2319 break; 2320 case AESCCMP_ENCRYPTION: 2321 enc_algo = CAM_AES; 2322 break; 2323 default: 2324 pr_err("switch case %#x not processed\n", 2325 enc_algo); 2326 enc_algo = CAM_TKIP; 2327 break; 2328 } 2329 2330 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2331 macaddr = cam_const_addr[key_index]; 2332 entry_id = key_index; 2333 } else { 2334 if (is_group) { 2335 macaddr = cam_const_broad; 2336 entry_id = key_index; 2337 } else { 2338 if (mac->opmode == NL80211_IFTYPE_AP || 2339 mac->opmode == NL80211_IFTYPE_MESH_POINT) { 2340 entry_id = 2341 rtl_cam_get_free_entry(hw, p_macaddr); 2342 if (entry_id >= TOTAL_CAM_ENTRY) { 2343 pr_err("Can not find free hw security cam entry\n"); 2344 return; 2345 } 2346 } else { 2347 entry_id = CAM_PAIRWISE_KEY_POSITION; 2348 } 2349 key_index = PAIRWISE_KEYIDX; 2350 is_pairwise = true; 2351 } 2352 } 2353 2354 if (rtlpriv->sec.key_len[key_index] == 0) { 2355 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2356 "delete one entry, entry_id is %d\n", 2357 entry_id); 2358 if (mac->opmode == NL80211_IFTYPE_AP || 2359 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2360 rtl_cam_del_entry(hw, p_macaddr); 2361 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2362 } else { 2363 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2364 "add one entry\n"); 2365 if (is_pairwise) { 2366 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2367 "set Pairwise key\n"); 2368 2369 rtl_cam_add_one_entry(hw, macaddr, key_index, 2370 entry_id, enc_algo, 2371 CAM_CONFIG_NO_USEDK, 2372 rtlpriv->sec.key_buf[key_index]); 2373 } else { 2374 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2375 "set group key\n"); 2376 2377 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2378 rtl_cam_add_one_entry(hw, 2379 rtlefuse->dev_addr, 2380 PAIRWISE_KEYIDX, 2381 CAM_PAIRWISE_KEY_POSITION, 2382 enc_algo, 2383 CAM_CONFIG_NO_USEDK, 2384 rtlpriv->sec.key_buf 2385 [entry_id]); 2386 } 2387 2388 rtl_cam_add_one_entry(hw, macaddr, key_index, 2389 entry_id, enc_algo, 2390 CAM_CONFIG_NO_USEDK, 2391 rtlpriv->sec.key_buf[entry_id]); 2392 } 2393 2394 } 2395 } 2396 } 2397 2398 static void rtl8188ee_bt_var_init(struct ieee80211_hw *hw) 2399 { 2400 struct rtl_priv *rtlpriv = rtl_priv(hw); 2401 2402 rtlpriv->btcoexist.bt_coexistence = 2403 rtlpriv->btcoexist.eeprom_bt_coexist; 2404 rtlpriv->btcoexist.bt_ant_num = rtlpriv->btcoexist.eeprom_bt_ant_num; 2405 rtlpriv->btcoexist.bt_coexist_type = rtlpriv->btcoexist.eeprom_bt_type; 2406 2407 if (rtlpriv->btcoexist.reg_bt_iso == 2) 2408 rtlpriv->btcoexist.bt_ant_isolation = 2409 rtlpriv->btcoexist.eeprom_bt_ant_isol; 2410 else 2411 rtlpriv->btcoexist.bt_ant_isolation = 2412 rtlpriv->btcoexist.reg_bt_iso; 2413 2414 rtlpriv->btcoexist.bt_radio_shared_type = 2415 rtlpriv->btcoexist.eeprom_bt_radio_shared; 2416 2417 if (rtlpriv->btcoexist.bt_coexistence) { 2418 if (rtlpriv->btcoexist.reg_bt_sco == 1) 2419 rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION; 2420 else if (rtlpriv->btcoexist.reg_bt_sco == 2) 2421 rtlpriv->btcoexist.bt_service = BT_SCO; 2422 else if (rtlpriv->btcoexist.reg_bt_sco == 4) 2423 rtlpriv->btcoexist.bt_service = BT_BUSY; 2424 else if (rtlpriv->btcoexist.reg_bt_sco == 5) 2425 rtlpriv->btcoexist.bt_service = BT_OTHERBUSY; 2426 else 2427 rtlpriv->btcoexist.bt_service = BT_IDLE; 2428 2429 rtlpriv->btcoexist.bt_edca_ul = 0; 2430 rtlpriv->btcoexist.bt_edca_dl = 0; 2431 rtlpriv->btcoexist.bt_rssi_state = 0xff; 2432 } 2433 } 2434 2435 void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 2436 bool auto_load_fail, u8 *hwinfo) 2437 { 2438 struct rtl_priv *rtlpriv = rtl_priv(hw); 2439 u8 value; 2440 2441 if (!auto_load_fail) { 2442 rtlpriv->btcoexist.eeprom_bt_coexist = 2443 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0xe0) >> 5); 2444 if (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] == 0xFF) 2445 rtlpriv->btcoexist.eeprom_bt_coexist = 0; 2446 value = hwinfo[EEPROM_RF_BT_SETTING_88E]; 2447 rtlpriv->btcoexist.eeprom_bt_type = ((value & 0xe) >> 1); 2448 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1); 2449 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4); 2450 rtlpriv->btcoexist.eeprom_bt_radio_shared = 2451 ((value & 0x20) >> 5); 2452 } else { 2453 rtlpriv->btcoexist.eeprom_bt_coexist = 0; 2454 rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE; 2455 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2; 2456 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0; 2457 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED; 2458 } 2459 2460 rtl8188ee_bt_var_init(hw); 2461 } 2462 2463 void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw) 2464 { 2465 struct rtl_priv *rtlpriv = rtl_priv(hw); 2466 2467 /* 0:Low, 1:High, 2:From Efuse. */ 2468 rtlpriv->btcoexist.reg_bt_iso = 2; 2469 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 2470 rtlpriv->btcoexist.reg_bt_sco = 0; 2471 } 2472 2473 void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw) 2474 { 2475 struct rtl_priv *rtlpriv = rtl_priv(hw); 2476 struct rtl_phy *rtlphy = &rtlpriv->phy; 2477 u8 u1_tmp; 2478 2479 if (rtlpriv->btcoexist.bt_coexistence && 2480 ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) || 2481 rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) { 2482 if (rtlpriv->btcoexist.bt_ant_isolation) 2483 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0); 2484 2485 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) & BIT(0); 2486 u1_tmp = u1_tmp | 2487 ((rtlpriv->btcoexist.bt_ant_isolation == 1) ? 2488 0 : BIT((1)) | 2489 ((rtlpriv->btcoexist.bt_service == BT_SCO) ? 2490 0 : BIT(2))); 2491 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp); 2492 2493 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa); 2494 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040); 2495 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010); 2496 2497 /* Config to 1T1R. */ 2498 if (rtlphy->rf_type == RF_1T1R) { 2499 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE); 2500 u1_tmp &= ~(BIT(1)); 2501 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp); 2502 2503 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE); 2504 u1_tmp &= ~(BIT(1)); 2505 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp); 2506 } 2507 } 2508 } 2509 2510 void rtl88ee_suspend(struct ieee80211_hw *hw) 2511 { 2512 } 2513 2514 void rtl88ee_resume(struct ieee80211_hw *hw) 2515 { 2516 } 2517