1 /******************************************************************************
2  *
3  * Copyright(c) 2009-2013  Realtek Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * The full GNU General Public License is included in this distribution in the
15  * file called LICENSE.
16  *
17  * Contact Information:
18  * wlanfae <wlanfae@realtek.com>
19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20  * Hsinchu 300, Taiwan.
21  *
22  * Larry Finger <Larry.Finger@lwfinger.net>
23  *
24  *****************************************************************************/
25 
26 #ifndef __RTL92C_DEF_H__
27 #define __RTL92C_DEF_H__
28 
29 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE			0
30 #define HAL_PRIME_CHNL_OFFSET_LOWER			1
31 #define HAL_PRIME_CHNL_OFFSET_UPPER			2
32 
33 #define RX_MPDU_QUEUE					0
34 #define RX_CMD_QUEUE					1
35 
36 #define	C2H_RX_CMD_HDR_LEN				8
37 #define	GET_C2H_CMD_CMD_LEN(__prxhdr)			\
38 	LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
39 #define	GET_C2H_CMD_ELEMENT_ID(__prxhdr)		\
40 	LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
41 #define	GET_C2H_CMD_CMD_SEQ(__prxhdr)			\
42 	LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
43 #define	GET_C2H_CMD_CONTINUE(__prxhdr)			\
44 	LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
45 #define	GET_C2H_CMD_CONTENT(__prxhdr)			\
46 	((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
47 
48 #define	GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr)	\
49 	LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
50 #define	GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr)	\
51 	LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
52 #define	GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr)	\
53 	LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
54 #define	GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr)	\
55 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
56 #define	GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr)	\
57 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
58 #define	GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr)	\
59 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
60 #define	GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr)	\
61 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
62 #define	GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr)	\
63 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
64 #define	GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr)	\
65 	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
66 
67 #define CHIP_BONDING_IDENTIFIER(_value)	(((_value)>>22)&0x3)
68 
69 /* [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3
70  * [7] Manufacturer: TSMC=0, UMC=1
71  * [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2
72  * [3] Chip type: TEST=0, NORMAL=1
73  * [2:0] IC type: 81xxC=0, 8723=1, 92D=2
74  */
75 #define CHIP_8723			BIT(0)
76 #define CHIP_92D			BIT(1)
77 #define NORMAL_CHIP			BIT(3)
78 #define RF_TYPE_1T1R			(~(BIT(4)|BIT(5)|BIT(6)))
79 #define RF_TYPE_1T2R			BIT(4)
80 #define RF_TYPE_2T2R			BIT(5)
81 #define CHIP_VENDOR_UMC			BIT(7)
82 #define B_CUT_VERSION			BIT(12)
83 #define C_CUT_VERSION			BIT(13)
84 #define D_CUT_VERSION			((BIT(12)|BIT(13)))
85 #define E_CUT_VERSION			BIT(14)
86 
87 /* MASK */
88 #define IC_TYPE_MASK			(BIT(0)|BIT(1)|BIT(2))
89 #define CHIP_TYPE_MASK			BIT(3)
90 #define RF_TYPE_MASK			(BIT(4)|BIT(5)|BIT(6))
91 #define MANUFACTUER_MASK		BIT(7)
92 #define ROM_VERSION_MASK		(BIT(11)|BIT(10)|BIT(9)|BIT(8))
93 #define CUT_VERSION_MASK		(BIT(15)|BIT(14)|BIT(13)|BIT(12))
94 
95 /* Get element */
96 #define GET_CVID_IC_TYPE(version)	((version) & IC_TYPE_MASK)
97 #define GET_CVID_CHIP_TYPE(version)	((version) & CHIP_TYPE_MASK)
98 #define GET_CVID_RF_TYPE(version)	((version) & RF_TYPE_MASK)
99 #define GET_CVID_MANUFACTUER(version)	((version) & MANUFACTUER_MASK)
100 #define GET_CVID_ROM_VERSION(version)	((version) & ROM_VERSION_MASK)
101 #define GET_CVID_CUT_VERSION(version)	((version) & CUT_VERSION_MASK)
102 
103 #define IS_81XXC(version)						\
104 	((GET_CVID_IC_TYPE(version) == 0) ? true : false)
105 #define IS_8723_SERIES(version)						\
106 	((GET_CVID_IC_TYPE(version) == CHIP_8723) ? true : false)
107 #define IS_92D(version)							\
108 	((GET_CVID_IC_TYPE(version) == CHIP_92D) ? true : false)
109 
110 #define IS_NORMAL_CHIP(version)						\
111 	((GET_CVID_CHIP_TYPE(version)) ? true : false)
112 #define IS_NORMAL_CHIP92D(version)					\
113 	((GET_CVID_CHIP_TYPE(version)) ? true : false)
114 
115 #define IS_1T1R(version)						\
116 	((GET_CVID_RF_TYPE(version)) ? false : true)
117 #define IS_1T2R(version)						\
118 	((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? true : false)
119 #define IS_2T2R(version)						\
120 	((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? true : false)
121 #define IS_CHIP_VENDOR_UMC(version)					\
122 	((GET_CVID_MANUFACTUER(version)) ? true : false)
123 
124 #define IS_92C_SERIAL(version)						\
125 	((IS_81XXC(version) && IS_2T2R(version)) ? true : false)
126 #define IS_81xxC_VENDOR_UMC_A_CUT(version)				\
127 	(IS_81XXC(version) ? ((IS_CHIP_VENDOR_UMC(version)) ?		\
128 	 ((GET_CVID_CUT_VERSION(version)) ? false : true) : false) : false)
129 #define IS_81XXC_VENDOR_UMC_B_CUT(version)				\
130 	(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ?		\
131 	((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? true	\
132 	: false) : false) : false)
133 
134 enum version_8188e {
135 	VERSION_TEST_CHIP_88E = 0x00,
136 	VERSION_NORMAL_CHIP_88E = 0x01,
137 	VERSION_UNKNOWN = 0xFF,
138 };
139 
140 enum rx_packet_type {
141 	NORMAL_RX,
142 	TX_REPORT1,
143 	TX_REPORT2,
144 	HIS_REPORT,
145 };
146 
147 enum rtl819x_loopback_e {
148 	RTL819X_NO_LOOPBACK = 0,
149 	RTL819X_MAC_LOOPBACK = 1,
150 	RTL819X_DMA_LOOPBACK = 2,
151 	RTL819X_CCK_LOOPBACK = 3,
152 };
153 
154 enum rf_optype {
155 	RF_OP_BY_SW_3WIRE = 0,
156 	RF_OP_BY_FW,
157 	RF_OP_MAX
158 };
159 
160 enum rf_power_state {
161 	RF_ON,
162 	RF_OFF,
163 	RF_SLEEP,
164 	RF_SHUT_DOWN,
165 };
166 
167 enum power_save_mode {
168 	POWER_SAVE_MODE_ACTIVE,
169 	POWER_SAVE_MODE_SAVE,
170 };
171 
172 enum power_polocy_config {
173 	POWERCFG_MAX_POWER_SAVINGS,
174 	POWERCFG_GLOBAL_POWER_SAVINGS,
175 	POWERCFG_LOCAL_POWER_SAVINGS,
176 	POWERCFG_LENOVO,
177 };
178 
179 enum interface_select_pci {
180 	INTF_SEL1_MINICARD = 0,
181 	INTF_SEL0_PCIE = 1,
182 	INTF_SEL2_RSV = 2,
183 	INTF_SEL3_RSV = 3,
184 };
185 
186 enum hal_fw_c2h_cmd_id {
187 	HAL_FW_C2H_CMD_READ_MACREG = 0,
188 	HAL_FW_C2H_CMD_READ_BBREG = 1,
189 	HAL_FW_C2H_CMD_READ_RFREG = 2,
190 	HAL_FW_C2H_CMD_READ_EEPROM = 3,
191 	HAL_FW_C2H_CMD_READ_EFUSE = 4,
192 	HAL_FW_C2H_CMD_READ_CAM = 5,
193 	HAL_FW_C2H_CMD_GET_BASICRATE = 6,
194 	HAL_FW_C2H_CMD_GET_DATARATE = 7,
195 	HAL_FW_C2H_CMD_SURVEY = 8,
196 	HAL_FW_C2H_CMD_SURVEYDONE = 9,
197 	HAL_FW_C2H_CMD_JOINBSS = 10,
198 	HAL_FW_C2H_CMD_ADDSTA = 11,
199 	HAL_FW_C2H_CMD_DELSTA = 12,
200 	HAL_FW_C2H_CMD_ATIMDONE = 13,
201 	HAL_FW_C2H_CMD_TX_REPORT = 14,
202 	HAL_FW_C2H_CMD_CCX_REPORT = 15,
203 	HAL_FW_C2H_CMD_DTM_REPORT = 16,
204 	HAL_FW_C2H_CMD_TX_RATE_STATISTICS = 17,
205 	HAL_FW_C2H_CMD_C2HLBK = 18,
206 	HAL_FW_C2H_CMD_C2HDBG = 19,
207 	HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
208 	HAL_FW_C2H_CMD_MAX
209 };
210 
211 enum rtl_desc_qsel {
212 	QSLT_BK = 0x2,
213 	QSLT_BE = 0x0,
214 	QSLT_VI = 0x5,
215 	QSLT_VO = 0x7,
216 	QSLT_BEACON = 0x10,
217 	QSLT_HIGH = 0x11,
218 	QSLT_MGNT = 0x12,
219 	QSLT_CMD = 0x13,
220 };
221 
222 enum rtl_desc92c_rate {
223 	DESC92C_RATE1M = 0x00,
224 	DESC92C_RATE2M = 0x01,
225 	DESC92C_RATE5_5M = 0x02,
226 	DESC92C_RATE11M = 0x03,
227 
228 	DESC92C_RATE6M = 0x04,
229 	DESC92C_RATE9M = 0x05,
230 	DESC92C_RATE12M = 0x06,
231 	DESC92C_RATE18M = 0x07,
232 	DESC92C_RATE24M = 0x08,
233 	DESC92C_RATE36M = 0x09,
234 	DESC92C_RATE48M = 0x0a,
235 	DESC92C_RATE54M = 0x0b,
236 
237 	DESC92C_RATEMCS0 = 0x0c,
238 	DESC92C_RATEMCS1 = 0x0d,
239 	DESC92C_RATEMCS2 = 0x0e,
240 	DESC92C_RATEMCS3 = 0x0f,
241 	DESC92C_RATEMCS4 = 0x10,
242 	DESC92C_RATEMCS5 = 0x11,
243 	DESC92C_RATEMCS6 = 0x12,
244 	DESC92C_RATEMCS7 = 0x13,
245 	DESC92C_RATEMCS8 = 0x14,
246 	DESC92C_RATEMCS9 = 0x15,
247 	DESC92C_RATEMCS10 = 0x16,
248 	DESC92C_RATEMCS11 = 0x17,
249 	DESC92C_RATEMCS12 = 0x18,
250 	DESC92C_RATEMCS13 = 0x19,
251 	DESC92C_RATEMCS14 = 0x1a,
252 	DESC92C_RATEMCS15 = 0x1b,
253 	DESC92C_RATEMCS15_SG = 0x1c,
254 	DESC92C_RATEMCS32 = 0x20,
255 };
256 
257 struct phy_sts_cck_8192s_t {
258 	u8 adc_pwdb_X[4];
259 	u8 sq_rpt;
260 	u8 cck_agc_rpt;
261 };
262 
263 struct h2c_cmd_8192c {
264 	u8 element_id;
265 	u32 cmd_len;
266 	u8 *p_cmdbuffer;
267 };
268 
269 #endif
270