1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __RTL_PCI_H__ 27 #define __RTL_PCI_H__ 28 29 #include <linux/pci.h> 30 /* 1: MSDU packet queue, 31 * 2: Rx Command Queue 32 */ 33 #define RTL_PCI_RX_MPDU_QUEUE 0 34 #define RTL_PCI_RX_CMD_QUEUE 1 35 #define RTL_PCI_MAX_RX_QUEUE 2 36 37 #define RTL_PCI_MAX_RX_COUNT 512/*64*/ 38 #define RTL_PCI_MAX_TX_QUEUE_COUNT 9 39 40 #define RT_TXDESC_NUM 128 41 #define TX_DESC_NUM_92E 512 42 #define TX_DESC_NUM_8822B 512 43 #define RT_TXDESC_NUM_BE_QUEUE 256 44 45 #define BK_QUEUE 0 46 #define BE_QUEUE 1 47 #define VI_QUEUE 2 48 #define VO_QUEUE 3 49 #define BEACON_QUEUE 4 50 #define TXCMD_QUEUE 5 51 #define MGNT_QUEUE 6 52 #define HIGH_QUEUE 7 53 #define HCCA_QUEUE 8 54 #define H2C_QUEUE TXCMD_QUEUE /* In 8822B */ 55 56 #define RTL_PCI_DEVICE(vend, dev, cfg) \ 57 .vendor = (vend), \ 58 .device = (dev), \ 59 .subvendor = PCI_ANY_ID, \ 60 .subdevice = PCI_ANY_ID,\ 61 .driver_data = (kernel_ulong_t)&(cfg) 62 63 #define INTEL_VENDOR_ID 0x8086 64 #define SIS_VENDOR_ID 0x1039 65 #define ATI_VENDOR_ID 0x1002 66 #define ATI_DEVICE_ID 0x7914 67 #define AMD_VENDOR_ID 0x1022 68 69 #define PCI_MAX_BRIDGE_NUMBER 255 70 #define PCI_MAX_DEVICES 32 71 #define PCI_MAX_FUNCTION 8 72 73 #define PCI_CONF_ADDRESS 0x0CF8 /*PCI Configuration Space Address */ 74 #define PCI_CONF_DATA 0x0CFC /*PCI Configuration Space Data */ 75 76 #define PCI_CLASS_BRIDGE_DEV 0x06 77 #define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04 78 #define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10 79 #define PCI_CAP_ID_EXP 0x10 80 81 #define U1DONTCARE 0xFF 82 #define U2DONTCARE 0xFFFF 83 #define U4DONTCARE 0xFFFFFFFF 84 85 #define RTL_PCI_8192_DID 0x8192 /*8192 PCI-E */ 86 #define RTL_PCI_8192SE_DID 0x8192 /*8192 SE */ 87 #define RTL_PCI_8174_DID 0x8174 /*8192 SE */ 88 #define RTL_PCI_8173_DID 0x8173 /*8191 SE Crab */ 89 #define RTL_PCI_8172_DID 0x8172 /*8191 SE RE */ 90 #define RTL_PCI_8171_DID 0x8171 /*8191 SE Unicron */ 91 #define RTL_PCI_8723AE_DID 0x8723 /*8723AE */ 92 #define RTL_PCI_0045_DID 0x0045 /*8190 PCI for Ceraga */ 93 #define RTL_PCI_0046_DID 0x0046 /*8190 Cardbus for Ceraga */ 94 #define RTL_PCI_0044_DID 0x0044 /*8192e PCIE for Ceraga */ 95 #define RTL_PCI_0047_DID 0x0047 /*8192e Express Card for Ceraga */ 96 #define RTL_PCI_700F_DID 0x700F 97 #define RTL_PCI_701F_DID 0x701F 98 #define RTL_PCI_DLINK_DID 0x3304 99 #define RTL_PCI_8723AE_DID 0x8723 /*8723e */ 100 #define RTL_PCI_8192CET_DID 0x8191 /*8192ce */ 101 #define RTL_PCI_8192CE_DID 0x8178 /*8192ce */ 102 #define RTL_PCI_8191CE_DID 0x8177 /*8192ce */ 103 #define RTL_PCI_8188CE_DID 0x8176 /*8192ce */ 104 #define RTL_PCI_8192CU_DID 0x8191 /*8192ce */ 105 #define RTL_PCI_8192DE_DID 0x8193 /*8192de */ 106 #define RTL_PCI_8192DE_DID2 0x002B /*92DE*/ 107 #define RTL_PCI_8188EE_DID 0x8179 /*8188ee*/ 108 #define RTL_PCI_8723BE_DID 0xB723 /*8723be*/ 109 #define RTL_PCI_8192EE_DID 0x818B /*8192ee*/ 110 #define RTL_PCI_8821AE_DID 0x8821 /*8821ae*/ 111 #define RTL_PCI_8812AE_DID 0x8812 /*8812ae*/ 112 #define RTL_PCI_8822BE_DID 0xB822 /*8822be*/ 113 114 /*8192 support 16 pages of IO registers*/ 115 #define RTL_MEM_MAPPED_IO_RANGE_8190PCI 0x1000 116 #define RTL_MEM_MAPPED_IO_RANGE_8192PCIE 0x4000 117 #define RTL_MEM_MAPPED_IO_RANGE_8192SE 0x4000 118 #define RTL_MEM_MAPPED_IO_RANGE_8192CE 0x4000 119 #define RTL_MEM_MAPPED_IO_RANGE_8192DE 0x4000 120 121 #define RTL_PCI_REVISION_ID_8190PCI 0x00 122 #define RTL_PCI_REVISION_ID_8192PCIE 0x01 123 #define RTL_PCI_REVISION_ID_8192SE 0x10 124 #define RTL_PCI_REVISION_ID_8192CE 0x1 125 #define RTL_PCI_REVISION_ID_8192DE 0x0 126 127 #define RTL_DEFAULT_HARDWARE_TYPE HARDWARE_TYPE_RTL8192CE 128 129 enum pci_bridge_vendor { 130 PCI_BRIDGE_VENDOR_INTEL = 0x0, /*0b'0000,0001 */ 131 PCI_BRIDGE_VENDOR_ATI, /*0b'0000,0010*/ 132 PCI_BRIDGE_VENDOR_AMD, /*0b'0000,0100*/ 133 PCI_BRIDGE_VENDOR_SIS, /*0b'0000,1000*/ 134 PCI_BRIDGE_VENDOR_UNKNOWN, /*0b'0100,0000*/ 135 PCI_BRIDGE_VENDOR_MAX, 136 }; 137 138 struct rtl_pci_capabilities_header { 139 u8 capability_id; 140 u8 next; 141 }; 142 143 /* In new TRX flow, Buffer_desc is new concept 144 * But TX wifi info == TX descriptor in old flow 145 * RX wifi info == RX descriptor in old flow 146 */ 147 struct rtl_tx_buffer_desc { 148 u32 dword[4 * (1 << (BUFDESC_SEG_NUM + 1))]; 149 } __packed; 150 151 struct rtl_tx_desc { 152 u32 dword[16]; 153 } __packed; 154 155 struct rtl_rx_buffer_desc { /*rx buffer desc*/ 156 u32 dword[4]; 157 } __packed; 158 159 struct rtl_rx_desc { /*old: rx desc new: rx wifi info*/ 160 u32 dword[8]; 161 } __packed; 162 163 struct rtl_tx_cmd_desc { 164 u32 dword[16]; 165 } __packed; 166 167 struct rtl8192_tx_ring { 168 struct rtl_tx_desc *desc; 169 dma_addr_t dma; 170 unsigned int idx; 171 unsigned int entries; 172 struct sk_buff_head queue; 173 /*add for new trx flow*/ 174 struct rtl_tx_buffer_desc *buffer_desc; /*tx buffer descriptor*/ 175 dma_addr_t buffer_desc_dma; /*tx bufferd desc dma memory*/ 176 u16 avl_desc; /* available_desc_to_write */ 177 u16 cur_tx_wp; /* current_tx_write_point */ 178 u16 cur_tx_rp; /* current_tx_read_point */ 179 }; 180 181 struct rtl8192_rx_ring { 182 struct rtl_rx_desc *desc; 183 dma_addr_t dma; 184 unsigned int idx; 185 struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT]; 186 /*add for new trx flow*/ 187 struct rtl_rx_buffer_desc *buffer_desc; /*rx buffer descriptor*/ 188 u16 next_rx_rp; /* next_rx_read_point */ 189 }; 190 191 struct rtl_pci { 192 struct pci_dev *pdev; 193 bool irq_enabled; 194 195 bool driver_is_goingto_unload; 196 bool up_first_time; 197 bool first_init; 198 bool being_init_adapter; 199 bool init_ready; 200 201 /*Tx */ 202 struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT]; 203 int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT]; 204 u32 transmit_config; 205 206 /*Rx */ 207 struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE]; 208 int rxringcount; 209 u16 rxbuffersize; 210 u32 receive_config; 211 212 /*irq */ 213 u8 irq_alloc; 214 u32 irq_mask[4]; /* 0-1: normal, 2: unused, 3: h2c */ 215 u32 sys_irq_mask; 216 217 /*Bcn control register setting */ 218 u32 reg_bcn_ctrl_val; 219 220 /*ASPM*/ u8 const_pci_aspm; 221 u8 const_amdpci_aspm; 222 u8 const_hwsw_rfoff_d3; 223 u8 const_support_pciaspm; 224 /*pci-e bridge */ 225 u8 const_hostpci_aspm_setting; 226 /*pci-e device */ 227 u8 const_devicepci_aspm_setting; 228 /* If it supports ASPM, Offset[560h] = 0x40, 229 * otherwise Offset[560h] = 0x00. 230 */ 231 bool support_aspm; 232 bool support_backdoor; 233 234 /*QOS & EDCA */ 235 enum acm_method acm_method; 236 237 u16 shortretry_limit; 238 u16 longretry_limit; 239 240 /* MSI support */ 241 bool msi_support; 242 bool using_msi; 243 /* interrupt clear before set */ 244 bool int_clear; 245 }; 246 247 struct mp_adapter { 248 u8 linkctrl_reg; 249 250 u8 busnumber; 251 u8 devnumber; 252 u8 funcnumber; 253 254 u8 pcibridge_busnum; 255 u8 pcibridge_devnum; 256 u8 pcibridge_funcnum; 257 258 u8 pcibridge_vendor; 259 u16 pcibridge_vendorid; 260 u16 pcibridge_deviceid; 261 262 u8 num4bytes; 263 264 u8 pcibridge_pciehdr_offset; 265 u8 pcibridge_linkctrlreg; 266 267 bool amd_l1_patch; 268 }; 269 270 struct rtl_pci_priv { 271 struct bt_coexist_info bt_coexist; 272 struct rtl_led_ctl ledctl; 273 struct rtl_pci dev; 274 struct mp_adapter ndis_adapter; 275 }; 276 277 #define rtl_pcipriv(hw) (((struct rtl_pci_priv *)(rtl_priv(hw))->priv)) 278 #define rtl_pcidev(pcipriv) (&((pcipriv)->dev)) 279 280 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw); 281 282 extern const struct rtl_intf_ops rtl_pci_ops; 283 284 int rtl_pci_probe(struct pci_dev *pdev, 285 const struct pci_device_id *id); 286 void rtl_pci_disconnect(struct pci_dev *pdev); 287 #ifdef CONFIG_PM_SLEEP 288 int rtl_pci_suspend(struct device *dev); 289 int rtl_pci_resume(struct device *dev); 290 #endif /* CONFIG_PM_SLEEP */ 291 static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr) 292 { 293 return readb((u8 __iomem *)rtlpriv->io.pci_mem_start + addr); 294 } 295 296 static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr) 297 { 298 return readw((u8 __iomem *)rtlpriv->io.pci_mem_start + addr); 299 } 300 301 static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr) 302 { 303 return readl((u8 __iomem *)rtlpriv->io.pci_mem_start + addr); 304 } 305 306 static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val) 307 { 308 writeb(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr); 309 } 310 311 static inline void pci_write16_async(struct rtl_priv *rtlpriv, 312 u32 addr, u16 val) 313 { 314 writew(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr); 315 } 316 317 static inline void pci_write32_async(struct rtl_priv *rtlpriv, 318 u32 addr, u32 val) 319 { 320 writel(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr); 321 } 322 323 static inline u16 calc_fifo_space(u16 rp, u16 wp) 324 { 325 if (rp <= wp) 326 return RTL_PCI_MAX_RX_COUNT - 1 + rp - wp; 327 return rp - wp - 1; 328 } 329 330 #endif 331