1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "wifi.h" 27 #include "core.h" 28 #include "pci.h" 29 #include "base.h" 30 #include "ps.h" 31 #include "efuse.h" 32 #include <linux/interrupt.h> 33 #include <linux/export.h> 34 #include <linux/kmemleak.h> 35 #include <linux/module.h> 36 37 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 38 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 39 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>"); 40 MODULE_LICENSE("GPL"); 41 MODULE_DESCRIPTION("PCI basic driver for rtlwifi"); 42 43 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { 44 INTEL_VENDOR_ID, 45 ATI_VENDOR_ID, 46 AMD_VENDOR_ID, 47 SIS_VENDOR_ID 48 }; 49 50 static const u8 ac_to_hwq[] = { 51 VO_QUEUE, 52 VI_QUEUE, 53 BE_QUEUE, 54 BK_QUEUE 55 }; 56 57 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb) 58 { 59 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 60 __le16 fc = rtl_get_fc(skb); 61 u8 queue_index = skb_get_queue_mapping(skb); 62 struct ieee80211_hdr *hdr; 63 64 if (unlikely(ieee80211_is_beacon(fc))) 65 return BEACON_QUEUE; 66 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) 67 return MGNT_QUEUE; 68 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 69 if (ieee80211_is_nullfunc(fc)) 70 return HIGH_QUEUE; 71 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) { 72 hdr = rtl_get_hdr(skb); 73 74 if (is_multicast_ether_addr(hdr->addr1) || 75 is_broadcast_ether_addr(hdr->addr1)) 76 return HIGH_QUEUE; 77 } 78 79 return ac_to_hwq[queue_index]; 80 } 81 82 /* Update PCI dependent default settings*/ 83 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) 84 { 85 struct rtl_priv *rtlpriv = rtl_priv(hw); 86 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 87 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 88 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 89 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 90 u8 init_aspm; 91 92 ppsc->reg_rfps_level = 0; 93 ppsc->support_aspm = false; 94 95 /*Update PCI ASPM setting */ 96 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm; 97 switch (rtlpci->const_pci_aspm) { 98 case 0: 99 /*No ASPM */ 100 break; 101 102 case 1: 103 /*ASPM dynamically enabled/disable. */ 104 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; 105 break; 106 107 case 2: 108 /*ASPM with Clock Req dynamically enabled/disable. */ 109 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | 110 RT_RF_OFF_LEVL_CLK_REQ); 111 break; 112 113 case 3: 114 /* Always enable ASPM and Clock Req 115 * from initialization to halt. 116 */ 117 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); 118 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | 119 RT_RF_OFF_LEVL_CLK_REQ); 120 break; 121 122 case 4: 123 /* Always enable ASPM without Clock Req 124 * from initialization to halt. 125 */ 126 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | 127 RT_RF_OFF_LEVL_CLK_REQ); 128 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; 129 break; 130 } 131 132 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 133 134 /*Update Radio OFF setting */ 135 switch (rtlpci->const_hwsw_rfoff_d3) { 136 case 1: 137 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 138 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 139 break; 140 141 case 2: 142 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 143 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 144 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 145 break; 146 147 case 3: 148 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; 149 break; 150 } 151 152 /*Set HW definition to determine if it supports ASPM. */ 153 switch (rtlpci->const_support_pciaspm) { 154 case 0: 155 /*Not support ASPM. */ 156 ppsc->support_aspm = false; 157 break; 158 case 1: 159 /*Support ASPM. */ 160 ppsc->support_aspm = true; 161 ppsc->support_backdoor = true; 162 break; 163 case 2: 164 /*ASPM value set by chipset. */ 165 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) 166 ppsc->support_aspm = true; 167 break; 168 default: 169 pr_err("switch case %#x not processed\n", 170 rtlpci->const_support_pciaspm); 171 break; 172 } 173 174 /* toshiba aspm issue, toshiba will set aspm selfly 175 * so we should not set aspm in driver 176 */ 177 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm); 178 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE && 179 init_aspm == 0x43) 180 ppsc->support_aspm = false; 181 } 182 183 static bool _rtl_pci_platform_switch_device_pci_aspm( 184 struct ieee80211_hw *hw, 185 u8 value) 186 { 187 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 188 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 189 190 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE) 191 value |= 0x40; 192 193 pci_write_config_byte(rtlpci->pdev, 0x80, value); 194 195 return false; 196 } 197 198 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/ 199 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value) 200 { 201 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 202 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 203 204 pci_write_config_byte(rtlpci->pdev, 0x81, value); 205 206 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 207 udelay(100); 208 } 209 210 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ 211 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) 212 { 213 struct rtl_priv *rtlpriv = rtl_priv(hw); 214 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 215 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 216 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 217 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 218 u8 num4bytes = pcipriv->ndis_adapter.num4bytes; 219 /*Retrieve original configuration settings. */ 220 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg; 221 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter. 222 pcibridge_linkctrlreg; 223 u16 aspmlevel = 0; 224 u8 tmp_u1b = 0; 225 226 if (!ppsc->support_aspm) 227 return; 228 229 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 230 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 231 "PCI(Bridge) UNKNOWN\n"); 232 233 return; 234 } 235 236 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 237 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 238 _rtl_pci_switch_clk_req(hw, 0x0); 239 } 240 241 /*for promising device will in L0 state after an I/O. */ 242 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b); 243 244 /*Set corresponding value. */ 245 aspmlevel |= BIT(0) | BIT(1); 246 linkctrl_reg &= ~aspmlevel; 247 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1)); 248 249 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg); 250 udelay(50); 251 252 /*4 Disable Pci Bridge ASPM */ 253 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), 254 pcibridge_linkctrlreg); 255 256 udelay(50); 257 } 258 259 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for 260 *power saving We should follow the sequence to enable 261 *RTL8192SE first then enable Pci Bridge ASPM 262 *or the system will show bluescreen. 263 */ 264 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) 265 { 266 struct rtl_priv *rtlpriv = rtl_priv(hw); 267 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 268 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 269 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 270 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 271 u8 num4bytes = pcipriv->ndis_adapter.num4bytes; 272 u16 aspmlevel; 273 u8 u_pcibridge_aspmsetting; 274 u8 u_device_aspmsetting; 275 276 if (!ppsc->support_aspm) 277 return; 278 279 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 280 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 281 "PCI(Bridge) UNKNOWN\n"); 282 return; 283 } 284 285 /*4 Enable Pci Bridge ASPM */ 286 287 u_pcibridge_aspmsetting = 288 pcipriv->ndis_adapter.pcibridge_linkctrlreg | 289 rtlpci->const_hostpci_aspm_setting; 290 291 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) 292 u_pcibridge_aspmsetting &= ~BIT(0); 293 294 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), 295 u_pcibridge_aspmsetting); 296 297 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 298 "PlatformEnableASPM(): Write reg[%x] = %x\n", 299 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10), 300 u_pcibridge_aspmsetting); 301 302 udelay(50); 303 304 /*Get ASPM level (with/without Clock Req) */ 305 aspmlevel = rtlpci->const_devicepci_aspm_setting; 306 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg; 307 308 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/ 309 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */ 310 311 u_device_aspmsetting |= aspmlevel; 312 313 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting); 314 315 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 316 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level & 317 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0); 318 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 319 } 320 udelay(100); 321 } 322 323 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw) 324 { 325 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 326 327 bool status = false; 328 u8 offset_e0; 329 unsigned int offset_e4; 330 331 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0); 332 333 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0); 334 335 if (offset_e0 == 0xA0) { 336 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4); 337 if (offset_e4 & BIT(23)) 338 status = true; 339 } 340 341 return status; 342 } 343 344 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw, 345 struct rtl_priv **buddy_priv) 346 { 347 struct rtl_priv *rtlpriv = rtl_priv(hw); 348 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 349 bool find_buddy_priv = false; 350 struct rtl_priv *tpriv; 351 struct rtl_pci_priv *tpcipriv = NULL; 352 353 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) { 354 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list, 355 list) { 356 tpcipriv = (struct rtl_pci_priv *)tpriv->priv; 357 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 358 "pcipriv->ndis_adapter.funcnumber %x\n", 359 pcipriv->ndis_adapter.funcnumber); 360 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 361 "tpcipriv->ndis_adapter.funcnumber %x\n", 362 tpcipriv->ndis_adapter.funcnumber); 363 364 if (pcipriv->ndis_adapter.busnumber == 365 tpcipriv->ndis_adapter.busnumber && 366 pcipriv->ndis_adapter.devnumber == 367 tpcipriv->ndis_adapter.devnumber && 368 pcipriv->ndis_adapter.funcnumber != 369 tpcipriv->ndis_adapter.funcnumber) { 370 find_buddy_priv = true; 371 break; 372 } 373 } 374 } 375 376 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 377 "find_buddy_priv %d\n", find_buddy_priv); 378 379 if (find_buddy_priv) 380 *buddy_priv = tpriv; 381 382 return find_buddy_priv; 383 } 384 385 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw) 386 { 387 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 388 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 389 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset; 390 u8 linkctrl_reg; 391 u8 num4bbytes; 392 393 num4bbytes = (capabilityoffset + 0x10) / 4; 394 395 /*Read Link Control Register */ 396 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg); 397 398 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg; 399 } 400 401 static void rtl_pci_parse_configuration(struct pci_dev *pdev, 402 struct ieee80211_hw *hw) 403 { 404 struct rtl_priv *rtlpriv = rtl_priv(hw); 405 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 406 407 u8 tmp; 408 u16 linkctrl_reg; 409 410 /*Link Control Register */ 411 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg); 412 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg; 413 414 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", 415 pcipriv->ndis_adapter.linkctrl_reg); 416 417 pci_read_config_byte(pdev, 0x98, &tmp); 418 tmp |= BIT(4); 419 pci_write_config_byte(pdev, 0x98, tmp); 420 421 tmp = 0x17; 422 pci_write_config_byte(pdev, 0x70f, tmp); 423 } 424 425 static void rtl_pci_init_aspm(struct ieee80211_hw *hw) 426 { 427 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 428 429 _rtl_pci_update_default_setting(hw); 430 431 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { 432 /*Always enable ASPM & Clock Req. */ 433 rtl_pci_enable_aspm(hw); 434 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM); 435 } 436 } 437 438 static void _rtl_pci_io_handler_init(struct device *dev, 439 struct ieee80211_hw *hw) 440 { 441 struct rtl_priv *rtlpriv = rtl_priv(hw); 442 443 rtlpriv->io.dev = dev; 444 445 rtlpriv->io.write8_async = pci_write8_async; 446 rtlpriv->io.write16_async = pci_write16_async; 447 rtlpriv->io.write32_async = pci_write32_async; 448 449 rtlpriv->io.read8_sync = pci_read8_sync; 450 rtlpriv->io.read16_sync = pci_read16_sync; 451 rtlpriv->io.read32_sync = pci_read32_sync; 452 } 453 454 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw, 455 struct sk_buff *skb, 456 struct rtl_tcb_desc *tcb_desc, u8 tid) 457 { 458 struct rtl_priv *rtlpriv = rtl_priv(hw); 459 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 460 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 461 struct sk_buff *next_skb; 462 u8 additionlen = FCS_LEN; 463 464 /* here open is 4, wep/tkip is 8, aes is 12*/ 465 if (info->control.hw_key) 466 additionlen += info->control.hw_key->icv_len; 467 468 /* The most skb num is 6 */ 469 tcb_desc->empkt_num = 0; 470 spin_lock_bh(&rtlpriv->locks.waitq_lock); 471 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) { 472 struct ieee80211_tx_info *next_info; 473 474 next_info = IEEE80211_SKB_CB(next_skb); 475 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) { 476 tcb_desc->empkt_len[tcb_desc->empkt_num] = 477 next_skb->len + additionlen; 478 tcb_desc->empkt_num++; 479 } else { 480 break; 481 } 482 483 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid], 484 next_skb)) 485 break; 486 487 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num) 488 break; 489 } 490 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 491 492 return true; 493 } 494 495 /* just for early mode now */ 496 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw) 497 { 498 struct rtl_priv *rtlpriv = rtl_priv(hw); 499 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 500 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 501 struct sk_buff *skb = NULL; 502 struct ieee80211_tx_info *info = NULL; 503 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 504 int tid; 505 506 if (!rtlpriv->rtlhal.earlymode_enable) 507 return; 508 509 if (rtlpriv->dm.supp_phymode_switch && 510 (rtlpriv->easy_concurrent_ctl.switch_in_process || 511 (rtlpriv->buddy_priv && 512 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process))) 513 return; 514 /* we just use em for BE/BK/VI/VO */ 515 for (tid = 7; tid >= 0; tid--) { 516 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)]; 517 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; 518 519 while (!mac->act_scanning && 520 rtlpriv->psc.rfpwr_state == ERFON) { 521 struct rtl_tcb_desc tcb_desc; 522 523 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 524 525 spin_lock_bh(&rtlpriv->locks.waitq_lock); 526 if (!skb_queue_empty(&mac->skb_waitq[tid]) && 527 (ring->entries - skb_queue_len(&ring->queue) > 528 rtlhal->max_earlymode_num)) { 529 skb = skb_dequeue(&mac->skb_waitq[tid]); 530 } else { 531 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 532 break; 533 } 534 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 535 536 /* Some macaddr can't do early mode. like 537 * multicast/broadcast/no_qos data 538 */ 539 info = IEEE80211_SKB_CB(skb); 540 if (info->flags & IEEE80211_TX_CTL_AMPDU) 541 _rtl_update_earlymode_info(hw, skb, 542 &tcb_desc, tid); 543 544 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc); 545 } 546 } 547 } 548 549 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) 550 { 551 struct rtl_priv *rtlpriv = rtl_priv(hw); 552 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 553 554 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 555 556 while (skb_queue_len(&ring->queue)) { 557 struct sk_buff *skb; 558 struct ieee80211_tx_info *info; 559 __le16 fc; 560 u8 tid; 561 u8 *entry; 562 563 if (rtlpriv->use_new_trx_flow) 564 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 565 else 566 entry = (u8 *)(&ring->desc[ring->idx]); 567 568 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx)) 569 return; 570 ring->idx = (ring->idx + 1) % ring->entries; 571 572 skb = __skb_dequeue(&ring->queue); 573 pci_unmap_single(rtlpci->pdev, 574 rtlpriv->cfg->ops-> 575 get_desc(hw, (u8 *)entry, true, 576 HW_DESC_TXBUFF_ADDR), 577 skb->len, PCI_DMA_TODEVICE); 578 579 /* remove early mode header */ 580 if (rtlpriv->rtlhal.earlymode_enable) 581 skb_pull(skb, EM_HDR_LEN); 582 583 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, 584 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", 585 ring->idx, 586 skb_queue_len(&ring->queue), 587 *(u16 *)(skb->data + 22)); 588 589 if (prio == TXCMD_QUEUE) { 590 dev_kfree_skb(skb); 591 goto tx_status_ok; 592 } 593 594 /* for sw LPS, just after NULL skb send out, we can 595 * sure AP knows we are sleeping, we should not let 596 * rf sleep 597 */ 598 fc = rtl_get_fc(skb); 599 if (ieee80211_is_nullfunc(fc)) { 600 if (ieee80211_has_pm(fc)) { 601 rtlpriv->mac80211.offchan_delay = true; 602 rtlpriv->psc.state_inap = true; 603 } else { 604 rtlpriv->psc.state_inap = false; 605 } 606 } 607 if (ieee80211_is_action(fc)) { 608 struct ieee80211_mgmt *action_frame = 609 (struct ieee80211_mgmt *)skb->data; 610 if (action_frame->u.action.u.ht_smps.action == 611 WLAN_HT_ACTION_SMPS) { 612 dev_kfree_skb(skb); 613 goto tx_status_ok; 614 } 615 } 616 617 /* update tid tx pkt num */ 618 tid = rtl_get_tid(skb); 619 if (tid <= 7) 620 rtlpriv->link_info.tidtx_inperiod[tid]++; 621 622 info = IEEE80211_SKB_CB(skb); 623 ieee80211_tx_info_clear_status(info); 624 625 info->flags |= IEEE80211_TX_STAT_ACK; 626 /*info->status.rates[0].count = 1; */ 627 628 ieee80211_tx_status_irqsafe(hw, skb); 629 630 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) { 631 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, 632 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", 633 prio, ring->idx, 634 skb_queue_len(&ring->queue)); 635 636 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb)); 637 } 638 tx_status_ok: 639 skb = NULL; 640 } 641 642 if (((rtlpriv->link_info.num_rx_inperiod + 643 rtlpriv->link_info.num_tx_inperiod) > 8) || 644 rtlpriv->link_info.num_rx_inperiod > 2) 645 rtl_lps_leave(hw); 646 } 647 648 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, 649 struct sk_buff *new_skb, u8 *entry, 650 int rxring_idx, int desc_idx) 651 { 652 struct rtl_priv *rtlpriv = rtl_priv(hw); 653 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 654 u32 bufferaddress; 655 u8 tmp_one = 1; 656 struct sk_buff *skb; 657 658 if (likely(new_skb)) { 659 skb = new_skb; 660 goto remap; 661 } 662 skb = dev_alloc_skb(rtlpci->rxbuffersize); 663 if (!skb) 664 return 0; 665 666 remap: 667 /* just set skb->cb to mapping addr for pci_unmap_single use */ 668 *((dma_addr_t *)skb->cb) = 669 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb), 670 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 671 bufferaddress = *((dma_addr_t *)skb->cb); 672 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress)) 673 return 0; 674 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb; 675 if (rtlpriv->use_new_trx_flow) { 676 /* skb->cb may be 64 bit address */ 677 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 678 HW_DESC_RX_PREPARE, 679 (u8 *)(dma_addr_t *)skb->cb); 680 } else { 681 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 682 HW_DESC_RXBUFF_ADDR, 683 (u8 *)&bufferaddress); 684 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 685 HW_DESC_RXPKT_LEN, 686 (u8 *)&rtlpci->rxbuffersize); 687 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 688 HW_DESC_RXOWN, 689 (u8 *)&tmp_one); 690 } 691 return 1; 692 } 693 694 /* inorder to receive 8K AMSDU we have set skb to 695 * 9100bytes in init rx ring, but if this packet is 696 * not a AMSDU, this large packet will be sent to 697 * TCP/IP directly, this cause big packet ping fail 698 * like: "ping -s 65507", so here we will realloc skb 699 * based on the true size of packet, Mac80211 700 * Probably will do it better, but does not yet. 701 * 702 * Some platform will fail when alloc skb sometimes. 703 * in this condition, we will send the old skb to 704 * mac80211 directly, this will not cause any other 705 * issues, but only this packet will be lost by TCP/IP 706 */ 707 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw, 708 struct sk_buff *skb, 709 struct ieee80211_rx_status rx_status) 710 { 711 if (unlikely(!rtl_action_proc(hw, skb, false))) { 712 dev_kfree_skb_any(skb); 713 } else { 714 struct sk_buff *uskb = NULL; 715 716 uskb = dev_alloc_skb(skb->len + 128); 717 if (likely(uskb)) { 718 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, 719 sizeof(rx_status)); 720 skb_put_data(uskb, skb->data, skb->len); 721 dev_kfree_skb_any(skb); 722 ieee80211_rx_irqsafe(hw, uskb); 723 } else { 724 ieee80211_rx_irqsafe(hw, skb); 725 } 726 } 727 } 728 729 /*hsisr interrupt handler*/ 730 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw) 731 { 732 struct rtl_priv *rtlpriv = rtl_priv(hw); 733 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 734 735 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR], 736 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) | 737 rtlpci->sys_irq_mask); 738 } 739 740 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) 741 { 742 struct rtl_priv *rtlpriv = rtl_priv(hw); 743 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 744 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE; 745 struct ieee80211_rx_status rx_status = { 0 }; 746 unsigned int count = rtlpci->rxringcount; 747 u8 own; 748 u8 tmp_one; 749 bool unicast = false; 750 u8 hw_queue = 0; 751 unsigned int rx_remained_cnt = 0; 752 struct rtl_stats stats = { 753 .signal = 0, 754 .rate = 0, 755 }; 756 757 /*RX NORMAL PKT */ 758 while (count--) { 759 struct ieee80211_hdr *hdr; 760 __le16 fc; 761 u16 len; 762 /*rx buffer descriptor */ 763 struct rtl_rx_buffer_desc *buffer_desc = NULL; 764 /*if use new trx flow, it means wifi info */ 765 struct rtl_rx_desc *pdesc = NULL; 766 /*rx pkt */ 767 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[ 768 rtlpci->rx_ring[rxring_idx].idx]; 769 struct sk_buff *new_skb; 770 771 if (rtlpriv->use_new_trx_flow) { 772 if (rx_remained_cnt == 0) 773 rx_remained_cnt = 774 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw, 775 hw_queue); 776 if (rx_remained_cnt == 0) 777 return; 778 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[ 779 rtlpci->rx_ring[rxring_idx].idx]; 780 pdesc = (struct rtl_rx_desc *)skb->data; 781 } else { /* rx descriptor */ 782 pdesc = &rtlpci->rx_ring[rxring_idx].desc[ 783 rtlpci->rx_ring[rxring_idx].idx]; 784 785 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 786 false, 787 HW_DESC_OWN); 788 if (own) /* wait data to be filled by hardware */ 789 return; 790 } 791 792 /* Reaching this point means: data is filled already 793 * AAAAAAttention !!! 794 * We can NOT access 'skb' before 'pci_unmap_single' 795 */ 796 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), 797 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 798 799 /* get a new skb - if fail, old one will be reused */ 800 new_skb = dev_alloc_skb(rtlpci->rxbuffersize); 801 if (unlikely(!new_skb)) 802 goto no_new; 803 memset(&rx_status, 0, sizeof(rx_status)); 804 rtlpriv->cfg->ops->query_rx_desc(hw, &stats, 805 &rx_status, (u8 *)pdesc, skb); 806 807 if (rtlpriv->use_new_trx_flow) 808 rtlpriv->cfg->ops->rx_check_dma_ok(hw, 809 (u8 *)buffer_desc, 810 hw_queue); 811 812 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false, 813 HW_DESC_RXPKT_LEN); 814 815 if (skb->end - skb->tail > len) { 816 skb_put(skb, len); 817 if (rtlpriv->use_new_trx_flow) 818 skb_reserve(skb, stats.rx_drvinfo_size + 819 stats.rx_bufshift + 24); 820 else 821 skb_reserve(skb, stats.rx_drvinfo_size + 822 stats.rx_bufshift); 823 } else { 824 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 825 "skb->end - skb->tail = %d, len is %d\n", 826 skb->end - skb->tail, len); 827 dev_kfree_skb_any(skb); 828 goto new_trx_end; 829 } 830 /* handle command packet here */ 831 if (rtlpriv->cfg->ops->rx_command_packet && 832 rtlpriv->cfg->ops->rx_command_packet(hw, &stats, skb)) { 833 dev_kfree_skb_any(skb); 834 goto new_trx_end; 835 } 836 837 /* NOTICE This can not be use for mac80211, 838 * this is done in mac80211 code, 839 * if done here sec DHCP will fail 840 * skb_trim(skb, skb->len - 4); 841 */ 842 843 hdr = rtl_get_hdr(skb); 844 fc = rtl_get_fc(skb); 845 846 if (!stats.crc && !stats.hwerror) { 847 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, 848 sizeof(rx_status)); 849 850 if (is_broadcast_ether_addr(hdr->addr1)) { 851 ;/*TODO*/ 852 } else if (is_multicast_ether_addr(hdr->addr1)) { 853 ;/*TODO*/ 854 } else { 855 unicast = true; 856 rtlpriv->stats.rxbytesunicast += skb->len; 857 } 858 rtl_is_special_data(hw, skb, false, true); 859 860 if (ieee80211_is_data(fc)) { 861 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX); 862 if (unicast) 863 rtlpriv->link_info.num_rx_inperiod++; 864 } 865 866 rtl_collect_scan_list(hw, skb); 867 868 /* static bcn for roaming */ 869 rtl_beacon_statistic(hw, skb); 870 rtl_p2p_info(hw, (void *)skb->data, skb->len); 871 /* for sw lps */ 872 rtl_swlps_beacon(hw, (void *)skb->data, skb->len); 873 rtl_recognize_peer(hw, (void *)skb->data, skb->len); 874 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP && 875 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G && 876 (ieee80211_is_beacon(fc) || 877 ieee80211_is_probe_resp(fc))) { 878 dev_kfree_skb_any(skb); 879 } else { 880 _rtl_pci_rx_to_mac80211(hw, skb, rx_status); 881 } 882 } else { 883 dev_kfree_skb_any(skb); 884 } 885 new_trx_end: 886 if (rtlpriv->use_new_trx_flow) { 887 rtlpci->rx_ring[hw_queue].next_rx_rp += 1; 888 rtlpci->rx_ring[hw_queue].next_rx_rp %= 889 RTL_PCI_MAX_RX_COUNT; 890 891 rx_remained_cnt--; 892 rtl_write_word(rtlpriv, 0x3B4, 893 rtlpci->rx_ring[hw_queue].next_rx_rp); 894 } 895 if (((rtlpriv->link_info.num_rx_inperiod + 896 rtlpriv->link_info.num_tx_inperiod) > 8) || 897 rtlpriv->link_info.num_rx_inperiod > 2) 898 rtl_lps_leave(hw); 899 skb = new_skb; 900 no_new: 901 if (rtlpriv->use_new_trx_flow) { 902 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc, 903 rxring_idx, 904 rtlpci->rx_ring[rxring_idx].idx); 905 } else { 906 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc, 907 rxring_idx, 908 rtlpci->rx_ring[rxring_idx].idx); 909 if (rtlpci->rx_ring[rxring_idx].idx == 910 rtlpci->rxringcount - 1) 911 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, 912 false, 913 HW_DESC_RXERO, 914 (u8 *)&tmp_one); 915 } 916 rtlpci->rx_ring[rxring_idx].idx = 917 (rtlpci->rx_ring[rxring_idx].idx + 1) % 918 rtlpci->rxringcount; 919 } 920 } 921 922 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) 923 { 924 struct ieee80211_hw *hw = dev_id; 925 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 926 struct rtl_priv *rtlpriv = rtl_priv(hw); 927 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 928 unsigned long flags; 929 struct rtl_int intvec = {0}; 930 931 irqreturn_t ret = IRQ_HANDLED; 932 933 if (rtlpci->irq_enabled == 0) 934 return ret; 935 936 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 937 rtlpriv->cfg->ops->disable_interrupt(hw); 938 939 /*read ISR: 4/8bytes */ 940 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec); 941 942 /*Shared IRQ or HW disappeared */ 943 if (!intvec.inta || intvec.inta == 0xffff) 944 goto done; 945 946 /*<1> beacon related */ 947 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) 948 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 949 "beacon ok interrupt!\n"); 950 951 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) 952 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 953 "beacon err interrupt!\n"); 954 955 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) 956 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); 957 958 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) { 959 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 960 "prepare beacon for interrupt!\n"); 961 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet); 962 } 963 964 /*<2> Tx related */ 965 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW])) 966 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); 967 968 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) { 969 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 970 "Manage ok interrupt!\n"); 971 _rtl_pci_tx_isr(hw, MGNT_QUEUE); 972 } 973 974 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) { 975 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 976 "HIGH_QUEUE ok interrupt!\n"); 977 _rtl_pci_tx_isr(hw, HIGH_QUEUE); 978 } 979 980 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) { 981 rtlpriv->link_info.num_tx_inperiod++; 982 983 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 984 "BK Tx OK interrupt!\n"); 985 _rtl_pci_tx_isr(hw, BK_QUEUE); 986 } 987 988 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) { 989 rtlpriv->link_info.num_tx_inperiod++; 990 991 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 992 "BE TX OK interrupt!\n"); 993 _rtl_pci_tx_isr(hw, BE_QUEUE); 994 } 995 996 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) { 997 rtlpriv->link_info.num_tx_inperiod++; 998 999 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1000 "VI TX OK interrupt!\n"); 1001 _rtl_pci_tx_isr(hw, VI_QUEUE); 1002 } 1003 1004 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) { 1005 rtlpriv->link_info.num_tx_inperiod++; 1006 1007 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1008 "Vo TX OK interrupt!\n"); 1009 _rtl_pci_tx_isr(hw, VO_QUEUE); 1010 } 1011 1012 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) { 1013 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) { 1014 rtlpriv->link_info.num_tx_inperiod++; 1015 1016 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1017 "H2C TX OK interrupt!\n"); 1018 _rtl_pci_tx_isr(hw, H2C_QUEUE); 1019 } 1020 } 1021 1022 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) { 1023 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) { 1024 rtlpriv->link_info.num_tx_inperiod++; 1025 1026 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1027 "CMD TX OK interrupt!\n"); 1028 _rtl_pci_tx_isr(hw, TXCMD_QUEUE); 1029 } 1030 } 1031 1032 /*<3> Rx related */ 1033 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) { 1034 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); 1035 _rtl_pci_rx_interrupt(hw); 1036 } 1037 1038 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) { 1039 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1040 "rx descriptor unavailable!\n"); 1041 _rtl_pci_rx_interrupt(hw); 1042 } 1043 1044 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) { 1045 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); 1046 _rtl_pci_rx_interrupt(hw); 1047 } 1048 1049 /*<4> fw related*/ 1050 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { 1051 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) { 1052 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1053 "firmware interrupt!\n"); 1054 queue_delayed_work(rtlpriv->works.rtl_wq, 1055 &rtlpriv->works.fwevt_wq, 0); 1056 } 1057 } 1058 1059 /*<5> hsisr related*/ 1060 /* Only 8188EE & 8723BE Supported. 1061 * If Other ICs Come in, System will corrupt, 1062 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR] 1063 * are not initialized 1064 */ 1065 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE || 1066 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) { 1067 if (unlikely(intvec.inta & 1068 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) { 1069 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1070 "hsisr interrupt!\n"); 1071 _rtl_pci_hs_interrupt(hw); 1072 } 1073 } 1074 1075 if (rtlpriv->rtlhal.earlymode_enable) 1076 tasklet_schedule(&rtlpriv->works.irq_tasklet); 1077 1078 done: 1079 rtlpriv->cfg->ops->enable_interrupt(hw); 1080 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1081 return ret; 1082 } 1083 1084 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw) 1085 { 1086 _rtl_pci_tx_chk_waitq(hw); 1087 } 1088 1089 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw) 1090 { 1091 struct rtl_priv *rtlpriv = rtl_priv(hw); 1092 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1093 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1094 struct rtl8192_tx_ring *ring = NULL; 1095 struct ieee80211_hdr *hdr = NULL; 1096 struct ieee80211_tx_info *info = NULL; 1097 struct sk_buff *pskb = NULL; 1098 struct rtl_tx_desc *pdesc = NULL; 1099 struct rtl_tcb_desc tcb_desc; 1100 /*This is for new trx flow*/ 1101 struct rtl_tx_buffer_desc *pbuffer_desc = NULL; 1102 u8 temp_one = 1; 1103 u8 *entry; 1104 1105 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 1106 ring = &rtlpci->tx_ring[BEACON_QUEUE]; 1107 pskb = __skb_dequeue(&ring->queue); 1108 if (rtlpriv->use_new_trx_flow) 1109 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1110 else 1111 entry = (u8 *)(&ring->desc[ring->idx]); 1112 if (pskb) { 1113 pci_unmap_single(rtlpci->pdev, 1114 rtlpriv->cfg->ops->get_desc( 1115 hw, (u8 *)entry, true, HW_DESC_TXBUFF_ADDR), 1116 pskb->len, PCI_DMA_TODEVICE); 1117 kfree_skb(pskb); 1118 } 1119 1120 /*NB: the beacon data buffer must be 32-bit aligned. */ 1121 pskb = ieee80211_beacon_get(hw, mac->vif); 1122 if (!pskb) 1123 return; 1124 hdr = rtl_get_hdr(pskb); 1125 info = IEEE80211_SKB_CB(pskb); 1126 pdesc = &ring->desc[0]; 1127 if (rtlpriv->use_new_trx_flow) 1128 pbuffer_desc = &ring->buffer_desc[0]; 1129 1130 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1131 (u8 *)pbuffer_desc, info, NULL, pskb, 1132 BEACON_QUEUE, &tcb_desc); 1133 1134 __skb_queue_tail(&ring->queue, pskb); 1135 1136 if (rtlpriv->use_new_trx_flow) { 1137 temp_one = 4; 1138 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true, 1139 HW_DESC_OWN, (u8 *)&temp_one); 1140 } else { 1141 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN, 1142 &temp_one); 1143 } 1144 } 1145 1146 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw) 1147 { 1148 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1149 struct rtl_priv *rtlpriv = rtl_priv(hw); 1150 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1151 u8 i; 1152 u16 desc_num; 1153 1154 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) 1155 desc_num = TX_DESC_NUM_92E; 1156 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) 1157 desc_num = TX_DESC_NUM_8822B; 1158 else 1159 desc_num = RT_TXDESC_NUM; 1160 1161 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1162 rtlpci->txringcount[i] = desc_num; 1163 1164 /*we just alloc 2 desc for beacon queue, 1165 *because we just need first desc in hw beacon. 1166 */ 1167 rtlpci->txringcount[BEACON_QUEUE] = 2; 1168 1169 /*BE queue need more descriptor for performance 1170 *consideration or, No more tx desc will happen, 1171 *and may cause mac80211 mem leakage. 1172 */ 1173 if (!rtl_priv(hw)->use_new_trx_flow) 1174 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE; 1175 1176 rtlpci->rxbuffersize = 9100; /*2048/1024; */ 1177 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */ 1178 } 1179 1180 static void _rtl_pci_init_struct(struct ieee80211_hw *hw, 1181 struct pci_dev *pdev) 1182 { 1183 struct rtl_priv *rtlpriv = rtl_priv(hw); 1184 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1185 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1186 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1187 1188 rtlpci->up_first_time = true; 1189 rtlpci->being_init_adapter = false; 1190 1191 rtlhal->hw = hw; 1192 rtlpci->pdev = pdev; 1193 1194 /*Tx/Rx related var */ 1195 _rtl_pci_init_trx_var(hw); 1196 1197 /*IBSS*/ 1198 mac->beacon_interval = 100; 1199 1200 /*AMPDU*/ 1201 mac->min_space_cfg = 0; 1202 mac->max_mss_density = 0; 1203 /*set sane AMPDU defaults */ 1204 mac->current_ampdu_density = 7; 1205 mac->current_ampdu_factor = 3; 1206 1207 /*Retry Limit*/ 1208 mac->retry_short = 7; 1209 mac->retry_long = 7; 1210 1211 /*QOS*/ 1212 rtlpci->acm_method = EACMWAY2_SW; 1213 1214 /*task */ 1215 tasklet_init(&rtlpriv->works.irq_tasklet, 1216 (void (*)(unsigned long))_rtl_pci_irq_tasklet, 1217 (unsigned long)hw); 1218 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet, 1219 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet, 1220 (unsigned long)hw); 1221 INIT_WORK(&rtlpriv->works.lps_change_work, 1222 rtl_lps_change_work_callback); 1223 } 1224 1225 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, 1226 unsigned int prio, unsigned int entries) 1227 { 1228 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1229 struct rtl_priv *rtlpriv = rtl_priv(hw); 1230 struct rtl_tx_buffer_desc *buffer_desc; 1231 struct rtl_tx_desc *desc; 1232 dma_addr_t buffer_desc_dma, desc_dma; 1233 u32 nextdescaddress; 1234 int i; 1235 1236 /* alloc tx buffer desc for new trx flow*/ 1237 if (rtlpriv->use_new_trx_flow) { 1238 buffer_desc = 1239 pci_zalloc_consistent(rtlpci->pdev, 1240 sizeof(*buffer_desc) * entries, 1241 &buffer_desc_dma); 1242 1243 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) { 1244 pr_err("Cannot allocate TX ring (prio = %d)\n", 1245 prio); 1246 return -ENOMEM; 1247 } 1248 1249 rtlpci->tx_ring[prio].buffer_desc = buffer_desc; 1250 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma; 1251 1252 rtlpci->tx_ring[prio].cur_tx_rp = 0; 1253 rtlpci->tx_ring[prio].cur_tx_wp = 0; 1254 } 1255 1256 /* alloc dma for this ring */ 1257 desc = pci_zalloc_consistent(rtlpci->pdev, 1258 sizeof(*desc) * entries, &desc_dma); 1259 1260 if (!desc || (unsigned long)desc & 0xFF) { 1261 pr_err("Cannot allocate TX ring (prio = %d)\n", prio); 1262 return -ENOMEM; 1263 } 1264 1265 rtlpci->tx_ring[prio].desc = desc; 1266 rtlpci->tx_ring[prio].dma = desc_dma; 1267 1268 rtlpci->tx_ring[prio].idx = 0; 1269 rtlpci->tx_ring[prio].entries = entries; 1270 skb_queue_head_init(&rtlpci->tx_ring[prio].queue); 1271 1272 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", 1273 prio, desc); 1274 1275 /* init every desc in this ring */ 1276 if (!rtlpriv->use_new_trx_flow) { 1277 for (i = 0; i < entries; i++) { 1278 nextdescaddress = (u32)desc_dma + 1279 ((i + 1) % entries) * 1280 sizeof(*desc); 1281 1282 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i], 1283 true, 1284 HW_DESC_TX_NEXTDESC_ADDR, 1285 (u8 *)&nextdescaddress); 1286 } 1287 } 1288 return 0; 1289 } 1290 1291 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1292 { 1293 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1294 struct rtl_priv *rtlpriv = rtl_priv(hw); 1295 int i; 1296 1297 if (rtlpriv->use_new_trx_flow) { 1298 struct rtl_rx_buffer_desc *entry = NULL; 1299 /* alloc dma for this ring */ 1300 rtlpci->rx_ring[rxring_idx].buffer_desc = 1301 pci_zalloc_consistent(rtlpci->pdev, 1302 sizeof(*rtlpci->rx_ring[rxring_idx]. 1303 buffer_desc) * 1304 rtlpci->rxringcount, 1305 &rtlpci->rx_ring[rxring_idx].dma); 1306 if (!rtlpci->rx_ring[rxring_idx].buffer_desc || 1307 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) { 1308 pr_err("Cannot allocate RX ring\n"); 1309 return -ENOMEM; 1310 } 1311 1312 /* init every desc in this ring */ 1313 rtlpci->rx_ring[rxring_idx].idx = 0; 1314 for (i = 0; i < rtlpci->rxringcount; i++) { 1315 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i]; 1316 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1317 rxring_idx, i)) 1318 return -ENOMEM; 1319 } 1320 } else { 1321 struct rtl_rx_desc *entry = NULL; 1322 u8 tmp_one = 1; 1323 /* alloc dma for this ring */ 1324 rtlpci->rx_ring[rxring_idx].desc = 1325 pci_zalloc_consistent(rtlpci->pdev, 1326 sizeof(*rtlpci->rx_ring[rxring_idx]. 1327 desc) * rtlpci->rxringcount, 1328 &rtlpci->rx_ring[rxring_idx].dma); 1329 if (!rtlpci->rx_ring[rxring_idx].desc || 1330 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) { 1331 pr_err("Cannot allocate RX ring\n"); 1332 return -ENOMEM; 1333 } 1334 1335 /* init every desc in this ring */ 1336 rtlpci->rx_ring[rxring_idx].idx = 0; 1337 1338 for (i = 0; i < rtlpci->rxringcount; i++) { 1339 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1340 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1341 rxring_idx, i)) 1342 return -ENOMEM; 1343 } 1344 1345 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1346 HW_DESC_RXERO, &tmp_one); 1347 } 1348 return 0; 1349 } 1350 1351 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw, 1352 unsigned int prio) 1353 { 1354 struct rtl_priv *rtlpriv = rtl_priv(hw); 1355 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1356 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 1357 1358 /* free every desc in this ring */ 1359 while (skb_queue_len(&ring->queue)) { 1360 u8 *entry; 1361 struct sk_buff *skb = __skb_dequeue(&ring->queue); 1362 1363 if (rtlpriv->use_new_trx_flow) 1364 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1365 else 1366 entry = (u8 *)(&ring->desc[ring->idx]); 1367 1368 pci_unmap_single(rtlpci->pdev, 1369 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1370 true, 1371 HW_DESC_TXBUFF_ADDR), 1372 skb->len, PCI_DMA_TODEVICE); 1373 kfree_skb(skb); 1374 ring->idx = (ring->idx + 1) % ring->entries; 1375 } 1376 1377 /* free dma of this ring */ 1378 pci_free_consistent(rtlpci->pdev, 1379 sizeof(*ring->desc) * ring->entries, 1380 ring->desc, ring->dma); 1381 ring->desc = NULL; 1382 if (rtlpriv->use_new_trx_flow) { 1383 pci_free_consistent(rtlpci->pdev, 1384 sizeof(*ring->buffer_desc) * ring->entries, 1385 ring->buffer_desc, ring->buffer_desc_dma); 1386 ring->buffer_desc = NULL; 1387 } 1388 } 1389 1390 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1391 { 1392 struct rtl_priv *rtlpriv = rtl_priv(hw); 1393 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1394 int i; 1395 1396 /* free every desc in this ring */ 1397 for (i = 0; i < rtlpci->rxringcount; i++) { 1398 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i]; 1399 1400 if (!skb) 1401 continue; 1402 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), 1403 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 1404 kfree_skb(skb); 1405 } 1406 1407 /* free dma of this ring */ 1408 if (rtlpriv->use_new_trx_flow) { 1409 pci_free_consistent(rtlpci->pdev, 1410 sizeof(*rtlpci->rx_ring[rxring_idx]. 1411 buffer_desc) * rtlpci->rxringcount, 1412 rtlpci->rx_ring[rxring_idx].buffer_desc, 1413 rtlpci->rx_ring[rxring_idx].dma); 1414 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL; 1415 } else { 1416 pci_free_consistent(rtlpci->pdev, 1417 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1418 rtlpci->rxringcount, 1419 rtlpci->rx_ring[rxring_idx].desc, 1420 rtlpci->rx_ring[rxring_idx].dma); 1421 rtlpci->rx_ring[rxring_idx].desc = NULL; 1422 } 1423 } 1424 1425 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw) 1426 { 1427 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1428 int ret; 1429 int i, rxring_idx; 1430 1431 /* rxring_idx 0:RX_MPDU_QUEUE 1432 * rxring_idx 1:RX_CMD_QUEUE 1433 */ 1434 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1435 ret = _rtl_pci_init_rx_ring(hw, rxring_idx); 1436 if (ret) 1437 return ret; 1438 } 1439 1440 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1441 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]); 1442 if (ret) 1443 goto err_free_rings; 1444 } 1445 1446 return 0; 1447 1448 err_free_rings: 1449 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1450 _rtl_pci_free_rx_ring(hw, rxring_idx); 1451 1452 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1453 if (rtlpci->tx_ring[i].desc || 1454 rtlpci->tx_ring[i].buffer_desc) 1455 _rtl_pci_free_tx_ring(hw, i); 1456 1457 return 1; 1458 } 1459 1460 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw) 1461 { 1462 u32 i, rxring_idx; 1463 1464 /*free rx rings */ 1465 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1466 _rtl_pci_free_rx_ring(hw, rxring_idx); 1467 1468 /*free tx rings */ 1469 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1470 _rtl_pci_free_tx_ring(hw, i); 1471 1472 return 0; 1473 } 1474 1475 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw) 1476 { 1477 struct rtl_priv *rtlpriv = rtl_priv(hw); 1478 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1479 int i, rxring_idx; 1480 unsigned long flags; 1481 u8 tmp_one = 1; 1482 u32 bufferaddress; 1483 /* rxring_idx 0:RX_MPDU_QUEUE */ 1484 /* rxring_idx 1:RX_CMD_QUEUE */ 1485 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1486 /* force the rx_ring[RX_MPDU_QUEUE/ 1487 * RX_CMD_QUEUE].idx to the first one 1488 *new trx flow, do nothing 1489 */ 1490 if (!rtlpriv->use_new_trx_flow && 1491 rtlpci->rx_ring[rxring_idx].desc) { 1492 struct rtl_rx_desc *entry = NULL; 1493 1494 rtlpci->rx_ring[rxring_idx].idx = 0; 1495 for (i = 0; i < rtlpci->rxringcount; i++) { 1496 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1497 bufferaddress = 1498 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1499 false, HW_DESC_RXBUFF_ADDR); 1500 memset((u8 *)entry, 0, 1501 sizeof(*rtlpci->rx_ring 1502 [rxring_idx].desc));/*clear one entry*/ 1503 if (rtlpriv->use_new_trx_flow) { 1504 rtlpriv->cfg->ops->set_desc(hw, 1505 (u8 *)entry, false, 1506 HW_DESC_RX_PREPARE, 1507 (u8 *)&bufferaddress); 1508 } else { 1509 rtlpriv->cfg->ops->set_desc(hw, 1510 (u8 *)entry, false, 1511 HW_DESC_RXBUFF_ADDR, 1512 (u8 *)&bufferaddress); 1513 rtlpriv->cfg->ops->set_desc(hw, 1514 (u8 *)entry, false, 1515 HW_DESC_RXPKT_LEN, 1516 (u8 *)&rtlpci->rxbuffersize); 1517 rtlpriv->cfg->ops->set_desc(hw, 1518 (u8 *)entry, false, 1519 HW_DESC_RXOWN, 1520 (u8 *)&tmp_one); 1521 } 1522 } 1523 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1524 HW_DESC_RXERO, (u8 *)&tmp_one); 1525 } 1526 rtlpci->rx_ring[rxring_idx].idx = 0; 1527 } 1528 1529 /*after reset, release previous pending packet, 1530 *and force the tx idx to the first one 1531 */ 1532 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1533 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1534 if (rtlpci->tx_ring[i].desc || 1535 rtlpci->tx_ring[i].buffer_desc) { 1536 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i]; 1537 1538 while (skb_queue_len(&ring->queue)) { 1539 u8 *entry; 1540 struct sk_buff *skb = 1541 __skb_dequeue(&ring->queue); 1542 if (rtlpriv->use_new_trx_flow) 1543 entry = (u8 *)(&ring->buffer_desc 1544 [ring->idx]); 1545 else 1546 entry = (u8 *)(&ring->desc[ring->idx]); 1547 1548 pci_unmap_single(rtlpci->pdev, 1549 rtlpriv->cfg->ops-> 1550 get_desc(hw, (u8 *) 1551 entry, 1552 true, 1553 HW_DESC_TXBUFF_ADDR), 1554 skb->len, PCI_DMA_TODEVICE); 1555 dev_kfree_skb_irq(skb); 1556 ring->idx = (ring->idx + 1) % ring->entries; 1557 } 1558 1559 if (rtlpriv->use_new_trx_flow) { 1560 rtlpci->tx_ring[i].cur_tx_rp = 0; 1561 rtlpci->tx_ring[i].cur_tx_wp = 0; 1562 } 1563 1564 ring->idx = 0; 1565 ring->entries = rtlpci->txringcount[i]; 1566 } 1567 } 1568 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1569 1570 return 0; 1571 } 1572 1573 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw, 1574 struct ieee80211_sta *sta, 1575 struct sk_buff *skb) 1576 { 1577 struct rtl_priv *rtlpriv = rtl_priv(hw); 1578 struct rtl_sta_info *sta_entry = NULL; 1579 u8 tid = rtl_get_tid(skb); 1580 __le16 fc = rtl_get_fc(skb); 1581 1582 if (!sta) 1583 return false; 1584 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1585 1586 if (!rtlpriv->rtlhal.earlymode_enable) 1587 return false; 1588 if (ieee80211_is_nullfunc(fc)) 1589 return false; 1590 if (ieee80211_is_qos_nullfunc(fc)) 1591 return false; 1592 if (ieee80211_is_pspoll(fc)) 1593 return false; 1594 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL) 1595 return false; 1596 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE) 1597 return false; 1598 if (tid > 7) 1599 return false; 1600 1601 /* maybe every tid should be checked */ 1602 if (!rtlpriv->link_info.higher_busytxtraffic[tid]) 1603 return false; 1604 1605 spin_lock_bh(&rtlpriv->locks.waitq_lock); 1606 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb); 1607 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 1608 1609 return true; 1610 } 1611 1612 static int rtl_pci_tx(struct ieee80211_hw *hw, 1613 struct ieee80211_sta *sta, 1614 struct sk_buff *skb, 1615 struct rtl_tcb_desc *ptcb_desc) 1616 { 1617 struct rtl_priv *rtlpriv = rtl_priv(hw); 1618 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1619 struct rtl8192_tx_ring *ring; 1620 struct rtl_tx_desc *pdesc; 1621 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL; 1622 u16 idx; 1623 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb); 1624 unsigned long flags; 1625 struct ieee80211_hdr *hdr = rtl_get_hdr(skb); 1626 __le16 fc = rtl_get_fc(skb); 1627 u8 *pda_addr = hdr->addr1; 1628 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1629 u8 own; 1630 u8 temp_one = 1; 1631 1632 if (ieee80211_is_mgmt(fc)) 1633 rtl_tx_mgmt_proc(hw, skb); 1634 1635 if (rtlpriv->psc.sw_ps_enabled) { 1636 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) && 1637 !ieee80211_has_pm(fc)) 1638 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1639 } 1640 1641 rtl_action_proc(hw, skb, true); 1642 1643 if (is_multicast_ether_addr(pda_addr)) 1644 rtlpriv->stats.txbytesmulticast += skb->len; 1645 else if (is_broadcast_ether_addr(pda_addr)) 1646 rtlpriv->stats.txbytesbroadcast += skb->len; 1647 else 1648 rtlpriv->stats.txbytesunicast += skb->len; 1649 1650 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1651 ring = &rtlpci->tx_ring[hw_queue]; 1652 if (hw_queue != BEACON_QUEUE) { 1653 if (rtlpriv->use_new_trx_flow) 1654 idx = ring->cur_tx_wp; 1655 else 1656 idx = (ring->idx + skb_queue_len(&ring->queue)) % 1657 ring->entries; 1658 } else { 1659 idx = 0; 1660 } 1661 1662 pdesc = &ring->desc[idx]; 1663 if (rtlpriv->use_new_trx_flow) { 1664 ptx_bd_desc = &ring->buffer_desc[idx]; 1665 } else { 1666 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 1667 true, HW_DESC_OWN); 1668 1669 if (own == 1 && hw_queue != BEACON_QUEUE) { 1670 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1671 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1672 hw_queue, ring->idx, idx, 1673 skb_queue_len(&ring->queue)); 1674 1675 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, 1676 flags); 1677 return skb->len; 1678 } 1679 } 1680 1681 if (rtlpriv->cfg->ops->get_available_desc && 1682 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) { 1683 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1684 "get_available_desc fail\n"); 1685 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1686 return skb->len; 1687 } 1688 1689 if (ieee80211_is_data(fc)) 1690 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX); 1691 1692 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1693 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc); 1694 1695 __skb_queue_tail(&ring->queue, skb); 1696 1697 if (rtlpriv->use_new_trx_flow) { 1698 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1699 HW_DESC_OWN, &hw_queue); 1700 } else { 1701 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1702 HW_DESC_OWN, &temp_one); 1703 } 1704 1705 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 && 1706 hw_queue != BEACON_QUEUE) { 1707 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 1708 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1709 hw_queue, ring->idx, idx, 1710 skb_queue_len(&ring->queue)); 1711 1712 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 1713 } 1714 1715 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1716 1717 rtlpriv->cfg->ops->tx_polling(hw, hw_queue); 1718 1719 return 0; 1720 } 1721 1722 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1723 { 1724 struct rtl_priv *rtlpriv = rtl_priv(hw); 1725 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1726 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1727 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1728 u16 i = 0; 1729 int queue_id; 1730 struct rtl8192_tx_ring *ring; 1731 1732 if (mac->skip_scan) 1733 return; 1734 1735 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) { 1736 u32 queue_len; 1737 1738 if (((queues >> queue_id) & 0x1) == 0) { 1739 queue_id--; 1740 continue; 1741 } 1742 ring = &pcipriv->dev.tx_ring[queue_id]; 1743 queue_len = skb_queue_len(&ring->queue); 1744 if (queue_len == 0 || queue_id == BEACON_QUEUE || 1745 queue_id == TXCMD_QUEUE) { 1746 queue_id--; 1747 continue; 1748 } else { 1749 msleep(20); 1750 i++; 1751 } 1752 1753 /* we just wait 1s for all queues */ 1754 if (rtlpriv->psc.rfpwr_state == ERFOFF || 1755 is_hal_stop(rtlhal) || i >= 200) 1756 return; 1757 } 1758 } 1759 1760 static void rtl_pci_deinit(struct ieee80211_hw *hw) 1761 { 1762 struct rtl_priv *rtlpriv = rtl_priv(hw); 1763 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1764 1765 _rtl_pci_deinit_trx_ring(hw); 1766 1767 synchronize_irq(rtlpci->pdev->irq); 1768 tasklet_kill(&rtlpriv->works.irq_tasklet); 1769 cancel_work_sync(&rtlpriv->works.lps_change_work); 1770 1771 flush_workqueue(rtlpriv->works.rtl_wq); 1772 destroy_workqueue(rtlpriv->works.rtl_wq); 1773 } 1774 1775 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev) 1776 { 1777 int err; 1778 1779 _rtl_pci_init_struct(hw, pdev); 1780 1781 err = _rtl_pci_init_trx_ring(hw); 1782 if (err) { 1783 pr_err("tx ring initialization failed\n"); 1784 return err; 1785 } 1786 1787 return 0; 1788 } 1789 1790 static int rtl_pci_start(struct ieee80211_hw *hw) 1791 { 1792 struct rtl_priv *rtlpriv = rtl_priv(hw); 1793 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1794 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1795 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1796 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw)); 1797 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops; 1798 1799 int err; 1800 1801 rtl_pci_reset_trx_ring(hw); 1802 1803 rtlpci->driver_is_goingto_unload = false; 1804 if (rtlpriv->cfg->ops->get_btc_status && 1805 rtlpriv->cfg->ops->get_btc_status()) { 1806 rtlpriv->btcoexist.btc_info.ap_num = 36; 1807 btc_ops->btc_init_variables(rtlpriv); 1808 btc_ops->btc_init_hal_vars(rtlpriv); 1809 } else if (btc_ops) { 1810 btc_ops->btc_init_variables_wifi_only(rtlpriv); 1811 } 1812 1813 err = rtlpriv->cfg->ops->hw_init(hw); 1814 if (err) { 1815 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1816 "Failed to config hardware!\n"); 1817 return err; 1818 } 1819 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, 1820 &rtlmac->retry_long); 1821 1822 rtlpriv->cfg->ops->enable_interrupt(hw); 1823 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); 1824 1825 rtl_init_rx_config(hw); 1826 1827 /*should be after adapter start and interrupt enable. */ 1828 set_hal_start(rtlhal); 1829 1830 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1831 1832 rtlpci->up_first_time = false; 1833 1834 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__); 1835 return 0; 1836 } 1837 1838 static void rtl_pci_stop(struct ieee80211_hw *hw) 1839 { 1840 struct rtl_priv *rtlpriv = rtl_priv(hw); 1841 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1842 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1843 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1844 unsigned long flags; 1845 u8 rf_timeout = 0; 1846 1847 if (rtlpriv->cfg->ops->get_btc_status()) 1848 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv); 1849 1850 if (rtlpriv->btcoexist.btc_ops) 1851 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv); 1852 1853 /*should be before disable interrupt&adapter 1854 *and will do it immediately. 1855 */ 1856 set_hal_stop(rtlhal); 1857 1858 rtlpci->driver_is_goingto_unload = true; 1859 rtlpriv->cfg->ops->disable_interrupt(hw); 1860 cancel_work_sync(&rtlpriv->works.lps_change_work); 1861 1862 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1863 while (ppsc->rfchange_inprogress) { 1864 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1865 if (rf_timeout > 100) { 1866 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1867 break; 1868 } 1869 mdelay(1); 1870 rf_timeout++; 1871 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1872 } 1873 ppsc->rfchange_inprogress = true; 1874 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1875 1876 rtlpriv->cfg->ops->hw_disable(hw); 1877 /* some things are not needed if firmware not available */ 1878 if (!rtlpriv->max_fw_size) 1879 return; 1880 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1881 1882 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1883 ppsc->rfchange_inprogress = false; 1884 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1885 1886 rtl_pci_enable_aspm(hw); 1887 } 1888 1889 static bool _rtl_pci_find_adapter(struct pci_dev *pdev, 1890 struct ieee80211_hw *hw) 1891 { 1892 struct rtl_priv *rtlpriv = rtl_priv(hw); 1893 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1894 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1895 struct pci_dev *bridge_pdev = pdev->bus->self; 1896 u16 venderid; 1897 u16 deviceid; 1898 u8 revisionid; 1899 u16 irqline; 1900 u8 tmp; 1901 1902 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1903 venderid = pdev->vendor; 1904 deviceid = pdev->device; 1905 pci_read_config_byte(pdev, 0x8, &revisionid); 1906 pci_read_config_word(pdev, 0x3C, &irqline); 1907 1908 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses 1909 * r8192e_pci, and RTL8192SE, which uses this driver. If the 1910 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then 1911 * the correct driver is r8192e_pci, thus this routine should 1912 * return false. 1913 */ 1914 if (deviceid == RTL_PCI_8192SE_DID && 1915 revisionid == RTL_PCI_REVISION_ID_8192PCIE) 1916 return false; 1917 1918 if (deviceid == RTL_PCI_8192_DID || 1919 deviceid == RTL_PCI_0044_DID || 1920 deviceid == RTL_PCI_0047_DID || 1921 deviceid == RTL_PCI_8192SE_DID || 1922 deviceid == RTL_PCI_8174_DID || 1923 deviceid == RTL_PCI_8173_DID || 1924 deviceid == RTL_PCI_8172_DID || 1925 deviceid == RTL_PCI_8171_DID) { 1926 switch (revisionid) { 1927 case RTL_PCI_REVISION_ID_8192PCIE: 1928 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1929 "8192 PCI-E is found - vid/did=%x/%x\n", 1930 venderid, deviceid); 1931 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E; 1932 return false; 1933 case RTL_PCI_REVISION_ID_8192SE: 1934 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1935 "8192SE is found - vid/did=%x/%x\n", 1936 venderid, deviceid); 1937 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1938 break; 1939 default: 1940 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1941 "Err: Unknown device - vid/did=%x/%x\n", 1942 venderid, deviceid); 1943 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1944 break; 1945 } 1946 } else if (deviceid == RTL_PCI_8723AE_DID) { 1947 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE; 1948 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1949 "8723AE PCI-E is found - vid/did=%x/%x\n", 1950 venderid, deviceid); 1951 } else if (deviceid == RTL_PCI_8192CET_DID || 1952 deviceid == RTL_PCI_8192CE_DID || 1953 deviceid == RTL_PCI_8191CE_DID || 1954 deviceid == RTL_PCI_8188CE_DID) { 1955 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE; 1956 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1957 "8192C PCI-E is found - vid/did=%x/%x\n", 1958 venderid, deviceid); 1959 } else if (deviceid == RTL_PCI_8192DE_DID || 1960 deviceid == RTL_PCI_8192DE_DID2) { 1961 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE; 1962 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1963 "8192D PCI-E is found - vid/did=%x/%x\n", 1964 venderid, deviceid); 1965 } else if (deviceid == RTL_PCI_8188EE_DID) { 1966 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE; 1967 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1968 "Find adapter, Hardware type is 8188EE\n"); 1969 } else if (deviceid == RTL_PCI_8723BE_DID) { 1970 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE; 1971 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1972 "Find adapter, Hardware type is 8723BE\n"); 1973 } else if (deviceid == RTL_PCI_8192EE_DID) { 1974 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE; 1975 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1976 "Find adapter, Hardware type is 8192EE\n"); 1977 } else if (deviceid == RTL_PCI_8821AE_DID) { 1978 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE; 1979 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1980 "Find adapter, Hardware type is 8821AE\n"); 1981 } else if (deviceid == RTL_PCI_8812AE_DID) { 1982 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE; 1983 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1984 "Find adapter, Hardware type is 8812AE\n"); 1985 } else if (deviceid == RTL_PCI_8822BE_DID) { 1986 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE; 1987 rtlhal->bandset = BAND_ON_BOTH; 1988 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1989 "Find adapter, Hardware type is 8822BE\n"); 1990 } else { 1991 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1992 "Err: Unknown device - vid/did=%x/%x\n", 1993 venderid, deviceid); 1994 1995 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE; 1996 } 1997 1998 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) { 1999 if (revisionid == 0 || revisionid == 1) { 2000 if (revisionid == 0) { 2001 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2002 "Find 92DE MAC0\n"); 2003 rtlhal->interfaceindex = 0; 2004 } else if (revisionid == 1) { 2005 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2006 "Find 92DE MAC1\n"); 2007 rtlhal->interfaceindex = 1; 2008 } 2009 } else { 2010 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2011 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", 2012 venderid, deviceid, revisionid); 2013 rtlhal->interfaceindex = 0; 2014 } 2015 } 2016 2017 switch (rtlhal->hw_type) { 2018 case HARDWARE_TYPE_RTL8192EE: 2019 case HARDWARE_TYPE_RTL8822BE: 2020 /* use new trx flow */ 2021 rtlpriv->use_new_trx_flow = true; 2022 break; 2023 2024 default: 2025 rtlpriv->use_new_trx_flow = false; 2026 break; 2027 } 2028 2029 /*find bus info */ 2030 pcipriv->ndis_adapter.busnumber = pdev->bus->number; 2031 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn); 2032 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn); 2033 2034 /*find bridge info */ 2035 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 2036 /* some ARM have no bridge_pdev and will crash here 2037 * so we should check if bridge_pdev is NULL 2038 */ 2039 if (bridge_pdev) { 2040 /*find bridge info if available */ 2041 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor; 2042 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { 2043 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { 2044 pcipriv->ndis_adapter.pcibridge_vendor = tmp; 2045 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2046 "Pci Bridge Vendor is found index: %d\n", 2047 tmp); 2048 break; 2049 } 2050 } 2051 } 2052 2053 if (pcipriv->ndis_adapter.pcibridge_vendor != 2054 PCI_BRIDGE_VENDOR_UNKNOWN) { 2055 pcipriv->ndis_adapter.pcibridge_busnum = 2056 bridge_pdev->bus->number; 2057 pcipriv->ndis_adapter.pcibridge_devnum = 2058 PCI_SLOT(bridge_pdev->devfn); 2059 pcipriv->ndis_adapter.pcibridge_funcnum = 2060 PCI_FUNC(bridge_pdev->devfn); 2061 pcipriv->ndis_adapter.pcibridge_pciehdr_offset = 2062 pci_pcie_cap(bridge_pdev); 2063 pcipriv->ndis_adapter.num4bytes = 2064 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4; 2065 2066 rtl_pci_get_linkcontrol_field(hw); 2067 2068 if (pcipriv->ndis_adapter.pcibridge_vendor == 2069 PCI_BRIDGE_VENDOR_AMD) { 2070 pcipriv->ndis_adapter.amd_l1_patch = 2071 rtl_pci_get_amd_l1_patch(hw); 2072 } 2073 } 2074 2075 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2076 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", 2077 pcipriv->ndis_adapter.busnumber, 2078 pcipriv->ndis_adapter.devnumber, 2079 pcipriv->ndis_adapter.funcnumber, 2080 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); 2081 2082 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2083 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n", 2084 pcipriv->ndis_adapter.pcibridge_busnum, 2085 pcipriv->ndis_adapter.pcibridge_devnum, 2086 pcipriv->ndis_adapter.pcibridge_funcnum, 2087 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], 2088 pcipriv->ndis_adapter.pcibridge_pciehdr_offset, 2089 pcipriv->ndis_adapter.pcibridge_linkctrlreg, 2090 pcipriv->ndis_adapter.amd_l1_patch); 2091 2092 rtl_pci_parse_configuration(pdev, hw); 2093 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list); 2094 2095 return true; 2096 } 2097 2098 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw) 2099 { 2100 struct rtl_priv *rtlpriv = rtl_priv(hw); 2101 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2102 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2103 int ret; 2104 2105 ret = pci_enable_msi(rtlpci->pdev); 2106 if (ret < 0) 2107 return ret; 2108 2109 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2110 IRQF_SHARED, KBUILD_MODNAME, hw); 2111 if (ret < 0) { 2112 pci_disable_msi(rtlpci->pdev); 2113 return ret; 2114 } 2115 2116 rtlpci->using_msi = true; 2117 2118 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 2119 "MSI Interrupt Mode!\n"); 2120 return 0; 2121 } 2122 2123 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw) 2124 { 2125 struct rtl_priv *rtlpriv = rtl_priv(hw); 2126 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2127 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2128 int ret; 2129 2130 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2131 IRQF_SHARED, KBUILD_MODNAME, hw); 2132 if (ret < 0) 2133 return ret; 2134 2135 rtlpci->using_msi = false; 2136 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 2137 "Pin-based Interrupt Mode!\n"); 2138 return 0; 2139 } 2140 2141 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw) 2142 { 2143 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2144 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2145 int ret; 2146 2147 if (rtlpci->msi_support) { 2148 ret = rtl_pci_intr_mode_msi(hw); 2149 if (ret < 0) 2150 ret = rtl_pci_intr_mode_legacy(hw); 2151 } else { 2152 ret = rtl_pci_intr_mode_legacy(hw); 2153 } 2154 return ret; 2155 } 2156 2157 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64) 2158 { 2159 u8 value; 2160 2161 pci_read_config_byte(pdev, 0x719, &value); 2162 2163 /* 0x719 Bit5 is DMA64 bit fetch. */ 2164 if (dma64) 2165 value |= BIT(5); 2166 else 2167 value &= ~BIT(5); 2168 2169 pci_write_config_byte(pdev, 0x719, value); 2170 } 2171 2172 int rtl_pci_probe(struct pci_dev *pdev, 2173 const struct pci_device_id *id) 2174 { 2175 struct ieee80211_hw *hw = NULL; 2176 2177 struct rtl_priv *rtlpriv = NULL; 2178 struct rtl_pci_priv *pcipriv = NULL; 2179 struct rtl_pci *rtlpci; 2180 unsigned long pmem_start, pmem_len, pmem_flags; 2181 int err; 2182 2183 err = pci_enable_device(pdev); 2184 if (err) { 2185 WARN_ONCE(true, "%s : Cannot enable new PCI device\n", 2186 pci_name(pdev)); 2187 return err; 2188 } 2189 2190 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 && 2191 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 2192 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { 2193 WARN_ONCE(true, 2194 "Unable to obtain 64bit DMA for consistent allocations\n"); 2195 err = -ENOMEM; 2196 goto fail1; 2197 } 2198 2199 platform_enable_dma64(pdev, true); 2200 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 2201 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 2202 WARN_ONCE(true, 2203 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n"); 2204 err = -ENOMEM; 2205 goto fail1; 2206 } 2207 2208 platform_enable_dma64(pdev, false); 2209 } 2210 2211 pci_set_master(pdev); 2212 2213 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) + 2214 sizeof(struct rtl_priv), &rtl_ops); 2215 if (!hw) { 2216 WARN_ONCE(true, 2217 "%s : ieee80211 alloc failed\n", pci_name(pdev)); 2218 err = -ENOMEM; 2219 goto fail1; 2220 } 2221 2222 SET_IEEE80211_DEV(hw, &pdev->dev); 2223 pci_set_drvdata(pdev, hw); 2224 2225 rtlpriv = hw->priv; 2226 rtlpriv->hw = hw; 2227 pcipriv = (void *)rtlpriv->priv; 2228 pcipriv->dev.pdev = pdev; 2229 init_completion(&rtlpriv->firmware_loading_complete); 2230 /*proximity init here*/ 2231 rtlpriv->proximity.proxim_on = false; 2232 2233 pcipriv = (void *)rtlpriv->priv; 2234 pcipriv->dev.pdev = pdev; 2235 2236 /* init cfg & intf_ops */ 2237 rtlpriv->rtlhal.interface = INTF_PCI; 2238 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data); 2239 rtlpriv->intf_ops = &rtl_pci_ops; 2240 rtlpriv->glb_var = &rtl_global_var; 2241 2242 /* MEM map */ 2243 err = pci_request_regions(pdev, KBUILD_MODNAME); 2244 if (err) { 2245 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n"); 2246 goto fail1; 2247 } 2248 2249 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id); 2250 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id); 2251 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id); 2252 2253 /*shared mem start */ 2254 rtlpriv->io.pci_mem_start = 2255 (unsigned long)pci_iomap(pdev, 2256 rtlpriv->cfg->bar_id, pmem_len); 2257 if (rtlpriv->io.pci_mem_start == 0) { 2258 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n"); 2259 err = -ENOMEM; 2260 goto fail2; 2261 } 2262 2263 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2264 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", 2265 pmem_start, pmem_len, pmem_flags, 2266 rtlpriv->io.pci_mem_start); 2267 2268 /* Disable Clk Request */ 2269 pci_write_config_byte(pdev, 0x81, 0); 2270 /* leave D3 mode */ 2271 pci_write_config_byte(pdev, 0x44, 0); 2272 pci_write_config_byte(pdev, 0x04, 0x06); 2273 pci_write_config_byte(pdev, 0x04, 0x07); 2274 2275 /* find adapter */ 2276 if (!_rtl_pci_find_adapter(pdev, hw)) { 2277 err = -ENODEV; 2278 goto fail2; 2279 } 2280 2281 /* Init IO handler */ 2282 _rtl_pci_io_handler_init(&pdev->dev, hw); 2283 2284 /*like read eeprom and so on */ 2285 rtlpriv->cfg->ops->read_eeprom_info(hw); 2286 2287 if (rtlpriv->cfg->ops->init_sw_vars(hw)) { 2288 pr_err("Can't init_sw_vars\n"); 2289 err = -ENODEV; 2290 goto fail3; 2291 } 2292 rtlpriv->cfg->ops->init_sw_leds(hw); 2293 2294 /*aspm */ 2295 rtl_pci_init_aspm(hw); 2296 2297 /* Init mac80211 sw */ 2298 err = rtl_init_core(hw); 2299 if (err) { 2300 pr_err("Can't allocate sw for mac80211\n"); 2301 goto fail3; 2302 } 2303 2304 /* Init PCI sw */ 2305 err = rtl_pci_init(hw, pdev); 2306 if (err) { 2307 pr_err("Failed to init PCI\n"); 2308 goto fail3; 2309 } 2310 2311 err = ieee80211_register_hw(hw); 2312 if (err) { 2313 pr_err("Can't register mac80211 hw.\n"); 2314 err = -ENODEV; 2315 goto fail3; 2316 } 2317 rtlpriv->mac80211.mac80211_registered = 1; 2318 2319 /* add for debug */ 2320 rtl_debug_add_one(hw); 2321 2322 /*init rfkill */ 2323 rtl_init_rfkill(hw); /* Init PCI sw */ 2324 2325 rtlpci = rtl_pcidev(pcipriv); 2326 err = rtl_pci_intr_mode_decide(hw); 2327 if (err) { 2328 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2329 "%s: failed to register IRQ handler\n", 2330 wiphy_name(hw->wiphy)); 2331 goto fail3; 2332 } 2333 rtlpci->irq_alloc = 1; 2334 2335 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2336 return 0; 2337 2338 fail3: 2339 pci_set_drvdata(pdev, NULL); 2340 rtl_deinit_core(hw); 2341 2342 fail2: 2343 if (rtlpriv->io.pci_mem_start != 0) 2344 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2345 2346 pci_release_regions(pdev); 2347 complete(&rtlpriv->firmware_loading_complete); 2348 2349 fail1: 2350 if (hw) 2351 ieee80211_free_hw(hw); 2352 pci_disable_device(pdev); 2353 2354 return err; 2355 } 2356 EXPORT_SYMBOL(rtl_pci_probe); 2357 2358 void rtl_pci_disconnect(struct pci_dev *pdev) 2359 { 2360 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2361 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2362 struct rtl_priv *rtlpriv = rtl_priv(hw); 2363 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2364 struct rtl_mac *rtlmac = rtl_mac(rtlpriv); 2365 2366 /* just in case driver is removed before firmware callback */ 2367 wait_for_completion(&rtlpriv->firmware_loading_complete); 2368 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2369 2370 /* remove form debug */ 2371 rtl_debug_remove_one(hw); 2372 2373 /*ieee80211_unregister_hw will call ops_stop */ 2374 if (rtlmac->mac80211_registered == 1) { 2375 ieee80211_unregister_hw(hw); 2376 rtlmac->mac80211_registered = 0; 2377 } else { 2378 rtl_deinit_deferred_work(hw); 2379 rtlpriv->intf_ops->adapter_stop(hw); 2380 } 2381 rtlpriv->cfg->ops->disable_interrupt(hw); 2382 2383 /*deinit rfkill */ 2384 rtl_deinit_rfkill(hw); 2385 2386 rtl_pci_deinit(hw); 2387 rtl_deinit_core(hw); 2388 rtlpriv->cfg->ops->deinit_sw_vars(hw); 2389 2390 if (rtlpci->irq_alloc) { 2391 free_irq(rtlpci->pdev->irq, hw); 2392 rtlpci->irq_alloc = 0; 2393 } 2394 2395 if (rtlpci->using_msi) 2396 pci_disable_msi(rtlpci->pdev); 2397 2398 list_del(&rtlpriv->list); 2399 if (rtlpriv->io.pci_mem_start != 0) { 2400 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2401 pci_release_regions(pdev); 2402 } 2403 2404 pci_disable_device(pdev); 2405 2406 rtl_pci_disable_aspm(hw); 2407 2408 pci_set_drvdata(pdev, NULL); 2409 2410 ieee80211_free_hw(hw); 2411 } 2412 EXPORT_SYMBOL(rtl_pci_disconnect); 2413 2414 #ifdef CONFIG_PM_SLEEP 2415 /*************************************** 2416 * kernel pci power state define: 2417 * PCI_D0 ((pci_power_t __force) 0) 2418 * PCI_D1 ((pci_power_t __force) 1) 2419 * PCI_D2 ((pci_power_t __force) 2) 2420 * PCI_D3hot ((pci_power_t __force) 3) 2421 * PCI_D3cold ((pci_power_t __force) 4) 2422 * PCI_UNKNOWN ((pci_power_t __force) 5) 2423 2424 * This function is called when system 2425 * goes into suspend state mac80211 will 2426 * call rtl_mac_stop() from the mac80211 2427 * suspend function first, So there is 2428 * no need to call hw_disable here. 2429 ****************************************/ 2430 int rtl_pci_suspend(struct device *dev) 2431 { 2432 struct pci_dev *pdev = to_pci_dev(dev); 2433 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2434 struct rtl_priv *rtlpriv = rtl_priv(hw); 2435 2436 rtlpriv->cfg->ops->hw_suspend(hw); 2437 rtl_deinit_rfkill(hw); 2438 2439 return 0; 2440 } 2441 EXPORT_SYMBOL(rtl_pci_suspend); 2442 2443 int rtl_pci_resume(struct device *dev) 2444 { 2445 struct pci_dev *pdev = to_pci_dev(dev); 2446 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2447 struct rtl_priv *rtlpriv = rtl_priv(hw); 2448 2449 rtlpriv->cfg->ops->hw_resume(hw); 2450 rtl_init_rfkill(hw); 2451 return 0; 2452 } 2453 EXPORT_SYMBOL(rtl_pci_resume); 2454 #endif /* CONFIG_PM_SLEEP */ 2455 2456 const struct rtl_intf_ops rtl_pci_ops = { 2457 .read_efuse_byte = read_efuse_byte, 2458 .adapter_start = rtl_pci_start, 2459 .adapter_stop = rtl_pci_stop, 2460 .check_buddy_priv = rtl_pci_check_buddy_priv, 2461 .adapter_tx = rtl_pci_tx, 2462 .flush = rtl_pci_flush, 2463 .reset_trx_ring = rtl_pci_reset_trx_ring, 2464 .waitq_insert = rtl_pci_tx_chk_waitq_insert, 2465 2466 .disable_aspm = rtl_pci_disable_aspm, 2467 .enable_aspm = rtl_pci_enable_aspm, 2468 }; 2469