1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30 #include "wifi.h" 31 #include "core.h" 32 #include "pci.h" 33 #include "base.h" 34 #include "ps.h" 35 #include "efuse.h" 36 #include <linux/interrupt.h> 37 #include <linux/export.h> 38 #include <linux/kmemleak.h> 39 #include <linux/module.h> 40 41 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 42 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 43 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>"); 44 MODULE_LICENSE("GPL"); 45 MODULE_DESCRIPTION("PCI basic driver for rtlwifi"); 46 47 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { 48 INTEL_VENDOR_ID, 49 ATI_VENDOR_ID, 50 AMD_VENDOR_ID, 51 SIS_VENDOR_ID 52 }; 53 54 static const u8 ac_to_hwq[] = { 55 VO_QUEUE, 56 VI_QUEUE, 57 BE_QUEUE, 58 BK_QUEUE 59 }; 60 61 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, 62 struct sk_buff *skb) 63 { 64 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 65 __le16 fc = rtl_get_fc(skb); 66 u8 queue_index = skb_get_queue_mapping(skb); 67 68 if (unlikely(ieee80211_is_beacon(fc))) 69 return BEACON_QUEUE; 70 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) 71 return MGNT_QUEUE; 72 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 73 if (ieee80211_is_nullfunc(fc)) 74 return HIGH_QUEUE; 75 76 return ac_to_hwq[queue_index]; 77 } 78 79 /* Update PCI dependent default settings*/ 80 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) 81 { 82 struct rtl_priv *rtlpriv = rtl_priv(hw); 83 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 84 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 85 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 86 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 87 u8 init_aspm; 88 89 ppsc->reg_rfps_level = 0; 90 ppsc->support_aspm = false; 91 92 /*Update PCI ASPM setting */ 93 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm; 94 switch (rtlpci->const_pci_aspm) { 95 case 0: 96 /*No ASPM */ 97 break; 98 99 case 1: 100 /*ASPM dynamically enabled/disable. */ 101 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; 102 break; 103 104 case 2: 105 /*ASPM with Clock Req dynamically enabled/disable. */ 106 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | 107 RT_RF_OFF_LEVL_CLK_REQ); 108 break; 109 110 case 3: 111 /* 112 * Always enable ASPM and Clock Req 113 * from initialization to halt. 114 * */ 115 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); 116 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | 117 RT_RF_OFF_LEVL_CLK_REQ); 118 break; 119 120 case 4: 121 /* 122 * Always enable ASPM without Clock Req 123 * from initialization to halt. 124 * */ 125 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | 126 RT_RF_OFF_LEVL_CLK_REQ); 127 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; 128 break; 129 } 130 131 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 132 133 /*Update Radio OFF setting */ 134 switch (rtlpci->const_hwsw_rfoff_d3) { 135 case 1: 136 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 137 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 138 break; 139 140 case 2: 141 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 142 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 143 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 144 break; 145 146 case 3: 147 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; 148 break; 149 } 150 151 /*Set HW definition to determine if it supports ASPM. */ 152 switch (rtlpci->const_support_pciaspm) { 153 case 0:{ 154 /*Not support ASPM. */ 155 bool support_aspm = false; 156 ppsc->support_aspm = support_aspm; 157 break; 158 } 159 case 1:{ 160 /*Support ASPM. */ 161 bool support_aspm = true; 162 bool support_backdoor = true; 163 ppsc->support_aspm = support_aspm; 164 165 /*if (priv->oem_id == RT_CID_TOSHIBA && 166 !priv->ndis_adapter.amd_l1_patch) 167 support_backdoor = false; */ 168 169 ppsc->support_backdoor = support_backdoor; 170 171 break; 172 } 173 case 2: 174 /*ASPM value set by chipset. */ 175 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) { 176 bool support_aspm = true; 177 ppsc->support_aspm = support_aspm; 178 } 179 break; 180 default: 181 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 182 "switch case not processed\n"); 183 break; 184 } 185 186 /* toshiba aspm issue, toshiba will set aspm selfly 187 * so we should not set aspm in driver */ 188 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm); 189 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE && 190 init_aspm == 0x43) 191 ppsc->support_aspm = false; 192 } 193 194 static bool _rtl_pci_platform_switch_device_pci_aspm( 195 struct ieee80211_hw *hw, 196 u8 value) 197 { 198 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 199 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 200 201 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE) 202 value |= 0x40; 203 204 pci_write_config_byte(rtlpci->pdev, 0x80, value); 205 206 return false; 207 } 208 209 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/ 210 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value) 211 { 212 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 213 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 214 215 pci_write_config_byte(rtlpci->pdev, 0x81, value); 216 217 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 218 udelay(100); 219 } 220 221 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ 222 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) 223 { 224 struct rtl_priv *rtlpriv = rtl_priv(hw); 225 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 226 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 227 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 228 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 229 u8 num4bytes = pcipriv->ndis_adapter.num4bytes; 230 /*Retrieve original configuration settings. */ 231 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg; 232 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter. 233 pcibridge_linkctrlreg; 234 u16 aspmlevel = 0; 235 u8 tmp_u1b = 0; 236 237 if (!ppsc->support_aspm) 238 return; 239 240 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 241 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 242 "PCI(Bridge) UNKNOWN\n"); 243 244 return; 245 } 246 247 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 248 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 249 _rtl_pci_switch_clk_req(hw, 0x0); 250 } 251 252 /*for promising device will in L0 state after an I/O. */ 253 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b); 254 255 /*Set corresponding value. */ 256 aspmlevel |= BIT(0) | BIT(1); 257 linkctrl_reg &= ~aspmlevel; 258 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1)); 259 260 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg); 261 udelay(50); 262 263 /*4 Disable Pci Bridge ASPM */ 264 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), 265 pcibridge_linkctrlreg); 266 267 udelay(50); 268 } 269 270 /* 271 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for 272 *power saving We should follow the sequence to enable 273 *RTL8192SE first then enable Pci Bridge ASPM 274 *or the system will show bluescreen. 275 */ 276 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) 277 { 278 struct rtl_priv *rtlpriv = rtl_priv(hw); 279 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 280 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 281 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 282 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 283 u8 num4bytes = pcipriv->ndis_adapter.num4bytes; 284 u16 aspmlevel; 285 u8 u_pcibridge_aspmsetting; 286 u8 u_device_aspmsetting; 287 288 if (!ppsc->support_aspm) 289 return; 290 291 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 292 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 293 "PCI(Bridge) UNKNOWN\n"); 294 return; 295 } 296 297 /*4 Enable Pci Bridge ASPM */ 298 299 u_pcibridge_aspmsetting = 300 pcipriv->ndis_adapter.pcibridge_linkctrlreg | 301 rtlpci->const_hostpci_aspm_setting; 302 303 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) 304 u_pcibridge_aspmsetting &= ~BIT(0); 305 306 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), 307 u_pcibridge_aspmsetting); 308 309 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 310 "PlatformEnableASPM(): Write reg[%x] = %x\n", 311 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10), 312 u_pcibridge_aspmsetting); 313 314 udelay(50); 315 316 /*Get ASPM level (with/without Clock Req) */ 317 aspmlevel = rtlpci->const_devicepci_aspm_setting; 318 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg; 319 320 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/ 321 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */ 322 323 u_device_aspmsetting |= aspmlevel; 324 325 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting); 326 327 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 328 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level & 329 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0); 330 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 331 } 332 udelay(100); 333 } 334 335 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw) 336 { 337 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 338 339 bool status = false; 340 u8 offset_e0; 341 unsigned offset_e4; 342 343 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0); 344 345 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0); 346 347 if (offset_e0 == 0xA0) { 348 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4); 349 if (offset_e4 & BIT(23)) 350 status = true; 351 } 352 353 return status; 354 } 355 356 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw, 357 struct rtl_priv **buddy_priv) 358 { 359 struct rtl_priv *rtlpriv = rtl_priv(hw); 360 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 361 bool find_buddy_priv = false; 362 struct rtl_priv *tpriv = NULL; 363 struct rtl_pci_priv *tpcipriv = NULL; 364 365 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) { 366 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list, 367 list) { 368 if (tpriv) { 369 tpcipriv = (struct rtl_pci_priv *)tpriv->priv; 370 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 371 "pcipriv->ndis_adapter.funcnumber %x\n", 372 pcipriv->ndis_adapter.funcnumber); 373 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 374 "tpcipriv->ndis_adapter.funcnumber %x\n", 375 tpcipriv->ndis_adapter.funcnumber); 376 377 if ((pcipriv->ndis_adapter.busnumber == 378 tpcipriv->ndis_adapter.busnumber) && 379 (pcipriv->ndis_adapter.devnumber == 380 tpcipriv->ndis_adapter.devnumber) && 381 (pcipriv->ndis_adapter.funcnumber != 382 tpcipriv->ndis_adapter.funcnumber)) { 383 find_buddy_priv = true; 384 break; 385 } 386 } 387 } 388 } 389 390 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 391 "find_buddy_priv %d\n", find_buddy_priv); 392 393 if (find_buddy_priv) 394 *buddy_priv = tpriv; 395 396 return find_buddy_priv; 397 } 398 399 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw) 400 { 401 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 402 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 403 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset; 404 u8 linkctrl_reg; 405 u8 num4bbytes; 406 407 num4bbytes = (capabilityoffset + 0x10) / 4; 408 409 /*Read Link Control Register */ 410 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg); 411 412 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg; 413 } 414 415 static void rtl_pci_parse_configuration(struct pci_dev *pdev, 416 struct ieee80211_hw *hw) 417 { 418 struct rtl_priv *rtlpriv = rtl_priv(hw); 419 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 420 421 u8 tmp; 422 u16 linkctrl_reg; 423 424 /*Link Control Register */ 425 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg); 426 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg; 427 428 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", 429 pcipriv->ndis_adapter.linkctrl_reg); 430 431 pci_read_config_byte(pdev, 0x98, &tmp); 432 tmp |= BIT(4); 433 pci_write_config_byte(pdev, 0x98, tmp); 434 435 tmp = 0x17; 436 pci_write_config_byte(pdev, 0x70f, tmp); 437 } 438 439 static void rtl_pci_init_aspm(struct ieee80211_hw *hw) 440 { 441 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 442 443 _rtl_pci_update_default_setting(hw); 444 445 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { 446 /*Always enable ASPM & Clock Req. */ 447 rtl_pci_enable_aspm(hw); 448 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM); 449 } 450 451 } 452 453 static void _rtl_pci_io_handler_init(struct device *dev, 454 struct ieee80211_hw *hw) 455 { 456 struct rtl_priv *rtlpriv = rtl_priv(hw); 457 458 rtlpriv->io.dev = dev; 459 460 rtlpriv->io.write8_async = pci_write8_async; 461 rtlpriv->io.write16_async = pci_write16_async; 462 rtlpriv->io.write32_async = pci_write32_async; 463 464 rtlpriv->io.read8_sync = pci_read8_sync; 465 rtlpriv->io.read16_sync = pci_read16_sync; 466 rtlpriv->io.read32_sync = pci_read32_sync; 467 468 } 469 470 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw, 471 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid) 472 { 473 struct rtl_priv *rtlpriv = rtl_priv(hw); 474 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 475 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 476 struct sk_buff *next_skb; 477 u8 additionlen = FCS_LEN; 478 479 /* here open is 4, wep/tkip is 8, aes is 12*/ 480 if (info->control.hw_key) 481 additionlen += info->control.hw_key->icv_len; 482 483 /* The most skb num is 6 */ 484 tcb_desc->empkt_num = 0; 485 spin_lock_bh(&rtlpriv->locks.waitq_lock); 486 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) { 487 struct ieee80211_tx_info *next_info; 488 489 next_info = IEEE80211_SKB_CB(next_skb); 490 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) { 491 tcb_desc->empkt_len[tcb_desc->empkt_num] = 492 next_skb->len + additionlen; 493 tcb_desc->empkt_num++; 494 } else { 495 break; 496 } 497 498 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid], 499 next_skb)) 500 break; 501 502 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num) 503 break; 504 } 505 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 506 507 return true; 508 } 509 510 /* just for early mode now */ 511 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw) 512 { 513 struct rtl_priv *rtlpriv = rtl_priv(hw); 514 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 515 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 516 struct sk_buff *skb = NULL; 517 struct ieee80211_tx_info *info = NULL; 518 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 519 int tid; 520 521 if (!rtlpriv->rtlhal.earlymode_enable) 522 return; 523 524 if (rtlpriv->dm.supp_phymode_switch && 525 (rtlpriv->easy_concurrent_ctl.switch_in_process || 526 (rtlpriv->buddy_priv && 527 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process))) 528 return; 529 /* we juse use em for BE/BK/VI/VO */ 530 for (tid = 7; tid >= 0; tid--) { 531 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)]; 532 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; 533 while (!mac->act_scanning && 534 rtlpriv->psc.rfpwr_state == ERFON) { 535 struct rtl_tcb_desc tcb_desc; 536 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 537 538 spin_lock_bh(&rtlpriv->locks.waitq_lock); 539 if (!skb_queue_empty(&mac->skb_waitq[tid]) && 540 (ring->entries - skb_queue_len(&ring->queue) > 541 rtlhal->max_earlymode_num)) { 542 skb = skb_dequeue(&mac->skb_waitq[tid]); 543 } else { 544 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 545 break; 546 } 547 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 548 549 /* Some macaddr can't do early mode. like 550 * multicast/broadcast/no_qos data */ 551 info = IEEE80211_SKB_CB(skb); 552 if (info->flags & IEEE80211_TX_CTL_AMPDU) 553 _rtl_update_earlymode_info(hw, skb, 554 &tcb_desc, tid); 555 556 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc); 557 } 558 } 559 } 560 561 562 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) 563 { 564 struct rtl_priv *rtlpriv = rtl_priv(hw); 565 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 566 567 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 568 569 while (skb_queue_len(&ring->queue)) { 570 struct sk_buff *skb; 571 struct ieee80211_tx_info *info; 572 __le16 fc; 573 u8 tid; 574 u8 *entry; 575 576 if (rtlpriv->use_new_trx_flow) 577 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 578 else 579 entry = (u8 *)(&ring->desc[ring->idx]); 580 581 if (rtlpriv->cfg->ops->get_available_desc && 582 rtlpriv->cfg->ops->get_available_desc(hw, prio) <= 1) { 583 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_DMESG, 584 "no available desc!\n"); 585 return; 586 } 587 588 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx)) 589 return; 590 ring->idx = (ring->idx + 1) % ring->entries; 591 592 skb = __skb_dequeue(&ring->queue); 593 pci_unmap_single(rtlpci->pdev, 594 rtlpriv->cfg->ops-> 595 get_desc((u8 *)entry, true, 596 HW_DESC_TXBUFF_ADDR), 597 skb->len, PCI_DMA_TODEVICE); 598 599 /* remove early mode header */ 600 if (rtlpriv->rtlhal.earlymode_enable) 601 skb_pull(skb, EM_HDR_LEN); 602 603 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, 604 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", 605 ring->idx, 606 skb_queue_len(&ring->queue), 607 *(u16 *)(skb->data + 22)); 608 609 if (prio == TXCMD_QUEUE) { 610 dev_kfree_skb(skb); 611 goto tx_status_ok; 612 613 } 614 615 /* for sw LPS, just after NULL skb send out, we can 616 * sure AP knows we are sleeping, we should not let 617 * rf sleep 618 */ 619 fc = rtl_get_fc(skb); 620 if (ieee80211_is_nullfunc(fc)) { 621 if (ieee80211_has_pm(fc)) { 622 rtlpriv->mac80211.offchan_delay = true; 623 rtlpriv->psc.state_inap = true; 624 } else { 625 rtlpriv->psc.state_inap = false; 626 } 627 } 628 if (ieee80211_is_action(fc)) { 629 struct ieee80211_mgmt *action_frame = 630 (struct ieee80211_mgmt *)skb->data; 631 if (action_frame->u.action.u.ht_smps.action == 632 WLAN_HT_ACTION_SMPS) { 633 dev_kfree_skb(skb); 634 goto tx_status_ok; 635 } 636 } 637 638 /* update tid tx pkt num */ 639 tid = rtl_get_tid(skb); 640 if (tid <= 7) 641 rtlpriv->link_info.tidtx_inperiod[tid]++; 642 643 info = IEEE80211_SKB_CB(skb); 644 ieee80211_tx_info_clear_status(info); 645 646 info->flags |= IEEE80211_TX_STAT_ACK; 647 /*info->status.rates[0].count = 1; */ 648 649 ieee80211_tx_status_irqsafe(hw, skb); 650 651 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) { 652 653 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, 654 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", 655 prio, ring->idx, 656 skb_queue_len(&ring->queue)); 657 658 ieee80211_wake_queue(hw, 659 skb_get_queue_mapping 660 (skb)); 661 } 662 tx_status_ok: 663 skb = NULL; 664 } 665 666 if (((rtlpriv->link_info.num_rx_inperiod + 667 rtlpriv->link_info.num_tx_inperiod) > 8) || 668 (rtlpriv->link_info.num_rx_inperiod > 2)) { 669 rtlpriv->enter_ps = false; 670 schedule_work(&rtlpriv->works.lps_change_work); 671 } 672 } 673 674 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, 675 struct sk_buff *new_skb, u8 *entry, 676 int rxring_idx, int desc_idx) 677 { 678 struct rtl_priv *rtlpriv = rtl_priv(hw); 679 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 680 u32 bufferaddress; 681 u8 tmp_one = 1; 682 struct sk_buff *skb; 683 684 if (likely(new_skb)) { 685 skb = new_skb; 686 goto remap; 687 } 688 skb = dev_alloc_skb(rtlpci->rxbuffersize); 689 if (!skb) 690 return 0; 691 692 remap: 693 /* just set skb->cb to mapping addr for pci_unmap_single use */ 694 *((dma_addr_t *)skb->cb) = 695 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb), 696 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 697 bufferaddress = *((dma_addr_t *)skb->cb); 698 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress)) 699 return 0; 700 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb; 701 if (rtlpriv->use_new_trx_flow) { 702 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 703 HW_DESC_RX_PREPARE, 704 (u8 *)&bufferaddress); 705 } else { 706 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 707 HW_DESC_RXBUFF_ADDR, 708 (u8 *)&bufferaddress); 709 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 710 HW_DESC_RXPKT_LEN, 711 (u8 *)&rtlpci->rxbuffersize); 712 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 713 HW_DESC_RXOWN, 714 (u8 *)&tmp_one); 715 } 716 return 1; 717 } 718 719 /* inorder to receive 8K AMSDU we have set skb to 720 * 9100bytes in init rx ring, but if this packet is 721 * not a AMSDU, this large packet will be sent to 722 * TCP/IP directly, this cause big packet ping fail 723 * like: "ping -s 65507", so here we will realloc skb 724 * based on the true size of packet, Mac80211 725 * Probably will do it better, but does not yet. 726 * 727 * Some platform will fail when alloc skb sometimes. 728 * in this condition, we will send the old skb to 729 * mac80211 directly, this will not cause any other 730 * issues, but only this packet will be lost by TCP/IP 731 */ 732 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw, 733 struct sk_buff *skb, 734 struct ieee80211_rx_status rx_status) 735 { 736 if (unlikely(!rtl_action_proc(hw, skb, false))) { 737 dev_kfree_skb_any(skb); 738 } else { 739 struct sk_buff *uskb = NULL; 740 u8 *pdata; 741 742 uskb = dev_alloc_skb(skb->len + 128); 743 if (likely(uskb)) { 744 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, 745 sizeof(rx_status)); 746 pdata = (u8 *)skb_put(uskb, skb->len); 747 memcpy(pdata, skb->data, skb->len); 748 dev_kfree_skb_any(skb); 749 ieee80211_rx_irqsafe(hw, uskb); 750 } else { 751 ieee80211_rx_irqsafe(hw, skb); 752 } 753 } 754 } 755 756 /*hsisr interrupt handler*/ 757 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw) 758 { 759 struct rtl_priv *rtlpriv = rtl_priv(hw); 760 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 761 762 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR], 763 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) | 764 rtlpci->sys_irq_mask); 765 } 766 767 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) 768 { 769 struct rtl_priv *rtlpriv = rtl_priv(hw); 770 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 771 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE; 772 struct ieee80211_rx_status rx_status = { 0 }; 773 unsigned int count = rtlpci->rxringcount; 774 u8 own; 775 u8 tmp_one; 776 bool unicast = false; 777 u8 hw_queue = 0; 778 unsigned int rx_remained_cnt; 779 struct rtl_stats stats = { 780 .signal = 0, 781 .rate = 0, 782 }; 783 784 /*RX NORMAL PKT */ 785 while (count--) { 786 struct ieee80211_hdr *hdr; 787 __le16 fc; 788 u16 len; 789 /*rx buffer descriptor */ 790 struct rtl_rx_buffer_desc *buffer_desc = NULL; 791 /*if use new trx flow, it means wifi info */ 792 struct rtl_rx_desc *pdesc = NULL; 793 /*rx pkt */ 794 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[ 795 rtlpci->rx_ring[rxring_idx].idx]; 796 struct sk_buff *new_skb; 797 798 if (rtlpriv->use_new_trx_flow) { 799 rx_remained_cnt = 800 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw, 801 hw_queue); 802 if (rx_remained_cnt == 0) 803 return; 804 805 } else { /* rx descriptor */ 806 pdesc = &rtlpci->rx_ring[rxring_idx].desc[ 807 rtlpci->rx_ring[rxring_idx].idx]; 808 809 own = (u8)rtlpriv->cfg->ops->get_desc((u8 *)pdesc, 810 false, 811 HW_DESC_OWN); 812 if (own) /* wait data to be filled by hardware */ 813 return; 814 } 815 816 /* Reaching this point means: data is filled already 817 * AAAAAAttention !!! 818 * We can NOT access 'skb' before 'pci_unmap_single' 819 */ 820 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), 821 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 822 823 /* get a new skb - if fail, old one will be reused */ 824 new_skb = dev_alloc_skb(rtlpci->rxbuffersize); 825 if (unlikely(!new_skb)) 826 goto no_new; 827 if (rtlpriv->use_new_trx_flow) { 828 buffer_desc = 829 &rtlpci->rx_ring[rxring_idx].buffer_desc 830 [rtlpci->rx_ring[rxring_idx].idx]; 831 /*means rx wifi info*/ 832 pdesc = (struct rtl_rx_desc *)skb->data; 833 } 834 memset(&rx_status , 0 , sizeof(rx_status)); 835 rtlpriv->cfg->ops->query_rx_desc(hw, &stats, 836 &rx_status, (u8 *)pdesc, skb); 837 838 if (rtlpriv->use_new_trx_flow) 839 rtlpriv->cfg->ops->rx_check_dma_ok(hw, 840 (u8 *)buffer_desc, 841 hw_queue); 842 843 len = rtlpriv->cfg->ops->get_desc((u8 *)pdesc, false, 844 HW_DESC_RXPKT_LEN); 845 846 if (skb->end - skb->tail > len) { 847 skb_put(skb, len); 848 if (rtlpriv->use_new_trx_flow) 849 skb_reserve(skb, stats.rx_drvinfo_size + 850 stats.rx_bufshift + 24); 851 else 852 skb_reserve(skb, stats.rx_drvinfo_size + 853 stats.rx_bufshift); 854 } else { 855 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 856 "skb->end - skb->tail = %d, len is %d\n", 857 skb->end - skb->tail, len); 858 dev_kfree_skb_any(skb); 859 goto new_trx_end; 860 } 861 /* handle command packet here */ 862 if (rtlpriv->cfg->ops->rx_command_packet && 863 rtlpriv->cfg->ops->rx_command_packet(hw, stats, skb)) { 864 dev_kfree_skb_any(skb); 865 goto new_trx_end; 866 } 867 868 /* 869 * NOTICE This can not be use for mac80211, 870 * this is done in mac80211 code, 871 * if done here sec DHCP will fail 872 * skb_trim(skb, skb->len - 4); 873 */ 874 875 hdr = rtl_get_hdr(skb); 876 fc = rtl_get_fc(skb); 877 878 if (!stats.crc && !stats.hwerror) { 879 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, 880 sizeof(rx_status)); 881 882 if (is_broadcast_ether_addr(hdr->addr1)) { 883 ;/*TODO*/ 884 } else if (is_multicast_ether_addr(hdr->addr1)) { 885 ;/*TODO*/ 886 } else { 887 unicast = true; 888 rtlpriv->stats.rxbytesunicast += skb->len; 889 } 890 rtl_is_special_data(hw, skb, false, true); 891 892 if (ieee80211_is_data(fc)) { 893 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX); 894 if (unicast) 895 rtlpriv->link_info.num_rx_inperiod++; 896 } 897 /* static bcn for roaming */ 898 rtl_beacon_statistic(hw, skb); 899 rtl_p2p_info(hw, (void *)skb->data, skb->len); 900 /* for sw lps */ 901 rtl_swlps_beacon(hw, (void *)skb->data, skb->len); 902 rtl_recognize_peer(hw, (void *)skb->data, skb->len); 903 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) && 904 (rtlpriv->rtlhal.current_bandtype == 905 BAND_ON_2_4G) && 906 (ieee80211_is_beacon(fc) || 907 ieee80211_is_probe_resp(fc))) { 908 dev_kfree_skb_any(skb); 909 } else { 910 _rtl_pci_rx_to_mac80211(hw, skb, rx_status); 911 } 912 } else { 913 dev_kfree_skb_any(skb); 914 } 915 new_trx_end: 916 if (rtlpriv->use_new_trx_flow) { 917 rtlpci->rx_ring[hw_queue].next_rx_rp += 1; 918 rtlpci->rx_ring[hw_queue].next_rx_rp %= 919 RTL_PCI_MAX_RX_COUNT; 920 921 rx_remained_cnt--; 922 rtl_write_word(rtlpriv, 0x3B4, 923 rtlpci->rx_ring[hw_queue].next_rx_rp); 924 } 925 if (((rtlpriv->link_info.num_rx_inperiod + 926 rtlpriv->link_info.num_tx_inperiod) > 8) || 927 (rtlpriv->link_info.num_rx_inperiod > 2)) { 928 rtlpriv->enter_ps = false; 929 schedule_work(&rtlpriv->works.lps_change_work); 930 } 931 skb = new_skb; 932 no_new: 933 if (rtlpriv->use_new_trx_flow) { 934 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc, 935 rxring_idx, 936 rtlpci->rx_ring[rxring_idx].idx); 937 } else { 938 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc, 939 rxring_idx, 940 rtlpci->rx_ring[rxring_idx].idx); 941 if (rtlpci->rx_ring[rxring_idx].idx == 942 rtlpci->rxringcount - 1) 943 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, 944 false, 945 HW_DESC_RXERO, 946 (u8 *)&tmp_one); 947 } 948 rtlpci->rx_ring[rxring_idx].idx = 949 (rtlpci->rx_ring[rxring_idx].idx + 1) % 950 rtlpci->rxringcount; 951 } 952 } 953 954 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) 955 { 956 struct ieee80211_hw *hw = dev_id; 957 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 958 struct rtl_priv *rtlpriv = rtl_priv(hw); 959 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 960 unsigned long flags; 961 u32 inta = 0; 962 u32 intb = 0; 963 irqreturn_t ret = IRQ_HANDLED; 964 965 if (rtlpci->irq_enabled == 0) 966 return ret; 967 968 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock , flags); 969 rtlpriv->cfg->ops->disable_interrupt(hw); 970 971 /*read ISR: 4/8bytes */ 972 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb); 973 974 /*Shared IRQ or HW disappared */ 975 if (!inta || inta == 0xffff) 976 goto done; 977 978 /*<1> beacon related */ 979 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) { 980 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 981 "beacon ok interrupt!\n"); 982 } 983 984 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) { 985 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 986 "beacon err interrupt!\n"); 987 } 988 989 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) { 990 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); 991 } 992 993 if (inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) { 994 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 995 "prepare beacon for interrupt!\n"); 996 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet); 997 } 998 999 /*<2> Tx related */ 1000 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW])) 1001 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); 1002 1003 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) { 1004 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1005 "Manage ok interrupt!\n"); 1006 _rtl_pci_tx_isr(hw, MGNT_QUEUE); 1007 } 1008 1009 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) { 1010 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1011 "HIGH_QUEUE ok interrupt!\n"); 1012 _rtl_pci_tx_isr(hw, HIGH_QUEUE); 1013 } 1014 1015 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) { 1016 rtlpriv->link_info.num_tx_inperiod++; 1017 1018 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1019 "BK Tx OK interrupt!\n"); 1020 _rtl_pci_tx_isr(hw, BK_QUEUE); 1021 } 1022 1023 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) { 1024 rtlpriv->link_info.num_tx_inperiod++; 1025 1026 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1027 "BE TX OK interrupt!\n"); 1028 _rtl_pci_tx_isr(hw, BE_QUEUE); 1029 } 1030 1031 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) { 1032 rtlpriv->link_info.num_tx_inperiod++; 1033 1034 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1035 "VI TX OK interrupt!\n"); 1036 _rtl_pci_tx_isr(hw, VI_QUEUE); 1037 } 1038 1039 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) { 1040 rtlpriv->link_info.num_tx_inperiod++; 1041 1042 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1043 "Vo TX OK interrupt!\n"); 1044 _rtl_pci_tx_isr(hw, VO_QUEUE); 1045 } 1046 1047 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) { 1048 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) { 1049 rtlpriv->link_info.num_tx_inperiod++; 1050 1051 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1052 "CMD TX OK interrupt!\n"); 1053 _rtl_pci_tx_isr(hw, TXCMD_QUEUE); 1054 } 1055 } 1056 1057 /*<3> Rx related */ 1058 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) { 1059 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); 1060 _rtl_pci_rx_interrupt(hw); 1061 } 1062 1063 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) { 1064 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1065 "rx descriptor unavailable!\n"); 1066 _rtl_pci_rx_interrupt(hw); 1067 } 1068 1069 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) { 1070 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); 1071 _rtl_pci_rx_interrupt(hw); 1072 } 1073 1074 /*<4> fw related*/ 1075 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { 1076 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) { 1077 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1078 "firmware interrupt!\n"); 1079 queue_delayed_work(rtlpriv->works.rtl_wq, 1080 &rtlpriv->works.fwevt_wq, 0); 1081 } 1082 } 1083 1084 /*<5> hsisr related*/ 1085 /* Only 8188EE & 8723BE Supported. 1086 * If Other ICs Come in, System will corrupt, 1087 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR] 1088 * are not initialized 1089 */ 1090 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE || 1091 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) { 1092 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) { 1093 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1094 "hsisr interrupt!\n"); 1095 _rtl_pci_hs_interrupt(hw); 1096 } 1097 } 1098 1099 if (rtlpriv->rtlhal.earlymode_enable) 1100 tasklet_schedule(&rtlpriv->works.irq_tasklet); 1101 1102 done: 1103 rtlpriv->cfg->ops->enable_interrupt(hw); 1104 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1105 return ret; 1106 } 1107 1108 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw) 1109 { 1110 _rtl_pci_tx_chk_waitq(hw); 1111 } 1112 1113 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw) 1114 { 1115 struct rtl_priv *rtlpriv = rtl_priv(hw); 1116 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1117 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1118 struct rtl8192_tx_ring *ring = NULL; 1119 struct ieee80211_hdr *hdr = NULL; 1120 struct ieee80211_tx_info *info = NULL; 1121 struct sk_buff *pskb = NULL; 1122 struct rtl_tx_desc *pdesc = NULL; 1123 struct rtl_tcb_desc tcb_desc; 1124 /*This is for new trx flow*/ 1125 struct rtl_tx_buffer_desc *pbuffer_desc = NULL; 1126 u8 temp_one = 1; 1127 u8 *entry; 1128 1129 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 1130 ring = &rtlpci->tx_ring[BEACON_QUEUE]; 1131 pskb = __skb_dequeue(&ring->queue); 1132 if (rtlpriv->use_new_trx_flow) 1133 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1134 else 1135 entry = (u8 *)(&ring->desc[ring->idx]); 1136 if (pskb) { 1137 pci_unmap_single(rtlpci->pdev, 1138 rtlpriv->cfg->ops->get_desc( 1139 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR), 1140 pskb->len, PCI_DMA_TODEVICE); 1141 kfree_skb(pskb); 1142 } 1143 1144 /*NB: the beacon data buffer must be 32-bit aligned. */ 1145 pskb = ieee80211_beacon_get(hw, mac->vif); 1146 if (pskb == NULL) 1147 return; 1148 hdr = rtl_get_hdr(pskb); 1149 info = IEEE80211_SKB_CB(pskb); 1150 pdesc = &ring->desc[0]; 1151 if (rtlpriv->use_new_trx_flow) 1152 pbuffer_desc = &ring->buffer_desc[0]; 1153 1154 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1155 (u8 *)pbuffer_desc, info, NULL, pskb, 1156 BEACON_QUEUE, &tcb_desc); 1157 1158 __skb_queue_tail(&ring->queue, pskb); 1159 1160 if (rtlpriv->use_new_trx_flow) { 1161 temp_one = 4; 1162 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true, 1163 HW_DESC_OWN, (u8 *)&temp_one); 1164 } else { 1165 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN, 1166 &temp_one); 1167 } 1168 return; 1169 } 1170 1171 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw) 1172 { 1173 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1174 struct rtl_priv *rtlpriv = rtl_priv(hw); 1175 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1176 u8 i; 1177 u16 desc_num; 1178 1179 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) 1180 desc_num = TX_DESC_NUM_92E; 1181 else 1182 desc_num = RT_TXDESC_NUM; 1183 1184 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1185 rtlpci->txringcount[i] = desc_num; 1186 1187 /* 1188 *we just alloc 2 desc for beacon queue, 1189 *because we just need first desc in hw beacon. 1190 */ 1191 rtlpci->txringcount[BEACON_QUEUE] = 2; 1192 1193 /*BE queue need more descriptor for performance 1194 *consideration or, No more tx desc will happen, 1195 *and may cause mac80211 mem leakage. 1196 */ 1197 if (!rtl_priv(hw)->use_new_trx_flow) 1198 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE; 1199 1200 rtlpci->rxbuffersize = 9100; /*2048/1024; */ 1201 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */ 1202 } 1203 1204 static void _rtl_pci_init_struct(struct ieee80211_hw *hw, 1205 struct pci_dev *pdev) 1206 { 1207 struct rtl_priv *rtlpriv = rtl_priv(hw); 1208 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1209 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1210 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1211 1212 rtlpci->up_first_time = true; 1213 rtlpci->being_init_adapter = false; 1214 1215 rtlhal->hw = hw; 1216 rtlpci->pdev = pdev; 1217 1218 /*Tx/Rx related var */ 1219 _rtl_pci_init_trx_var(hw); 1220 1221 /*IBSS*/ mac->beacon_interval = 100; 1222 1223 /*AMPDU*/ 1224 mac->min_space_cfg = 0; 1225 mac->max_mss_density = 0; 1226 /*set sane AMPDU defaults */ 1227 mac->current_ampdu_density = 7; 1228 mac->current_ampdu_factor = 3; 1229 1230 /*QOS*/ 1231 rtlpci->acm_method = EACMWAY2_SW; 1232 1233 /*task */ 1234 tasklet_init(&rtlpriv->works.irq_tasklet, 1235 (void (*)(unsigned long))_rtl_pci_irq_tasklet, 1236 (unsigned long)hw); 1237 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet, 1238 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet, 1239 (unsigned long)hw); 1240 INIT_WORK(&rtlpriv->works.lps_change_work, 1241 rtl_lps_change_work_callback); 1242 } 1243 1244 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, 1245 unsigned int prio, unsigned int entries) 1246 { 1247 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1248 struct rtl_priv *rtlpriv = rtl_priv(hw); 1249 struct rtl_tx_buffer_desc *buffer_desc; 1250 struct rtl_tx_desc *desc; 1251 dma_addr_t buffer_desc_dma, desc_dma; 1252 u32 nextdescaddress; 1253 int i; 1254 1255 /* alloc tx buffer desc for new trx flow*/ 1256 if (rtlpriv->use_new_trx_flow) { 1257 buffer_desc = 1258 pci_zalloc_consistent(rtlpci->pdev, 1259 sizeof(*buffer_desc) * entries, 1260 &buffer_desc_dma); 1261 1262 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) { 1263 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1264 "Cannot allocate TX ring (prio = %d)\n", 1265 prio); 1266 return -ENOMEM; 1267 } 1268 1269 rtlpci->tx_ring[prio].buffer_desc = buffer_desc; 1270 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma; 1271 1272 rtlpci->tx_ring[prio].cur_tx_rp = 0; 1273 rtlpci->tx_ring[prio].cur_tx_wp = 0; 1274 rtlpci->tx_ring[prio].avl_desc = entries; 1275 } 1276 1277 /* alloc dma for this ring */ 1278 desc = pci_zalloc_consistent(rtlpci->pdev, 1279 sizeof(*desc) * entries, &desc_dma); 1280 1281 if (!desc || (unsigned long)desc & 0xFF) { 1282 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1283 "Cannot allocate TX ring (prio = %d)\n", prio); 1284 return -ENOMEM; 1285 } 1286 1287 rtlpci->tx_ring[prio].desc = desc; 1288 rtlpci->tx_ring[prio].dma = desc_dma; 1289 1290 rtlpci->tx_ring[prio].idx = 0; 1291 rtlpci->tx_ring[prio].entries = entries; 1292 skb_queue_head_init(&rtlpci->tx_ring[prio].queue); 1293 1294 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", 1295 prio, desc); 1296 1297 /* init every desc in this ring */ 1298 if (!rtlpriv->use_new_trx_flow) { 1299 for (i = 0; i < entries; i++) { 1300 nextdescaddress = (u32)desc_dma + 1301 ((i + 1) % entries) * 1302 sizeof(*desc); 1303 1304 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i], 1305 true, 1306 HW_DESC_TX_NEXTDESC_ADDR, 1307 (u8 *)&nextdescaddress); 1308 } 1309 } 1310 return 0; 1311 } 1312 1313 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1314 { 1315 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1316 struct rtl_priv *rtlpriv = rtl_priv(hw); 1317 int i; 1318 1319 if (rtlpriv->use_new_trx_flow) { 1320 struct rtl_rx_buffer_desc *entry = NULL; 1321 /* alloc dma for this ring */ 1322 rtlpci->rx_ring[rxring_idx].buffer_desc = 1323 pci_zalloc_consistent(rtlpci->pdev, 1324 sizeof(*rtlpci->rx_ring[rxring_idx]. 1325 buffer_desc) * 1326 rtlpci->rxringcount, 1327 &rtlpci->rx_ring[rxring_idx].dma); 1328 if (!rtlpci->rx_ring[rxring_idx].buffer_desc || 1329 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) { 1330 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1331 "Cannot allocate RX ring\n"); 1332 return -ENOMEM; 1333 } 1334 1335 /* init every desc in this ring */ 1336 rtlpci->rx_ring[rxring_idx].idx = 0; 1337 for (i = 0; i < rtlpci->rxringcount; i++) { 1338 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i]; 1339 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1340 rxring_idx, i)) 1341 return -ENOMEM; 1342 } 1343 } else { 1344 struct rtl_rx_desc *entry = NULL; 1345 u8 tmp_one = 1; 1346 /* alloc dma for this ring */ 1347 rtlpci->rx_ring[rxring_idx].desc = 1348 pci_zalloc_consistent(rtlpci->pdev, 1349 sizeof(*rtlpci->rx_ring[rxring_idx]. 1350 desc) * rtlpci->rxringcount, 1351 &rtlpci->rx_ring[rxring_idx].dma); 1352 if (!rtlpci->rx_ring[rxring_idx].desc || 1353 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) { 1354 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1355 "Cannot allocate RX ring\n"); 1356 return -ENOMEM; 1357 } 1358 1359 /* init every desc in this ring */ 1360 rtlpci->rx_ring[rxring_idx].idx = 0; 1361 1362 for (i = 0; i < rtlpci->rxringcount; i++) { 1363 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1364 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1365 rxring_idx, i)) 1366 return -ENOMEM; 1367 } 1368 1369 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1370 HW_DESC_RXERO, &tmp_one); 1371 } 1372 return 0; 1373 } 1374 1375 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw, 1376 unsigned int prio) 1377 { 1378 struct rtl_priv *rtlpriv = rtl_priv(hw); 1379 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1380 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 1381 1382 /* free every desc in this ring */ 1383 while (skb_queue_len(&ring->queue)) { 1384 u8 *entry; 1385 struct sk_buff *skb = __skb_dequeue(&ring->queue); 1386 1387 if (rtlpriv->use_new_trx_flow) 1388 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1389 else 1390 entry = (u8 *)(&ring->desc[ring->idx]); 1391 1392 pci_unmap_single(rtlpci->pdev, 1393 rtlpriv->cfg-> 1394 ops->get_desc((u8 *)entry, true, 1395 HW_DESC_TXBUFF_ADDR), 1396 skb->len, PCI_DMA_TODEVICE); 1397 kfree_skb(skb); 1398 ring->idx = (ring->idx + 1) % ring->entries; 1399 } 1400 1401 /* free dma of this ring */ 1402 pci_free_consistent(rtlpci->pdev, 1403 sizeof(*ring->desc) * ring->entries, 1404 ring->desc, ring->dma); 1405 ring->desc = NULL; 1406 if (rtlpriv->use_new_trx_flow) { 1407 pci_free_consistent(rtlpci->pdev, 1408 sizeof(*ring->buffer_desc) * ring->entries, 1409 ring->buffer_desc, ring->buffer_desc_dma); 1410 ring->buffer_desc = NULL; 1411 } 1412 } 1413 1414 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1415 { 1416 struct rtl_priv *rtlpriv = rtl_priv(hw); 1417 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1418 int i; 1419 1420 /* free every desc in this ring */ 1421 for (i = 0; i < rtlpci->rxringcount; i++) { 1422 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i]; 1423 1424 if (!skb) 1425 continue; 1426 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), 1427 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 1428 kfree_skb(skb); 1429 } 1430 1431 /* free dma of this ring */ 1432 if (rtlpriv->use_new_trx_flow) { 1433 pci_free_consistent(rtlpci->pdev, 1434 sizeof(*rtlpci->rx_ring[rxring_idx]. 1435 buffer_desc) * rtlpci->rxringcount, 1436 rtlpci->rx_ring[rxring_idx].buffer_desc, 1437 rtlpci->rx_ring[rxring_idx].dma); 1438 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL; 1439 } else { 1440 pci_free_consistent(rtlpci->pdev, 1441 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1442 rtlpci->rxringcount, 1443 rtlpci->rx_ring[rxring_idx].desc, 1444 rtlpci->rx_ring[rxring_idx].dma); 1445 rtlpci->rx_ring[rxring_idx].desc = NULL; 1446 } 1447 } 1448 1449 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw) 1450 { 1451 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1452 int ret; 1453 int i, rxring_idx; 1454 1455 /* rxring_idx 0:RX_MPDU_QUEUE 1456 * rxring_idx 1:RX_CMD_QUEUE 1457 */ 1458 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1459 ret = _rtl_pci_init_rx_ring(hw, rxring_idx); 1460 if (ret) 1461 return ret; 1462 } 1463 1464 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1465 ret = _rtl_pci_init_tx_ring(hw, i, 1466 rtlpci->txringcount[i]); 1467 if (ret) 1468 goto err_free_rings; 1469 } 1470 1471 return 0; 1472 1473 err_free_rings: 1474 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1475 _rtl_pci_free_rx_ring(hw, rxring_idx); 1476 1477 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1478 if (rtlpci->tx_ring[i].desc || 1479 rtlpci->tx_ring[i].buffer_desc) 1480 _rtl_pci_free_tx_ring(hw, i); 1481 1482 return 1; 1483 } 1484 1485 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw) 1486 { 1487 u32 i, rxring_idx; 1488 1489 /*free rx rings */ 1490 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1491 _rtl_pci_free_rx_ring(hw, rxring_idx); 1492 1493 /*free tx rings */ 1494 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1495 _rtl_pci_free_tx_ring(hw, i); 1496 1497 return 0; 1498 } 1499 1500 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw) 1501 { 1502 struct rtl_priv *rtlpriv = rtl_priv(hw); 1503 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1504 int i, rxring_idx; 1505 unsigned long flags; 1506 u8 tmp_one = 1; 1507 u32 bufferaddress; 1508 /* rxring_idx 0:RX_MPDU_QUEUE */ 1509 /* rxring_idx 1:RX_CMD_QUEUE */ 1510 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1511 /* force the rx_ring[RX_MPDU_QUEUE/ 1512 * RX_CMD_QUEUE].idx to the first one 1513 *new trx flow, do nothing 1514 */ 1515 if (!rtlpriv->use_new_trx_flow && 1516 rtlpci->rx_ring[rxring_idx].desc) { 1517 struct rtl_rx_desc *entry = NULL; 1518 1519 rtlpci->rx_ring[rxring_idx].idx = 0; 1520 for (i = 0; i < rtlpci->rxringcount; i++) { 1521 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1522 bufferaddress = 1523 rtlpriv->cfg->ops->get_desc((u8 *)entry, 1524 false , HW_DESC_RXBUFF_ADDR); 1525 memset((u8 *)entry , 0 , 1526 sizeof(*rtlpci->rx_ring 1527 [rxring_idx].desc));/*clear one entry*/ 1528 if (rtlpriv->use_new_trx_flow) { 1529 rtlpriv->cfg->ops->set_desc(hw, 1530 (u8 *)entry, false, 1531 HW_DESC_RX_PREPARE, 1532 (u8 *)&bufferaddress); 1533 } else { 1534 rtlpriv->cfg->ops->set_desc(hw, 1535 (u8 *)entry, false, 1536 HW_DESC_RXBUFF_ADDR, 1537 (u8 *)&bufferaddress); 1538 rtlpriv->cfg->ops->set_desc(hw, 1539 (u8 *)entry, false, 1540 HW_DESC_RXPKT_LEN, 1541 (u8 *)&rtlpci->rxbuffersize); 1542 rtlpriv->cfg->ops->set_desc(hw, 1543 (u8 *)entry, false, 1544 HW_DESC_RXOWN, 1545 (u8 *)&tmp_one); 1546 } 1547 } 1548 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1549 HW_DESC_RXERO, (u8 *)&tmp_one); 1550 } 1551 rtlpci->rx_ring[rxring_idx].idx = 0; 1552 } 1553 1554 /* 1555 *after reset, release previous pending packet, 1556 *and force the tx idx to the first one 1557 */ 1558 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1559 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1560 if (rtlpci->tx_ring[i].desc || 1561 rtlpci->tx_ring[i].buffer_desc) { 1562 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i]; 1563 1564 while (skb_queue_len(&ring->queue)) { 1565 u8 *entry; 1566 struct sk_buff *skb = 1567 __skb_dequeue(&ring->queue); 1568 if (rtlpriv->use_new_trx_flow) 1569 entry = (u8 *)(&ring->buffer_desc 1570 [ring->idx]); 1571 else 1572 entry = (u8 *)(&ring->desc[ring->idx]); 1573 1574 pci_unmap_single(rtlpci->pdev, 1575 rtlpriv->cfg->ops-> 1576 get_desc((u8 *) 1577 entry, 1578 true, 1579 HW_DESC_TXBUFF_ADDR), 1580 skb->len, PCI_DMA_TODEVICE); 1581 kfree_skb(skb); 1582 ring->idx = (ring->idx + 1) % ring->entries; 1583 } 1584 ring->idx = 0; 1585 } 1586 } 1587 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1588 1589 return 0; 1590 } 1591 1592 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw, 1593 struct ieee80211_sta *sta, 1594 struct sk_buff *skb) 1595 { 1596 struct rtl_priv *rtlpriv = rtl_priv(hw); 1597 struct rtl_sta_info *sta_entry = NULL; 1598 u8 tid = rtl_get_tid(skb); 1599 __le16 fc = rtl_get_fc(skb); 1600 1601 if (!sta) 1602 return false; 1603 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1604 1605 if (!rtlpriv->rtlhal.earlymode_enable) 1606 return false; 1607 if (ieee80211_is_nullfunc(fc)) 1608 return false; 1609 if (ieee80211_is_qos_nullfunc(fc)) 1610 return false; 1611 if (ieee80211_is_pspoll(fc)) 1612 return false; 1613 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL) 1614 return false; 1615 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE) 1616 return false; 1617 if (tid > 7) 1618 return false; 1619 1620 /* maybe every tid should be checked */ 1621 if (!rtlpriv->link_info.higher_busytxtraffic[tid]) 1622 return false; 1623 1624 spin_lock_bh(&rtlpriv->locks.waitq_lock); 1625 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb); 1626 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 1627 1628 return true; 1629 } 1630 1631 static int rtl_pci_tx(struct ieee80211_hw *hw, 1632 struct ieee80211_sta *sta, 1633 struct sk_buff *skb, 1634 struct rtl_tcb_desc *ptcb_desc) 1635 { 1636 struct rtl_priv *rtlpriv = rtl_priv(hw); 1637 struct rtl_sta_info *sta_entry = NULL; 1638 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1639 struct rtl8192_tx_ring *ring; 1640 struct rtl_tx_desc *pdesc; 1641 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL; 1642 u16 idx; 1643 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb); 1644 unsigned long flags; 1645 struct ieee80211_hdr *hdr = rtl_get_hdr(skb); 1646 __le16 fc = rtl_get_fc(skb); 1647 u8 *pda_addr = hdr->addr1; 1648 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1649 /*ssn */ 1650 u8 tid = 0; 1651 u16 seq_number = 0; 1652 u8 own; 1653 u8 temp_one = 1; 1654 1655 if (ieee80211_is_mgmt(fc)) 1656 rtl_tx_mgmt_proc(hw, skb); 1657 1658 if (rtlpriv->psc.sw_ps_enabled) { 1659 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) && 1660 !ieee80211_has_pm(fc)) 1661 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1662 } 1663 1664 rtl_action_proc(hw, skb, true); 1665 1666 if (is_multicast_ether_addr(pda_addr)) 1667 rtlpriv->stats.txbytesmulticast += skb->len; 1668 else if (is_broadcast_ether_addr(pda_addr)) 1669 rtlpriv->stats.txbytesbroadcast += skb->len; 1670 else 1671 rtlpriv->stats.txbytesunicast += skb->len; 1672 1673 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1674 ring = &rtlpci->tx_ring[hw_queue]; 1675 if (hw_queue != BEACON_QUEUE) { 1676 if (rtlpriv->use_new_trx_flow) 1677 idx = ring->cur_tx_wp; 1678 else 1679 idx = (ring->idx + skb_queue_len(&ring->queue)) % 1680 ring->entries; 1681 } else { 1682 idx = 0; 1683 } 1684 1685 pdesc = &ring->desc[idx]; 1686 if (rtlpriv->use_new_trx_flow) { 1687 ptx_bd_desc = &ring->buffer_desc[idx]; 1688 } else { 1689 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *)pdesc, 1690 true, HW_DESC_OWN); 1691 1692 if ((own == 1) && (hw_queue != BEACON_QUEUE)) { 1693 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1694 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1695 hw_queue, ring->idx, idx, 1696 skb_queue_len(&ring->queue)); 1697 1698 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, 1699 flags); 1700 return skb->len; 1701 } 1702 } 1703 1704 if (rtlpriv->cfg->ops->get_available_desc && 1705 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) { 1706 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1707 "get_available_desc fail\n"); 1708 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, 1709 flags); 1710 return skb->len; 1711 } 1712 1713 if (ieee80211_is_data_qos(fc)) { 1714 tid = rtl_get_tid(skb); 1715 if (sta) { 1716 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1717 seq_number = (le16_to_cpu(hdr->seq_ctrl) & 1718 IEEE80211_SCTL_SEQ) >> 4; 1719 seq_number += 1; 1720 1721 if (!ieee80211_has_morefrags(hdr->frame_control)) 1722 sta_entry->tids[tid].seq_number = seq_number; 1723 } 1724 } 1725 1726 if (ieee80211_is_data(fc)) 1727 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX); 1728 1729 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1730 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc); 1731 1732 __skb_queue_tail(&ring->queue, skb); 1733 1734 if (rtlpriv->use_new_trx_flow) { 1735 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1736 HW_DESC_OWN, &hw_queue); 1737 } else { 1738 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1739 HW_DESC_OWN, &temp_one); 1740 } 1741 1742 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 && 1743 hw_queue != BEACON_QUEUE) { 1744 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 1745 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1746 hw_queue, ring->idx, idx, 1747 skb_queue_len(&ring->queue)); 1748 1749 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 1750 } 1751 1752 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1753 1754 rtlpriv->cfg->ops->tx_polling(hw, hw_queue); 1755 1756 return 0; 1757 } 1758 1759 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1760 { 1761 struct rtl_priv *rtlpriv = rtl_priv(hw); 1762 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1763 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1764 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1765 u16 i = 0; 1766 int queue_id; 1767 struct rtl8192_tx_ring *ring; 1768 1769 if (mac->skip_scan) 1770 return; 1771 1772 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) { 1773 u32 queue_len; 1774 1775 if (((queues >> queue_id) & 0x1) == 0) { 1776 queue_id--; 1777 continue; 1778 } 1779 ring = &pcipriv->dev.tx_ring[queue_id]; 1780 queue_len = skb_queue_len(&ring->queue); 1781 if (queue_len == 0 || queue_id == BEACON_QUEUE || 1782 queue_id == TXCMD_QUEUE) { 1783 queue_id--; 1784 continue; 1785 } else { 1786 msleep(20); 1787 i++; 1788 } 1789 1790 /* we just wait 1s for all queues */ 1791 if (rtlpriv->psc.rfpwr_state == ERFOFF || 1792 is_hal_stop(rtlhal) || i >= 200) 1793 return; 1794 } 1795 } 1796 1797 static void rtl_pci_deinit(struct ieee80211_hw *hw) 1798 { 1799 struct rtl_priv *rtlpriv = rtl_priv(hw); 1800 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1801 1802 _rtl_pci_deinit_trx_ring(hw); 1803 1804 synchronize_irq(rtlpci->pdev->irq); 1805 tasklet_kill(&rtlpriv->works.irq_tasklet); 1806 cancel_work_sync(&rtlpriv->works.lps_change_work); 1807 1808 flush_workqueue(rtlpriv->works.rtl_wq); 1809 destroy_workqueue(rtlpriv->works.rtl_wq); 1810 1811 } 1812 1813 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev) 1814 { 1815 struct rtl_priv *rtlpriv = rtl_priv(hw); 1816 int err; 1817 1818 _rtl_pci_init_struct(hw, pdev); 1819 1820 err = _rtl_pci_init_trx_ring(hw); 1821 if (err) { 1822 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1823 "tx ring initialization failed\n"); 1824 return err; 1825 } 1826 1827 return 0; 1828 } 1829 1830 static int rtl_pci_start(struct ieee80211_hw *hw) 1831 { 1832 struct rtl_priv *rtlpriv = rtl_priv(hw); 1833 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1834 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1835 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1836 1837 int err; 1838 1839 rtl_pci_reset_trx_ring(hw); 1840 1841 rtlpci->driver_is_goingto_unload = false; 1842 if (rtlpriv->cfg->ops->get_btc_status && 1843 rtlpriv->cfg->ops->get_btc_status()) { 1844 rtlpriv->btcoexist.btc_ops->btc_init_variables(rtlpriv); 1845 rtlpriv->btcoexist.btc_ops->btc_init_hal_vars(rtlpriv); 1846 } 1847 err = rtlpriv->cfg->ops->hw_init(hw); 1848 if (err) { 1849 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1850 "Failed to config hardware!\n"); 1851 return err; 1852 } 1853 1854 rtlpriv->cfg->ops->enable_interrupt(hw); 1855 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); 1856 1857 rtl_init_rx_config(hw); 1858 1859 /*should be after adapter start and interrupt enable. */ 1860 set_hal_start(rtlhal); 1861 1862 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1863 1864 rtlpci->up_first_time = false; 1865 1866 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "rtl_pci_start OK\n"); 1867 return 0; 1868 } 1869 1870 static void rtl_pci_stop(struct ieee80211_hw *hw) 1871 { 1872 struct rtl_priv *rtlpriv = rtl_priv(hw); 1873 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1874 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1875 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1876 unsigned long flags; 1877 u8 RFInProgressTimeOut = 0; 1878 1879 if (rtlpriv->cfg->ops->get_btc_status()) 1880 rtlpriv->btcoexist.btc_ops->btc_halt_notify(); 1881 1882 /* 1883 *should be before disable interrupt&adapter 1884 *and will do it immediately. 1885 */ 1886 set_hal_stop(rtlhal); 1887 1888 rtlpci->driver_is_goingto_unload = true; 1889 rtlpriv->cfg->ops->disable_interrupt(hw); 1890 cancel_work_sync(&rtlpriv->works.lps_change_work); 1891 1892 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1893 while (ppsc->rfchange_inprogress) { 1894 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1895 if (RFInProgressTimeOut > 100) { 1896 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1897 break; 1898 } 1899 mdelay(1); 1900 RFInProgressTimeOut++; 1901 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1902 } 1903 ppsc->rfchange_inprogress = true; 1904 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1905 1906 rtlpriv->cfg->ops->hw_disable(hw); 1907 /* some things are not needed if firmware not available */ 1908 if (!rtlpriv->max_fw_size) 1909 return; 1910 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1911 1912 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1913 ppsc->rfchange_inprogress = false; 1914 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1915 1916 rtl_pci_enable_aspm(hw); 1917 } 1918 1919 static bool _rtl_pci_find_adapter(struct pci_dev *pdev, 1920 struct ieee80211_hw *hw) 1921 { 1922 struct rtl_priv *rtlpriv = rtl_priv(hw); 1923 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1924 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1925 struct pci_dev *bridge_pdev = pdev->bus->self; 1926 u16 venderid; 1927 u16 deviceid; 1928 u8 revisionid; 1929 u16 irqline; 1930 u8 tmp; 1931 1932 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1933 venderid = pdev->vendor; 1934 deviceid = pdev->device; 1935 pci_read_config_byte(pdev, 0x8, &revisionid); 1936 pci_read_config_word(pdev, 0x3C, &irqline); 1937 1938 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses 1939 * r8192e_pci, and RTL8192SE, which uses this driver. If the 1940 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then 1941 * the correct driver is r8192e_pci, thus this routine should 1942 * return false. 1943 */ 1944 if (deviceid == RTL_PCI_8192SE_DID && 1945 revisionid == RTL_PCI_REVISION_ID_8192PCIE) 1946 return false; 1947 1948 if (deviceid == RTL_PCI_8192_DID || 1949 deviceid == RTL_PCI_0044_DID || 1950 deviceid == RTL_PCI_0047_DID || 1951 deviceid == RTL_PCI_8192SE_DID || 1952 deviceid == RTL_PCI_8174_DID || 1953 deviceid == RTL_PCI_8173_DID || 1954 deviceid == RTL_PCI_8172_DID || 1955 deviceid == RTL_PCI_8171_DID) { 1956 switch (revisionid) { 1957 case RTL_PCI_REVISION_ID_8192PCIE: 1958 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1959 "8192 PCI-E is found - vid/did=%x/%x\n", 1960 venderid, deviceid); 1961 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E; 1962 return false; 1963 case RTL_PCI_REVISION_ID_8192SE: 1964 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1965 "8192SE is found - vid/did=%x/%x\n", 1966 venderid, deviceid); 1967 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1968 break; 1969 default: 1970 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1971 "Err: Unknown device - vid/did=%x/%x\n", 1972 venderid, deviceid); 1973 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1974 break; 1975 1976 } 1977 } else if (deviceid == RTL_PCI_8723AE_DID) { 1978 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE; 1979 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1980 "8723AE PCI-E is found - " 1981 "vid/did=%x/%x\n", venderid, deviceid); 1982 } else if (deviceid == RTL_PCI_8192CET_DID || 1983 deviceid == RTL_PCI_8192CE_DID || 1984 deviceid == RTL_PCI_8191CE_DID || 1985 deviceid == RTL_PCI_8188CE_DID) { 1986 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE; 1987 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1988 "8192C PCI-E is found - vid/did=%x/%x\n", 1989 venderid, deviceid); 1990 } else if (deviceid == RTL_PCI_8192DE_DID || 1991 deviceid == RTL_PCI_8192DE_DID2) { 1992 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE; 1993 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1994 "8192D PCI-E is found - vid/did=%x/%x\n", 1995 venderid, deviceid); 1996 } else if (deviceid == RTL_PCI_8188EE_DID) { 1997 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE; 1998 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1999 "Find adapter, Hardware type is 8188EE\n"); 2000 } else if (deviceid == RTL_PCI_8723BE_DID) { 2001 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE; 2002 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, 2003 "Find adapter, Hardware type is 8723BE\n"); 2004 } else if (deviceid == RTL_PCI_8192EE_DID) { 2005 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE; 2006 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, 2007 "Find adapter, Hardware type is 8192EE\n"); 2008 } else if (deviceid == RTL_PCI_8821AE_DID) { 2009 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE; 2010 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, 2011 "Find adapter, Hardware type is 8821AE\n"); 2012 } else if (deviceid == RTL_PCI_8812AE_DID) { 2013 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE; 2014 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, 2015 "Find adapter, Hardware type is 8812AE\n"); 2016 } else { 2017 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2018 "Err: Unknown device - vid/did=%x/%x\n", 2019 venderid, deviceid); 2020 2021 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE; 2022 } 2023 2024 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) { 2025 if (revisionid == 0 || revisionid == 1) { 2026 if (revisionid == 0) { 2027 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2028 "Find 92DE MAC0\n"); 2029 rtlhal->interfaceindex = 0; 2030 } else if (revisionid == 1) { 2031 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2032 "Find 92DE MAC1\n"); 2033 rtlhal->interfaceindex = 1; 2034 } 2035 } else { 2036 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2037 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", 2038 venderid, deviceid, revisionid); 2039 rtlhal->interfaceindex = 0; 2040 } 2041 } 2042 2043 /* 92ee use new trx flow */ 2044 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) 2045 rtlpriv->use_new_trx_flow = true; 2046 else 2047 rtlpriv->use_new_trx_flow = false; 2048 2049 /*find bus info */ 2050 pcipriv->ndis_adapter.busnumber = pdev->bus->number; 2051 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn); 2052 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn); 2053 2054 /*find bridge info */ 2055 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 2056 /* some ARM have no bridge_pdev and will crash here 2057 * so we should check if bridge_pdev is NULL 2058 */ 2059 if (bridge_pdev) { 2060 /*find bridge info if available */ 2061 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor; 2062 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { 2063 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { 2064 pcipriv->ndis_adapter.pcibridge_vendor = tmp; 2065 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2066 "Pci Bridge Vendor is found index: %d\n", 2067 tmp); 2068 break; 2069 } 2070 } 2071 } 2072 2073 if (pcipriv->ndis_adapter.pcibridge_vendor != 2074 PCI_BRIDGE_VENDOR_UNKNOWN) { 2075 pcipriv->ndis_adapter.pcibridge_busnum = 2076 bridge_pdev->bus->number; 2077 pcipriv->ndis_adapter.pcibridge_devnum = 2078 PCI_SLOT(bridge_pdev->devfn); 2079 pcipriv->ndis_adapter.pcibridge_funcnum = 2080 PCI_FUNC(bridge_pdev->devfn); 2081 pcipriv->ndis_adapter.pcibridge_pciehdr_offset = 2082 pci_pcie_cap(bridge_pdev); 2083 pcipriv->ndis_adapter.num4bytes = 2084 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4; 2085 2086 rtl_pci_get_linkcontrol_field(hw); 2087 2088 if (pcipriv->ndis_adapter.pcibridge_vendor == 2089 PCI_BRIDGE_VENDOR_AMD) { 2090 pcipriv->ndis_adapter.amd_l1_patch = 2091 rtl_pci_get_amd_l1_patch(hw); 2092 } 2093 } 2094 2095 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2096 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", 2097 pcipriv->ndis_adapter.busnumber, 2098 pcipriv->ndis_adapter.devnumber, 2099 pcipriv->ndis_adapter.funcnumber, 2100 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); 2101 2102 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2103 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n", 2104 pcipriv->ndis_adapter.pcibridge_busnum, 2105 pcipriv->ndis_adapter.pcibridge_devnum, 2106 pcipriv->ndis_adapter.pcibridge_funcnum, 2107 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], 2108 pcipriv->ndis_adapter.pcibridge_pciehdr_offset, 2109 pcipriv->ndis_adapter.pcibridge_linkctrlreg, 2110 pcipriv->ndis_adapter.amd_l1_patch); 2111 2112 rtl_pci_parse_configuration(pdev, hw); 2113 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list); 2114 2115 return true; 2116 } 2117 2118 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw) 2119 { 2120 struct rtl_priv *rtlpriv = rtl_priv(hw); 2121 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2122 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2123 int ret; 2124 2125 ret = pci_enable_msi(rtlpci->pdev); 2126 if (ret < 0) 2127 return ret; 2128 2129 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2130 IRQF_SHARED, KBUILD_MODNAME, hw); 2131 if (ret < 0) { 2132 pci_disable_msi(rtlpci->pdev); 2133 return ret; 2134 } 2135 2136 rtlpci->using_msi = true; 2137 2138 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG, 2139 "MSI Interrupt Mode!\n"); 2140 return 0; 2141 } 2142 2143 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw) 2144 { 2145 struct rtl_priv *rtlpriv = rtl_priv(hw); 2146 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2147 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2148 int ret; 2149 2150 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2151 IRQF_SHARED, KBUILD_MODNAME, hw); 2152 if (ret < 0) 2153 return ret; 2154 2155 rtlpci->using_msi = false; 2156 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG, 2157 "Pin-based Interrupt Mode!\n"); 2158 return 0; 2159 } 2160 2161 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw) 2162 { 2163 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2164 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2165 int ret; 2166 2167 if (rtlpci->msi_support) { 2168 ret = rtl_pci_intr_mode_msi(hw); 2169 if (ret < 0) 2170 ret = rtl_pci_intr_mode_legacy(hw); 2171 } else { 2172 ret = rtl_pci_intr_mode_legacy(hw); 2173 } 2174 return ret; 2175 } 2176 2177 int rtl_pci_probe(struct pci_dev *pdev, 2178 const struct pci_device_id *id) 2179 { 2180 struct ieee80211_hw *hw = NULL; 2181 2182 struct rtl_priv *rtlpriv = NULL; 2183 struct rtl_pci_priv *pcipriv = NULL; 2184 struct rtl_pci *rtlpci; 2185 unsigned long pmem_start, pmem_len, pmem_flags; 2186 int err; 2187 2188 err = pci_enable_device(pdev); 2189 if (err) { 2190 RT_ASSERT(false, "%s : Cannot enable new PCI device\n", 2191 pci_name(pdev)); 2192 return err; 2193 } 2194 2195 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 2196 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 2197 RT_ASSERT(false, 2198 "Unable to obtain 32bit DMA for consistent allocations\n"); 2199 err = -ENOMEM; 2200 goto fail1; 2201 } 2202 } 2203 2204 pci_set_master(pdev); 2205 2206 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) + 2207 sizeof(struct rtl_priv), &rtl_ops); 2208 if (!hw) { 2209 RT_ASSERT(false, 2210 "%s : ieee80211 alloc failed\n", pci_name(pdev)); 2211 err = -ENOMEM; 2212 goto fail1; 2213 } 2214 2215 SET_IEEE80211_DEV(hw, &pdev->dev); 2216 pci_set_drvdata(pdev, hw); 2217 2218 rtlpriv = hw->priv; 2219 rtlpriv->hw = hw; 2220 pcipriv = (void *)rtlpriv->priv; 2221 pcipriv->dev.pdev = pdev; 2222 init_completion(&rtlpriv->firmware_loading_complete); 2223 /*proximity init here*/ 2224 rtlpriv->proximity.proxim_on = false; 2225 2226 pcipriv = (void *)rtlpriv->priv; 2227 pcipriv->dev.pdev = pdev; 2228 2229 /* init cfg & intf_ops */ 2230 rtlpriv->rtlhal.interface = INTF_PCI; 2231 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data); 2232 rtlpriv->intf_ops = &rtl_pci_ops; 2233 rtlpriv->glb_var = &rtl_global_var; 2234 2235 /* 2236 *init dbgp flags before all 2237 *other functions, because we will 2238 *use it in other funtions like 2239 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA 2240 *you can not use these macro 2241 *before this 2242 */ 2243 rtl_dbgp_flag_init(hw); 2244 2245 /* MEM map */ 2246 err = pci_request_regions(pdev, KBUILD_MODNAME); 2247 if (err) { 2248 RT_ASSERT(false, "Can't obtain PCI resources\n"); 2249 goto fail1; 2250 } 2251 2252 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id); 2253 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id); 2254 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id); 2255 2256 /*shared mem start */ 2257 rtlpriv->io.pci_mem_start = 2258 (unsigned long)pci_iomap(pdev, 2259 rtlpriv->cfg->bar_id, pmem_len); 2260 if (rtlpriv->io.pci_mem_start == 0) { 2261 RT_ASSERT(false, "Can't map PCI mem\n"); 2262 err = -ENOMEM; 2263 goto fail2; 2264 } 2265 2266 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2267 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", 2268 pmem_start, pmem_len, pmem_flags, 2269 rtlpriv->io.pci_mem_start); 2270 2271 /* Disable Clk Request */ 2272 pci_write_config_byte(pdev, 0x81, 0); 2273 /* leave D3 mode */ 2274 pci_write_config_byte(pdev, 0x44, 0); 2275 pci_write_config_byte(pdev, 0x04, 0x06); 2276 pci_write_config_byte(pdev, 0x04, 0x07); 2277 2278 /* find adapter */ 2279 if (!_rtl_pci_find_adapter(pdev, hw)) { 2280 err = -ENODEV; 2281 goto fail3; 2282 } 2283 2284 /* Init IO handler */ 2285 _rtl_pci_io_handler_init(&pdev->dev, hw); 2286 2287 /*like read eeprom and so on */ 2288 rtlpriv->cfg->ops->read_eeprom_info(hw); 2289 2290 if (rtlpriv->cfg->ops->init_sw_vars(hw)) { 2291 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Can't init_sw_vars\n"); 2292 err = -ENODEV; 2293 goto fail3; 2294 } 2295 rtlpriv->cfg->ops->init_sw_leds(hw); 2296 2297 /*aspm */ 2298 rtl_pci_init_aspm(hw); 2299 2300 /* Init mac80211 sw */ 2301 err = rtl_init_core(hw); 2302 if (err) { 2303 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2304 "Can't allocate sw for mac80211\n"); 2305 goto fail3; 2306 } 2307 2308 /* Init PCI sw */ 2309 err = rtl_pci_init(hw, pdev); 2310 if (err) { 2311 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Failed to init PCI\n"); 2312 goto fail3; 2313 } 2314 2315 err = ieee80211_register_hw(hw); 2316 if (err) { 2317 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2318 "Can't register mac80211 hw.\n"); 2319 err = -ENODEV; 2320 goto fail3; 2321 } 2322 rtlpriv->mac80211.mac80211_registered = 1; 2323 2324 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group); 2325 if (err) { 2326 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2327 "failed to create sysfs device attributes\n"); 2328 goto fail3; 2329 } 2330 2331 /*init rfkill */ 2332 rtl_init_rfkill(hw); /* Init PCI sw */ 2333 2334 rtlpci = rtl_pcidev(pcipriv); 2335 err = rtl_pci_intr_mode_decide(hw); 2336 if (err) { 2337 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2338 "%s: failed to register IRQ handler\n", 2339 wiphy_name(hw->wiphy)); 2340 goto fail3; 2341 } 2342 rtlpci->irq_alloc = 1; 2343 2344 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2345 return 0; 2346 2347 fail3: 2348 pci_set_drvdata(pdev, NULL); 2349 rtl_deinit_core(hw); 2350 2351 if (rtlpriv->io.pci_mem_start != 0) 2352 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2353 2354 fail2: 2355 pci_release_regions(pdev); 2356 complete(&rtlpriv->firmware_loading_complete); 2357 2358 fail1: 2359 if (hw) 2360 ieee80211_free_hw(hw); 2361 pci_disable_device(pdev); 2362 2363 return err; 2364 2365 } 2366 EXPORT_SYMBOL(rtl_pci_probe); 2367 2368 void rtl_pci_disconnect(struct pci_dev *pdev) 2369 { 2370 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2371 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2372 struct rtl_priv *rtlpriv = rtl_priv(hw); 2373 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2374 struct rtl_mac *rtlmac = rtl_mac(rtlpriv); 2375 2376 /* just in case driver is removed before firmware callback */ 2377 wait_for_completion(&rtlpriv->firmware_loading_complete); 2378 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2379 2380 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group); 2381 2382 /*ieee80211_unregister_hw will call ops_stop */ 2383 if (rtlmac->mac80211_registered == 1) { 2384 ieee80211_unregister_hw(hw); 2385 rtlmac->mac80211_registered = 0; 2386 } else { 2387 rtl_deinit_deferred_work(hw); 2388 rtlpriv->intf_ops->adapter_stop(hw); 2389 } 2390 rtlpriv->cfg->ops->disable_interrupt(hw); 2391 2392 /*deinit rfkill */ 2393 rtl_deinit_rfkill(hw); 2394 2395 rtl_pci_deinit(hw); 2396 rtl_deinit_core(hw); 2397 rtlpriv->cfg->ops->deinit_sw_vars(hw); 2398 2399 if (rtlpci->irq_alloc) { 2400 synchronize_irq(rtlpci->pdev->irq); 2401 free_irq(rtlpci->pdev->irq, hw); 2402 rtlpci->irq_alloc = 0; 2403 } 2404 2405 if (rtlpci->using_msi) 2406 pci_disable_msi(rtlpci->pdev); 2407 2408 list_del(&rtlpriv->list); 2409 if (rtlpriv->io.pci_mem_start != 0) { 2410 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2411 pci_release_regions(pdev); 2412 } 2413 2414 pci_disable_device(pdev); 2415 2416 rtl_pci_disable_aspm(hw); 2417 2418 pci_set_drvdata(pdev, NULL); 2419 2420 ieee80211_free_hw(hw); 2421 } 2422 EXPORT_SYMBOL(rtl_pci_disconnect); 2423 2424 #ifdef CONFIG_PM_SLEEP 2425 /*************************************** 2426 kernel pci power state define: 2427 PCI_D0 ((pci_power_t __force) 0) 2428 PCI_D1 ((pci_power_t __force) 1) 2429 PCI_D2 ((pci_power_t __force) 2) 2430 PCI_D3hot ((pci_power_t __force) 3) 2431 PCI_D3cold ((pci_power_t __force) 4) 2432 PCI_UNKNOWN ((pci_power_t __force) 5) 2433 2434 This function is called when system 2435 goes into suspend state mac80211 will 2436 call rtl_mac_stop() from the mac80211 2437 suspend function first, So there is 2438 no need to call hw_disable here. 2439 ****************************************/ 2440 int rtl_pci_suspend(struct device *dev) 2441 { 2442 struct pci_dev *pdev = to_pci_dev(dev); 2443 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2444 struct rtl_priv *rtlpriv = rtl_priv(hw); 2445 2446 rtlpriv->cfg->ops->hw_suspend(hw); 2447 rtl_deinit_rfkill(hw); 2448 2449 return 0; 2450 } 2451 EXPORT_SYMBOL(rtl_pci_suspend); 2452 2453 int rtl_pci_resume(struct device *dev) 2454 { 2455 struct pci_dev *pdev = to_pci_dev(dev); 2456 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2457 struct rtl_priv *rtlpriv = rtl_priv(hw); 2458 2459 rtlpriv->cfg->ops->hw_resume(hw); 2460 rtl_init_rfkill(hw); 2461 return 0; 2462 } 2463 EXPORT_SYMBOL(rtl_pci_resume); 2464 #endif /* CONFIG_PM_SLEEP */ 2465 2466 struct rtl_intf_ops rtl_pci_ops = { 2467 .read_efuse_byte = read_efuse_byte, 2468 .adapter_start = rtl_pci_start, 2469 .adapter_stop = rtl_pci_stop, 2470 .check_buddy_priv = rtl_pci_check_buddy_priv, 2471 .adapter_tx = rtl_pci_tx, 2472 .flush = rtl_pci_flush, 2473 .reset_trx_ring = rtl_pci_reset_trx_ring, 2474 .waitq_insert = rtl_pci_tx_chk_waitq_insert, 2475 2476 .disable_aspm = rtl_pci_disable_aspm, 2477 .enable_aspm = rtl_pci_enable_aspm, 2478 }; 2479