1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #include "wifi.h"
5 #include "core.h"
6 #include "pci.h"
7 #include "base.h"
8 #include "ps.h"
9 #include "efuse.h"
10 #include <linux/interrupt.h>
11 #include <linux/export.h>
12 #include <linux/module.h>
13 
14 MODULE_AUTHOR("lizhaoming	<chaoming_li@realsil.com.cn>");
15 MODULE_AUTHOR("Realtek WlanFAE	<wlanfae@realtek.com>");
16 MODULE_AUTHOR("Larry Finger	<Larry.FInger@lwfinger.net>");
17 MODULE_LICENSE("GPL");
18 MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
19 
20 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
21 	INTEL_VENDOR_ID,
22 	ATI_VENDOR_ID,
23 	AMD_VENDOR_ID,
24 	SIS_VENDOR_ID
25 };
26 
27 static const u8 ac_to_hwq[] = {
28 	VO_QUEUE,
29 	VI_QUEUE,
30 	BE_QUEUE,
31 	BK_QUEUE
32 };
33 
34 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb)
35 {
36 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
37 	__le16 fc = rtl_get_fc(skb);
38 	u8 queue_index = skb_get_queue_mapping(skb);
39 	struct ieee80211_hdr *hdr;
40 
41 	if (unlikely(ieee80211_is_beacon(fc)))
42 		return BEACON_QUEUE;
43 	if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
44 		return MGNT_QUEUE;
45 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
46 		if (ieee80211_is_nullfunc(fc))
47 			return HIGH_QUEUE;
48 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
49 		hdr = rtl_get_hdr(skb);
50 
51 		if (is_multicast_ether_addr(hdr->addr1) ||
52 		    is_broadcast_ether_addr(hdr->addr1))
53 			return HIGH_QUEUE;
54 	}
55 
56 	return ac_to_hwq[queue_index];
57 }
58 
59 /* Update PCI dependent default settings*/
60 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
61 {
62 	struct rtl_priv *rtlpriv = rtl_priv(hw);
63 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
64 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
65 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
66 	u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
67 	u8 init_aspm;
68 
69 	ppsc->reg_rfps_level = 0;
70 	ppsc->support_aspm = false;
71 
72 	/*Update PCI ASPM setting */
73 	ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
74 	switch (rtlpci->const_pci_aspm) {
75 	case 0:
76 		/*No ASPM */
77 		break;
78 
79 	case 1:
80 		/*ASPM dynamically enabled/disable. */
81 		ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
82 		break;
83 
84 	case 2:
85 		/*ASPM with Clock Req dynamically enabled/disable. */
86 		ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
87 					 RT_RF_OFF_LEVL_CLK_REQ);
88 		break;
89 
90 	case 3:
91 		/* Always enable ASPM and Clock Req
92 		 * from initialization to halt.
93 		 */
94 		ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
95 		ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
96 					 RT_RF_OFF_LEVL_CLK_REQ);
97 		break;
98 
99 	case 4:
100 		/* Always enable ASPM without Clock Req
101 		 * from initialization to halt.
102 		 */
103 		ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
104 					  RT_RF_OFF_LEVL_CLK_REQ);
105 		ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
106 		break;
107 	}
108 
109 	ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
110 
111 	/*Update Radio OFF setting */
112 	switch (rtlpci->const_hwsw_rfoff_d3) {
113 	case 1:
114 		if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
115 			ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
116 		break;
117 
118 	case 2:
119 		if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
120 			ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
121 		ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
122 		break;
123 
124 	case 3:
125 		ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
126 		break;
127 	}
128 
129 	/*Set HW definition to determine if it supports ASPM. */
130 	switch (rtlpci->const_support_pciaspm) {
131 	case 0:
132 		/*Not support ASPM. */
133 		ppsc->support_aspm = false;
134 		break;
135 	case 1:
136 		/*Support ASPM. */
137 		ppsc->support_aspm = true;
138 		ppsc->support_backdoor = true;
139 		break;
140 	case 2:
141 		/*ASPM value set by chipset. */
142 		if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
143 			ppsc->support_aspm = true;
144 		break;
145 	default:
146 		pr_err("switch case %#x not processed\n",
147 		       rtlpci->const_support_pciaspm);
148 		break;
149 	}
150 
151 	/* toshiba aspm issue, toshiba will set aspm selfly
152 	 * so we should not set aspm in driver
153 	 */
154 	pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
155 	if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
156 	    init_aspm == 0x43)
157 		ppsc->support_aspm = false;
158 }
159 
160 static bool _rtl_pci_platform_switch_device_pci_aspm(
161 			struct ieee80211_hw *hw,
162 			u8 value)
163 {
164 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
165 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
166 
167 	value &= PCI_EXP_LNKCTL_ASPMC;
168 
169 	if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
170 		value |= PCI_EXP_LNKCTL_CCC;
171 
172 	pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL,
173 					   PCI_EXP_LNKCTL_ASPMC | value,
174 					   value);
175 
176 	return false;
177 }
178 
179 /* @value is PCI_EXP_LNKCTL_CLKREQ_EN or 0 to enable/disable clk request. */
180 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u16 value)
181 {
182 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
183 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
184 
185 	value &= PCI_EXP_LNKCTL_CLKREQ_EN;
186 
187 	pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL,
188 					   PCI_EXP_LNKCTL_CLKREQ_EN,
189 					   value);
190 
191 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
192 		udelay(100);
193 }
194 
195 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
196 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
197 {
198 	struct rtl_priv *rtlpriv = rtl_priv(hw);
199 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
200 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
201 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
202 	u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
203 	/*Retrieve original configuration settings. */
204 	u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
205 	u16 aspmlevel = 0;
206 	u8 tmp_u1b = 0;
207 
208 	if (!ppsc->support_aspm)
209 		return;
210 
211 	if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
212 		rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
213 			"PCI(Bridge) UNKNOWN\n");
214 
215 		return;
216 	}
217 
218 	if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
219 		RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
220 		_rtl_pci_switch_clk_req(hw, 0x0);
221 	}
222 
223 	/*for promising device will in L0 state after an I/O. */
224 	pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
225 
226 	/*Set corresponding value. */
227 	aspmlevel |= BIT(0) | BIT(1);
228 	linkctrl_reg &= ~aspmlevel;
229 
230 	_rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
231 }
232 
233 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
234  *power saving We should follow the sequence to enable
235  *RTL8192SE first then enable Pci Bridge ASPM
236  *or the system will show bluescreen.
237  */
238 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
239 {
240 	struct rtl_priv *rtlpriv = rtl_priv(hw);
241 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
242 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
243 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
244 	u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
245 	u16 aspmlevel;
246 	u8 u_device_aspmsetting;
247 
248 	if (!ppsc->support_aspm)
249 		return;
250 
251 	if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
252 		rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
253 			"PCI(Bridge) UNKNOWN\n");
254 		return;
255 	}
256 
257 	/*Get ASPM level (with/without Clock Req) */
258 	aspmlevel = rtlpci->const_devicepci_aspm_setting;
259 	u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
260 
261 	/*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
262 	/*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
263 
264 	u_device_aspmsetting |= aspmlevel;
265 
266 	_rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
267 
268 	if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
269 		_rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
270 					     RT_RF_OFF_LEVL_CLK_REQ) ?
271 					     PCI_EXP_LNKCTL_CLKREQ_EN : 0);
272 		RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
273 	}
274 	udelay(100);
275 }
276 
277 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
278 {
279 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
280 
281 	bool status = false;
282 	u8 offset_e0;
283 	unsigned int offset_e4;
284 
285 	pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
286 
287 	pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
288 
289 	if (offset_e0 == 0xA0) {
290 		pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
291 		if (offset_e4 & BIT(23))
292 			status = true;
293 	}
294 
295 	return status;
296 }
297 
298 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
299 				     struct rtl_priv **buddy_priv)
300 {
301 	struct rtl_priv *rtlpriv = rtl_priv(hw);
302 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
303 	struct rtl_priv *tpriv = NULL, *iter;
304 	struct rtl_pci_priv *tpcipriv = NULL;
305 
306 	if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
307 		list_for_each_entry(iter, &rtlpriv->glb_var->glb_priv_list,
308 				    list) {
309 			tpcipriv = (struct rtl_pci_priv *)iter->priv;
310 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
311 				"pcipriv->ndis_adapter.funcnumber %x\n",
312 				pcipriv->ndis_adapter.funcnumber);
313 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
314 				"tpcipriv->ndis_adapter.funcnumber %x\n",
315 				tpcipriv->ndis_adapter.funcnumber);
316 
317 			if (pcipriv->ndis_adapter.busnumber ==
318 			    tpcipriv->ndis_adapter.busnumber &&
319 			    pcipriv->ndis_adapter.devnumber ==
320 			    tpcipriv->ndis_adapter.devnumber &&
321 			    pcipriv->ndis_adapter.funcnumber !=
322 			    tpcipriv->ndis_adapter.funcnumber) {
323 				tpriv = iter;
324 				break;
325 			}
326 		}
327 	}
328 
329 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
330 		"find_buddy_priv %d\n", tpriv != NULL);
331 
332 	if (tpriv)
333 		*buddy_priv = tpriv;
334 
335 	return tpriv != NULL;
336 }
337 
338 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
339 					struct ieee80211_hw *hw)
340 {
341 	struct rtl_priv *rtlpriv = rtl_priv(hw);
342 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
343 
344 	u8 tmp;
345 	u16 linkctrl_reg;
346 
347 	/*Link Control Register */
348 	pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
349 	pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
350 
351 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
352 		pcipriv->ndis_adapter.linkctrl_reg);
353 
354 	pci_read_config_byte(pdev, 0x98, &tmp);
355 	tmp |= BIT(4);
356 	pci_write_config_byte(pdev, 0x98, tmp);
357 
358 	tmp = 0x17;
359 	pci_write_config_byte(pdev, 0x70f, tmp);
360 }
361 
362 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
363 {
364 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
365 
366 	_rtl_pci_update_default_setting(hw);
367 
368 	if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
369 		/*Always enable ASPM & Clock Req. */
370 		rtl_pci_enable_aspm(hw);
371 		RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
372 	}
373 }
374 
375 static void _rtl_pci_io_handler_init(struct device *dev,
376 				     struct ieee80211_hw *hw)
377 {
378 	struct rtl_priv *rtlpriv = rtl_priv(hw);
379 
380 	rtlpriv->io.dev = dev;
381 
382 	rtlpriv->io.write8_async = pci_write8_async;
383 	rtlpriv->io.write16_async = pci_write16_async;
384 	rtlpriv->io.write32_async = pci_write32_async;
385 
386 	rtlpriv->io.read8_sync = pci_read8_sync;
387 	rtlpriv->io.read16_sync = pci_read16_sync;
388 	rtlpriv->io.read32_sync = pci_read32_sync;
389 }
390 
391 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
392 				       struct sk_buff *skb,
393 				       struct rtl_tcb_desc *tcb_desc, u8 tid)
394 {
395 	struct rtl_priv *rtlpriv = rtl_priv(hw);
396 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
397 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
398 	struct sk_buff *next_skb;
399 	u8 additionlen = FCS_LEN;
400 
401 	/* here open is 4, wep/tkip is 8, aes is 12*/
402 	if (info->control.hw_key)
403 		additionlen += info->control.hw_key->icv_len;
404 
405 	/* The most skb num is 6 */
406 	tcb_desc->empkt_num = 0;
407 	spin_lock_bh(&rtlpriv->locks.waitq_lock);
408 	skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
409 		struct ieee80211_tx_info *next_info;
410 
411 		next_info = IEEE80211_SKB_CB(next_skb);
412 		if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
413 			tcb_desc->empkt_len[tcb_desc->empkt_num] =
414 				next_skb->len + additionlen;
415 			tcb_desc->empkt_num++;
416 		} else {
417 			break;
418 		}
419 
420 		if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
421 				      next_skb))
422 			break;
423 
424 		if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
425 			break;
426 	}
427 	spin_unlock_bh(&rtlpriv->locks.waitq_lock);
428 
429 	return true;
430 }
431 
432 /* just for early mode now */
433 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
434 {
435 	struct rtl_priv *rtlpriv = rtl_priv(hw);
436 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
437 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
438 	struct sk_buff *skb = NULL;
439 	struct ieee80211_tx_info *info = NULL;
440 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
441 	int tid;
442 
443 	if (!rtlpriv->rtlhal.earlymode_enable)
444 		return;
445 
446 	/* we just use em for BE/BK/VI/VO */
447 	for (tid = 7; tid >= 0; tid--) {
448 		u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
449 		struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
450 
451 		while (!mac->act_scanning &&
452 		       rtlpriv->psc.rfpwr_state == ERFON) {
453 			struct rtl_tcb_desc tcb_desc;
454 
455 			memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
456 
457 			spin_lock(&rtlpriv->locks.waitq_lock);
458 			if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
459 			    (ring->entries - skb_queue_len(&ring->queue) >
460 			     rtlhal->max_earlymode_num)) {
461 				skb = skb_dequeue(&mac->skb_waitq[tid]);
462 			} else {
463 				spin_unlock(&rtlpriv->locks.waitq_lock);
464 				break;
465 			}
466 			spin_unlock(&rtlpriv->locks.waitq_lock);
467 
468 			/* Some macaddr can't do early mode. like
469 			 * multicast/broadcast/no_qos data
470 			 */
471 			info = IEEE80211_SKB_CB(skb);
472 			if (info->flags & IEEE80211_TX_CTL_AMPDU)
473 				_rtl_update_earlymode_info(hw, skb,
474 							   &tcb_desc, tid);
475 
476 			rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
477 		}
478 	}
479 }
480 
481 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
482 {
483 	struct rtl_priv *rtlpriv = rtl_priv(hw);
484 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
485 
486 	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
487 
488 	while (skb_queue_len(&ring->queue)) {
489 		struct sk_buff *skb;
490 		struct ieee80211_tx_info *info;
491 		__le16 fc;
492 		u8 tid;
493 		u8 *entry;
494 
495 		if (rtlpriv->use_new_trx_flow)
496 			entry = (u8 *)(&ring->buffer_desc[ring->idx]);
497 		else
498 			entry = (u8 *)(&ring->desc[ring->idx]);
499 
500 		if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
501 			return;
502 		ring->idx = (ring->idx + 1) % ring->entries;
503 
504 		skb = __skb_dequeue(&ring->queue);
505 		dma_unmap_single(&rtlpci->pdev->dev,
506 				 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
507 						true, HW_DESC_TXBUFF_ADDR),
508 				 skb->len, DMA_TO_DEVICE);
509 
510 		/* remove early mode header */
511 		if (rtlpriv->rtlhal.earlymode_enable)
512 			skb_pull(skb, EM_HDR_LEN);
513 
514 		rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
515 			"new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
516 			ring->idx,
517 			skb_queue_len(&ring->queue),
518 			*(u16 *)(skb->data + 22));
519 
520 		if (prio == TXCMD_QUEUE) {
521 			dev_kfree_skb(skb);
522 			goto tx_status_ok;
523 		}
524 
525 		/* for sw LPS, just after NULL skb send out, we can
526 		 * sure AP knows we are sleeping, we should not let
527 		 * rf sleep
528 		 */
529 		fc = rtl_get_fc(skb);
530 		if (ieee80211_is_nullfunc(fc)) {
531 			if (ieee80211_has_pm(fc)) {
532 				rtlpriv->mac80211.offchan_delay = true;
533 				rtlpriv->psc.state_inap = true;
534 			} else {
535 				rtlpriv->psc.state_inap = false;
536 			}
537 		}
538 		if (ieee80211_is_action(fc)) {
539 			struct ieee80211_mgmt *action_frame =
540 				(struct ieee80211_mgmt *)skb->data;
541 			if (action_frame->u.action.u.ht_smps.action ==
542 			    WLAN_HT_ACTION_SMPS) {
543 				dev_kfree_skb(skb);
544 				goto tx_status_ok;
545 			}
546 		}
547 
548 		/* update tid tx pkt num */
549 		tid = rtl_get_tid(skb);
550 		if (tid <= 7)
551 			rtlpriv->link_info.tidtx_inperiod[tid]++;
552 
553 		info = IEEE80211_SKB_CB(skb);
554 
555 		if (likely(!ieee80211_is_nullfunc(fc))) {
556 			ieee80211_tx_info_clear_status(info);
557 			info->flags |= IEEE80211_TX_STAT_ACK;
558 			/*info->status.rates[0].count = 1; */
559 			ieee80211_tx_status_irqsafe(hw, skb);
560 		} else {
561 			rtl_tx_ackqueue(hw, skb);
562 		}
563 
564 		if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
565 			rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,
566 				"more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
567 				prio, ring->idx,
568 				skb_queue_len(&ring->queue));
569 
570 			ieee80211_wake_queue(hw, skb_get_queue_mapping(skb));
571 		}
572 tx_status_ok:
573 		skb = NULL;
574 	}
575 
576 	if (((rtlpriv->link_info.num_rx_inperiod +
577 	      rtlpriv->link_info.num_tx_inperiod) > 8) ||
578 	      rtlpriv->link_info.num_rx_inperiod > 2)
579 		rtl_lps_leave(hw, false);
580 }
581 
582 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
583 				    struct sk_buff *new_skb, u8 *entry,
584 				    int rxring_idx, int desc_idx)
585 {
586 	struct rtl_priv *rtlpriv = rtl_priv(hw);
587 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
588 	u32 bufferaddress;
589 	u8 tmp_one = 1;
590 	struct sk_buff *skb;
591 
592 	if (likely(new_skb)) {
593 		skb = new_skb;
594 		goto remap;
595 	}
596 	skb = dev_alloc_skb(rtlpci->rxbuffersize);
597 	if (!skb)
598 		return 0;
599 
600 remap:
601 	/* just set skb->cb to mapping addr for pci_unmap_single use */
602 	*((dma_addr_t *)skb->cb) =
603 		dma_map_single(&rtlpci->pdev->dev, skb_tail_pointer(skb),
604 			       rtlpci->rxbuffersize, DMA_FROM_DEVICE);
605 	bufferaddress = *((dma_addr_t *)skb->cb);
606 	if (dma_mapping_error(&rtlpci->pdev->dev, bufferaddress))
607 		return 0;
608 	rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
609 	if (rtlpriv->use_new_trx_flow) {
610 		/* skb->cb may be 64 bit address */
611 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
612 					    HW_DESC_RX_PREPARE,
613 					    (u8 *)(dma_addr_t *)skb->cb);
614 	} else {
615 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
616 					    HW_DESC_RXBUFF_ADDR,
617 					    (u8 *)&bufferaddress);
618 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
619 					    HW_DESC_RXPKT_LEN,
620 					    (u8 *)&rtlpci->rxbuffersize);
621 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
622 					    HW_DESC_RXOWN,
623 					    (u8 *)&tmp_one);
624 	}
625 	return 1;
626 }
627 
628 /* inorder to receive 8K AMSDU we have set skb to
629  * 9100bytes in init rx ring, but if this packet is
630  * not a AMSDU, this large packet will be sent to
631  * TCP/IP directly, this cause big packet ping fail
632  * like: "ping -s 65507", so here we will realloc skb
633  * based on the true size of packet, Mac80211
634  * Probably will do it better, but does not yet.
635  *
636  * Some platform will fail when alloc skb sometimes.
637  * in this condition, we will send the old skb to
638  * mac80211 directly, this will not cause any other
639  * issues, but only this packet will be lost by TCP/IP
640  */
641 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
642 				    struct sk_buff *skb,
643 				    struct ieee80211_rx_status rx_status)
644 {
645 	if (unlikely(!rtl_action_proc(hw, skb, false))) {
646 		dev_kfree_skb_any(skb);
647 	} else {
648 		struct sk_buff *uskb = NULL;
649 
650 		uskb = dev_alloc_skb(skb->len + 128);
651 		if (likely(uskb)) {
652 			memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
653 			       sizeof(rx_status));
654 			skb_put_data(uskb, skb->data, skb->len);
655 			dev_kfree_skb_any(skb);
656 			ieee80211_rx_irqsafe(hw, uskb);
657 		} else {
658 			ieee80211_rx_irqsafe(hw, skb);
659 		}
660 	}
661 }
662 
663 /*hsisr interrupt handler*/
664 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
665 {
666 	struct rtl_priv *rtlpriv = rtl_priv(hw);
667 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
668 
669 	rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
670 		       rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
671 		       rtlpci->sys_irq_mask);
672 }
673 
674 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
675 {
676 	struct rtl_priv *rtlpriv = rtl_priv(hw);
677 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
678 	int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
679 	struct ieee80211_rx_status rx_status = { 0 };
680 	unsigned int count = rtlpci->rxringcount;
681 	u8 own;
682 	u8 tmp_one;
683 	bool unicast = false;
684 	u8 hw_queue = 0;
685 	unsigned int rx_remained_cnt = 0;
686 	struct rtl_stats stats = {
687 		.signal = 0,
688 		.rate = 0,
689 	};
690 
691 	/*RX NORMAL PKT */
692 	while (count--) {
693 		struct ieee80211_hdr *hdr;
694 		__le16 fc;
695 		u16 len;
696 		/*rx buffer descriptor */
697 		struct rtl_rx_buffer_desc *buffer_desc = NULL;
698 		/*if use new trx flow, it means wifi info */
699 		struct rtl_rx_desc *pdesc = NULL;
700 		/*rx pkt */
701 		struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
702 				      rtlpci->rx_ring[rxring_idx].idx];
703 		struct sk_buff *new_skb;
704 
705 		if (rtlpriv->use_new_trx_flow) {
706 			if (rx_remained_cnt == 0)
707 				rx_remained_cnt =
708 				rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
709 								      hw_queue);
710 			if (rx_remained_cnt == 0)
711 				return;
712 			buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
713 				rtlpci->rx_ring[rxring_idx].idx];
714 			pdesc = (struct rtl_rx_desc *)skb->data;
715 		} else {	/* rx descriptor */
716 			pdesc = &rtlpci->rx_ring[rxring_idx].desc[
717 				rtlpci->rx_ring[rxring_idx].idx];
718 
719 			own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
720 							      false,
721 							      HW_DESC_OWN);
722 			if (own) /* wait data to be filled by hardware */
723 				return;
724 		}
725 
726 		/* Reaching this point means: data is filled already
727 		 * AAAAAAttention !!!
728 		 * We can NOT access 'skb' before 'pci_unmap_single'
729 		 */
730 		dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
731 				 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
732 
733 		/* get a new skb - if fail, old one will be reused */
734 		new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
735 		if (unlikely(!new_skb))
736 			goto no_new;
737 		memset(&rx_status, 0, sizeof(rx_status));
738 		rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
739 						 &rx_status, (u8 *)pdesc, skb);
740 
741 		if (rtlpriv->use_new_trx_flow)
742 			rtlpriv->cfg->ops->rx_check_dma_ok(hw,
743 							   (u8 *)buffer_desc,
744 							   hw_queue);
745 
746 		len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
747 						  HW_DESC_RXPKT_LEN);
748 
749 		if (skb->end - skb->tail > len) {
750 			skb_put(skb, len);
751 			if (rtlpriv->use_new_trx_flow)
752 				skb_reserve(skb, stats.rx_drvinfo_size +
753 					    stats.rx_bufshift + 24);
754 			else
755 				skb_reserve(skb, stats.rx_drvinfo_size +
756 					    stats.rx_bufshift);
757 		} else {
758 			rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
759 				"skb->end - skb->tail = %d, len is %d\n",
760 				skb->end - skb->tail, len);
761 			dev_kfree_skb_any(skb);
762 			goto new_trx_end;
763 		}
764 		/* handle command packet here */
765 		if (stats.packet_report_type == C2H_PACKET) {
766 			rtl_c2hcmd_enqueue(hw, skb);
767 			goto new_trx_end;
768 		}
769 
770 		/* NOTICE This can not be use for mac80211,
771 		 * this is done in mac80211 code,
772 		 * if done here sec DHCP will fail
773 		 * skb_trim(skb, skb->len - 4);
774 		 */
775 
776 		hdr = rtl_get_hdr(skb);
777 		fc = rtl_get_fc(skb);
778 
779 		if (!stats.crc && !stats.hwerror && (skb->len > FCS_LEN)) {
780 			memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
781 			       sizeof(rx_status));
782 
783 			if (is_broadcast_ether_addr(hdr->addr1)) {
784 				;/*TODO*/
785 			} else if (is_multicast_ether_addr(hdr->addr1)) {
786 				;/*TODO*/
787 			} else {
788 				unicast = true;
789 				rtlpriv->stats.rxbytesunicast += skb->len;
790 			}
791 			rtl_is_special_data(hw, skb, false, true);
792 
793 			if (ieee80211_is_data(fc)) {
794 				rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
795 				if (unicast)
796 					rtlpriv->link_info.num_rx_inperiod++;
797 			}
798 
799 			rtl_collect_scan_list(hw, skb);
800 
801 			/* static bcn for roaming */
802 			rtl_beacon_statistic(hw, skb);
803 			rtl_p2p_info(hw, (void *)skb->data, skb->len);
804 			/* for sw lps */
805 			rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
806 			rtl_recognize_peer(hw, (void *)skb->data, skb->len);
807 			if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP &&
808 			    rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G &&
809 			    (ieee80211_is_beacon(fc) ||
810 			     ieee80211_is_probe_resp(fc))) {
811 				dev_kfree_skb_any(skb);
812 			} else {
813 				_rtl_pci_rx_to_mac80211(hw, skb, rx_status);
814 			}
815 		} else {
816 			/* drop packets with errors or those too short */
817 			dev_kfree_skb_any(skb);
818 		}
819 new_trx_end:
820 		if (rtlpriv->use_new_trx_flow) {
821 			rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
822 			rtlpci->rx_ring[hw_queue].next_rx_rp %=
823 					RTL_PCI_MAX_RX_COUNT;
824 
825 			rx_remained_cnt--;
826 			rtl_write_word(rtlpriv, 0x3B4,
827 				       rtlpci->rx_ring[hw_queue].next_rx_rp);
828 		}
829 		if (((rtlpriv->link_info.num_rx_inperiod +
830 		      rtlpriv->link_info.num_tx_inperiod) > 8) ||
831 		      rtlpriv->link_info.num_rx_inperiod > 2)
832 			rtl_lps_leave(hw, false);
833 		skb = new_skb;
834 no_new:
835 		if (rtlpriv->use_new_trx_flow) {
836 			_rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
837 						 rxring_idx,
838 						 rtlpci->rx_ring[rxring_idx].idx);
839 		} else {
840 			_rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
841 						 rxring_idx,
842 						 rtlpci->rx_ring[rxring_idx].idx);
843 			if (rtlpci->rx_ring[rxring_idx].idx ==
844 			    rtlpci->rxringcount - 1)
845 				rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
846 							    false,
847 							    HW_DESC_RXERO,
848 							    (u8 *)&tmp_one);
849 		}
850 		rtlpci->rx_ring[rxring_idx].idx =
851 				(rtlpci->rx_ring[rxring_idx].idx + 1) %
852 				rtlpci->rxringcount;
853 	}
854 }
855 
856 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
857 {
858 	struct ieee80211_hw *hw = dev_id;
859 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
860 	struct rtl_priv *rtlpriv = rtl_priv(hw);
861 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
862 	unsigned long flags;
863 	struct rtl_int intvec = {0};
864 
865 	irqreturn_t ret = IRQ_HANDLED;
866 
867 	if (rtlpci->irq_enabled == 0)
868 		return ret;
869 
870 	spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
871 	rtlpriv->cfg->ops->disable_interrupt(hw);
872 
873 	/*read ISR: 4/8bytes */
874 	rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec);
875 
876 	/*Shared IRQ or HW disappeared */
877 	if (!intvec.inta || intvec.inta == 0xffff)
878 		goto done;
879 
880 	/*<1> beacon related */
881 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK])
882 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
883 			"beacon ok interrupt!\n");
884 
885 	if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER]))
886 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
887 			"beacon err interrupt!\n");
888 
889 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
890 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
891 
892 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
893 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
894 			"prepare beacon for interrupt!\n");
895 		tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
896 	}
897 
898 	/*<2> Tx related */
899 	if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
900 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
901 
902 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
903 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
904 			"Manage ok interrupt!\n");
905 		_rtl_pci_tx_isr(hw, MGNT_QUEUE);
906 	}
907 
908 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
909 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
910 			"HIGH_QUEUE ok interrupt!\n");
911 		_rtl_pci_tx_isr(hw, HIGH_QUEUE);
912 	}
913 
914 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
915 		rtlpriv->link_info.num_tx_inperiod++;
916 
917 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
918 			"BK Tx OK interrupt!\n");
919 		_rtl_pci_tx_isr(hw, BK_QUEUE);
920 	}
921 
922 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
923 		rtlpriv->link_info.num_tx_inperiod++;
924 
925 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
926 			"BE TX OK interrupt!\n");
927 		_rtl_pci_tx_isr(hw, BE_QUEUE);
928 	}
929 
930 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
931 		rtlpriv->link_info.num_tx_inperiod++;
932 
933 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
934 			"VI TX OK interrupt!\n");
935 		_rtl_pci_tx_isr(hw, VI_QUEUE);
936 	}
937 
938 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
939 		rtlpriv->link_info.num_tx_inperiod++;
940 
941 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
942 			"Vo TX OK interrupt!\n");
943 		_rtl_pci_tx_isr(hw, VO_QUEUE);
944 	}
945 
946 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
947 		if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
948 			rtlpriv->link_info.num_tx_inperiod++;
949 
950 			rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
951 				"H2C TX OK interrupt!\n");
952 			_rtl_pci_tx_isr(hw, H2C_QUEUE);
953 		}
954 	}
955 
956 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
957 		if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
958 			rtlpriv->link_info.num_tx_inperiod++;
959 
960 			rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
961 				"CMD TX OK interrupt!\n");
962 			_rtl_pci_tx_isr(hw, TXCMD_QUEUE);
963 		}
964 	}
965 
966 	/*<3> Rx related */
967 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
968 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
969 		_rtl_pci_rx_interrupt(hw);
970 	}
971 
972 	if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
973 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
974 			"rx descriptor unavailable!\n");
975 		_rtl_pci_rx_interrupt(hw);
976 	}
977 
978 	if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
979 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
980 		_rtl_pci_rx_interrupt(hw);
981 	}
982 
983 	/*<4> fw related*/
984 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
985 		if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
986 			rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
987 				"firmware interrupt!\n");
988 			queue_delayed_work(rtlpriv->works.rtl_wq,
989 					   &rtlpriv->works.fwevt_wq, 0);
990 		}
991 	}
992 
993 	/*<5> hsisr related*/
994 	/* Only 8188EE & 8723BE Supported.
995 	 * If Other ICs Come in, System will corrupt,
996 	 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
997 	 * are not initialized
998 	 */
999 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1000 	    rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1001 		if (unlikely(intvec.inta &
1002 		    rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1003 			rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
1004 				"hsisr interrupt!\n");
1005 			_rtl_pci_hs_interrupt(hw);
1006 		}
1007 	}
1008 
1009 	if (rtlpriv->rtlhal.earlymode_enable)
1010 		tasklet_schedule(&rtlpriv->works.irq_tasklet);
1011 
1012 done:
1013 	rtlpriv->cfg->ops->enable_interrupt(hw);
1014 	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1015 	return ret;
1016 }
1017 
1018 static void _rtl_pci_irq_tasklet(struct tasklet_struct *t)
1019 {
1020 	struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, works.irq_tasklet);
1021 	struct ieee80211_hw *hw = rtlpriv->hw;
1022 	_rtl_pci_tx_chk_waitq(hw);
1023 }
1024 
1025 static void _rtl_pci_prepare_bcn_tasklet(struct tasklet_struct *t)
1026 {
1027 	struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t,
1028 						works.irq_prepare_bcn_tasklet);
1029 	struct ieee80211_hw *hw = rtlpriv->hw;
1030 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1031 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1032 	struct rtl8192_tx_ring *ring = NULL;
1033 	struct ieee80211_hdr *hdr = NULL;
1034 	struct ieee80211_tx_info *info = NULL;
1035 	struct sk_buff *pskb = NULL;
1036 	struct rtl_tx_desc *pdesc = NULL;
1037 	struct rtl_tcb_desc tcb_desc;
1038 	/*This is for new trx flow*/
1039 	struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1040 	u8 temp_one = 1;
1041 	u8 *entry;
1042 
1043 	memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1044 	ring = &rtlpci->tx_ring[BEACON_QUEUE];
1045 	pskb = __skb_dequeue(&ring->queue);
1046 	if (rtlpriv->use_new_trx_flow)
1047 		entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1048 	else
1049 		entry = (u8 *)(&ring->desc[ring->idx]);
1050 	if (pskb) {
1051 		dma_unmap_single(&rtlpci->pdev->dev,
1052 				 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1053 						true, HW_DESC_TXBUFF_ADDR),
1054 				 pskb->len, DMA_TO_DEVICE);
1055 		kfree_skb(pskb);
1056 	}
1057 
1058 	/*NB: the beacon data buffer must be 32-bit aligned. */
1059 	pskb = ieee80211_beacon_get(hw, mac->vif, 0);
1060 	if (!pskb)
1061 		return;
1062 	hdr = rtl_get_hdr(pskb);
1063 	info = IEEE80211_SKB_CB(pskb);
1064 	pdesc = &ring->desc[0];
1065 	if (rtlpriv->use_new_trx_flow)
1066 		pbuffer_desc = &ring->buffer_desc[0];
1067 
1068 	rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1069 					(u8 *)pbuffer_desc, info, NULL, pskb,
1070 					BEACON_QUEUE, &tcb_desc);
1071 
1072 	__skb_queue_tail(&ring->queue, pskb);
1073 
1074 	if (rtlpriv->use_new_trx_flow) {
1075 		temp_one = 4;
1076 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1077 					    HW_DESC_OWN, (u8 *)&temp_one);
1078 	} else {
1079 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1080 					    &temp_one);
1081 	}
1082 }
1083 
1084 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1085 {
1086 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1087 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1088 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1089 	u8 i;
1090 	u16 desc_num;
1091 
1092 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1093 		desc_num = TX_DESC_NUM_92E;
1094 	else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE)
1095 		desc_num = TX_DESC_NUM_8822B;
1096 	else
1097 		desc_num = RT_TXDESC_NUM;
1098 
1099 	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1100 		rtlpci->txringcount[i] = desc_num;
1101 
1102 	/*we just alloc 2 desc for beacon queue,
1103 	 *because we just need first desc in hw beacon.
1104 	 */
1105 	rtlpci->txringcount[BEACON_QUEUE] = 2;
1106 
1107 	/*BE queue need more descriptor for performance
1108 	 *consideration or, No more tx desc will happen,
1109 	 *and may cause mac80211 mem leakage.
1110 	 */
1111 	if (!rtl_priv(hw)->use_new_trx_flow)
1112 		rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1113 
1114 	rtlpci->rxbuffersize = 9100;	/*2048/1024; */
1115 	rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT;	/*64; */
1116 }
1117 
1118 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1119 				 struct pci_dev *pdev)
1120 {
1121 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1122 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1123 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1124 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1125 
1126 	rtlpci->up_first_time = true;
1127 	rtlpci->being_init_adapter = false;
1128 
1129 	rtlhal->hw = hw;
1130 	rtlpci->pdev = pdev;
1131 
1132 	/*Tx/Rx related var */
1133 	_rtl_pci_init_trx_var(hw);
1134 
1135 	/*IBSS*/
1136 	mac->beacon_interval = 100;
1137 
1138 	/*AMPDU*/
1139 	mac->min_space_cfg = 0;
1140 	mac->max_mss_density = 0;
1141 	/*set sane AMPDU defaults */
1142 	mac->current_ampdu_density = 7;
1143 	mac->current_ampdu_factor = 3;
1144 
1145 	/*Retry Limit*/
1146 	mac->retry_short = 7;
1147 	mac->retry_long = 7;
1148 
1149 	/*QOS*/
1150 	rtlpci->acm_method = EACMWAY2_SW;
1151 
1152 	/*task */
1153 	tasklet_setup(&rtlpriv->works.irq_tasklet, _rtl_pci_irq_tasklet);
1154 	tasklet_setup(&rtlpriv->works.irq_prepare_bcn_tasklet,
1155 		     _rtl_pci_prepare_bcn_tasklet);
1156 	INIT_WORK(&rtlpriv->works.lps_change_work,
1157 		  rtl_lps_change_work_callback);
1158 }
1159 
1160 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1161 				 unsigned int prio, unsigned int entries)
1162 {
1163 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1164 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1165 	struct rtl_tx_buffer_desc *buffer_desc;
1166 	struct rtl_tx_desc *desc;
1167 	dma_addr_t buffer_desc_dma, desc_dma;
1168 	u32 nextdescaddress;
1169 	int i;
1170 
1171 	/* alloc tx buffer desc for new trx flow*/
1172 	if (rtlpriv->use_new_trx_flow) {
1173 		buffer_desc =
1174 		   dma_alloc_coherent(&rtlpci->pdev->dev,
1175 				      sizeof(*buffer_desc) * entries,
1176 				      &buffer_desc_dma, GFP_KERNEL);
1177 
1178 		if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1179 			pr_err("Cannot allocate TX ring (prio = %d)\n",
1180 			       prio);
1181 			return -ENOMEM;
1182 		}
1183 
1184 		rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1185 		rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1186 
1187 		rtlpci->tx_ring[prio].cur_tx_rp = 0;
1188 		rtlpci->tx_ring[prio].cur_tx_wp = 0;
1189 	}
1190 
1191 	/* alloc dma for this ring */
1192 	desc = dma_alloc_coherent(&rtlpci->pdev->dev, sizeof(*desc) * entries,
1193 				  &desc_dma, GFP_KERNEL);
1194 
1195 	if (!desc || (unsigned long)desc & 0xFF) {
1196 		pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
1197 		return -ENOMEM;
1198 	}
1199 
1200 	rtlpci->tx_ring[prio].desc = desc;
1201 	rtlpci->tx_ring[prio].dma = desc_dma;
1202 
1203 	rtlpci->tx_ring[prio].idx = 0;
1204 	rtlpci->tx_ring[prio].entries = entries;
1205 	skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1206 
1207 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1208 		prio, desc);
1209 
1210 	/* init every desc in this ring */
1211 	if (!rtlpriv->use_new_trx_flow) {
1212 		for (i = 0; i < entries; i++) {
1213 			nextdescaddress = (u32)desc_dma +
1214 					  ((i +	1) % entries) *
1215 					  sizeof(*desc);
1216 
1217 			rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1218 						    true,
1219 						    HW_DESC_TX_NEXTDESC_ADDR,
1220 						    (u8 *)&nextdescaddress);
1221 		}
1222 	}
1223 	return 0;
1224 }
1225 
1226 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1227 {
1228 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1229 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1230 	int i;
1231 
1232 	if (rtlpriv->use_new_trx_flow) {
1233 		struct rtl_rx_buffer_desc *entry = NULL;
1234 		/* alloc dma for this ring */
1235 		rtlpci->rx_ring[rxring_idx].buffer_desc =
1236 		    dma_alloc_coherent(&rtlpci->pdev->dev,
1237 				       sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1238 				       rtlpci->rxringcount,
1239 				       &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
1240 		if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1241 		    (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1242 			pr_err("Cannot allocate RX ring\n");
1243 			return -ENOMEM;
1244 		}
1245 
1246 		/* init every desc in this ring */
1247 		rtlpci->rx_ring[rxring_idx].idx = 0;
1248 		for (i = 0; i < rtlpci->rxringcount; i++) {
1249 			entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1250 			if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1251 						      rxring_idx, i))
1252 				return -ENOMEM;
1253 		}
1254 	} else {
1255 		struct rtl_rx_desc *entry = NULL;
1256 		u8 tmp_one = 1;
1257 		/* alloc dma for this ring */
1258 		rtlpci->rx_ring[rxring_idx].desc =
1259 		    dma_alloc_coherent(&rtlpci->pdev->dev,
1260 				       sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1261 				       rtlpci->rxringcount,
1262 				       &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
1263 		if (!rtlpci->rx_ring[rxring_idx].desc ||
1264 		    (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1265 			pr_err("Cannot allocate RX ring\n");
1266 			return -ENOMEM;
1267 		}
1268 
1269 		/* init every desc in this ring */
1270 		rtlpci->rx_ring[rxring_idx].idx = 0;
1271 
1272 		for (i = 0; i < rtlpci->rxringcount; i++) {
1273 			entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1274 			if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1275 						      rxring_idx, i))
1276 				return -ENOMEM;
1277 		}
1278 
1279 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1280 					    HW_DESC_RXERO, &tmp_one);
1281 	}
1282 	return 0;
1283 }
1284 
1285 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1286 				  unsigned int prio)
1287 {
1288 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1289 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1290 	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1291 
1292 	/* free every desc in this ring */
1293 	while (skb_queue_len(&ring->queue)) {
1294 		u8 *entry;
1295 		struct sk_buff *skb = __skb_dequeue(&ring->queue);
1296 
1297 		if (rtlpriv->use_new_trx_flow)
1298 			entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1299 		else
1300 			entry = (u8 *)(&ring->desc[ring->idx]);
1301 
1302 		dma_unmap_single(&rtlpci->pdev->dev,
1303 				 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1304 						true, HW_DESC_TXBUFF_ADDR),
1305 				 skb->len, DMA_TO_DEVICE);
1306 		kfree_skb(skb);
1307 		ring->idx = (ring->idx + 1) % ring->entries;
1308 	}
1309 
1310 	/* free dma of this ring */
1311 	dma_free_coherent(&rtlpci->pdev->dev,
1312 			  sizeof(*ring->desc) * ring->entries, ring->desc,
1313 			  ring->dma);
1314 	ring->desc = NULL;
1315 	if (rtlpriv->use_new_trx_flow) {
1316 		dma_free_coherent(&rtlpci->pdev->dev,
1317 				  sizeof(*ring->buffer_desc) * ring->entries,
1318 				  ring->buffer_desc, ring->buffer_desc_dma);
1319 		ring->buffer_desc = NULL;
1320 	}
1321 }
1322 
1323 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1324 {
1325 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1326 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1327 	int i;
1328 
1329 	/* free every desc in this ring */
1330 	for (i = 0; i < rtlpci->rxringcount; i++) {
1331 		struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1332 
1333 		if (!skb)
1334 			continue;
1335 		dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
1336 				 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
1337 		kfree_skb(skb);
1338 	}
1339 
1340 	/* free dma of this ring */
1341 	if (rtlpriv->use_new_trx_flow) {
1342 		dma_free_coherent(&rtlpci->pdev->dev,
1343 				  sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1344 				  rtlpci->rxringcount,
1345 				  rtlpci->rx_ring[rxring_idx].buffer_desc,
1346 				  rtlpci->rx_ring[rxring_idx].dma);
1347 		rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1348 	} else {
1349 		dma_free_coherent(&rtlpci->pdev->dev,
1350 				  sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1351 				  rtlpci->rxringcount,
1352 				  rtlpci->rx_ring[rxring_idx].desc,
1353 				  rtlpci->rx_ring[rxring_idx].dma);
1354 		rtlpci->rx_ring[rxring_idx].desc = NULL;
1355 	}
1356 }
1357 
1358 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1359 {
1360 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1361 	int ret;
1362 	int i, rxring_idx;
1363 
1364 	/* rxring_idx 0:RX_MPDU_QUEUE
1365 	 * rxring_idx 1:RX_CMD_QUEUE
1366 	 */
1367 	for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1368 		ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1369 		if (ret)
1370 			return ret;
1371 	}
1372 
1373 	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1374 		ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
1375 		if (ret)
1376 			goto err_free_rings;
1377 	}
1378 
1379 	return 0;
1380 
1381 err_free_rings:
1382 	for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1383 		_rtl_pci_free_rx_ring(hw, rxring_idx);
1384 
1385 	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1386 		if (rtlpci->tx_ring[i].desc ||
1387 		    rtlpci->tx_ring[i].buffer_desc)
1388 			_rtl_pci_free_tx_ring(hw, i);
1389 
1390 	return 1;
1391 }
1392 
1393 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1394 {
1395 	u32 i, rxring_idx;
1396 
1397 	/*free rx rings */
1398 	for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1399 		_rtl_pci_free_rx_ring(hw, rxring_idx);
1400 
1401 	/*free tx rings */
1402 	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1403 		_rtl_pci_free_tx_ring(hw, i);
1404 
1405 	return 0;
1406 }
1407 
1408 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1409 {
1410 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1411 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1412 	int i, rxring_idx;
1413 	unsigned long flags;
1414 	u8 tmp_one = 1;
1415 	u32 bufferaddress;
1416 	/* rxring_idx 0:RX_MPDU_QUEUE */
1417 	/* rxring_idx 1:RX_CMD_QUEUE */
1418 	for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1419 		/* force the rx_ring[RX_MPDU_QUEUE/
1420 		 * RX_CMD_QUEUE].idx to the first one
1421 		 *new trx flow, do nothing
1422 		 */
1423 		if (!rtlpriv->use_new_trx_flow &&
1424 		    rtlpci->rx_ring[rxring_idx].desc) {
1425 			struct rtl_rx_desc *entry = NULL;
1426 
1427 			rtlpci->rx_ring[rxring_idx].idx = 0;
1428 			for (i = 0; i < rtlpci->rxringcount; i++) {
1429 				entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1430 				bufferaddress =
1431 				  rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1432 				  false, HW_DESC_RXBUFF_ADDR);
1433 				memset((u8 *)entry, 0,
1434 				       sizeof(*rtlpci->rx_ring
1435 				       [rxring_idx].desc));/*clear one entry*/
1436 				if (rtlpriv->use_new_trx_flow) {
1437 					rtlpriv->cfg->ops->set_desc(hw,
1438 					    (u8 *)entry, false,
1439 					    HW_DESC_RX_PREPARE,
1440 					    (u8 *)&bufferaddress);
1441 				} else {
1442 					rtlpriv->cfg->ops->set_desc(hw,
1443 					    (u8 *)entry, false,
1444 					    HW_DESC_RXBUFF_ADDR,
1445 					    (u8 *)&bufferaddress);
1446 					rtlpriv->cfg->ops->set_desc(hw,
1447 					    (u8 *)entry, false,
1448 					    HW_DESC_RXPKT_LEN,
1449 					    (u8 *)&rtlpci->rxbuffersize);
1450 					rtlpriv->cfg->ops->set_desc(hw,
1451 					    (u8 *)entry, false,
1452 					    HW_DESC_RXOWN,
1453 					    (u8 *)&tmp_one);
1454 				}
1455 			}
1456 			rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1457 					    HW_DESC_RXERO, (u8 *)&tmp_one);
1458 		}
1459 		rtlpci->rx_ring[rxring_idx].idx = 0;
1460 	}
1461 
1462 	/*after reset, release previous pending packet,
1463 	 *and force the  tx idx to the first one
1464 	 */
1465 	spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1466 	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1467 		if (rtlpci->tx_ring[i].desc ||
1468 		    rtlpci->tx_ring[i].buffer_desc) {
1469 			struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1470 
1471 			while (skb_queue_len(&ring->queue)) {
1472 				u8 *entry;
1473 				struct sk_buff *skb =
1474 					__skb_dequeue(&ring->queue);
1475 				if (rtlpriv->use_new_trx_flow)
1476 					entry = (u8 *)(&ring->buffer_desc
1477 								[ring->idx]);
1478 				else
1479 					entry = (u8 *)(&ring->desc[ring->idx]);
1480 
1481 				dma_unmap_single(&rtlpci->pdev->dev,
1482 						 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1483 								true, HW_DESC_TXBUFF_ADDR),
1484 						 skb->len, DMA_TO_DEVICE);
1485 				dev_kfree_skb_irq(skb);
1486 				ring->idx = (ring->idx + 1) % ring->entries;
1487 			}
1488 
1489 			if (rtlpriv->use_new_trx_flow) {
1490 				rtlpci->tx_ring[i].cur_tx_rp = 0;
1491 				rtlpci->tx_ring[i].cur_tx_wp = 0;
1492 			}
1493 
1494 			ring->idx = 0;
1495 			ring->entries = rtlpci->txringcount[i];
1496 		}
1497 	}
1498 	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1499 
1500 	return 0;
1501 }
1502 
1503 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1504 					struct ieee80211_sta *sta,
1505 					struct sk_buff *skb)
1506 {
1507 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1508 	struct rtl_sta_info *sta_entry = NULL;
1509 	u8 tid = rtl_get_tid(skb);
1510 	__le16 fc = rtl_get_fc(skb);
1511 
1512 	if (!sta)
1513 		return false;
1514 	sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1515 
1516 	if (!rtlpriv->rtlhal.earlymode_enable)
1517 		return false;
1518 	if (ieee80211_is_nullfunc(fc))
1519 		return false;
1520 	if (ieee80211_is_qos_nullfunc(fc))
1521 		return false;
1522 	if (ieee80211_is_pspoll(fc))
1523 		return false;
1524 	if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1525 		return false;
1526 	if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1527 		return false;
1528 	if (tid > 7)
1529 		return false;
1530 
1531 	/* maybe every tid should be checked */
1532 	if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1533 		return false;
1534 
1535 	spin_lock_bh(&rtlpriv->locks.waitq_lock);
1536 	skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1537 	spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1538 
1539 	return true;
1540 }
1541 
1542 static int rtl_pci_tx(struct ieee80211_hw *hw,
1543 		      struct ieee80211_sta *sta,
1544 		      struct sk_buff *skb,
1545 		      struct rtl_tcb_desc *ptcb_desc)
1546 {
1547 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1548 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1549 	struct rtl8192_tx_ring *ring;
1550 	struct rtl_tx_desc *pdesc;
1551 	struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1552 	u16 idx;
1553 	u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1554 	unsigned long flags;
1555 	struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1556 	__le16 fc = rtl_get_fc(skb);
1557 	u8 *pda_addr = hdr->addr1;
1558 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1559 	u8 own;
1560 	u8 temp_one = 1;
1561 
1562 	if (ieee80211_is_mgmt(fc))
1563 		rtl_tx_mgmt_proc(hw, skb);
1564 
1565 	if (rtlpriv->psc.sw_ps_enabled) {
1566 		if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1567 		    !ieee80211_has_pm(fc))
1568 			hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1569 	}
1570 
1571 	rtl_action_proc(hw, skb, true);
1572 
1573 	if (is_multicast_ether_addr(pda_addr))
1574 		rtlpriv->stats.txbytesmulticast += skb->len;
1575 	else if (is_broadcast_ether_addr(pda_addr))
1576 		rtlpriv->stats.txbytesbroadcast += skb->len;
1577 	else
1578 		rtlpriv->stats.txbytesunicast += skb->len;
1579 
1580 	spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1581 	ring = &rtlpci->tx_ring[hw_queue];
1582 	if (hw_queue != BEACON_QUEUE) {
1583 		if (rtlpriv->use_new_trx_flow)
1584 			idx = ring->cur_tx_wp;
1585 		else
1586 			idx = (ring->idx + skb_queue_len(&ring->queue)) %
1587 			      ring->entries;
1588 	} else {
1589 		idx = 0;
1590 	}
1591 
1592 	pdesc = &ring->desc[idx];
1593 	if (rtlpriv->use_new_trx_flow) {
1594 		ptx_bd_desc = &ring->buffer_desc[idx];
1595 	} else {
1596 		own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
1597 				true, HW_DESC_OWN);
1598 
1599 		if (own == 1 && hw_queue != BEACON_QUEUE) {
1600 			rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1601 				"No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1602 				hw_queue, ring->idx, idx,
1603 				skb_queue_len(&ring->queue));
1604 
1605 			spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1606 					       flags);
1607 			return skb->len;
1608 		}
1609 	}
1610 
1611 	if (rtlpriv->cfg->ops->get_available_desc &&
1612 	    rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1613 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1614 			"get_available_desc fail\n");
1615 		spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1616 		return skb->len;
1617 	}
1618 
1619 	if (ieee80211_is_data(fc))
1620 		rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1621 
1622 	rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1623 			(u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1624 
1625 	__skb_queue_tail(&ring->queue, skb);
1626 
1627 	if (rtlpriv->use_new_trx_flow) {
1628 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1629 					    HW_DESC_OWN, &hw_queue);
1630 	} else {
1631 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1632 					    HW_DESC_OWN, &temp_one);
1633 	}
1634 
1635 	if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1636 	    hw_queue != BEACON_QUEUE) {
1637 		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1638 			"less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1639 			 hw_queue, ring->idx, idx,
1640 			 skb_queue_len(&ring->queue));
1641 
1642 		ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1643 	}
1644 
1645 	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1646 
1647 	rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1648 
1649 	return 0;
1650 }
1651 
1652 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1653 {
1654 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1655 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1656 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1657 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1658 	u16 i = 0;
1659 	int queue_id;
1660 	struct rtl8192_tx_ring *ring;
1661 
1662 	if (mac->skip_scan)
1663 		return;
1664 
1665 	for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1666 		u32 queue_len;
1667 
1668 		if (((queues >> queue_id) & 0x1) == 0) {
1669 			queue_id--;
1670 			continue;
1671 		}
1672 		ring = &pcipriv->dev.tx_ring[queue_id];
1673 		queue_len = skb_queue_len(&ring->queue);
1674 		if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1675 		    queue_id == TXCMD_QUEUE) {
1676 			queue_id--;
1677 			continue;
1678 		} else {
1679 			msleep(20);
1680 			i++;
1681 		}
1682 
1683 		/* we just wait 1s for all queues */
1684 		if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1685 		    is_hal_stop(rtlhal) || i >= 200)
1686 			return;
1687 	}
1688 }
1689 
1690 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1691 {
1692 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1693 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1694 
1695 	_rtl_pci_deinit_trx_ring(hw);
1696 
1697 	synchronize_irq(rtlpci->pdev->irq);
1698 	tasklet_kill(&rtlpriv->works.irq_tasklet);
1699 	cancel_work_sync(&rtlpriv->works.lps_change_work);
1700 
1701 	destroy_workqueue(rtlpriv->works.rtl_wq);
1702 }
1703 
1704 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1705 {
1706 	int err;
1707 
1708 	_rtl_pci_init_struct(hw, pdev);
1709 
1710 	err = _rtl_pci_init_trx_ring(hw);
1711 	if (err) {
1712 		pr_err("tx ring initialization failed\n");
1713 		return err;
1714 	}
1715 
1716 	return 0;
1717 }
1718 
1719 static int rtl_pci_start(struct ieee80211_hw *hw)
1720 {
1721 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1722 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1723 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1724 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1725 	struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
1726 	struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
1727 
1728 	int err;
1729 
1730 	rtl_pci_reset_trx_ring(hw);
1731 
1732 	rtlpci->driver_is_goingto_unload = false;
1733 	if (rtlpriv->cfg->ops->get_btc_status &&
1734 	    rtlpriv->cfg->ops->get_btc_status()) {
1735 		rtlpriv->btcoexist.btc_info.ap_num = 36;
1736 		btc_ops->btc_init_variables(rtlpriv);
1737 		btc_ops->btc_init_hal_vars(rtlpriv);
1738 	} else if (btc_ops) {
1739 		btc_ops->btc_init_variables_wifi_only(rtlpriv);
1740 	}
1741 
1742 	err = rtlpriv->cfg->ops->hw_init(hw);
1743 	if (err) {
1744 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1745 			"Failed to config hardware!\n");
1746 		kfree(rtlpriv->btcoexist.btc_context);
1747 		kfree(rtlpriv->btcoexist.wifi_only_context);
1748 		return err;
1749 	}
1750 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1751 			&rtlmac->retry_long);
1752 
1753 	rtlpriv->cfg->ops->enable_interrupt(hw);
1754 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1755 
1756 	rtl_init_rx_config(hw);
1757 
1758 	/*should be after adapter start and interrupt enable. */
1759 	set_hal_start(rtlhal);
1760 
1761 	RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1762 
1763 	rtlpci->up_first_time = false;
1764 
1765 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
1766 	return 0;
1767 }
1768 
1769 static void rtl_pci_stop(struct ieee80211_hw *hw)
1770 {
1771 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1772 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1773 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1774 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1775 	unsigned long flags;
1776 	u8 rf_timeout = 0;
1777 
1778 	if (rtlpriv->cfg->ops->get_btc_status())
1779 		rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv);
1780 
1781 	if (rtlpriv->btcoexist.btc_ops)
1782 		rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv);
1783 
1784 	/*should be before disable interrupt&adapter
1785 	 *and will do it immediately.
1786 	 */
1787 	set_hal_stop(rtlhal);
1788 
1789 	rtlpci->driver_is_goingto_unload = true;
1790 	rtlpriv->cfg->ops->disable_interrupt(hw);
1791 	cancel_work_sync(&rtlpriv->works.lps_change_work);
1792 
1793 	spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1794 	while (ppsc->rfchange_inprogress) {
1795 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1796 		if (rf_timeout > 100) {
1797 			spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1798 			break;
1799 		}
1800 		mdelay(1);
1801 		rf_timeout++;
1802 		spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1803 	}
1804 	ppsc->rfchange_inprogress = true;
1805 	spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1806 
1807 	rtlpriv->cfg->ops->hw_disable(hw);
1808 	/* some things are not needed if firmware not available */
1809 	if (!rtlpriv->max_fw_size)
1810 		return;
1811 	rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1812 
1813 	spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1814 	ppsc->rfchange_inprogress = false;
1815 	spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1816 
1817 	rtl_pci_enable_aspm(hw);
1818 }
1819 
1820 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1821 				  struct ieee80211_hw *hw)
1822 {
1823 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1824 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1825 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1826 	struct pci_dev *bridge_pdev = pdev->bus->self;
1827 	u16 venderid;
1828 	u16 deviceid;
1829 	u8 revisionid;
1830 	u16 irqline;
1831 	u8 tmp;
1832 
1833 	pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1834 	venderid = pdev->vendor;
1835 	deviceid = pdev->device;
1836 	pci_read_config_byte(pdev, 0x8, &revisionid);
1837 	pci_read_config_word(pdev, 0x3C, &irqline);
1838 
1839 	/* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1840 	 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1841 	 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1842 	 * the correct driver is r8192e_pci, thus this routine should
1843 	 * return false.
1844 	 */
1845 	if (deviceid == RTL_PCI_8192SE_DID &&
1846 	    revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1847 		return false;
1848 
1849 	if (deviceid == RTL_PCI_8192_DID ||
1850 	    deviceid == RTL_PCI_0044_DID ||
1851 	    deviceid == RTL_PCI_0047_DID ||
1852 	    deviceid == RTL_PCI_8192SE_DID ||
1853 	    deviceid == RTL_PCI_8174_DID ||
1854 	    deviceid == RTL_PCI_8173_DID ||
1855 	    deviceid == RTL_PCI_8172_DID ||
1856 	    deviceid == RTL_PCI_8171_DID) {
1857 		switch (revisionid) {
1858 		case RTL_PCI_REVISION_ID_8192PCIE:
1859 			rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1860 				"8192 PCI-E is found - vid/did=%x/%x\n",
1861 				venderid, deviceid);
1862 			rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1863 			return false;
1864 		case RTL_PCI_REVISION_ID_8192SE:
1865 			rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1866 				"8192SE is found - vid/did=%x/%x\n",
1867 				venderid, deviceid);
1868 			rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1869 			break;
1870 		default:
1871 			rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1872 				"Err: Unknown device - vid/did=%x/%x\n",
1873 				venderid, deviceid);
1874 			rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1875 			break;
1876 		}
1877 	} else if (deviceid == RTL_PCI_8723AE_DID) {
1878 		rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1879 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1880 			"8723AE PCI-E is found - vid/did=%x/%x\n",
1881 			venderid, deviceid);
1882 	} else if (deviceid == RTL_PCI_8192CET_DID ||
1883 		   deviceid == RTL_PCI_8192CE_DID ||
1884 		   deviceid == RTL_PCI_8191CE_DID ||
1885 		   deviceid == RTL_PCI_8188CE_DID) {
1886 		rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1887 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1888 			"8192C PCI-E is found - vid/did=%x/%x\n",
1889 			venderid, deviceid);
1890 	} else if (deviceid == RTL_PCI_8192DE_DID ||
1891 		   deviceid == RTL_PCI_8192DE_DID2) {
1892 		rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1893 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1894 			"8192D PCI-E is found - vid/did=%x/%x\n",
1895 			venderid, deviceid);
1896 	} else if (deviceid == RTL_PCI_8188EE_DID) {
1897 		rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1898 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1899 			"Find adapter, Hardware type is 8188EE\n");
1900 	} else if (deviceid == RTL_PCI_8723BE_DID) {
1901 		rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1902 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1903 			"Find adapter, Hardware type is 8723BE\n");
1904 	} else if (deviceid == RTL_PCI_8192EE_DID) {
1905 		rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
1906 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1907 			"Find adapter, Hardware type is 8192EE\n");
1908 	} else if (deviceid == RTL_PCI_8821AE_DID) {
1909 		rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
1910 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1911 			"Find adapter, Hardware type is 8821AE\n");
1912 	} else if (deviceid == RTL_PCI_8812AE_DID) {
1913 		rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
1914 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1915 			"Find adapter, Hardware type is 8812AE\n");
1916 	} else if (deviceid == RTL_PCI_8822BE_DID) {
1917 		rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE;
1918 		rtlhal->bandset = BAND_ON_BOTH;
1919 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1920 			"Find adapter, Hardware type is 8822BE\n");
1921 	} else {
1922 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1923 			"Err: Unknown device - vid/did=%x/%x\n",
1924 			 venderid, deviceid);
1925 
1926 		rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1927 	}
1928 
1929 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1930 		if (revisionid == 0 || revisionid == 1) {
1931 			if (revisionid == 0) {
1932 				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1933 					"Find 92DE MAC0\n");
1934 				rtlhal->interfaceindex = 0;
1935 			} else if (revisionid == 1) {
1936 				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1937 					"Find 92DE MAC1\n");
1938 				rtlhal->interfaceindex = 1;
1939 			}
1940 		} else {
1941 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1942 				"Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1943 				 venderid, deviceid, revisionid);
1944 			rtlhal->interfaceindex = 0;
1945 		}
1946 	}
1947 
1948 	switch (rtlhal->hw_type) {
1949 	case HARDWARE_TYPE_RTL8192EE:
1950 	case HARDWARE_TYPE_RTL8822BE:
1951 		/* use new trx flow */
1952 		rtlpriv->use_new_trx_flow = true;
1953 		break;
1954 
1955 	default:
1956 		rtlpriv->use_new_trx_flow = false;
1957 		break;
1958 	}
1959 
1960 	/*find bus info */
1961 	pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1962 	pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1963 	pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1964 
1965 	/*find bridge info */
1966 	pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1967 	/* some ARM have no bridge_pdev and will crash here
1968 	 * so we should check if bridge_pdev is NULL
1969 	 */
1970 	if (bridge_pdev) {
1971 		/*find bridge info if available */
1972 		pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1973 		for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1974 			if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1975 				pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1976 				rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1977 					"Pci Bridge Vendor is found index: %d\n",
1978 					tmp);
1979 				break;
1980 			}
1981 		}
1982 	}
1983 
1984 	if (pcipriv->ndis_adapter.pcibridge_vendor !=
1985 		PCI_BRIDGE_VENDOR_UNKNOWN) {
1986 		pcipriv->ndis_adapter.pcibridge_busnum =
1987 		    bridge_pdev->bus->number;
1988 		pcipriv->ndis_adapter.pcibridge_devnum =
1989 		    PCI_SLOT(bridge_pdev->devfn);
1990 		pcipriv->ndis_adapter.pcibridge_funcnum =
1991 		    PCI_FUNC(bridge_pdev->devfn);
1992 
1993 		if (pcipriv->ndis_adapter.pcibridge_vendor ==
1994 		    PCI_BRIDGE_VENDOR_AMD) {
1995 			pcipriv->ndis_adapter.amd_l1_patch =
1996 			    rtl_pci_get_amd_l1_patch(hw);
1997 		}
1998 	}
1999 
2000 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2001 		"pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2002 		pcipriv->ndis_adapter.busnumber,
2003 		pcipriv->ndis_adapter.devnumber,
2004 		pcipriv->ndis_adapter.funcnumber,
2005 		pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
2006 
2007 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2008 		"pci_bridge busnumber:devnumber:funcnumber:vendor:amd %d:%d:%d:%x:%x\n",
2009 		pcipriv->ndis_adapter.pcibridge_busnum,
2010 		pcipriv->ndis_adapter.pcibridge_devnum,
2011 		pcipriv->ndis_adapter.pcibridge_funcnum,
2012 		pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2013 		pcipriv->ndis_adapter.amd_l1_patch);
2014 
2015 	rtl_pci_parse_configuration(pdev, hw);
2016 	list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2017 
2018 	return true;
2019 }
2020 
2021 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2022 {
2023 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2024 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2025 	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2026 	int ret;
2027 
2028 	ret = pci_enable_msi(rtlpci->pdev);
2029 	if (ret < 0)
2030 		return ret;
2031 
2032 	ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2033 			  IRQF_SHARED, KBUILD_MODNAME, hw);
2034 	if (ret < 0) {
2035 		pci_disable_msi(rtlpci->pdev);
2036 		return ret;
2037 	}
2038 
2039 	rtlpci->using_msi = true;
2040 
2041 	rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2042 		"MSI Interrupt Mode!\n");
2043 	return 0;
2044 }
2045 
2046 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2047 {
2048 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2049 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2050 	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2051 	int ret;
2052 
2053 	ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2054 			  IRQF_SHARED, KBUILD_MODNAME, hw);
2055 	if (ret < 0)
2056 		return ret;
2057 
2058 	rtlpci->using_msi = false;
2059 	rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2060 		"Pin-based Interrupt Mode!\n");
2061 	return 0;
2062 }
2063 
2064 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2065 {
2066 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2067 	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2068 	int ret;
2069 
2070 	if (rtlpci->msi_support) {
2071 		ret = rtl_pci_intr_mode_msi(hw);
2072 		if (ret < 0)
2073 			ret = rtl_pci_intr_mode_legacy(hw);
2074 	} else {
2075 		ret = rtl_pci_intr_mode_legacy(hw);
2076 	}
2077 	return ret;
2078 }
2079 
2080 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
2081 {
2082 	u8	value;
2083 
2084 	pci_read_config_byte(pdev, 0x719, &value);
2085 
2086 	/* 0x719 Bit5 is DMA64 bit fetch. */
2087 	if (dma64)
2088 		value |= BIT(5);
2089 	else
2090 		value &= ~BIT(5);
2091 
2092 	pci_write_config_byte(pdev, 0x719, value);
2093 }
2094 
2095 int rtl_pci_probe(struct pci_dev *pdev,
2096 		  const struct pci_device_id *id)
2097 {
2098 	struct ieee80211_hw *hw = NULL;
2099 
2100 	struct rtl_priv *rtlpriv = NULL;
2101 	struct rtl_pci_priv *pcipriv = NULL;
2102 	struct rtl_pci *rtlpci;
2103 	unsigned long pmem_start, pmem_len, pmem_flags;
2104 	int err;
2105 
2106 	err = pci_enable_device(pdev);
2107 	if (err) {
2108 		WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
2109 			  pci_name(pdev));
2110 		return err;
2111 	}
2112 
2113 	if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 &&
2114 	    !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2115 		if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2116 			WARN_ONCE(true,
2117 				  "Unable to obtain 64bit DMA for consistent allocations\n");
2118 			err = -ENOMEM;
2119 			goto fail1;
2120 		}
2121 
2122 		platform_enable_dma64(pdev, true);
2123 	} else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
2124 		if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
2125 			WARN_ONCE(true,
2126 				  "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
2127 			err = -ENOMEM;
2128 			goto fail1;
2129 		}
2130 
2131 		platform_enable_dma64(pdev, false);
2132 	}
2133 
2134 	pci_set_master(pdev);
2135 
2136 	hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2137 				sizeof(struct rtl_priv), &rtl_ops);
2138 	if (!hw) {
2139 		WARN_ONCE(true,
2140 			  "%s : ieee80211 alloc failed\n", pci_name(pdev));
2141 		err = -ENOMEM;
2142 		goto fail1;
2143 	}
2144 
2145 	SET_IEEE80211_DEV(hw, &pdev->dev);
2146 	pci_set_drvdata(pdev, hw);
2147 
2148 	rtlpriv = hw->priv;
2149 	rtlpriv->hw = hw;
2150 	pcipriv = (void *)rtlpriv->priv;
2151 	pcipriv->dev.pdev = pdev;
2152 	init_completion(&rtlpriv->firmware_loading_complete);
2153 	/*proximity init here*/
2154 	rtlpriv->proximity.proxim_on = false;
2155 
2156 	pcipriv = (void *)rtlpriv->priv;
2157 	pcipriv->dev.pdev = pdev;
2158 
2159 	/* init cfg & intf_ops */
2160 	rtlpriv->rtlhal.interface = INTF_PCI;
2161 	rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2162 	rtlpriv->intf_ops = &rtl_pci_ops;
2163 	rtlpriv->glb_var = &rtl_global_var;
2164 	rtl_efuse_ops_init(hw);
2165 
2166 	/* MEM map */
2167 	err = pci_request_regions(pdev, KBUILD_MODNAME);
2168 	if (err) {
2169 		WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
2170 		goto fail1;
2171 	}
2172 
2173 	pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2174 	pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2175 	pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2176 
2177 	/*shared mem start */
2178 	rtlpriv->io.pci_mem_start =
2179 			(unsigned long)pci_iomap(pdev,
2180 			rtlpriv->cfg->bar_id, pmem_len);
2181 	if (rtlpriv->io.pci_mem_start == 0) {
2182 		WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
2183 		err = -ENOMEM;
2184 		goto fail2;
2185 	}
2186 
2187 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2188 		"mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2189 		pmem_start, pmem_len, pmem_flags,
2190 		rtlpriv->io.pci_mem_start);
2191 
2192 	/* Disable Clk Request */
2193 	pci_write_config_byte(pdev, 0x81, 0);
2194 	/* leave D3 mode */
2195 	pci_write_config_byte(pdev, 0x44, 0);
2196 	pci_write_config_byte(pdev, 0x04, 0x06);
2197 	pci_write_config_byte(pdev, 0x04, 0x07);
2198 
2199 	/* find adapter */
2200 	if (!_rtl_pci_find_adapter(pdev, hw)) {
2201 		err = -ENODEV;
2202 		goto fail2;
2203 	}
2204 
2205 	/* Init IO handler */
2206 	_rtl_pci_io_handler_init(&pdev->dev, hw);
2207 
2208 	/*like read eeprom and so on */
2209 	rtlpriv->cfg->ops->read_eeprom_info(hw);
2210 
2211 	if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2212 		pr_err("Can't init_sw_vars\n");
2213 		err = -ENODEV;
2214 		goto fail3;
2215 	}
2216 	rtl_init_sw_leds(hw);
2217 
2218 	/*aspm */
2219 	rtl_pci_init_aspm(hw);
2220 
2221 	/* Init mac80211 sw */
2222 	err = rtl_init_core(hw);
2223 	if (err) {
2224 		pr_err("Can't allocate sw for mac80211\n");
2225 		goto fail3;
2226 	}
2227 
2228 	/* Init PCI sw */
2229 	err = rtl_pci_init(hw, pdev);
2230 	if (err) {
2231 		pr_err("Failed to init PCI\n");
2232 		goto fail3;
2233 	}
2234 
2235 	err = ieee80211_register_hw(hw);
2236 	if (err) {
2237 		pr_err("Can't register mac80211 hw.\n");
2238 		err = -ENODEV;
2239 		goto fail3;
2240 	}
2241 	rtlpriv->mac80211.mac80211_registered = 1;
2242 
2243 	/* add for debug */
2244 	rtl_debug_add_one(hw);
2245 
2246 	/*init rfkill */
2247 	rtl_init_rfkill(hw);	/* Init PCI sw */
2248 
2249 	rtlpci = rtl_pcidev(pcipriv);
2250 	err = rtl_pci_intr_mode_decide(hw);
2251 	if (err) {
2252 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2253 			"%s: failed to register IRQ handler\n",
2254 			wiphy_name(hw->wiphy));
2255 		goto fail3;
2256 	}
2257 	rtlpci->irq_alloc = 1;
2258 
2259 	set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2260 	return 0;
2261 
2262 fail3:
2263 	pci_set_drvdata(pdev, NULL);
2264 	rtl_deinit_core(hw);
2265 
2266 fail2:
2267 	if (rtlpriv->io.pci_mem_start != 0)
2268 		pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2269 
2270 	pci_release_regions(pdev);
2271 	complete(&rtlpriv->firmware_loading_complete);
2272 
2273 fail1:
2274 	if (hw)
2275 		ieee80211_free_hw(hw);
2276 	pci_disable_device(pdev);
2277 
2278 	return err;
2279 }
2280 EXPORT_SYMBOL(rtl_pci_probe);
2281 
2282 void rtl_pci_disconnect(struct pci_dev *pdev)
2283 {
2284 	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2285 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2286 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2287 	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2288 	struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2289 
2290 	/* just in case driver is removed before firmware callback */
2291 	wait_for_completion(&rtlpriv->firmware_loading_complete);
2292 	clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2293 
2294 	/* remove form debug */
2295 	rtl_debug_remove_one(hw);
2296 
2297 	/*ieee80211_unregister_hw will call ops_stop */
2298 	if (rtlmac->mac80211_registered == 1) {
2299 		ieee80211_unregister_hw(hw);
2300 		rtlmac->mac80211_registered = 0;
2301 	} else {
2302 		rtl_deinit_deferred_work(hw, false);
2303 		rtlpriv->intf_ops->adapter_stop(hw);
2304 	}
2305 	rtlpriv->cfg->ops->disable_interrupt(hw);
2306 
2307 	/*deinit rfkill */
2308 	rtl_deinit_rfkill(hw);
2309 
2310 	rtl_pci_deinit(hw);
2311 	rtl_deinit_core(hw);
2312 	rtlpriv->cfg->ops->deinit_sw_vars(hw);
2313 
2314 	if (rtlpci->irq_alloc) {
2315 		free_irq(rtlpci->pdev->irq, hw);
2316 		rtlpci->irq_alloc = 0;
2317 	}
2318 
2319 	if (rtlpci->using_msi)
2320 		pci_disable_msi(rtlpci->pdev);
2321 
2322 	list_del(&rtlpriv->list);
2323 	if (rtlpriv->io.pci_mem_start != 0) {
2324 		pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2325 		pci_release_regions(pdev);
2326 	}
2327 
2328 	pci_disable_device(pdev);
2329 
2330 	rtl_pci_disable_aspm(hw);
2331 
2332 	pci_set_drvdata(pdev, NULL);
2333 
2334 	ieee80211_free_hw(hw);
2335 }
2336 EXPORT_SYMBOL(rtl_pci_disconnect);
2337 
2338 #ifdef CONFIG_PM_SLEEP
2339 /***************************************
2340  * kernel pci power state define:
2341  * PCI_D0         ((pci_power_t __force) 0)
2342  * PCI_D1         ((pci_power_t __force) 1)
2343  * PCI_D2         ((pci_power_t __force) 2)
2344  * PCI_D3hot      ((pci_power_t __force) 3)
2345  * PCI_D3cold     ((pci_power_t __force) 4)
2346  * PCI_UNKNOWN    ((pci_power_t __force) 5)
2347 
2348  * This function is called when system
2349  * goes into suspend state mac80211 will
2350  * call rtl_mac_stop() from the mac80211
2351  * suspend function first, So there is
2352  * no need to call hw_disable here.
2353  ****************************************/
2354 int rtl_pci_suspend(struct device *dev)
2355 {
2356 	struct ieee80211_hw *hw = dev_get_drvdata(dev);
2357 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2358 
2359 	rtlpriv->cfg->ops->hw_suspend(hw);
2360 	rtl_deinit_rfkill(hw);
2361 
2362 	return 0;
2363 }
2364 EXPORT_SYMBOL(rtl_pci_suspend);
2365 
2366 int rtl_pci_resume(struct device *dev)
2367 {
2368 	struct ieee80211_hw *hw = dev_get_drvdata(dev);
2369 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2370 
2371 	rtlpriv->cfg->ops->hw_resume(hw);
2372 	rtl_init_rfkill(hw);
2373 	return 0;
2374 }
2375 EXPORT_SYMBOL(rtl_pci_resume);
2376 #endif /* CONFIG_PM_SLEEP */
2377 
2378 const struct rtl_intf_ops rtl_pci_ops = {
2379 	.read_efuse_byte = read_efuse_byte,
2380 	.adapter_start = rtl_pci_start,
2381 	.adapter_stop = rtl_pci_stop,
2382 	.check_buddy_priv = rtl_pci_check_buddy_priv,
2383 	.adapter_tx = rtl_pci_tx,
2384 	.flush = rtl_pci_flush,
2385 	.reset_trx_ring = rtl_pci_reset_trx_ring,
2386 	.waitq_insert = rtl_pci_tx_chk_waitq_insert,
2387 
2388 	.disable_aspm = rtl_pci_disable_aspm,
2389 	.enable_aspm = rtl_pci_enable_aspm,
2390 };
2391