1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #include "wifi.h"
5 #include "core.h"
6 #include "pci.h"
7 #include "base.h"
8 #include "ps.h"
9 #include "efuse.h"
10 #include <linux/interrupt.h>
11 #include <linux/export.h>
12 #include <linux/module.h>
13 
14 MODULE_AUTHOR("lizhaoming	<chaoming_li@realsil.com.cn>");
15 MODULE_AUTHOR("Realtek WlanFAE	<wlanfae@realtek.com>");
16 MODULE_AUTHOR("Larry Finger	<Larry.FInger@lwfinger.net>");
17 MODULE_LICENSE("GPL");
18 MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
19 
20 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
21 	INTEL_VENDOR_ID,
22 	ATI_VENDOR_ID,
23 	AMD_VENDOR_ID,
24 	SIS_VENDOR_ID
25 };
26 
27 static const u8 ac_to_hwq[] = {
28 	VO_QUEUE,
29 	VI_QUEUE,
30 	BE_QUEUE,
31 	BK_QUEUE
32 };
33 
34 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb)
35 {
36 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
37 	__le16 fc = rtl_get_fc(skb);
38 	u8 queue_index = skb_get_queue_mapping(skb);
39 	struct ieee80211_hdr *hdr;
40 
41 	if (unlikely(ieee80211_is_beacon(fc)))
42 		return BEACON_QUEUE;
43 	if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
44 		return MGNT_QUEUE;
45 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
46 		if (ieee80211_is_nullfunc(fc))
47 			return HIGH_QUEUE;
48 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
49 		hdr = rtl_get_hdr(skb);
50 
51 		if (is_multicast_ether_addr(hdr->addr1) ||
52 		    is_broadcast_ether_addr(hdr->addr1))
53 			return HIGH_QUEUE;
54 	}
55 
56 	return ac_to_hwq[queue_index];
57 }
58 
59 /* Update PCI dependent default settings*/
60 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
61 {
62 	struct rtl_priv *rtlpriv = rtl_priv(hw);
63 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
64 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
65 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
66 	u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
67 	u8 init_aspm;
68 
69 	ppsc->reg_rfps_level = 0;
70 	ppsc->support_aspm = false;
71 
72 	/*Update PCI ASPM setting */
73 	ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
74 	switch (rtlpci->const_pci_aspm) {
75 	case 0:
76 		/*No ASPM */
77 		break;
78 
79 	case 1:
80 		/*ASPM dynamically enabled/disable. */
81 		ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
82 		break;
83 
84 	case 2:
85 		/*ASPM with Clock Req dynamically enabled/disable. */
86 		ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
87 					 RT_RF_OFF_LEVL_CLK_REQ);
88 		break;
89 
90 	case 3:
91 		/* Always enable ASPM and Clock Req
92 		 * from initialization to halt.
93 		 */
94 		ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
95 		ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
96 					 RT_RF_OFF_LEVL_CLK_REQ);
97 		break;
98 
99 	case 4:
100 		/* Always enable ASPM without Clock Req
101 		 * from initialization to halt.
102 		 */
103 		ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
104 					  RT_RF_OFF_LEVL_CLK_REQ);
105 		ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
106 		break;
107 	}
108 
109 	ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
110 
111 	/*Update Radio OFF setting */
112 	switch (rtlpci->const_hwsw_rfoff_d3) {
113 	case 1:
114 		if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
115 			ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
116 		break;
117 
118 	case 2:
119 		if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
120 			ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
121 		ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
122 		break;
123 
124 	case 3:
125 		ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
126 		break;
127 	}
128 
129 	/*Set HW definition to determine if it supports ASPM. */
130 	switch (rtlpci->const_support_pciaspm) {
131 	case 0:
132 		/*Not support ASPM. */
133 		ppsc->support_aspm = false;
134 		break;
135 	case 1:
136 		/*Support ASPM. */
137 		ppsc->support_aspm = true;
138 		ppsc->support_backdoor = true;
139 		break;
140 	case 2:
141 		/*ASPM value set by chipset. */
142 		if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
143 			ppsc->support_aspm = true;
144 		break;
145 	default:
146 		pr_err("switch case %#x not processed\n",
147 		       rtlpci->const_support_pciaspm);
148 		break;
149 	}
150 
151 	/* toshiba aspm issue, toshiba will set aspm selfly
152 	 * so we should not set aspm in driver
153 	 */
154 	pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
155 	if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
156 	    init_aspm == 0x43)
157 		ppsc->support_aspm = false;
158 }
159 
160 static bool _rtl_pci_platform_switch_device_pci_aspm(
161 			struct ieee80211_hw *hw,
162 			u8 value)
163 {
164 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
165 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
166 
167 	if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
168 		value |= 0x40;
169 
170 	pci_write_config_byte(rtlpci->pdev, 0x80, value);
171 
172 	return false;
173 }
174 
175 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
176 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
177 {
178 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
179 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
180 
181 	pci_write_config_byte(rtlpci->pdev, 0x81, value);
182 
183 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
184 		udelay(100);
185 }
186 
187 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
188 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
189 {
190 	struct rtl_priv *rtlpriv = rtl_priv(hw);
191 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
192 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
193 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
194 	u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
195 	u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
196 	/*Retrieve original configuration settings. */
197 	u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
198 	u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
199 				pcibridge_linkctrlreg;
200 	u16 aspmlevel = 0;
201 	u8 tmp_u1b = 0;
202 
203 	if (!ppsc->support_aspm)
204 		return;
205 
206 	if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
207 		rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
208 			"PCI(Bridge) UNKNOWN\n");
209 
210 		return;
211 	}
212 
213 	if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
214 		RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
215 		_rtl_pci_switch_clk_req(hw, 0x0);
216 	}
217 
218 	/*for promising device will in L0 state after an I/O. */
219 	pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
220 
221 	/*Set corresponding value. */
222 	aspmlevel |= BIT(0) | BIT(1);
223 	linkctrl_reg &= ~aspmlevel;
224 	pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
225 
226 	_rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
227 	udelay(50);
228 
229 	/*4 Disable Pci Bridge ASPM */
230 	pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
231 			      pcibridge_linkctrlreg);
232 
233 	udelay(50);
234 }
235 
236 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
237  *power saving We should follow the sequence to enable
238  *RTL8192SE first then enable Pci Bridge ASPM
239  *or the system will show bluescreen.
240  */
241 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
242 {
243 	struct rtl_priv *rtlpriv = rtl_priv(hw);
244 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
245 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
246 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
247 	u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
248 	u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
249 	u16 aspmlevel;
250 	u8 u_pcibridge_aspmsetting;
251 	u8 u_device_aspmsetting;
252 
253 	if (!ppsc->support_aspm)
254 		return;
255 
256 	if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
257 		rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
258 			"PCI(Bridge) UNKNOWN\n");
259 		return;
260 	}
261 
262 	/*4 Enable Pci Bridge ASPM */
263 
264 	u_pcibridge_aspmsetting =
265 	    pcipriv->ndis_adapter.pcibridge_linkctrlreg |
266 	    rtlpci->const_hostpci_aspm_setting;
267 
268 	if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
269 		u_pcibridge_aspmsetting &= ~BIT(0);
270 
271 	pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
272 			      u_pcibridge_aspmsetting);
273 
274 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
275 		"PlatformEnableASPM(): Write reg[%x] = %x\n",
276 		(pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
277 		u_pcibridge_aspmsetting);
278 
279 	udelay(50);
280 
281 	/*Get ASPM level (with/without Clock Req) */
282 	aspmlevel = rtlpci->const_devicepci_aspm_setting;
283 	u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
284 
285 	/*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
286 	/*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
287 
288 	u_device_aspmsetting |= aspmlevel;
289 
290 	_rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
291 
292 	if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
293 		_rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
294 					     RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
295 		RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
296 	}
297 	udelay(100);
298 }
299 
300 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
301 {
302 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
303 
304 	bool status = false;
305 	u8 offset_e0;
306 	unsigned int offset_e4;
307 
308 	pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
309 
310 	pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
311 
312 	if (offset_e0 == 0xA0) {
313 		pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
314 		if (offset_e4 & BIT(23))
315 			status = true;
316 	}
317 
318 	return status;
319 }
320 
321 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
322 				     struct rtl_priv **buddy_priv)
323 {
324 	struct rtl_priv *rtlpriv = rtl_priv(hw);
325 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
326 	bool find_buddy_priv = false;
327 	struct rtl_priv *tpriv;
328 	struct rtl_pci_priv *tpcipriv = NULL;
329 
330 	if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
331 		list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
332 				    list) {
333 			tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
334 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
335 				"pcipriv->ndis_adapter.funcnumber %x\n",
336 				pcipriv->ndis_adapter.funcnumber);
337 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
338 				"tpcipriv->ndis_adapter.funcnumber %x\n",
339 				tpcipriv->ndis_adapter.funcnumber);
340 
341 			if (pcipriv->ndis_adapter.busnumber ==
342 			    tpcipriv->ndis_adapter.busnumber &&
343 			    pcipriv->ndis_adapter.devnumber ==
344 			    tpcipriv->ndis_adapter.devnumber &&
345 			    pcipriv->ndis_adapter.funcnumber !=
346 			    tpcipriv->ndis_adapter.funcnumber) {
347 				find_buddy_priv = true;
348 				break;
349 			}
350 		}
351 	}
352 
353 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
354 		"find_buddy_priv %d\n", find_buddy_priv);
355 
356 	if (find_buddy_priv)
357 		*buddy_priv = tpriv;
358 
359 	return find_buddy_priv;
360 }
361 
362 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
363 {
364 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
365 	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
366 	u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
367 	u8 linkctrl_reg;
368 	u8 num4bbytes;
369 
370 	num4bbytes = (capabilityoffset + 0x10) / 4;
371 
372 	/*Read  Link Control Register */
373 	pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
374 
375 	pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
376 }
377 
378 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
379 					struct ieee80211_hw *hw)
380 {
381 	struct rtl_priv *rtlpriv = rtl_priv(hw);
382 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
383 
384 	u8 tmp;
385 	u16 linkctrl_reg;
386 
387 	/*Link Control Register */
388 	pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
389 	pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
390 
391 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
392 		pcipriv->ndis_adapter.linkctrl_reg);
393 
394 	pci_read_config_byte(pdev, 0x98, &tmp);
395 	tmp |= BIT(4);
396 	pci_write_config_byte(pdev, 0x98, tmp);
397 
398 	tmp = 0x17;
399 	pci_write_config_byte(pdev, 0x70f, tmp);
400 }
401 
402 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
403 {
404 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
405 
406 	_rtl_pci_update_default_setting(hw);
407 
408 	if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
409 		/*Always enable ASPM & Clock Req. */
410 		rtl_pci_enable_aspm(hw);
411 		RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
412 	}
413 }
414 
415 static void _rtl_pci_io_handler_init(struct device *dev,
416 				     struct ieee80211_hw *hw)
417 {
418 	struct rtl_priv *rtlpriv = rtl_priv(hw);
419 
420 	rtlpriv->io.dev = dev;
421 
422 	rtlpriv->io.write8_async = pci_write8_async;
423 	rtlpriv->io.write16_async = pci_write16_async;
424 	rtlpriv->io.write32_async = pci_write32_async;
425 
426 	rtlpriv->io.read8_sync = pci_read8_sync;
427 	rtlpriv->io.read16_sync = pci_read16_sync;
428 	rtlpriv->io.read32_sync = pci_read32_sync;
429 }
430 
431 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
432 				       struct sk_buff *skb,
433 				       struct rtl_tcb_desc *tcb_desc, u8 tid)
434 {
435 	struct rtl_priv *rtlpriv = rtl_priv(hw);
436 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
437 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
438 	struct sk_buff *next_skb;
439 	u8 additionlen = FCS_LEN;
440 
441 	/* here open is 4, wep/tkip is 8, aes is 12*/
442 	if (info->control.hw_key)
443 		additionlen += info->control.hw_key->icv_len;
444 
445 	/* The most skb num is 6 */
446 	tcb_desc->empkt_num = 0;
447 	spin_lock_bh(&rtlpriv->locks.waitq_lock);
448 	skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
449 		struct ieee80211_tx_info *next_info;
450 
451 		next_info = IEEE80211_SKB_CB(next_skb);
452 		if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
453 			tcb_desc->empkt_len[tcb_desc->empkt_num] =
454 				next_skb->len + additionlen;
455 			tcb_desc->empkt_num++;
456 		} else {
457 			break;
458 		}
459 
460 		if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
461 				      next_skb))
462 			break;
463 
464 		if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
465 			break;
466 	}
467 	spin_unlock_bh(&rtlpriv->locks.waitq_lock);
468 
469 	return true;
470 }
471 
472 /* just for early mode now */
473 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
474 {
475 	struct rtl_priv *rtlpriv = rtl_priv(hw);
476 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
477 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
478 	struct sk_buff *skb = NULL;
479 	struct ieee80211_tx_info *info = NULL;
480 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
481 	int tid;
482 
483 	if (!rtlpriv->rtlhal.earlymode_enable)
484 		return;
485 
486 	if (rtlpriv->dm.supp_phymode_switch &&
487 	    (rtlpriv->easy_concurrent_ctl.switch_in_process ||
488 	    (rtlpriv->buddy_priv &&
489 	    rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
490 		return;
491 	/* we just use em for BE/BK/VI/VO */
492 	for (tid = 7; tid >= 0; tid--) {
493 		u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
494 		struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
495 
496 		while (!mac->act_scanning &&
497 		       rtlpriv->psc.rfpwr_state == ERFON) {
498 			struct rtl_tcb_desc tcb_desc;
499 
500 			memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
501 
502 			spin_lock(&rtlpriv->locks.waitq_lock);
503 			if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
504 			    (ring->entries - skb_queue_len(&ring->queue) >
505 			     rtlhal->max_earlymode_num)) {
506 				skb = skb_dequeue(&mac->skb_waitq[tid]);
507 			} else {
508 				spin_unlock(&rtlpriv->locks.waitq_lock);
509 				break;
510 			}
511 			spin_unlock(&rtlpriv->locks.waitq_lock);
512 
513 			/* Some macaddr can't do early mode. like
514 			 * multicast/broadcast/no_qos data
515 			 */
516 			info = IEEE80211_SKB_CB(skb);
517 			if (info->flags & IEEE80211_TX_CTL_AMPDU)
518 				_rtl_update_earlymode_info(hw, skb,
519 							   &tcb_desc, tid);
520 
521 			rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
522 		}
523 	}
524 }
525 
526 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
527 {
528 	struct rtl_priv *rtlpriv = rtl_priv(hw);
529 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
530 
531 	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
532 
533 	while (skb_queue_len(&ring->queue)) {
534 		struct sk_buff *skb;
535 		struct ieee80211_tx_info *info;
536 		__le16 fc;
537 		u8 tid;
538 		u8 *entry;
539 
540 		if (rtlpriv->use_new_trx_flow)
541 			entry = (u8 *)(&ring->buffer_desc[ring->idx]);
542 		else
543 			entry = (u8 *)(&ring->desc[ring->idx]);
544 
545 		if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
546 			return;
547 		ring->idx = (ring->idx + 1) % ring->entries;
548 
549 		skb = __skb_dequeue(&ring->queue);
550 		dma_unmap_single(&rtlpci->pdev->dev,
551 				 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
552 						true, HW_DESC_TXBUFF_ADDR),
553 				 skb->len, DMA_TO_DEVICE);
554 
555 		/* remove early mode header */
556 		if (rtlpriv->rtlhal.earlymode_enable)
557 			skb_pull(skb, EM_HDR_LEN);
558 
559 		rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
560 			"new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
561 			ring->idx,
562 			skb_queue_len(&ring->queue),
563 			*(u16 *)(skb->data + 22));
564 
565 		if (prio == TXCMD_QUEUE) {
566 			dev_kfree_skb(skb);
567 			goto tx_status_ok;
568 		}
569 
570 		/* for sw LPS, just after NULL skb send out, we can
571 		 * sure AP knows we are sleeping, we should not let
572 		 * rf sleep
573 		 */
574 		fc = rtl_get_fc(skb);
575 		if (ieee80211_is_nullfunc(fc)) {
576 			if (ieee80211_has_pm(fc)) {
577 				rtlpriv->mac80211.offchan_delay = true;
578 				rtlpriv->psc.state_inap = true;
579 			} else {
580 				rtlpriv->psc.state_inap = false;
581 			}
582 		}
583 		if (ieee80211_is_action(fc)) {
584 			struct ieee80211_mgmt *action_frame =
585 				(struct ieee80211_mgmt *)skb->data;
586 			if (action_frame->u.action.u.ht_smps.action ==
587 			    WLAN_HT_ACTION_SMPS) {
588 				dev_kfree_skb(skb);
589 				goto tx_status_ok;
590 			}
591 		}
592 
593 		/* update tid tx pkt num */
594 		tid = rtl_get_tid(skb);
595 		if (tid <= 7)
596 			rtlpriv->link_info.tidtx_inperiod[tid]++;
597 
598 		info = IEEE80211_SKB_CB(skb);
599 
600 		if (likely(!ieee80211_is_nullfunc(fc))) {
601 			ieee80211_tx_info_clear_status(info);
602 			info->flags |= IEEE80211_TX_STAT_ACK;
603 			/*info->status.rates[0].count = 1; */
604 			ieee80211_tx_status_irqsafe(hw, skb);
605 		} else {
606 			rtl_tx_ackqueue(hw, skb);
607 		}
608 
609 		if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
610 			rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,
611 				"more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
612 				prio, ring->idx,
613 				skb_queue_len(&ring->queue));
614 
615 			ieee80211_wake_queue(hw, skb_get_queue_mapping(skb));
616 		}
617 tx_status_ok:
618 		skb = NULL;
619 	}
620 
621 	if (((rtlpriv->link_info.num_rx_inperiod +
622 	      rtlpriv->link_info.num_tx_inperiod) > 8) ||
623 	      rtlpriv->link_info.num_rx_inperiod > 2)
624 		rtl_lps_leave(hw, false);
625 }
626 
627 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
628 				    struct sk_buff *new_skb, u8 *entry,
629 				    int rxring_idx, int desc_idx)
630 {
631 	struct rtl_priv *rtlpriv = rtl_priv(hw);
632 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
633 	u32 bufferaddress;
634 	u8 tmp_one = 1;
635 	struct sk_buff *skb;
636 
637 	if (likely(new_skb)) {
638 		skb = new_skb;
639 		goto remap;
640 	}
641 	skb = dev_alloc_skb(rtlpci->rxbuffersize);
642 	if (!skb)
643 		return 0;
644 
645 remap:
646 	/* just set skb->cb to mapping addr for pci_unmap_single use */
647 	*((dma_addr_t *)skb->cb) =
648 		dma_map_single(&rtlpci->pdev->dev, skb_tail_pointer(skb),
649 			       rtlpci->rxbuffersize, DMA_FROM_DEVICE);
650 	bufferaddress = *((dma_addr_t *)skb->cb);
651 	if (dma_mapping_error(&rtlpci->pdev->dev, bufferaddress))
652 		return 0;
653 	rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
654 	if (rtlpriv->use_new_trx_flow) {
655 		/* skb->cb may be 64 bit address */
656 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
657 					    HW_DESC_RX_PREPARE,
658 					    (u8 *)(dma_addr_t *)skb->cb);
659 	} else {
660 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
661 					    HW_DESC_RXBUFF_ADDR,
662 					    (u8 *)&bufferaddress);
663 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
664 					    HW_DESC_RXPKT_LEN,
665 					    (u8 *)&rtlpci->rxbuffersize);
666 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
667 					    HW_DESC_RXOWN,
668 					    (u8 *)&tmp_one);
669 	}
670 	return 1;
671 }
672 
673 /* inorder to receive 8K AMSDU we have set skb to
674  * 9100bytes in init rx ring, but if this packet is
675  * not a AMSDU, this large packet will be sent to
676  * TCP/IP directly, this cause big packet ping fail
677  * like: "ping -s 65507", so here we will realloc skb
678  * based on the true size of packet, Mac80211
679  * Probably will do it better, but does not yet.
680  *
681  * Some platform will fail when alloc skb sometimes.
682  * in this condition, we will send the old skb to
683  * mac80211 directly, this will not cause any other
684  * issues, but only this packet will be lost by TCP/IP
685  */
686 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
687 				    struct sk_buff *skb,
688 				    struct ieee80211_rx_status rx_status)
689 {
690 	if (unlikely(!rtl_action_proc(hw, skb, false))) {
691 		dev_kfree_skb_any(skb);
692 	} else {
693 		struct sk_buff *uskb = NULL;
694 
695 		uskb = dev_alloc_skb(skb->len + 128);
696 		if (likely(uskb)) {
697 			memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
698 			       sizeof(rx_status));
699 			skb_put_data(uskb, skb->data, skb->len);
700 			dev_kfree_skb_any(skb);
701 			ieee80211_rx_irqsafe(hw, uskb);
702 		} else {
703 			ieee80211_rx_irqsafe(hw, skb);
704 		}
705 	}
706 }
707 
708 /*hsisr interrupt handler*/
709 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
710 {
711 	struct rtl_priv *rtlpriv = rtl_priv(hw);
712 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
713 
714 	rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
715 		       rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
716 		       rtlpci->sys_irq_mask);
717 }
718 
719 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
720 {
721 	struct rtl_priv *rtlpriv = rtl_priv(hw);
722 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
723 	int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
724 	struct ieee80211_rx_status rx_status = { 0 };
725 	unsigned int count = rtlpci->rxringcount;
726 	u8 own;
727 	u8 tmp_one;
728 	bool unicast = false;
729 	u8 hw_queue = 0;
730 	unsigned int rx_remained_cnt = 0;
731 	struct rtl_stats stats = {
732 		.signal = 0,
733 		.rate = 0,
734 	};
735 
736 	/*RX NORMAL PKT */
737 	while (count--) {
738 		struct ieee80211_hdr *hdr;
739 		__le16 fc;
740 		u16 len;
741 		/*rx buffer descriptor */
742 		struct rtl_rx_buffer_desc *buffer_desc = NULL;
743 		/*if use new trx flow, it means wifi info */
744 		struct rtl_rx_desc *pdesc = NULL;
745 		/*rx pkt */
746 		struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
747 				      rtlpci->rx_ring[rxring_idx].idx];
748 		struct sk_buff *new_skb;
749 
750 		if (rtlpriv->use_new_trx_flow) {
751 			if (rx_remained_cnt == 0)
752 				rx_remained_cnt =
753 				rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
754 								      hw_queue);
755 			if (rx_remained_cnt == 0)
756 				return;
757 			buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
758 				rtlpci->rx_ring[rxring_idx].idx];
759 			pdesc = (struct rtl_rx_desc *)skb->data;
760 		} else {	/* rx descriptor */
761 			pdesc = &rtlpci->rx_ring[rxring_idx].desc[
762 				rtlpci->rx_ring[rxring_idx].idx];
763 
764 			own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
765 							      false,
766 							      HW_DESC_OWN);
767 			if (own) /* wait data to be filled by hardware */
768 				return;
769 		}
770 
771 		/* Reaching this point means: data is filled already
772 		 * AAAAAAttention !!!
773 		 * We can NOT access 'skb' before 'pci_unmap_single'
774 		 */
775 		dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
776 				 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
777 
778 		/* get a new skb - if fail, old one will be reused */
779 		new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
780 		if (unlikely(!new_skb))
781 			goto no_new;
782 		memset(&rx_status, 0, sizeof(rx_status));
783 		rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
784 						 &rx_status, (u8 *)pdesc, skb);
785 
786 		if (rtlpriv->use_new_trx_flow)
787 			rtlpriv->cfg->ops->rx_check_dma_ok(hw,
788 							   (u8 *)buffer_desc,
789 							   hw_queue);
790 
791 		len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
792 						  HW_DESC_RXPKT_LEN);
793 
794 		if (skb->end - skb->tail > len) {
795 			skb_put(skb, len);
796 			if (rtlpriv->use_new_trx_flow)
797 				skb_reserve(skb, stats.rx_drvinfo_size +
798 					    stats.rx_bufshift + 24);
799 			else
800 				skb_reserve(skb, stats.rx_drvinfo_size +
801 					    stats.rx_bufshift);
802 		} else {
803 			rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
804 				"skb->end - skb->tail = %d, len is %d\n",
805 				skb->end - skb->tail, len);
806 			dev_kfree_skb_any(skb);
807 			goto new_trx_end;
808 		}
809 		/* handle command packet here */
810 		if (stats.packet_report_type == C2H_PACKET) {
811 			rtl_c2hcmd_enqueue(hw, skb);
812 			goto new_trx_end;
813 		}
814 
815 		/* NOTICE This can not be use for mac80211,
816 		 * this is done in mac80211 code,
817 		 * if done here sec DHCP will fail
818 		 * skb_trim(skb, skb->len - 4);
819 		 */
820 
821 		hdr = rtl_get_hdr(skb);
822 		fc = rtl_get_fc(skb);
823 
824 		if (!stats.crc && !stats.hwerror && (skb->len > FCS_LEN)) {
825 			memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
826 			       sizeof(rx_status));
827 
828 			if (is_broadcast_ether_addr(hdr->addr1)) {
829 				;/*TODO*/
830 			} else if (is_multicast_ether_addr(hdr->addr1)) {
831 				;/*TODO*/
832 			} else {
833 				unicast = true;
834 				rtlpriv->stats.rxbytesunicast += skb->len;
835 			}
836 			rtl_is_special_data(hw, skb, false, true);
837 
838 			if (ieee80211_is_data(fc)) {
839 				rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
840 				if (unicast)
841 					rtlpriv->link_info.num_rx_inperiod++;
842 			}
843 
844 			rtl_collect_scan_list(hw, skb);
845 
846 			/* static bcn for roaming */
847 			rtl_beacon_statistic(hw, skb);
848 			rtl_p2p_info(hw, (void *)skb->data, skb->len);
849 			/* for sw lps */
850 			rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
851 			rtl_recognize_peer(hw, (void *)skb->data, skb->len);
852 			if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP &&
853 			    rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G &&
854 			    (ieee80211_is_beacon(fc) ||
855 			     ieee80211_is_probe_resp(fc))) {
856 				dev_kfree_skb_any(skb);
857 			} else {
858 				_rtl_pci_rx_to_mac80211(hw, skb, rx_status);
859 			}
860 		} else {
861 			/* drop packets with errors or those too short */
862 			dev_kfree_skb_any(skb);
863 		}
864 new_trx_end:
865 		if (rtlpriv->use_new_trx_flow) {
866 			rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
867 			rtlpci->rx_ring[hw_queue].next_rx_rp %=
868 					RTL_PCI_MAX_RX_COUNT;
869 
870 			rx_remained_cnt--;
871 			rtl_write_word(rtlpriv, 0x3B4,
872 				       rtlpci->rx_ring[hw_queue].next_rx_rp);
873 		}
874 		if (((rtlpriv->link_info.num_rx_inperiod +
875 		      rtlpriv->link_info.num_tx_inperiod) > 8) ||
876 		      rtlpriv->link_info.num_rx_inperiod > 2)
877 			rtl_lps_leave(hw, false);
878 		skb = new_skb;
879 no_new:
880 		if (rtlpriv->use_new_trx_flow) {
881 			_rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
882 						 rxring_idx,
883 						 rtlpci->rx_ring[rxring_idx].idx);
884 		} else {
885 			_rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
886 						 rxring_idx,
887 						 rtlpci->rx_ring[rxring_idx].idx);
888 			if (rtlpci->rx_ring[rxring_idx].idx ==
889 			    rtlpci->rxringcount - 1)
890 				rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
891 							    false,
892 							    HW_DESC_RXERO,
893 							    (u8 *)&tmp_one);
894 		}
895 		rtlpci->rx_ring[rxring_idx].idx =
896 				(rtlpci->rx_ring[rxring_idx].idx + 1) %
897 				rtlpci->rxringcount;
898 	}
899 }
900 
901 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
902 {
903 	struct ieee80211_hw *hw = dev_id;
904 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
905 	struct rtl_priv *rtlpriv = rtl_priv(hw);
906 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
907 	unsigned long flags;
908 	struct rtl_int intvec = {0};
909 
910 	irqreturn_t ret = IRQ_HANDLED;
911 
912 	if (rtlpci->irq_enabled == 0)
913 		return ret;
914 
915 	spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
916 	rtlpriv->cfg->ops->disable_interrupt(hw);
917 
918 	/*read ISR: 4/8bytes */
919 	rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec);
920 
921 	/*Shared IRQ or HW disappeared */
922 	if (!intvec.inta || intvec.inta == 0xffff)
923 		goto done;
924 
925 	/*<1> beacon related */
926 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK])
927 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
928 			"beacon ok interrupt!\n");
929 
930 	if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER]))
931 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
932 			"beacon err interrupt!\n");
933 
934 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
935 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
936 
937 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
938 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
939 			"prepare beacon for interrupt!\n");
940 		tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
941 	}
942 
943 	/*<2> Tx related */
944 	if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
945 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
946 
947 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
948 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
949 			"Manage ok interrupt!\n");
950 		_rtl_pci_tx_isr(hw, MGNT_QUEUE);
951 	}
952 
953 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
954 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
955 			"HIGH_QUEUE ok interrupt!\n");
956 		_rtl_pci_tx_isr(hw, HIGH_QUEUE);
957 	}
958 
959 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
960 		rtlpriv->link_info.num_tx_inperiod++;
961 
962 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
963 			"BK Tx OK interrupt!\n");
964 		_rtl_pci_tx_isr(hw, BK_QUEUE);
965 	}
966 
967 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
968 		rtlpriv->link_info.num_tx_inperiod++;
969 
970 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
971 			"BE TX OK interrupt!\n");
972 		_rtl_pci_tx_isr(hw, BE_QUEUE);
973 	}
974 
975 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
976 		rtlpriv->link_info.num_tx_inperiod++;
977 
978 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
979 			"VI TX OK interrupt!\n");
980 		_rtl_pci_tx_isr(hw, VI_QUEUE);
981 	}
982 
983 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
984 		rtlpriv->link_info.num_tx_inperiod++;
985 
986 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
987 			"Vo TX OK interrupt!\n");
988 		_rtl_pci_tx_isr(hw, VO_QUEUE);
989 	}
990 
991 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
992 		if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
993 			rtlpriv->link_info.num_tx_inperiod++;
994 
995 			rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
996 				"H2C TX OK interrupt!\n");
997 			_rtl_pci_tx_isr(hw, H2C_QUEUE);
998 		}
999 	}
1000 
1001 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1002 		if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
1003 			rtlpriv->link_info.num_tx_inperiod++;
1004 
1005 			rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
1006 				"CMD TX OK interrupt!\n");
1007 			_rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1008 		}
1009 	}
1010 
1011 	/*<3> Rx related */
1012 	if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
1013 		rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
1014 		_rtl_pci_rx_interrupt(hw);
1015 	}
1016 
1017 	if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1018 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1019 			"rx descriptor unavailable!\n");
1020 		_rtl_pci_rx_interrupt(hw);
1021 	}
1022 
1023 	if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
1024 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
1025 		_rtl_pci_rx_interrupt(hw);
1026 	}
1027 
1028 	/*<4> fw related*/
1029 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
1030 		if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
1031 			rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
1032 				"firmware interrupt!\n");
1033 			queue_delayed_work(rtlpriv->works.rtl_wq,
1034 					   &rtlpriv->works.fwevt_wq, 0);
1035 		}
1036 	}
1037 
1038 	/*<5> hsisr related*/
1039 	/* Only 8188EE & 8723BE Supported.
1040 	 * If Other ICs Come in, System will corrupt,
1041 	 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
1042 	 * are not initialized
1043 	 */
1044 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1045 	    rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1046 		if (unlikely(intvec.inta &
1047 		    rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1048 			rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
1049 				"hsisr interrupt!\n");
1050 			_rtl_pci_hs_interrupt(hw);
1051 		}
1052 	}
1053 
1054 	if (rtlpriv->rtlhal.earlymode_enable)
1055 		tasklet_schedule(&rtlpriv->works.irq_tasklet);
1056 
1057 done:
1058 	rtlpriv->cfg->ops->enable_interrupt(hw);
1059 	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1060 	return ret;
1061 }
1062 
1063 static void _rtl_pci_irq_tasklet(struct tasklet_struct *t)
1064 {
1065 	struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, works.irq_tasklet);
1066 	struct ieee80211_hw *hw = rtlpriv->hw;
1067 	_rtl_pci_tx_chk_waitq(hw);
1068 }
1069 
1070 static void _rtl_pci_prepare_bcn_tasklet(struct tasklet_struct *t)
1071 {
1072 	struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t,
1073 						works.irq_prepare_bcn_tasklet);
1074 	struct ieee80211_hw *hw = rtlpriv->hw;
1075 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1076 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1077 	struct rtl8192_tx_ring *ring = NULL;
1078 	struct ieee80211_hdr *hdr = NULL;
1079 	struct ieee80211_tx_info *info = NULL;
1080 	struct sk_buff *pskb = NULL;
1081 	struct rtl_tx_desc *pdesc = NULL;
1082 	struct rtl_tcb_desc tcb_desc;
1083 	/*This is for new trx flow*/
1084 	struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1085 	u8 temp_one = 1;
1086 	u8 *entry;
1087 
1088 	memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1089 	ring = &rtlpci->tx_ring[BEACON_QUEUE];
1090 	pskb = __skb_dequeue(&ring->queue);
1091 	if (rtlpriv->use_new_trx_flow)
1092 		entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1093 	else
1094 		entry = (u8 *)(&ring->desc[ring->idx]);
1095 	if (pskb) {
1096 		dma_unmap_single(&rtlpci->pdev->dev,
1097 				 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1098 						true, HW_DESC_TXBUFF_ADDR),
1099 				 pskb->len, DMA_TO_DEVICE);
1100 		kfree_skb(pskb);
1101 	}
1102 
1103 	/*NB: the beacon data buffer must be 32-bit aligned. */
1104 	pskb = ieee80211_beacon_get(hw, mac->vif);
1105 	if (!pskb)
1106 		return;
1107 	hdr = rtl_get_hdr(pskb);
1108 	info = IEEE80211_SKB_CB(pskb);
1109 	pdesc = &ring->desc[0];
1110 	if (rtlpriv->use_new_trx_flow)
1111 		pbuffer_desc = &ring->buffer_desc[0];
1112 
1113 	rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1114 					(u8 *)pbuffer_desc, info, NULL, pskb,
1115 					BEACON_QUEUE, &tcb_desc);
1116 
1117 	__skb_queue_tail(&ring->queue, pskb);
1118 
1119 	if (rtlpriv->use_new_trx_flow) {
1120 		temp_one = 4;
1121 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1122 					    HW_DESC_OWN, (u8 *)&temp_one);
1123 	} else {
1124 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1125 					    &temp_one);
1126 	}
1127 }
1128 
1129 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1130 {
1131 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1132 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1133 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1134 	u8 i;
1135 	u16 desc_num;
1136 
1137 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1138 		desc_num = TX_DESC_NUM_92E;
1139 	else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE)
1140 		desc_num = TX_DESC_NUM_8822B;
1141 	else
1142 		desc_num = RT_TXDESC_NUM;
1143 
1144 	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1145 		rtlpci->txringcount[i] = desc_num;
1146 
1147 	/*we just alloc 2 desc for beacon queue,
1148 	 *because we just need first desc in hw beacon.
1149 	 */
1150 	rtlpci->txringcount[BEACON_QUEUE] = 2;
1151 
1152 	/*BE queue need more descriptor for performance
1153 	 *consideration or, No more tx desc will happen,
1154 	 *and may cause mac80211 mem leakage.
1155 	 */
1156 	if (!rtl_priv(hw)->use_new_trx_flow)
1157 		rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1158 
1159 	rtlpci->rxbuffersize = 9100;	/*2048/1024; */
1160 	rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT;	/*64; */
1161 }
1162 
1163 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1164 				 struct pci_dev *pdev)
1165 {
1166 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1167 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1168 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1169 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1170 
1171 	rtlpci->up_first_time = true;
1172 	rtlpci->being_init_adapter = false;
1173 
1174 	rtlhal->hw = hw;
1175 	rtlpci->pdev = pdev;
1176 
1177 	/*Tx/Rx related var */
1178 	_rtl_pci_init_trx_var(hw);
1179 
1180 	/*IBSS*/
1181 	mac->beacon_interval = 100;
1182 
1183 	/*AMPDU*/
1184 	mac->min_space_cfg = 0;
1185 	mac->max_mss_density = 0;
1186 	/*set sane AMPDU defaults */
1187 	mac->current_ampdu_density = 7;
1188 	mac->current_ampdu_factor = 3;
1189 
1190 	/*Retry Limit*/
1191 	mac->retry_short = 7;
1192 	mac->retry_long = 7;
1193 
1194 	/*QOS*/
1195 	rtlpci->acm_method = EACMWAY2_SW;
1196 
1197 	/*task */
1198 	tasklet_setup(&rtlpriv->works.irq_tasklet, _rtl_pci_irq_tasklet);
1199 	tasklet_setup(&rtlpriv->works.irq_prepare_bcn_tasklet,
1200 		     _rtl_pci_prepare_bcn_tasklet);
1201 	INIT_WORK(&rtlpriv->works.lps_change_work,
1202 		  rtl_lps_change_work_callback);
1203 }
1204 
1205 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1206 				 unsigned int prio, unsigned int entries)
1207 {
1208 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1209 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1210 	struct rtl_tx_buffer_desc *buffer_desc;
1211 	struct rtl_tx_desc *desc;
1212 	dma_addr_t buffer_desc_dma, desc_dma;
1213 	u32 nextdescaddress;
1214 	int i;
1215 
1216 	/* alloc tx buffer desc for new trx flow*/
1217 	if (rtlpriv->use_new_trx_flow) {
1218 		buffer_desc =
1219 		   dma_alloc_coherent(&rtlpci->pdev->dev,
1220 				      sizeof(*buffer_desc) * entries,
1221 				      &buffer_desc_dma, GFP_KERNEL);
1222 
1223 		if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1224 			pr_err("Cannot allocate TX ring (prio = %d)\n",
1225 			       prio);
1226 			return -ENOMEM;
1227 		}
1228 
1229 		rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1230 		rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1231 
1232 		rtlpci->tx_ring[prio].cur_tx_rp = 0;
1233 		rtlpci->tx_ring[prio].cur_tx_wp = 0;
1234 	}
1235 
1236 	/* alloc dma for this ring */
1237 	desc = dma_alloc_coherent(&rtlpci->pdev->dev, sizeof(*desc) * entries,
1238 				  &desc_dma, GFP_KERNEL);
1239 
1240 	if (!desc || (unsigned long)desc & 0xFF) {
1241 		pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
1242 		return -ENOMEM;
1243 	}
1244 
1245 	rtlpci->tx_ring[prio].desc = desc;
1246 	rtlpci->tx_ring[prio].dma = desc_dma;
1247 
1248 	rtlpci->tx_ring[prio].idx = 0;
1249 	rtlpci->tx_ring[prio].entries = entries;
1250 	skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1251 
1252 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1253 		prio, desc);
1254 
1255 	/* init every desc in this ring */
1256 	if (!rtlpriv->use_new_trx_flow) {
1257 		for (i = 0; i < entries; i++) {
1258 			nextdescaddress = (u32)desc_dma +
1259 					  ((i +	1) % entries) *
1260 					  sizeof(*desc);
1261 
1262 			rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1263 						    true,
1264 						    HW_DESC_TX_NEXTDESC_ADDR,
1265 						    (u8 *)&nextdescaddress);
1266 		}
1267 	}
1268 	return 0;
1269 }
1270 
1271 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1272 {
1273 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1274 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1275 	int i;
1276 
1277 	if (rtlpriv->use_new_trx_flow) {
1278 		struct rtl_rx_buffer_desc *entry = NULL;
1279 		/* alloc dma for this ring */
1280 		rtlpci->rx_ring[rxring_idx].buffer_desc =
1281 		    dma_alloc_coherent(&rtlpci->pdev->dev,
1282 				       sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1283 				       rtlpci->rxringcount,
1284 				       &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
1285 		if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1286 		    (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1287 			pr_err("Cannot allocate RX ring\n");
1288 			return -ENOMEM;
1289 		}
1290 
1291 		/* init every desc in this ring */
1292 		rtlpci->rx_ring[rxring_idx].idx = 0;
1293 		for (i = 0; i < rtlpci->rxringcount; i++) {
1294 			entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1295 			if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1296 						      rxring_idx, i))
1297 				return -ENOMEM;
1298 		}
1299 	} else {
1300 		struct rtl_rx_desc *entry = NULL;
1301 		u8 tmp_one = 1;
1302 		/* alloc dma for this ring */
1303 		rtlpci->rx_ring[rxring_idx].desc =
1304 		    dma_alloc_coherent(&rtlpci->pdev->dev,
1305 				       sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1306 				       rtlpci->rxringcount,
1307 				       &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
1308 		if (!rtlpci->rx_ring[rxring_idx].desc ||
1309 		    (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1310 			pr_err("Cannot allocate RX ring\n");
1311 			return -ENOMEM;
1312 		}
1313 
1314 		/* init every desc in this ring */
1315 		rtlpci->rx_ring[rxring_idx].idx = 0;
1316 
1317 		for (i = 0; i < rtlpci->rxringcount; i++) {
1318 			entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1319 			if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1320 						      rxring_idx, i))
1321 				return -ENOMEM;
1322 		}
1323 
1324 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1325 					    HW_DESC_RXERO, &tmp_one);
1326 	}
1327 	return 0;
1328 }
1329 
1330 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1331 				  unsigned int prio)
1332 {
1333 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1334 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1335 	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1336 
1337 	/* free every desc in this ring */
1338 	while (skb_queue_len(&ring->queue)) {
1339 		u8 *entry;
1340 		struct sk_buff *skb = __skb_dequeue(&ring->queue);
1341 
1342 		if (rtlpriv->use_new_trx_flow)
1343 			entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1344 		else
1345 			entry = (u8 *)(&ring->desc[ring->idx]);
1346 
1347 		dma_unmap_single(&rtlpci->pdev->dev,
1348 				 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1349 						true, HW_DESC_TXBUFF_ADDR),
1350 				 skb->len, DMA_TO_DEVICE);
1351 		kfree_skb(skb);
1352 		ring->idx = (ring->idx + 1) % ring->entries;
1353 	}
1354 
1355 	/* free dma of this ring */
1356 	dma_free_coherent(&rtlpci->pdev->dev,
1357 			  sizeof(*ring->desc) * ring->entries, ring->desc,
1358 			  ring->dma);
1359 	ring->desc = NULL;
1360 	if (rtlpriv->use_new_trx_flow) {
1361 		dma_free_coherent(&rtlpci->pdev->dev,
1362 				  sizeof(*ring->buffer_desc) * ring->entries,
1363 				  ring->buffer_desc, ring->buffer_desc_dma);
1364 		ring->buffer_desc = NULL;
1365 	}
1366 }
1367 
1368 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1369 {
1370 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1371 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1372 	int i;
1373 
1374 	/* free every desc in this ring */
1375 	for (i = 0; i < rtlpci->rxringcount; i++) {
1376 		struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1377 
1378 		if (!skb)
1379 			continue;
1380 		dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
1381 				 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
1382 		kfree_skb(skb);
1383 	}
1384 
1385 	/* free dma of this ring */
1386 	if (rtlpriv->use_new_trx_flow) {
1387 		dma_free_coherent(&rtlpci->pdev->dev,
1388 				  sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1389 				  rtlpci->rxringcount,
1390 				  rtlpci->rx_ring[rxring_idx].buffer_desc,
1391 				  rtlpci->rx_ring[rxring_idx].dma);
1392 		rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1393 	} else {
1394 		dma_free_coherent(&rtlpci->pdev->dev,
1395 				  sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1396 				  rtlpci->rxringcount,
1397 				  rtlpci->rx_ring[rxring_idx].desc,
1398 				  rtlpci->rx_ring[rxring_idx].dma);
1399 		rtlpci->rx_ring[rxring_idx].desc = NULL;
1400 	}
1401 }
1402 
1403 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1404 {
1405 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1406 	int ret;
1407 	int i, rxring_idx;
1408 
1409 	/* rxring_idx 0:RX_MPDU_QUEUE
1410 	 * rxring_idx 1:RX_CMD_QUEUE
1411 	 */
1412 	for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1413 		ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1414 		if (ret)
1415 			return ret;
1416 	}
1417 
1418 	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1419 		ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
1420 		if (ret)
1421 			goto err_free_rings;
1422 	}
1423 
1424 	return 0;
1425 
1426 err_free_rings:
1427 	for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1428 		_rtl_pci_free_rx_ring(hw, rxring_idx);
1429 
1430 	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1431 		if (rtlpci->tx_ring[i].desc ||
1432 		    rtlpci->tx_ring[i].buffer_desc)
1433 			_rtl_pci_free_tx_ring(hw, i);
1434 
1435 	return 1;
1436 }
1437 
1438 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1439 {
1440 	u32 i, rxring_idx;
1441 
1442 	/*free rx rings */
1443 	for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1444 		_rtl_pci_free_rx_ring(hw, rxring_idx);
1445 
1446 	/*free tx rings */
1447 	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1448 		_rtl_pci_free_tx_ring(hw, i);
1449 
1450 	return 0;
1451 }
1452 
1453 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1454 {
1455 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1456 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1457 	int i, rxring_idx;
1458 	unsigned long flags;
1459 	u8 tmp_one = 1;
1460 	u32 bufferaddress;
1461 	/* rxring_idx 0:RX_MPDU_QUEUE */
1462 	/* rxring_idx 1:RX_CMD_QUEUE */
1463 	for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1464 		/* force the rx_ring[RX_MPDU_QUEUE/
1465 		 * RX_CMD_QUEUE].idx to the first one
1466 		 *new trx flow, do nothing
1467 		 */
1468 		if (!rtlpriv->use_new_trx_flow &&
1469 		    rtlpci->rx_ring[rxring_idx].desc) {
1470 			struct rtl_rx_desc *entry = NULL;
1471 
1472 			rtlpci->rx_ring[rxring_idx].idx = 0;
1473 			for (i = 0; i < rtlpci->rxringcount; i++) {
1474 				entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1475 				bufferaddress =
1476 				  rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1477 				  false, HW_DESC_RXBUFF_ADDR);
1478 				memset((u8 *)entry, 0,
1479 				       sizeof(*rtlpci->rx_ring
1480 				       [rxring_idx].desc));/*clear one entry*/
1481 				if (rtlpriv->use_new_trx_flow) {
1482 					rtlpriv->cfg->ops->set_desc(hw,
1483 					    (u8 *)entry, false,
1484 					    HW_DESC_RX_PREPARE,
1485 					    (u8 *)&bufferaddress);
1486 				} else {
1487 					rtlpriv->cfg->ops->set_desc(hw,
1488 					    (u8 *)entry, false,
1489 					    HW_DESC_RXBUFF_ADDR,
1490 					    (u8 *)&bufferaddress);
1491 					rtlpriv->cfg->ops->set_desc(hw,
1492 					    (u8 *)entry, false,
1493 					    HW_DESC_RXPKT_LEN,
1494 					    (u8 *)&rtlpci->rxbuffersize);
1495 					rtlpriv->cfg->ops->set_desc(hw,
1496 					    (u8 *)entry, false,
1497 					    HW_DESC_RXOWN,
1498 					    (u8 *)&tmp_one);
1499 				}
1500 			}
1501 			rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1502 					    HW_DESC_RXERO, (u8 *)&tmp_one);
1503 		}
1504 		rtlpci->rx_ring[rxring_idx].idx = 0;
1505 	}
1506 
1507 	/*after reset, release previous pending packet,
1508 	 *and force the  tx idx to the first one
1509 	 */
1510 	spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1511 	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1512 		if (rtlpci->tx_ring[i].desc ||
1513 		    rtlpci->tx_ring[i].buffer_desc) {
1514 			struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1515 
1516 			while (skb_queue_len(&ring->queue)) {
1517 				u8 *entry;
1518 				struct sk_buff *skb =
1519 					__skb_dequeue(&ring->queue);
1520 				if (rtlpriv->use_new_trx_flow)
1521 					entry = (u8 *)(&ring->buffer_desc
1522 								[ring->idx]);
1523 				else
1524 					entry = (u8 *)(&ring->desc[ring->idx]);
1525 
1526 				dma_unmap_single(&rtlpci->pdev->dev,
1527 						 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1528 								true, HW_DESC_TXBUFF_ADDR),
1529 						 skb->len, DMA_TO_DEVICE);
1530 				dev_kfree_skb_irq(skb);
1531 				ring->idx = (ring->idx + 1) % ring->entries;
1532 			}
1533 
1534 			if (rtlpriv->use_new_trx_flow) {
1535 				rtlpci->tx_ring[i].cur_tx_rp = 0;
1536 				rtlpci->tx_ring[i].cur_tx_wp = 0;
1537 			}
1538 
1539 			ring->idx = 0;
1540 			ring->entries = rtlpci->txringcount[i];
1541 		}
1542 	}
1543 	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1544 
1545 	return 0;
1546 }
1547 
1548 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1549 					struct ieee80211_sta *sta,
1550 					struct sk_buff *skb)
1551 {
1552 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1553 	struct rtl_sta_info *sta_entry = NULL;
1554 	u8 tid = rtl_get_tid(skb);
1555 	__le16 fc = rtl_get_fc(skb);
1556 
1557 	if (!sta)
1558 		return false;
1559 	sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1560 
1561 	if (!rtlpriv->rtlhal.earlymode_enable)
1562 		return false;
1563 	if (ieee80211_is_nullfunc(fc))
1564 		return false;
1565 	if (ieee80211_is_qos_nullfunc(fc))
1566 		return false;
1567 	if (ieee80211_is_pspoll(fc))
1568 		return false;
1569 	if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1570 		return false;
1571 	if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1572 		return false;
1573 	if (tid > 7)
1574 		return false;
1575 
1576 	/* maybe every tid should be checked */
1577 	if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1578 		return false;
1579 
1580 	spin_lock_bh(&rtlpriv->locks.waitq_lock);
1581 	skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1582 	spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1583 
1584 	return true;
1585 }
1586 
1587 static int rtl_pci_tx(struct ieee80211_hw *hw,
1588 		      struct ieee80211_sta *sta,
1589 		      struct sk_buff *skb,
1590 		      struct rtl_tcb_desc *ptcb_desc)
1591 {
1592 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1593 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1594 	struct rtl8192_tx_ring *ring;
1595 	struct rtl_tx_desc *pdesc;
1596 	struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1597 	u16 idx;
1598 	u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1599 	unsigned long flags;
1600 	struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1601 	__le16 fc = rtl_get_fc(skb);
1602 	u8 *pda_addr = hdr->addr1;
1603 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1604 	u8 own;
1605 	u8 temp_one = 1;
1606 
1607 	if (ieee80211_is_mgmt(fc))
1608 		rtl_tx_mgmt_proc(hw, skb);
1609 
1610 	if (rtlpriv->psc.sw_ps_enabled) {
1611 		if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1612 		    !ieee80211_has_pm(fc))
1613 			hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1614 	}
1615 
1616 	rtl_action_proc(hw, skb, true);
1617 
1618 	if (is_multicast_ether_addr(pda_addr))
1619 		rtlpriv->stats.txbytesmulticast += skb->len;
1620 	else if (is_broadcast_ether_addr(pda_addr))
1621 		rtlpriv->stats.txbytesbroadcast += skb->len;
1622 	else
1623 		rtlpriv->stats.txbytesunicast += skb->len;
1624 
1625 	spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1626 	ring = &rtlpci->tx_ring[hw_queue];
1627 	if (hw_queue != BEACON_QUEUE) {
1628 		if (rtlpriv->use_new_trx_flow)
1629 			idx = ring->cur_tx_wp;
1630 		else
1631 			idx = (ring->idx + skb_queue_len(&ring->queue)) %
1632 			      ring->entries;
1633 	} else {
1634 		idx = 0;
1635 	}
1636 
1637 	pdesc = &ring->desc[idx];
1638 	if (rtlpriv->use_new_trx_flow) {
1639 		ptx_bd_desc = &ring->buffer_desc[idx];
1640 	} else {
1641 		own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
1642 				true, HW_DESC_OWN);
1643 
1644 		if (own == 1 && hw_queue != BEACON_QUEUE) {
1645 			rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1646 				"No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1647 				hw_queue, ring->idx, idx,
1648 				skb_queue_len(&ring->queue));
1649 
1650 			spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1651 					       flags);
1652 			return skb->len;
1653 		}
1654 	}
1655 
1656 	if (rtlpriv->cfg->ops->get_available_desc &&
1657 	    rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1658 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1659 			"get_available_desc fail\n");
1660 		spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1661 		return skb->len;
1662 	}
1663 
1664 	if (ieee80211_is_data(fc))
1665 		rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1666 
1667 	rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1668 			(u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1669 
1670 	__skb_queue_tail(&ring->queue, skb);
1671 
1672 	if (rtlpriv->use_new_trx_flow) {
1673 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1674 					    HW_DESC_OWN, &hw_queue);
1675 	} else {
1676 		rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1677 					    HW_DESC_OWN, &temp_one);
1678 	}
1679 
1680 	if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1681 	    hw_queue != BEACON_QUEUE) {
1682 		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1683 			"less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1684 			 hw_queue, ring->idx, idx,
1685 			 skb_queue_len(&ring->queue));
1686 
1687 		ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1688 	}
1689 
1690 	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1691 
1692 	rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1693 
1694 	return 0;
1695 }
1696 
1697 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1698 {
1699 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1700 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1701 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1702 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1703 	u16 i = 0;
1704 	int queue_id;
1705 	struct rtl8192_tx_ring *ring;
1706 
1707 	if (mac->skip_scan)
1708 		return;
1709 
1710 	for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1711 		u32 queue_len;
1712 
1713 		if (((queues >> queue_id) & 0x1) == 0) {
1714 			queue_id--;
1715 			continue;
1716 		}
1717 		ring = &pcipriv->dev.tx_ring[queue_id];
1718 		queue_len = skb_queue_len(&ring->queue);
1719 		if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1720 		    queue_id == TXCMD_QUEUE) {
1721 			queue_id--;
1722 			continue;
1723 		} else {
1724 			msleep(20);
1725 			i++;
1726 		}
1727 
1728 		/* we just wait 1s for all queues */
1729 		if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1730 		    is_hal_stop(rtlhal) || i >= 200)
1731 			return;
1732 	}
1733 }
1734 
1735 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1736 {
1737 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1738 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1739 
1740 	_rtl_pci_deinit_trx_ring(hw);
1741 
1742 	synchronize_irq(rtlpci->pdev->irq);
1743 	tasklet_kill(&rtlpriv->works.irq_tasklet);
1744 	cancel_work_sync(&rtlpriv->works.lps_change_work);
1745 
1746 	flush_workqueue(rtlpriv->works.rtl_wq);
1747 	destroy_workqueue(rtlpriv->works.rtl_wq);
1748 }
1749 
1750 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1751 {
1752 	int err;
1753 
1754 	_rtl_pci_init_struct(hw, pdev);
1755 
1756 	err = _rtl_pci_init_trx_ring(hw);
1757 	if (err) {
1758 		pr_err("tx ring initialization failed\n");
1759 		return err;
1760 	}
1761 
1762 	return 0;
1763 }
1764 
1765 static int rtl_pci_start(struct ieee80211_hw *hw)
1766 {
1767 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1768 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1769 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1770 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1771 	struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
1772 	struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
1773 
1774 	int err;
1775 
1776 	rtl_pci_reset_trx_ring(hw);
1777 
1778 	rtlpci->driver_is_goingto_unload = false;
1779 	if (rtlpriv->cfg->ops->get_btc_status &&
1780 	    rtlpriv->cfg->ops->get_btc_status()) {
1781 		rtlpriv->btcoexist.btc_info.ap_num = 36;
1782 		btc_ops->btc_init_variables(rtlpriv);
1783 		btc_ops->btc_init_hal_vars(rtlpriv);
1784 	} else if (btc_ops) {
1785 		btc_ops->btc_init_variables_wifi_only(rtlpriv);
1786 	}
1787 
1788 	err = rtlpriv->cfg->ops->hw_init(hw);
1789 	if (err) {
1790 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1791 			"Failed to config hardware!\n");
1792 		kfree(rtlpriv->btcoexist.btc_context);
1793 		kfree(rtlpriv->btcoexist.wifi_only_context);
1794 		return err;
1795 	}
1796 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1797 			&rtlmac->retry_long);
1798 
1799 	rtlpriv->cfg->ops->enable_interrupt(hw);
1800 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1801 
1802 	rtl_init_rx_config(hw);
1803 
1804 	/*should be after adapter start and interrupt enable. */
1805 	set_hal_start(rtlhal);
1806 
1807 	RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1808 
1809 	rtlpci->up_first_time = false;
1810 
1811 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
1812 	return 0;
1813 }
1814 
1815 static void rtl_pci_stop(struct ieee80211_hw *hw)
1816 {
1817 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1818 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1819 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1820 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1821 	unsigned long flags;
1822 	u8 rf_timeout = 0;
1823 
1824 	if (rtlpriv->cfg->ops->get_btc_status())
1825 		rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv);
1826 
1827 	if (rtlpriv->btcoexist.btc_ops)
1828 		rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv);
1829 
1830 	/*should be before disable interrupt&adapter
1831 	 *and will do it immediately.
1832 	 */
1833 	set_hal_stop(rtlhal);
1834 
1835 	rtlpci->driver_is_goingto_unload = true;
1836 	rtlpriv->cfg->ops->disable_interrupt(hw);
1837 	cancel_work_sync(&rtlpriv->works.lps_change_work);
1838 
1839 	spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1840 	while (ppsc->rfchange_inprogress) {
1841 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1842 		if (rf_timeout > 100) {
1843 			spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1844 			break;
1845 		}
1846 		mdelay(1);
1847 		rf_timeout++;
1848 		spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1849 	}
1850 	ppsc->rfchange_inprogress = true;
1851 	spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1852 
1853 	rtlpriv->cfg->ops->hw_disable(hw);
1854 	/* some things are not needed if firmware not available */
1855 	if (!rtlpriv->max_fw_size)
1856 		return;
1857 	rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1858 
1859 	spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1860 	ppsc->rfchange_inprogress = false;
1861 	spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1862 
1863 	rtl_pci_enable_aspm(hw);
1864 }
1865 
1866 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1867 				  struct ieee80211_hw *hw)
1868 {
1869 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1870 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1871 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1872 	struct pci_dev *bridge_pdev = pdev->bus->self;
1873 	u16 venderid;
1874 	u16 deviceid;
1875 	u8 revisionid;
1876 	u16 irqline;
1877 	u8 tmp;
1878 
1879 	pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1880 	venderid = pdev->vendor;
1881 	deviceid = pdev->device;
1882 	pci_read_config_byte(pdev, 0x8, &revisionid);
1883 	pci_read_config_word(pdev, 0x3C, &irqline);
1884 
1885 	/* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1886 	 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1887 	 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1888 	 * the correct driver is r8192e_pci, thus this routine should
1889 	 * return false.
1890 	 */
1891 	if (deviceid == RTL_PCI_8192SE_DID &&
1892 	    revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1893 		return false;
1894 
1895 	if (deviceid == RTL_PCI_8192_DID ||
1896 	    deviceid == RTL_PCI_0044_DID ||
1897 	    deviceid == RTL_PCI_0047_DID ||
1898 	    deviceid == RTL_PCI_8192SE_DID ||
1899 	    deviceid == RTL_PCI_8174_DID ||
1900 	    deviceid == RTL_PCI_8173_DID ||
1901 	    deviceid == RTL_PCI_8172_DID ||
1902 	    deviceid == RTL_PCI_8171_DID) {
1903 		switch (revisionid) {
1904 		case RTL_PCI_REVISION_ID_8192PCIE:
1905 			rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1906 				"8192 PCI-E is found - vid/did=%x/%x\n",
1907 				venderid, deviceid);
1908 			rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1909 			return false;
1910 		case RTL_PCI_REVISION_ID_8192SE:
1911 			rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1912 				"8192SE is found - vid/did=%x/%x\n",
1913 				venderid, deviceid);
1914 			rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1915 			break;
1916 		default:
1917 			rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1918 				"Err: Unknown device - vid/did=%x/%x\n",
1919 				venderid, deviceid);
1920 			rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1921 			break;
1922 		}
1923 	} else if (deviceid == RTL_PCI_8723AE_DID) {
1924 		rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1925 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1926 			"8723AE PCI-E is found - vid/did=%x/%x\n",
1927 			venderid, deviceid);
1928 	} else if (deviceid == RTL_PCI_8192CET_DID ||
1929 		   deviceid == RTL_PCI_8192CE_DID ||
1930 		   deviceid == RTL_PCI_8191CE_DID ||
1931 		   deviceid == RTL_PCI_8188CE_DID) {
1932 		rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1933 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1934 			"8192C PCI-E is found - vid/did=%x/%x\n",
1935 			venderid, deviceid);
1936 	} else if (deviceid == RTL_PCI_8192DE_DID ||
1937 		   deviceid == RTL_PCI_8192DE_DID2) {
1938 		rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1939 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1940 			"8192D PCI-E is found - vid/did=%x/%x\n",
1941 			venderid, deviceid);
1942 	} else if (deviceid == RTL_PCI_8188EE_DID) {
1943 		rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1944 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1945 			"Find adapter, Hardware type is 8188EE\n");
1946 	} else if (deviceid == RTL_PCI_8723BE_DID) {
1947 		rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1948 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1949 			"Find adapter, Hardware type is 8723BE\n");
1950 	} else if (deviceid == RTL_PCI_8192EE_DID) {
1951 		rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
1952 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1953 			"Find adapter, Hardware type is 8192EE\n");
1954 	} else if (deviceid == RTL_PCI_8821AE_DID) {
1955 		rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
1956 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1957 			"Find adapter, Hardware type is 8821AE\n");
1958 	} else if (deviceid == RTL_PCI_8812AE_DID) {
1959 		rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
1960 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1961 			"Find adapter, Hardware type is 8812AE\n");
1962 	} else if (deviceid == RTL_PCI_8822BE_DID) {
1963 		rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE;
1964 		rtlhal->bandset = BAND_ON_BOTH;
1965 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1966 			"Find adapter, Hardware type is 8822BE\n");
1967 	} else {
1968 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1969 			"Err: Unknown device - vid/did=%x/%x\n",
1970 			 venderid, deviceid);
1971 
1972 		rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1973 	}
1974 
1975 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1976 		if (revisionid == 0 || revisionid == 1) {
1977 			if (revisionid == 0) {
1978 				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1979 					"Find 92DE MAC0\n");
1980 				rtlhal->interfaceindex = 0;
1981 			} else if (revisionid == 1) {
1982 				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1983 					"Find 92DE MAC1\n");
1984 				rtlhal->interfaceindex = 1;
1985 			}
1986 		} else {
1987 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1988 				"Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1989 				 venderid, deviceid, revisionid);
1990 			rtlhal->interfaceindex = 0;
1991 		}
1992 	}
1993 
1994 	switch (rtlhal->hw_type) {
1995 	case HARDWARE_TYPE_RTL8192EE:
1996 	case HARDWARE_TYPE_RTL8822BE:
1997 		/* use new trx flow */
1998 		rtlpriv->use_new_trx_flow = true;
1999 		break;
2000 
2001 	default:
2002 		rtlpriv->use_new_trx_flow = false;
2003 		break;
2004 	}
2005 
2006 	/*find bus info */
2007 	pcipriv->ndis_adapter.busnumber = pdev->bus->number;
2008 	pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
2009 	pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
2010 
2011 	/*find bridge info */
2012 	pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
2013 	/* some ARM have no bridge_pdev and will crash here
2014 	 * so we should check if bridge_pdev is NULL
2015 	 */
2016 	if (bridge_pdev) {
2017 		/*find bridge info if available */
2018 		pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
2019 		for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
2020 			if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
2021 				pcipriv->ndis_adapter.pcibridge_vendor = tmp;
2022 				rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2023 					"Pci Bridge Vendor is found index: %d\n",
2024 					tmp);
2025 				break;
2026 			}
2027 		}
2028 	}
2029 
2030 	if (pcipriv->ndis_adapter.pcibridge_vendor !=
2031 		PCI_BRIDGE_VENDOR_UNKNOWN) {
2032 		pcipriv->ndis_adapter.pcibridge_busnum =
2033 		    bridge_pdev->bus->number;
2034 		pcipriv->ndis_adapter.pcibridge_devnum =
2035 		    PCI_SLOT(bridge_pdev->devfn);
2036 		pcipriv->ndis_adapter.pcibridge_funcnum =
2037 		    PCI_FUNC(bridge_pdev->devfn);
2038 		pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2039 		    pci_pcie_cap(bridge_pdev);
2040 		pcipriv->ndis_adapter.num4bytes =
2041 		    (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
2042 
2043 		rtl_pci_get_linkcontrol_field(hw);
2044 
2045 		if (pcipriv->ndis_adapter.pcibridge_vendor ==
2046 		    PCI_BRIDGE_VENDOR_AMD) {
2047 			pcipriv->ndis_adapter.amd_l1_patch =
2048 			    rtl_pci_get_amd_l1_patch(hw);
2049 		}
2050 	}
2051 
2052 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2053 		"pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2054 		pcipriv->ndis_adapter.busnumber,
2055 		pcipriv->ndis_adapter.devnumber,
2056 		pcipriv->ndis_adapter.funcnumber,
2057 		pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
2058 
2059 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2060 		"pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2061 		pcipriv->ndis_adapter.pcibridge_busnum,
2062 		pcipriv->ndis_adapter.pcibridge_devnum,
2063 		pcipriv->ndis_adapter.pcibridge_funcnum,
2064 		pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2065 		pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2066 		pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2067 		pcipriv->ndis_adapter.amd_l1_patch);
2068 
2069 	rtl_pci_parse_configuration(pdev, hw);
2070 	list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2071 
2072 	return true;
2073 }
2074 
2075 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2076 {
2077 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2078 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2079 	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2080 	int ret;
2081 
2082 	ret = pci_enable_msi(rtlpci->pdev);
2083 	if (ret < 0)
2084 		return ret;
2085 
2086 	ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2087 			  IRQF_SHARED, KBUILD_MODNAME, hw);
2088 	if (ret < 0) {
2089 		pci_disable_msi(rtlpci->pdev);
2090 		return ret;
2091 	}
2092 
2093 	rtlpci->using_msi = true;
2094 
2095 	rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2096 		"MSI Interrupt Mode!\n");
2097 	return 0;
2098 }
2099 
2100 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2101 {
2102 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2103 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2104 	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2105 	int ret;
2106 
2107 	ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2108 			  IRQF_SHARED, KBUILD_MODNAME, hw);
2109 	if (ret < 0)
2110 		return ret;
2111 
2112 	rtlpci->using_msi = false;
2113 	rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2114 		"Pin-based Interrupt Mode!\n");
2115 	return 0;
2116 }
2117 
2118 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2119 {
2120 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2121 	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2122 	int ret;
2123 
2124 	if (rtlpci->msi_support) {
2125 		ret = rtl_pci_intr_mode_msi(hw);
2126 		if (ret < 0)
2127 			ret = rtl_pci_intr_mode_legacy(hw);
2128 	} else {
2129 		ret = rtl_pci_intr_mode_legacy(hw);
2130 	}
2131 	return ret;
2132 }
2133 
2134 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
2135 {
2136 	u8	value;
2137 
2138 	pci_read_config_byte(pdev, 0x719, &value);
2139 
2140 	/* 0x719 Bit5 is DMA64 bit fetch. */
2141 	if (dma64)
2142 		value |= BIT(5);
2143 	else
2144 		value &= ~BIT(5);
2145 
2146 	pci_write_config_byte(pdev, 0x719, value);
2147 }
2148 
2149 int rtl_pci_probe(struct pci_dev *pdev,
2150 		  const struct pci_device_id *id)
2151 {
2152 	struct ieee80211_hw *hw = NULL;
2153 
2154 	struct rtl_priv *rtlpriv = NULL;
2155 	struct rtl_pci_priv *pcipriv = NULL;
2156 	struct rtl_pci *rtlpci;
2157 	unsigned long pmem_start, pmem_len, pmem_flags;
2158 	int err;
2159 
2160 	err = pci_enable_device(pdev);
2161 	if (err) {
2162 		WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
2163 			  pci_name(pdev));
2164 		return err;
2165 	}
2166 
2167 	if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 &&
2168 	    !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2169 		if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2170 			WARN_ONCE(true,
2171 				  "Unable to obtain 64bit DMA for consistent allocations\n");
2172 			err = -ENOMEM;
2173 			goto fail1;
2174 		}
2175 
2176 		platform_enable_dma64(pdev, true);
2177 	} else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
2178 		if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
2179 			WARN_ONCE(true,
2180 				  "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
2181 			err = -ENOMEM;
2182 			goto fail1;
2183 		}
2184 
2185 		platform_enable_dma64(pdev, false);
2186 	}
2187 
2188 	pci_set_master(pdev);
2189 
2190 	hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2191 				sizeof(struct rtl_priv), &rtl_ops);
2192 	if (!hw) {
2193 		WARN_ONCE(true,
2194 			  "%s : ieee80211 alloc failed\n", pci_name(pdev));
2195 		err = -ENOMEM;
2196 		goto fail1;
2197 	}
2198 
2199 	SET_IEEE80211_DEV(hw, &pdev->dev);
2200 	pci_set_drvdata(pdev, hw);
2201 
2202 	rtlpriv = hw->priv;
2203 	rtlpriv->hw = hw;
2204 	pcipriv = (void *)rtlpriv->priv;
2205 	pcipriv->dev.pdev = pdev;
2206 	init_completion(&rtlpriv->firmware_loading_complete);
2207 	/*proximity init here*/
2208 	rtlpriv->proximity.proxim_on = false;
2209 
2210 	pcipriv = (void *)rtlpriv->priv;
2211 	pcipriv->dev.pdev = pdev;
2212 
2213 	/* init cfg & intf_ops */
2214 	rtlpriv->rtlhal.interface = INTF_PCI;
2215 	rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2216 	rtlpriv->intf_ops = &rtl_pci_ops;
2217 	rtlpriv->glb_var = &rtl_global_var;
2218 	rtl_efuse_ops_init(hw);
2219 
2220 	/* MEM map */
2221 	err = pci_request_regions(pdev, KBUILD_MODNAME);
2222 	if (err) {
2223 		WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
2224 		goto fail1;
2225 	}
2226 
2227 	pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2228 	pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2229 	pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2230 
2231 	/*shared mem start */
2232 	rtlpriv->io.pci_mem_start =
2233 			(unsigned long)pci_iomap(pdev,
2234 			rtlpriv->cfg->bar_id, pmem_len);
2235 	if (rtlpriv->io.pci_mem_start == 0) {
2236 		WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
2237 		err = -ENOMEM;
2238 		goto fail2;
2239 	}
2240 
2241 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2242 		"mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2243 		pmem_start, pmem_len, pmem_flags,
2244 		rtlpriv->io.pci_mem_start);
2245 
2246 	/* Disable Clk Request */
2247 	pci_write_config_byte(pdev, 0x81, 0);
2248 	/* leave D3 mode */
2249 	pci_write_config_byte(pdev, 0x44, 0);
2250 	pci_write_config_byte(pdev, 0x04, 0x06);
2251 	pci_write_config_byte(pdev, 0x04, 0x07);
2252 
2253 	/* find adapter */
2254 	if (!_rtl_pci_find_adapter(pdev, hw)) {
2255 		err = -ENODEV;
2256 		goto fail2;
2257 	}
2258 
2259 	/* Init IO handler */
2260 	_rtl_pci_io_handler_init(&pdev->dev, hw);
2261 
2262 	/*like read eeprom and so on */
2263 	rtlpriv->cfg->ops->read_eeprom_info(hw);
2264 
2265 	if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2266 		pr_err("Can't init_sw_vars\n");
2267 		err = -ENODEV;
2268 		goto fail3;
2269 	}
2270 	rtlpriv->cfg->ops->init_sw_leds(hw);
2271 
2272 	/*aspm */
2273 	rtl_pci_init_aspm(hw);
2274 
2275 	/* Init mac80211 sw */
2276 	err = rtl_init_core(hw);
2277 	if (err) {
2278 		pr_err("Can't allocate sw for mac80211\n");
2279 		goto fail3;
2280 	}
2281 
2282 	/* Init PCI sw */
2283 	err = rtl_pci_init(hw, pdev);
2284 	if (err) {
2285 		pr_err("Failed to init PCI\n");
2286 		goto fail3;
2287 	}
2288 
2289 	err = ieee80211_register_hw(hw);
2290 	if (err) {
2291 		pr_err("Can't register mac80211 hw.\n");
2292 		err = -ENODEV;
2293 		goto fail3;
2294 	}
2295 	rtlpriv->mac80211.mac80211_registered = 1;
2296 
2297 	/* add for debug */
2298 	rtl_debug_add_one(hw);
2299 
2300 	/*init rfkill */
2301 	rtl_init_rfkill(hw);	/* Init PCI sw */
2302 
2303 	rtlpci = rtl_pcidev(pcipriv);
2304 	err = rtl_pci_intr_mode_decide(hw);
2305 	if (err) {
2306 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2307 			"%s: failed to register IRQ handler\n",
2308 			wiphy_name(hw->wiphy));
2309 		goto fail3;
2310 	}
2311 	rtlpci->irq_alloc = 1;
2312 
2313 	set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2314 	return 0;
2315 
2316 fail3:
2317 	pci_set_drvdata(pdev, NULL);
2318 	rtl_deinit_core(hw);
2319 
2320 fail2:
2321 	if (rtlpriv->io.pci_mem_start != 0)
2322 		pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2323 
2324 	pci_release_regions(pdev);
2325 	complete(&rtlpriv->firmware_loading_complete);
2326 
2327 fail1:
2328 	if (hw)
2329 		ieee80211_free_hw(hw);
2330 	pci_disable_device(pdev);
2331 
2332 	return err;
2333 }
2334 EXPORT_SYMBOL(rtl_pci_probe);
2335 
2336 void rtl_pci_disconnect(struct pci_dev *pdev)
2337 {
2338 	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2339 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2340 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2341 	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2342 	struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2343 
2344 	/* just in case driver is removed before firmware callback */
2345 	wait_for_completion(&rtlpriv->firmware_loading_complete);
2346 	clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2347 
2348 	/* remove form debug */
2349 	rtl_debug_remove_one(hw);
2350 
2351 	/*ieee80211_unregister_hw will call ops_stop */
2352 	if (rtlmac->mac80211_registered == 1) {
2353 		ieee80211_unregister_hw(hw);
2354 		rtlmac->mac80211_registered = 0;
2355 	} else {
2356 		rtl_deinit_deferred_work(hw, false);
2357 		rtlpriv->intf_ops->adapter_stop(hw);
2358 	}
2359 	rtlpriv->cfg->ops->disable_interrupt(hw);
2360 
2361 	/*deinit rfkill */
2362 	rtl_deinit_rfkill(hw);
2363 
2364 	rtl_pci_deinit(hw);
2365 	rtl_deinit_core(hw);
2366 	rtlpriv->cfg->ops->deinit_sw_vars(hw);
2367 
2368 	if (rtlpci->irq_alloc) {
2369 		free_irq(rtlpci->pdev->irq, hw);
2370 		rtlpci->irq_alloc = 0;
2371 	}
2372 
2373 	if (rtlpci->using_msi)
2374 		pci_disable_msi(rtlpci->pdev);
2375 
2376 	list_del(&rtlpriv->list);
2377 	if (rtlpriv->io.pci_mem_start != 0) {
2378 		pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2379 		pci_release_regions(pdev);
2380 	}
2381 
2382 	pci_disable_device(pdev);
2383 
2384 	rtl_pci_disable_aspm(hw);
2385 
2386 	pci_set_drvdata(pdev, NULL);
2387 
2388 	ieee80211_free_hw(hw);
2389 }
2390 EXPORT_SYMBOL(rtl_pci_disconnect);
2391 
2392 #ifdef CONFIG_PM_SLEEP
2393 /***************************************
2394  * kernel pci power state define:
2395  * PCI_D0         ((pci_power_t __force) 0)
2396  * PCI_D1         ((pci_power_t __force) 1)
2397  * PCI_D2         ((pci_power_t __force) 2)
2398  * PCI_D3hot      ((pci_power_t __force) 3)
2399  * PCI_D3cold     ((pci_power_t __force) 4)
2400  * PCI_UNKNOWN    ((pci_power_t __force) 5)
2401 
2402  * This function is called when system
2403  * goes into suspend state mac80211 will
2404  * call rtl_mac_stop() from the mac80211
2405  * suspend function first, So there is
2406  * no need to call hw_disable here.
2407  ****************************************/
2408 int rtl_pci_suspend(struct device *dev)
2409 {
2410 	struct ieee80211_hw *hw = dev_get_drvdata(dev);
2411 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2412 
2413 	rtlpriv->cfg->ops->hw_suspend(hw);
2414 	rtl_deinit_rfkill(hw);
2415 
2416 	return 0;
2417 }
2418 EXPORT_SYMBOL(rtl_pci_suspend);
2419 
2420 int rtl_pci_resume(struct device *dev)
2421 {
2422 	struct ieee80211_hw *hw = dev_get_drvdata(dev);
2423 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2424 
2425 	rtlpriv->cfg->ops->hw_resume(hw);
2426 	rtl_init_rfkill(hw);
2427 	return 0;
2428 }
2429 EXPORT_SYMBOL(rtl_pci_resume);
2430 #endif /* CONFIG_PM_SLEEP */
2431 
2432 const struct rtl_intf_ops rtl_pci_ops = {
2433 	.read_efuse_byte = read_efuse_byte,
2434 	.adapter_start = rtl_pci_start,
2435 	.adapter_stop = rtl_pci_stop,
2436 	.check_buddy_priv = rtl_pci_check_buddy_priv,
2437 	.adapter_tx = rtl_pci_tx,
2438 	.flush = rtl_pci_flush,
2439 	.reset_trx_ring = rtl_pci_reset_trx_ring,
2440 	.waitq_insert = rtl_pci_tx_chk_waitq_insert,
2441 
2442 	.disable_aspm = rtl_pci_disable_aspm,
2443 	.enable_aspm = rtl_pci_enable_aspm,
2444 };
2445