1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "wifi.h" 27 #include "core.h" 28 #include "pci.h" 29 #include "base.h" 30 #include "ps.h" 31 #include "efuse.h" 32 #include <linux/interrupt.h> 33 #include <linux/export.h> 34 #include <linux/kmemleak.h> 35 #include <linux/module.h> 36 37 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 38 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 39 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>"); 40 MODULE_LICENSE("GPL"); 41 MODULE_DESCRIPTION("PCI basic driver for rtlwifi"); 42 43 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { 44 INTEL_VENDOR_ID, 45 ATI_VENDOR_ID, 46 AMD_VENDOR_ID, 47 SIS_VENDOR_ID 48 }; 49 50 static const u8 ac_to_hwq[] = { 51 VO_QUEUE, 52 VI_QUEUE, 53 BE_QUEUE, 54 BK_QUEUE 55 }; 56 57 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, 58 struct sk_buff *skb) 59 { 60 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 61 __le16 fc = rtl_get_fc(skb); 62 u8 queue_index = skb_get_queue_mapping(skb); 63 64 if (unlikely(ieee80211_is_beacon(fc))) 65 return BEACON_QUEUE; 66 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) 67 return MGNT_QUEUE; 68 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 69 if (ieee80211_is_nullfunc(fc)) 70 return HIGH_QUEUE; 71 72 return ac_to_hwq[queue_index]; 73 } 74 75 /* Update PCI dependent default settings*/ 76 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) 77 { 78 struct rtl_priv *rtlpriv = rtl_priv(hw); 79 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 80 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 81 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 82 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 83 u8 init_aspm; 84 85 ppsc->reg_rfps_level = 0; 86 ppsc->support_aspm = false; 87 88 /*Update PCI ASPM setting */ 89 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm; 90 switch (rtlpci->const_pci_aspm) { 91 case 0: 92 /*No ASPM */ 93 break; 94 95 case 1: 96 /*ASPM dynamically enabled/disable. */ 97 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; 98 break; 99 100 case 2: 101 /*ASPM with Clock Req dynamically enabled/disable. */ 102 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | 103 RT_RF_OFF_LEVL_CLK_REQ); 104 break; 105 106 case 3: 107 /* 108 * Always enable ASPM and Clock Req 109 * from initialization to halt. 110 * */ 111 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); 112 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | 113 RT_RF_OFF_LEVL_CLK_REQ); 114 break; 115 116 case 4: 117 /* 118 * Always enable ASPM without Clock Req 119 * from initialization to halt. 120 * */ 121 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | 122 RT_RF_OFF_LEVL_CLK_REQ); 123 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; 124 break; 125 } 126 127 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 128 129 /*Update Radio OFF setting */ 130 switch (rtlpci->const_hwsw_rfoff_d3) { 131 case 1: 132 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 133 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 134 break; 135 136 case 2: 137 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 138 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 139 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 140 break; 141 142 case 3: 143 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; 144 break; 145 } 146 147 /*Set HW definition to determine if it supports ASPM. */ 148 switch (rtlpci->const_support_pciaspm) { 149 case 0:{ 150 /*Not support ASPM. */ 151 bool support_aspm = false; 152 ppsc->support_aspm = support_aspm; 153 break; 154 } 155 case 1:{ 156 /*Support ASPM. */ 157 bool support_aspm = true; 158 bool support_backdoor = true; 159 ppsc->support_aspm = support_aspm; 160 161 /*if (priv->oem_id == RT_CID_TOSHIBA && 162 !priv->ndis_adapter.amd_l1_patch) 163 support_backdoor = false; */ 164 165 ppsc->support_backdoor = support_backdoor; 166 167 break; 168 } 169 case 2: 170 /*ASPM value set by chipset. */ 171 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) { 172 bool support_aspm = true; 173 ppsc->support_aspm = support_aspm; 174 } 175 break; 176 default: 177 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 178 "switch case %#x not processed\n", 179 rtlpci->const_support_pciaspm); 180 break; 181 } 182 183 /* toshiba aspm issue, toshiba will set aspm selfly 184 * so we should not set aspm in driver */ 185 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm); 186 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE && 187 init_aspm == 0x43) 188 ppsc->support_aspm = false; 189 } 190 191 static bool _rtl_pci_platform_switch_device_pci_aspm( 192 struct ieee80211_hw *hw, 193 u8 value) 194 { 195 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 196 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 197 198 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE) 199 value |= 0x40; 200 201 pci_write_config_byte(rtlpci->pdev, 0x80, value); 202 203 return false; 204 } 205 206 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/ 207 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value) 208 { 209 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 210 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 211 212 pci_write_config_byte(rtlpci->pdev, 0x81, value); 213 214 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 215 udelay(100); 216 } 217 218 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ 219 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) 220 { 221 struct rtl_priv *rtlpriv = rtl_priv(hw); 222 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 223 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 224 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 225 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 226 u8 num4bytes = pcipriv->ndis_adapter.num4bytes; 227 /*Retrieve original configuration settings. */ 228 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg; 229 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter. 230 pcibridge_linkctrlreg; 231 u16 aspmlevel = 0; 232 u8 tmp_u1b = 0; 233 234 if (!ppsc->support_aspm) 235 return; 236 237 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 238 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 239 "PCI(Bridge) UNKNOWN\n"); 240 241 return; 242 } 243 244 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 245 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 246 _rtl_pci_switch_clk_req(hw, 0x0); 247 } 248 249 /*for promising device will in L0 state after an I/O. */ 250 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b); 251 252 /*Set corresponding value. */ 253 aspmlevel |= BIT(0) | BIT(1); 254 linkctrl_reg &= ~aspmlevel; 255 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1)); 256 257 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg); 258 udelay(50); 259 260 /*4 Disable Pci Bridge ASPM */ 261 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), 262 pcibridge_linkctrlreg); 263 264 udelay(50); 265 } 266 267 /* 268 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for 269 *power saving We should follow the sequence to enable 270 *RTL8192SE first then enable Pci Bridge ASPM 271 *or the system will show bluescreen. 272 */ 273 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) 274 { 275 struct rtl_priv *rtlpriv = rtl_priv(hw); 276 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 277 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 278 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 279 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 280 u8 num4bytes = pcipriv->ndis_adapter.num4bytes; 281 u16 aspmlevel; 282 u8 u_pcibridge_aspmsetting; 283 u8 u_device_aspmsetting; 284 285 if (!ppsc->support_aspm) 286 return; 287 288 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 289 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 290 "PCI(Bridge) UNKNOWN\n"); 291 return; 292 } 293 294 /*4 Enable Pci Bridge ASPM */ 295 296 u_pcibridge_aspmsetting = 297 pcipriv->ndis_adapter.pcibridge_linkctrlreg | 298 rtlpci->const_hostpci_aspm_setting; 299 300 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) 301 u_pcibridge_aspmsetting &= ~BIT(0); 302 303 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), 304 u_pcibridge_aspmsetting); 305 306 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 307 "PlatformEnableASPM(): Write reg[%x] = %x\n", 308 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10), 309 u_pcibridge_aspmsetting); 310 311 udelay(50); 312 313 /*Get ASPM level (with/without Clock Req) */ 314 aspmlevel = rtlpci->const_devicepci_aspm_setting; 315 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg; 316 317 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/ 318 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */ 319 320 u_device_aspmsetting |= aspmlevel; 321 322 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting); 323 324 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 325 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level & 326 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0); 327 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 328 } 329 udelay(100); 330 } 331 332 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw) 333 { 334 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 335 336 bool status = false; 337 u8 offset_e0; 338 unsigned offset_e4; 339 340 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0); 341 342 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0); 343 344 if (offset_e0 == 0xA0) { 345 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4); 346 if (offset_e4 & BIT(23)) 347 status = true; 348 } 349 350 return status; 351 } 352 353 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw, 354 struct rtl_priv **buddy_priv) 355 { 356 struct rtl_priv *rtlpriv = rtl_priv(hw); 357 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 358 bool find_buddy_priv = false; 359 struct rtl_priv *tpriv; 360 struct rtl_pci_priv *tpcipriv = NULL; 361 362 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) { 363 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list, 364 list) { 365 tpcipriv = (struct rtl_pci_priv *)tpriv->priv; 366 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 367 "pcipriv->ndis_adapter.funcnumber %x\n", 368 pcipriv->ndis_adapter.funcnumber); 369 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 370 "tpcipriv->ndis_adapter.funcnumber %x\n", 371 tpcipriv->ndis_adapter.funcnumber); 372 373 if ((pcipriv->ndis_adapter.busnumber == 374 tpcipriv->ndis_adapter.busnumber) && 375 (pcipriv->ndis_adapter.devnumber == 376 tpcipriv->ndis_adapter.devnumber) && 377 (pcipriv->ndis_adapter.funcnumber != 378 tpcipriv->ndis_adapter.funcnumber)) { 379 find_buddy_priv = true; 380 break; 381 } 382 } 383 } 384 385 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 386 "find_buddy_priv %d\n", find_buddy_priv); 387 388 if (find_buddy_priv) 389 *buddy_priv = tpriv; 390 391 return find_buddy_priv; 392 } 393 394 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw) 395 { 396 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 397 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 398 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset; 399 u8 linkctrl_reg; 400 u8 num4bbytes; 401 402 num4bbytes = (capabilityoffset + 0x10) / 4; 403 404 /*Read Link Control Register */ 405 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg); 406 407 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg; 408 } 409 410 static void rtl_pci_parse_configuration(struct pci_dev *pdev, 411 struct ieee80211_hw *hw) 412 { 413 struct rtl_priv *rtlpriv = rtl_priv(hw); 414 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 415 416 u8 tmp; 417 u16 linkctrl_reg; 418 419 /*Link Control Register */ 420 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg); 421 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg; 422 423 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", 424 pcipriv->ndis_adapter.linkctrl_reg); 425 426 pci_read_config_byte(pdev, 0x98, &tmp); 427 tmp |= BIT(4); 428 pci_write_config_byte(pdev, 0x98, tmp); 429 430 tmp = 0x17; 431 pci_write_config_byte(pdev, 0x70f, tmp); 432 } 433 434 static void rtl_pci_init_aspm(struct ieee80211_hw *hw) 435 { 436 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 437 438 _rtl_pci_update_default_setting(hw); 439 440 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { 441 /*Always enable ASPM & Clock Req. */ 442 rtl_pci_enable_aspm(hw); 443 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM); 444 } 445 446 } 447 448 static void _rtl_pci_io_handler_init(struct device *dev, 449 struct ieee80211_hw *hw) 450 { 451 struct rtl_priv *rtlpriv = rtl_priv(hw); 452 453 rtlpriv->io.dev = dev; 454 455 rtlpriv->io.write8_async = pci_write8_async; 456 rtlpriv->io.write16_async = pci_write16_async; 457 rtlpriv->io.write32_async = pci_write32_async; 458 459 rtlpriv->io.read8_sync = pci_read8_sync; 460 rtlpriv->io.read16_sync = pci_read16_sync; 461 rtlpriv->io.read32_sync = pci_read32_sync; 462 463 } 464 465 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw, 466 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid) 467 { 468 struct rtl_priv *rtlpriv = rtl_priv(hw); 469 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 470 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 471 struct sk_buff *next_skb; 472 u8 additionlen = FCS_LEN; 473 474 /* here open is 4, wep/tkip is 8, aes is 12*/ 475 if (info->control.hw_key) 476 additionlen += info->control.hw_key->icv_len; 477 478 /* The most skb num is 6 */ 479 tcb_desc->empkt_num = 0; 480 spin_lock_bh(&rtlpriv->locks.waitq_lock); 481 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) { 482 struct ieee80211_tx_info *next_info; 483 484 next_info = IEEE80211_SKB_CB(next_skb); 485 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) { 486 tcb_desc->empkt_len[tcb_desc->empkt_num] = 487 next_skb->len + additionlen; 488 tcb_desc->empkt_num++; 489 } else { 490 break; 491 } 492 493 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid], 494 next_skb)) 495 break; 496 497 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num) 498 break; 499 } 500 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 501 502 return true; 503 } 504 505 /* just for early mode now */ 506 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw) 507 { 508 struct rtl_priv *rtlpriv = rtl_priv(hw); 509 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 510 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 511 struct sk_buff *skb = NULL; 512 struct ieee80211_tx_info *info = NULL; 513 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 514 int tid; 515 516 if (!rtlpriv->rtlhal.earlymode_enable) 517 return; 518 519 if (rtlpriv->dm.supp_phymode_switch && 520 (rtlpriv->easy_concurrent_ctl.switch_in_process || 521 (rtlpriv->buddy_priv && 522 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process))) 523 return; 524 /* we juse use em for BE/BK/VI/VO */ 525 for (tid = 7; tid >= 0; tid--) { 526 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)]; 527 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; 528 while (!mac->act_scanning && 529 rtlpriv->psc.rfpwr_state == ERFON) { 530 struct rtl_tcb_desc tcb_desc; 531 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 532 533 spin_lock_bh(&rtlpriv->locks.waitq_lock); 534 if (!skb_queue_empty(&mac->skb_waitq[tid]) && 535 (ring->entries - skb_queue_len(&ring->queue) > 536 rtlhal->max_earlymode_num)) { 537 skb = skb_dequeue(&mac->skb_waitq[tid]); 538 } else { 539 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 540 break; 541 } 542 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 543 544 /* Some macaddr can't do early mode. like 545 * multicast/broadcast/no_qos data */ 546 info = IEEE80211_SKB_CB(skb); 547 if (info->flags & IEEE80211_TX_CTL_AMPDU) 548 _rtl_update_earlymode_info(hw, skb, 549 &tcb_desc, tid); 550 551 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc); 552 } 553 } 554 } 555 556 557 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) 558 { 559 struct rtl_priv *rtlpriv = rtl_priv(hw); 560 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 561 562 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 563 564 while (skb_queue_len(&ring->queue)) { 565 struct sk_buff *skb; 566 struct ieee80211_tx_info *info; 567 __le16 fc; 568 u8 tid; 569 u8 *entry; 570 571 if (rtlpriv->use_new_trx_flow) 572 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 573 else 574 entry = (u8 *)(&ring->desc[ring->idx]); 575 576 if (rtlpriv->cfg->ops->get_available_desc && 577 rtlpriv->cfg->ops->get_available_desc(hw, prio) <= 1) { 578 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_DMESG, 579 "no available desc!\n"); 580 return; 581 } 582 583 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx)) 584 return; 585 ring->idx = (ring->idx + 1) % ring->entries; 586 587 skb = __skb_dequeue(&ring->queue); 588 pci_unmap_single(rtlpci->pdev, 589 rtlpriv->cfg->ops-> 590 get_desc((u8 *)entry, true, 591 HW_DESC_TXBUFF_ADDR), 592 skb->len, PCI_DMA_TODEVICE); 593 594 /* remove early mode header */ 595 if (rtlpriv->rtlhal.earlymode_enable) 596 skb_pull(skb, EM_HDR_LEN); 597 598 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, 599 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", 600 ring->idx, 601 skb_queue_len(&ring->queue), 602 *(u16 *)(skb->data + 22)); 603 604 if (prio == TXCMD_QUEUE) { 605 dev_kfree_skb(skb); 606 goto tx_status_ok; 607 608 } 609 610 /* for sw LPS, just after NULL skb send out, we can 611 * sure AP knows we are sleeping, we should not let 612 * rf sleep 613 */ 614 fc = rtl_get_fc(skb); 615 if (ieee80211_is_nullfunc(fc)) { 616 if (ieee80211_has_pm(fc)) { 617 rtlpriv->mac80211.offchan_delay = true; 618 rtlpriv->psc.state_inap = true; 619 } else { 620 rtlpriv->psc.state_inap = false; 621 } 622 } 623 if (ieee80211_is_action(fc)) { 624 struct ieee80211_mgmt *action_frame = 625 (struct ieee80211_mgmt *)skb->data; 626 if (action_frame->u.action.u.ht_smps.action == 627 WLAN_HT_ACTION_SMPS) { 628 dev_kfree_skb(skb); 629 goto tx_status_ok; 630 } 631 } 632 633 /* update tid tx pkt num */ 634 tid = rtl_get_tid(skb); 635 if (tid <= 7) 636 rtlpriv->link_info.tidtx_inperiod[tid]++; 637 638 info = IEEE80211_SKB_CB(skb); 639 ieee80211_tx_info_clear_status(info); 640 641 info->flags |= IEEE80211_TX_STAT_ACK; 642 /*info->status.rates[0].count = 1; */ 643 644 ieee80211_tx_status_irqsafe(hw, skb); 645 646 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) { 647 648 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, 649 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", 650 prio, ring->idx, 651 skb_queue_len(&ring->queue)); 652 653 ieee80211_wake_queue(hw, 654 skb_get_queue_mapping 655 (skb)); 656 } 657 tx_status_ok: 658 skb = NULL; 659 } 660 661 if (((rtlpriv->link_info.num_rx_inperiod + 662 rtlpriv->link_info.num_tx_inperiod) > 8) || 663 (rtlpriv->link_info.num_rx_inperiod > 2)) 664 rtl_lps_leave(hw); 665 } 666 667 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, 668 struct sk_buff *new_skb, u8 *entry, 669 int rxring_idx, int desc_idx) 670 { 671 struct rtl_priv *rtlpriv = rtl_priv(hw); 672 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 673 u32 bufferaddress; 674 u8 tmp_one = 1; 675 struct sk_buff *skb; 676 677 if (likely(new_skb)) { 678 skb = new_skb; 679 goto remap; 680 } 681 skb = dev_alloc_skb(rtlpci->rxbuffersize); 682 if (!skb) 683 return 0; 684 685 remap: 686 /* just set skb->cb to mapping addr for pci_unmap_single use */ 687 *((dma_addr_t *)skb->cb) = 688 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb), 689 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 690 bufferaddress = *((dma_addr_t *)skb->cb); 691 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress)) 692 return 0; 693 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb; 694 if (rtlpriv->use_new_trx_flow) { 695 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 696 HW_DESC_RX_PREPARE, 697 (u8 *)&bufferaddress); 698 } else { 699 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 700 HW_DESC_RXBUFF_ADDR, 701 (u8 *)&bufferaddress); 702 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 703 HW_DESC_RXPKT_LEN, 704 (u8 *)&rtlpci->rxbuffersize); 705 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 706 HW_DESC_RXOWN, 707 (u8 *)&tmp_one); 708 } 709 return 1; 710 } 711 712 /* inorder to receive 8K AMSDU we have set skb to 713 * 9100bytes in init rx ring, but if this packet is 714 * not a AMSDU, this large packet will be sent to 715 * TCP/IP directly, this cause big packet ping fail 716 * like: "ping -s 65507", so here we will realloc skb 717 * based on the true size of packet, Mac80211 718 * Probably will do it better, but does not yet. 719 * 720 * Some platform will fail when alloc skb sometimes. 721 * in this condition, we will send the old skb to 722 * mac80211 directly, this will not cause any other 723 * issues, but only this packet will be lost by TCP/IP 724 */ 725 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw, 726 struct sk_buff *skb, 727 struct ieee80211_rx_status rx_status) 728 { 729 if (unlikely(!rtl_action_proc(hw, skb, false))) { 730 dev_kfree_skb_any(skb); 731 } else { 732 struct sk_buff *uskb = NULL; 733 u8 *pdata; 734 735 uskb = dev_alloc_skb(skb->len + 128); 736 if (likely(uskb)) { 737 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, 738 sizeof(rx_status)); 739 pdata = (u8 *)skb_put(uskb, skb->len); 740 memcpy(pdata, skb->data, skb->len); 741 dev_kfree_skb_any(skb); 742 ieee80211_rx_irqsafe(hw, uskb); 743 } else { 744 ieee80211_rx_irqsafe(hw, skb); 745 } 746 } 747 } 748 749 /*hsisr interrupt handler*/ 750 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw) 751 { 752 struct rtl_priv *rtlpriv = rtl_priv(hw); 753 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 754 755 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR], 756 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) | 757 rtlpci->sys_irq_mask); 758 } 759 760 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) 761 { 762 struct rtl_priv *rtlpriv = rtl_priv(hw); 763 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 764 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE; 765 struct ieee80211_rx_status rx_status = { 0 }; 766 unsigned int count = rtlpci->rxringcount; 767 u8 own; 768 u8 tmp_one; 769 bool unicast = false; 770 u8 hw_queue = 0; 771 unsigned int rx_remained_cnt; 772 struct rtl_stats stats = { 773 .signal = 0, 774 .rate = 0, 775 }; 776 777 /*RX NORMAL PKT */ 778 while (count--) { 779 struct ieee80211_hdr *hdr; 780 __le16 fc; 781 u16 len; 782 /*rx buffer descriptor */ 783 struct rtl_rx_buffer_desc *buffer_desc = NULL; 784 /*if use new trx flow, it means wifi info */ 785 struct rtl_rx_desc *pdesc = NULL; 786 /*rx pkt */ 787 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[ 788 rtlpci->rx_ring[rxring_idx].idx]; 789 struct sk_buff *new_skb; 790 791 if (rtlpriv->use_new_trx_flow) { 792 rx_remained_cnt = 793 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw, 794 hw_queue); 795 if (rx_remained_cnt == 0) 796 return; 797 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[ 798 rtlpci->rx_ring[rxring_idx].idx]; 799 pdesc = (struct rtl_rx_desc *)skb->data; 800 } else { /* rx descriptor */ 801 pdesc = &rtlpci->rx_ring[rxring_idx].desc[ 802 rtlpci->rx_ring[rxring_idx].idx]; 803 804 own = (u8)rtlpriv->cfg->ops->get_desc((u8 *)pdesc, 805 false, 806 HW_DESC_OWN); 807 if (own) /* wait data to be filled by hardware */ 808 return; 809 } 810 811 /* Reaching this point means: data is filled already 812 * AAAAAAttention !!! 813 * We can NOT access 'skb' before 'pci_unmap_single' 814 */ 815 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), 816 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 817 818 /* get a new skb - if fail, old one will be reused */ 819 new_skb = dev_alloc_skb(rtlpci->rxbuffersize); 820 if (unlikely(!new_skb)) 821 goto no_new; 822 memset(&rx_status , 0 , sizeof(rx_status)); 823 rtlpriv->cfg->ops->query_rx_desc(hw, &stats, 824 &rx_status, (u8 *)pdesc, skb); 825 826 if (rtlpriv->use_new_trx_flow) 827 rtlpriv->cfg->ops->rx_check_dma_ok(hw, 828 (u8 *)buffer_desc, 829 hw_queue); 830 831 len = rtlpriv->cfg->ops->get_desc((u8 *)pdesc, false, 832 HW_DESC_RXPKT_LEN); 833 834 if (skb->end - skb->tail > len) { 835 skb_put(skb, len); 836 if (rtlpriv->use_new_trx_flow) 837 skb_reserve(skb, stats.rx_drvinfo_size + 838 stats.rx_bufshift + 24); 839 else 840 skb_reserve(skb, stats.rx_drvinfo_size + 841 stats.rx_bufshift); 842 } else { 843 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 844 "skb->end - skb->tail = %d, len is %d\n", 845 skb->end - skb->tail, len); 846 dev_kfree_skb_any(skb); 847 goto new_trx_end; 848 } 849 /* handle command packet here */ 850 if (rtlpriv->cfg->ops->rx_command_packet && 851 rtlpriv->cfg->ops->rx_command_packet(hw, &stats, skb)) { 852 dev_kfree_skb_any(skb); 853 goto new_trx_end; 854 } 855 856 /* 857 * NOTICE This can not be use for mac80211, 858 * this is done in mac80211 code, 859 * if done here sec DHCP will fail 860 * skb_trim(skb, skb->len - 4); 861 */ 862 863 hdr = rtl_get_hdr(skb); 864 fc = rtl_get_fc(skb); 865 866 if (!stats.crc && !stats.hwerror) { 867 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, 868 sizeof(rx_status)); 869 870 if (is_broadcast_ether_addr(hdr->addr1)) { 871 ;/*TODO*/ 872 } else if (is_multicast_ether_addr(hdr->addr1)) { 873 ;/*TODO*/ 874 } else { 875 unicast = true; 876 rtlpriv->stats.rxbytesunicast += skb->len; 877 } 878 rtl_is_special_data(hw, skb, false, true); 879 880 if (ieee80211_is_data(fc)) { 881 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX); 882 if (unicast) 883 rtlpriv->link_info.num_rx_inperiod++; 884 } 885 /* static bcn for roaming */ 886 rtl_beacon_statistic(hw, skb); 887 rtl_p2p_info(hw, (void *)skb->data, skb->len); 888 /* for sw lps */ 889 rtl_swlps_beacon(hw, (void *)skb->data, skb->len); 890 rtl_recognize_peer(hw, (void *)skb->data, skb->len); 891 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) && 892 (rtlpriv->rtlhal.current_bandtype == 893 BAND_ON_2_4G) && 894 (ieee80211_is_beacon(fc) || 895 ieee80211_is_probe_resp(fc))) { 896 dev_kfree_skb_any(skb); 897 } else { 898 _rtl_pci_rx_to_mac80211(hw, skb, rx_status); 899 } 900 } else { 901 dev_kfree_skb_any(skb); 902 } 903 new_trx_end: 904 if (rtlpriv->use_new_trx_flow) { 905 rtlpci->rx_ring[hw_queue].next_rx_rp += 1; 906 rtlpci->rx_ring[hw_queue].next_rx_rp %= 907 RTL_PCI_MAX_RX_COUNT; 908 909 rx_remained_cnt--; 910 rtl_write_word(rtlpriv, 0x3B4, 911 rtlpci->rx_ring[hw_queue].next_rx_rp); 912 } 913 if (((rtlpriv->link_info.num_rx_inperiod + 914 rtlpriv->link_info.num_tx_inperiod) > 8) || 915 (rtlpriv->link_info.num_rx_inperiod > 2)) 916 rtl_lps_leave(hw); 917 skb = new_skb; 918 no_new: 919 if (rtlpriv->use_new_trx_flow) { 920 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc, 921 rxring_idx, 922 rtlpci->rx_ring[rxring_idx].idx); 923 } else { 924 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc, 925 rxring_idx, 926 rtlpci->rx_ring[rxring_idx].idx); 927 if (rtlpci->rx_ring[rxring_idx].idx == 928 rtlpci->rxringcount - 1) 929 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, 930 false, 931 HW_DESC_RXERO, 932 (u8 *)&tmp_one); 933 } 934 rtlpci->rx_ring[rxring_idx].idx = 935 (rtlpci->rx_ring[rxring_idx].idx + 1) % 936 rtlpci->rxringcount; 937 } 938 } 939 940 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) 941 { 942 struct ieee80211_hw *hw = dev_id; 943 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 944 struct rtl_priv *rtlpriv = rtl_priv(hw); 945 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 946 unsigned long flags; 947 u32 inta = 0; 948 u32 intb = 0; 949 irqreturn_t ret = IRQ_HANDLED; 950 951 if (rtlpci->irq_enabled == 0) 952 return ret; 953 954 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock , flags); 955 rtlpriv->cfg->ops->disable_interrupt(hw); 956 957 /*read ISR: 4/8bytes */ 958 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb); 959 960 /*Shared IRQ or HW disappared */ 961 if (!inta || inta == 0xffff) 962 goto done; 963 964 /*<1> beacon related */ 965 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) { 966 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 967 "beacon ok interrupt!\n"); 968 } 969 970 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) { 971 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 972 "beacon err interrupt!\n"); 973 } 974 975 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) { 976 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); 977 } 978 979 if (inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) { 980 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 981 "prepare beacon for interrupt!\n"); 982 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet); 983 } 984 985 /*<2> Tx related */ 986 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW])) 987 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); 988 989 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) { 990 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 991 "Manage ok interrupt!\n"); 992 _rtl_pci_tx_isr(hw, MGNT_QUEUE); 993 } 994 995 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) { 996 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 997 "HIGH_QUEUE ok interrupt!\n"); 998 _rtl_pci_tx_isr(hw, HIGH_QUEUE); 999 } 1000 1001 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) { 1002 rtlpriv->link_info.num_tx_inperiod++; 1003 1004 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1005 "BK Tx OK interrupt!\n"); 1006 _rtl_pci_tx_isr(hw, BK_QUEUE); 1007 } 1008 1009 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) { 1010 rtlpriv->link_info.num_tx_inperiod++; 1011 1012 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1013 "BE TX OK interrupt!\n"); 1014 _rtl_pci_tx_isr(hw, BE_QUEUE); 1015 } 1016 1017 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) { 1018 rtlpriv->link_info.num_tx_inperiod++; 1019 1020 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1021 "VI TX OK interrupt!\n"); 1022 _rtl_pci_tx_isr(hw, VI_QUEUE); 1023 } 1024 1025 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) { 1026 rtlpriv->link_info.num_tx_inperiod++; 1027 1028 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1029 "Vo TX OK interrupt!\n"); 1030 _rtl_pci_tx_isr(hw, VO_QUEUE); 1031 } 1032 1033 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) { 1034 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) { 1035 rtlpriv->link_info.num_tx_inperiod++; 1036 1037 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1038 "CMD TX OK interrupt!\n"); 1039 _rtl_pci_tx_isr(hw, TXCMD_QUEUE); 1040 } 1041 } 1042 1043 /*<3> Rx related */ 1044 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) { 1045 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); 1046 _rtl_pci_rx_interrupt(hw); 1047 } 1048 1049 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) { 1050 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1051 "rx descriptor unavailable!\n"); 1052 _rtl_pci_rx_interrupt(hw); 1053 } 1054 1055 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) { 1056 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); 1057 _rtl_pci_rx_interrupt(hw); 1058 } 1059 1060 /*<4> fw related*/ 1061 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { 1062 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) { 1063 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1064 "firmware interrupt!\n"); 1065 queue_delayed_work(rtlpriv->works.rtl_wq, 1066 &rtlpriv->works.fwevt_wq, 0); 1067 } 1068 } 1069 1070 /*<5> hsisr related*/ 1071 /* Only 8188EE & 8723BE Supported. 1072 * If Other ICs Come in, System will corrupt, 1073 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR] 1074 * are not initialized 1075 */ 1076 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE || 1077 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) { 1078 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) { 1079 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1080 "hsisr interrupt!\n"); 1081 _rtl_pci_hs_interrupt(hw); 1082 } 1083 } 1084 1085 if (rtlpriv->rtlhal.earlymode_enable) 1086 tasklet_schedule(&rtlpriv->works.irq_tasklet); 1087 1088 done: 1089 rtlpriv->cfg->ops->enable_interrupt(hw); 1090 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1091 return ret; 1092 } 1093 1094 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw) 1095 { 1096 _rtl_pci_tx_chk_waitq(hw); 1097 } 1098 1099 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw) 1100 { 1101 struct rtl_priv *rtlpriv = rtl_priv(hw); 1102 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1103 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1104 struct rtl8192_tx_ring *ring = NULL; 1105 struct ieee80211_hdr *hdr = NULL; 1106 struct ieee80211_tx_info *info = NULL; 1107 struct sk_buff *pskb = NULL; 1108 struct rtl_tx_desc *pdesc = NULL; 1109 struct rtl_tcb_desc tcb_desc; 1110 /*This is for new trx flow*/ 1111 struct rtl_tx_buffer_desc *pbuffer_desc = NULL; 1112 u8 temp_one = 1; 1113 u8 *entry; 1114 1115 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 1116 ring = &rtlpci->tx_ring[BEACON_QUEUE]; 1117 pskb = __skb_dequeue(&ring->queue); 1118 if (rtlpriv->use_new_trx_flow) 1119 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1120 else 1121 entry = (u8 *)(&ring->desc[ring->idx]); 1122 if (pskb) { 1123 pci_unmap_single(rtlpci->pdev, 1124 rtlpriv->cfg->ops->get_desc( 1125 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR), 1126 pskb->len, PCI_DMA_TODEVICE); 1127 kfree_skb(pskb); 1128 } 1129 1130 /*NB: the beacon data buffer must be 32-bit aligned. */ 1131 pskb = ieee80211_beacon_get(hw, mac->vif); 1132 if (pskb == NULL) 1133 return; 1134 hdr = rtl_get_hdr(pskb); 1135 info = IEEE80211_SKB_CB(pskb); 1136 pdesc = &ring->desc[0]; 1137 if (rtlpriv->use_new_trx_flow) 1138 pbuffer_desc = &ring->buffer_desc[0]; 1139 1140 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1141 (u8 *)pbuffer_desc, info, NULL, pskb, 1142 BEACON_QUEUE, &tcb_desc); 1143 1144 __skb_queue_tail(&ring->queue, pskb); 1145 1146 if (rtlpriv->use_new_trx_flow) { 1147 temp_one = 4; 1148 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true, 1149 HW_DESC_OWN, (u8 *)&temp_one); 1150 } else { 1151 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN, 1152 &temp_one); 1153 } 1154 return; 1155 } 1156 1157 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw) 1158 { 1159 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1160 struct rtl_priv *rtlpriv = rtl_priv(hw); 1161 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1162 u8 i; 1163 u16 desc_num; 1164 1165 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) 1166 desc_num = TX_DESC_NUM_92E; 1167 else 1168 desc_num = RT_TXDESC_NUM; 1169 1170 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1171 rtlpci->txringcount[i] = desc_num; 1172 1173 /* 1174 *we just alloc 2 desc for beacon queue, 1175 *because we just need first desc in hw beacon. 1176 */ 1177 rtlpci->txringcount[BEACON_QUEUE] = 2; 1178 1179 /*BE queue need more descriptor for performance 1180 *consideration or, No more tx desc will happen, 1181 *and may cause mac80211 mem leakage. 1182 */ 1183 if (!rtl_priv(hw)->use_new_trx_flow) 1184 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE; 1185 1186 rtlpci->rxbuffersize = 9100; /*2048/1024; */ 1187 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */ 1188 } 1189 1190 static void _rtl_pci_init_struct(struct ieee80211_hw *hw, 1191 struct pci_dev *pdev) 1192 { 1193 struct rtl_priv *rtlpriv = rtl_priv(hw); 1194 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1195 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1196 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1197 1198 rtlpci->up_first_time = true; 1199 rtlpci->being_init_adapter = false; 1200 1201 rtlhal->hw = hw; 1202 rtlpci->pdev = pdev; 1203 1204 /*Tx/Rx related var */ 1205 _rtl_pci_init_trx_var(hw); 1206 1207 /*IBSS*/ 1208 mac->beacon_interval = 100; 1209 1210 /*AMPDU*/ 1211 mac->min_space_cfg = 0; 1212 mac->max_mss_density = 0; 1213 /*set sane AMPDU defaults */ 1214 mac->current_ampdu_density = 7; 1215 mac->current_ampdu_factor = 3; 1216 1217 /*QOS*/ 1218 rtlpci->acm_method = EACMWAY2_SW; 1219 1220 /*task */ 1221 tasklet_init(&rtlpriv->works.irq_tasklet, 1222 (void (*)(unsigned long))_rtl_pci_irq_tasklet, 1223 (unsigned long)hw); 1224 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet, 1225 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet, 1226 (unsigned long)hw); 1227 INIT_WORK(&rtlpriv->works.lps_change_work, 1228 rtl_lps_change_work_callback); 1229 } 1230 1231 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, 1232 unsigned int prio, unsigned int entries) 1233 { 1234 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1235 struct rtl_priv *rtlpriv = rtl_priv(hw); 1236 struct rtl_tx_buffer_desc *buffer_desc; 1237 struct rtl_tx_desc *desc; 1238 dma_addr_t buffer_desc_dma, desc_dma; 1239 u32 nextdescaddress; 1240 int i; 1241 1242 /* alloc tx buffer desc for new trx flow*/ 1243 if (rtlpriv->use_new_trx_flow) { 1244 buffer_desc = 1245 pci_zalloc_consistent(rtlpci->pdev, 1246 sizeof(*buffer_desc) * entries, 1247 &buffer_desc_dma); 1248 1249 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) { 1250 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1251 "Cannot allocate TX ring (prio = %d)\n", 1252 prio); 1253 return -ENOMEM; 1254 } 1255 1256 rtlpci->tx_ring[prio].buffer_desc = buffer_desc; 1257 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma; 1258 1259 rtlpci->tx_ring[prio].cur_tx_rp = 0; 1260 rtlpci->tx_ring[prio].cur_tx_wp = 0; 1261 rtlpci->tx_ring[prio].avl_desc = entries; 1262 } 1263 1264 /* alloc dma for this ring */ 1265 desc = pci_zalloc_consistent(rtlpci->pdev, 1266 sizeof(*desc) * entries, &desc_dma); 1267 1268 if (!desc || (unsigned long)desc & 0xFF) { 1269 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1270 "Cannot allocate TX ring (prio = %d)\n", prio); 1271 return -ENOMEM; 1272 } 1273 1274 rtlpci->tx_ring[prio].desc = desc; 1275 rtlpci->tx_ring[prio].dma = desc_dma; 1276 1277 rtlpci->tx_ring[prio].idx = 0; 1278 rtlpci->tx_ring[prio].entries = entries; 1279 skb_queue_head_init(&rtlpci->tx_ring[prio].queue); 1280 1281 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", 1282 prio, desc); 1283 1284 /* init every desc in this ring */ 1285 if (!rtlpriv->use_new_trx_flow) { 1286 for (i = 0; i < entries; i++) { 1287 nextdescaddress = (u32)desc_dma + 1288 ((i + 1) % entries) * 1289 sizeof(*desc); 1290 1291 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i], 1292 true, 1293 HW_DESC_TX_NEXTDESC_ADDR, 1294 (u8 *)&nextdescaddress); 1295 } 1296 } 1297 return 0; 1298 } 1299 1300 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1301 { 1302 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1303 struct rtl_priv *rtlpriv = rtl_priv(hw); 1304 int i; 1305 1306 if (rtlpriv->use_new_trx_flow) { 1307 struct rtl_rx_buffer_desc *entry = NULL; 1308 /* alloc dma for this ring */ 1309 rtlpci->rx_ring[rxring_idx].buffer_desc = 1310 pci_zalloc_consistent(rtlpci->pdev, 1311 sizeof(*rtlpci->rx_ring[rxring_idx]. 1312 buffer_desc) * 1313 rtlpci->rxringcount, 1314 &rtlpci->rx_ring[rxring_idx].dma); 1315 if (!rtlpci->rx_ring[rxring_idx].buffer_desc || 1316 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) { 1317 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1318 "Cannot allocate RX ring\n"); 1319 return -ENOMEM; 1320 } 1321 1322 /* init every desc in this ring */ 1323 rtlpci->rx_ring[rxring_idx].idx = 0; 1324 for (i = 0; i < rtlpci->rxringcount; i++) { 1325 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i]; 1326 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1327 rxring_idx, i)) 1328 return -ENOMEM; 1329 } 1330 } else { 1331 struct rtl_rx_desc *entry = NULL; 1332 u8 tmp_one = 1; 1333 /* alloc dma for this ring */ 1334 rtlpci->rx_ring[rxring_idx].desc = 1335 pci_zalloc_consistent(rtlpci->pdev, 1336 sizeof(*rtlpci->rx_ring[rxring_idx]. 1337 desc) * rtlpci->rxringcount, 1338 &rtlpci->rx_ring[rxring_idx].dma); 1339 if (!rtlpci->rx_ring[rxring_idx].desc || 1340 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) { 1341 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1342 "Cannot allocate RX ring\n"); 1343 return -ENOMEM; 1344 } 1345 1346 /* init every desc in this ring */ 1347 rtlpci->rx_ring[rxring_idx].idx = 0; 1348 1349 for (i = 0; i < rtlpci->rxringcount; i++) { 1350 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1351 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1352 rxring_idx, i)) 1353 return -ENOMEM; 1354 } 1355 1356 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1357 HW_DESC_RXERO, &tmp_one); 1358 } 1359 return 0; 1360 } 1361 1362 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw, 1363 unsigned int prio) 1364 { 1365 struct rtl_priv *rtlpriv = rtl_priv(hw); 1366 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1367 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 1368 1369 /* free every desc in this ring */ 1370 while (skb_queue_len(&ring->queue)) { 1371 u8 *entry; 1372 struct sk_buff *skb = __skb_dequeue(&ring->queue); 1373 1374 if (rtlpriv->use_new_trx_flow) 1375 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1376 else 1377 entry = (u8 *)(&ring->desc[ring->idx]); 1378 1379 pci_unmap_single(rtlpci->pdev, 1380 rtlpriv->cfg-> 1381 ops->get_desc((u8 *)entry, true, 1382 HW_DESC_TXBUFF_ADDR), 1383 skb->len, PCI_DMA_TODEVICE); 1384 kfree_skb(skb); 1385 ring->idx = (ring->idx + 1) % ring->entries; 1386 } 1387 1388 /* free dma of this ring */ 1389 pci_free_consistent(rtlpci->pdev, 1390 sizeof(*ring->desc) * ring->entries, 1391 ring->desc, ring->dma); 1392 ring->desc = NULL; 1393 if (rtlpriv->use_new_trx_flow) { 1394 pci_free_consistent(rtlpci->pdev, 1395 sizeof(*ring->buffer_desc) * ring->entries, 1396 ring->buffer_desc, ring->buffer_desc_dma); 1397 ring->buffer_desc = NULL; 1398 } 1399 } 1400 1401 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1402 { 1403 struct rtl_priv *rtlpriv = rtl_priv(hw); 1404 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1405 int i; 1406 1407 /* free every desc in this ring */ 1408 for (i = 0; i < rtlpci->rxringcount; i++) { 1409 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i]; 1410 1411 if (!skb) 1412 continue; 1413 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), 1414 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 1415 kfree_skb(skb); 1416 } 1417 1418 /* free dma of this ring */ 1419 if (rtlpriv->use_new_trx_flow) { 1420 pci_free_consistent(rtlpci->pdev, 1421 sizeof(*rtlpci->rx_ring[rxring_idx]. 1422 buffer_desc) * rtlpci->rxringcount, 1423 rtlpci->rx_ring[rxring_idx].buffer_desc, 1424 rtlpci->rx_ring[rxring_idx].dma); 1425 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL; 1426 } else { 1427 pci_free_consistent(rtlpci->pdev, 1428 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1429 rtlpci->rxringcount, 1430 rtlpci->rx_ring[rxring_idx].desc, 1431 rtlpci->rx_ring[rxring_idx].dma); 1432 rtlpci->rx_ring[rxring_idx].desc = NULL; 1433 } 1434 } 1435 1436 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw) 1437 { 1438 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1439 int ret; 1440 int i, rxring_idx; 1441 1442 /* rxring_idx 0:RX_MPDU_QUEUE 1443 * rxring_idx 1:RX_CMD_QUEUE 1444 */ 1445 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1446 ret = _rtl_pci_init_rx_ring(hw, rxring_idx); 1447 if (ret) 1448 return ret; 1449 } 1450 1451 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1452 ret = _rtl_pci_init_tx_ring(hw, i, 1453 rtlpci->txringcount[i]); 1454 if (ret) 1455 goto err_free_rings; 1456 } 1457 1458 return 0; 1459 1460 err_free_rings: 1461 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1462 _rtl_pci_free_rx_ring(hw, rxring_idx); 1463 1464 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1465 if (rtlpci->tx_ring[i].desc || 1466 rtlpci->tx_ring[i].buffer_desc) 1467 _rtl_pci_free_tx_ring(hw, i); 1468 1469 return 1; 1470 } 1471 1472 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw) 1473 { 1474 u32 i, rxring_idx; 1475 1476 /*free rx rings */ 1477 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1478 _rtl_pci_free_rx_ring(hw, rxring_idx); 1479 1480 /*free tx rings */ 1481 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1482 _rtl_pci_free_tx_ring(hw, i); 1483 1484 return 0; 1485 } 1486 1487 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw) 1488 { 1489 struct rtl_priv *rtlpriv = rtl_priv(hw); 1490 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1491 int i, rxring_idx; 1492 unsigned long flags; 1493 u8 tmp_one = 1; 1494 u32 bufferaddress; 1495 /* rxring_idx 0:RX_MPDU_QUEUE */ 1496 /* rxring_idx 1:RX_CMD_QUEUE */ 1497 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1498 /* force the rx_ring[RX_MPDU_QUEUE/ 1499 * RX_CMD_QUEUE].idx to the first one 1500 *new trx flow, do nothing 1501 */ 1502 if (!rtlpriv->use_new_trx_flow && 1503 rtlpci->rx_ring[rxring_idx].desc) { 1504 struct rtl_rx_desc *entry = NULL; 1505 1506 rtlpci->rx_ring[rxring_idx].idx = 0; 1507 for (i = 0; i < rtlpci->rxringcount; i++) { 1508 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1509 bufferaddress = 1510 rtlpriv->cfg->ops->get_desc((u8 *)entry, 1511 false , HW_DESC_RXBUFF_ADDR); 1512 memset((u8 *)entry , 0 , 1513 sizeof(*rtlpci->rx_ring 1514 [rxring_idx].desc));/*clear one entry*/ 1515 if (rtlpriv->use_new_trx_flow) { 1516 rtlpriv->cfg->ops->set_desc(hw, 1517 (u8 *)entry, false, 1518 HW_DESC_RX_PREPARE, 1519 (u8 *)&bufferaddress); 1520 } else { 1521 rtlpriv->cfg->ops->set_desc(hw, 1522 (u8 *)entry, false, 1523 HW_DESC_RXBUFF_ADDR, 1524 (u8 *)&bufferaddress); 1525 rtlpriv->cfg->ops->set_desc(hw, 1526 (u8 *)entry, false, 1527 HW_DESC_RXPKT_LEN, 1528 (u8 *)&rtlpci->rxbuffersize); 1529 rtlpriv->cfg->ops->set_desc(hw, 1530 (u8 *)entry, false, 1531 HW_DESC_RXOWN, 1532 (u8 *)&tmp_one); 1533 } 1534 } 1535 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1536 HW_DESC_RXERO, (u8 *)&tmp_one); 1537 } 1538 rtlpci->rx_ring[rxring_idx].idx = 0; 1539 } 1540 1541 /* 1542 *after reset, release previous pending packet, 1543 *and force the tx idx to the first one 1544 */ 1545 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1546 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1547 if (rtlpci->tx_ring[i].desc || 1548 rtlpci->tx_ring[i].buffer_desc) { 1549 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i]; 1550 1551 while (skb_queue_len(&ring->queue)) { 1552 u8 *entry; 1553 struct sk_buff *skb = 1554 __skb_dequeue(&ring->queue); 1555 if (rtlpriv->use_new_trx_flow) 1556 entry = (u8 *)(&ring->buffer_desc 1557 [ring->idx]); 1558 else 1559 entry = (u8 *)(&ring->desc[ring->idx]); 1560 1561 pci_unmap_single(rtlpci->pdev, 1562 rtlpriv->cfg->ops-> 1563 get_desc((u8 *) 1564 entry, 1565 true, 1566 HW_DESC_TXBUFF_ADDR), 1567 skb->len, PCI_DMA_TODEVICE); 1568 dev_kfree_skb_irq(skb); 1569 ring->idx = (ring->idx + 1) % ring->entries; 1570 } 1571 ring->idx = 0; 1572 } 1573 } 1574 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1575 1576 return 0; 1577 } 1578 1579 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw, 1580 struct ieee80211_sta *sta, 1581 struct sk_buff *skb) 1582 { 1583 struct rtl_priv *rtlpriv = rtl_priv(hw); 1584 struct rtl_sta_info *sta_entry = NULL; 1585 u8 tid = rtl_get_tid(skb); 1586 __le16 fc = rtl_get_fc(skb); 1587 1588 if (!sta) 1589 return false; 1590 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1591 1592 if (!rtlpriv->rtlhal.earlymode_enable) 1593 return false; 1594 if (ieee80211_is_nullfunc(fc)) 1595 return false; 1596 if (ieee80211_is_qos_nullfunc(fc)) 1597 return false; 1598 if (ieee80211_is_pspoll(fc)) 1599 return false; 1600 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL) 1601 return false; 1602 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE) 1603 return false; 1604 if (tid > 7) 1605 return false; 1606 1607 /* maybe every tid should be checked */ 1608 if (!rtlpriv->link_info.higher_busytxtraffic[tid]) 1609 return false; 1610 1611 spin_lock_bh(&rtlpriv->locks.waitq_lock); 1612 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb); 1613 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 1614 1615 return true; 1616 } 1617 1618 static int rtl_pci_tx(struct ieee80211_hw *hw, 1619 struct ieee80211_sta *sta, 1620 struct sk_buff *skb, 1621 struct rtl_tcb_desc *ptcb_desc) 1622 { 1623 struct rtl_priv *rtlpriv = rtl_priv(hw); 1624 struct rtl_sta_info *sta_entry = NULL; 1625 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1626 struct rtl8192_tx_ring *ring; 1627 struct rtl_tx_desc *pdesc; 1628 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL; 1629 u16 idx; 1630 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb); 1631 unsigned long flags; 1632 struct ieee80211_hdr *hdr = rtl_get_hdr(skb); 1633 __le16 fc = rtl_get_fc(skb); 1634 u8 *pda_addr = hdr->addr1; 1635 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1636 /*ssn */ 1637 u8 tid = 0; 1638 u16 seq_number = 0; 1639 u8 own; 1640 u8 temp_one = 1; 1641 1642 if (ieee80211_is_mgmt(fc)) 1643 rtl_tx_mgmt_proc(hw, skb); 1644 1645 if (rtlpriv->psc.sw_ps_enabled) { 1646 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) && 1647 !ieee80211_has_pm(fc)) 1648 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1649 } 1650 1651 rtl_action_proc(hw, skb, true); 1652 1653 if (is_multicast_ether_addr(pda_addr)) 1654 rtlpriv->stats.txbytesmulticast += skb->len; 1655 else if (is_broadcast_ether_addr(pda_addr)) 1656 rtlpriv->stats.txbytesbroadcast += skb->len; 1657 else 1658 rtlpriv->stats.txbytesunicast += skb->len; 1659 1660 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1661 ring = &rtlpci->tx_ring[hw_queue]; 1662 if (hw_queue != BEACON_QUEUE) { 1663 if (rtlpriv->use_new_trx_flow) 1664 idx = ring->cur_tx_wp; 1665 else 1666 idx = (ring->idx + skb_queue_len(&ring->queue)) % 1667 ring->entries; 1668 } else { 1669 idx = 0; 1670 } 1671 1672 pdesc = &ring->desc[idx]; 1673 if (rtlpriv->use_new_trx_flow) { 1674 ptx_bd_desc = &ring->buffer_desc[idx]; 1675 } else { 1676 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *)pdesc, 1677 true, HW_DESC_OWN); 1678 1679 if ((own == 1) && (hw_queue != BEACON_QUEUE)) { 1680 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1681 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1682 hw_queue, ring->idx, idx, 1683 skb_queue_len(&ring->queue)); 1684 1685 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, 1686 flags); 1687 return skb->len; 1688 } 1689 } 1690 1691 if (rtlpriv->cfg->ops->get_available_desc && 1692 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) { 1693 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1694 "get_available_desc fail\n"); 1695 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, 1696 flags); 1697 return skb->len; 1698 } 1699 1700 if (ieee80211_is_data_qos(fc)) { 1701 tid = rtl_get_tid(skb); 1702 if (sta) { 1703 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1704 seq_number = (le16_to_cpu(hdr->seq_ctrl) & 1705 IEEE80211_SCTL_SEQ) >> 4; 1706 seq_number += 1; 1707 1708 if (!ieee80211_has_morefrags(hdr->frame_control)) 1709 sta_entry->tids[tid].seq_number = seq_number; 1710 } 1711 } 1712 1713 if (ieee80211_is_data(fc)) 1714 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX); 1715 1716 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1717 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc); 1718 1719 __skb_queue_tail(&ring->queue, skb); 1720 1721 if (rtlpriv->use_new_trx_flow) { 1722 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1723 HW_DESC_OWN, &hw_queue); 1724 } else { 1725 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1726 HW_DESC_OWN, &temp_one); 1727 } 1728 1729 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 && 1730 hw_queue != BEACON_QUEUE) { 1731 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 1732 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1733 hw_queue, ring->idx, idx, 1734 skb_queue_len(&ring->queue)); 1735 1736 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 1737 } 1738 1739 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1740 1741 rtlpriv->cfg->ops->tx_polling(hw, hw_queue); 1742 1743 return 0; 1744 } 1745 1746 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1747 { 1748 struct rtl_priv *rtlpriv = rtl_priv(hw); 1749 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1750 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1751 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1752 u16 i = 0; 1753 int queue_id; 1754 struct rtl8192_tx_ring *ring; 1755 1756 if (mac->skip_scan) 1757 return; 1758 1759 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) { 1760 u32 queue_len; 1761 1762 if (((queues >> queue_id) & 0x1) == 0) { 1763 queue_id--; 1764 continue; 1765 } 1766 ring = &pcipriv->dev.tx_ring[queue_id]; 1767 queue_len = skb_queue_len(&ring->queue); 1768 if (queue_len == 0 || queue_id == BEACON_QUEUE || 1769 queue_id == TXCMD_QUEUE) { 1770 queue_id--; 1771 continue; 1772 } else { 1773 msleep(20); 1774 i++; 1775 } 1776 1777 /* we just wait 1s for all queues */ 1778 if (rtlpriv->psc.rfpwr_state == ERFOFF || 1779 is_hal_stop(rtlhal) || i >= 200) 1780 return; 1781 } 1782 } 1783 1784 static void rtl_pci_deinit(struct ieee80211_hw *hw) 1785 { 1786 struct rtl_priv *rtlpriv = rtl_priv(hw); 1787 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1788 1789 _rtl_pci_deinit_trx_ring(hw); 1790 1791 synchronize_irq(rtlpci->pdev->irq); 1792 tasklet_kill(&rtlpriv->works.irq_tasklet); 1793 cancel_work_sync(&rtlpriv->works.lps_change_work); 1794 1795 flush_workqueue(rtlpriv->works.rtl_wq); 1796 destroy_workqueue(rtlpriv->works.rtl_wq); 1797 1798 } 1799 1800 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev) 1801 { 1802 struct rtl_priv *rtlpriv = rtl_priv(hw); 1803 int err; 1804 1805 _rtl_pci_init_struct(hw, pdev); 1806 1807 err = _rtl_pci_init_trx_ring(hw); 1808 if (err) { 1809 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1810 "tx ring initialization failed\n"); 1811 return err; 1812 } 1813 1814 return 0; 1815 } 1816 1817 static int rtl_pci_start(struct ieee80211_hw *hw) 1818 { 1819 struct rtl_priv *rtlpriv = rtl_priv(hw); 1820 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1821 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1822 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1823 1824 int err; 1825 1826 rtl_pci_reset_trx_ring(hw); 1827 1828 rtlpci->driver_is_goingto_unload = false; 1829 if (rtlpriv->cfg->ops->get_btc_status && 1830 rtlpriv->cfg->ops->get_btc_status()) { 1831 rtlpriv->btcoexist.btc_ops->btc_init_variables(rtlpriv); 1832 rtlpriv->btcoexist.btc_ops->btc_init_hal_vars(rtlpriv); 1833 } 1834 err = rtlpriv->cfg->ops->hw_init(hw); 1835 if (err) { 1836 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1837 "Failed to config hardware!\n"); 1838 return err; 1839 } 1840 1841 rtlpriv->cfg->ops->enable_interrupt(hw); 1842 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); 1843 1844 rtl_init_rx_config(hw); 1845 1846 /*should be after adapter start and interrupt enable. */ 1847 set_hal_start(rtlhal); 1848 1849 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1850 1851 rtlpci->up_first_time = false; 1852 1853 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "rtl_pci_start OK\n"); 1854 return 0; 1855 } 1856 1857 static void rtl_pci_stop(struct ieee80211_hw *hw) 1858 { 1859 struct rtl_priv *rtlpriv = rtl_priv(hw); 1860 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1861 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1862 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1863 unsigned long flags; 1864 u8 RFInProgressTimeOut = 0; 1865 1866 if (rtlpriv->cfg->ops->get_btc_status()) 1867 rtlpriv->btcoexist.btc_ops->btc_halt_notify(); 1868 1869 /* 1870 *should be before disable interrupt&adapter 1871 *and will do it immediately. 1872 */ 1873 set_hal_stop(rtlhal); 1874 1875 rtlpci->driver_is_goingto_unload = true; 1876 rtlpriv->cfg->ops->disable_interrupt(hw); 1877 cancel_work_sync(&rtlpriv->works.lps_change_work); 1878 1879 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1880 while (ppsc->rfchange_inprogress) { 1881 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1882 if (RFInProgressTimeOut > 100) { 1883 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1884 break; 1885 } 1886 mdelay(1); 1887 RFInProgressTimeOut++; 1888 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1889 } 1890 ppsc->rfchange_inprogress = true; 1891 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1892 1893 rtlpriv->cfg->ops->hw_disable(hw); 1894 /* some things are not needed if firmware not available */ 1895 if (!rtlpriv->max_fw_size) 1896 return; 1897 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1898 1899 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1900 ppsc->rfchange_inprogress = false; 1901 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1902 1903 rtl_pci_enable_aspm(hw); 1904 } 1905 1906 static bool _rtl_pci_find_adapter(struct pci_dev *pdev, 1907 struct ieee80211_hw *hw) 1908 { 1909 struct rtl_priv *rtlpriv = rtl_priv(hw); 1910 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1911 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1912 struct pci_dev *bridge_pdev = pdev->bus->self; 1913 u16 venderid; 1914 u16 deviceid; 1915 u8 revisionid; 1916 u16 irqline; 1917 u8 tmp; 1918 1919 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1920 venderid = pdev->vendor; 1921 deviceid = pdev->device; 1922 pci_read_config_byte(pdev, 0x8, &revisionid); 1923 pci_read_config_word(pdev, 0x3C, &irqline); 1924 1925 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses 1926 * r8192e_pci, and RTL8192SE, which uses this driver. If the 1927 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then 1928 * the correct driver is r8192e_pci, thus this routine should 1929 * return false. 1930 */ 1931 if (deviceid == RTL_PCI_8192SE_DID && 1932 revisionid == RTL_PCI_REVISION_ID_8192PCIE) 1933 return false; 1934 1935 if (deviceid == RTL_PCI_8192_DID || 1936 deviceid == RTL_PCI_0044_DID || 1937 deviceid == RTL_PCI_0047_DID || 1938 deviceid == RTL_PCI_8192SE_DID || 1939 deviceid == RTL_PCI_8174_DID || 1940 deviceid == RTL_PCI_8173_DID || 1941 deviceid == RTL_PCI_8172_DID || 1942 deviceid == RTL_PCI_8171_DID) { 1943 switch (revisionid) { 1944 case RTL_PCI_REVISION_ID_8192PCIE: 1945 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1946 "8192 PCI-E is found - vid/did=%x/%x\n", 1947 venderid, deviceid); 1948 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E; 1949 return false; 1950 case RTL_PCI_REVISION_ID_8192SE: 1951 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1952 "8192SE is found - vid/did=%x/%x\n", 1953 venderid, deviceid); 1954 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1955 break; 1956 default: 1957 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1958 "Err: Unknown device - vid/did=%x/%x\n", 1959 venderid, deviceid); 1960 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1961 break; 1962 1963 } 1964 } else if (deviceid == RTL_PCI_8723AE_DID) { 1965 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE; 1966 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1967 "8723AE PCI-E is found - " 1968 "vid/did=%x/%x\n", venderid, deviceid); 1969 } else if (deviceid == RTL_PCI_8192CET_DID || 1970 deviceid == RTL_PCI_8192CE_DID || 1971 deviceid == RTL_PCI_8191CE_DID || 1972 deviceid == RTL_PCI_8188CE_DID) { 1973 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE; 1974 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1975 "8192C PCI-E is found - vid/did=%x/%x\n", 1976 venderid, deviceid); 1977 } else if (deviceid == RTL_PCI_8192DE_DID || 1978 deviceid == RTL_PCI_8192DE_DID2) { 1979 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE; 1980 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1981 "8192D PCI-E is found - vid/did=%x/%x\n", 1982 venderid, deviceid); 1983 } else if (deviceid == RTL_PCI_8188EE_DID) { 1984 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE; 1985 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1986 "Find adapter, Hardware type is 8188EE\n"); 1987 } else if (deviceid == RTL_PCI_8723BE_DID) { 1988 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE; 1989 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, 1990 "Find adapter, Hardware type is 8723BE\n"); 1991 } else if (deviceid == RTL_PCI_8192EE_DID) { 1992 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE; 1993 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, 1994 "Find adapter, Hardware type is 8192EE\n"); 1995 } else if (deviceid == RTL_PCI_8821AE_DID) { 1996 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE; 1997 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, 1998 "Find adapter, Hardware type is 8821AE\n"); 1999 } else if (deviceid == RTL_PCI_8812AE_DID) { 2000 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE; 2001 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, 2002 "Find adapter, Hardware type is 8812AE\n"); 2003 } else { 2004 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2005 "Err: Unknown device - vid/did=%x/%x\n", 2006 venderid, deviceid); 2007 2008 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE; 2009 } 2010 2011 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) { 2012 if (revisionid == 0 || revisionid == 1) { 2013 if (revisionid == 0) { 2014 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2015 "Find 92DE MAC0\n"); 2016 rtlhal->interfaceindex = 0; 2017 } else if (revisionid == 1) { 2018 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2019 "Find 92DE MAC1\n"); 2020 rtlhal->interfaceindex = 1; 2021 } 2022 } else { 2023 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2024 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", 2025 venderid, deviceid, revisionid); 2026 rtlhal->interfaceindex = 0; 2027 } 2028 } 2029 2030 /* 92ee use new trx flow */ 2031 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) 2032 rtlpriv->use_new_trx_flow = true; 2033 else 2034 rtlpriv->use_new_trx_flow = false; 2035 2036 /*find bus info */ 2037 pcipriv->ndis_adapter.busnumber = pdev->bus->number; 2038 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn); 2039 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn); 2040 2041 /*find bridge info */ 2042 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 2043 /* some ARM have no bridge_pdev and will crash here 2044 * so we should check if bridge_pdev is NULL 2045 */ 2046 if (bridge_pdev) { 2047 /*find bridge info if available */ 2048 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor; 2049 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { 2050 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { 2051 pcipriv->ndis_adapter.pcibridge_vendor = tmp; 2052 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2053 "Pci Bridge Vendor is found index: %d\n", 2054 tmp); 2055 break; 2056 } 2057 } 2058 } 2059 2060 if (pcipriv->ndis_adapter.pcibridge_vendor != 2061 PCI_BRIDGE_VENDOR_UNKNOWN) { 2062 pcipriv->ndis_adapter.pcibridge_busnum = 2063 bridge_pdev->bus->number; 2064 pcipriv->ndis_adapter.pcibridge_devnum = 2065 PCI_SLOT(bridge_pdev->devfn); 2066 pcipriv->ndis_adapter.pcibridge_funcnum = 2067 PCI_FUNC(bridge_pdev->devfn); 2068 pcipriv->ndis_adapter.pcibridge_pciehdr_offset = 2069 pci_pcie_cap(bridge_pdev); 2070 pcipriv->ndis_adapter.num4bytes = 2071 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4; 2072 2073 rtl_pci_get_linkcontrol_field(hw); 2074 2075 if (pcipriv->ndis_adapter.pcibridge_vendor == 2076 PCI_BRIDGE_VENDOR_AMD) { 2077 pcipriv->ndis_adapter.amd_l1_patch = 2078 rtl_pci_get_amd_l1_patch(hw); 2079 } 2080 } 2081 2082 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2083 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", 2084 pcipriv->ndis_adapter.busnumber, 2085 pcipriv->ndis_adapter.devnumber, 2086 pcipriv->ndis_adapter.funcnumber, 2087 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); 2088 2089 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2090 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n", 2091 pcipriv->ndis_adapter.pcibridge_busnum, 2092 pcipriv->ndis_adapter.pcibridge_devnum, 2093 pcipriv->ndis_adapter.pcibridge_funcnum, 2094 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], 2095 pcipriv->ndis_adapter.pcibridge_pciehdr_offset, 2096 pcipriv->ndis_adapter.pcibridge_linkctrlreg, 2097 pcipriv->ndis_adapter.amd_l1_patch); 2098 2099 rtl_pci_parse_configuration(pdev, hw); 2100 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list); 2101 2102 return true; 2103 } 2104 2105 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw) 2106 { 2107 struct rtl_priv *rtlpriv = rtl_priv(hw); 2108 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2109 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2110 int ret; 2111 2112 ret = pci_enable_msi(rtlpci->pdev); 2113 if (ret < 0) 2114 return ret; 2115 2116 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2117 IRQF_SHARED, KBUILD_MODNAME, hw); 2118 if (ret < 0) { 2119 pci_disable_msi(rtlpci->pdev); 2120 return ret; 2121 } 2122 2123 rtlpci->using_msi = true; 2124 2125 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG, 2126 "MSI Interrupt Mode!\n"); 2127 return 0; 2128 } 2129 2130 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw) 2131 { 2132 struct rtl_priv *rtlpriv = rtl_priv(hw); 2133 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2134 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2135 int ret; 2136 2137 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2138 IRQF_SHARED, KBUILD_MODNAME, hw); 2139 if (ret < 0) 2140 return ret; 2141 2142 rtlpci->using_msi = false; 2143 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG, 2144 "Pin-based Interrupt Mode!\n"); 2145 return 0; 2146 } 2147 2148 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw) 2149 { 2150 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2151 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2152 int ret; 2153 2154 if (rtlpci->msi_support) { 2155 ret = rtl_pci_intr_mode_msi(hw); 2156 if (ret < 0) 2157 ret = rtl_pci_intr_mode_legacy(hw); 2158 } else { 2159 ret = rtl_pci_intr_mode_legacy(hw); 2160 } 2161 return ret; 2162 } 2163 2164 int rtl_pci_probe(struct pci_dev *pdev, 2165 const struct pci_device_id *id) 2166 { 2167 struct ieee80211_hw *hw = NULL; 2168 2169 struct rtl_priv *rtlpriv = NULL; 2170 struct rtl_pci_priv *pcipriv = NULL; 2171 struct rtl_pci *rtlpci; 2172 unsigned long pmem_start, pmem_len, pmem_flags; 2173 int err; 2174 2175 err = pci_enable_device(pdev); 2176 if (err) { 2177 RT_ASSERT(false, "%s : Cannot enable new PCI device\n", 2178 pci_name(pdev)); 2179 return err; 2180 } 2181 2182 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 2183 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 2184 RT_ASSERT(false, 2185 "Unable to obtain 32bit DMA for consistent allocations\n"); 2186 err = -ENOMEM; 2187 goto fail1; 2188 } 2189 } 2190 2191 pci_set_master(pdev); 2192 2193 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) + 2194 sizeof(struct rtl_priv), &rtl_ops); 2195 if (!hw) { 2196 RT_ASSERT(false, 2197 "%s : ieee80211 alloc failed\n", pci_name(pdev)); 2198 err = -ENOMEM; 2199 goto fail1; 2200 } 2201 2202 SET_IEEE80211_DEV(hw, &pdev->dev); 2203 pci_set_drvdata(pdev, hw); 2204 2205 rtlpriv = hw->priv; 2206 rtlpriv->hw = hw; 2207 pcipriv = (void *)rtlpriv->priv; 2208 pcipriv->dev.pdev = pdev; 2209 init_completion(&rtlpriv->firmware_loading_complete); 2210 /*proximity init here*/ 2211 rtlpriv->proximity.proxim_on = false; 2212 2213 pcipriv = (void *)rtlpriv->priv; 2214 pcipriv->dev.pdev = pdev; 2215 2216 /* init cfg & intf_ops */ 2217 rtlpriv->rtlhal.interface = INTF_PCI; 2218 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data); 2219 rtlpriv->intf_ops = &rtl_pci_ops; 2220 rtlpriv->glb_var = &rtl_global_var; 2221 2222 /* 2223 *init dbgp flags before all 2224 *other functions, because we will 2225 *use it in other funtions like 2226 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA 2227 *you can not use these macro 2228 *before this 2229 */ 2230 rtl_dbgp_flag_init(hw); 2231 2232 /* MEM map */ 2233 err = pci_request_regions(pdev, KBUILD_MODNAME); 2234 if (err) { 2235 RT_ASSERT(false, "Can't obtain PCI resources\n"); 2236 goto fail1; 2237 } 2238 2239 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id); 2240 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id); 2241 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id); 2242 2243 /*shared mem start */ 2244 rtlpriv->io.pci_mem_start = 2245 (unsigned long)pci_iomap(pdev, 2246 rtlpriv->cfg->bar_id, pmem_len); 2247 if (rtlpriv->io.pci_mem_start == 0) { 2248 RT_ASSERT(false, "Can't map PCI mem\n"); 2249 err = -ENOMEM; 2250 goto fail2; 2251 } 2252 2253 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2254 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", 2255 pmem_start, pmem_len, pmem_flags, 2256 rtlpriv->io.pci_mem_start); 2257 2258 /* Disable Clk Request */ 2259 pci_write_config_byte(pdev, 0x81, 0); 2260 /* leave D3 mode */ 2261 pci_write_config_byte(pdev, 0x44, 0); 2262 pci_write_config_byte(pdev, 0x04, 0x06); 2263 pci_write_config_byte(pdev, 0x04, 0x07); 2264 2265 /* find adapter */ 2266 if (!_rtl_pci_find_adapter(pdev, hw)) { 2267 err = -ENODEV; 2268 goto fail3; 2269 } 2270 2271 /* Init IO handler */ 2272 _rtl_pci_io_handler_init(&pdev->dev, hw); 2273 2274 /*like read eeprom and so on */ 2275 rtlpriv->cfg->ops->read_eeprom_info(hw); 2276 2277 if (rtlpriv->cfg->ops->init_sw_vars(hw)) { 2278 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Can't init_sw_vars\n"); 2279 err = -ENODEV; 2280 goto fail3; 2281 } 2282 rtlpriv->cfg->ops->init_sw_leds(hw); 2283 2284 /*aspm */ 2285 rtl_pci_init_aspm(hw); 2286 2287 /* Init mac80211 sw */ 2288 err = rtl_init_core(hw); 2289 if (err) { 2290 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2291 "Can't allocate sw for mac80211\n"); 2292 goto fail3; 2293 } 2294 2295 /* Init PCI sw */ 2296 err = rtl_pci_init(hw, pdev); 2297 if (err) { 2298 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Failed to init PCI\n"); 2299 goto fail3; 2300 } 2301 2302 err = ieee80211_register_hw(hw); 2303 if (err) { 2304 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2305 "Can't register mac80211 hw.\n"); 2306 err = -ENODEV; 2307 goto fail3; 2308 } 2309 rtlpriv->mac80211.mac80211_registered = 1; 2310 2311 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group); 2312 if (err) { 2313 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2314 "failed to create sysfs device attributes\n"); 2315 goto fail3; 2316 } 2317 2318 /*init rfkill */ 2319 rtl_init_rfkill(hw); /* Init PCI sw */ 2320 2321 rtlpci = rtl_pcidev(pcipriv); 2322 err = rtl_pci_intr_mode_decide(hw); 2323 if (err) { 2324 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2325 "%s: failed to register IRQ handler\n", 2326 wiphy_name(hw->wiphy)); 2327 goto fail3; 2328 } 2329 rtlpci->irq_alloc = 1; 2330 2331 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2332 return 0; 2333 2334 fail3: 2335 pci_set_drvdata(pdev, NULL); 2336 rtl_deinit_core(hw); 2337 2338 if (rtlpriv->io.pci_mem_start != 0) 2339 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2340 2341 fail2: 2342 pci_release_regions(pdev); 2343 complete(&rtlpriv->firmware_loading_complete); 2344 2345 fail1: 2346 if (hw) 2347 ieee80211_free_hw(hw); 2348 pci_disable_device(pdev); 2349 2350 return err; 2351 2352 } 2353 EXPORT_SYMBOL(rtl_pci_probe); 2354 2355 void rtl_pci_disconnect(struct pci_dev *pdev) 2356 { 2357 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2358 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2359 struct rtl_priv *rtlpriv = rtl_priv(hw); 2360 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2361 struct rtl_mac *rtlmac = rtl_mac(rtlpriv); 2362 2363 /* just in case driver is removed before firmware callback */ 2364 wait_for_completion(&rtlpriv->firmware_loading_complete); 2365 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2366 2367 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group); 2368 2369 /*ieee80211_unregister_hw will call ops_stop */ 2370 if (rtlmac->mac80211_registered == 1) { 2371 ieee80211_unregister_hw(hw); 2372 rtlmac->mac80211_registered = 0; 2373 } else { 2374 rtl_deinit_deferred_work(hw); 2375 rtlpriv->intf_ops->adapter_stop(hw); 2376 } 2377 rtlpriv->cfg->ops->disable_interrupt(hw); 2378 2379 /*deinit rfkill */ 2380 rtl_deinit_rfkill(hw); 2381 2382 rtl_pci_deinit(hw); 2383 rtl_deinit_core(hw); 2384 rtlpriv->cfg->ops->deinit_sw_vars(hw); 2385 2386 if (rtlpci->irq_alloc) { 2387 free_irq(rtlpci->pdev->irq, hw); 2388 rtlpci->irq_alloc = 0; 2389 } 2390 2391 if (rtlpci->using_msi) 2392 pci_disable_msi(rtlpci->pdev); 2393 2394 list_del(&rtlpriv->list); 2395 if (rtlpriv->io.pci_mem_start != 0) { 2396 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2397 pci_release_regions(pdev); 2398 } 2399 2400 pci_disable_device(pdev); 2401 2402 rtl_pci_disable_aspm(hw); 2403 2404 pci_set_drvdata(pdev, NULL); 2405 2406 ieee80211_free_hw(hw); 2407 } 2408 EXPORT_SYMBOL(rtl_pci_disconnect); 2409 2410 #ifdef CONFIG_PM_SLEEP 2411 /*************************************** 2412 kernel pci power state define: 2413 PCI_D0 ((pci_power_t __force) 0) 2414 PCI_D1 ((pci_power_t __force) 1) 2415 PCI_D2 ((pci_power_t __force) 2) 2416 PCI_D3hot ((pci_power_t __force) 3) 2417 PCI_D3cold ((pci_power_t __force) 4) 2418 PCI_UNKNOWN ((pci_power_t __force) 5) 2419 2420 This function is called when system 2421 goes into suspend state mac80211 will 2422 call rtl_mac_stop() from the mac80211 2423 suspend function first, So there is 2424 no need to call hw_disable here. 2425 ****************************************/ 2426 int rtl_pci_suspend(struct device *dev) 2427 { 2428 struct pci_dev *pdev = to_pci_dev(dev); 2429 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2430 struct rtl_priv *rtlpriv = rtl_priv(hw); 2431 2432 rtlpriv->cfg->ops->hw_suspend(hw); 2433 rtl_deinit_rfkill(hw); 2434 2435 return 0; 2436 } 2437 EXPORT_SYMBOL(rtl_pci_suspend); 2438 2439 int rtl_pci_resume(struct device *dev) 2440 { 2441 struct pci_dev *pdev = to_pci_dev(dev); 2442 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2443 struct rtl_priv *rtlpriv = rtl_priv(hw); 2444 2445 rtlpriv->cfg->ops->hw_resume(hw); 2446 rtl_init_rfkill(hw); 2447 return 0; 2448 } 2449 EXPORT_SYMBOL(rtl_pci_resume); 2450 #endif /* CONFIG_PM_SLEEP */ 2451 2452 const struct rtl_intf_ops rtl_pci_ops = { 2453 .read_efuse_byte = read_efuse_byte, 2454 .adapter_start = rtl_pci_start, 2455 .adapter_stop = rtl_pci_stop, 2456 .check_buddy_priv = rtl_pci_check_buddy_priv, 2457 .adapter_tx = rtl_pci_tx, 2458 .flush = rtl_pci_flush, 2459 .reset_trx_ring = rtl_pci_reset_trx_ring, 2460 .waitq_insert = rtl_pci_tx_chk_waitq_insert, 2461 2462 .disable_aspm = rtl_pci_disable_aspm, 2463 .enable_aspm = rtl_pci_enable_aspm, 2464 }; 2465