1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "wifi.h" 27 #include "core.h" 28 #include "pci.h" 29 #include "base.h" 30 #include "ps.h" 31 #include "efuse.h" 32 #include <linux/interrupt.h> 33 #include <linux/export.h> 34 #include <linux/kmemleak.h> 35 #include <linux/module.h> 36 37 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 38 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 39 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>"); 40 MODULE_LICENSE("GPL"); 41 MODULE_DESCRIPTION("PCI basic driver for rtlwifi"); 42 43 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { 44 INTEL_VENDOR_ID, 45 ATI_VENDOR_ID, 46 AMD_VENDOR_ID, 47 SIS_VENDOR_ID 48 }; 49 50 static const u8 ac_to_hwq[] = { 51 VO_QUEUE, 52 VI_QUEUE, 53 BE_QUEUE, 54 BK_QUEUE 55 }; 56 57 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb) 58 { 59 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 60 __le16 fc = rtl_get_fc(skb); 61 u8 queue_index = skb_get_queue_mapping(skb); 62 63 if (unlikely(ieee80211_is_beacon(fc))) 64 return BEACON_QUEUE; 65 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) 66 return MGNT_QUEUE; 67 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 68 if (ieee80211_is_nullfunc(fc)) 69 return HIGH_QUEUE; 70 71 return ac_to_hwq[queue_index]; 72 } 73 74 /* Update PCI dependent default settings*/ 75 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) 76 { 77 struct rtl_priv *rtlpriv = rtl_priv(hw); 78 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 79 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 80 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 81 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 82 u8 init_aspm; 83 84 ppsc->reg_rfps_level = 0; 85 ppsc->support_aspm = false; 86 87 /*Update PCI ASPM setting */ 88 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm; 89 switch (rtlpci->const_pci_aspm) { 90 case 0: 91 /*No ASPM */ 92 break; 93 94 case 1: 95 /*ASPM dynamically enabled/disable. */ 96 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; 97 break; 98 99 case 2: 100 /*ASPM with Clock Req dynamically enabled/disable. */ 101 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | 102 RT_RF_OFF_LEVL_CLK_REQ); 103 break; 104 105 case 3: 106 /* Always enable ASPM and Clock Req 107 * from initialization to halt. 108 */ 109 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); 110 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | 111 RT_RF_OFF_LEVL_CLK_REQ); 112 break; 113 114 case 4: 115 /* Always enable ASPM without Clock Req 116 * from initialization to halt. 117 */ 118 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | 119 RT_RF_OFF_LEVL_CLK_REQ); 120 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; 121 break; 122 } 123 124 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 125 126 /*Update Radio OFF setting */ 127 switch (rtlpci->const_hwsw_rfoff_d3) { 128 case 1: 129 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 130 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 131 break; 132 133 case 2: 134 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 135 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 136 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 137 break; 138 139 case 3: 140 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; 141 break; 142 } 143 144 /*Set HW definition to determine if it supports ASPM. */ 145 switch (rtlpci->const_support_pciaspm) { 146 case 0: 147 /*Not support ASPM. */ 148 ppsc->support_aspm = false; 149 break; 150 case 1: 151 /*Support ASPM. */ 152 ppsc->support_aspm = true; 153 ppsc->support_backdoor = true; 154 break; 155 case 2: 156 /*ASPM value set by chipset. */ 157 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) 158 ppsc->support_aspm = true; 159 break; 160 default: 161 pr_err("switch case %#x not processed\n", 162 rtlpci->const_support_pciaspm); 163 break; 164 } 165 166 /* toshiba aspm issue, toshiba will set aspm selfly 167 * so we should not set aspm in driver 168 */ 169 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm); 170 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE && 171 init_aspm == 0x43) 172 ppsc->support_aspm = false; 173 } 174 175 static bool _rtl_pci_platform_switch_device_pci_aspm( 176 struct ieee80211_hw *hw, 177 u8 value) 178 { 179 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 180 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 181 182 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE) 183 value |= 0x40; 184 185 pci_write_config_byte(rtlpci->pdev, 0x80, value); 186 187 return false; 188 } 189 190 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/ 191 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value) 192 { 193 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 194 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 195 196 pci_write_config_byte(rtlpci->pdev, 0x81, value); 197 198 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 199 udelay(100); 200 } 201 202 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ 203 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) 204 { 205 struct rtl_priv *rtlpriv = rtl_priv(hw); 206 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 207 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 208 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 209 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 210 u8 num4bytes = pcipriv->ndis_adapter.num4bytes; 211 /*Retrieve original configuration settings. */ 212 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg; 213 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter. 214 pcibridge_linkctrlreg; 215 u16 aspmlevel = 0; 216 u8 tmp_u1b = 0; 217 218 if (!ppsc->support_aspm) 219 return; 220 221 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 222 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 223 "PCI(Bridge) UNKNOWN\n"); 224 225 return; 226 } 227 228 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 229 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 230 _rtl_pci_switch_clk_req(hw, 0x0); 231 } 232 233 /*for promising device will in L0 state after an I/O. */ 234 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b); 235 236 /*Set corresponding value. */ 237 aspmlevel |= BIT(0) | BIT(1); 238 linkctrl_reg &= ~aspmlevel; 239 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1)); 240 241 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg); 242 udelay(50); 243 244 /*4 Disable Pci Bridge ASPM */ 245 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), 246 pcibridge_linkctrlreg); 247 248 udelay(50); 249 } 250 251 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for 252 *power saving We should follow the sequence to enable 253 *RTL8192SE first then enable Pci Bridge ASPM 254 *or the system will show bluescreen. 255 */ 256 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) 257 { 258 struct rtl_priv *rtlpriv = rtl_priv(hw); 259 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 260 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 261 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 262 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 263 u8 num4bytes = pcipriv->ndis_adapter.num4bytes; 264 u16 aspmlevel; 265 u8 u_pcibridge_aspmsetting; 266 u8 u_device_aspmsetting; 267 268 if (!ppsc->support_aspm) 269 return; 270 271 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 272 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 273 "PCI(Bridge) UNKNOWN\n"); 274 return; 275 } 276 277 /*4 Enable Pci Bridge ASPM */ 278 279 u_pcibridge_aspmsetting = 280 pcipriv->ndis_adapter.pcibridge_linkctrlreg | 281 rtlpci->const_hostpci_aspm_setting; 282 283 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) 284 u_pcibridge_aspmsetting &= ~BIT(0); 285 286 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), 287 u_pcibridge_aspmsetting); 288 289 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 290 "PlatformEnableASPM(): Write reg[%x] = %x\n", 291 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10), 292 u_pcibridge_aspmsetting); 293 294 udelay(50); 295 296 /*Get ASPM level (with/without Clock Req) */ 297 aspmlevel = rtlpci->const_devicepci_aspm_setting; 298 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg; 299 300 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/ 301 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */ 302 303 u_device_aspmsetting |= aspmlevel; 304 305 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting); 306 307 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 308 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level & 309 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0); 310 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 311 } 312 udelay(100); 313 } 314 315 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw) 316 { 317 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 318 319 bool status = false; 320 u8 offset_e0; 321 unsigned int offset_e4; 322 323 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0); 324 325 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0); 326 327 if (offset_e0 == 0xA0) { 328 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4); 329 if (offset_e4 & BIT(23)) 330 status = true; 331 } 332 333 return status; 334 } 335 336 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw, 337 struct rtl_priv **buddy_priv) 338 { 339 struct rtl_priv *rtlpriv = rtl_priv(hw); 340 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 341 bool find_buddy_priv = false; 342 struct rtl_priv *tpriv; 343 struct rtl_pci_priv *tpcipriv = NULL; 344 345 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) { 346 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list, 347 list) { 348 tpcipriv = (struct rtl_pci_priv *)tpriv->priv; 349 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 350 "pcipriv->ndis_adapter.funcnumber %x\n", 351 pcipriv->ndis_adapter.funcnumber); 352 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 353 "tpcipriv->ndis_adapter.funcnumber %x\n", 354 tpcipriv->ndis_adapter.funcnumber); 355 356 if (pcipriv->ndis_adapter.busnumber == 357 tpcipriv->ndis_adapter.busnumber && 358 pcipriv->ndis_adapter.devnumber == 359 tpcipriv->ndis_adapter.devnumber && 360 pcipriv->ndis_adapter.funcnumber != 361 tpcipriv->ndis_adapter.funcnumber) { 362 find_buddy_priv = true; 363 break; 364 } 365 } 366 } 367 368 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 369 "find_buddy_priv %d\n", find_buddy_priv); 370 371 if (find_buddy_priv) 372 *buddy_priv = tpriv; 373 374 return find_buddy_priv; 375 } 376 377 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw) 378 { 379 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 380 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 381 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset; 382 u8 linkctrl_reg; 383 u8 num4bbytes; 384 385 num4bbytes = (capabilityoffset + 0x10) / 4; 386 387 /*Read Link Control Register */ 388 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg); 389 390 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg; 391 } 392 393 static void rtl_pci_parse_configuration(struct pci_dev *pdev, 394 struct ieee80211_hw *hw) 395 { 396 struct rtl_priv *rtlpriv = rtl_priv(hw); 397 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 398 399 u8 tmp; 400 u16 linkctrl_reg; 401 402 /*Link Control Register */ 403 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg); 404 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg; 405 406 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", 407 pcipriv->ndis_adapter.linkctrl_reg); 408 409 pci_read_config_byte(pdev, 0x98, &tmp); 410 tmp |= BIT(4); 411 pci_write_config_byte(pdev, 0x98, tmp); 412 413 tmp = 0x17; 414 pci_write_config_byte(pdev, 0x70f, tmp); 415 } 416 417 static void rtl_pci_init_aspm(struct ieee80211_hw *hw) 418 { 419 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 420 421 _rtl_pci_update_default_setting(hw); 422 423 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { 424 /*Always enable ASPM & Clock Req. */ 425 rtl_pci_enable_aspm(hw); 426 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM); 427 } 428 } 429 430 static void _rtl_pci_io_handler_init(struct device *dev, 431 struct ieee80211_hw *hw) 432 { 433 struct rtl_priv *rtlpriv = rtl_priv(hw); 434 435 rtlpriv->io.dev = dev; 436 437 rtlpriv->io.write8_async = pci_write8_async; 438 rtlpriv->io.write16_async = pci_write16_async; 439 rtlpriv->io.write32_async = pci_write32_async; 440 441 rtlpriv->io.read8_sync = pci_read8_sync; 442 rtlpriv->io.read16_sync = pci_read16_sync; 443 rtlpriv->io.read32_sync = pci_read32_sync; 444 } 445 446 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw, 447 struct sk_buff *skb, 448 struct rtl_tcb_desc *tcb_desc, u8 tid) 449 { 450 struct rtl_priv *rtlpriv = rtl_priv(hw); 451 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 452 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 453 struct sk_buff *next_skb; 454 u8 additionlen = FCS_LEN; 455 456 /* here open is 4, wep/tkip is 8, aes is 12*/ 457 if (info->control.hw_key) 458 additionlen += info->control.hw_key->icv_len; 459 460 /* The most skb num is 6 */ 461 tcb_desc->empkt_num = 0; 462 spin_lock_bh(&rtlpriv->locks.waitq_lock); 463 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) { 464 struct ieee80211_tx_info *next_info; 465 466 next_info = IEEE80211_SKB_CB(next_skb); 467 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) { 468 tcb_desc->empkt_len[tcb_desc->empkt_num] = 469 next_skb->len + additionlen; 470 tcb_desc->empkt_num++; 471 } else { 472 break; 473 } 474 475 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid], 476 next_skb)) 477 break; 478 479 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num) 480 break; 481 } 482 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 483 484 return true; 485 } 486 487 /* just for early mode now */ 488 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw) 489 { 490 struct rtl_priv *rtlpriv = rtl_priv(hw); 491 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 492 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 493 struct sk_buff *skb = NULL; 494 struct ieee80211_tx_info *info = NULL; 495 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 496 int tid; 497 498 if (!rtlpriv->rtlhal.earlymode_enable) 499 return; 500 501 if (rtlpriv->dm.supp_phymode_switch && 502 (rtlpriv->easy_concurrent_ctl.switch_in_process || 503 (rtlpriv->buddy_priv && 504 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process))) 505 return; 506 /* we just use em for BE/BK/VI/VO */ 507 for (tid = 7; tid >= 0; tid--) { 508 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)]; 509 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; 510 511 while (!mac->act_scanning && 512 rtlpriv->psc.rfpwr_state == ERFON) { 513 struct rtl_tcb_desc tcb_desc; 514 515 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 516 517 spin_lock_bh(&rtlpriv->locks.waitq_lock); 518 if (!skb_queue_empty(&mac->skb_waitq[tid]) && 519 (ring->entries - skb_queue_len(&ring->queue) > 520 rtlhal->max_earlymode_num)) { 521 skb = skb_dequeue(&mac->skb_waitq[tid]); 522 } else { 523 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 524 break; 525 } 526 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 527 528 /* Some macaddr can't do early mode. like 529 * multicast/broadcast/no_qos data 530 */ 531 info = IEEE80211_SKB_CB(skb); 532 if (info->flags & IEEE80211_TX_CTL_AMPDU) 533 _rtl_update_earlymode_info(hw, skb, 534 &tcb_desc, tid); 535 536 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc); 537 } 538 } 539 } 540 541 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) 542 { 543 struct rtl_priv *rtlpriv = rtl_priv(hw); 544 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 545 546 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 547 548 while (skb_queue_len(&ring->queue)) { 549 struct sk_buff *skb; 550 struct ieee80211_tx_info *info; 551 __le16 fc; 552 u8 tid; 553 u8 *entry; 554 555 if (rtlpriv->use_new_trx_flow) 556 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 557 else 558 entry = (u8 *)(&ring->desc[ring->idx]); 559 560 if (rtlpriv->cfg->ops->get_available_desc && 561 rtlpriv->cfg->ops->get_available_desc(hw, prio) <= 1) { 562 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_DMESG, 563 "no available desc!\n"); 564 return; 565 } 566 567 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx)) 568 return; 569 ring->idx = (ring->idx + 1) % ring->entries; 570 571 skb = __skb_dequeue(&ring->queue); 572 pci_unmap_single(rtlpci->pdev, 573 rtlpriv->cfg->ops-> 574 get_desc(hw, (u8 *)entry, true, 575 HW_DESC_TXBUFF_ADDR), 576 skb->len, PCI_DMA_TODEVICE); 577 578 /* remove early mode header */ 579 if (rtlpriv->rtlhal.earlymode_enable) 580 skb_pull(skb, EM_HDR_LEN); 581 582 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, 583 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", 584 ring->idx, 585 skb_queue_len(&ring->queue), 586 *(u16 *)(skb->data + 22)); 587 588 if (prio == TXCMD_QUEUE) { 589 dev_kfree_skb(skb); 590 goto tx_status_ok; 591 } 592 593 /* for sw LPS, just after NULL skb send out, we can 594 * sure AP knows we are sleeping, we should not let 595 * rf sleep 596 */ 597 fc = rtl_get_fc(skb); 598 if (ieee80211_is_nullfunc(fc)) { 599 if (ieee80211_has_pm(fc)) { 600 rtlpriv->mac80211.offchan_delay = true; 601 rtlpriv->psc.state_inap = true; 602 } else { 603 rtlpriv->psc.state_inap = false; 604 } 605 } 606 if (ieee80211_is_action(fc)) { 607 struct ieee80211_mgmt *action_frame = 608 (struct ieee80211_mgmt *)skb->data; 609 if (action_frame->u.action.u.ht_smps.action == 610 WLAN_HT_ACTION_SMPS) { 611 dev_kfree_skb(skb); 612 goto tx_status_ok; 613 } 614 } 615 616 /* update tid tx pkt num */ 617 tid = rtl_get_tid(skb); 618 if (tid <= 7) 619 rtlpriv->link_info.tidtx_inperiod[tid]++; 620 621 info = IEEE80211_SKB_CB(skb); 622 ieee80211_tx_info_clear_status(info); 623 624 info->flags |= IEEE80211_TX_STAT_ACK; 625 /*info->status.rates[0].count = 1; */ 626 627 ieee80211_tx_status_irqsafe(hw, skb); 628 629 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) { 630 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, 631 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", 632 prio, ring->idx, 633 skb_queue_len(&ring->queue)); 634 635 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb)); 636 } 637 tx_status_ok: 638 skb = NULL; 639 } 640 641 if (((rtlpriv->link_info.num_rx_inperiod + 642 rtlpriv->link_info.num_tx_inperiod) > 8) || 643 rtlpriv->link_info.num_rx_inperiod > 2) 644 rtl_lps_leave(hw); 645 } 646 647 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, 648 struct sk_buff *new_skb, u8 *entry, 649 int rxring_idx, int desc_idx) 650 { 651 struct rtl_priv *rtlpriv = rtl_priv(hw); 652 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 653 u32 bufferaddress; 654 u8 tmp_one = 1; 655 struct sk_buff *skb; 656 657 if (likely(new_skb)) { 658 skb = new_skb; 659 goto remap; 660 } 661 skb = dev_alloc_skb(rtlpci->rxbuffersize); 662 if (!skb) 663 return 0; 664 665 remap: 666 /* just set skb->cb to mapping addr for pci_unmap_single use */ 667 *((dma_addr_t *)skb->cb) = 668 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb), 669 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 670 bufferaddress = *((dma_addr_t *)skb->cb); 671 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress)) 672 return 0; 673 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb; 674 if (rtlpriv->use_new_trx_flow) { 675 /* skb->cb may be 64 bit address */ 676 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 677 HW_DESC_RX_PREPARE, 678 (u8 *)(dma_addr_t *)skb->cb); 679 } else { 680 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 681 HW_DESC_RXBUFF_ADDR, 682 (u8 *)&bufferaddress); 683 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 684 HW_DESC_RXPKT_LEN, 685 (u8 *)&rtlpci->rxbuffersize); 686 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 687 HW_DESC_RXOWN, 688 (u8 *)&tmp_one); 689 } 690 return 1; 691 } 692 693 /* inorder to receive 8K AMSDU we have set skb to 694 * 9100bytes in init rx ring, but if this packet is 695 * not a AMSDU, this large packet will be sent to 696 * TCP/IP directly, this cause big packet ping fail 697 * like: "ping -s 65507", so here we will realloc skb 698 * based on the true size of packet, Mac80211 699 * Probably will do it better, but does not yet. 700 * 701 * Some platform will fail when alloc skb sometimes. 702 * in this condition, we will send the old skb to 703 * mac80211 directly, this will not cause any other 704 * issues, but only this packet will be lost by TCP/IP 705 */ 706 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw, 707 struct sk_buff *skb, 708 struct ieee80211_rx_status rx_status) 709 { 710 if (unlikely(!rtl_action_proc(hw, skb, false))) { 711 dev_kfree_skb_any(skb); 712 } else { 713 struct sk_buff *uskb = NULL; 714 715 uskb = dev_alloc_skb(skb->len + 128); 716 if (likely(uskb)) { 717 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, 718 sizeof(rx_status)); 719 skb_put_data(uskb, skb->data, skb->len); 720 dev_kfree_skb_any(skb); 721 ieee80211_rx_irqsafe(hw, uskb); 722 } else { 723 ieee80211_rx_irqsafe(hw, skb); 724 } 725 } 726 } 727 728 /*hsisr interrupt handler*/ 729 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw) 730 { 731 struct rtl_priv *rtlpriv = rtl_priv(hw); 732 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 733 734 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR], 735 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) | 736 rtlpci->sys_irq_mask); 737 } 738 739 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) 740 { 741 struct rtl_priv *rtlpriv = rtl_priv(hw); 742 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 743 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE; 744 struct ieee80211_rx_status rx_status = { 0 }; 745 unsigned int count = rtlpci->rxringcount; 746 u8 own; 747 u8 tmp_one; 748 bool unicast = false; 749 u8 hw_queue = 0; 750 unsigned int rx_remained_cnt; 751 struct rtl_stats stats = { 752 .signal = 0, 753 .rate = 0, 754 }; 755 756 /*RX NORMAL PKT */ 757 while (count--) { 758 struct ieee80211_hdr *hdr; 759 __le16 fc; 760 u16 len; 761 /*rx buffer descriptor */ 762 struct rtl_rx_buffer_desc *buffer_desc = NULL; 763 /*if use new trx flow, it means wifi info */ 764 struct rtl_rx_desc *pdesc = NULL; 765 /*rx pkt */ 766 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[ 767 rtlpci->rx_ring[rxring_idx].idx]; 768 struct sk_buff *new_skb; 769 770 if (rtlpriv->use_new_trx_flow) { 771 rx_remained_cnt = 772 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw, 773 hw_queue); 774 if (rx_remained_cnt == 0) 775 return; 776 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[ 777 rtlpci->rx_ring[rxring_idx].idx]; 778 pdesc = (struct rtl_rx_desc *)skb->data; 779 } else { /* rx descriptor */ 780 pdesc = &rtlpci->rx_ring[rxring_idx].desc[ 781 rtlpci->rx_ring[rxring_idx].idx]; 782 783 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 784 false, 785 HW_DESC_OWN); 786 if (own) /* wait data to be filled by hardware */ 787 return; 788 } 789 790 /* Reaching this point means: data is filled already 791 * AAAAAAttention !!! 792 * We can NOT access 'skb' before 'pci_unmap_single' 793 */ 794 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), 795 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 796 797 /* get a new skb - if fail, old one will be reused */ 798 new_skb = dev_alloc_skb(rtlpci->rxbuffersize); 799 if (unlikely(!new_skb)) 800 goto no_new; 801 memset(&rx_status, 0, sizeof(rx_status)); 802 rtlpriv->cfg->ops->query_rx_desc(hw, &stats, 803 &rx_status, (u8 *)pdesc, skb); 804 805 if (rtlpriv->use_new_trx_flow) 806 rtlpriv->cfg->ops->rx_check_dma_ok(hw, 807 (u8 *)buffer_desc, 808 hw_queue); 809 810 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false, 811 HW_DESC_RXPKT_LEN); 812 813 if (skb->end - skb->tail > len) { 814 skb_put(skb, len); 815 if (rtlpriv->use_new_trx_flow) 816 skb_reserve(skb, stats.rx_drvinfo_size + 817 stats.rx_bufshift + 24); 818 else 819 skb_reserve(skb, stats.rx_drvinfo_size + 820 stats.rx_bufshift); 821 } else { 822 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 823 "skb->end - skb->tail = %d, len is %d\n", 824 skb->end - skb->tail, len); 825 dev_kfree_skb_any(skb); 826 goto new_trx_end; 827 } 828 /* handle command packet here */ 829 if (rtlpriv->cfg->ops->rx_command_packet && 830 rtlpriv->cfg->ops->rx_command_packet(hw, &stats, skb)) { 831 dev_kfree_skb_any(skb); 832 goto new_trx_end; 833 } 834 835 /* NOTICE This can not be use for mac80211, 836 * this is done in mac80211 code, 837 * if done here sec DHCP will fail 838 * skb_trim(skb, skb->len - 4); 839 */ 840 841 hdr = rtl_get_hdr(skb); 842 fc = rtl_get_fc(skb); 843 844 if (!stats.crc && !stats.hwerror) { 845 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, 846 sizeof(rx_status)); 847 848 if (is_broadcast_ether_addr(hdr->addr1)) { 849 ;/*TODO*/ 850 } else if (is_multicast_ether_addr(hdr->addr1)) { 851 ;/*TODO*/ 852 } else { 853 unicast = true; 854 rtlpriv->stats.rxbytesunicast += skb->len; 855 } 856 rtl_is_special_data(hw, skb, false, true); 857 858 if (ieee80211_is_data(fc)) { 859 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX); 860 if (unicast) 861 rtlpriv->link_info.num_rx_inperiod++; 862 } 863 864 rtl_collect_scan_list(hw, skb); 865 866 /* static bcn for roaming */ 867 rtl_beacon_statistic(hw, skb); 868 rtl_p2p_info(hw, (void *)skb->data, skb->len); 869 /* for sw lps */ 870 rtl_swlps_beacon(hw, (void *)skb->data, skb->len); 871 rtl_recognize_peer(hw, (void *)skb->data, skb->len); 872 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP && 873 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G && 874 (ieee80211_is_beacon(fc) || 875 ieee80211_is_probe_resp(fc))) { 876 dev_kfree_skb_any(skb); 877 } else { 878 _rtl_pci_rx_to_mac80211(hw, skb, rx_status); 879 } 880 } else { 881 dev_kfree_skb_any(skb); 882 } 883 new_trx_end: 884 if (rtlpriv->use_new_trx_flow) { 885 rtlpci->rx_ring[hw_queue].next_rx_rp += 1; 886 rtlpci->rx_ring[hw_queue].next_rx_rp %= 887 RTL_PCI_MAX_RX_COUNT; 888 889 rx_remained_cnt--; 890 rtl_write_word(rtlpriv, 0x3B4, 891 rtlpci->rx_ring[hw_queue].next_rx_rp); 892 } 893 if (((rtlpriv->link_info.num_rx_inperiod + 894 rtlpriv->link_info.num_tx_inperiod) > 8) || 895 rtlpriv->link_info.num_rx_inperiod > 2) 896 rtl_lps_leave(hw); 897 skb = new_skb; 898 no_new: 899 if (rtlpriv->use_new_trx_flow) { 900 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc, 901 rxring_idx, 902 rtlpci->rx_ring[rxring_idx].idx); 903 } else { 904 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc, 905 rxring_idx, 906 rtlpci->rx_ring[rxring_idx].idx); 907 if (rtlpci->rx_ring[rxring_idx].idx == 908 rtlpci->rxringcount - 1) 909 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, 910 false, 911 HW_DESC_RXERO, 912 (u8 *)&tmp_one); 913 } 914 rtlpci->rx_ring[rxring_idx].idx = 915 (rtlpci->rx_ring[rxring_idx].idx + 1) % 916 rtlpci->rxringcount; 917 } 918 } 919 920 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) 921 { 922 struct ieee80211_hw *hw = dev_id; 923 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 924 struct rtl_priv *rtlpriv = rtl_priv(hw); 925 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 926 unsigned long flags; 927 u32 inta = 0; 928 u32 intb = 0; 929 u32 intc = 0; 930 u32 intd = 0; 931 irqreturn_t ret = IRQ_HANDLED; 932 933 if (rtlpci->irq_enabled == 0) 934 return ret; 935 936 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 937 rtlpriv->cfg->ops->disable_interrupt(hw); 938 939 /*read ISR: 4/8bytes */ 940 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb, &intc, &intd); 941 942 /*Shared IRQ or HW disappeared */ 943 if (!inta || inta == 0xffff) 944 goto done; 945 946 /*<1> beacon related */ 947 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) 948 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 949 "beacon ok interrupt!\n"); 950 951 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) 952 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 953 "beacon err interrupt!\n"); 954 955 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) 956 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); 957 958 if (inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) { 959 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 960 "prepare beacon for interrupt!\n"); 961 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet); 962 } 963 964 /*<2> Tx related */ 965 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW])) 966 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); 967 968 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) { 969 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 970 "Manage ok interrupt!\n"); 971 _rtl_pci_tx_isr(hw, MGNT_QUEUE); 972 } 973 974 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) { 975 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 976 "HIGH_QUEUE ok interrupt!\n"); 977 _rtl_pci_tx_isr(hw, HIGH_QUEUE); 978 } 979 980 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) { 981 rtlpriv->link_info.num_tx_inperiod++; 982 983 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 984 "BK Tx OK interrupt!\n"); 985 _rtl_pci_tx_isr(hw, BK_QUEUE); 986 } 987 988 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) { 989 rtlpriv->link_info.num_tx_inperiod++; 990 991 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 992 "BE TX OK interrupt!\n"); 993 _rtl_pci_tx_isr(hw, BE_QUEUE); 994 } 995 996 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) { 997 rtlpriv->link_info.num_tx_inperiod++; 998 999 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1000 "VI TX OK interrupt!\n"); 1001 _rtl_pci_tx_isr(hw, VI_QUEUE); 1002 } 1003 1004 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) { 1005 rtlpriv->link_info.num_tx_inperiod++; 1006 1007 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1008 "Vo TX OK interrupt!\n"); 1009 _rtl_pci_tx_isr(hw, VO_QUEUE); 1010 } 1011 1012 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) { 1013 if (intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) { 1014 rtlpriv->link_info.num_tx_inperiod++; 1015 1016 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1017 "H2C TX OK interrupt!\n"); 1018 _rtl_pci_tx_isr(hw, H2C_QUEUE); 1019 } 1020 } 1021 1022 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) { 1023 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) { 1024 rtlpriv->link_info.num_tx_inperiod++; 1025 1026 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1027 "CMD TX OK interrupt!\n"); 1028 _rtl_pci_tx_isr(hw, TXCMD_QUEUE); 1029 } 1030 } 1031 1032 /*<3> Rx related */ 1033 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) { 1034 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); 1035 _rtl_pci_rx_interrupt(hw); 1036 } 1037 1038 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) { 1039 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1040 "rx descriptor unavailable!\n"); 1041 _rtl_pci_rx_interrupt(hw); 1042 } 1043 1044 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) { 1045 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); 1046 _rtl_pci_rx_interrupt(hw); 1047 } 1048 1049 /*<4> fw related*/ 1050 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { 1051 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) { 1052 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1053 "firmware interrupt!\n"); 1054 queue_delayed_work(rtlpriv->works.rtl_wq, 1055 &rtlpriv->works.fwevt_wq, 0); 1056 } 1057 } 1058 1059 /*<5> hsisr related*/ 1060 /* Only 8188EE & 8723BE Supported. 1061 * If Other ICs Come in, System will corrupt, 1062 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR] 1063 * are not initialized 1064 */ 1065 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE || 1066 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) { 1067 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) { 1068 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1069 "hsisr interrupt!\n"); 1070 _rtl_pci_hs_interrupt(hw); 1071 } 1072 } 1073 1074 if (rtlpriv->rtlhal.earlymode_enable) 1075 tasklet_schedule(&rtlpriv->works.irq_tasklet); 1076 1077 done: 1078 rtlpriv->cfg->ops->enable_interrupt(hw); 1079 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1080 return ret; 1081 } 1082 1083 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw) 1084 { 1085 _rtl_pci_tx_chk_waitq(hw); 1086 } 1087 1088 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw) 1089 { 1090 struct rtl_priv *rtlpriv = rtl_priv(hw); 1091 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1092 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1093 struct rtl8192_tx_ring *ring = NULL; 1094 struct ieee80211_hdr *hdr = NULL; 1095 struct ieee80211_tx_info *info = NULL; 1096 struct sk_buff *pskb = NULL; 1097 struct rtl_tx_desc *pdesc = NULL; 1098 struct rtl_tcb_desc tcb_desc; 1099 /*This is for new trx flow*/ 1100 struct rtl_tx_buffer_desc *pbuffer_desc = NULL; 1101 u8 temp_one = 1; 1102 u8 *entry; 1103 1104 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 1105 ring = &rtlpci->tx_ring[BEACON_QUEUE]; 1106 pskb = __skb_dequeue(&ring->queue); 1107 if (rtlpriv->use_new_trx_flow) 1108 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1109 else 1110 entry = (u8 *)(&ring->desc[ring->idx]); 1111 if (pskb) { 1112 pci_unmap_single(rtlpci->pdev, 1113 rtlpriv->cfg->ops->get_desc( 1114 hw, (u8 *)entry, true, HW_DESC_TXBUFF_ADDR), 1115 pskb->len, PCI_DMA_TODEVICE); 1116 kfree_skb(pskb); 1117 } 1118 1119 /*NB: the beacon data buffer must be 32-bit aligned. */ 1120 pskb = ieee80211_beacon_get(hw, mac->vif); 1121 if (!pskb) 1122 return; 1123 hdr = rtl_get_hdr(pskb); 1124 info = IEEE80211_SKB_CB(pskb); 1125 pdesc = &ring->desc[0]; 1126 if (rtlpriv->use_new_trx_flow) 1127 pbuffer_desc = &ring->buffer_desc[0]; 1128 1129 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1130 (u8 *)pbuffer_desc, info, NULL, pskb, 1131 BEACON_QUEUE, &tcb_desc); 1132 1133 __skb_queue_tail(&ring->queue, pskb); 1134 1135 if (rtlpriv->use_new_trx_flow) { 1136 temp_one = 4; 1137 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true, 1138 HW_DESC_OWN, (u8 *)&temp_one); 1139 } else { 1140 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN, 1141 &temp_one); 1142 } 1143 } 1144 1145 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw) 1146 { 1147 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1148 struct rtl_priv *rtlpriv = rtl_priv(hw); 1149 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1150 u8 i; 1151 u16 desc_num; 1152 1153 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) 1154 desc_num = TX_DESC_NUM_92E; 1155 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) 1156 desc_num = TX_DESC_NUM_8822B; 1157 else 1158 desc_num = RT_TXDESC_NUM; 1159 1160 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1161 rtlpci->txringcount[i] = desc_num; 1162 1163 /*we just alloc 2 desc for beacon queue, 1164 *because we just need first desc in hw beacon. 1165 */ 1166 rtlpci->txringcount[BEACON_QUEUE] = 2; 1167 1168 /*BE queue need more descriptor for performance 1169 *consideration or, No more tx desc will happen, 1170 *and may cause mac80211 mem leakage. 1171 */ 1172 if (!rtl_priv(hw)->use_new_trx_flow) 1173 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE; 1174 1175 rtlpci->rxbuffersize = 9100; /*2048/1024; */ 1176 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */ 1177 } 1178 1179 static void _rtl_pci_init_struct(struct ieee80211_hw *hw, 1180 struct pci_dev *pdev) 1181 { 1182 struct rtl_priv *rtlpriv = rtl_priv(hw); 1183 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1184 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1185 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1186 1187 rtlpci->up_first_time = true; 1188 rtlpci->being_init_adapter = false; 1189 1190 rtlhal->hw = hw; 1191 rtlpci->pdev = pdev; 1192 1193 /*Tx/Rx related var */ 1194 _rtl_pci_init_trx_var(hw); 1195 1196 /*IBSS*/ 1197 mac->beacon_interval = 100; 1198 1199 /*AMPDU*/ 1200 mac->min_space_cfg = 0; 1201 mac->max_mss_density = 0; 1202 /*set sane AMPDU defaults */ 1203 mac->current_ampdu_density = 7; 1204 mac->current_ampdu_factor = 3; 1205 1206 /*Retry Limit*/ 1207 mac->retry_short = 7; 1208 mac->retry_long = 7; 1209 1210 /*QOS*/ 1211 rtlpci->acm_method = EACMWAY2_SW; 1212 1213 /*task */ 1214 tasklet_init(&rtlpriv->works.irq_tasklet, 1215 (void (*)(unsigned long))_rtl_pci_irq_tasklet, 1216 (unsigned long)hw); 1217 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet, 1218 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet, 1219 (unsigned long)hw); 1220 INIT_WORK(&rtlpriv->works.lps_change_work, 1221 rtl_lps_change_work_callback); 1222 } 1223 1224 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, 1225 unsigned int prio, unsigned int entries) 1226 { 1227 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1228 struct rtl_priv *rtlpriv = rtl_priv(hw); 1229 struct rtl_tx_buffer_desc *buffer_desc; 1230 struct rtl_tx_desc *desc; 1231 dma_addr_t buffer_desc_dma, desc_dma; 1232 u32 nextdescaddress; 1233 int i; 1234 1235 /* alloc tx buffer desc for new trx flow*/ 1236 if (rtlpriv->use_new_trx_flow) { 1237 buffer_desc = 1238 pci_zalloc_consistent(rtlpci->pdev, 1239 sizeof(*buffer_desc) * entries, 1240 &buffer_desc_dma); 1241 1242 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) { 1243 pr_err("Cannot allocate TX ring (prio = %d)\n", 1244 prio); 1245 return -ENOMEM; 1246 } 1247 1248 rtlpci->tx_ring[prio].buffer_desc = buffer_desc; 1249 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma; 1250 1251 rtlpci->tx_ring[prio].cur_tx_rp = 0; 1252 rtlpci->tx_ring[prio].cur_tx_wp = 0; 1253 rtlpci->tx_ring[prio].avl_desc = entries; 1254 } 1255 1256 /* alloc dma for this ring */ 1257 desc = pci_zalloc_consistent(rtlpci->pdev, 1258 sizeof(*desc) * entries, &desc_dma); 1259 1260 if (!desc || (unsigned long)desc & 0xFF) { 1261 pr_err("Cannot allocate TX ring (prio = %d)\n", prio); 1262 return -ENOMEM; 1263 } 1264 1265 rtlpci->tx_ring[prio].desc = desc; 1266 rtlpci->tx_ring[prio].dma = desc_dma; 1267 1268 rtlpci->tx_ring[prio].idx = 0; 1269 rtlpci->tx_ring[prio].entries = entries; 1270 skb_queue_head_init(&rtlpci->tx_ring[prio].queue); 1271 1272 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", 1273 prio, desc); 1274 1275 /* init every desc in this ring */ 1276 if (!rtlpriv->use_new_trx_flow) { 1277 for (i = 0; i < entries; i++) { 1278 nextdescaddress = (u32)desc_dma + 1279 ((i + 1) % entries) * 1280 sizeof(*desc); 1281 1282 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i], 1283 true, 1284 HW_DESC_TX_NEXTDESC_ADDR, 1285 (u8 *)&nextdescaddress); 1286 } 1287 } 1288 return 0; 1289 } 1290 1291 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1292 { 1293 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1294 struct rtl_priv *rtlpriv = rtl_priv(hw); 1295 int i; 1296 1297 if (rtlpriv->use_new_trx_flow) { 1298 struct rtl_rx_buffer_desc *entry = NULL; 1299 /* alloc dma for this ring */ 1300 rtlpci->rx_ring[rxring_idx].buffer_desc = 1301 pci_zalloc_consistent(rtlpci->pdev, 1302 sizeof(*rtlpci->rx_ring[rxring_idx]. 1303 buffer_desc) * 1304 rtlpci->rxringcount, 1305 &rtlpci->rx_ring[rxring_idx].dma); 1306 if (!rtlpci->rx_ring[rxring_idx].buffer_desc || 1307 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) { 1308 pr_err("Cannot allocate RX ring\n"); 1309 return -ENOMEM; 1310 } 1311 1312 /* init every desc in this ring */ 1313 rtlpci->rx_ring[rxring_idx].idx = 0; 1314 for (i = 0; i < rtlpci->rxringcount; i++) { 1315 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i]; 1316 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1317 rxring_idx, i)) 1318 return -ENOMEM; 1319 } 1320 } else { 1321 struct rtl_rx_desc *entry = NULL; 1322 u8 tmp_one = 1; 1323 /* alloc dma for this ring */ 1324 rtlpci->rx_ring[rxring_idx].desc = 1325 pci_zalloc_consistent(rtlpci->pdev, 1326 sizeof(*rtlpci->rx_ring[rxring_idx]. 1327 desc) * rtlpci->rxringcount, 1328 &rtlpci->rx_ring[rxring_idx].dma); 1329 if (!rtlpci->rx_ring[rxring_idx].desc || 1330 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) { 1331 pr_err("Cannot allocate RX ring\n"); 1332 return -ENOMEM; 1333 } 1334 1335 /* init every desc in this ring */ 1336 rtlpci->rx_ring[rxring_idx].idx = 0; 1337 1338 for (i = 0; i < rtlpci->rxringcount; i++) { 1339 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1340 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1341 rxring_idx, i)) 1342 return -ENOMEM; 1343 } 1344 1345 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1346 HW_DESC_RXERO, &tmp_one); 1347 } 1348 return 0; 1349 } 1350 1351 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw, 1352 unsigned int prio) 1353 { 1354 struct rtl_priv *rtlpriv = rtl_priv(hw); 1355 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1356 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 1357 1358 /* free every desc in this ring */ 1359 while (skb_queue_len(&ring->queue)) { 1360 u8 *entry; 1361 struct sk_buff *skb = __skb_dequeue(&ring->queue); 1362 1363 if (rtlpriv->use_new_trx_flow) 1364 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1365 else 1366 entry = (u8 *)(&ring->desc[ring->idx]); 1367 1368 pci_unmap_single(rtlpci->pdev, 1369 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1370 true, 1371 HW_DESC_TXBUFF_ADDR), 1372 skb->len, PCI_DMA_TODEVICE); 1373 kfree_skb(skb); 1374 ring->idx = (ring->idx + 1) % ring->entries; 1375 } 1376 1377 /* free dma of this ring */ 1378 pci_free_consistent(rtlpci->pdev, 1379 sizeof(*ring->desc) * ring->entries, 1380 ring->desc, ring->dma); 1381 ring->desc = NULL; 1382 if (rtlpriv->use_new_trx_flow) { 1383 pci_free_consistent(rtlpci->pdev, 1384 sizeof(*ring->buffer_desc) * ring->entries, 1385 ring->buffer_desc, ring->buffer_desc_dma); 1386 ring->buffer_desc = NULL; 1387 } 1388 } 1389 1390 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1391 { 1392 struct rtl_priv *rtlpriv = rtl_priv(hw); 1393 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1394 int i; 1395 1396 /* free every desc in this ring */ 1397 for (i = 0; i < rtlpci->rxringcount; i++) { 1398 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i]; 1399 1400 if (!skb) 1401 continue; 1402 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), 1403 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 1404 kfree_skb(skb); 1405 } 1406 1407 /* free dma of this ring */ 1408 if (rtlpriv->use_new_trx_flow) { 1409 pci_free_consistent(rtlpci->pdev, 1410 sizeof(*rtlpci->rx_ring[rxring_idx]. 1411 buffer_desc) * rtlpci->rxringcount, 1412 rtlpci->rx_ring[rxring_idx].buffer_desc, 1413 rtlpci->rx_ring[rxring_idx].dma); 1414 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL; 1415 } else { 1416 pci_free_consistent(rtlpci->pdev, 1417 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1418 rtlpci->rxringcount, 1419 rtlpci->rx_ring[rxring_idx].desc, 1420 rtlpci->rx_ring[rxring_idx].dma); 1421 rtlpci->rx_ring[rxring_idx].desc = NULL; 1422 } 1423 } 1424 1425 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw) 1426 { 1427 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1428 int ret; 1429 int i, rxring_idx; 1430 1431 /* rxring_idx 0:RX_MPDU_QUEUE 1432 * rxring_idx 1:RX_CMD_QUEUE 1433 */ 1434 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1435 ret = _rtl_pci_init_rx_ring(hw, rxring_idx); 1436 if (ret) 1437 return ret; 1438 } 1439 1440 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1441 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]); 1442 if (ret) 1443 goto err_free_rings; 1444 } 1445 1446 return 0; 1447 1448 err_free_rings: 1449 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1450 _rtl_pci_free_rx_ring(hw, rxring_idx); 1451 1452 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1453 if (rtlpci->tx_ring[i].desc || 1454 rtlpci->tx_ring[i].buffer_desc) 1455 _rtl_pci_free_tx_ring(hw, i); 1456 1457 return 1; 1458 } 1459 1460 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw) 1461 { 1462 u32 i, rxring_idx; 1463 1464 /*free rx rings */ 1465 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1466 _rtl_pci_free_rx_ring(hw, rxring_idx); 1467 1468 /*free tx rings */ 1469 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1470 _rtl_pci_free_tx_ring(hw, i); 1471 1472 return 0; 1473 } 1474 1475 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw) 1476 { 1477 struct rtl_priv *rtlpriv = rtl_priv(hw); 1478 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1479 int i, rxring_idx; 1480 unsigned long flags; 1481 u8 tmp_one = 1; 1482 u32 bufferaddress; 1483 /* rxring_idx 0:RX_MPDU_QUEUE */ 1484 /* rxring_idx 1:RX_CMD_QUEUE */ 1485 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1486 /* force the rx_ring[RX_MPDU_QUEUE/ 1487 * RX_CMD_QUEUE].idx to the first one 1488 *new trx flow, do nothing 1489 */ 1490 if (!rtlpriv->use_new_trx_flow && 1491 rtlpci->rx_ring[rxring_idx].desc) { 1492 struct rtl_rx_desc *entry = NULL; 1493 1494 rtlpci->rx_ring[rxring_idx].idx = 0; 1495 for (i = 0; i < rtlpci->rxringcount; i++) { 1496 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1497 bufferaddress = 1498 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1499 false, HW_DESC_RXBUFF_ADDR); 1500 memset((u8 *)entry, 0, 1501 sizeof(*rtlpci->rx_ring 1502 [rxring_idx].desc));/*clear one entry*/ 1503 if (rtlpriv->use_new_trx_flow) { 1504 rtlpriv->cfg->ops->set_desc(hw, 1505 (u8 *)entry, false, 1506 HW_DESC_RX_PREPARE, 1507 (u8 *)&bufferaddress); 1508 } else { 1509 rtlpriv->cfg->ops->set_desc(hw, 1510 (u8 *)entry, false, 1511 HW_DESC_RXBUFF_ADDR, 1512 (u8 *)&bufferaddress); 1513 rtlpriv->cfg->ops->set_desc(hw, 1514 (u8 *)entry, false, 1515 HW_DESC_RXPKT_LEN, 1516 (u8 *)&rtlpci->rxbuffersize); 1517 rtlpriv->cfg->ops->set_desc(hw, 1518 (u8 *)entry, false, 1519 HW_DESC_RXOWN, 1520 (u8 *)&tmp_one); 1521 } 1522 } 1523 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1524 HW_DESC_RXERO, (u8 *)&tmp_one); 1525 } 1526 rtlpci->rx_ring[rxring_idx].idx = 0; 1527 } 1528 1529 /*after reset, release previous pending packet, 1530 *and force the tx idx to the first one 1531 */ 1532 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1533 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1534 if (rtlpci->tx_ring[i].desc || 1535 rtlpci->tx_ring[i].buffer_desc) { 1536 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i]; 1537 1538 while (skb_queue_len(&ring->queue)) { 1539 u8 *entry; 1540 struct sk_buff *skb = 1541 __skb_dequeue(&ring->queue); 1542 if (rtlpriv->use_new_trx_flow) 1543 entry = (u8 *)(&ring->buffer_desc 1544 [ring->idx]); 1545 else 1546 entry = (u8 *)(&ring->desc[ring->idx]); 1547 1548 pci_unmap_single(rtlpci->pdev, 1549 rtlpriv->cfg->ops-> 1550 get_desc(hw, (u8 *) 1551 entry, 1552 true, 1553 HW_DESC_TXBUFF_ADDR), 1554 skb->len, PCI_DMA_TODEVICE); 1555 dev_kfree_skb_irq(skb); 1556 ring->idx = (ring->idx + 1) % ring->entries; 1557 } 1558 ring->idx = 0; 1559 } 1560 } 1561 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1562 1563 return 0; 1564 } 1565 1566 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw, 1567 struct ieee80211_sta *sta, 1568 struct sk_buff *skb) 1569 { 1570 struct rtl_priv *rtlpriv = rtl_priv(hw); 1571 struct rtl_sta_info *sta_entry = NULL; 1572 u8 tid = rtl_get_tid(skb); 1573 __le16 fc = rtl_get_fc(skb); 1574 1575 if (!sta) 1576 return false; 1577 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1578 1579 if (!rtlpriv->rtlhal.earlymode_enable) 1580 return false; 1581 if (ieee80211_is_nullfunc(fc)) 1582 return false; 1583 if (ieee80211_is_qos_nullfunc(fc)) 1584 return false; 1585 if (ieee80211_is_pspoll(fc)) 1586 return false; 1587 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL) 1588 return false; 1589 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE) 1590 return false; 1591 if (tid > 7) 1592 return false; 1593 1594 /* maybe every tid should be checked */ 1595 if (!rtlpriv->link_info.higher_busytxtraffic[tid]) 1596 return false; 1597 1598 spin_lock_bh(&rtlpriv->locks.waitq_lock); 1599 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb); 1600 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 1601 1602 return true; 1603 } 1604 1605 static int rtl_pci_tx(struct ieee80211_hw *hw, 1606 struct ieee80211_sta *sta, 1607 struct sk_buff *skb, 1608 struct rtl_tcb_desc *ptcb_desc) 1609 { 1610 struct rtl_priv *rtlpriv = rtl_priv(hw); 1611 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1612 struct rtl8192_tx_ring *ring; 1613 struct rtl_tx_desc *pdesc; 1614 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL; 1615 u16 idx; 1616 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb); 1617 unsigned long flags; 1618 struct ieee80211_hdr *hdr = rtl_get_hdr(skb); 1619 __le16 fc = rtl_get_fc(skb); 1620 u8 *pda_addr = hdr->addr1; 1621 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1622 u8 own; 1623 u8 temp_one = 1; 1624 1625 if (ieee80211_is_mgmt(fc)) 1626 rtl_tx_mgmt_proc(hw, skb); 1627 1628 if (rtlpriv->psc.sw_ps_enabled) { 1629 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) && 1630 !ieee80211_has_pm(fc)) 1631 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1632 } 1633 1634 rtl_action_proc(hw, skb, true); 1635 1636 if (is_multicast_ether_addr(pda_addr)) 1637 rtlpriv->stats.txbytesmulticast += skb->len; 1638 else if (is_broadcast_ether_addr(pda_addr)) 1639 rtlpriv->stats.txbytesbroadcast += skb->len; 1640 else 1641 rtlpriv->stats.txbytesunicast += skb->len; 1642 1643 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1644 ring = &rtlpci->tx_ring[hw_queue]; 1645 if (hw_queue != BEACON_QUEUE) { 1646 if (rtlpriv->use_new_trx_flow) 1647 idx = ring->cur_tx_wp; 1648 else 1649 idx = (ring->idx + skb_queue_len(&ring->queue)) % 1650 ring->entries; 1651 } else { 1652 idx = 0; 1653 } 1654 1655 pdesc = &ring->desc[idx]; 1656 if (rtlpriv->use_new_trx_flow) { 1657 ptx_bd_desc = &ring->buffer_desc[idx]; 1658 } else { 1659 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 1660 true, HW_DESC_OWN); 1661 1662 if (own == 1 && hw_queue != BEACON_QUEUE) { 1663 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1664 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1665 hw_queue, ring->idx, idx, 1666 skb_queue_len(&ring->queue)); 1667 1668 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, 1669 flags); 1670 return skb->len; 1671 } 1672 } 1673 1674 if (rtlpriv->cfg->ops->get_available_desc && 1675 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) { 1676 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1677 "get_available_desc fail\n"); 1678 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1679 return skb->len; 1680 } 1681 1682 if (ieee80211_is_data(fc)) 1683 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX); 1684 1685 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1686 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc); 1687 1688 __skb_queue_tail(&ring->queue, skb); 1689 1690 if (rtlpriv->use_new_trx_flow) { 1691 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1692 HW_DESC_OWN, &hw_queue); 1693 } else { 1694 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1695 HW_DESC_OWN, &temp_one); 1696 } 1697 1698 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 && 1699 hw_queue != BEACON_QUEUE) { 1700 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 1701 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1702 hw_queue, ring->idx, idx, 1703 skb_queue_len(&ring->queue)); 1704 1705 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 1706 } 1707 1708 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1709 1710 rtlpriv->cfg->ops->tx_polling(hw, hw_queue); 1711 1712 return 0; 1713 } 1714 1715 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1716 { 1717 struct rtl_priv *rtlpriv = rtl_priv(hw); 1718 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1719 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1720 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1721 u16 i = 0; 1722 int queue_id; 1723 struct rtl8192_tx_ring *ring; 1724 1725 if (mac->skip_scan) 1726 return; 1727 1728 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) { 1729 u32 queue_len; 1730 1731 if (((queues >> queue_id) & 0x1) == 0) { 1732 queue_id--; 1733 continue; 1734 } 1735 ring = &pcipriv->dev.tx_ring[queue_id]; 1736 queue_len = skb_queue_len(&ring->queue); 1737 if (queue_len == 0 || queue_id == BEACON_QUEUE || 1738 queue_id == TXCMD_QUEUE) { 1739 queue_id--; 1740 continue; 1741 } else { 1742 msleep(20); 1743 i++; 1744 } 1745 1746 /* we just wait 1s for all queues */ 1747 if (rtlpriv->psc.rfpwr_state == ERFOFF || 1748 is_hal_stop(rtlhal) || i >= 200) 1749 return; 1750 } 1751 } 1752 1753 static void rtl_pci_deinit(struct ieee80211_hw *hw) 1754 { 1755 struct rtl_priv *rtlpriv = rtl_priv(hw); 1756 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1757 1758 _rtl_pci_deinit_trx_ring(hw); 1759 1760 synchronize_irq(rtlpci->pdev->irq); 1761 tasklet_kill(&rtlpriv->works.irq_tasklet); 1762 cancel_work_sync(&rtlpriv->works.lps_change_work); 1763 1764 flush_workqueue(rtlpriv->works.rtl_wq); 1765 destroy_workqueue(rtlpriv->works.rtl_wq); 1766 } 1767 1768 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev) 1769 { 1770 int err; 1771 1772 _rtl_pci_init_struct(hw, pdev); 1773 1774 err = _rtl_pci_init_trx_ring(hw); 1775 if (err) { 1776 pr_err("tx ring initialization failed\n"); 1777 return err; 1778 } 1779 1780 return 0; 1781 } 1782 1783 static int rtl_pci_start(struct ieee80211_hw *hw) 1784 { 1785 struct rtl_priv *rtlpriv = rtl_priv(hw); 1786 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1787 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1788 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1789 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw)); 1790 1791 int err; 1792 1793 rtl_pci_reset_trx_ring(hw); 1794 1795 rtlpci->driver_is_goingto_unload = false; 1796 if (rtlpriv->cfg->ops->get_btc_status && 1797 rtlpriv->cfg->ops->get_btc_status()) { 1798 rtlpriv->btcoexist.btc_info.ap_num = 36; 1799 rtlpriv->btcoexist.btc_ops->btc_init_variables(rtlpriv); 1800 rtlpriv->btcoexist.btc_ops->btc_init_hal_vars(rtlpriv); 1801 } 1802 err = rtlpriv->cfg->ops->hw_init(hw); 1803 if (err) { 1804 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1805 "Failed to config hardware!\n"); 1806 return err; 1807 } 1808 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, 1809 &rtlmac->retry_long); 1810 1811 rtlpriv->cfg->ops->enable_interrupt(hw); 1812 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); 1813 1814 rtl_init_rx_config(hw); 1815 1816 /*should be after adapter start and interrupt enable. */ 1817 set_hal_start(rtlhal); 1818 1819 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1820 1821 rtlpci->up_first_time = false; 1822 1823 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__); 1824 return 0; 1825 } 1826 1827 static void rtl_pci_stop(struct ieee80211_hw *hw) 1828 { 1829 struct rtl_priv *rtlpriv = rtl_priv(hw); 1830 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1831 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1832 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1833 unsigned long flags; 1834 u8 rf_timeout = 0; 1835 1836 if (rtlpriv->cfg->ops->get_btc_status()) 1837 rtlpriv->btcoexist.btc_ops->btc_halt_notify(); 1838 1839 /*should be before disable interrupt&adapter 1840 *and will do it immediately. 1841 */ 1842 set_hal_stop(rtlhal); 1843 1844 rtlpci->driver_is_goingto_unload = true; 1845 rtlpriv->cfg->ops->disable_interrupt(hw); 1846 cancel_work_sync(&rtlpriv->works.lps_change_work); 1847 1848 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1849 while (ppsc->rfchange_inprogress) { 1850 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1851 if (rf_timeout > 100) { 1852 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1853 break; 1854 } 1855 mdelay(1); 1856 rf_timeout++; 1857 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1858 } 1859 ppsc->rfchange_inprogress = true; 1860 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1861 1862 rtlpriv->cfg->ops->hw_disable(hw); 1863 /* some things are not needed if firmware not available */ 1864 if (!rtlpriv->max_fw_size) 1865 return; 1866 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1867 1868 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1869 ppsc->rfchange_inprogress = false; 1870 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1871 1872 rtl_pci_enable_aspm(hw); 1873 } 1874 1875 static bool _rtl_pci_find_adapter(struct pci_dev *pdev, 1876 struct ieee80211_hw *hw) 1877 { 1878 struct rtl_priv *rtlpriv = rtl_priv(hw); 1879 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1880 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1881 struct pci_dev *bridge_pdev = pdev->bus->self; 1882 u16 venderid; 1883 u16 deviceid; 1884 u8 revisionid; 1885 u16 irqline; 1886 u8 tmp; 1887 1888 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1889 venderid = pdev->vendor; 1890 deviceid = pdev->device; 1891 pci_read_config_byte(pdev, 0x8, &revisionid); 1892 pci_read_config_word(pdev, 0x3C, &irqline); 1893 1894 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses 1895 * r8192e_pci, and RTL8192SE, which uses this driver. If the 1896 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then 1897 * the correct driver is r8192e_pci, thus this routine should 1898 * return false. 1899 */ 1900 if (deviceid == RTL_PCI_8192SE_DID && 1901 revisionid == RTL_PCI_REVISION_ID_8192PCIE) 1902 return false; 1903 1904 if (deviceid == RTL_PCI_8192_DID || 1905 deviceid == RTL_PCI_0044_DID || 1906 deviceid == RTL_PCI_0047_DID || 1907 deviceid == RTL_PCI_8192SE_DID || 1908 deviceid == RTL_PCI_8174_DID || 1909 deviceid == RTL_PCI_8173_DID || 1910 deviceid == RTL_PCI_8172_DID || 1911 deviceid == RTL_PCI_8171_DID) { 1912 switch (revisionid) { 1913 case RTL_PCI_REVISION_ID_8192PCIE: 1914 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1915 "8192 PCI-E is found - vid/did=%x/%x\n", 1916 venderid, deviceid); 1917 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E; 1918 return false; 1919 case RTL_PCI_REVISION_ID_8192SE: 1920 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1921 "8192SE is found - vid/did=%x/%x\n", 1922 venderid, deviceid); 1923 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1924 break; 1925 default: 1926 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1927 "Err: Unknown device - vid/did=%x/%x\n", 1928 venderid, deviceid); 1929 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1930 break; 1931 } 1932 } else if (deviceid == RTL_PCI_8723AE_DID) { 1933 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE; 1934 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1935 "8723AE PCI-E is found - vid/did=%x/%x\n", 1936 venderid, deviceid); 1937 } else if (deviceid == RTL_PCI_8192CET_DID || 1938 deviceid == RTL_PCI_8192CE_DID || 1939 deviceid == RTL_PCI_8191CE_DID || 1940 deviceid == RTL_PCI_8188CE_DID) { 1941 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE; 1942 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1943 "8192C PCI-E is found - vid/did=%x/%x\n", 1944 venderid, deviceid); 1945 } else if (deviceid == RTL_PCI_8192DE_DID || 1946 deviceid == RTL_PCI_8192DE_DID2) { 1947 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE; 1948 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1949 "8192D PCI-E is found - vid/did=%x/%x\n", 1950 venderid, deviceid); 1951 } else if (deviceid == RTL_PCI_8188EE_DID) { 1952 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE; 1953 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1954 "Find adapter, Hardware type is 8188EE\n"); 1955 } else if (deviceid == RTL_PCI_8723BE_DID) { 1956 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE; 1957 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1958 "Find adapter, Hardware type is 8723BE\n"); 1959 } else if (deviceid == RTL_PCI_8192EE_DID) { 1960 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE; 1961 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1962 "Find adapter, Hardware type is 8192EE\n"); 1963 } else if (deviceid == RTL_PCI_8821AE_DID) { 1964 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE; 1965 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1966 "Find adapter, Hardware type is 8821AE\n"); 1967 } else if (deviceid == RTL_PCI_8812AE_DID) { 1968 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE; 1969 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1970 "Find adapter, Hardware type is 8812AE\n"); 1971 } else if (deviceid == RTL_PCI_8822BE_DID) { 1972 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE; 1973 rtlhal->bandset = BAND_ON_BOTH; 1974 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1975 "Find adapter, Hardware type is 8822BE\n"); 1976 } else { 1977 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1978 "Err: Unknown device - vid/did=%x/%x\n", 1979 venderid, deviceid); 1980 1981 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE; 1982 } 1983 1984 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) { 1985 if (revisionid == 0 || revisionid == 1) { 1986 if (revisionid == 0) { 1987 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1988 "Find 92DE MAC0\n"); 1989 rtlhal->interfaceindex = 0; 1990 } else if (revisionid == 1) { 1991 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1992 "Find 92DE MAC1\n"); 1993 rtlhal->interfaceindex = 1; 1994 } 1995 } else { 1996 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1997 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", 1998 venderid, deviceid, revisionid); 1999 rtlhal->interfaceindex = 0; 2000 } 2001 } 2002 2003 switch (rtlhal->hw_type) { 2004 case HARDWARE_TYPE_RTL8192EE: 2005 case HARDWARE_TYPE_RTL8822BE: 2006 /* use new trx flow */ 2007 rtlpriv->use_new_trx_flow = true; 2008 break; 2009 2010 default: 2011 rtlpriv->use_new_trx_flow = false; 2012 break; 2013 } 2014 2015 /*find bus info */ 2016 pcipriv->ndis_adapter.busnumber = pdev->bus->number; 2017 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn); 2018 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn); 2019 2020 /*find bridge info */ 2021 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 2022 /* some ARM have no bridge_pdev and will crash here 2023 * so we should check if bridge_pdev is NULL 2024 */ 2025 if (bridge_pdev) { 2026 /*find bridge info if available */ 2027 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor; 2028 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { 2029 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { 2030 pcipriv->ndis_adapter.pcibridge_vendor = tmp; 2031 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2032 "Pci Bridge Vendor is found index: %d\n", 2033 tmp); 2034 break; 2035 } 2036 } 2037 } 2038 2039 if (pcipriv->ndis_adapter.pcibridge_vendor != 2040 PCI_BRIDGE_VENDOR_UNKNOWN) { 2041 pcipriv->ndis_adapter.pcibridge_busnum = 2042 bridge_pdev->bus->number; 2043 pcipriv->ndis_adapter.pcibridge_devnum = 2044 PCI_SLOT(bridge_pdev->devfn); 2045 pcipriv->ndis_adapter.pcibridge_funcnum = 2046 PCI_FUNC(bridge_pdev->devfn); 2047 pcipriv->ndis_adapter.pcibridge_pciehdr_offset = 2048 pci_pcie_cap(bridge_pdev); 2049 pcipriv->ndis_adapter.num4bytes = 2050 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4; 2051 2052 rtl_pci_get_linkcontrol_field(hw); 2053 2054 if (pcipriv->ndis_adapter.pcibridge_vendor == 2055 PCI_BRIDGE_VENDOR_AMD) { 2056 pcipriv->ndis_adapter.amd_l1_patch = 2057 rtl_pci_get_amd_l1_patch(hw); 2058 } 2059 } 2060 2061 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2062 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", 2063 pcipriv->ndis_adapter.busnumber, 2064 pcipriv->ndis_adapter.devnumber, 2065 pcipriv->ndis_adapter.funcnumber, 2066 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); 2067 2068 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2069 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n", 2070 pcipriv->ndis_adapter.pcibridge_busnum, 2071 pcipriv->ndis_adapter.pcibridge_devnum, 2072 pcipriv->ndis_adapter.pcibridge_funcnum, 2073 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], 2074 pcipriv->ndis_adapter.pcibridge_pciehdr_offset, 2075 pcipriv->ndis_adapter.pcibridge_linkctrlreg, 2076 pcipriv->ndis_adapter.amd_l1_patch); 2077 2078 rtl_pci_parse_configuration(pdev, hw); 2079 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list); 2080 2081 return true; 2082 } 2083 2084 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw) 2085 { 2086 struct rtl_priv *rtlpriv = rtl_priv(hw); 2087 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2088 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2089 int ret; 2090 2091 ret = pci_enable_msi(rtlpci->pdev); 2092 if (ret < 0) 2093 return ret; 2094 2095 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2096 IRQF_SHARED, KBUILD_MODNAME, hw); 2097 if (ret < 0) { 2098 pci_disable_msi(rtlpci->pdev); 2099 return ret; 2100 } 2101 2102 rtlpci->using_msi = true; 2103 2104 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 2105 "MSI Interrupt Mode!\n"); 2106 return 0; 2107 } 2108 2109 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw) 2110 { 2111 struct rtl_priv *rtlpriv = rtl_priv(hw); 2112 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2113 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2114 int ret; 2115 2116 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2117 IRQF_SHARED, KBUILD_MODNAME, hw); 2118 if (ret < 0) 2119 return ret; 2120 2121 rtlpci->using_msi = false; 2122 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 2123 "Pin-based Interrupt Mode!\n"); 2124 return 0; 2125 } 2126 2127 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw) 2128 { 2129 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2130 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2131 int ret; 2132 2133 if (rtlpci->msi_support) { 2134 ret = rtl_pci_intr_mode_msi(hw); 2135 if (ret < 0) 2136 ret = rtl_pci_intr_mode_legacy(hw); 2137 } else { 2138 ret = rtl_pci_intr_mode_legacy(hw); 2139 } 2140 return ret; 2141 } 2142 2143 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64) 2144 { 2145 u8 value; 2146 2147 pci_read_config_byte(pdev, 0x719, &value); 2148 2149 /* 0x719 Bit5 is DMA64 bit fetch. */ 2150 if (dma64) 2151 value |= BIT(5); 2152 else 2153 value &= ~BIT(5); 2154 2155 pci_write_config_byte(pdev, 0x719, value); 2156 } 2157 2158 int rtl_pci_probe(struct pci_dev *pdev, 2159 const struct pci_device_id *id) 2160 { 2161 struct ieee80211_hw *hw = NULL; 2162 2163 struct rtl_priv *rtlpriv = NULL; 2164 struct rtl_pci_priv *pcipriv = NULL; 2165 struct rtl_pci *rtlpci; 2166 unsigned long pmem_start, pmem_len, pmem_flags; 2167 int err; 2168 2169 err = pci_enable_device(pdev); 2170 if (err) { 2171 WARN_ONCE(true, "%s : Cannot enable new PCI device\n", 2172 pci_name(pdev)); 2173 return err; 2174 } 2175 2176 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 && 2177 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 2178 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { 2179 WARN_ONCE(true, 2180 "Unable to obtain 64bit DMA for consistent allocations\n"); 2181 err = -ENOMEM; 2182 goto fail1; 2183 } 2184 2185 platform_enable_dma64(pdev, true); 2186 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 2187 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 2188 WARN_ONCE(true, 2189 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n"); 2190 err = -ENOMEM; 2191 goto fail1; 2192 } 2193 2194 platform_enable_dma64(pdev, false); 2195 } 2196 2197 pci_set_master(pdev); 2198 2199 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) + 2200 sizeof(struct rtl_priv), &rtl_ops); 2201 if (!hw) { 2202 WARN_ONCE(true, 2203 "%s : ieee80211 alloc failed\n", pci_name(pdev)); 2204 err = -ENOMEM; 2205 goto fail1; 2206 } 2207 2208 SET_IEEE80211_DEV(hw, &pdev->dev); 2209 pci_set_drvdata(pdev, hw); 2210 2211 rtlpriv = hw->priv; 2212 rtlpriv->hw = hw; 2213 pcipriv = (void *)rtlpriv->priv; 2214 pcipriv->dev.pdev = pdev; 2215 init_completion(&rtlpriv->firmware_loading_complete); 2216 /*proximity init here*/ 2217 rtlpriv->proximity.proxim_on = false; 2218 2219 pcipriv = (void *)rtlpriv->priv; 2220 pcipriv->dev.pdev = pdev; 2221 2222 /* init cfg & intf_ops */ 2223 rtlpriv->rtlhal.interface = INTF_PCI; 2224 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data); 2225 rtlpriv->intf_ops = &rtl_pci_ops; 2226 rtlpriv->glb_var = &rtl_global_var; 2227 2228 /* MEM map */ 2229 err = pci_request_regions(pdev, KBUILD_MODNAME); 2230 if (err) { 2231 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n"); 2232 goto fail1; 2233 } 2234 2235 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id); 2236 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id); 2237 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id); 2238 2239 /*shared mem start */ 2240 rtlpriv->io.pci_mem_start = 2241 (unsigned long)pci_iomap(pdev, 2242 rtlpriv->cfg->bar_id, pmem_len); 2243 if (rtlpriv->io.pci_mem_start == 0) { 2244 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n"); 2245 err = -ENOMEM; 2246 goto fail2; 2247 } 2248 2249 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2250 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", 2251 pmem_start, pmem_len, pmem_flags, 2252 rtlpriv->io.pci_mem_start); 2253 2254 /* Disable Clk Request */ 2255 pci_write_config_byte(pdev, 0x81, 0); 2256 /* leave D3 mode */ 2257 pci_write_config_byte(pdev, 0x44, 0); 2258 pci_write_config_byte(pdev, 0x04, 0x06); 2259 pci_write_config_byte(pdev, 0x04, 0x07); 2260 2261 /* find adapter */ 2262 if (!_rtl_pci_find_adapter(pdev, hw)) { 2263 err = -ENODEV; 2264 goto fail2; 2265 } 2266 2267 /* Init IO handler */ 2268 _rtl_pci_io_handler_init(&pdev->dev, hw); 2269 2270 /*like read eeprom and so on */ 2271 rtlpriv->cfg->ops->read_eeprom_info(hw); 2272 2273 if (rtlpriv->cfg->ops->init_sw_vars(hw)) { 2274 pr_err("Can't init_sw_vars\n"); 2275 err = -ENODEV; 2276 goto fail3; 2277 } 2278 rtlpriv->cfg->ops->init_sw_leds(hw); 2279 2280 /*aspm */ 2281 rtl_pci_init_aspm(hw); 2282 2283 /* Init mac80211 sw */ 2284 err = rtl_init_core(hw); 2285 if (err) { 2286 pr_err("Can't allocate sw for mac80211\n"); 2287 goto fail3; 2288 } 2289 2290 /* Init PCI sw */ 2291 err = rtl_pci_init(hw, pdev); 2292 if (err) { 2293 pr_err("Failed to init PCI\n"); 2294 goto fail3; 2295 } 2296 2297 err = ieee80211_register_hw(hw); 2298 if (err) { 2299 pr_err("Can't register mac80211 hw.\n"); 2300 err = -ENODEV; 2301 goto fail3; 2302 } 2303 rtlpriv->mac80211.mac80211_registered = 1; 2304 2305 /*init rfkill */ 2306 rtl_init_rfkill(hw); /* Init PCI sw */ 2307 2308 rtlpci = rtl_pcidev(pcipriv); 2309 err = rtl_pci_intr_mode_decide(hw); 2310 if (err) { 2311 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2312 "%s: failed to register IRQ handler\n", 2313 wiphy_name(hw->wiphy)); 2314 goto fail3; 2315 } 2316 rtlpci->irq_alloc = 1; 2317 2318 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2319 return 0; 2320 2321 fail3: 2322 pci_set_drvdata(pdev, NULL); 2323 rtl_deinit_core(hw); 2324 2325 fail2: 2326 if (rtlpriv->io.pci_mem_start != 0) 2327 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2328 2329 pci_release_regions(pdev); 2330 complete(&rtlpriv->firmware_loading_complete); 2331 2332 fail1: 2333 if (hw) 2334 ieee80211_free_hw(hw); 2335 pci_disable_device(pdev); 2336 2337 return err; 2338 } 2339 EXPORT_SYMBOL(rtl_pci_probe); 2340 2341 void rtl_pci_disconnect(struct pci_dev *pdev) 2342 { 2343 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2344 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2345 struct rtl_priv *rtlpriv = rtl_priv(hw); 2346 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2347 struct rtl_mac *rtlmac = rtl_mac(rtlpriv); 2348 2349 /* just in case driver is removed before firmware callback */ 2350 wait_for_completion(&rtlpriv->firmware_loading_complete); 2351 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2352 2353 /*ieee80211_unregister_hw will call ops_stop */ 2354 if (rtlmac->mac80211_registered == 1) { 2355 ieee80211_unregister_hw(hw); 2356 rtlmac->mac80211_registered = 0; 2357 } else { 2358 rtl_deinit_deferred_work(hw); 2359 rtlpriv->intf_ops->adapter_stop(hw); 2360 } 2361 rtlpriv->cfg->ops->disable_interrupt(hw); 2362 2363 /*deinit rfkill */ 2364 rtl_deinit_rfkill(hw); 2365 2366 rtl_pci_deinit(hw); 2367 rtl_deinit_core(hw); 2368 rtlpriv->cfg->ops->deinit_sw_vars(hw); 2369 2370 if (rtlpci->irq_alloc) { 2371 free_irq(rtlpci->pdev->irq, hw); 2372 rtlpci->irq_alloc = 0; 2373 } 2374 2375 if (rtlpci->using_msi) 2376 pci_disable_msi(rtlpci->pdev); 2377 2378 list_del(&rtlpriv->list); 2379 if (rtlpriv->io.pci_mem_start != 0) { 2380 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2381 pci_release_regions(pdev); 2382 } 2383 2384 pci_disable_device(pdev); 2385 2386 rtl_pci_disable_aspm(hw); 2387 2388 pci_set_drvdata(pdev, NULL); 2389 2390 ieee80211_free_hw(hw); 2391 } 2392 EXPORT_SYMBOL(rtl_pci_disconnect); 2393 2394 #ifdef CONFIG_PM_SLEEP 2395 /*************************************** 2396 * kernel pci power state define: 2397 * PCI_D0 ((pci_power_t __force) 0) 2398 * PCI_D1 ((pci_power_t __force) 1) 2399 * PCI_D2 ((pci_power_t __force) 2) 2400 * PCI_D3hot ((pci_power_t __force) 3) 2401 * PCI_D3cold ((pci_power_t __force) 4) 2402 * PCI_UNKNOWN ((pci_power_t __force) 5) 2403 2404 * This function is called when system 2405 * goes into suspend state mac80211 will 2406 * call rtl_mac_stop() from the mac80211 2407 * suspend function first, So there is 2408 * no need to call hw_disable here. 2409 ****************************************/ 2410 int rtl_pci_suspend(struct device *dev) 2411 { 2412 struct pci_dev *pdev = to_pci_dev(dev); 2413 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2414 struct rtl_priv *rtlpriv = rtl_priv(hw); 2415 2416 rtlpriv->cfg->ops->hw_suspend(hw); 2417 rtl_deinit_rfkill(hw); 2418 2419 return 0; 2420 } 2421 EXPORT_SYMBOL(rtl_pci_suspend); 2422 2423 int rtl_pci_resume(struct device *dev) 2424 { 2425 struct pci_dev *pdev = to_pci_dev(dev); 2426 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2427 struct rtl_priv *rtlpriv = rtl_priv(hw); 2428 2429 rtlpriv->cfg->ops->hw_resume(hw); 2430 rtl_init_rfkill(hw); 2431 return 0; 2432 } 2433 EXPORT_SYMBOL(rtl_pci_resume); 2434 #endif /* CONFIG_PM_SLEEP */ 2435 2436 const struct rtl_intf_ops rtl_pci_ops = { 2437 .read_efuse_byte = read_efuse_byte, 2438 .adapter_start = rtl_pci_start, 2439 .adapter_stop = rtl_pci_stop, 2440 .check_buddy_priv = rtl_pci_check_buddy_priv, 2441 .adapter_tx = rtl_pci_tx, 2442 .flush = rtl_pci_flush, 2443 .reset_trx_ring = rtl_pci_reset_trx_ring, 2444 .waitq_insert = rtl_pci_tx_chk_waitq_insert, 2445 2446 .disable_aspm = rtl_pci_disable_aspm, 2447 .enable_aspm = rtl_pci_enable_aspm, 2448 }; 2449