1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4 #include "wifi.h" 5 #include "core.h" 6 #include "pci.h" 7 #include "base.h" 8 #include "ps.h" 9 #include "efuse.h" 10 #include <linux/interrupt.h> 11 #include <linux/export.h> 12 #include <linux/module.h> 13 14 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 15 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 16 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>"); 17 MODULE_LICENSE("GPL"); 18 MODULE_DESCRIPTION("PCI basic driver for rtlwifi"); 19 20 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { 21 INTEL_VENDOR_ID, 22 ATI_VENDOR_ID, 23 AMD_VENDOR_ID, 24 SIS_VENDOR_ID 25 }; 26 27 static const u8 ac_to_hwq[] = { 28 VO_QUEUE, 29 VI_QUEUE, 30 BE_QUEUE, 31 BK_QUEUE 32 }; 33 34 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb) 35 { 36 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 37 __le16 fc = rtl_get_fc(skb); 38 u8 queue_index = skb_get_queue_mapping(skb); 39 struct ieee80211_hdr *hdr; 40 41 if (unlikely(ieee80211_is_beacon(fc))) 42 return BEACON_QUEUE; 43 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) 44 return MGNT_QUEUE; 45 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 46 if (ieee80211_is_nullfunc(fc)) 47 return HIGH_QUEUE; 48 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) { 49 hdr = rtl_get_hdr(skb); 50 51 if (is_multicast_ether_addr(hdr->addr1) || 52 is_broadcast_ether_addr(hdr->addr1)) 53 return HIGH_QUEUE; 54 } 55 56 return ac_to_hwq[queue_index]; 57 } 58 59 /* Update PCI dependent default settings*/ 60 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) 61 { 62 struct rtl_priv *rtlpriv = rtl_priv(hw); 63 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 64 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 65 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 66 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 67 u8 init_aspm; 68 69 ppsc->reg_rfps_level = 0; 70 ppsc->support_aspm = false; 71 72 /*Update PCI ASPM setting */ 73 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm; 74 switch (rtlpci->const_pci_aspm) { 75 case 0: 76 /*No ASPM */ 77 break; 78 79 case 1: 80 /*ASPM dynamically enabled/disable. */ 81 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; 82 break; 83 84 case 2: 85 /*ASPM with Clock Req dynamically enabled/disable. */ 86 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | 87 RT_RF_OFF_LEVL_CLK_REQ); 88 break; 89 90 case 3: 91 /* Always enable ASPM and Clock Req 92 * from initialization to halt. 93 */ 94 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); 95 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | 96 RT_RF_OFF_LEVL_CLK_REQ); 97 break; 98 99 case 4: 100 /* Always enable ASPM without Clock Req 101 * from initialization to halt. 102 */ 103 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | 104 RT_RF_OFF_LEVL_CLK_REQ); 105 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; 106 break; 107 } 108 109 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 110 111 /*Update Radio OFF setting */ 112 switch (rtlpci->const_hwsw_rfoff_d3) { 113 case 1: 114 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 115 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 116 break; 117 118 case 2: 119 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 120 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 121 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 122 break; 123 124 case 3: 125 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; 126 break; 127 } 128 129 /*Set HW definition to determine if it supports ASPM. */ 130 switch (rtlpci->const_support_pciaspm) { 131 case 0: 132 /*Not support ASPM. */ 133 ppsc->support_aspm = false; 134 break; 135 case 1: 136 /*Support ASPM. */ 137 ppsc->support_aspm = true; 138 ppsc->support_backdoor = true; 139 break; 140 case 2: 141 /*ASPM value set by chipset. */ 142 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) 143 ppsc->support_aspm = true; 144 break; 145 default: 146 pr_err("switch case %#x not processed\n", 147 rtlpci->const_support_pciaspm); 148 break; 149 } 150 151 /* toshiba aspm issue, toshiba will set aspm selfly 152 * so we should not set aspm in driver 153 */ 154 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm); 155 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE && 156 init_aspm == 0x43) 157 ppsc->support_aspm = false; 158 } 159 160 static bool _rtl_pci_platform_switch_device_pci_aspm( 161 struct ieee80211_hw *hw, 162 u8 value) 163 { 164 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 165 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 166 167 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE) 168 value |= 0x40; 169 170 pci_write_config_byte(rtlpci->pdev, 0x80, value); 171 172 return false; 173 } 174 175 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/ 176 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value) 177 { 178 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 179 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 180 181 pci_write_config_byte(rtlpci->pdev, 0x81, value); 182 183 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 184 udelay(100); 185 } 186 187 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ 188 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) 189 { 190 struct rtl_priv *rtlpriv = rtl_priv(hw); 191 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 192 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 193 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 194 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 195 u8 num4bytes = pcipriv->ndis_adapter.num4bytes; 196 /*Retrieve original configuration settings. */ 197 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg; 198 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter. 199 pcibridge_linkctrlreg; 200 u16 aspmlevel = 0; 201 u8 tmp_u1b = 0; 202 203 if (!ppsc->support_aspm) 204 return; 205 206 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 207 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 208 "PCI(Bridge) UNKNOWN\n"); 209 210 return; 211 } 212 213 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 214 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 215 _rtl_pci_switch_clk_req(hw, 0x0); 216 } 217 218 /*for promising device will in L0 state after an I/O. */ 219 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b); 220 221 /*Set corresponding value. */ 222 aspmlevel |= BIT(0) | BIT(1); 223 linkctrl_reg &= ~aspmlevel; 224 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1)); 225 226 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg); 227 udelay(50); 228 229 /*4 Disable Pci Bridge ASPM */ 230 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), 231 pcibridge_linkctrlreg); 232 233 udelay(50); 234 } 235 236 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for 237 *power saving We should follow the sequence to enable 238 *RTL8192SE first then enable Pci Bridge ASPM 239 *or the system will show bluescreen. 240 */ 241 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) 242 { 243 struct rtl_priv *rtlpriv = rtl_priv(hw); 244 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 245 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 246 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 247 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 248 u8 num4bytes = pcipriv->ndis_adapter.num4bytes; 249 u16 aspmlevel; 250 u8 u_pcibridge_aspmsetting; 251 u8 u_device_aspmsetting; 252 253 if (!ppsc->support_aspm) 254 return; 255 256 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 257 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 258 "PCI(Bridge) UNKNOWN\n"); 259 return; 260 } 261 262 /*4 Enable Pci Bridge ASPM */ 263 264 u_pcibridge_aspmsetting = 265 pcipriv->ndis_adapter.pcibridge_linkctrlreg | 266 rtlpci->const_hostpci_aspm_setting; 267 268 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) 269 u_pcibridge_aspmsetting &= ~BIT(0); 270 271 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), 272 u_pcibridge_aspmsetting); 273 274 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 275 "PlatformEnableASPM(): Write reg[%x] = %x\n", 276 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10), 277 u_pcibridge_aspmsetting); 278 279 udelay(50); 280 281 /*Get ASPM level (with/without Clock Req) */ 282 aspmlevel = rtlpci->const_devicepci_aspm_setting; 283 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg; 284 285 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/ 286 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */ 287 288 u_device_aspmsetting |= aspmlevel; 289 290 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting); 291 292 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 293 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level & 294 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0); 295 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 296 } 297 udelay(100); 298 } 299 300 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw) 301 { 302 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 303 304 bool status = false; 305 u8 offset_e0; 306 unsigned int offset_e4; 307 308 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0); 309 310 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0); 311 312 if (offset_e0 == 0xA0) { 313 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4); 314 if (offset_e4 & BIT(23)) 315 status = true; 316 } 317 318 return status; 319 } 320 321 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw, 322 struct rtl_priv **buddy_priv) 323 { 324 struct rtl_priv *rtlpriv = rtl_priv(hw); 325 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 326 bool find_buddy_priv = false; 327 struct rtl_priv *tpriv; 328 struct rtl_pci_priv *tpcipriv = NULL; 329 330 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) { 331 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list, 332 list) { 333 tpcipriv = (struct rtl_pci_priv *)tpriv->priv; 334 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 335 "pcipriv->ndis_adapter.funcnumber %x\n", 336 pcipriv->ndis_adapter.funcnumber); 337 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 338 "tpcipriv->ndis_adapter.funcnumber %x\n", 339 tpcipriv->ndis_adapter.funcnumber); 340 341 if (pcipriv->ndis_adapter.busnumber == 342 tpcipriv->ndis_adapter.busnumber && 343 pcipriv->ndis_adapter.devnumber == 344 tpcipriv->ndis_adapter.devnumber && 345 pcipriv->ndis_adapter.funcnumber != 346 tpcipriv->ndis_adapter.funcnumber) { 347 find_buddy_priv = true; 348 break; 349 } 350 } 351 } 352 353 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 354 "find_buddy_priv %d\n", find_buddy_priv); 355 356 if (find_buddy_priv) 357 *buddy_priv = tpriv; 358 359 return find_buddy_priv; 360 } 361 362 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw) 363 { 364 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 365 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 366 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset; 367 u8 linkctrl_reg; 368 u8 num4bbytes; 369 370 num4bbytes = (capabilityoffset + 0x10) / 4; 371 372 /*Read Link Control Register */ 373 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg); 374 375 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg; 376 } 377 378 static void rtl_pci_parse_configuration(struct pci_dev *pdev, 379 struct ieee80211_hw *hw) 380 { 381 struct rtl_priv *rtlpriv = rtl_priv(hw); 382 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 383 384 u8 tmp; 385 u16 linkctrl_reg; 386 387 /*Link Control Register */ 388 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg); 389 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg; 390 391 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", 392 pcipriv->ndis_adapter.linkctrl_reg); 393 394 pci_read_config_byte(pdev, 0x98, &tmp); 395 tmp |= BIT(4); 396 pci_write_config_byte(pdev, 0x98, tmp); 397 398 tmp = 0x17; 399 pci_write_config_byte(pdev, 0x70f, tmp); 400 } 401 402 static void rtl_pci_init_aspm(struct ieee80211_hw *hw) 403 { 404 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 405 406 _rtl_pci_update_default_setting(hw); 407 408 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { 409 /*Always enable ASPM & Clock Req. */ 410 rtl_pci_enable_aspm(hw); 411 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM); 412 } 413 } 414 415 static void _rtl_pci_io_handler_init(struct device *dev, 416 struct ieee80211_hw *hw) 417 { 418 struct rtl_priv *rtlpriv = rtl_priv(hw); 419 420 rtlpriv->io.dev = dev; 421 422 rtlpriv->io.write8_async = pci_write8_async; 423 rtlpriv->io.write16_async = pci_write16_async; 424 rtlpriv->io.write32_async = pci_write32_async; 425 426 rtlpriv->io.read8_sync = pci_read8_sync; 427 rtlpriv->io.read16_sync = pci_read16_sync; 428 rtlpriv->io.read32_sync = pci_read32_sync; 429 } 430 431 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw, 432 struct sk_buff *skb, 433 struct rtl_tcb_desc *tcb_desc, u8 tid) 434 { 435 struct rtl_priv *rtlpriv = rtl_priv(hw); 436 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 437 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 438 struct sk_buff *next_skb; 439 u8 additionlen = FCS_LEN; 440 441 /* here open is 4, wep/tkip is 8, aes is 12*/ 442 if (info->control.hw_key) 443 additionlen += info->control.hw_key->icv_len; 444 445 /* The most skb num is 6 */ 446 tcb_desc->empkt_num = 0; 447 spin_lock_bh(&rtlpriv->locks.waitq_lock); 448 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) { 449 struct ieee80211_tx_info *next_info; 450 451 next_info = IEEE80211_SKB_CB(next_skb); 452 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) { 453 tcb_desc->empkt_len[tcb_desc->empkt_num] = 454 next_skb->len + additionlen; 455 tcb_desc->empkt_num++; 456 } else { 457 break; 458 } 459 460 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid], 461 next_skb)) 462 break; 463 464 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num) 465 break; 466 } 467 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 468 469 return true; 470 } 471 472 /* just for early mode now */ 473 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw) 474 { 475 struct rtl_priv *rtlpriv = rtl_priv(hw); 476 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 477 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 478 struct sk_buff *skb = NULL; 479 struct ieee80211_tx_info *info = NULL; 480 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 481 int tid; 482 483 if (!rtlpriv->rtlhal.earlymode_enable) 484 return; 485 486 if (rtlpriv->dm.supp_phymode_switch && 487 (rtlpriv->easy_concurrent_ctl.switch_in_process || 488 (rtlpriv->buddy_priv && 489 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process))) 490 return; 491 /* we just use em for BE/BK/VI/VO */ 492 for (tid = 7; tid >= 0; tid--) { 493 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)]; 494 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; 495 496 while (!mac->act_scanning && 497 rtlpriv->psc.rfpwr_state == ERFON) { 498 struct rtl_tcb_desc tcb_desc; 499 500 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 501 502 spin_lock(&rtlpriv->locks.waitq_lock); 503 if (!skb_queue_empty(&mac->skb_waitq[tid]) && 504 (ring->entries - skb_queue_len(&ring->queue) > 505 rtlhal->max_earlymode_num)) { 506 skb = skb_dequeue(&mac->skb_waitq[tid]); 507 } else { 508 spin_unlock(&rtlpriv->locks.waitq_lock); 509 break; 510 } 511 spin_unlock(&rtlpriv->locks.waitq_lock); 512 513 /* Some macaddr can't do early mode. like 514 * multicast/broadcast/no_qos data 515 */ 516 info = IEEE80211_SKB_CB(skb); 517 if (info->flags & IEEE80211_TX_CTL_AMPDU) 518 _rtl_update_earlymode_info(hw, skb, 519 &tcb_desc, tid); 520 521 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc); 522 } 523 } 524 } 525 526 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) 527 { 528 struct rtl_priv *rtlpriv = rtl_priv(hw); 529 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 530 531 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 532 533 while (skb_queue_len(&ring->queue)) { 534 struct sk_buff *skb; 535 struct ieee80211_tx_info *info; 536 __le16 fc; 537 u8 tid; 538 u8 *entry; 539 540 if (rtlpriv->use_new_trx_flow) 541 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 542 else 543 entry = (u8 *)(&ring->desc[ring->idx]); 544 545 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx)) 546 return; 547 ring->idx = (ring->idx + 1) % ring->entries; 548 549 skb = __skb_dequeue(&ring->queue); 550 pci_unmap_single(rtlpci->pdev, 551 rtlpriv->cfg->ops-> 552 get_desc(hw, (u8 *)entry, true, 553 HW_DESC_TXBUFF_ADDR), 554 skb->len, PCI_DMA_TODEVICE); 555 556 /* remove early mode header */ 557 if (rtlpriv->rtlhal.earlymode_enable) 558 skb_pull(skb, EM_HDR_LEN); 559 560 rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, 561 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", 562 ring->idx, 563 skb_queue_len(&ring->queue), 564 *(u16 *)(skb->data + 22)); 565 566 if (prio == TXCMD_QUEUE) { 567 dev_kfree_skb(skb); 568 goto tx_status_ok; 569 } 570 571 /* for sw LPS, just after NULL skb send out, we can 572 * sure AP knows we are sleeping, we should not let 573 * rf sleep 574 */ 575 fc = rtl_get_fc(skb); 576 if (ieee80211_is_nullfunc(fc)) { 577 if (ieee80211_has_pm(fc)) { 578 rtlpriv->mac80211.offchan_delay = true; 579 rtlpriv->psc.state_inap = true; 580 } else { 581 rtlpriv->psc.state_inap = false; 582 } 583 } 584 if (ieee80211_is_action(fc)) { 585 struct ieee80211_mgmt *action_frame = 586 (struct ieee80211_mgmt *)skb->data; 587 if (action_frame->u.action.u.ht_smps.action == 588 WLAN_HT_ACTION_SMPS) { 589 dev_kfree_skb(skb); 590 goto tx_status_ok; 591 } 592 } 593 594 /* update tid tx pkt num */ 595 tid = rtl_get_tid(skb); 596 if (tid <= 7) 597 rtlpriv->link_info.tidtx_inperiod[tid]++; 598 599 info = IEEE80211_SKB_CB(skb); 600 601 if (likely(!ieee80211_is_nullfunc(fc))) { 602 ieee80211_tx_info_clear_status(info); 603 info->flags |= IEEE80211_TX_STAT_ACK; 604 /*info->status.rates[0].count = 1; */ 605 ieee80211_tx_status_irqsafe(hw, skb); 606 } else { 607 rtl_tx_ackqueue(hw, skb); 608 } 609 610 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) { 611 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG, 612 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", 613 prio, ring->idx, 614 skb_queue_len(&ring->queue)); 615 616 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb)); 617 } 618 tx_status_ok: 619 skb = NULL; 620 } 621 622 if (((rtlpriv->link_info.num_rx_inperiod + 623 rtlpriv->link_info.num_tx_inperiod) > 8) || 624 rtlpriv->link_info.num_rx_inperiod > 2) 625 rtl_lps_leave(hw); 626 } 627 628 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, 629 struct sk_buff *new_skb, u8 *entry, 630 int rxring_idx, int desc_idx) 631 { 632 struct rtl_priv *rtlpriv = rtl_priv(hw); 633 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 634 u32 bufferaddress; 635 u8 tmp_one = 1; 636 struct sk_buff *skb; 637 638 if (likely(new_skb)) { 639 skb = new_skb; 640 goto remap; 641 } 642 skb = dev_alloc_skb(rtlpci->rxbuffersize); 643 if (!skb) 644 return 0; 645 646 remap: 647 /* just set skb->cb to mapping addr for pci_unmap_single use */ 648 *((dma_addr_t *)skb->cb) = 649 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb), 650 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 651 bufferaddress = *((dma_addr_t *)skb->cb); 652 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress)) 653 return 0; 654 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb; 655 if (rtlpriv->use_new_trx_flow) { 656 /* skb->cb may be 64 bit address */ 657 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 658 HW_DESC_RX_PREPARE, 659 (u8 *)(dma_addr_t *)skb->cb); 660 } else { 661 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 662 HW_DESC_RXBUFF_ADDR, 663 (u8 *)&bufferaddress); 664 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 665 HW_DESC_RXPKT_LEN, 666 (u8 *)&rtlpci->rxbuffersize); 667 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 668 HW_DESC_RXOWN, 669 (u8 *)&tmp_one); 670 } 671 return 1; 672 } 673 674 /* inorder to receive 8K AMSDU we have set skb to 675 * 9100bytes in init rx ring, but if this packet is 676 * not a AMSDU, this large packet will be sent to 677 * TCP/IP directly, this cause big packet ping fail 678 * like: "ping -s 65507", so here we will realloc skb 679 * based on the true size of packet, Mac80211 680 * Probably will do it better, but does not yet. 681 * 682 * Some platform will fail when alloc skb sometimes. 683 * in this condition, we will send the old skb to 684 * mac80211 directly, this will not cause any other 685 * issues, but only this packet will be lost by TCP/IP 686 */ 687 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw, 688 struct sk_buff *skb, 689 struct ieee80211_rx_status rx_status) 690 { 691 if (unlikely(!rtl_action_proc(hw, skb, false))) { 692 dev_kfree_skb_any(skb); 693 } else { 694 struct sk_buff *uskb = NULL; 695 696 uskb = dev_alloc_skb(skb->len + 128); 697 if (likely(uskb)) { 698 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, 699 sizeof(rx_status)); 700 skb_put_data(uskb, skb->data, skb->len); 701 dev_kfree_skb_any(skb); 702 ieee80211_rx_irqsafe(hw, uskb); 703 } else { 704 ieee80211_rx_irqsafe(hw, skb); 705 } 706 } 707 } 708 709 /*hsisr interrupt handler*/ 710 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw) 711 { 712 struct rtl_priv *rtlpriv = rtl_priv(hw); 713 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 714 715 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR], 716 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) | 717 rtlpci->sys_irq_mask); 718 } 719 720 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) 721 { 722 struct rtl_priv *rtlpriv = rtl_priv(hw); 723 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 724 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE; 725 struct ieee80211_rx_status rx_status = { 0 }; 726 unsigned int count = rtlpci->rxringcount; 727 u8 own; 728 u8 tmp_one; 729 bool unicast = false; 730 u8 hw_queue = 0; 731 unsigned int rx_remained_cnt = 0; 732 struct rtl_stats stats = { 733 .signal = 0, 734 .rate = 0, 735 }; 736 737 /*RX NORMAL PKT */ 738 while (count--) { 739 struct ieee80211_hdr *hdr; 740 __le16 fc; 741 u16 len; 742 /*rx buffer descriptor */ 743 struct rtl_rx_buffer_desc *buffer_desc = NULL; 744 /*if use new trx flow, it means wifi info */ 745 struct rtl_rx_desc *pdesc = NULL; 746 /*rx pkt */ 747 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[ 748 rtlpci->rx_ring[rxring_idx].idx]; 749 struct sk_buff *new_skb; 750 751 if (rtlpriv->use_new_trx_flow) { 752 if (rx_remained_cnt == 0) 753 rx_remained_cnt = 754 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw, 755 hw_queue); 756 if (rx_remained_cnt == 0) 757 return; 758 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[ 759 rtlpci->rx_ring[rxring_idx].idx]; 760 pdesc = (struct rtl_rx_desc *)skb->data; 761 } else { /* rx descriptor */ 762 pdesc = &rtlpci->rx_ring[rxring_idx].desc[ 763 rtlpci->rx_ring[rxring_idx].idx]; 764 765 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 766 false, 767 HW_DESC_OWN); 768 if (own) /* wait data to be filled by hardware */ 769 return; 770 } 771 772 /* Reaching this point means: data is filled already 773 * AAAAAAttention !!! 774 * We can NOT access 'skb' before 'pci_unmap_single' 775 */ 776 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), 777 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 778 779 /* get a new skb - if fail, old one will be reused */ 780 new_skb = dev_alloc_skb(rtlpci->rxbuffersize); 781 if (unlikely(!new_skb)) 782 goto no_new; 783 memset(&rx_status, 0, sizeof(rx_status)); 784 rtlpriv->cfg->ops->query_rx_desc(hw, &stats, 785 &rx_status, (u8 *)pdesc, skb); 786 787 if (rtlpriv->use_new_trx_flow) 788 rtlpriv->cfg->ops->rx_check_dma_ok(hw, 789 (u8 *)buffer_desc, 790 hw_queue); 791 792 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false, 793 HW_DESC_RXPKT_LEN); 794 795 if (skb->end - skb->tail > len) { 796 skb_put(skb, len); 797 if (rtlpriv->use_new_trx_flow) 798 skb_reserve(skb, stats.rx_drvinfo_size + 799 stats.rx_bufshift + 24); 800 else 801 skb_reserve(skb, stats.rx_drvinfo_size + 802 stats.rx_bufshift); 803 } else { 804 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 805 "skb->end - skb->tail = %d, len is %d\n", 806 skb->end - skb->tail, len); 807 dev_kfree_skb_any(skb); 808 goto new_trx_end; 809 } 810 /* handle command packet here */ 811 if (stats.packet_report_type == C2H_PACKET) { 812 rtl_c2hcmd_enqueue(hw, skb); 813 goto new_trx_end; 814 } 815 816 /* NOTICE This can not be use for mac80211, 817 * this is done in mac80211 code, 818 * if done here sec DHCP will fail 819 * skb_trim(skb, skb->len - 4); 820 */ 821 822 hdr = rtl_get_hdr(skb); 823 fc = rtl_get_fc(skb); 824 825 if (!stats.crc && !stats.hwerror && (skb->len > FCS_LEN)) { 826 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, 827 sizeof(rx_status)); 828 829 if (is_broadcast_ether_addr(hdr->addr1)) { 830 ;/*TODO*/ 831 } else if (is_multicast_ether_addr(hdr->addr1)) { 832 ;/*TODO*/ 833 } else { 834 unicast = true; 835 rtlpriv->stats.rxbytesunicast += skb->len; 836 } 837 rtl_is_special_data(hw, skb, false, true); 838 839 if (ieee80211_is_data(fc)) { 840 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX); 841 if (unicast) 842 rtlpriv->link_info.num_rx_inperiod++; 843 } 844 845 rtl_collect_scan_list(hw, skb); 846 847 /* static bcn for roaming */ 848 rtl_beacon_statistic(hw, skb); 849 rtl_p2p_info(hw, (void *)skb->data, skb->len); 850 /* for sw lps */ 851 rtl_swlps_beacon(hw, (void *)skb->data, skb->len); 852 rtl_recognize_peer(hw, (void *)skb->data, skb->len); 853 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP && 854 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G && 855 (ieee80211_is_beacon(fc) || 856 ieee80211_is_probe_resp(fc))) { 857 dev_kfree_skb_any(skb); 858 } else { 859 _rtl_pci_rx_to_mac80211(hw, skb, rx_status); 860 } 861 } else { 862 /* drop packets with errors or those too short */ 863 dev_kfree_skb_any(skb); 864 } 865 new_trx_end: 866 if (rtlpriv->use_new_trx_flow) { 867 rtlpci->rx_ring[hw_queue].next_rx_rp += 1; 868 rtlpci->rx_ring[hw_queue].next_rx_rp %= 869 RTL_PCI_MAX_RX_COUNT; 870 871 rx_remained_cnt--; 872 rtl_write_word(rtlpriv, 0x3B4, 873 rtlpci->rx_ring[hw_queue].next_rx_rp); 874 } 875 if (((rtlpriv->link_info.num_rx_inperiod + 876 rtlpriv->link_info.num_tx_inperiod) > 8) || 877 rtlpriv->link_info.num_rx_inperiod > 2) 878 rtl_lps_leave(hw); 879 skb = new_skb; 880 no_new: 881 if (rtlpriv->use_new_trx_flow) { 882 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc, 883 rxring_idx, 884 rtlpci->rx_ring[rxring_idx].idx); 885 } else { 886 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc, 887 rxring_idx, 888 rtlpci->rx_ring[rxring_idx].idx); 889 if (rtlpci->rx_ring[rxring_idx].idx == 890 rtlpci->rxringcount - 1) 891 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, 892 false, 893 HW_DESC_RXERO, 894 (u8 *)&tmp_one); 895 } 896 rtlpci->rx_ring[rxring_idx].idx = 897 (rtlpci->rx_ring[rxring_idx].idx + 1) % 898 rtlpci->rxringcount; 899 } 900 } 901 902 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) 903 { 904 struct ieee80211_hw *hw = dev_id; 905 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 906 struct rtl_priv *rtlpriv = rtl_priv(hw); 907 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 908 unsigned long flags; 909 struct rtl_int intvec = {0}; 910 911 irqreturn_t ret = IRQ_HANDLED; 912 913 if (rtlpci->irq_enabled == 0) 914 return ret; 915 916 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 917 rtlpriv->cfg->ops->disable_interrupt(hw); 918 919 /*read ISR: 4/8bytes */ 920 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec); 921 922 /*Shared IRQ or HW disappeared */ 923 if (!intvec.inta || intvec.inta == 0xffff) 924 goto done; 925 926 /*<1> beacon related */ 927 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) 928 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 929 "beacon ok interrupt!\n"); 930 931 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) 932 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 933 "beacon err interrupt!\n"); 934 935 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) 936 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); 937 938 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) { 939 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 940 "prepare beacon for interrupt!\n"); 941 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet); 942 } 943 944 /*<2> Tx related */ 945 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW])) 946 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); 947 948 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) { 949 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 950 "Manage ok interrupt!\n"); 951 _rtl_pci_tx_isr(hw, MGNT_QUEUE); 952 } 953 954 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) { 955 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 956 "HIGH_QUEUE ok interrupt!\n"); 957 _rtl_pci_tx_isr(hw, HIGH_QUEUE); 958 } 959 960 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) { 961 rtlpriv->link_info.num_tx_inperiod++; 962 963 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 964 "BK Tx OK interrupt!\n"); 965 _rtl_pci_tx_isr(hw, BK_QUEUE); 966 } 967 968 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) { 969 rtlpriv->link_info.num_tx_inperiod++; 970 971 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 972 "BE TX OK interrupt!\n"); 973 _rtl_pci_tx_isr(hw, BE_QUEUE); 974 } 975 976 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) { 977 rtlpriv->link_info.num_tx_inperiod++; 978 979 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 980 "VI TX OK interrupt!\n"); 981 _rtl_pci_tx_isr(hw, VI_QUEUE); 982 } 983 984 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) { 985 rtlpriv->link_info.num_tx_inperiod++; 986 987 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 988 "Vo TX OK interrupt!\n"); 989 _rtl_pci_tx_isr(hw, VO_QUEUE); 990 } 991 992 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) { 993 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) { 994 rtlpriv->link_info.num_tx_inperiod++; 995 996 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 997 "H2C TX OK interrupt!\n"); 998 _rtl_pci_tx_isr(hw, H2C_QUEUE); 999 } 1000 } 1001 1002 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) { 1003 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) { 1004 rtlpriv->link_info.num_tx_inperiod++; 1005 1006 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 1007 "CMD TX OK interrupt!\n"); 1008 _rtl_pci_tx_isr(hw, TXCMD_QUEUE); 1009 } 1010 } 1011 1012 /*<3> Rx related */ 1013 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) { 1014 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); 1015 _rtl_pci_rx_interrupt(hw); 1016 } 1017 1018 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) { 1019 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1020 "rx descriptor unavailable!\n"); 1021 _rtl_pci_rx_interrupt(hw); 1022 } 1023 1024 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) { 1025 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); 1026 _rtl_pci_rx_interrupt(hw); 1027 } 1028 1029 /*<4> fw related*/ 1030 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { 1031 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) { 1032 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 1033 "firmware interrupt!\n"); 1034 queue_delayed_work(rtlpriv->works.rtl_wq, 1035 &rtlpriv->works.fwevt_wq, 0); 1036 } 1037 } 1038 1039 /*<5> hsisr related*/ 1040 /* Only 8188EE & 8723BE Supported. 1041 * If Other ICs Come in, System will corrupt, 1042 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR] 1043 * are not initialized 1044 */ 1045 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE || 1046 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) { 1047 if (unlikely(intvec.inta & 1048 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) { 1049 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 1050 "hsisr interrupt!\n"); 1051 _rtl_pci_hs_interrupt(hw); 1052 } 1053 } 1054 1055 if (rtlpriv->rtlhal.earlymode_enable) 1056 tasklet_schedule(&rtlpriv->works.irq_tasklet); 1057 1058 done: 1059 rtlpriv->cfg->ops->enable_interrupt(hw); 1060 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1061 return ret; 1062 } 1063 1064 static void _rtl_pci_irq_tasklet(struct tasklet_struct *t) 1065 { 1066 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, works.irq_tasklet); 1067 struct ieee80211_hw *hw = rtlpriv->hw; 1068 _rtl_pci_tx_chk_waitq(hw); 1069 } 1070 1071 static void _rtl_pci_prepare_bcn_tasklet(struct tasklet_struct *t) 1072 { 1073 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, 1074 works.irq_prepare_bcn_tasklet); 1075 struct ieee80211_hw *hw = rtlpriv->hw; 1076 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1077 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1078 struct rtl8192_tx_ring *ring = NULL; 1079 struct ieee80211_hdr *hdr = NULL; 1080 struct ieee80211_tx_info *info = NULL; 1081 struct sk_buff *pskb = NULL; 1082 struct rtl_tx_desc *pdesc = NULL; 1083 struct rtl_tcb_desc tcb_desc; 1084 /*This is for new trx flow*/ 1085 struct rtl_tx_buffer_desc *pbuffer_desc = NULL; 1086 u8 temp_one = 1; 1087 u8 *entry; 1088 1089 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 1090 ring = &rtlpci->tx_ring[BEACON_QUEUE]; 1091 pskb = __skb_dequeue(&ring->queue); 1092 if (rtlpriv->use_new_trx_flow) 1093 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1094 else 1095 entry = (u8 *)(&ring->desc[ring->idx]); 1096 if (pskb) { 1097 pci_unmap_single(rtlpci->pdev, 1098 rtlpriv->cfg->ops->get_desc( 1099 hw, (u8 *)entry, true, HW_DESC_TXBUFF_ADDR), 1100 pskb->len, PCI_DMA_TODEVICE); 1101 kfree_skb(pskb); 1102 } 1103 1104 /*NB: the beacon data buffer must be 32-bit aligned. */ 1105 pskb = ieee80211_beacon_get(hw, mac->vif); 1106 if (!pskb) 1107 return; 1108 hdr = rtl_get_hdr(pskb); 1109 info = IEEE80211_SKB_CB(pskb); 1110 pdesc = &ring->desc[0]; 1111 if (rtlpriv->use_new_trx_flow) 1112 pbuffer_desc = &ring->buffer_desc[0]; 1113 1114 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1115 (u8 *)pbuffer_desc, info, NULL, pskb, 1116 BEACON_QUEUE, &tcb_desc); 1117 1118 __skb_queue_tail(&ring->queue, pskb); 1119 1120 if (rtlpriv->use_new_trx_flow) { 1121 temp_one = 4; 1122 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true, 1123 HW_DESC_OWN, (u8 *)&temp_one); 1124 } else { 1125 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN, 1126 &temp_one); 1127 } 1128 } 1129 1130 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw) 1131 { 1132 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1133 struct rtl_priv *rtlpriv = rtl_priv(hw); 1134 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1135 u8 i; 1136 u16 desc_num; 1137 1138 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) 1139 desc_num = TX_DESC_NUM_92E; 1140 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) 1141 desc_num = TX_DESC_NUM_8822B; 1142 else 1143 desc_num = RT_TXDESC_NUM; 1144 1145 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1146 rtlpci->txringcount[i] = desc_num; 1147 1148 /*we just alloc 2 desc for beacon queue, 1149 *because we just need first desc in hw beacon. 1150 */ 1151 rtlpci->txringcount[BEACON_QUEUE] = 2; 1152 1153 /*BE queue need more descriptor for performance 1154 *consideration or, No more tx desc will happen, 1155 *and may cause mac80211 mem leakage. 1156 */ 1157 if (!rtl_priv(hw)->use_new_trx_flow) 1158 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE; 1159 1160 rtlpci->rxbuffersize = 9100; /*2048/1024; */ 1161 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */ 1162 } 1163 1164 static void _rtl_pci_init_struct(struct ieee80211_hw *hw, 1165 struct pci_dev *pdev) 1166 { 1167 struct rtl_priv *rtlpriv = rtl_priv(hw); 1168 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1169 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1170 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1171 1172 rtlpci->up_first_time = true; 1173 rtlpci->being_init_adapter = false; 1174 1175 rtlhal->hw = hw; 1176 rtlpci->pdev = pdev; 1177 1178 /*Tx/Rx related var */ 1179 _rtl_pci_init_trx_var(hw); 1180 1181 /*IBSS*/ 1182 mac->beacon_interval = 100; 1183 1184 /*AMPDU*/ 1185 mac->min_space_cfg = 0; 1186 mac->max_mss_density = 0; 1187 /*set sane AMPDU defaults */ 1188 mac->current_ampdu_density = 7; 1189 mac->current_ampdu_factor = 3; 1190 1191 /*Retry Limit*/ 1192 mac->retry_short = 7; 1193 mac->retry_long = 7; 1194 1195 /*QOS*/ 1196 rtlpci->acm_method = EACMWAY2_SW; 1197 1198 /*task */ 1199 tasklet_setup(&rtlpriv->works.irq_tasklet, _rtl_pci_irq_tasklet); 1200 tasklet_setup(&rtlpriv->works.irq_prepare_bcn_tasklet, 1201 _rtl_pci_prepare_bcn_tasklet); 1202 INIT_WORK(&rtlpriv->works.lps_change_work, 1203 rtl_lps_change_work_callback); 1204 } 1205 1206 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, 1207 unsigned int prio, unsigned int entries) 1208 { 1209 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1210 struct rtl_priv *rtlpriv = rtl_priv(hw); 1211 struct rtl_tx_buffer_desc *buffer_desc; 1212 struct rtl_tx_desc *desc; 1213 dma_addr_t buffer_desc_dma, desc_dma; 1214 u32 nextdescaddress; 1215 int i; 1216 1217 /* alloc tx buffer desc for new trx flow*/ 1218 if (rtlpriv->use_new_trx_flow) { 1219 buffer_desc = 1220 pci_zalloc_consistent(rtlpci->pdev, 1221 sizeof(*buffer_desc) * entries, 1222 &buffer_desc_dma); 1223 1224 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) { 1225 pr_err("Cannot allocate TX ring (prio = %d)\n", 1226 prio); 1227 return -ENOMEM; 1228 } 1229 1230 rtlpci->tx_ring[prio].buffer_desc = buffer_desc; 1231 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma; 1232 1233 rtlpci->tx_ring[prio].cur_tx_rp = 0; 1234 rtlpci->tx_ring[prio].cur_tx_wp = 0; 1235 } 1236 1237 /* alloc dma for this ring */ 1238 desc = pci_zalloc_consistent(rtlpci->pdev, 1239 sizeof(*desc) * entries, &desc_dma); 1240 1241 if (!desc || (unsigned long)desc & 0xFF) { 1242 pr_err("Cannot allocate TX ring (prio = %d)\n", prio); 1243 return -ENOMEM; 1244 } 1245 1246 rtlpci->tx_ring[prio].desc = desc; 1247 rtlpci->tx_ring[prio].dma = desc_dma; 1248 1249 rtlpci->tx_ring[prio].idx = 0; 1250 rtlpci->tx_ring[prio].entries = entries; 1251 skb_queue_head_init(&rtlpci->tx_ring[prio].queue); 1252 1253 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", 1254 prio, desc); 1255 1256 /* init every desc in this ring */ 1257 if (!rtlpriv->use_new_trx_flow) { 1258 for (i = 0; i < entries; i++) { 1259 nextdescaddress = (u32)desc_dma + 1260 ((i + 1) % entries) * 1261 sizeof(*desc); 1262 1263 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i], 1264 true, 1265 HW_DESC_TX_NEXTDESC_ADDR, 1266 (u8 *)&nextdescaddress); 1267 } 1268 } 1269 return 0; 1270 } 1271 1272 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1273 { 1274 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1275 struct rtl_priv *rtlpriv = rtl_priv(hw); 1276 int i; 1277 1278 if (rtlpriv->use_new_trx_flow) { 1279 struct rtl_rx_buffer_desc *entry = NULL; 1280 /* alloc dma for this ring */ 1281 rtlpci->rx_ring[rxring_idx].buffer_desc = 1282 pci_zalloc_consistent(rtlpci->pdev, 1283 sizeof(*rtlpci->rx_ring[rxring_idx]. 1284 buffer_desc) * 1285 rtlpci->rxringcount, 1286 &rtlpci->rx_ring[rxring_idx].dma); 1287 if (!rtlpci->rx_ring[rxring_idx].buffer_desc || 1288 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) { 1289 pr_err("Cannot allocate RX ring\n"); 1290 return -ENOMEM; 1291 } 1292 1293 /* init every desc in this ring */ 1294 rtlpci->rx_ring[rxring_idx].idx = 0; 1295 for (i = 0; i < rtlpci->rxringcount; i++) { 1296 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i]; 1297 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1298 rxring_idx, i)) 1299 return -ENOMEM; 1300 } 1301 } else { 1302 struct rtl_rx_desc *entry = NULL; 1303 u8 tmp_one = 1; 1304 /* alloc dma for this ring */ 1305 rtlpci->rx_ring[rxring_idx].desc = 1306 pci_zalloc_consistent(rtlpci->pdev, 1307 sizeof(*rtlpci->rx_ring[rxring_idx]. 1308 desc) * rtlpci->rxringcount, 1309 &rtlpci->rx_ring[rxring_idx].dma); 1310 if (!rtlpci->rx_ring[rxring_idx].desc || 1311 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) { 1312 pr_err("Cannot allocate RX ring\n"); 1313 return -ENOMEM; 1314 } 1315 1316 /* init every desc in this ring */ 1317 rtlpci->rx_ring[rxring_idx].idx = 0; 1318 1319 for (i = 0; i < rtlpci->rxringcount; i++) { 1320 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1321 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1322 rxring_idx, i)) 1323 return -ENOMEM; 1324 } 1325 1326 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1327 HW_DESC_RXERO, &tmp_one); 1328 } 1329 return 0; 1330 } 1331 1332 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw, 1333 unsigned int prio) 1334 { 1335 struct rtl_priv *rtlpriv = rtl_priv(hw); 1336 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1337 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 1338 1339 /* free every desc in this ring */ 1340 while (skb_queue_len(&ring->queue)) { 1341 u8 *entry; 1342 struct sk_buff *skb = __skb_dequeue(&ring->queue); 1343 1344 if (rtlpriv->use_new_trx_flow) 1345 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1346 else 1347 entry = (u8 *)(&ring->desc[ring->idx]); 1348 1349 pci_unmap_single(rtlpci->pdev, 1350 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1351 true, 1352 HW_DESC_TXBUFF_ADDR), 1353 skb->len, PCI_DMA_TODEVICE); 1354 kfree_skb(skb); 1355 ring->idx = (ring->idx + 1) % ring->entries; 1356 } 1357 1358 /* free dma of this ring */ 1359 pci_free_consistent(rtlpci->pdev, 1360 sizeof(*ring->desc) * ring->entries, 1361 ring->desc, ring->dma); 1362 ring->desc = NULL; 1363 if (rtlpriv->use_new_trx_flow) { 1364 pci_free_consistent(rtlpci->pdev, 1365 sizeof(*ring->buffer_desc) * ring->entries, 1366 ring->buffer_desc, ring->buffer_desc_dma); 1367 ring->buffer_desc = NULL; 1368 } 1369 } 1370 1371 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1372 { 1373 struct rtl_priv *rtlpriv = rtl_priv(hw); 1374 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1375 int i; 1376 1377 /* free every desc in this ring */ 1378 for (i = 0; i < rtlpci->rxringcount; i++) { 1379 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i]; 1380 1381 if (!skb) 1382 continue; 1383 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), 1384 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 1385 kfree_skb(skb); 1386 } 1387 1388 /* free dma of this ring */ 1389 if (rtlpriv->use_new_trx_flow) { 1390 pci_free_consistent(rtlpci->pdev, 1391 sizeof(*rtlpci->rx_ring[rxring_idx]. 1392 buffer_desc) * rtlpci->rxringcount, 1393 rtlpci->rx_ring[rxring_idx].buffer_desc, 1394 rtlpci->rx_ring[rxring_idx].dma); 1395 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL; 1396 } else { 1397 pci_free_consistent(rtlpci->pdev, 1398 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1399 rtlpci->rxringcount, 1400 rtlpci->rx_ring[rxring_idx].desc, 1401 rtlpci->rx_ring[rxring_idx].dma); 1402 rtlpci->rx_ring[rxring_idx].desc = NULL; 1403 } 1404 } 1405 1406 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw) 1407 { 1408 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1409 int ret; 1410 int i, rxring_idx; 1411 1412 /* rxring_idx 0:RX_MPDU_QUEUE 1413 * rxring_idx 1:RX_CMD_QUEUE 1414 */ 1415 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1416 ret = _rtl_pci_init_rx_ring(hw, rxring_idx); 1417 if (ret) 1418 return ret; 1419 } 1420 1421 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1422 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]); 1423 if (ret) 1424 goto err_free_rings; 1425 } 1426 1427 return 0; 1428 1429 err_free_rings: 1430 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1431 _rtl_pci_free_rx_ring(hw, rxring_idx); 1432 1433 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1434 if (rtlpci->tx_ring[i].desc || 1435 rtlpci->tx_ring[i].buffer_desc) 1436 _rtl_pci_free_tx_ring(hw, i); 1437 1438 return 1; 1439 } 1440 1441 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw) 1442 { 1443 u32 i, rxring_idx; 1444 1445 /*free rx rings */ 1446 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1447 _rtl_pci_free_rx_ring(hw, rxring_idx); 1448 1449 /*free tx rings */ 1450 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1451 _rtl_pci_free_tx_ring(hw, i); 1452 1453 return 0; 1454 } 1455 1456 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw) 1457 { 1458 struct rtl_priv *rtlpriv = rtl_priv(hw); 1459 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1460 int i, rxring_idx; 1461 unsigned long flags; 1462 u8 tmp_one = 1; 1463 u32 bufferaddress; 1464 /* rxring_idx 0:RX_MPDU_QUEUE */ 1465 /* rxring_idx 1:RX_CMD_QUEUE */ 1466 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1467 /* force the rx_ring[RX_MPDU_QUEUE/ 1468 * RX_CMD_QUEUE].idx to the first one 1469 *new trx flow, do nothing 1470 */ 1471 if (!rtlpriv->use_new_trx_flow && 1472 rtlpci->rx_ring[rxring_idx].desc) { 1473 struct rtl_rx_desc *entry = NULL; 1474 1475 rtlpci->rx_ring[rxring_idx].idx = 0; 1476 for (i = 0; i < rtlpci->rxringcount; i++) { 1477 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1478 bufferaddress = 1479 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1480 false, HW_DESC_RXBUFF_ADDR); 1481 memset((u8 *)entry, 0, 1482 sizeof(*rtlpci->rx_ring 1483 [rxring_idx].desc));/*clear one entry*/ 1484 if (rtlpriv->use_new_trx_flow) { 1485 rtlpriv->cfg->ops->set_desc(hw, 1486 (u8 *)entry, false, 1487 HW_DESC_RX_PREPARE, 1488 (u8 *)&bufferaddress); 1489 } else { 1490 rtlpriv->cfg->ops->set_desc(hw, 1491 (u8 *)entry, false, 1492 HW_DESC_RXBUFF_ADDR, 1493 (u8 *)&bufferaddress); 1494 rtlpriv->cfg->ops->set_desc(hw, 1495 (u8 *)entry, false, 1496 HW_DESC_RXPKT_LEN, 1497 (u8 *)&rtlpci->rxbuffersize); 1498 rtlpriv->cfg->ops->set_desc(hw, 1499 (u8 *)entry, false, 1500 HW_DESC_RXOWN, 1501 (u8 *)&tmp_one); 1502 } 1503 } 1504 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1505 HW_DESC_RXERO, (u8 *)&tmp_one); 1506 } 1507 rtlpci->rx_ring[rxring_idx].idx = 0; 1508 } 1509 1510 /*after reset, release previous pending packet, 1511 *and force the tx idx to the first one 1512 */ 1513 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1514 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1515 if (rtlpci->tx_ring[i].desc || 1516 rtlpci->tx_ring[i].buffer_desc) { 1517 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i]; 1518 1519 while (skb_queue_len(&ring->queue)) { 1520 u8 *entry; 1521 struct sk_buff *skb = 1522 __skb_dequeue(&ring->queue); 1523 if (rtlpriv->use_new_trx_flow) 1524 entry = (u8 *)(&ring->buffer_desc 1525 [ring->idx]); 1526 else 1527 entry = (u8 *)(&ring->desc[ring->idx]); 1528 1529 pci_unmap_single(rtlpci->pdev, 1530 rtlpriv->cfg->ops-> 1531 get_desc(hw, (u8 *) 1532 entry, 1533 true, 1534 HW_DESC_TXBUFF_ADDR), 1535 skb->len, PCI_DMA_TODEVICE); 1536 dev_kfree_skb_irq(skb); 1537 ring->idx = (ring->idx + 1) % ring->entries; 1538 } 1539 1540 if (rtlpriv->use_new_trx_flow) { 1541 rtlpci->tx_ring[i].cur_tx_rp = 0; 1542 rtlpci->tx_ring[i].cur_tx_wp = 0; 1543 } 1544 1545 ring->idx = 0; 1546 ring->entries = rtlpci->txringcount[i]; 1547 } 1548 } 1549 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1550 1551 return 0; 1552 } 1553 1554 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw, 1555 struct ieee80211_sta *sta, 1556 struct sk_buff *skb) 1557 { 1558 struct rtl_priv *rtlpriv = rtl_priv(hw); 1559 struct rtl_sta_info *sta_entry = NULL; 1560 u8 tid = rtl_get_tid(skb); 1561 __le16 fc = rtl_get_fc(skb); 1562 1563 if (!sta) 1564 return false; 1565 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1566 1567 if (!rtlpriv->rtlhal.earlymode_enable) 1568 return false; 1569 if (ieee80211_is_nullfunc(fc)) 1570 return false; 1571 if (ieee80211_is_qos_nullfunc(fc)) 1572 return false; 1573 if (ieee80211_is_pspoll(fc)) 1574 return false; 1575 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL) 1576 return false; 1577 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE) 1578 return false; 1579 if (tid > 7) 1580 return false; 1581 1582 /* maybe every tid should be checked */ 1583 if (!rtlpriv->link_info.higher_busytxtraffic[tid]) 1584 return false; 1585 1586 spin_lock_bh(&rtlpriv->locks.waitq_lock); 1587 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb); 1588 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 1589 1590 return true; 1591 } 1592 1593 static int rtl_pci_tx(struct ieee80211_hw *hw, 1594 struct ieee80211_sta *sta, 1595 struct sk_buff *skb, 1596 struct rtl_tcb_desc *ptcb_desc) 1597 { 1598 struct rtl_priv *rtlpriv = rtl_priv(hw); 1599 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1600 struct rtl8192_tx_ring *ring; 1601 struct rtl_tx_desc *pdesc; 1602 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL; 1603 u16 idx; 1604 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb); 1605 unsigned long flags; 1606 struct ieee80211_hdr *hdr = rtl_get_hdr(skb); 1607 __le16 fc = rtl_get_fc(skb); 1608 u8 *pda_addr = hdr->addr1; 1609 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1610 u8 own; 1611 u8 temp_one = 1; 1612 1613 if (ieee80211_is_mgmt(fc)) 1614 rtl_tx_mgmt_proc(hw, skb); 1615 1616 if (rtlpriv->psc.sw_ps_enabled) { 1617 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) && 1618 !ieee80211_has_pm(fc)) 1619 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1620 } 1621 1622 rtl_action_proc(hw, skb, true); 1623 1624 if (is_multicast_ether_addr(pda_addr)) 1625 rtlpriv->stats.txbytesmulticast += skb->len; 1626 else if (is_broadcast_ether_addr(pda_addr)) 1627 rtlpriv->stats.txbytesbroadcast += skb->len; 1628 else 1629 rtlpriv->stats.txbytesunicast += skb->len; 1630 1631 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1632 ring = &rtlpci->tx_ring[hw_queue]; 1633 if (hw_queue != BEACON_QUEUE) { 1634 if (rtlpriv->use_new_trx_flow) 1635 idx = ring->cur_tx_wp; 1636 else 1637 idx = (ring->idx + skb_queue_len(&ring->queue)) % 1638 ring->entries; 1639 } else { 1640 idx = 0; 1641 } 1642 1643 pdesc = &ring->desc[idx]; 1644 if (rtlpriv->use_new_trx_flow) { 1645 ptx_bd_desc = &ring->buffer_desc[idx]; 1646 } else { 1647 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 1648 true, HW_DESC_OWN); 1649 1650 if (own == 1 && hw_queue != BEACON_QUEUE) { 1651 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1652 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1653 hw_queue, ring->idx, idx, 1654 skb_queue_len(&ring->queue)); 1655 1656 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, 1657 flags); 1658 return skb->len; 1659 } 1660 } 1661 1662 if (rtlpriv->cfg->ops->get_available_desc && 1663 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) { 1664 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1665 "get_available_desc fail\n"); 1666 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1667 return skb->len; 1668 } 1669 1670 if (ieee80211_is_data(fc)) 1671 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX); 1672 1673 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1674 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc); 1675 1676 __skb_queue_tail(&ring->queue, skb); 1677 1678 if (rtlpriv->use_new_trx_flow) { 1679 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1680 HW_DESC_OWN, &hw_queue); 1681 } else { 1682 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1683 HW_DESC_OWN, &temp_one); 1684 } 1685 1686 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 && 1687 hw_queue != BEACON_QUEUE) { 1688 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 1689 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1690 hw_queue, ring->idx, idx, 1691 skb_queue_len(&ring->queue)); 1692 1693 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 1694 } 1695 1696 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1697 1698 rtlpriv->cfg->ops->tx_polling(hw, hw_queue); 1699 1700 return 0; 1701 } 1702 1703 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1704 { 1705 struct rtl_priv *rtlpriv = rtl_priv(hw); 1706 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1707 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1708 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1709 u16 i = 0; 1710 int queue_id; 1711 struct rtl8192_tx_ring *ring; 1712 1713 if (mac->skip_scan) 1714 return; 1715 1716 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) { 1717 u32 queue_len; 1718 1719 if (((queues >> queue_id) & 0x1) == 0) { 1720 queue_id--; 1721 continue; 1722 } 1723 ring = &pcipriv->dev.tx_ring[queue_id]; 1724 queue_len = skb_queue_len(&ring->queue); 1725 if (queue_len == 0 || queue_id == BEACON_QUEUE || 1726 queue_id == TXCMD_QUEUE) { 1727 queue_id--; 1728 continue; 1729 } else { 1730 msleep(20); 1731 i++; 1732 } 1733 1734 /* we just wait 1s for all queues */ 1735 if (rtlpriv->psc.rfpwr_state == ERFOFF || 1736 is_hal_stop(rtlhal) || i >= 200) 1737 return; 1738 } 1739 } 1740 1741 static void rtl_pci_deinit(struct ieee80211_hw *hw) 1742 { 1743 struct rtl_priv *rtlpriv = rtl_priv(hw); 1744 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1745 1746 _rtl_pci_deinit_trx_ring(hw); 1747 1748 synchronize_irq(rtlpci->pdev->irq); 1749 tasklet_kill(&rtlpriv->works.irq_tasklet); 1750 cancel_work_sync(&rtlpriv->works.lps_change_work); 1751 1752 flush_workqueue(rtlpriv->works.rtl_wq); 1753 destroy_workqueue(rtlpriv->works.rtl_wq); 1754 } 1755 1756 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev) 1757 { 1758 int err; 1759 1760 _rtl_pci_init_struct(hw, pdev); 1761 1762 err = _rtl_pci_init_trx_ring(hw); 1763 if (err) { 1764 pr_err("tx ring initialization failed\n"); 1765 return err; 1766 } 1767 1768 return 0; 1769 } 1770 1771 static int rtl_pci_start(struct ieee80211_hw *hw) 1772 { 1773 struct rtl_priv *rtlpriv = rtl_priv(hw); 1774 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1775 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1776 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1777 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw)); 1778 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops; 1779 1780 int err; 1781 1782 rtl_pci_reset_trx_ring(hw); 1783 1784 rtlpci->driver_is_goingto_unload = false; 1785 if (rtlpriv->cfg->ops->get_btc_status && 1786 rtlpriv->cfg->ops->get_btc_status()) { 1787 rtlpriv->btcoexist.btc_info.ap_num = 36; 1788 btc_ops->btc_init_variables(rtlpriv); 1789 btc_ops->btc_init_hal_vars(rtlpriv); 1790 } else if (btc_ops) { 1791 btc_ops->btc_init_variables_wifi_only(rtlpriv); 1792 } 1793 1794 err = rtlpriv->cfg->ops->hw_init(hw); 1795 if (err) { 1796 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1797 "Failed to config hardware!\n"); 1798 kfree(rtlpriv->btcoexist.btc_context); 1799 kfree(rtlpriv->btcoexist.wifi_only_context); 1800 return err; 1801 } 1802 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, 1803 &rtlmac->retry_long); 1804 1805 rtlpriv->cfg->ops->enable_interrupt(hw); 1806 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); 1807 1808 rtl_init_rx_config(hw); 1809 1810 /*should be after adapter start and interrupt enable. */ 1811 set_hal_start(rtlhal); 1812 1813 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1814 1815 rtlpci->up_first_time = false; 1816 1817 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__); 1818 return 0; 1819 } 1820 1821 static void rtl_pci_stop(struct ieee80211_hw *hw) 1822 { 1823 struct rtl_priv *rtlpriv = rtl_priv(hw); 1824 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1825 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1826 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1827 unsigned long flags; 1828 u8 rf_timeout = 0; 1829 1830 if (rtlpriv->cfg->ops->get_btc_status()) 1831 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv); 1832 1833 if (rtlpriv->btcoexist.btc_ops) 1834 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv); 1835 1836 /*should be before disable interrupt&adapter 1837 *and will do it immediately. 1838 */ 1839 set_hal_stop(rtlhal); 1840 1841 rtlpci->driver_is_goingto_unload = true; 1842 rtlpriv->cfg->ops->disable_interrupt(hw); 1843 cancel_work_sync(&rtlpriv->works.lps_change_work); 1844 1845 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1846 while (ppsc->rfchange_inprogress) { 1847 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1848 if (rf_timeout > 100) { 1849 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1850 break; 1851 } 1852 mdelay(1); 1853 rf_timeout++; 1854 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1855 } 1856 ppsc->rfchange_inprogress = true; 1857 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1858 1859 rtlpriv->cfg->ops->hw_disable(hw); 1860 /* some things are not needed if firmware not available */ 1861 if (!rtlpriv->max_fw_size) 1862 return; 1863 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1864 1865 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1866 ppsc->rfchange_inprogress = false; 1867 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1868 1869 rtl_pci_enable_aspm(hw); 1870 } 1871 1872 static bool _rtl_pci_find_adapter(struct pci_dev *pdev, 1873 struct ieee80211_hw *hw) 1874 { 1875 struct rtl_priv *rtlpriv = rtl_priv(hw); 1876 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1877 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1878 struct pci_dev *bridge_pdev = pdev->bus->self; 1879 u16 venderid; 1880 u16 deviceid; 1881 u8 revisionid; 1882 u16 irqline; 1883 u8 tmp; 1884 1885 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1886 venderid = pdev->vendor; 1887 deviceid = pdev->device; 1888 pci_read_config_byte(pdev, 0x8, &revisionid); 1889 pci_read_config_word(pdev, 0x3C, &irqline); 1890 1891 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses 1892 * r8192e_pci, and RTL8192SE, which uses this driver. If the 1893 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then 1894 * the correct driver is r8192e_pci, thus this routine should 1895 * return false. 1896 */ 1897 if (deviceid == RTL_PCI_8192SE_DID && 1898 revisionid == RTL_PCI_REVISION_ID_8192PCIE) 1899 return false; 1900 1901 if (deviceid == RTL_PCI_8192_DID || 1902 deviceid == RTL_PCI_0044_DID || 1903 deviceid == RTL_PCI_0047_DID || 1904 deviceid == RTL_PCI_8192SE_DID || 1905 deviceid == RTL_PCI_8174_DID || 1906 deviceid == RTL_PCI_8173_DID || 1907 deviceid == RTL_PCI_8172_DID || 1908 deviceid == RTL_PCI_8171_DID) { 1909 switch (revisionid) { 1910 case RTL_PCI_REVISION_ID_8192PCIE: 1911 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1912 "8192 PCI-E is found - vid/did=%x/%x\n", 1913 venderid, deviceid); 1914 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E; 1915 return false; 1916 case RTL_PCI_REVISION_ID_8192SE: 1917 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1918 "8192SE is found - vid/did=%x/%x\n", 1919 venderid, deviceid); 1920 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1921 break; 1922 default: 1923 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1924 "Err: Unknown device - vid/did=%x/%x\n", 1925 venderid, deviceid); 1926 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1927 break; 1928 } 1929 } else if (deviceid == RTL_PCI_8723AE_DID) { 1930 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE; 1931 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1932 "8723AE PCI-E is found - vid/did=%x/%x\n", 1933 venderid, deviceid); 1934 } else if (deviceid == RTL_PCI_8192CET_DID || 1935 deviceid == RTL_PCI_8192CE_DID || 1936 deviceid == RTL_PCI_8191CE_DID || 1937 deviceid == RTL_PCI_8188CE_DID) { 1938 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE; 1939 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1940 "8192C PCI-E is found - vid/did=%x/%x\n", 1941 venderid, deviceid); 1942 } else if (deviceid == RTL_PCI_8192DE_DID || 1943 deviceid == RTL_PCI_8192DE_DID2) { 1944 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE; 1945 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1946 "8192D PCI-E is found - vid/did=%x/%x\n", 1947 venderid, deviceid); 1948 } else if (deviceid == RTL_PCI_8188EE_DID) { 1949 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE; 1950 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1951 "Find adapter, Hardware type is 8188EE\n"); 1952 } else if (deviceid == RTL_PCI_8723BE_DID) { 1953 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE; 1954 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1955 "Find adapter, Hardware type is 8723BE\n"); 1956 } else if (deviceid == RTL_PCI_8192EE_DID) { 1957 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE; 1958 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1959 "Find adapter, Hardware type is 8192EE\n"); 1960 } else if (deviceid == RTL_PCI_8821AE_DID) { 1961 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE; 1962 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1963 "Find adapter, Hardware type is 8821AE\n"); 1964 } else if (deviceid == RTL_PCI_8812AE_DID) { 1965 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE; 1966 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1967 "Find adapter, Hardware type is 8812AE\n"); 1968 } else if (deviceid == RTL_PCI_8822BE_DID) { 1969 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE; 1970 rtlhal->bandset = BAND_ON_BOTH; 1971 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1972 "Find adapter, Hardware type is 8822BE\n"); 1973 } else { 1974 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1975 "Err: Unknown device - vid/did=%x/%x\n", 1976 venderid, deviceid); 1977 1978 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE; 1979 } 1980 1981 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) { 1982 if (revisionid == 0 || revisionid == 1) { 1983 if (revisionid == 0) { 1984 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1985 "Find 92DE MAC0\n"); 1986 rtlhal->interfaceindex = 0; 1987 } else if (revisionid == 1) { 1988 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1989 "Find 92DE MAC1\n"); 1990 rtlhal->interfaceindex = 1; 1991 } 1992 } else { 1993 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1994 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", 1995 venderid, deviceid, revisionid); 1996 rtlhal->interfaceindex = 0; 1997 } 1998 } 1999 2000 switch (rtlhal->hw_type) { 2001 case HARDWARE_TYPE_RTL8192EE: 2002 case HARDWARE_TYPE_RTL8822BE: 2003 /* use new trx flow */ 2004 rtlpriv->use_new_trx_flow = true; 2005 break; 2006 2007 default: 2008 rtlpriv->use_new_trx_flow = false; 2009 break; 2010 } 2011 2012 /*find bus info */ 2013 pcipriv->ndis_adapter.busnumber = pdev->bus->number; 2014 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn); 2015 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn); 2016 2017 /*find bridge info */ 2018 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 2019 /* some ARM have no bridge_pdev and will crash here 2020 * so we should check if bridge_pdev is NULL 2021 */ 2022 if (bridge_pdev) { 2023 /*find bridge info if available */ 2024 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor; 2025 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { 2026 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { 2027 pcipriv->ndis_adapter.pcibridge_vendor = tmp; 2028 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2029 "Pci Bridge Vendor is found index: %d\n", 2030 tmp); 2031 break; 2032 } 2033 } 2034 } 2035 2036 if (pcipriv->ndis_adapter.pcibridge_vendor != 2037 PCI_BRIDGE_VENDOR_UNKNOWN) { 2038 pcipriv->ndis_adapter.pcibridge_busnum = 2039 bridge_pdev->bus->number; 2040 pcipriv->ndis_adapter.pcibridge_devnum = 2041 PCI_SLOT(bridge_pdev->devfn); 2042 pcipriv->ndis_adapter.pcibridge_funcnum = 2043 PCI_FUNC(bridge_pdev->devfn); 2044 pcipriv->ndis_adapter.pcibridge_pciehdr_offset = 2045 pci_pcie_cap(bridge_pdev); 2046 pcipriv->ndis_adapter.num4bytes = 2047 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4; 2048 2049 rtl_pci_get_linkcontrol_field(hw); 2050 2051 if (pcipriv->ndis_adapter.pcibridge_vendor == 2052 PCI_BRIDGE_VENDOR_AMD) { 2053 pcipriv->ndis_adapter.amd_l1_patch = 2054 rtl_pci_get_amd_l1_patch(hw); 2055 } 2056 } 2057 2058 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2059 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", 2060 pcipriv->ndis_adapter.busnumber, 2061 pcipriv->ndis_adapter.devnumber, 2062 pcipriv->ndis_adapter.funcnumber, 2063 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); 2064 2065 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2066 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n", 2067 pcipriv->ndis_adapter.pcibridge_busnum, 2068 pcipriv->ndis_adapter.pcibridge_devnum, 2069 pcipriv->ndis_adapter.pcibridge_funcnum, 2070 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], 2071 pcipriv->ndis_adapter.pcibridge_pciehdr_offset, 2072 pcipriv->ndis_adapter.pcibridge_linkctrlreg, 2073 pcipriv->ndis_adapter.amd_l1_patch); 2074 2075 rtl_pci_parse_configuration(pdev, hw); 2076 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list); 2077 2078 return true; 2079 } 2080 2081 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw) 2082 { 2083 struct rtl_priv *rtlpriv = rtl_priv(hw); 2084 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2085 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2086 int ret; 2087 2088 ret = pci_enable_msi(rtlpci->pdev); 2089 if (ret < 0) 2090 return ret; 2091 2092 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2093 IRQF_SHARED, KBUILD_MODNAME, hw); 2094 if (ret < 0) { 2095 pci_disable_msi(rtlpci->pdev); 2096 return ret; 2097 } 2098 2099 rtlpci->using_msi = true; 2100 2101 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 2102 "MSI Interrupt Mode!\n"); 2103 return 0; 2104 } 2105 2106 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw) 2107 { 2108 struct rtl_priv *rtlpriv = rtl_priv(hw); 2109 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2110 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2111 int ret; 2112 2113 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2114 IRQF_SHARED, KBUILD_MODNAME, hw); 2115 if (ret < 0) 2116 return ret; 2117 2118 rtlpci->using_msi = false; 2119 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 2120 "Pin-based Interrupt Mode!\n"); 2121 return 0; 2122 } 2123 2124 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw) 2125 { 2126 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2127 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2128 int ret; 2129 2130 if (rtlpci->msi_support) { 2131 ret = rtl_pci_intr_mode_msi(hw); 2132 if (ret < 0) 2133 ret = rtl_pci_intr_mode_legacy(hw); 2134 } else { 2135 ret = rtl_pci_intr_mode_legacy(hw); 2136 } 2137 return ret; 2138 } 2139 2140 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64) 2141 { 2142 u8 value; 2143 2144 pci_read_config_byte(pdev, 0x719, &value); 2145 2146 /* 0x719 Bit5 is DMA64 bit fetch. */ 2147 if (dma64) 2148 value |= BIT(5); 2149 else 2150 value &= ~BIT(5); 2151 2152 pci_write_config_byte(pdev, 0x719, value); 2153 } 2154 2155 int rtl_pci_probe(struct pci_dev *pdev, 2156 const struct pci_device_id *id) 2157 { 2158 struct ieee80211_hw *hw = NULL; 2159 2160 struct rtl_priv *rtlpriv = NULL; 2161 struct rtl_pci_priv *pcipriv = NULL; 2162 struct rtl_pci *rtlpci; 2163 unsigned long pmem_start, pmem_len, pmem_flags; 2164 int err; 2165 2166 err = pci_enable_device(pdev); 2167 if (err) { 2168 WARN_ONCE(true, "%s : Cannot enable new PCI device\n", 2169 pci_name(pdev)); 2170 return err; 2171 } 2172 2173 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 && 2174 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 2175 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { 2176 WARN_ONCE(true, 2177 "Unable to obtain 64bit DMA for consistent allocations\n"); 2178 err = -ENOMEM; 2179 goto fail1; 2180 } 2181 2182 platform_enable_dma64(pdev, true); 2183 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 2184 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 2185 WARN_ONCE(true, 2186 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n"); 2187 err = -ENOMEM; 2188 goto fail1; 2189 } 2190 2191 platform_enable_dma64(pdev, false); 2192 } 2193 2194 pci_set_master(pdev); 2195 2196 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) + 2197 sizeof(struct rtl_priv), &rtl_ops); 2198 if (!hw) { 2199 WARN_ONCE(true, 2200 "%s : ieee80211 alloc failed\n", pci_name(pdev)); 2201 err = -ENOMEM; 2202 goto fail1; 2203 } 2204 2205 SET_IEEE80211_DEV(hw, &pdev->dev); 2206 pci_set_drvdata(pdev, hw); 2207 2208 rtlpriv = hw->priv; 2209 rtlpriv->hw = hw; 2210 pcipriv = (void *)rtlpriv->priv; 2211 pcipriv->dev.pdev = pdev; 2212 init_completion(&rtlpriv->firmware_loading_complete); 2213 /*proximity init here*/ 2214 rtlpriv->proximity.proxim_on = false; 2215 2216 pcipriv = (void *)rtlpriv->priv; 2217 pcipriv->dev.pdev = pdev; 2218 2219 /* init cfg & intf_ops */ 2220 rtlpriv->rtlhal.interface = INTF_PCI; 2221 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data); 2222 rtlpriv->intf_ops = &rtl_pci_ops; 2223 rtlpriv->glb_var = &rtl_global_var; 2224 rtl_efuse_ops_init(hw); 2225 2226 /* MEM map */ 2227 err = pci_request_regions(pdev, KBUILD_MODNAME); 2228 if (err) { 2229 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n"); 2230 goto fail1; 2231 } 2232 2233 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id); 2234 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id); 2235 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id); 2236 2237 /*shared mem start */ 2238 rtlpriv->io.pci_mem_start = 2239 (unsigned long)pci_iomap(pdev, 2240 rtlpriv->cfg->bar_id, pmem_len); 2241 if (rtlpriv->io.pci_mem_start == 0) { 2242 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n"); 2243 err = -ENOMEM; 2244 goto fail2; 2245 } 2246 2247 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2248 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", 2249 pmem_start, pmem_len, pmem_flags, 2250 rtlpriv->io.pci_mem_start); 2251 2252 /* Disable Clk Request */ 2253 pci_write_config_byte(pdev, 0x81, 0); 2254 /* leave D3 mode */ 2255 pci_write_config_byte(pdev, 0x44, 0); 2256 pci_write_config_byte(pdev, 0x04, 0x06); 2257 pci_write_config_byte(pdev, 0x04, 0x07); 2258 2259 /* find adapter */ 2260 if (!_rtl_pci_find_adapter(pdev, hw)) { 2261 err = -ENODEV; 2262 goto fail2; 2263 } 2264 2265 /* Init IO handler */ 2266 _rtl_pci_io_handler_init(&pdev->dev, hw); 2267 2268 /*like read eeprom and so on */ 2269 rtlpriv->cfg->ops->read_eeprom_info(hw); 2270 2271 if (rtlpriv->cfg->ops->init_sw_vars(hw)) { 2272 pr_err("Can't init_sw_vars\n"); 2273 err = -ENODEV; 2274 goto fail3; 2275 } 2276 rtlpriv->cfg->ops->init_sw_leds(hw); 2277 2278 /*aspm */ 2279 rtl_pci_init_aspm(hw); 2280 2281 /* Init mac80211 sw */ 2282 err = rtl_init_core(hw); 2283 if (err) { 2284 pr_err("Can't allocate sw for mac80211\n"); 2285 goto fail3; 2286 } 2287 2288 /* Init PCI sw */ 2289 err = rtl_pci_init(hw, pdev); 2290 if (err) { 2291 pr_err("Failed to init PCI\n"); 2292 goto fail3; 2293 } 2294 2295 err = ieee80211_register_hw(hw); 2296 if (err) { 2297 pr_err("Can't register mac80211 hw.\n"); 2298 err = -ENODEV; 2299 goto fail3; 2300 } 2301 rtlpriv->mac80211.mac80211_registered = 1; 2302 2303 /* add for debug */ 2304 rtl_debug_add_one(hw); 2305 2306 /*init rfkill */ 2307 rtl_init_rfkill(hw); /* Init PCI sw */ 2308 2309 rtlpci = rtl_pcidev(pcipriv); 2310 err = rtl_pci_intr_mode_decide(hw); 2311 if (err) { 2312 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2313 "%s: failed to register IRQ handler\n", 2314 wiphy_name(hw->wiphy)); 2315 goto fail3; 2316 } 2317 rtlpci->irq_alloc = 1; 2318 2319 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2320 return 0; 2321 2322 fail3: 2323 pci_set_drvdata(pdev, NULL); 2324 rtl_deinit_core(hw); 2325 2326 fail2: 2327 if (rtlpriv->io.pci_mem_start != 0) 2328 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2329 2330 pci_release_regions(pdev); 2331 complete(&rtlpriv->firmware_loading_complete); 2332 2333 fail1: 2334 if (hw) 2335 ieee80211_free_hw(hw); 2336 pci_disable_device(pdev); 2337 2338 return err; 2339 } 2340 EXPORT_SYMBOL(rtl_pci_probe); 2341 2342 void rtl_pci_disconnect(struct pci_dev *pdev) 2343 { 2344 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2345 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2346 struct rtl_priv *rtlpriv = rtl_priv(hw); 2347 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2348 struct rtl_mac *rtlmac = rtl_mac(rtlpriv); 2349 2350 /* just in case driver is removed before firmware callback */ 2351 wait_for_completion(&rtlpriv->firmware_loading_complete); 2352 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2353 2354 /* remove form debug */ 2355 rtl_debug_remove_one(hw); 2356 2357 /*ieee80211_unregister_hw will call ops_stop */ 2358 if (rtlmac->mac80211_registered == 1) { 2359 ieee80211_unregister_hw(hw); 2360 rtlmac->mac80211_registered = 0; 2361 } else { 2362 rtl_deinit_deferred_work(hw, false); 2363 rtlpriv->intf_ops->adapter_stop(hw); 2364 } 2365 rtlpriv->cfg->ops->disable_interrupt(hw); 2366 2367 /*deinit rfkill */ 2368 rtl_deinit_rfkill(hw); 2369 2370 rtl_pci_deinit(hw); 2371 rtl_deinit_core(hw); 2372 rtlpriv->cfg->ops->deinit_sw_vars(hw); 2373 2374 if (rtlpci->irq_alloc) { 2375 free_irq(rtlpci->pdev->irq, hw); 2376 rtlpci->irq_alloc = 0; 2377 } 2378 2379 if (rtlpci->using_msi) 2380 pci_disable_msi(rtlpci->pdev); 2381 2382 list_del(&rtlpriv->list); 2383 if (rtlpriv->io.pci_mem_start != 0) { 2384 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2385 pci_release_regions(pdev); 2386 } 2387 2388 pci_disable_device(pdev); 2389 2390 rtl_pci_disable_aspm(hw); 2391 2392 pci_set_drvdata(pdev, NULL); 2393 2394 ieee80211_free_hw(hw); 2395 } 2396 EXPORT_SYMBOL(rtl_pci_disconnect); 2397 2398 #ifdef CONFIG_PM_SLEEP 2399 /*************************************** 2400 * kernel pci power state define: 2401 * PCI_D0 ((pci_power_t __force) 0) 2402 * PCI_D1 ((pci_power_t __force) 1) 2403 * PCI_D2 ((pci_power_t __force) 2) 2404 * PCI_D3hot ((pci_power_t __force) 3) 2405 * PCI_D3cold ((pci_power_t __force) 4) 2406 * PCI_UNKNOWN ((pci_power_t __force) 5) 2407 2408 * This function is called when system 2409 * goes into suspend state mac80211 will 2410 * call rtl_mac_stop() from the mac80211 2411 * suspend function first, So there is 2412 * no need to call hw_disable here. 2413 ****************************************/ 2414 int rtl_pci_suspend(struct device *dev) 2415 { 2416 struct ieee80211_hw *hw = dev_get_drvdata(dev); 2417 struct rtl_priv *rtlpriv = rtl_priv(hw); 2418 2419 rtlpriv->cfg->ops->hw_suspend(hw); 2420 rtl_deinit_rfkill(hw); 2421 2422 return 0; 2423 } 2424 EXPORT_SYMBOL(rtl_pci_suspend); 2425 2426 int rtl_pci_resume(struct device *dev) 2427 { 2428 struct ieee80211_hw *hw = dev_get_drvdata(dev); 2429 struct rtl_priv *rtlpriv = rtl_priv(hw); 2430 2431 rtlpriv->cfg->ops->hw_resume(hw); 2432 rtl_init_rfkill(hw); 2433 return 0; 2434 } 2435 EXPORT_SYMBOL(rtl_pci_resume); 2436 #endif /* CONFIG_PM_SLEEP */ 2437 2438 const struct rtl_intf_ops rtl_pci_ops = { 2439 .read_efuse_byte = read_efuse_byte, 2440 .adapter_start = rtl_pci_start, 2441 .adapter_stop = rtl_pci_stop, 2442 .check_buddy_priv = rtl_pci_check_buddy_priv, 2443 .adapter_tx = rtl_pci_tx, 2444 .flush = rtl_pci_flush, 2445 .reset_trx_ring = rtl_pci_reset_trx_ring, 2446 .waitq_insert = rtl_pci_tx_chk_waitq_insert, 2447 2448 .disable_aspm = rtl_pci_disable_aspm, 2449 .enable_aspm = rtl_pci_enable_aspm, 2450 }; 2451