1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "wifi.h" 27 #include "core.h" 28 #include "pci.h" 29 #include "base.h" 30 #include "ps.h" 31 #include "efuse.h" 32 #include <linux/interrupt.h> 33 #include <linux/export.h> 34 #include <linux/kmemleak.h> 35 #include <linux/module.h> 36 37 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 38 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 39 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>"); 40 MODULE_LICENSE("GPL"); 41 MODULE_DESCRIPTION("PCI basic driver for rtlwifi"); 42 43 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { 44 INTEL_VENDOR_ID, 45 ATI_VENDOR_ID, 46 AMD_VENDOR_ID, 47 SIS_VENDOR_ID 48 }; 49 50 static const u8 ac_to_hwq[] = { 51 VO_QUEUE, 52 VI_QUEUE, 53 BE_QUEUE, 54 BK_QUEUE 55 }; 56 57 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, 58 struct sk_buff *skb) 59 { 60 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 61 __le16 fc = rtl_get_fc(skb); 62 u8 queue_index = skb_get_queue_mapping(skb); 63 64 if (unlikely(ieee80211_is_beacon(fc))) 65 return BEACON_QUEUE; 66 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) 67 return MGNT_QUEUE; 68 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 69 if (ieee80211_is_nullfunc(fc)) 70 return HIGH_QUEUE; 71 72 return ac_to_hwq[queue_index]; 73 } 74 75 /* Update PCI dependent default settings*/ 76 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) 77 { 78 struct rtl_priv *rtlpriv = rtl_priv(hw); 79 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 80 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 81 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 82 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 83 u8 init_aspm; 84 85 ppsc->reg_rfps_level = 0; 86 ppsc->support_aspm = false; 87 88 /*Update PCI ASPM setting */ 89 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm; 90 switch (rtlpci->const_pci_aspm) { 91 case 0: 92 /*No ASPM */ 93 break; 94 95 case 1: 96 /*ASPM dynamically enabled/disable. */ 97 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; 98 break; 99 100 case 2: 101 /*ASPM with Clock Req dynamically enabled/disable. */ 102 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | 103 RT_RF_OFF_LEVL_CLK_REQ); 104 break; 105 106 case 3: 107 /* 108 * Always enable ASPM and Clock Req 109 * from initialization to halt. 110 * */ 111 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); 112 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | 113 RT_RF_OFF_LEVL_CLK_REQ); 114 break; 115 116 case 4: 117 /* 118 * Always enable ASPM without Clock Req 119 * from initialization to halt. 120 * */ 121 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | 122 RT_RF_OFF_LEVL_CLK_REQ); 123 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; 124 break; 125 } 126 127 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 128 129 /*Update Radio OFF setting */ 130 switch (rtlpci->const_hwsw_rfoff_d3) { 131 case 1: 132 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 133 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 134 break; 135 136 case 2: 137 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 138 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 139 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 140 break; 141 142 case 3: 143 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; 144 break; 145 } 146 147 /*Set HW definition to determine if it supports ASPM. */ 148 switch (rtlpci->const_support_pciaspm) { 149 case 0:{ 150 /*Not support ASPM. */ 151 bool support_aspm = false; 152 ppsc->support_aspm = support_aspm; 153 break; 154 } 155 case 1:{ 156 /*Support ASPM. */ 157 bool support_aspm = true; 158 bool support_backdoor = true; 159 ppsc->support_aspm = support_aspm; 160 161 /*if (priv->oem_id == RT_CID_TOSHIBA && 162 !priv->ndis_adapter.amd_l1_patch) 163 support_backdoor = false; */ 164 165 ppsc->support_backdoor = support_backdoor; 166 167 break; 168 } 169 case 2: 170 /*ASPM value set by chipset. */ 171 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) { 172 bool support_aspm = true; 173 ppsc->support_aspm = support_aspm; 174 } 175 break; 176 default: 177 pr_err("switch case %#x not processed\n", 178 rtlpci->const_support_pciaspm); 179 break; 180 } 181 182 /* toshiba aspm issue, toshiba will set aspm selfly 183 * so we should not set aspm in driver */ 184 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm); 185 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE && 186 init_aspm == 0x43) 187 ppsc->support_aspm = false; 188 } 189 190 static bool _rtl_pci_platform_switch_device_pci_aspm( 191 struct ieee80211_hw *hw, 192 u8 value) 193 { 194 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 195 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 196 197 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE) 198 value |= 0x40; 199 200 pci_write_config_byte(rtlpci->pdev, 0x80, value); 201 202 return false; 203 } 204 205 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/ 206 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value) 207 { 208 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 209 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 210 211 pci_write_config_byte(rtlpci->pdev, 0x81, value); 212 213 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 214 udelay(100); 215 } 216 217 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ 218 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) 219 { 220 struct rtl_priv *rtlpriv = rtl_priv(hw); 221 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 222 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 223 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 224 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 225 u8 num4bytes = pcipriv->ndis_adapter.num4bytes; 226 /*Retrieve original configuration settings. */ 227 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg; 228 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter. 229 pcibridge_linkctrlreg; 230 u16 aspmlevel = 0; 231 u8 tmp_u1b = 0; 232 233 if (!ppsc->support_aspm) 234 return; 235 236 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 237 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 238 "PCI(Bridge) UNKNOWN\n"); 239 240 return; 241 } 242 243 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 244 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 245 _rtl_pci_switch_clk_req(hw, 0x0); 246 } 247 248 /*for promising device will in L0 state after an I/O. */ 249 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b); 250 251 /*Set corresponding value. */ 252 aspmlevel |= BIT(0) | BIT(1); 253 linkctrl_reg &= ~aspmlevel; 254 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1)); 255 256 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg); 257 udelay(50); 258 259 /*4 Disable Pci Bridge ASPM */ 260 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), 261 pcibridge_linkctrlreg); 262 263 udelay(50); 264 } 265 266 /* 267 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for 268 *power saving We should follow the sequence to enable 269 *RTL8192SE first then enable Pci Bridge ASPM 270 *or the system will show bluescreen. 271 */ 272 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) 273 { 274 struct rtl_priv *rtlpriv = rtl_priv(hw); 275 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 276 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 277 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 278 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 279 u8 num4bytes = pcipriv->ndis_adapter.num4bytes; 280 u16 aspmlevel; 281 u8 u_pcibridge_aspmsetting; 282 u8 u_device_aspmsetting; 283 284 if (!ppsc->support_aspm) 285 return; 286 287 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 288 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 289 "PCI(Bridge) UNKNOWN\n"); 290 return; 291 } 292 293 /*4 Enable Pci Bridge ASPM */ 294 295 u_pcibridge_aspmsetting = 296 pcipriv->ndis_adapter.pcibridge_linkctrlreg | 297 rtlpci->const_hostpci_aspm_setting; 298 299 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) 300 u_pcibridge_aspmsetting &= ~BIT(0); 301 302 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), 303 u_pcibridge_aspmsetting); 304 305 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 306 "PlatformEnableASPM(): Write reg[%x] = %x\n", 307 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10), 308 u_pcibridge_aspmsetting); 309 310 udelay(50); 311 312 /*Get ASPM level (with/without Clock Req) */ 313 aspmlevel = rtlpci->const_devicepci_aspm_setting; 314 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg; 315 316 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/ 317 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */ 318 319 u_device_aspmsetting |= aspmlevel; 320 321 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting); 322 323 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 324 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level & 325 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0); 326 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 327 } 328 udelay(100); 329 } 330 331 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw) 332 { 333 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 334 335 bool status = false; 336 u8 offset_e0; 337 unsigned offset_e4; 338 339 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0); 340 341 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0); 342 343 if (offset_e0 == 0xA0) { 344 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4); 345 if (offset_e4 & BIT(23)) 346 status = true; 347 } 348 349 return status; 350 } 351 352 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw, 353 struct rtl_priv **buddy_priv) 354 { 355 struct rtl_priv *rtlpriv = rtl_priv(hw); 356 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 357 bool find_buddy_priv = false; 358 struct rtl_priv *tpriv; 359 struct rtl_pci_priv *tpcipriv = NULL; 360 361 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) { 362 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list, 363 list) { 364 tpcipriv = (struct rtl_pci_priv *)tpriv->priv; 365 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 366 "pcipriv->ndis_adapter.funcnumber %x\n", 367 pcipriv->ndis_adapter.funcnumber); 368 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 369 "tpcipriv->ndis_adapter.funcnumber %x\n", 370 tpcipriv->ndis_adapter.funcnumber); 371 372 if ((pcipriv->ndis_adapter.busnumber == 373 tpcipriv->ndis_adapter.busnumber) && 374 (pcipriv->ndis_adapter.devnumber == 375 tpcipriv->ndis_adapter.devnumber) && 376 (pcipriv->ndis_adapter.funcnumber != 377 tpcipriv->ndis_adapter.funcnumber)) { 378 find_buddy_priv = true; 379 break; 380 } 381 } 382 } 383 384 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 385 "find_buddy_priv %d\n", find_buddy_priv); 386 387 if (find_buddy_priv) 388 *buddy_priv = tpriv; 389 390 return find_buddy_priv; 391 } 392 393 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw) 394 { 395 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 396 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 397 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset; 398 u8 linkctrl_reg; 399 u8 num4bbytes; 400 401 num4bbytes = (capabilityoffset + 0x10) / 4; 402 403 /*Read Link Control Register */ 404 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg); 405 406 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg; 407 } 408 409 static void rtl_pci_parse_configuration(struct pci_dev *pdev, 410 struct ieee80211_hw *hw) 411 { 412 struct rtl_priv *rtlpriv = rtl_priv(hw); 413 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 414 415 u8 tmp; 416 u16 linkctrl_reg; 417 418 /*Link Control Register */ 419 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg); 420 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg; 421 422 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", 423 pcipriv->ndis_adapter.linkctrl_reg); 424 425 pci_read_config_byte(pdev, 0x98, &tmp); 426 tmp |= BIT(4); 427 pci_write_config_byte(pdev, 0x98, tmp); 428 429 tmp = 0x17; 430 pci_write_config_byte(pdev, 0x70f, tmp); 431 } 432 433 static void rtl_pci_init_aspm(struct ieee80211_hw *hw) 434 { 435 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 436 437 _rtl_pci_update_default_setting(hw); 438 439 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { 440 /*Always enable ASPM & Clock Req. */ 441 rtl_pci_enable_aspm(hw); 442 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM); 443 } 444 445 } 446 447 static void _rtl_pci_io_handler_init(struct device *dev, 448 struct ieee80211_hw *hw) 449 { 450 struct rtl_priv *rtlpriv = rtl_priv(hw); 451 452 rtlpriv->io.dev = dev; 453 454 rtlpriv->io.write8_async = pci_write8_async; 455 rtlpriv->io.write16_async = pci_write16_async; 456 rtlpriv->io.write32_async = pci_write32_async; 457 458 rtlpriv->io.read8_sync = pci_read8_sync; 459 rtlpriv->io.read16_sync = pci_read16_sync; 460 rtlpriv->io.read32_sync = pci_read32_sync; 461 462 } 463 464 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw, 465 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid) 466 { 467 struct rtl_priv *rtlpriv = rtl_priv(hw); 468 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 469 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 470 struct sk_buff *next_skb; 471 u8 additionlen = FCS_LEN; 472 473 /* here open is 4, wep/tkip is 8, aes is 12*/ 474 if (info->control.hw_key) 475 additionlen += info->control.hw_key->icv_len; 476 477 /* The most skb num is 6 */ 478 tcb_desc->empkt_num = 0; 479 spin_lock_bh(&rtlpriv->locks.waitq_lock); 480 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) { 481 struct ieee80211_tx_info *next_info; 482 483 next_info = IEEE80211_SKB_CB(next_skb); 484 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) { 485 tcb_desc->empkt_len[tcb_desc->empkt_num] = 486 next_skb->len + additionlen; 487 tcb_desc->empkt_num++; 488 } else { 489 break; 490 } 491 492 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid], 493 next_skb)) 494 break; 495 496 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num) 497 break; 498 } 499 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 500 501 return true; 502 } 503 504 /* just for early mode now */ 505 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw) 506 { 507 struct rtl_priv *rtlpriv = rtl_priv(hw); 508 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 509 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 510 struct sk_buff *skb = NULL; 511 struct ieee80211_tx_info *info = NULL; 512 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 513 int tid; 514 515 if (!rtlpriv->rtlhal.earlymode_enable) 516 return; 517 518 if (rtlpriv->dm.supp_phymode_switch && 519 (rtlpriv->easy_concurrent_ctl.switch_in_process || 520 (rtlpriv->buddy_priv && 521 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process))) 522 return; 523 /* we juse use em for BE/BK/VI/VO */ 524 for (tid = 7; tid >= 0; tid--) { 525 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)]; 526 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; 527 while (!mac->act_scanning && 528 rtlpriv->psc.rfpwr_state == ERFON) { 529 struct rtl_tcb_desc tcb_desc; 530 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 531 532 spin_lock_bh(&rtlpriv->locks.waitq_lock); 533 if (!skb_queue_empty(&mac->skb_waitq[tid]) && 534 (ring->entries - skb_queue_len(&ring->queue) > 535 rtlhal->max_earlymode_num)) { 536 skb = skb_dequeue(&mac->skb_waitq[tid]); 537 } else { 538 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 539 break; 540 } 541 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 542 543 /* Some macaddr can't do early mode. like 544 * multicast/broadcast/no_qos data */ 545 info = IEEE80211_SKB_CB(skb); 546 if (info->flags & IEEE80211_TX_CTL_AMPDU) 547 _rtl_update_earlymode_info(hw, skb, 548 &tcb_desc, tid); 549 550 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc); 551 } 552 } 553 } 554 555 556 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) 557 { 558 struct rtl_priv *rtlpriv = rtl_priv(hw); 559 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 560 561 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 562 563 while (skb_queue_len(&ring->queue)) { 564 struct sk_buff *skb; 565 struct ieee80211_tx_info *info; 566 __le16 fc; 567 u8 tid; 568 u8 *entry; 569 570 if (rtlpriv->use_new_trx_flow) 571 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 572 else 573 entry = (u8 *)(&ring->desc[ring->idx]); 574 575 if (rtlpriv->cfg->ops->get_available_desc && 576 rtlpriv->cfg->ops->get_available_desc(hw, prio) <= 1) { 577 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_DMESG, 578 "no available desc!\n"); 579 return; 580 } 581 582 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx)) 583 return; 584 ring->idx = (ring->idx + 1) % ring->entries; 585 586 skb = __skb_dequeue(&ring->queue); 587 pci_unmap_single(rtlpci->pdev, 588 rtlpriv->cfg->ops-> 589 get_desc((u8 *)entry, true, 590 HW_DESC_TXBUFF_ADDR), 591 skb->len, PCI_DMA_TODEVICE); 592 593 /* remove early mode header */ 594 if (rtlpriv->rtlhal.earlymode_enable) 595 skb_pull(skb, EM_HDR_LEN); 596 597 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, 598 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", 599 ring->idx, 600 skb_queue_len(&ring->queue), 601 *(u16 *)(skb->data + 22)); 602 603 if (prio == TXCMD_QUEUE) { 604 dev_kfree_skb(skb); 605 goto tx_status_ok; 606 607 } 608 609 /* for sw LPS, just after NULL skb send out, we can 610 * sure AP knows we are sleeping, we should not let 611 * rf sleep 612 */ 613 fc = rtl_get_fc(skb); 614 if (ieee80211_is_nullfunc(fc)) { 615 if (ieee80211_has_pm(fc)) { 616 rtlpriv->mac80211.offchan_delay = true; 617 rtlpriv->psc.state_inap = true; 618 } else { 619 rtlpriv->psc.state_inap = false; 620 } 621 } 622 if (ieee80211_is_action(fc)) { 623 struct ieee80211_mgmt *action_frame = 624 (struct ieee80211_mgmt *)skb->data; 625 if (action_frame->u.action.u.ht_smps.action == 626 WLAN_HT_ACTION_SMPS) { 627 dev_kfree_skb(skb); 628 goto tx_status_ok; 629 } 630 } 631 632 /* update tid tx pkt num */ 633 tid = rtl_get_tid(skb); 634 if (tid <= 7) 635 rtlpriv->link_info.tidtx_inperiod[tid]++; 636 637 info = IEEE80211_SKB_CB(skb); 638 ieee80211_tx_info_clear_status(info); 639 640 info->flags |= IEEE80211_TX_STAT_ACK; 641 /*info->status.rates[0].count = 1; */ 642 643 ieee80211_tx_status_irqsafe(hw, skb); 644 645 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) { 646 647 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, 648 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", 649 prio, ring->idx, 650 skb_queue_len(&ring->queue)); 651 652 ieee80211_wake_queue(hw, 653 skb_get_queue_mapping 654 (skb)); 655 } 656 tx_status_ok: 657 skb = NULL; 658 } 659 660 if (((rtlpriv->link_info.num_rx_inperiod + 661 rtlpriv->link_info.num_tx_inperiod) > 8) || 662 (rtlpriv->link_info.num_rx_inperiod > 2)) 663 rtl_lps_leave(hw); 664 } 665 666 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, 667 struct sk_buff *new_skb, u8 *entry, 668 int rxring_idx, int desc_idx) 669 { 670 struct rtl_priv *rtlpriv = rtl_priv(hw); 671 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 672 u32 bufferaddress; 673 u8 tmp_one = 1; 674 struct sk_buff *skb; 675 676 if (likely(new_skb)) { 677 skb = new_skb; 678 goto remap; 679 } 680 skb = dev_alloc_skb(rtlpci->rxbuffersize); 681 if (!skb) 682 return 0; 683 684 remap: 685 /* just set skb->cb to mapping addr for pci_unmap_single use */ 686 *((dma_addr_t *)skb->cb) = 687 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb), 688 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 689 bufferaddress = *((dma_addr_t *)skb->cb); 690 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress)) 691 return 0; 692 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb; 693 if (rtlpriv->use_new_trx_flow) { 694 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 695 HW_DESC_RX_PREPARE, 696 (u8 *)&bufferaddress); 697 } else { 698 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 699 HW_DESC_RXBUFF_ADDR, 700 (u8 *)&bufferaddress); 701 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 702 HW_DESC_RXPKT_LEN, 703 (u8 *)&rtlpci->rxbuffersize); 704 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 705 HW_DESC_RXOWN, 706 (u8 *)&tmp_one); 707 } 708 return 1; 709 } 710 711 /* inorder to receive 8K AMSDU we have set skb to 712 * 9100bytes in init rx ring, but if this packet is 713 * not a AMSDU, this large packet will be sent to 714 * TCP/IP directly, this cause big packet ping fail 715 * like: "ping -s 65507", so here we will realloc skb 716 * based on the true size of packet, Mac80211 717 * Probably will do it better, but does not yet. 718 * 719 * Some platform will fail when alloc skb sometimes. 720 * in this condition, we will send the old skb to 721 * mac80211 directly, this will not cause any other 722 * issues, but only this packet will be lost by TCP/IP 723 */ 724 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw, 725 struct sk_buff *skb, 726 struct ieee80211_rx_status rx_status) 727 { 728 if (unlikely(!rtl_action_proc(hw, skb, false))) { 729 dev_kfree_skb_any(skb); 730 } else { 731 struct sk_buff *uskb = NULL; 732 u8 *pdata; 733 734 uskb = dev_alloc_skb(skb->len + 128); 735 if (likely(uskb)) { 736 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, 737 sizeof(rx_status)); 738 pdata = (u8 *)skb_put(uskb, skb->len); 739 memcpy(pdata, skb->data, skb->len); 740 dev_kfree_skb_any(skb); 741 ieee80211_rx_irqsafe(hw, uskb); 742 } else { 743 ieee80211_rx_irqsafe(hw, skb); 744 } 745 } 746 } 747 748 /*hsisr interrupt handler*/ 749 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw) 750 { 751 struct rtl_priv *rtlpriv = rtl_priv(hw); 752 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 753 754 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR], 755 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) | 756 rtlpci->sys_irq_mask); 757 } 758 759 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) 760 { 761 struct rtl_priv *rtlpriv = rtl_priv(hw); 762 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 763 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE; 764 struct ieee80211_rx_status rx_status = { 0 }; 765 unsigned int count = rtlpci->rxringcount; 766 u8 own; 767 u8 tmp_one; 768 bool unicast = false; 769 u8 hw_queue = 0; 770 unsigned int rx_remained_cnt; 771 struct rtl_stats stats = { 772 .signal = 0, 773 .rate = 0, 774 }; 775 776 /*RX NORMAL PKT */ 777 while (count--) { 778 struct ieee80211_hdr *hdr; 779 __le16 fc; 780 u16 len; 781 /*rx buffer descriptor */ 782 struct rtl_rx_buffer_desc *buffer_desc = NULL; 783 /*if use new trx flow, it means wifi info */ 784 struct rtl_rx_desc *pdesc = NULL; 785 /*rx pkt */ 786 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[ 787 rtlpci->rx_ring[rxring_idx].idx]; 788 struct sk_buff *new_skb; 789 790 if (rtlpriv->use_new_trx_flow) { 791 rx_remained_cnt = 792 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw, 793 hw_queue); 794 if (rx_remained_cnt == 0) 795 return; 796 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[ 797 rtlpci->rx_ring[rxring_idx].idx]; 798 pdesc = (struct rtl_rx_desc *)skb->data; 799 } else { /* rx descriptor */ 800 pdesc = &rtlpci->rx_ring[rxring_idx].desc[ 801 rtlpci->rx_ring[rxring_idx].idx]; 802 803 own = (u8)rtlpriv->cfg->ops->get_desc((u8 *)pdesc, 804 false, 805 HW_DESC_OWN); 806 if (own) /* wait data to be filled by hardware */ 807 return; 808 } 809 810 /* Reaching this point means: data is filled already 811 * AAAAAAttention !!! 812 * We can NOT access 'skb' before 'pci_unmap_single' 813 */ 814 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), 815 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 816 817 /* get a new skb - if fail, old one will be reused */ 818 new_skb = dev_alloc_skb(rtlpci->rxbuffersize); 819 if (unlikely(!new_skb)) 820 goto no_new; 821 memset(&rx_status , 0 , sizeof(rx_status)); 822 rtlpriv->cfg->ops->query_rx_desc(hw, &stats, 823 &rx_status, (u8 *)pdesc, skb); 824 825 if (rtlpriv->use_new_trx_flow) 826 rtlpriv->cfg->ops->rx_check_dma_ok(hw, 827 (u8 *)buffer_desc, 828 hw_queue); 829 830 len = rtlpriv->cfg->ops->get_desc((u8 *)pdesc, false, 831 HW_DESC_RXPKT_LEN); 832 833 if (skb->end - skb->tail > len) { 834 skb_put(skb, len); 835 if (rtlpriv->use_new_trx_flow) 836 skb_reserve(skb, stats.rx_drvinfo_size + 837 stats.rx_bufshift + 24); 838 else 839 skb_reserve(skb, stats.rx_drvinfo_size + 840 stats.rx_bufshift); 841 } else { 842 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 843 "skb->end - skb->tail = %d, len is %d\n", 844 skb->end - skb->tail, len); 845 dev_kfree_skb_any(skb); 846 goto new_trx_end; 847 } 848 /* handle command packet here */ 849 if (rtlpriv->cfg->ops->rx_command_packet && 850 rtlpriv->cfg->ops->rx_command_packet(hw, &stats, skb)) { 851 dev_kfree_skb_any(skb); 852 goto new_trx_end; 853 } 854 855 /* 856 * NOTICE This can not be use for mac80211, 857 * this is done in mac80211 code, 858 * if done here sec DHCP will fail 859 * skb_trim(skb, skb->len - 4); 860 */ 861 862 hdr = rtl_get_hdr(skb); 863 fc = rtl_get_fc(skb); 864 865 if (!stats.crc && !stats.hwerror) { 866 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, 867 sizeof(rx_status)); 868 869 if (is_broadcast_ether_addr(hdr->addr1)) { 870 ;/*TODO*/ 871 } else if (is_multicast_ether_addr(hdr->addr1)) { 872 ;/*TODO*/ 873 } else { 874 unicast = true; 875 rtlpriv->stats.rxbytesunicast += skb->len; 876 } 877 rtl_is_special_data(hw, skb, false, true); 878 879 if (ieee80211_is_data(fc)) { 880 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX); 881 if (unicast) 882 rtlpriv->link_info.num_rx_inperiod++; 883 } 884 /* static bcn for roaming */ 885 rtl_beacon_statistic(hw, skb); 886 rtl_p2p_info(hw, (void *)skb->data, skb->len); 887 /* for sw lps */ 888 rtl_swlps_beacon(hw, (void *)skb->data, skb->len); 889 rtl_recognize_peer(hw, (void *)skb->data, skb->len); 890 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) && 891 (rtlpriv->rtlhal.current_bandtype == 892 BAND_ON_2_4G) && 893 (ieee80211_is_beacon(fc) || 894 ieee80211_is_probe_resp(fc))) { 895 dev_kfree_skb_any(skb); 896 } else { 897 _rtl_pci_rx_to_mac80211(hw, skb, rx_status); 898 } 899 } else { 900 dev_kfree_skb_any(skb); 901 } 902 new_trx_end: 903 if (rtlpriv->use_new_trx_flow) { 904 rtlpci->rx_ring[hw_queue].next_rx_rp += 1; 905 rtlpci->rx_ring[hw_queue].next_rx_rp %= 906 RTL_PCI_MAX_RX_COUNT; 907 908 rx_remained_cnt--; 909 rtl_write_word(rtlpriv, 0x3B4, 910 rtlpci->rx_ring[hw_queue].next_rx_rp); 911 } 912 if (((rtlpriv->link_info.num_rx_inperiod + 913 rtlpriv->link_info.num_tx_inperiod) > 8) || 914 (rtlpriv->link_info.num_rx_inperiod > 2)) 915 rtl_lps_leave(hw); 916 skb = new_skb; 917 no_new: 918 if (rtlpriv->use_new_trx_flow) { 919 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc, 920 rxring_idx, 921 rtlpci->rx_ring[rxring_idx].idx); 922 } else { 923 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc, 924 rxring_idx, 925 rtlpci->rx_ring[rxring_idx].idx); 926 if (rtlpci->rx_ring[rxring_idx].idx == 927 rtlpci->rxringcount - 1) 928 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, 929 false, 930 HW_DESC_RXERO, 931 (u8 *)&tmp_one); 932 } 933 rtlpci->rx_ring[rxring_idx].idx = 934 (rtlpci->rx_ring[rxring_idx].idx + 1) % 935 rtlpci->rxringcount; 936 } 937 } 938 939 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) 940 { 941 struct ieee80211_hw *hw = dev_id; 942 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 943 struct rtl_priv *rtlpriv = rtl_priv(hw); 944 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 945 unsigned long flags; 946 u32 inta = 0; 947 u32 intb = 0; 948 irqreturn_t ret = IRQ_HANDLED; 949 950 if (rtlpci->irq_enabled == 0) 951 return ret; 952 953 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock , flags); 954 rtlpriv->cfg->ops->disable_interrupt(hw); 955 956 /*read ISR: 4/8bytes */ 957 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb); 958 959 /*Shared IRQ or HW disappared */ 960 if (!inta || inta == 0xffff) 961 goto done; 962 963 /*<1> beacon related */ 964 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) { 965 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 966 "beacon ok interrupt!\n"); 967 } 968 969 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) { 970 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 971 "beacon err interrupt!\n"); 972 } 973 974 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) { 975 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); 976 } 977 978 if (inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) { 979 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 980 "prepare beacon for interrupt!\n"); 981 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet); 982 } 983 984 /*<2> Tx related */ 985 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW])) 986 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); 987 988 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) { 989 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 990 "Manage ok interrupt!\n"); 991 _rtl_pci_tx_isr(hw, MGNT_QUEUE); 992 } 993 994 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) { 995 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 996 "HIGH_QUEUE ok interrupt!\n"); 997 _rtl_pci_tx_isr(hw, HIGH_QUEUE); 998 } 999 1000 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) { 1001 rtlpriv->link_info.num_tx_inperiod++; 1002 1003 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1004 "BK Tx OK interrupt!\n"); 1005 _rtl_pci_tx_isr(hw, BK_QUEUE); 1006 } 1007 1008 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) { 1009 rtlpriv->link_info.num_tx_inperiod++; 1010 1011 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1012 "BE TX OK interrupt!\n"); 1013 _rtl_pci_tx_isr(hw, BE_QUEUE); 1014 } 1015 1016 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) { 1017 rtlpriv->link_info.num_tx_inperiod++; 1018 1019 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1020 "VI TX OK interrupt!\n"); 1021 _rtl_pci_tx_isr(hw, VI_QUEUE); 1022 } 1023 1024 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) { 1025 rtlpriv->link_info.num_tx_inperiod++; 1026 1027 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1028 "Vo TX OK interrupt!\n"); 1029 _rtl_pci_tx_isr(hw, VO_QUEUE); 1030 } 1031 1032 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) { 1033 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) { 1034 rtlpriv->link_info.num_tx_inperiod++; 1035 1036 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1037 "CMD TX OK interrupt!\n"); 1038 _rtl_pci_tx_isr(hw, TXCMD_QUEUE); 1039 } 1040 } 1041 1042 /*<3> Rx related */ 1043 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) { 1044 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); 1045 _rtl_pci_rx_interrupt(hw); 1046 } 1047 1048 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) { 1049 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1050 "rx descriptor unavailable!\n"); 1051 _rtl_pci_rx_interrupt(hw); 1052 } 1053 1054 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) { 1055 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); 1056 _rtl_pci_rx_interrupt(hw); 1057 } 1058 1059 /*<4> fw related*/ 1060 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { 1061 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) { 1062 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1063 "firmware interrupt!\n"); 1064 queue_delayed_work(rtlpriv->works.rtl_wq, 1065 &rtlpriv->works.fwevt_wq, 0); 1066 } 1067 } 1068 1069 /*<5> hsisr related*/ 1070 /* Only 8188EE & 8723BE Supported. 1071 * If Other ICs Come in, System will corrupt, 1072 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR] 1073 * are not initialized 1074 */ 1075 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE || 1076 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) { 1077 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) { 1078 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1079 "hsisr interrupt!\n"); 1080 _rtl_pci_hs_interrupt(hw); 1081 } 1082 } 1083 1084 if (rtlpriv->rtlhal.earlymode_enable) 1085 tasklet_schedule(&rtlpriv->works.irq_tasklet); 1086 1087 done: 1088 rtlpriv->cfg->ops->enable_interrupt(hw); 1089 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1090 return ret; 1091 } 1092 1093 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw) 1094 { 1095 _rtl_pci_tx_chk_waitq(hw); 1096 } 1097 1098 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw) 1099 { 1100 struct rtl_priv *rtlpriv = rtl_priv(hw); 1101 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1102 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1103 struct rtl8192_tx_ring *ring = NULL; 1104 struct ieee80211_hdr *hdr = NULL; 1105 struct ieee80211_tx_info *info = NULL; 1106 struct sk_buff *pskb = NULL; 1107 struct rtl_tx_desc *pdesc = NULL; 1108 struct rtl_tcb_desc tcb_desc; 1109 /*This is for new trx flow*/ 1110 struct rtl_tx_buffer_desc *pbuffer_desc = NULL; 1111 u8 temp_one = 1; 1112 u8 *entry; 1113 1114 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 1115 ring = &rtlpci->tx_ring[BEACON_QUEUE]; 1116 pskb = __skb_dequeue(&ring->queue); 1117 if (rtlpriv->use_new_trx_flow) 1118 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1119 else 1120 entry = (u8 *)(&ring->desc[ring->idx]); 1121 if (pskb) { 1122 pci_unmap_single(rtlpci->pdev, 1123 rtlpriv->cfg->ops->get_desc( 1124 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR), 1125 pskb->len, PCI_DMA_TODEVICE); 1126 kfree_skb(pskb); 1127 } 1128 1129 /*NB: the beacon data buffer must be 32-bit aligned. */ 1130 pskb = ieee80211_beacon_get(hw, mac->vif); 1131 if (pskb == NULL) 1132 return; 1133 hdr = rtl_get_hdr(pskb); 1134 info = IEEE80211_SKB_CB(pskb); 1135 pdesc = &ring->desc[0]; 1136 if (rtlpriv->use_new_trx_flow) 1137 pbuffer_desc = &ring->buffer_desc[0]; 1138 1139 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1140 (u8 *)pbuffer_desc, info, NULL, pskb, 1141 BEACON_QUEUE, &tcb_desc); 1142 1143 __skb_queue_tail(&ring->queue, pskb); 1144 1145 if (rtlpriv->use_new_trx_flow) { 1146 temp_one = 4; 1147 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true, 1148 HW_DESC_OWN, (u8 *)&temp_one); 1149 } else { 1150 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN, 1151 &temp_one); 1152 } 1153 return; 1154 } 1155 1156 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw) 1157 { 1158 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1159 struct rtl_priv *rtlpriv = rtl_priv(hw); 1160 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1161 u8 i; 1162 u16 desc_num; 1163 1164 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) 1165 desc_num = TX_DESC_NUM_92E; 1166 else 1167 desc_num = RT_TXDESC_NUM; 1168 1169 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1170 rtlpci->txringcount[i] = desc_num; 1171 1172 /* 1173 *we just alloc 2 desc for beacon queue, 1174 *because we just need first desc in hw beacon. 1175 */ 1176 rtlpci->txringcount[BEACON_QUEUE] = 2; 1177 1178 /*BE queue need more descriptor for performance 1179 *consideration or, No more tx desc will happen, 1180 *and may cause mac80211 mem leakage. 1181 */ 1182 if (!rtl_priv(hw)->use_new_trx_flow) 1183 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE; 1184 1185 rtlpci->rxbuffersize = 9100; /*2048/1024; */ 1186 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */ 1187 } 1188 1189 static void _rtl_pci_init_struct(struct ieee80211_hw *hw, 1190 struct pci_dev *pdev) 1191 { 1192 struct rtl_priv *rtlpriv = rtl_priv(hw); 1193 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1194 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1195 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1196 1197 rtlpci->up_first_time = true; 1198 rtlpci->being_init_adapter = false; 1199 1200 rtlhal->hw = hw; 1201 rtlpci->pdev = pdev; 1202 1203 /*Tx/Rx related var */ 1204 _rtl_pci_init_trx_var(hw); 1205 1206 /*IBSS*/ 1207 mac->beacon_interval = 100; 1208 1209 /*AMPDU*/ 1210 mac->min_space_cfg = 0; 1211 mac->max_mss_density = 0; 1212 /*set sane AMPDU defaults */ 1213 mac->current_ampdu_density = 7; 1214 mac->current_ampdu_factor = 3; 1215 1216 /*Retry Limit*/ 1217 mac->retry_short = 7; 1218 mac->retry_long = 7; 1219 1220 /*QOS*/ 1221 rtlpci->acm_method = EACMWAY2_SW; 1222 1223 /*task */ 1224 tasklet_init(&rtlpriv->works.irq_tasklet, 1225 (void (*)(unsigned long))_rtl_pci_irq_tasklet, 1226 (unsigned long)hw); 1227 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet, 1228 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet, 1229 (unsigned long)hw); 1230 INIT_WORK(&rtlpriv->works.lps_change_work, 1231 rtl_lps_change_work_callback); 1232 } 1233 1234 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, 1235 unsigned int prio, unsigned int entries) 1236 { 1237 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1238 struct rtl_priv *rtlpriv = rtl_priv(hw); 1239 struct rtl_tx_buffer_desc *buffer_desc; 1240 struct rtl_tx_desc *desc; 1241 dma_addr_t buffer_desc_dma, desc_dma; 1242 u32 nextdescaddress; 1243 int i; 1244 1245 /* alloc tx buffer desc for new trx flow*/ 1246 if (rtlpriv->use_new_trx_flow) { 1247 buffer_desc = 1248 pci_zalloc_consistent(rtlpci->pdev, 1249 sizeof(*buffer_desc) * entries, 1250 &buffer_desc_dma); 1251 1252 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) { 1253 pr_err("Cannot allocate TX ring (prio = %d)\n", 1254 prio); 1255 return -ENOMEM; 1256 } 1257 1258 rtlpci->tx_ring[prio].buffer_desc = buffer_desc; 1259 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma; 1260 1261 rtlpci->tx_ring[prio].cur_tx_rp = 0; 1262 rtlpci->tx_ring[prio].cur_tx_wp = 0; 1263 rtlpci->tx_ring[prio].avl_desc = entries; 1264 } 1265 1266 /* alloc dma for this ring */ 1267 desc = pci_zalloc_consistent(rtlpci->pdev, 1268 sizeof(*desc) * entries, &desc_dma); 1269 1270 if (!desc || (unsigned long)desc & 0xFF) { 1271 pr_err("Cannot allocate TX ring (prio = %d)\n", prio); 1272 return -ENOMEM; 1273 } 1274 1275 rtlpci->tx_ring[prio].desc = desc; 1276 rtlpci->tx_ring[prio].dma = desc_dma; 1277 1278 rtlpci->tx_ring[prio].idx = 0; 1279 rtlpci->tx_ring[prio].entries = entries; 1280 skb_queue_head_init(&rtlpci->tx_ring[prio].queue); 1281 1282 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", 1283 prio, desc); 1284 1285 /* init every desc in this ring */ 1286 if (!rtlpriv->use_new_trx_flow) { 1287 for (i = 0; i < entries; i++) { 1288 nextdescaddress = (u32)desc_dma + 1289 ((i + 1) % entries) * 1290 sizeof(*desc); 1291 1292 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i], 1293 true, 1294 HW_DESC_TX_NEXTDESC_ADDR, 1295 (u8 *)&nextdescaddress); 1296 } 1297 } 1298 return 0; 1299 } 1300 1301 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1302 { 1303 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1304 struct rtl_priv *rtlpriv = rtl_priv(hw); 1305 int i; 1306 1307 if (rtlpriv->use_new_trx_flow) { 1308 struct rtl_rx_buffer_desc *entry = NULL; 1309 /* alloc dma for this ring */ 1310 rtlpci->rx_ring[rxring_idx].buffer_desc = 1311 pci_zalloc_consistent(rtlpci->pdev, 1312 sizeof(*rtlpci->rx_ring[rxring_idx]. 1313 buffer_desc) * 1314 rtlpci->rxringcount, 1315 &rtlpci->rx_ring[rxring_idx].dma); 1316 if (!rtlpci->rx_ring[rxring_idx].buffer_desc || 1317 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) { 1318 pr_err("Cannot allocate RX ring\n"); 1319 return -ENOMEM; 1320 } 1321 1322 /* init every desc in this ring */ 1323 rtlpci->rx_ring[rxring_idx].idx = 0; 1324 for (i = 0; i < rtlpci->rxringcount; i++) { 1325 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i]; 1326 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1327 rxring_idx, i)) 1328 return -ENOMEM; 1329 } 1330 } else { 1331 struct rtl_rx_desc *entry = NULL; 1332 u8 tmp_one = 1; 1333 /* alloc dma for this ring */ 1334 rtlpci->rx_ring[rxring_idx].desc = 1335 pci_zalloc_consistent(rtlpci->pdev, 1336 sizeof(*rtlpci->rx_ring[rxring_idx]. 1337 desc) * rtlpci->rxringcount, 1338 &rtlpci->rx_ring[rxring_idx].dma); 1339 if (!rtlpci->rx_ring[rxring_idx].desc || 1340 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) { 1341 pr_err("Cannot allocate RX ring\n"); 1342 return -ENOMEM; 1343 } 1344 1345 /* init every desc in this ring */ 1346 rtlpci->rx_ring[rxring_idx].idx = 0; 1347 1348 for (i = 0; i < rtlpci->rxringcount; i++) { 1349 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1350 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1351 rxring_idx, i)) 1352 return -ENOMEM; 1353 } 1354 1355 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1356 HW_DESC_RXERO, &tmp_one); 1357 } 1358 return 0; 1359 } 1360 1361 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw, 1362 unsigned int prio) 1363 { 1364 struct rtl_priv *rtlpriv = rtl_priv(hw); 1365 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1366 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 1367 1368 /* free every desc in this ring */ 1369 while (skb_queue_len(&ring->queue)) { 1370 u8 *entry; 1371 struct sk_buff *skb = __skb_dequeue(&ring->queue); 1372 1373 if (rtlpriv->use_new_trx_flow) 1374 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1375 else 1376 entry = (u8 *)(&ring->desc[ring->idx]); 1377 1378 pci_unmap_single(rtlpci->pdev, 1379 rtlpriv->cfg-> 1380 ops->get_desc((u8 *)entry, true, 1381 HW_DESC_TXBUFF_ADDR), 1382 skb->len, PCI_DMA_TODEVICE); 1383 kfree_skb(skb); 1384 ring->idx = (ring->idx + 1) % ring->entries; 1385 } 1386 1387 /* free dma of this ring */ 1388 pci_free_consistent(rtlpci->pdev, 1389 sizeof(*ring->desc) * ring->entries, 1390 ring->desc, ring->dma); 1391 ring->desc = NULL; 1392 if (rtlpriv->use_new_trx_flow) { 1393 pci_free_consistent(rtlpci->pdev, 1394 sizeof(*ring->buffer_desc) * ring->entries, 1395 ring->buffer_desc, ring->buffer_desc_dma); 1396 ring->buffer_desc = NULL; 1397 } 1398 } 1399 1400 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1401 { 1402 struct rtl_priv *rtlpriv = rtl_priv(hw); 1403 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1404 int i; 1405 1406 /* free every desc in this ring */ 1407 for (i = 0; i < rtlpci->rxringcount; i++) { 1408 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i]; 1409 1410 if (!skb) 1411 continue; 1412 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), 1413 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 1414 kfree_skb(skb); 1415 } 1416 1417 /* free dma of this ring */ 1418 if (rtlpriv->use_new_trx_flow) { 1419 pci_free_consistent(rtlpci->pdev, 1420 sizeof(*rtlpci->rx_ring[rxring_idx]. 1421 buffer_desc) * rtlpci->rxringcount, 1422 rtlpci->rx_ring[rxring_idx].buffer_desc, 1423 rtlpci->rx_ring[rxring_idx].dma); 1424 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL; 1425 } else { 1426 pci_free_consistent(rtlpci->pdev, 1427 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1428 rtlpci->rxringcount, 1429 rtlpci->rx_ring[rxring_idx].desc, 1430 rtlpci->rx_ring[rxring_idx].dma); 1431 rtlpci->rx_ring[rxring_idx].desc = NULL; 1432 } 1433 } 1434 1435 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw) 1436 { 1437 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1438 int ret; 1439 int i, rxring_idx; 1440 1441 /* rxring_idx 0:RX_MPDU_QUEUE 1442 * rxring_idx 1:RX_CMD_QUEUE 1443 */ 1444 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1445 ret = _rtl_pci_init_rx_ring(hw, rxring_idx); 1446 if (ret) 1447 return ret; 1448 } 1449 1450 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1451 ret = _rtl_pci_init_tx_ring(hw, i, 1452 rtlpci->txringcount[i]); 1453 if (ret) 1454 goto err_free_rings; 1455 } 1456 1457 return 0; 1458 1459 err_free_rings: 1460 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1461 _rtl_pci_free_rx_ring(hw, rxring_idx); 1462 1463 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1464 if (rtlpci->tx_ring[i].desc || 1465 rtlpci->tx_ring[i].buffer_desc) 1466 _rtl_pci_free_tx_ring(hw, i); 1467 1468 return 1; 1469 } 1470 1471 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw) 1472 { 1473 u32 i, rxring_idx; 1474 1475 /*free rx rings */ 1476 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1477 _rtl_pci_free_rx_ring(hw, rxring_idx); 1478 1479 /*free tx rings */ 1480 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1481 _rtl_pci_free_tx_ring(hw, i); 1482 1483 return 0; 1484 } 1485 1486 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw) 1487 { 1488 struct rtl_priv *rtlpriv = rtl_priv(hw); 1489 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1490 int i, rxring_idx; 1491 unsigned long flags; 1492 u8 tmp_one = 1; 1493 u32 bufferaddress; 1494 /* rxring_idx 0:RX_MPDU_QUEUE */ 1495 /* rxring_idx 1:RX_CMD_QUEUE */ 1496 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1497 /* force the rx_ring[RX_MPDU_QUEUE/ 1498 * RX_CMD_QUEUE].idx to the first one 1499 *new trx flow, do nothing 1500 */ 1501 if (!rtlpriv->use_new_trx_flow && 1502 rtlpci->rx_ring[rxring_idx].desc) { 1503 struct rtl_rx_desc *entry = NULL; 1504 1505 rtlpci->rx_ring[rxring_idx].idx = 0; 1506 for (i = 0; i < rtlpci->rxringcount; i++) { 1507 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1508 bufferaddress = 1509 rtlpriv->cfg->ops->get_desc((u8 *)entry, 1510 false , HW_DESC_RXBUFF_ADDR); 1511 memset((u8 *)entry , 0 , 1512 sizeof(*rtlpci->rx_ring 1513 [rxring_idx].desc));/*clear one entry*/ 1514 if (rtlpriv->use_new_trx_flow) { 1515 rtlpriv->cfg->ops->set_desc(hw, 1516 (u8 *)entry, false, 1517 HW_DESC_RX_PREPARE, 1518 (u8 *)&bufferaddress); 1519 } else { 1520 rtlpriv->cfg->ops->set_desc(hw, 1521 (u8 *)entry, false, 1522 HW_DESC_RXBUFF_ADDR, 1523 (u8 *)&bufferaddress); 1524 rtlpriv->cfg->ops->set_desc(hw, 1525 (u8 *)entry, false, 1526 HW_DESC_RXPKT_LEN, 1527 (u8 *)&rtlpci->rxbuffersize); 1528 rtlpriv->cfg->ops->set_desc(hw, 1529 (u8 *)entry, false, 1530 HW_DESC_RXOWN, 1531 (u8 *)&tmp_one); 1532 } 1533 } 1534 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1535 HW_DESC_RXERO, (u8 *)&tmp_one); 1536 } 1537 rtlpci->rx_ring[rxring_idx].idx = 0; 1538 } 1539 1540 /* 1541 *after reset, release previous pending packet, 1542 *and force the tx idx to the first one 1543 */ 1544 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1545 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1546 if (rtlpci->tx_ring[i].desc || 1547 rtlpci->tx_ring[i].buffer_desc) { 1548 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i]; 1549 1550 while (skb_queue_len(&ring->queue)) { 1551 u8 *entry; 1552 struct sk_buff *skb = 1553 __skb_dequeue(&ring->queue); 1554 if (rtlpriv->use_new_trx_flow) 1555 entry = (u8 *)(&ring->buffer_desc 1556 [ring->idx]); 1557 else 1558 entry = (u8 *)(&ring->desc[ring->idx]); 1559 1560 pci_unmap_single(rtlpci->pdev, 1561 rtlpriv->cfg->ops-> 1562 get_desc((u8 *) 1563 entry, 1564 true, 1565 HW_DESC_TXBUFF_ADDR), 1566 skb->len, PCI_DMA_TODEVICE); 1567 dev_kfree_skb_irq(skb); 1568 ring->idx = (ring->idx + 1) % ring->entries; 1569 } 1570 ring->idx = 0; 1571 } 1572 } 1573 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1574 1575 return 0; 1576 } 1577 1578 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw, 1579 struct ieee80211_sta *sta, 1580 struct sk_buff *skb) 1581 { 1582 struct rtl_priv *rtlpriv = rtl_priv(hw); 1583 struct rtl_sta_info *sta_entry = NULL; 1584 u8 tid = rtl_get_tid(skb); 1585 __le16 fc = rtl_get_fc(skb); 1586 1587 if (!sta) 1588 return false; 1589 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1590 1591 if (!rtlpriv->rtlhal.earlymode_enable) 1592 return false; 1593 if (ieee80211_is_nullfunc(fc)) 1594 return false; 1595 if (ieee80211_is_qos_nullfunc(fc)) 1596 return false; 1597 if (ieee80211_is_pspoll(fc)) 1598 return false; 1599 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL) 1600 return false; 1601 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE) 1602 return false; 1603 if (tid > 7) 1604 return false; 1605 1606 /* maybe every tid should be checked */ 1607 if (!rtlpriv->link_info.higher_busytxtraffic[tid]) 1608 return false; 1609 1610 spin_lock_bh(&rtlpriv->locks.waitq_lock); 1611 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb); 1612 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 1613 1614 return true; 1615 } 1616 1617 static int rtl_pci_tx(struct ieee80211_hw *hw, 1618 struct ieee80211_sta *sta, 1619 struct sk_buff *skb, 1620 struct rtl_tcb_desc *ptcb_desc) 1621 { 1622 struct rtl_priv *rtlpriv = rtl_priv(hw); 1623 struct rtl_sta_info *sta_entry = NULL; 1624 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1625 struct rtl8192_tx_ring *ring; 1626 struct rtl_tx_desc *pdesc; 1627 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL; 1628 u16 idx; 1629 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb); 1630 unsigned long flags; 1631 struct ieee80211_hdr *hdr = rtl_get_hdr(skb); 1632 __le16 fc = rtl_get_fc(skb); 1633 u8 *pda_addr = hdr->addr1; 1634 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1635 /*ssn */ 1636 u8 tid = 0; 1637 u16 seq_number = 0; 1638 u8 own; 1639 u8 temp_one = 1; 1640 1641 if (ieee80211_is_mgmt(fc)) 1642 rtl_tx_mgmt_proc(hw, skb); 1643 1644 if (rtlpriv->psc.sw_ps_enabled) { 1645 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) && 1646 !ieee80211_has_pm(fc)) 1647 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1648 } 1649 1650 rtl_action_proc(hw, skb, true); 1651 1652 if (is_multicast_ether_addr(pda_addr)) 1653 rtlpriv->stats.txbytesmulticast += skb->len; 1654 else if (is_broadcast_ether_addr(pda_addr)) 1655 rtlpriv->stats.txbytesbroadcast += skb->len; 1656 else 1657 rtlpriv->stats.txbytesunicast += skb->len; 1658 1659 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1660 ring = &rtlpci->tx_ring[hw_queue]; 1661 if (hw_queue != BEACON_QUEUE) { 1662 if (rtlpriv->use_new_trx_flow) 1663 idx = ring->cur_tx_wp; 1664 else 1665 idx = (ring->idx + skb_queue_len(&ring->queue)) % 1666 ring->entries; 1667 } else { 1668 idx = 0; 1669 } 1670 1671 pdesc = &ring->desc[idx]; 1672 if (rtlpriv->use_new_trx_flow) { 1673 ptx_bd_desc = &ring->buffer_desc[idx]; 1674 } else { 1675 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *)pdesc, 1676 true, HW_DESC_OWN); 1677 1678 if ((own == 1) && (hw_queue != BEACON_QUEUE)) { 1679 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1680 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1681 hw_queue, ring->idx, idx, 1682 skb_queue_len(&ring->queue)); 1683 1684 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, 1685 flags); 1686 return skb->len; 1687 } 1688 } 1689 1690 if (rtlpriv->cfg->ops->get_available_desc && 1691 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) { 1692 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1693 "get_available_desc fail\n"); 1694 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, 1695 flags); 1696 return skb->len; 1697 } 1698 1699 if (ieee80211_is_data_qos(fc)) { 1700 tid = rtl_get_tid(skb); 1701 if (sta) { 1702 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1703 seq_number = (le16_to_cpu(hdr->seq_ctrl) & 1704 IEEE80211_SCTL_SEQ) >> 4; 1705 seq_number += 1; 1706 1707 if (!ieee80211_has_morefrags(hdr->frame_control)) 1708 sta_entry->tids[tid].seq_number = seq_number; 1709 } 1710 } 1711 1712 if (ieee80211_is_data(fc)) 1713 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX); 1714 1715 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1716 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc); 1717 1718 __skb_queue_tail(&ring->queue, skb); 1719 1720 if (rtlpriv->use_new_trx_flow) { 1721 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1722 HW_DESC_OWN, &hw_queue); 1723 } else { 1724 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1725 HW_DESC_OWN, &temp_one); 1726 } 1727 1728 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 && 1729 hw_queue != BEACON_QUEUE) { 1730 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 1731 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1732 hw_queue, ring->idx, idx, 1733 skb_queue_len(&ring->queue)); 1734 1735 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 1736 } 1737 1738 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1739 1740 rtlpriv->cfg->ops->tx_polling(hw, hw_queue); 1741 1742 return 0; 1743 } 1744 1745 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1746 { 1747 struct rtl_priv *rtlpriv = rtl_priv(hw); 1748 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1749 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1750 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1751 u16 i = 0; 1752 int queue_id; 1753 struct rtl8192_tx_ring *ring; 1754 1755 if (mac->skip_scan) 1756 return; 1757 1758 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) { 1759 u32 queue_len; 1760 1761 if (((queues >> queue_id) & 0x1) == 0) { 1762 queue_id--; 1763 continue; 1764 } 1765 ring = &pcipriv->dev.tx_ring[queue_id]; 1766 queue_len = skb_queue_len(&ring->queue); 1767 if (queue_len == 0 || queue_id == BEACON_QUEUE || 1768 queue_id == TXCMD_QUEUE) { 1769 queue_id--; 1770 continue; 1771 } else { 1772 msleep(20); 1773 i++; 1774 } 1775 1776 /* we just wait 1s for all queues */ 1777 if (rtlpriv->psc.rfpwr_state == ERFOFF || 1778 is_hal_stop(rtlhal) || i >= 200) 1779 return; 1780 } 1781 } 1782 1783 static void rtl_pci_deinit(struct ieee80211_hw *hw) 1784 { 1785 struct rtl_priv *rtlpriv = rtl_priv(hw); 1786 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1787 1788 _rtl_pci_deinit_trx_ring(hw); 1789 1790 synchronize_irq(rtlpci->pdev->irq); 1791 tasklet_kill(&rtlpriv->works.irq_tasklet); 1792 cancel_work_sync(&rtlpriv->works.lps_change_work); 1793 1794 flush_workqueue(rtlpriv->works.rtl_wq); 1795 destroy_workqueue(rtlpriv->works.rtl_wq); 1796 1797 } 1798 1799 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev) 1800 { 1801 int err; 1802 1803 _rtl_pci_init_struct(hw, pdev); 1804 1805 err = _rtl_pci_init_trx_ring(hw); 1806 if (err) { 1807 pr_err("tx ring initialization failed\n"); 1808 return err; 1809 } 1810 1811 return 0; 1812 } 1813 1814 static int rtl_pci_start(struct ieee80211_hw *hw) 1815 { 1816 struct rtl_priv *rtlpriv = rtl_priv(hw); 1817 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1818 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1819 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1820 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw)); 1821 1822 int err; 1823 1824 rtl_pci_reset_trx_ring(hw); 1825 1826 rtlpci->driver_is_goingto_unload = false; 1827 if (rtlpriv->cfg->ops->get_btc_status && 1828 rtlpriv->cfg->ops->get_btc_status()) { 1829 rtlpriv->btcoexist.btc_ops->btc_init_variables(rtlpriv); 1830 rtlpriv->btcoexist.btc_ops->btc_init_hal_vars(rtlpriv); 1831 } 1832 err = rtlpriv->cfg->ops->hw_init(hw); 1833 if (err) { 1834 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1835 "Failed to config hardware!\n"); 1836 return err; 1837 } 1838 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, 1839 &rtlmac->retry_long); 1840 1841 rtlpriv->cfg->ops->enable_interrupt(hw); 1842 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); 1843 1844 rtl_init_rx_config(hw); 1845 1846 /*should be after adapter start and interrupt enable. */ 1847 set_hal_start(rtlhal); 1848 1849 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1850 1851 rtlpci->up_first_time = false; 1852 1853 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "rtl_pci_start OK\n"); 1854 return 0; 1855 } 1856 1857 static void rtl_pci_stop(struct ieee80211_hw *hw) 1858 { 1859 struct rtl_priv *rtlpriv = rtl_priv(hw); 1860 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1861 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1862 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1863 unsigned long flags; 1864 u8 RFInProgressTimeOut = 0; 1865 1866 if (rtlpriv->cfg->ops->get_btc_status()) 1867 rtlpriv->btcoexist.btc_ops->btc_halt_notify(); 1868 1869 /* 1870 *should be before disable interrupt&adapter 1871 *and will do it immediately. 1872 */ 1873 set_hal_stop(rtlhal); 1874 1875 rtlpci->driver_is_goingto_unload = true; 1876 rtlpriv->cfg->ops->disable_interrupt(hw); 1877 cancel_work_sync(&rtlpriv->works.lps_change_work); 1878 1879 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1880 while (ppsc->rfchange_inprogress) { 1881 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1882 if (RFInProgressTimeOut > 100) { 1883 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1884 break; 1885 } 1886 mdelay(1); 1887 RFInProgressTimeOut++; 1888 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1889 } 1890 ppsc->rfchange_inprogress = true; 1891 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1892 1893 rtlpriv->cfg->ops->hw_disable(hw); 1894 /* some things are not needed if firmware not available */ 1895 if (!rtlpriv->max_fw_size) 1896 return; 1897 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1898 1899 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1900 ppsc->rfchange_inprogress = false; 1901 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1902 1903 rtl_pci_enable_aspm(hw); 1904 } 1905 1906 static bool _rtl_pci_find_adapter(struct pci_dev *pdev, 1907 struct ieee80211_hw *hw) 1908 { 1909 struct rtl_priv *rtlpriv = rtl_priv(hw); 1910 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1911 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1912 struct pci_dev *bridge_pdev = pdev->bus->self; 1913 u16 venderid; 1914 u16 deviceid; 1915 u8 revisionid; 1916 u16 irqline; 1917 u8 tmp; 1918 1919 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1920 venderid = pdev->vendor; 1921 deviceid = pdev->device; 1922 pci_read_config_byte(pdev, 0x8, &revisionid); 1923 pci_read_config_word(pdev, 0x3C, &irqline); 1924 1925 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses 1926 * r8192e_pci, and RTL8192SE, which uses this driver. If the 1927 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then 1928 * the correct driver is r8192e_pci, thus this routine should 1929 * return false. 1930 */ 1931 if (deviceid == RTL_PCI_8192SE_DID && 1932 revisionid == RTL_PCI_REVISION_ID_8192PCIE) 1933 return false; 1934 1935 if (deviceid == RTL_PCI_8192_DID || 1936 deviceid == RTL_PCI_0044_DID || 1937 deviceid == RTL_PCI_0047_DID || 1938 deviceid == RTL_PCI_8192SE_DID || 1939 deviceid == RTL_PCI_8174_DID || 1940 deviceid == RTL_PCI_8173_DID || 1941 deviceid == RTL_PCI_8172_DID || 1942 deviceid == RTL_PCI_8171_DID) { 1943 switch (revisionid) { 1944 case RTL_PCI_REVISION_ID_8192PCIE: 1945 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1946 "8192 PCI-E is found - vid/did=%x/%x\n", 1947 venderid, deviceid); 1948 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E; 1949 return false; 1950 case RTL_PCI_REVISION_ID_8192SE: 1951 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1952 "8192SE is found - vid/did=%x/%x\n", 1953 venderid, deviceid); 1954 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1955 break; 1956 default: 1957 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1958 "Err: Unknown device - vid/did=%x/%x\n", 1959 venderid, deviceid); 1960 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1961 break; 1962 1963 } 1964 } else if (deviceid == RTL_PCI_8723AE_DID) { 1965 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE; 1966 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1967 "8723AE PCI-E is found - " 1968 "vid/did=%x/%x\n", venderid, deviceid); 1969 } else if (deviceid == RTL_PCI_8192CET_DID || 1970 deviceid == RTL_PCI_8192CE_DID || 1971 deviceid == RTL_PCI_8191CE_DID || 1972 deviceid == RTL_PCI_8188CE_DID) { 1973 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE; 1974 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1975 "8192C PCI-E is found - vid/did=%x/%x\n", 1976 venderid, deviceid); 1977 } else if (deviceid == RTL_PCI_8192DE_DID || 1978 deviceid == RTL_PCI_8192DE_DID2) { 1979 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE; 1980 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1981 "8192D PCI-E is found - vid/did=%x/%x\n", 1982 venderid, deviceid); 1983 } else if (deviceid == RTL_PCI_8188EE_DID) { 1984 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE; 1985 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1986 "Find adapter, Hardware type is 8188EE\n"); 1987 } else if (deviceid == RTL_PCI_8723BE_DID) { 1988 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE; 1989 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, 1990 "Find adapter, Hardware type is 8723BE\n"); 1991 } else if (deviceid == RTL_PCI_8192EE_DID) { 1992 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE; 1993 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, 1994 "Find adapter, Hardware type is 8192EE\n"); 1995 } else if (deviceid == RTL_PCI_8821AE_DID) { 1996 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE; 1997 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, 1998 "Find adapter, Hardware type is 8821AE\n"); 1999 } else if (deviceid == RTL_PCI_8812AE_DID) { 2000 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE; 2001 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, 2002 "Find adapter, Hardware type is 8812AE\n"); 2003 } else { 2004 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2005 "Err: Unknown device - vid/did=%x/%x\n", 2006 venderid, deviceid); 2007 2008 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE; 2009 } 2010 2011 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) { 2012 if (revisionid == 0 || revisionid == 1) { 2013 if (revisionid == 0) { 2014 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2015 "Find 92DE MAC0\n"); 2016 rtlhal->interfaceindex = 0; 2017 } else if (revisionid == 1) { 2018 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2019 "Find 92DE MAC1\n"); 2020 rtlhal->interfaceindex = 1; 2021 } 2022 } else { 2023 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2024 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", 2025 venderid, deviceid, revisionid); 2026 rtlhal->interfaceindex = 0; 2027 } 2028 } 2029 2030 /* 92ee use new trx flow */ 2031 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) 2032 rtlpriv->use_new_trx_flow = true; 2033 else 2034 rtlpriv->use_new_trx_flow = false; 2035 2036 /*find bus info */ 2037 pcipriv->ndis_adapter.busnumber = pdev->bus->number; 2038 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn); 2039 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn); 2040 2041 /*find bridge info */ 2042 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 2043 /* some ARM have no bridge_pdev and will crash here 2044 * so we should check if bridge_pdev is NULL 2045 */ 2046 if (bridge_pdev) { 2047 /*find bridge info if available */ 2048 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor; 2049 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { 2050 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { 2051 pcipriv->ndis_adapter.pcibridge_vendor = tmp; 2052 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2053 "Pci Bridge Vendor is found index: %d\n", 2054 tmp); 2055 break; 2056 } 2057 } 2058 } 2059 2060 if (pcipriv->ndis_adapter.pcibridge_vendor != 2061 PCI_BRIDGE_VENDOR_UNKNOWN) { 2062 pcipriv->ndis_adapter.pcibridge_busnum = 2063 bridge_pdev->bus->number; 2064 pcipriv->ndis_adapter.pcibridge_devnum = 2065 PCI_SLOT(bridge_pdev->devfn); 2066 pcipriv->ndis_adapter.pcibridge_funcnum = 2067 PCI_FUNC(bridge_pdev->devfn); 2068 pcipriv->ndis_adapter.pcibridge_pciehdr_offset = 2069 pci_pcie_cap(bridge_pdev); 2070 pcipriv->ndis_adapter.num4bytes = 2071 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4; 2072 2073 rtl_pci_get_linkcontrol_field(hw); 2074 2075 if (pcipriv->ndis_adapter.pcibridge_vendor == 2076 PCI_BRIDGE_VENDOR_AMD) { 2077 pcipriv->ndis_adapter.amd_l1_patch = 2078 rtl_pci_get_amd_l1_patch(hw); 2079 } 2080 } 2081 2082 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2083 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", 2084 pcipriv->ndis_adapter.busnumber, 2085 pcipriv->ndis_adapter.devnumber, 2086 pcipriv->ndis_adapter.funcnumber, 2087 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); 2088 2089 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2090 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n", 2091 pcipriv->ndis_adapter.pcibridge_busnum, 2092 pcipriv->ndis_adapter.pcibridge_devnum, 2093 pcipriv->ndis_adapter.pcibridge_funcnum, 2094 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], 2095 pcipriv->ndis_adapter.pcibridge_pciehdr_offset, 2096 pcipriv->ndis_adapter.pcibridge_linkctrlreg, 2097 pcipriv->ndis_adapter.amd_l1_patch); 2098 2099 rtl_pci_parse_configuration(pdev, hw); 2100 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list); 2101 2102 return true; 2103 } 2104 2105 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw) 2106 { 2107 struct rtl_priv *rtlpriv = rtl_priv(hw); 2108 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2109 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2110 int ret; 2111 2112 ret = pci_enable_msi(rtlpci->pdev); 2113 if (ret < 0) 2114 return ret; 2115 2116 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2117 IRQF_SHARED, KBUILD_MODNAME, hw); 2118 if (ret < 0) { 2119 pci_disable_msi(rtlpci->pdev); 2120 return ret; 2121 } 2122 2123 rtlpci->using_msi = true; 2124 2125 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG, 2126 "MSI Interrupt Mode!\n"); 2127 return 0; 2128 } 2129 2130 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw) 2131 { 2132 struct rtl_priv *rtlpriv = rtl_priv(hw); 2133 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2134 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2135 int ret; 2136 2137 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2138 IRQF_SHARED, KBUILD_MODNAME, hw); 2139 if (ret < 0) 2140 return ret; 2141 2142 rtlpci->using_msi = false; 2143 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG, 2144 "Pin-based Interrupt Mode!\n"); 2145 return 0; 2146 } 2147 2148 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw) 2149 { 2150 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2151 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2152 int ret; 2153 2154 if (rtlpci->msi_support) { 2155 ret = rtl_pci_intr_mode_msi(hw); 2156 if (ret < 0) 2157 ret = rtl_pci_intr_mode_legacy(hw); 2158 } else { 2159 ret = rtl_pci_intr_mode_legacy(hw); 2160 } 2161 return ret; 2162 } 2163 2164 int rtl_pci_probe(struct pci_dev *pdev, 2165 const struct pci_device_id *id) 2166 { 2167 struct ieee80211_hw *hw = NULL; 2168 2169 struct rtl_priv *rtlpriv = NULL; 2170 struct rtl_pci_priv *pcipriv = NULL; 2171 struct rtl_pci *rtlpci; 2172 unsigned long pmem_start, pmem_len, pmem_flags; 2173 int err; 2174 2175 err = pci_enable_device(pdev); 2176 if (err) { 2177 WARN_ONCE(true, "%s : Cannot enable new PCI device\n", 2178 pci_name(pdev)); 2179 return err; 2180 } 2181 2182 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 2183 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 2184 WARN_ONCE(true, 2185 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n"); 2186 err = -ENOMEM; 2187 goto fail1; 2188 } 2189 } 2190 2191 pci_set_master(pdev); 2192 2193 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) + 2194 sizeof(struct rtl_priv), &rtl_ops); 2195 if (!hw) { 2196 WARN_ONCE(true, 2197 "%s : ieee80211 alloc failed\n", pci_name(pdev)); 2198 err = -ENOMEM; 2199 goto fail1; 2200 } 2201 2202 SET_IEEE80211_DEV(hw, &pdev->dev); 2203 pci_set_drvdata(pdev, hw); 2204 2205 rtlpriv = hw->priv; 2206 rtlpriv->hw = hw; 2207 pcipriv = (void *)rtlpriv->priv; 2208 pcipriv->dev.pdev = pdev; 2209 init_completion(&rtlpriv->firmware_loading_complete); 2210 /*proximity init here*/ 2211 rtlpriv->proximity.proxim_on = false; 2212 2213 pcipriv = (void *)rtlpriv->priv; 2214 pcipriv->dev.pdev = pdev; 2215 2216 /* init cfg & intf_ops */ 2217 rtlpriv->rtlhal.interface = INTF_PCI; 2218 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data); 2219 rtlpriv->intf_ops = &rtl_pci_ops; 2220 rtlpriv->glb_var = &rtl_global_var; 2221 2222 /* MEM map */ 2223 err = pci_request_regions(pdev, KBUILD_MODNAME); 2224 if (err) { 2225 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n"); 2226 goto fail1; 2227 } 2228 2229 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id); 2230 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id); 2231 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id); 2232 2233 /*shared mem start */ 2234 rtlpriv->io.pci_mem_start = 2235 (unsigned long)pci_iomap(pdev, 2236 rtlpriv->cfg->bar_id, pmem_len); 2237 if (rtlpriv->io.pci_mem_start == 0) { 2238 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n"); 2239 err = -ENOMEM; 2240 goto fail2; 2241 } 2242 2243 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2244 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", 2245 pmem_start, pmem_len, pmem_flags, 2246 rtlpriv->io.pci_mem_start); 2247 2248 /* Disable Clk Request */ 2249 pci_write_config_byte(pdev, 0x81, 0); 2250 /* leave D3 mode */ 2251 pci_write_config_byte(pdev, 0x44, 0); 2252 pci_write_config_byte(pdev, 0x04, 0x06); 2253 pci_write_config_byte(pdev, 0x04, 0x07); 2254 2255 /* find adapter */ 2256 if (!_rtl_pci_find_adapter(pdev, hw)) { 2257 err = -ENODEV; 2258 goto fail3; 2259 } 2260 2261 /* Init IO handler */ 2262 _rtl_pci_io_handler_init(&pdev->dev, hw); 2263 2264 /*like read eeprom and so on */ 2265 rtlpriv->cfg->ops->read_eeprom_info(hw); 2266 2267 if (rtlpriv->cfg->ops->init_sw_vars(hw)) { 2268 pr_err("Can't init_sw_vars\n"); 2269 err = -ENODEV; 2270 goto fail3; 2271 } 2272 rtlpriv->cfg->ops->init_sw_leds(hw); 2273 2274 /*aspm */ 2275 rtl_pci_init_aspm(hw); 2276 2277 /* Init mac80211 sw */ 2278 err = rtl_init_core(hw); 2279 if (err) { 2280 pr_err("Can't allocate sw for mac80211\n"); 2281 goto fail3; 2282 } 2283 2284 /* Init PCI sw */ 2285 err = rtl_pci_init(hw, pdev); 2286 if (err) { 2287 pr_err("Failed to init PCI\n"); 2288 goto fail3; 2289 } 2290 2291 err = ieee80211_register_hw(hw); 2292 if (err) { 2293 pr_err("Can't register mac80211 hw.\n"); 2294 err = -ENODEV; 2295 goto fail3; 2296 } 2297 rtlpriv->mac80211.mac80211_registered = 1; 2298 2299 /*init rfkill */ 2300 rtl_init_rfkill(hw); /* Init PCI sw */ 2301 2302 rtlpci = rtl_pcidev(pcipriv); 2303 err = rtl_pci_intr_mode_decide(hw); 2304 if (err) { 2305 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2306 "%s: failed to register IRQ handler\n", 2307 wiphy_name(hw->wiphy)); 2308 goto fail3; 2309 } 2310 rtlpci->irq_alloc = 1; 2311 2312 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2313 return 0; 2314 2315 fail3: 2316 pci_set_drvdata(pdev, NULL); 2317 rtl_deinit_core(hw); 2318 2319 if (rtlpriv->io.pci_mem_start != 0) 2320 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2321 2322 fail2: 2323 pci_release_regions(pdev); 2324 complete(&rtlpriv->firmware_loading_complete); 2325 2326 fail1: 2327 if (hw) 2328 ieee80211_free_hw(hw); 2329 pci_disable_device(pdev); 2330 2331 return err; 2332 2333 } 2334 EXPORT_SYMBOL(rtl_pci_probe); 2335 2336 void rtl_pci_disconnect(struct pci_dev *pdev) 2337 { 2338 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2339 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2340 struct rtl_priv *rtlpriv = rtl_priv(hw); 2341 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2342 struct rtl_mac *rtlmac = rtl_mac(rtlpriv); 2343 2344 /* just in case driver is removed before firmware callback */ 2345 wait_for_completion(&rtlpriv->firmware_loading_complete); 2346 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2347 2348 /*ieee80211_unregister_hw will call ops_stop */ 2349 if (rtlmac->mac80211_registered == 1) { 2350 ieee80211_unregister_hw(hw); 2351 rtlmac->mac80211_registered = 0; 2352 } else { 2353 rtl_deinit_deferred_work(hw); 2354 rtlpriv->intf_ops->adapter_stop(hw); 2355 } 2356 rtlpriv->cfg->ops->disable_interrupt(hw); 2357 2358 /*deinit rfkill */ 2359 rtl_deinit_rfkill(hw); 2360 2361 rtl_pci_deinit(hw); 2362 rtl_deinit_core(hw); 2363 rtlpriv->cfg->ops->deinit_sw_vars(hw); 2364 2365 if (rtlpci->irq_alloc) { 2366 free_irq(rtlpci->pdev->irq, hw); 2367 rtlpci->irq_alloc = 0; 2368 } 2369 2370 if (rtlpci->using_msi) 2371 pci_disable_msi(rtlpci->pdev); 2372 2373 list_del(&rtlpriv->list); 2374 if (rtlpriv->io.pci_mem_start != 0) { 2375 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2376 pci_release_regions(pdev); 2377 } 2378 2379 pci_disable_device(pdev); 2380 2381 rtl_pci_disable_aspm(hw); 2382 2383 pci_set_drvdata(pdev, NULL); 2384 2385 ieee80211_free_hw(hw); 2386 } 2387 EXPORT_SYMBOL(rtl_pci_disconnect); 2388 2389 #ifdef CONFIG_PM_SLEEP 2390 /*************************************** 2391 kernel pci power state define: 2392 PCI_D0 ((pci_power_t __force) 0) 2393 PCI_D1 ((pci_power_t __force) 1) 2394 PCI_D2 ((pci_power_t __force) 2) 2395 PCI_D3hot ((pci_power_t __force) 3) 2396 PCI_D3cold ((pci_power_t __force) 4) 2397 PCI_UNKNOWN ((pci_power_t __force) 5) 2398 2399 This function is called when system 2400 goes into suspend state mac80211 will 2401 call rtl_mac_stop() from the mac80211 2402 suspend function first, So there is 2403 no need to call hw_disable here. 2404 ****************************************/ 2405 int rtl_pci_suspend(struct device *dev) 2406 { 2407 struct pci_dev *pdev = to_pci_dev(dev); 2408 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2409 struct rtl_priv *rtlpriv = rtl_priv(hw); 2410 2411 rtlpriv->cfg->ops->hw_suspend(hw); 2412 rtl_deinit_rfkill(hw); 2413 2414 return 0; 2415 } 2416 EXPORT_SYMBOL(rtl_pci_suspend); 2417 2418 int rtl_pci_resume(struct device *dev) 2419 { 2420 struct pci_dev *pdev = to_pci_dev(dev); 2421 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2422 struct rtl_priv *rtlpriv = rtl_priv(hw); 2423 2424 rtlpriv->cfg->ops->hw_resume(hw); 2425 rtl_init_rfkill(hw); 2426 return 0; 2427 } 2428 EXPORT_SYMBOL(rtl_pci_resume); 2429 #endif /* CONFIG_PM_SLEEP */ 2430 2431 const struct rtl_intf_ops rtl_pci_ops = { 2432 .read_efuse_byte = read_efuse_byte, 2433 .adapter_start = rtl_pci_start, 2434 .adapter_stop = rtl_pci_stop, 2435 .check_buddy_priv = rtl_pci_check_buddy_priv, 2436 .adapter_tx = rtl_pci_tx, 2437 .flush = rtl_pci_flush, 2438 .reset_trx_ring = rtl_pci_reset_trx_ring, 2439 .waitq_insert = rtl_pci_tx_chk_waitq_insert, 2440 2441 .disable_aspm = rtl_pci_disable_aspm, 2442 .enable_aspm = rtl_pci_enable_aspm, 2443 }; 2444