1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "wifi.h" 27 #include "core.h" 28 #include "pci.h" 29 #include "base.h" 30 #include "ps.h" 31 #include "efuse.h" 32 #include <linux/interrupt.h> 33 #include <linux/export.h> 34 #include <linux/kmemleak.h> 35 #include <linux/module.h> 36 37 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 38 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 39 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>"); 40 MODULE_LICENSE("GPL"); 41 MODULE_DESCRIPTION("PCI basic driver for rtlwifi"); 42 43 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { 44 INTEL_VENDOR_ID, 45 ATI_VENDOR_ID, 46 AMD_VENDOR_ID, 47 SIS_VENDOR_ID 48 }; 49 50 static const u8 ac_to_hwq[] = { 51 VO_QUEUE, 52 VI_QUEUE, 53 BE_QUEUE, 54 BK_QUEUE 55 }; 56 57 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, 58 struct sk_buff *skb) 59 { 60 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 61 __le16 fc = rtl_get_fc(skb); 62 u8 queue_index = skb_get_queue_mapping(skb); 63 64 if (unlikely(ieee80211_is_beacon(fc))) 65 return BEACON_QUEUE; 66 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) 67 return MGNT_QUEUE; 68 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 69 if (ieee80211_is_nullfunc(fc)) 70 return HIGH_QUEUE; 71 72 return ac_to_hwq[queue_index]; 73 } 74 75 /* Update PCI dependent default settings*/ 76 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) 77 { 78 struct rtl_priv *rtlpriv = rtl_priv(hw); 79 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 80 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 81 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 82 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 83 u8 init_aspm; 84 85 ppsc->reg_rfps_level = 0; 86 ppsc->support_aspm = false; 87 88 /*Update PCI ASPM setting */ 89 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm; 90 switch (rtlpci->const_pci_aspm) { 91 case 0: 92 /*No ASPM */ 93 break; 94 95 case 1: 96 /*ASPM dynamically enabled/disable. */ 97 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; 98 break; 99 100 case 2: 101 /*ASPM with Clock Req dynamically enabled/disable. */ 102 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | 103 RT_RF_OFF_LEVL_CLK_REQ); 104 break; 105 106 case 3: 107 /* 108 * Always enable ASPM and Clock Req 109 * from initialization to halt. 110 * */ 111 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); 112 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | 113 RT_RF_OFF_LEVL_CLK_REQ); 114 break; 115 116 case 4: 117 /* 118 * Always enable ASPM without Clock Req 119 * from initialization to halt. 120 * */ 121 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | 122 RT_RF_OFF_LEVL_CLK_REQ); 123 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; 124 break; 125 } 126 127 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 128 129 /*Update Radio OFF setting */ 130 switch (rtlpci->const_hwsw_rfoff_d3) { 131 case 1: 132 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 133 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 134 break; 135 136 case 2: 137 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 138 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 139 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 140 break; 141 142 case 3: 143 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; 144 break; 145 } 146 147 /*Set HW definition to determine if it supports ASPM. */ 148 switch (rtlpci->const_support_pciaspm) { 149 case 0:{ 150 /*Not support ASPM. */ 151 bool support_aspm = false; 152 ppsc->support_aspm = support_aspm; 153 break; 154 } 155 case 1:{ 156 /*Support ASPM. */ 157 bool support_aspm = true; 158 bool support_backdoor = true; 159 ppsc->support_aspm = support_aspm; 160 161 /*if (priv->oem_id == RT_CID_TOSHIBA && 162 !priv->ndis_adapter.amd_l1_patch) 163 support_backdoor = false; */ 164 165 ppsc->support_backdoor = support_backdoor; 166 167 break; 168 } 169 case 2: 170 /*ASPM value set by chipset. */ 171 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) { 172 bool support_aspm = true; 173 ppsc->support_aspm = support_aspm; 174 } 175 break; 176 default: 177 pr_err("switch case %#x not processed\n", 178 rtlpci->const_support_pciaspm); 179 break; 180 } 181 182 /* toshiba aspm issue, toshiba will set aspm selfly 183 * so we should not set aspm in driver */ 184 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm); 185 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE && 186 init_aspm == 0x43) 187 ppsc->support_aspm = false; 188 } 189 190 static bool _rtl_pci_platform_switch_device_pci_aspm( 191 struct ieee80211_hw *hw, 192 u8 value) 193 { 194 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 195 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 196 197 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE) 198 value |= 0x40; 199 200 pci_write_config_byte(rtlpci->pdev, 0x80, value); 201 202 return false; 203 } 204 205 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/ 206 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value) 207 { 208 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 209 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 210 211 pci_write_config_byte(rtlpci->pdev, 0x81, value); 212 213 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 214 udelay(100); 215 } 216 217 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ 218 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) 219 { 220 struct rtl_priv *rtlpriv = rtl_priv(hw); 221 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 222 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 223 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 224 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 225 u8 num4bytes = pcipriv->ndis_adapter.num4bytes; 226 /*Retrieve original configuration settings. */ 227 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg; 228 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter. 229 pcibridge_linkctrlreg; 230 u16 aspmlevel = 0; 231 u8 tmp_u1b = 0; 232 233 if (!ppsc->support_aspm) 234 return; 235 236 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 237 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 238 "PCI(Bridge) UNKNOWN\n"); 239 240 return; 241 } 242 243 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 244 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 245 _rtl_pci_switch_clk_req(hw, 0x0); 246 } 247 248 /*for promising device will in L0 state after an I/O. */ 249 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b); 250 251 /*Set corresponding value. */ 252 aspmlevel |= BIT(0) | BIT(1); 253 linkctrl_reg &= ~aspmlevel; 254 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1)); 255 256 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg); 257 udelay(50); 258 259 /*4 Disable Pci Bridge ASPM */ 260 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), 261 pcibridge_linkctrlreg); 262 263 udelay(50); 264 } 265 266 /* 267 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for 268 *power saving We should follow the sequence to enable 269 *RTL8192SE first then enable Pci Bridge ASPM 270 *or the system will show bluescreen. 271 */ 272 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) 273 { 274 struct rtl_priv *rtlpriv = rtl_priv(hw); 275 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 276 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 277 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 278 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 279 u8 num4bytes = pcipriv->ndis_adapter.num4bytes; 280 u16 aspmlevel; 281 u8 u_pcibridge_aspmsetting; 282 u8 u_device_aspmsetting; 283 284 if (!ppsc->support_aspm) 285 return; 286 287 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 288 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 289 "PCI(Bridge) UNKNOWN\n"); 290 return; 291 } 292 293 /*4 Enable Pci Bridge ASPM */ 294 295 u_pcibridge_aspmsetting = 296 pcipriv->ndis_adapter.pcibridge_linkctrlreg | 297 rtlpci->const_hostpci_aspm_setting; 298 299 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) 300 u_pcibridge_aspmsetting &= ~BIT(0); 301 302 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), 303 u_pcibridge_aspmsetting); 304 305 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 306 "PlatformEnableASPM(): Write reg[%x] = %x\n", 307 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10), 308 u_pcibridge_aspmsetting); 309 310 udelay(50); 311 312 /*Get ASPM level (with/without Clock Req) */ 313 aspmlevel = rtlpci->const_devicepci_aspm_setting; 314 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg; 315 316 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/ 317 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */ 318 319 u_device_aspmsetting |= aspmlevel; 320 321 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting); 322 323 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 324 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level & 325 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0); 326 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 327 } 328 udelay(100); 329 } 330 331 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw) 332 { 333 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 334 335 bool status = false; 336 u8 offset_e0; 337 unsigned offset_e4; 338 339 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0); 340 341 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0); 342 343 if (offset_e0 == 0xA0) { 344 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4); 345 if (offset_e4 & BIT(23)) 346 status = true; 347 } 348 349 return status; 350 } 351 352 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw, 353 struct rtl_priv **buddy_priv) 354 { 355 struct rtl_priv *rtlpriv = rtl_priv(hw); 356 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 357 bool find_buddy_priv = false; 358 struct rtl_priv *tpriv; 359 struct rtl_pci_priv *tpcipriv = NULL; 360 361 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) { 362 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list, 363 list) { 364 tpcipriv = (struct rtl_pci_priv *)tpriv->priv; 365 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 366 "pcipriv->ndis_adapter.funcnumber %x\n", 367 pcipriv->ndis_adapter.funcnumber); 368 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 369 "tpcipriv->ndis_adapter.funcnumber %x\n", 370 tpcipriv->ndis_adapter.funcnumber); 371 372 if ((pcipriv->ndis_adapter.busnumber == 373 tpcipriv->ndis_adapter.busnumber) && 374 (pcipriv->ndis_adapter.devnumber == 375 tpcipriv->ndis_adapter.devnumber) && 376 (pcipriv->ndis_adapter.funcnumber != 377 tpcipriv->ndis_adapter.funcnumber)) { 378 find_buddy_priv = true; 379 break; 380 } 381 } 382 } 383 384 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 385 "find_buddy_priv %d\n", find_buddy_priv); 386 387 if (find_buddy_priv) 388 *buddy_priv = tpriv; 389 390 return find_buddy_priv; 391 } 392 393 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw) 394 { 395 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 396 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 397 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset; 398 u8 linkctrl_reg; 399 u8 num4bbytes; 400 401 num4bbytes = (capabilityoffset + 0x10) / 4; 402 403 /*Read Link Control Register */ 404 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg); 405 406 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg; 407 } 408 409 static void rtl_pci_parse_configuration(struct pci_dev *pdev, 410 struct ieee80211_hw *hw) 411 { 412 struct rtl_priv *rtlpriv = rtl_priv(hw); 413 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 414 415 u8 tmp; 416 u16 linkctrl_reg; 417 418 /*Link Control Register */ 419 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg); 420 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg; 421 422 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", 423 pcipriv->ndis_adapter.linkctrl_reg); 424 425 pci_read_config_byte(pdev, 0x98, &tmp); 426 tmp |= BIT(4); 427 pci_write_config_byte(pdev, 0x98, tmp); 428 429 tmp = 0x17; 430 pci_write_config_byte(pdev, 0x70f, tmp); 431 } 432 433 static void rtl_pci_init_aspm(struct ieee80211_hw *hw) 434 { 435 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 436 437 _rtl_pci_update_default_setting(hw); 438 439 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { 440 /*Always enable ASPM & Clock Req. */ 441 rtl_pci_enable_aspm(hw); 442 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM); 443 } 444 445 } 446 447 static void _rtl_pci_io_handler_init(struct device *dev, 448 struct ieee80211_hw *hw) 449 { 450 struct rtl_priv *rtlpriv = rtl_priv(hw); 451 452 rtlpriv->io.dev = dev; 453 454 rtlpriv->io.write8_async = pci_write8_async; 455 rtlpriv->io.write16_async = pci_write16_async; 456 rtlpriv->io.write32_async = pci_write32_async; 457 458 rtlpriv->io.read8_sync = pci_read8_sync; 459 rtlpriv->io.read16_sync = pci_read16_sync; 460 rtlpriv->io.read32_sync = pci_read32_sync; 461 462 } 463 464 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw, 465 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid) 466 { 467 struct rtl_priv *rtlpriv = rtl_priv(hw); 468 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 469 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 470 struct sk_buff *next_skb; 471 u8 additionlen = FCS_LEN; 472 473 /* here open is 4, wep/tkip is 8, aes is 12*/ 474 if (info->control.hw_key) 475 additionlen += info->control.hw_key->icv_len; 476 477 /* The most skb num is 6 */ 478 tcb_desc->empkt_num = 0; 479 spin_lock_bh(&rtlpriv->locks.waitq_lock); 480 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) { 481 struct ieee80211_tx_info *next_info; 482 483 next_info = IEEE80211_SKB_CB(next_skb); 484 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) { 485 tcb_desc->empkt_len[tcb_desc->empkt_num] = 486 next_skb->len + additionlen; 487 tcb_desc->empkt_num++; 488 } else { 489 break; 490 } 491 492 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid], 493 next_skb)) 494 break; 495 496 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num) 497 break; 498 } 499 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 500 501 return true; 502 } 503 504 /* just for early mode now */ 505 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw) 506 { 507 struct rtl_priv *rtlpriv = rtl_priv(hw); 508 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 509 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 510 struct sk_buff *skb = NULL; 511 struct ieee80211_tx_info *info = NULL; 512 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 513 int tid; 514 515 if (!rtlpriv->rtlhal.earlymode_enable) 516 return; 517 518 if (rtlpriv->dm.supp_phymode_switch && 519 (rtlpriv->easy_concurrent_ctl.switch_in_process || 520 (rtlpriv->buddy_priv && 521 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process))) 522 return; 523 /* we juse use em for BE/BK/VI/VO */ 524 for (tid = 7; tid >= 0; tid--) { 525 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)]; 526 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; 527 while (!mac->act_scanning && 528 rtlpriv->psc.rfpwr_state == ERFON) { 529 struct rtl_tcb_desc tcb_desc; 530 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 531 532 spin_lock_bh(&rtlpriv->locks.waitq_lock); 533 if (!skb_queue_empty(&mac->skb_waitq[tid]) && 534 (ring->entries - skb_queue_len(&ring->queue) > 535 rtlhal->max_earlymode_num)) { 536 skb = skb_dequeue(&mac->skb_waitq[tid]); 537 } else { 538 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 539 break; 540 } 541 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 542 543 /* Some macaddr can't do early mode. like 544 * multicast/broadcast/no_qos data */ 545 info = IEEE80211_SKB_CB(skb); 546 if (info->flags & IEEE80211_TX_CTL_AMPDU) 547 _rtl_update_earlymode_info(hw, skb, 548 &tcb_desc, tid); 549 550 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc); 551 } 552 } 553 } 554 555 556 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) 557 { 558 struct rtl_priv *rtlpriv = rtl_priv(hw); 559 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 560 561 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 562 563 while (skb_queue_len(&ring->queue)) { 564 struct sk_buff *skb; 565 struct ieee80211_tx_info *info; 566 __le16 fc; 567 u8 tid; 568 u8 *entry; 569 570 if (rtlpriv->use_new_trx_flow) 571 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 572 else 573 entry = (u8 *)(&ring->desc[ring->idx]); 574 575 if (rtlpriv->cfg->ops->get_available_desc && 576 rtlpriv->cfg->ops->get_available_desc(hw, prio) <= 1) { 577 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_DMESG, 578 "no available desc!\n"); 579 return; 580 } 581 582 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx)) 583 return; 584 ring->idx = (ring->idx + 1) % ring->entries; 585 586 skb = __skb_dequeue(&ring->queue); 587 pci_unmap_single(rtlpci->pdev, 588 rtlpriv->cfg->ops-> 589 get_desc(hw, (u8 *)entry, true, 590 HW_DESC_TXBUFF_ADDR), 591 skb->len, PCI_DMA_TODEVICE); 592 593 /* remove early mode header */ 594 if (rtlpriv->rtlhal.earlymode_enable) 595 skb_pull(skb, EM_HDR_LEN); 596 597 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, 598 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", 599 ring->idx, 600 skb_queue_len(&ring->queue), 601 *(u16 *)(skb->data + 22)); 602 603 if (prio == TXCMD_QUEUE) { 604 dev_kfree_skb(skb); 605 goto tx_status_ok; 606 607 } 608 609 /* for sw LPS, just after NULL skb send out, we can 610 * sure AP knows we are sleeping, we should not let 611 * rf sleep 612 */ 613 fc = rtl_get_fc(skb); 614 if (ieee80211_is_nullfunc(fc)) { 615 if (ieee80211_has_pm(fc)) { 616 rtlpriv->mac80211.offchan_delay = true; 617 rtlpriv->psc.state_inap = true; 618 } else { 619 rtlpriv->psc.state_inap = false; 620 } 621 } 622 if (ieee80211_is_action(fc)) { 623 struct ieee80211_mgmt *action_frame = 624 (struct ieee80211_mgmt *)skb->data; 625 if (action_frame->u.action.u.ht_smps.action == 626 WLAN_HT_ACTION_SMPS) { 627 dev_kfree_skb(skb); 628 goto tx_status_ok; 629 } 630 } 631 632 /* update tid tx pkt num */ 633 tid = rtl_get_tid(skb); 634 if (tid <= 7) 635 rtlpriv->link_info.tidtx_inperiod[tid]++; 636 637 info = IEEE80211_SKB_CB(skb); 638 ieee80211_tx_info_clear_status(info); 639 640 info->flags |= IEEE80211_TX_STAT_ACK; 641 /*info->status.rates[0].count = 1; */ 642 643 ieee80211_tx_status_irqsafe(hw, skb); 644 645 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) { 646 647 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, 648 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", 649 prio, ring->idx, 650 skb_queue_len(&ring->queue)); 651 652 ieee80211_wake_queue(hw, 653 skb_get_queue_mapping 654 (skb)); 655 } 656 tx_status_ok: 657 skb = NULL; 658 } 659 660 if (((rtlpriv->link_info.num_rx_inperiod + 661 rtlpriv->link_info.num_tx_inperiod) > 8) || 662 (rtlpriv->link_info.num_rx_inperiod > 2)) 663 rtl_lps_leave(hw); 664 } 665 666 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, 667 struct sk_buff *new_skb, u8 *entry, 668 int rxring_idx, int desc_idx) 669 { 670 struct rtl_priv *rtlpriv = rtl_priv(hw); 671 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 672 u32 bufferaddress; 673 u8 tmp_one = 1; 674 struct sk_buff *skb; 675 676 if (likely(new_skb)) { 677 skb = new_skb; 678 goto remap; 679 } 680 skb = dev_alloc_skb(rtlpci->rxbuffersize); 681 if (!skb) 682 return 0; 683 684 remap: 685 /* just set skb->cb to mapping addr for pci_unmap_single use */ 686 *((dma_addr_t *)skb->cb) = 687 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb), 688 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 689 bufferaddress = *((dma_addr_t *)skb->cb); 690 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress)) 691 return 0; 692 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb; 693 if (rtlpriv->use_new_trx_flow) { 694 /* skb->cb may be 64 bit address */ 695 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 696 HW_DESC_RX_PREPARE, 697 (u8 *)(dma_addr_t *)skb->cb); 698 } else { 699 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 700 HW_DESC_RXBUFF_ADDR, 701 (u8 *)&bufferaddress); 702 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 703 HW_DESC_RXPKT_LEN, 704 (u8 *)&rtlpci->rxbuffersize); 705 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 706 HW_DESC_RXOWN, 707 (u8 *)&tmp_one); 708 } 709 return 1; 710 } 711 712 /* inorder to receive 8K AMSDU we have set skb to 713 * 9100bytes in init rx ring, but if this packet is 714 * not a AMSDU, this large packet will be sent to 715 * TCP/IP directly, this cause big packet ping fail 716 * like: "ping -s 65507", so here we will realloc skb 717 * based on the true size of packet, Mac80211 718 * Probably will do it better, but does not yet. 719 * 720 * Some platform will fail when alloc skb sometimes. 721 * in this condition, we will send the old skb to 722 * mac80211 directly, this will not cause any other 723 * issues, but only this packet will be lost by TCP/IP 724 */ 725 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw, 726 struct sk_buff *skb, 727 struct ieee80211_rx_status rx_status) 728 { 729 if (unlikely(!rtl_action_proc(hw, skb, false))) { 730 dev_kfree_skb_any(skb); 731 } else { 732 struct sk_buff *uskb = NULL; 733 734 uskb = dev_alloc_skb(skb->len + 128); 735 if (likely(uskb)) { 736 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, 737 sizeof(rx_status)); 738 skb_put_data(uskb, skb->data, skb->len); 739 dev_kfree_skb_any(skb); 740 ieee80211_rx_irqsafe(hw, uskb); 741 } else { 742 ieee80211_rx_irqsafe(hw, skb); 743 } 744 } 745 } 746 747 /*hsisr interrupt handler*/ 748 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw) 749 { 750 struct rtl_priv *rtlpriv = rtl_priv(hw); 751 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 752 753 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR], 754 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) | 755 rtlpci->sys_irq_mask); 756 } 757 758 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) 759 { 760 struct rtl_priv *rtlpriv = rtl_priv(hw); 761 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 762 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE; 763 struct ieee80211_rx_status rx_status = { 0 }; 764 unsigned int count = rtlpci->rxringcount; 765 u8 own; 766 u8 tmp_one; 767 bool unicast = false; 768 u8 hw_queue = 0; 769 unsigned int rx_remained_cnt; 770 struct rtl_stats stats = { 771 .signal = 0, 772 .rate = 0, 773 }; 774 775 /*RX NORMAL PKT */ 776 while (count--) { 777 struct ieee80211_hdr *hdr; 778 __le16 fc; 779 u16 len; 780 /*rx buffer descriptor */ 781 struct rtl_rx_buffer_desc *buffer_desc = NULL; 782 /*if use new trx flow, it means wifi info */ 783 struct rtl_rx_desc *pdesc = NULL; 784 /*rx pkt */ 785 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[ 786 rtlpci->rx_ring[rxring_idx].idx]; 787 struct sk_buff *new_skb; 788 789 if (rtlpriv->use_new_trx_flow) { 790 rx_remained_cnt = 791 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw, 792 hw_queue); 793 if (rx_remained_cnt == 0) 794 return; 795 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[ 796 rtlpci->rx_ring[rxring_idx].idx]; 797 pdesc = (struct rtl_rx_desc *)skb->data; 798 } else { /* rx descriptor */ 799 pdesc = &rtlpci->rx_ring[rxring_idx].desc[ 800 rtlpci->rx_ring[rxring_idx].idx]; 801 802 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 803 false, 804 HW_DESC_OWN); 805 if (own) /* wait data to be filled by hardware */ 806 return; 807 } 808 809 /* Reaching this point means: data is filled already 810 * AAAAAAttention !!! 811 * We can NOT access 'skb' before 'pci_unmap_single' 812 */ 813 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), 814 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 815 816 /* get a new skb - if fail, old one will be reused */ 817 new_skb = dev_alloc_skb(rtlpci->rxbuffersize); 818 if (unlikely(!new_skb)) 819 goto no_new; 820 memset(&rx_status , 0 , sizeof(rx_status)); 821 rtlpriv->cfg->ops->query_rx_desc(hw, &stats, 822 &rx_status, (u8 *)pdesc, skb); 823 824 if (rtlpriv->use_new_trx_flow) 825 rtlpriv->cfg->ops->rx_check_dma_ok(hw, 826 (u8 *)buffer_desc, 827 hw_queue); 828 829 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false, 830 HW_DESC_RXPKT_LEN); 831 832 if (skb->end - skb->tail > len) { 833 skb_put(skb, len); 834 if (rtlpriv->use_new_trx_flow) 835 skb_reserve(skb, stats.rx_drvinfo_size + 836 stats.rx_bufshift + 24); 837 else 838 skb_reserve(skb, stats.rx_drvinfo_size + 839 stats.rx_bufshift); 840 } else { 841 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 842 "skb->end - skb->tail = %d, len is %d\n", 843 skb->end - skb->tail, len); 844 dev_kfree_skb_any(skb); 845 goto new_trx_end; 846 } 847 /* handle command packet here */ 848 if (rtlpriv->cfg->ops->rx_command_packet && 849 rtlpriv->cfg->ops->rx_command_packet(hw, &stats, skb)) { 850 dev_kfree_skb_any(skb); 851 goto new_trx_end; 852 } 853 854 /* 855 * NOTICE This can not be use for mac80211, 856 * this is done in mac80211 code, 857 * if done here sec DHCP will fail 858 * skb_trim(skb, skb->len - 4); 859 */ 860 861 hdr = rtl_get_hdr(skb); 862 fc = rtl_get_fc(skb); 863 864 if (!stats.crc && !stats.hwerror) { 865 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, 866 sizeof(rx_status)); 867 868 if (is_broadcast_ether_addr(hdr->addr1)) { 869 ;/*TODO*/ 870 } else if (is_multicast_ether_addr(hdr->addr1)) { 871 ;/*TODO*/ 872 } else { 873 unicast = true; 874 rtlpriv->stats.rxbytesunicast += skb->len; 875 } 876 rtl_is_special_data(hw, skb, false, true); 877 878 if (ieee80211_is_data(fc)) { 879 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX); 880 if (unicast) 881 rtlpriv->link_info.num_rx_inperiod++; 882 } 883 884 rtl_collect_scan_list(hw, skb); 885 886 /* static bcn for roaming */ 887 rtl_beacon_statistic(hw, skb); 888 rtl_p2p_info(hw, (void *)skb->data, skb->len); 889 /* for sw lps */ 890 rtl_swlps_beacon(hw, (void *)skb->data, skb->len); 891 rtl_recognize_peer(hw, (void *)skb->data, skb->len); 892 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) && 893 (rtlpriv->rtlhal.current_bandtype == 894 BAND_ON_2_4G) && 895 (ieee80211_is_beacon(fc) || 896 ieee80211_is_probe_resp(fc))) { 897 dev_kfree_skb_any(skb); 898 } else { 899 _rtl_pci_rx_to_mac80211(hw, skb, rx_status); 900 } 901 } else { 902 dev_kfree_skb_any(skb); 903 } 904 new_trx_end: 905 if (rtlpriv->use_new_trx_flow) { 906 rtlpci->rx_ring[hw_queue].next_rx_rp += 1; 907 rtlpci->rx_ring[hw_queue].next_rx_rp %= 908 RTL_PCI_MAX_RX_COUNT; 909 910 rx_remained_cnt--; 911 rtl_write_word(rtlpriv, 0x3B4, 912 rtlpci->rx_ring[hw_queue].next_rx_rp); 913 } 914 if (((rtlpriv->link_info.num_rx_inperiod + 915 rtlpriv->link_info.num_tx_inperiod) > 8) || 916 (rtlpriv->link_info.num_rx_inperiod > 2)) 917 rtl_lps_leave(hw); 918 skb = new_skb; 919 no_new: 920 if (rtlpriv->use_new_trx_flow) { 921 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc, 922 rxring_idx, 923 rtlpci->rx_ring[rxring_idx].idx); 924 } else { 925 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc, 926 rxring_idx, 927 rtlpci->rx_ring[rxring_idx].idx); 928 if (rtlpci->rx_ring[rxring_idx].idx == 929 rtlpci->rxringcount - 1) 930 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, 931 false, 932 HW_DESC_RXERO, 933 (u8 *)&tmp_one); 934 } 935 rtlpci->rx_ring[rxring_idx].idx = 936 (rtlpci->rx_ring[rxring_idx].idx + 1) % 937 rtlpci->rxringcount; 938 } 939 } 940 941 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) 942 { 943 struct ieee80211_hw *hw = dev_id; 944 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 945 struct rtl_priv *rtlpriv = rtl_priv(hw); 946 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 947 unsigned long flags; 948 u32 inta = 0; 949 u32 intb = 0; 950 irqreturn_t ret = IRQ_HANDLED; 951 952 if (rtlpci->irq_enabled == 0) 953 return ret; 954 955 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock , flags); 956 rtlpriv->cfg->ops->disable_interrupt(hw); 957 958 /*read ISR: 4/8bytes */ 959 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb); 960 961 /*Shared IRQ or HW disappared */ 962 if (!inta || inta == 0xffff) 963 goto done; 964 965 /*<1> beacon related */ 966 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) { 967 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 968 "beacon ok interrupt!\n"); 969 } 970 971 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) { 972 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 973 "beacon err interrupt!\n"); 974 } 975 976 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) { 977 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); 978 } 979 980 if (inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) { 981 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 982 "prepare beacon for interrupt!\n"); 983 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet); 984 } 985 986 /*<2> Tx related */ 987 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW])) 988 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); 989 990 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) { 991 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 992 "Manage ok interrupt!\n"); 993 _rtl_pci_tx_isr(hw, MGNT_QUEUE); 994 } 995 996 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) { 997 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 998 "HIGH_QUEUE ok interrupt!\n"); 999 _rtl_pci_tx_isr(hw, HIGH_QUEUE); 1000 } 1001 1002 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) { 1003 rtlpriv->link_info.num_tx_inperiod++; 1004 1005 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1006 "BK Tx OK interrupt!\n"); 1007 _rtl_pci_tx_isr(hw, BK_QUEUE); 1008 } 1009 1010 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) { 1011 rtlpriv->link_info.num_tx_inperiod++; 1012 1013 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1014 "BE TX OK interrupt!\n"); 1015 _rtl_pci_tx_isr(hw, BE_QUEUE); 1016 } 1017 1018 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) { 1019 rtlpriv->link_info.num_tx_inperiod++; 1020 1021 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1022 "VI TX OK interrupt!\n"); 1023 _rtl_pci_tx_isr(hw, VI_QUEUE); 1024 } 1025 1026 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) { 1027 rtlpriv->link_info.num_tx_inperiod++; 1028 1029 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1030 "Vo TX OK interrupt!\n"); 1031 _rtl_pci_tx_isr(hw, VO_QUEUE); 1032 } 1033 1034 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) { 1035 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) { 1036 rtlpriv->link_info.num_tx_inperiod++; 1037 1038 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1039 "CMD TX OK interrupt!\n"); 1040 _rtl_pci_tx_isr(hw, TXCMD_QUEUE); 1041 } 1042 } 1043 1044 /*<3> Rx related */ 1045 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) { 1046 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); 1047 _rtl_pci_rx_interrupt(hw); 1048 } 1049 1050 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) { 1051 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1052 "rx descriptor unavailable!\n"); 1053 _rtl_pci_rx_interrupt(hw); 1054 } 1055 1056 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) { 1057 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); 1058 _rtl_pci_rx_interrupt(hw); 1059 } 1060 1061 /*<4> fw related*/ 1062 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { 1063 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) { 1064 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1065 "firmware interrupt!\n"); 1066 queue_delayed_work(rtlpriv->works.rtl_wq, 1067 &rtlpriv->works.fwevt_wq, 0); 1068 } 1069 } 1070 1071 /*<5> hsisr related*/ 1072 /* Only 8188EE & 8723BE Supported. 1073 * If Other ICs Come in, System will corrupt, 1074 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR] 1075 * are not initialized 1076 */ 1077 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE || 1078 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) { 1079 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) { 1080 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, 1081 "hsisr interrupt!\n"); 1082 _rtl_pci_hs_interrupt(hw); 1083 } 1084 } 1085 1086 if (rtlpriv->rtlhal.earlymode_enable) 1087 tasklet_schedule(&rtlpriv->works.irq_tasklet); 1088 1089 done: 1090 rtlpriv->cfg->ops->enable_interrupt(hw); 1091 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1092 return ret; 1093 } 1094 1095 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw) 1096 { 1097 _rtl_pci_tx_chk_waitq(hw); 1098 } 1099 1100 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw) 1101 { 1102 struct rtl_priv *rtlpriv = rtl_priv(hw); 1103 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1104 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1105 struct rtl8192_tx_ring *ring = NULL; 1106 struct ieee80211_hdr *hdr = NULL; 1107 struct ieee80211_tx_info *info = NULL; 1108 struct sk_buff *pskb = NULL; 1109 struct rtl_tx_desc *pdesc = NULL; 1110 struct rtl_tcb_desc tcb_desc; 1111 /*This is for new trx flow*/ 1112 struct rtl_tx_buffer_desc *pbuffer_desc = NULL; 1113 u8 temp_one = 1; 1114 u8 *entry; 1115 1116 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 1117 ring = &rtlpci->tx_ring[BEACON_QUEUE]; 1118 pskb = __skb_dequeue(&ring->queue); 1119 if (rtlpriv->use_new_trx_flow) 1120 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1121 else 1122 entry = (u8 *)(&ring->desc[ring->idx]); 1123 if (pskb) { 1124 pci_unmap_single(rtlpci->pdev, 1125 rtlpriv->cfg->ops->get_desc( 1126 hw, (u8 *)entry, true, HW_DESC_TXBUFF_ADDR), 1127 pskb->len, PCI_DMA_TODEVICE); 1128 kfree_skb(pskb); 1129 } 1130 1131 /*NB: the beacon data buffer must be 32-bit aligned. */ 1132 pskb = ieee80211_beacon_get(hw, mac->vif); 1133 if (pskb == NULL) 1134 return; 1135 hdr = rtl_get_hdr(pskb); 1136 info = IEEE80211_SKB_CB(pskb); 1137 pdesc = &ring->desc[0]; 1138 if (rtlpriv->use_new_trx_flow) 1139 pbuffer_desc = &ring->buffer_desc[0]; 1140 1141 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1142 (u8 *)pbuffer_desc, info, NULL, pskb, 1143 BEACON_QUEUE, &tcb_desc); 1144 1145 __skb_queue_tail(&ring->queue, pskb); 1146 1147 if (rtlpriv->use_new_trx_flow) { 1148 temp_one = 4; 1149 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true, 1150 HW_DESC_OWN, (u8 *)&temp_one); 1151 } else { 1152 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN, 1153 &temp_one); 1154 } 1155 return; 1156 } 1157 1158 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw) 1159 { 1160 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1161 struct rtl_priv *rtlpriv = rtl_priv(hw); 1162 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1163 u8 i; 1164 u16 desc_num; 1165 1166 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) 1167 desc_num = TX_DESC_NUM_92E; 1168 else 1169 desc_num = RT_TXDESC_NUM; 1170 1171 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1172 rtlpci->txringcount[i] = desc_num; 1173 1174 /* 1175 *we just alloc 2 desc for beacon queue, 1176 *because we just need first desc in hw beacon. 1177 */ 1178 rtlpci->txringcount[BEACON_QUEUE] = 2; 1179 1180 /*BE queue need more descriptor for performance 1181 *consideration or, No more tx desc will happen, 1182 *and may cause mac80211 mem leakage. 1183 */ 1184 if (!rtl_priv(hw)->use_new_trx_flow) 1185 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE; 1186 1187 rtlpci->rxbuffersize = 9100; /*2048/1024; */ 1188 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */ 1189 } 1190 1191 static void _rtl_pci_init_struct(struct ieee80211_hw *hw, 1192 struct pci_dev *pdev) 1193 { 1194 struct rtl_priv *rtlpriv = rtl_priv(hw); 1195 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1196 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1197 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1198 1199 rtlpci->up_first_time = true; 1200 rtlpci->being_init_adapter = false; 1201 1202 rtlhal->hw = hw; 1203 rtlpci->pdev = pdev; 1204 1205 /*Tx/Rx related var */ 1206 _rtl_pci_init_trx_var(hw); 1207 1208 /*IBSS*/ 1209 mac->beacon_interval = 100; 1210 1211 /*AMPDU*/ 1212 mac->min_space_cfg = 0; 1213 mac->max_mss_density = 0; 1214 /*set sane AMPDU defaults */ 1215 mac->current_ampdu_density = 7; 1216 mac->current_ampdu_factor = 3; 1217 1218 /*Retry Limit*/ 1219 mac->retry_short = 7; 1220 mac->retry_long = 7; 1221 1222 /*QOS*/ 1223 rtlpci->acm_method = EACMWAY2_SW; 1224 1225 /*task */ 1226 tasklet_init(&rtlpriv->works.irq_tasklet, 1227 (void (*)(unsigned long))_rtl_pci_irq_tasklet, 1228 (unsigned long)hw); 1229 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet, 1230 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet, 1231 (unsigned long)hw); 1232 INIT_WORK(&rtlpriv->works.lps_change_work, 1233 rtl_lps_change_work_callback); 1234 } 1235 1236 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, 1237 unsigned int prio, unsigned int entries) 1238 { 1239 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1240 struct rtl_priv *rtlpriv = rtl_priv(hw); 1241 struct rtl_tx_buffer_desc *buffer_desc; 1242 struct rtl_tx_desc *desc; 1243 dma_addr_t buffer_desc_dma, desc_dma; 1244 u32 nextdescaddress; 1245 int i; 1246 1247 /* alloc tx buffer desc for new trx flow*/ 1248 if (rtlpriv->use_new_trx_flow) { 1249 buffer_desc = 1250 pci_zalloc_consistent(rtlpci->pdev, 1251 sizeof(*buffer_desc) * entries, 1252 &buffer_desc_dma); 1253 1254 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) { 1255 pr_err("Cannot allocate TX ring (prio = %d)\n", 1256 prio); 1257 return -ENOMEM; 1258 } 1259 1260 rtlpci->tx_ring[prio].buffer_desc = buffer_desc; 1261 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma; 1262 1263 rtlpci->tx_ring[prio].cur_tx_rp = 0; 1264 rtlpci->tx_ring[prio].cur_tx_wp = 0; 1265 rtlpci->tx_ring[prio].avl_desc = entries; 1266 } 1267 1268 /* alloc dma for this ring */ 1269 desc = pci_zalloc_consistent(rtlpci->pdev, 1270 sizeof(*desc) * entries, &desc_dma); 1271 1272 if (!desc || (unsigned long)desc & 0xFF) { 1273 pr_err("Cannot allocate TX ring (prio = %d)\n", prio); 1274 return -ENOMEM; 1275 } 1276 1277 rtlpci->tx_ring[prio].desc = desc; 1278 rtlpci->tx_ring[prio].dma = desc_dma; 1279 1280 rtlpci->tx_ring[prio].idx = 0; 1281 rtlpci->tx_ring[prio].entries = entries; 1282 skb_queue_head_init(&rtlpci->tx_ring[prio].queue); 1283 1284 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", 1285 prio, desc); 1286 1287 /* init every desc in this ring */ 1288 if (!rtlpriv->use_new_trx_flow) { 1289 for (i = 0; i < entries; i++) { 1290 nextdescaddress = (u32)desc_dma + 1291 ((i + 1) % entries) * 1292 sizeof(*desc); 1293 1294 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i], 1295 true, 1296 HW_DESC_TX_NEXTDESC_ADDR, 1297 (u8 *)&nextdescaddress); 1298 } 1299 } 1300 return 0; 1301 } 1302 1303 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1304 { 1305 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1306 struct rtl_priv *rtlpriv = rtl_priv(hw); 1307 int i; 1308 1309 if (rtlpriv->use_new_trx_flow) { 1310 struct rtl_rx_buffer_desc *entry = NULL; 1311 /* alloc dma for this ring */ 1312 rtlpci->rx_ring[rxring_idx].buffer_desc = 1313 pci_zalloc_consistent(rtlpci->pdev, 1314 sizeof(*rtlpci->rx_ring[rxring_idx]. 1315 buffer_desc) * 1316 rtlpci->rxringcount, 1317 &rtlpci->rx_ring[rxring_idx].dma); 1318 if (!rtlpci->rx_ring[rxring_idx].buffer_desc || 1319 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) { 1320 pr_err("Cannot allocate RX ring\n"); 1321 return -ENOMEM; 1322 } 1323 1324 /* init every desc in this ring */ 1325 rtlpci->rx_ring[rxring_idx].idx = 0; 1326 for (i = 0; i < rtlpci->rxringcount; i++) { 1327 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i]; 1328 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1329 rxring_idx, i)) 1330 return -ENOMEM; 1331 } 1332 } else { 1333 struct rtl_rx_desc *entry = NULL; 1334 u8 tmp_one = 1; 1335 /* alloc dma for this ring */ 1336 rtlpci->rx_ring[rxring_idx].desc = 1337 pci_zalloc_consistent(rtlpci->pdev, 1338 sizeof(*rtlpci->rx_ring[rxring_idx]. 1339 desc) * rtlpci->rxringcount, 1340 &rtlpci->rx_ring[rxring_idx].dma); 1341 if (!rtlpci->rx_ring[rxring_idx].desc || 1342 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) { 1343 pr_err("Cannot allocate RX ring\n"); 1344 return -ENOMEM; 1345 } 1346 1347 /* init every desc in this ring */ 1348 rtlpci->rx_ring[rxring_idx].idx = 0; 1349 1350 for (i = 0; i < rtlpci->rxringcount; i++) { 1351 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1352 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1353 rxring_idx, i)) 1354 return -ENOMEM; 1355 } 1356 1357 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1358 HW_DESC_RXERO, &tmp_one); 1359 } 1360 return 0; 1361 } 1362 1363 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw, 1364 unsigned int prio) 1365 { 1366 struct rtl_priv *rtlpriv = rtl_priv(hw); 1367 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1368 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 1369 1370 /* free every desc in this ring */ 1371 while (skb_queue_len(&ring->queue)) { 1372 u8 *entry; 1373 struct sk_buff *skb = __skb_dequeue(&ring->queue); 1374 1375 if (rtlpriv->use_new_trx_flow) 1376 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1377 else 1378 entry = (u8 *)(&ring->desc[ring->idx]); 1379 1380 pci_unmap_single(rtlpci->pdev, 1381 rtlpriv->cfg-> 1382 ops->get_desc(hw, (u8 *)entry, 1383 true, 1384 HW_DESC_TXBUFF_ADDR), 1385 skb->len, PCI_DMA_TODEVICE); 1386 kfree_skb(skb); 1387 ring->idx = (ring->idx + 1) % ring->entries; 1388 } 1389 1390 /* free dma of this ring */ 1391 pci_free_consistent(rtlpci->pdev, 1392 sizeof(*ring->desc) * ring->entries, 1393 ring->desc, ring->dma); 1394 ring->desc = NULL; 1395 if (rtlpriv->use_new_trx_flow) { 1396 pci_free_consistent(rtlpci->pdev, 1397 sizeof(*ring->buffer_desc) * ring->entries, 1398 ring->buffer_desc, ring->buffer_desc_dma); 1399 ring->buffer_desc = NULL; 1400 } 1401 } 1402 1403 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1404 { 1405 struct rtl_priv *rtlpriv = rtl_priv(hw); 1406 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1407 int i; 1408 1409 /* free every desc in this ring */ 1410 for (i = 0; i < rtlpci->rxringcount; i++) { 1411 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i]; 1412 1413 if (!skb) 1414 continue; 1415 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), 1416 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); 1417 kfree_skb(skb); 1418 } 1419 1420 /* free dma of this ring */ 1421 if (rtlpriv->use_new_trx_flow) { 1422 pci_free_consistent(rtlpci->pdev, 1423 sizeof(*rtlpci->rx_ring[rxring_idx]. 1424 buffer_desc) * rtlpci->rxringcount, 1425 rtlpci->rx_ring[rxring_idx].buffer_desc, 1426 rtlpci->rx_ring[rxring_idx].dma); 1427 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL; 1428 } else { 1429 pci_free_consistent(rtlpci->pdev, 1430 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1431 rtlpci->rxringcount, 1432 rtlpci->rx_ring[rxring_idx].desc, 1433 rtlpci->rx_ring[rxring_idx].dma); 1434 rtlpci->rx_ring[rxring_idx].desc = NULL; 1435 } 1436 } 1437 1438 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw) 1439 { 1440 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1441 int ret; 1442 int i, rxring_idx; 1443 1444 /* rxring_idx 0:RX_MPDU_QUEUE 1445 * rxring_idx 1:RX_CMD_QUEUE 1446 */ 1447 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1448 ret = _rtl_pci_init_rx_ring(hw, rxring_idx); 1449 if (ret) 1450 return ret; 1451 } 1452 1453 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1454 ret = _rtl_pci_init_tx_ring(hw, i, 1455 rtlpci->txringcount[i]); 1456 if (ret) 1457 goto err_free_rings; 1458 } 1459 1460 return 0; 1461 1462 err_free_rings: 1463 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1464 _rtl_pci_free_rx_ring(hw, rxring_idx); 1465 1466 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1467 if (rtlpci->tx_ring[i].desc || 1468 rtlpci->tx_ring[i].buffer_desc) 1469 _rtl_pci_free_tx_ring(hw, i); 1470 1471 return 1; 1472 } 1473 1474 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw) 1475 { 1476 u32 i, rxring_idx; 1477 1478 /*free rx rings */ 1479 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1480 _rtl_pci_free_rx_ring(hw, rxring_idx); 1481 1482 /*free tx rings */ 1483 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1484 _rtl_pci_free_tx_ring(hw, i); 1485 1486 return 0; 1487 } 1488 1489 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw) 1490 { 1491 struct rtl_priv *rtlpriv = rtl_priv(hw); 1492 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1493 int i, rxring_idx; 1494 unsigned long flags; 1495 u8 tmp_one = 1; 1496 u32 bufferaddress; 1497 /* rxring_idx 0:RX_MPDU_QUEUE */ 1498 /* rxring_idx 1:RX_CMD_QUEUE */ 1499 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1500 /* force the rx_ring[RX_MPDU_QUEUE/ 1501 * RX_CMD_QUEUE].idx to the first one 1502 *new trx flow, do nothing 1503 */ 1504 if (!rtlpriv->use_new_trx_flow && 1505 rtlpci->rx_ring[rxring_idx].desc) { 1506 struct rtl_rx_desc *entry = NULL; 1507 1508 rtlpci->rx_ring[rxring_idx].idx = 0; 1509 for (i = 0; i < rtlpci->rxringcount; i++) { 1510 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1511 bufferaddress = 1512 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1513 false , HW_DESC_RXBUFF_ADDR); 1514 memset((u8 *)entry , 0 , 1515 sizeof(*rtlpci->rx_ring 1516 [rxring_idx].desc));/*clear one entry*/ 1517 if (rtlpriv->use_new_trx_flow) { 1518 rtlpriv->cfg->ops->set_desc(hw, 1519 (u8 *)entry, false, 1520 HW_DESC_RX_PREPARE, 1521 (u8 *)&bufferaddress); 1522 } else { 1523 rtlpriv->cfg->ops->set_desc(hw, 1524 (u8 *)entry, false, 1525 HW_DESC_RXBUFF_ADDR, 1526 (u8 *)&bufferaddress); 1527 rtlpriv->cfg->ops->set_desc(hw, 1528 (u8 *)entry, false, 1529 HW_DESC_RXPKT_LEN, 1530 (u8 *)&rtlpci->rxbuffersize); 1531 rtlpriv->cfg->ops->set_desc(hw, 1532 (u8 *)entry, false, 1533 HW_DESC_RXOWN, 1534 (u8 *)&tmp_one); 1535 } 1536 } 1537 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1538 HW_DESC_RXERO, (u8 *)&tmp_one); 1539 } 1540 rtlpci->rx_ring[rxring_idx].idx = 0; 1541 } 1542 1543 /* 1544 *after reset, release previous pending packet, 1545 *and force the tx idx to the first one 1546 */ 1547 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1548 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1549 if (rtlpci->tx_ring[i].desc || 1550 rtlpci->tx_ring[i].buffer_desc) { 1551 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i]; 1552 1553 while (skb_queue_len(&ring->queue)) { 1554 u8 *entry; 1555 struct sk_buff *skb = 1556 __skb_dequeue(&ring->queue); 1557 if (rtlpriv->use_new_trx_flow) 1558 entry = (u8 *)(&ring->buffer_desc 1559 [ring->idx]); 1560 else 1561 entry = (u8 *)(&ring->desc[ring->idx]); 1562 1563 pci_unmap_single(rtlpci->pdev, 1564 rtlpriv->cfg->ops-> 1565 get_desc(hw, (u8 *) 1566 entry, 1567 true, 1568 HW_DESC_TXBUFF_ADDR), 1569 skb->len, PCI_DMA_TODEVICE); 1570 dev_kfree_skb_irq(skb); 1571 ring->idx = (ring->idx + 1) % ring->entries; 1572 } 1573 ring->idx = 0; 1574 } 1575 } 1576 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1577 1578 return 0; 1579 } 1580 1581 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw, 1582 struct ieee80211_sta *sta, 1583 struct sk_buff *skb) 1584 { 1585 struct rtl_priv *rtlpriv = rtl_priv(hw); 1586 struct rtl_sta_info *sta_entry = NULL; 1587 u8 tid = rtl_get_tid(skb); 1588 __le16 fc = rtl_get_fc(skb); 1589 1590 if (!sta) 1591 return false; 1592 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1593 1594 if (!rtlpriv->rtlhal.earlymode_enable) 1595 return false; 1596 if (ieee80211_is_nullfunc(fc)) 1597 return false; 1598 if (ieee80211_is_qos_nullfunc(fc)) 1599 return false; 1600 if (ieee80211_is_pspoll(fc)) 1601 return false; 1602 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL) 1603 return false; 1604 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE) 1605 return false; 1606 if (tid > 7) 1607 return false; 1608 1609 /* maybe every tid should be checked */ 1610 if (!rtlpriv->link_info.higher_busytxtraffic[tid]) 1611 return false; 1612 1613 spin_lock_bh(&rtlpriv->locks.waitq_lock); 1614 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb); 1615 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 1616 1617 return true; 1618 } 1619 1620 static int rtl_pci_tx(struct ieee80211_hw *hw, 1621 struct ieee80211_sta *sta, 1622 struct sk_buff *skb, 1623 struct rtl_tcb_desc *ptcb_desc) 1624 { 1625 struct rtl_priv *rtlpriv = rtl_priv(hw); 1626 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1627 struct rtl8192_tx_ring *ring; 1628 struct rtl_tx_desc *pdesc; 1629 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL; 1630 u16 idx; 1631 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb); 1632 unsigned long flags; 1633 struct ieee80211_hdr *hdr = rtl_get_hdr(skb); 1634 __le16 fc = rtl_get_fc(skb); 1635 u8 *pda_addr = hdr->addr1; 1636 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1637 u8 own; 1638 u8 temp_one = 1; 1639 1640 if (ieee80211_is_mgmt(fc)) 1641 rtl_tx_mgmt_proc(hw, skb); 1642 1643 if (rtlpriv->psc.sw_ps_enabled) { 1644 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) && 1645 !ieee80211_has_pm(fc)) 1646 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1647 } 1648 1649 rtl_action_proc(hw, skb, true); 1650 1651 if (is_multicast_ether_addr(pda_addr)) 1652 rtlpriv->stats.txbytesmulticast += skb->len; 1653 else if (is_broadcast_ether_addr(pda_addr)) 1654 rtlpriv->stats.txbytesbroadcast += skb->len; 1655 else 1656 rtlpriv->stats.txbytesunicast += skb->len; 1657 1658 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1659 ring = &rtlpci->tx_ring[hw_queue]; 1660 if (hw_queue != BEACON_QUEUE) { 1661 if (rtlpriv->use_new_trx_flow) 1662 idx = ring->cur_tx_wp; 1663 else 1664 idx = (ring->idx + skb_queue_len(&ring->queue)) % 1665 ring->entries; 1666 } else { 1667 idx = 0; 1668 } 1669 1670 pdesc = &ring->desc[idx]; 1671 if (rtlpriv->use_new_trx_flow) { 1672 ptx_bd_desc = &ring->buffer_desc[idx]; 1673 } else { 1674 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 1675 true, HW_DESC_OWN); 1676 1677 if ((own == 1) && (hw_queue != BEACON_QUEUE)) { 1678 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1679 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1680 hw_queue, ring->idx, idx, 1681 skb_queue_len(&ring->queue)); 1682 1683 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, 1684 flags); 1685 return skb->len; 1686 } 1687 } 1688 1689 if (rtlpriv->cfg->ops->get_available_desc && 1690 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) { 1691 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1692 "get_available_desc fail\n"); 1693 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, 1694 flags); 1695 return skb->len; 1696 } 1697 1698 if (ieee80211_is_data(fc)) 1699 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX); 1700 1701 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1702 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc); 1703 1704 __skb_queue_tail(&ring->queue, skb); 1705 1706 if (rtlpriv->use_new_trx_flow) { 1707 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1708 HW_DESC_OWN, &hw_queue); 1709 } else { 1710 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1711 HW_DESC_OWN, &temp_one); 1712 } 1713 1714 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 && 1715 hw_queue != BEACON_QUEUE) { 1716 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 1717 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1718 hw_queue, ring->idx, idx, 1719 skb_queue_len(&ring->queue)); 1720 1721 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 1722 } 1723 1724 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1725 1726 rtlpriv->cfg->ops->tx_polling(hw, hw_queue); 1727 1728 return 0; 1729 } 1730 1731 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1732 { 1733 struct rtl_priv *rtlpriv = rtl_priv(hw); 1734 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1735 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1736 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1737 u16 i = 0; 1738 int queue_id; 1739 struct rtl8192_tx_ring *ring; 1740 1741 if (mac->skip_scan) 1742 return; 1743 1744 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) { 1745 u32 queue_len; 1746 1747 if (((queues >> queue_id) & 0x1) == 0) { 1748 queue_id--; 1749 continue; 1750 } 1751 ring = &pcipriv->dev.tx_ring[queue_id]; 1752 queue_len = skb_queue_len(&ring->queue); 1753 if (queue_len == 0 || queue_id == BEACON_QUEUE || 1754 queue_id == TXCMD_QUEUE) { 1755 queue_id--; 1756 continue; 1757 } else { 1758 msleep(20); 1759 i++; 1760 } 1761 1762 /* we just wait 1s for all queues */ 1763 if (rtlpriv->psc.rfpwr_state == ERFOFF || 1764 is_hal_stop(rtlhal) || i >= 200) 1765 return; 1766 } 1767 } 1768 1769 static void rtl_pci_deinit(struct ieee80211_hw *hw) 1770 { 1771 struct rtl_priv *rtlpriv = rtl_priv(hw); 1772 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1773 1774 _rtl_pci_deinit_trx_ring(hw); 1775 1776 synchronize_irq(rtlpci->pdev->irq); 1777 tasklet_kill(&rtlpriv->works.irq_tasklet); 1778 cancel_work_sync(&rtlpriv->works.lps_change_work); 1779 1780 flush_workqueue(rtlpriv->works.rtl_wq); 1781 destroy_workqueue(rtlpriv->works.rtl_wq); 1782 1783 } 1784 1785 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev) 1786 { 1787 int err; 1788 1789 _rtl_pci_init_struct(hw, pdev); 1790 1791 err = _rtl_pci_init_trx_ring(hw); 1792 if (err) { 1793 pr_err("tx ring initialization failed\n"); 1794 return err; 1795 } 1796 1797 return 0; 1798 } 1799 1800 static int rtl_pci_start(struct ieee80211_hw *hw) 1801 { 1802 struct rtl_priv *rtlpriv = rtl_priv(hw); 1803 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1804 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1805 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1806 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw)); 1807 1808 int err; 1809 1810 rtl_pci_reset_trx_ring(hw); 1811 1812 rtlpci->driver_is_goingto_unload = false; 1813 if (rtlpriv->cfg->ops->get_btc_status && 1814 rtlpriv->cfg->ops->get_btc_status()) { 1815 rtlpriv->btcoexist.btc_info.ap_num = 36; 1816 rtlpriv->btcoexist.btc_ops->btc_init_variables(rtlpriv); 1817 rtlpriv->btcoexist.btc_ops->btc_init_hal_vars(rtlpriv); 1818 } 1819 err = rtlpriv->cfg->ops->hw_init(hw); 1820 if (err) { 1821 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1822 "Failed to config hardware!\n"); 1823 return err; 1824 } 1825 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, 1826 &rtlmac->retry_long); 1827 1828 rtlpriv->cfg->ops->enable_interrupt(hw); 1829 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); 1830 1831 rtl_init_rx_config(hw); 1832 1833 /*should be after adapter start and interrupt enable. */ 1834 set_hal_start(rtlhal); 1835 1836 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1837 1838 rtlpci->up_first_time = false; 1839 1840 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "rtl_pci_start OK\n"); 1841 return 0; 1842 } 1843 1844 static void rtl_pci_stop(struct ieee80211_hw *hw) 1845 { 1846 struct rtl_priv *rtlpriv = rtl_priv(hw); 1847 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1848 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1849 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1850 unsigned long flags; 1851 u8 RFInProgressTimeOut = 0; 1852 1853 if (rtlpriv->cfg->ops->get_btc_status()) 1854 rtlpriv->btcoexist.btc_ops->btc_halt_notify(); 1855 1856 /* 1857 *should be before disable interrupt&adapter 1858 *and will do it immediately. 1859 */ 1860 set_hal_stop(rtlhal); 1861 1862 rtlpci->driver_is_goingto_unload = true; 1863 rtlpriv->cfg->ops->disable_interrupt(hw); 1864 cancel_work_sync(&rtlpriv->works.lps_change_work); 1865 1866 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1867 while (ppsc->rfchange_inprogress) { 1868 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1869 if (RFInProgressTimeOut > 100) { 1870 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1871 break; 1872 } 1873 mdelay(1); 1874 RFInProgressTimeOut++; 1875 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1876 } 1877 ppsc->rfchange_inprogress = true; 1878 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1879 1880 rtlpriv->cfg->ops->hw_disable(hw); 1881 /* some things are not needed if firmware not available */ 1882 if (!rtlpriv->max_fw_size) 1883 return; 1884 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1885 1886 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1887 ppsc->rfchange_inprogress = false; 1888 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1889 1890 rtl_pci_enable_aspm(hw); 1891 } 1892 1893 static bool _rtl_pci_find_adapter(struct pci_dev *pdev, 1894 struct ieee80211_hw *hw) 1895 { 1896 struct rtl_priv *rtlpriv = rtl_priv(hw); 1897 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1898 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1899 struct pci_dev *bridge_pdev = pdev->bus->self; 1900 u16 venderid; 1901 u16 deviceid; 1902 u8 revisionid; 1903 u16 irqline; 1904 u8 tmp; 1905 1906 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1907 venderid = pdev->vendor; 1908 deviceid = pdev->device; 1909 pci_read_config_byte(pdev, 0x8, &revisionid); 1910 pci_read_config_word(pdev, 0x3C, &irqline); 1911 1912 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses 1913 * r8192e_pci, and RTL8192SE, which uses this driver. If the 1914 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then 1915 * the correct driver is r8192e_pci, thus this routine should 1916 * return false. 1917 */ 1918 if (deviceid == RTL_PCI_8192SE_DID && 1919 revisionid == RTL_PCI_REVISION_ID_8192PCIE) 1920 return false; 1921 1922 if (deviceid == RTL_PCI_8192_DID || 1923 deviceid == RTL_PCI_0044_DID || 1924 deviceid == RTL_PCI_0047_DID || 1925 deviceid == RTL_PCI_8192SE_DID || 1926 deviceid == RTL_PCI_8174_DID || 1927 deviceid == RTL_PCI_8173_DID || 1928 deviceid == RTL_PCI_8172_DID || 1929 deviceid == RTL_PCI_8171_DID) { 1930 switch (revisionid) { 1931 case RTL_PCI_REVISION_ID_8192PCIE: 1932 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1933 "8192 PCI-E is found - vid/did=%x/%x\n", 1934 venderid, deviceid); 1935 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E; 1936 return false; 1937 case RTL_PCI_REVISION_ID_8192SE: 1938 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1939 "8192SE is found - vid/did=%x/%x\n", 1940 venderid, deviceid); 1941 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1942 break; 1943 default: 1944 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1945 "Err: Unknown device - vid/did=%x/%x\n", 1946 venderid, deviceid); 1947 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1948 break; 1949 1950 } 1951 } else if (deviceid == RTL_PCI_8723AE_DID) { 1952 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE; 1953 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1954 "8723AE PCI-E is found - " 1955 "vid/did=%x/%x\n", venderid, deviceid); 1956 } else if (deviceid == RTL_PCI_8192CET_DID || 1957 deviceid == RTL_PCI_8192CE_DID || 1958 deviceid == RTL_PCI_8191CE_DID || 1959 deviceid == RTL_PCI_8188CE_DID) { 1960 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE; 1961 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1962 "8192C PCI-E is found - vid/did=%x/%x\n", 1963 venderid, deviceid); 1964 } else if (deviceid == RTL_PCI_8192DE_DID || 1965 deviceid == RTL_PCI_8192DE_DID2) { 1966 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE; 1967 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1968 "8192D PCI-E is found - vid/did=%x/%x\n", 1969 venderid, deviceid); 1970 } else if (deviceid == RTL_PCI_8188EE_DID) { 1971 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE; 1972 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1973 "Find adapter, Hardware type is 8188EE\n"); 1974 } else if (deviceid == RTL_PCI_8723BE_DID) { 1975 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE; 1976 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, 1977 "Find adapter, Hardware type is 8723BE\n"); 1978 } else if (deviceid == RTL_PCI_8192EE_DID) { 1979 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE; 1980 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, 1981 "Find adapter, Hardware type is 8192EE\n"); 1982 } else if (deviceid == RTL_PCI_8821AE_DID) { 1983 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE; 1984 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, 1985 "Find adapter, Hardware type is 8821AE\n"); 1986 } else if (deviceid == RTL_PCI_8812AE_DID) { 1987 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE; 1988 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, 1989 "Find adapter, Hardware type is 8812AE\n"); 1990 } else { 1991 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1992 "Err: Unknown device - vid/did=%x/%x\n", 1993 venderid, deviceid); 1994 1995 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE; 1996 } 1997 1998 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) { 1999 if (revisionid == 0 || revisionid == 1) { 2000 if (revisionid == 0) { 2001 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2002 "Find 92DE MAC0\n"); 2003 rtlhal->interfaceindex = 0; 2004 } else if (revisionid == 1) { 2005 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2006 "Find 92DE MAC1\n"); 2007 rtlhal->interfaceindex = 1; 2008 } 2009 } else { 2010 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2011 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", 2012 venderid, deviceid, revisionid); 2013 rtlhal->interfaceindex = 0; 2014 } 2015 } 2016 2017 /* 92ee use new trx flow */ 2018 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) 2019 rtlpriv->use_new_trx_flow = true; 2020 else 2021 rtlpriv->use_new_trx_flow = false; 2022 2023 /*find bus info */ 2024 pcipriv->ndis_adapter.busnumber = pdev->bus->number; 2025 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn); 2026 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn); 2027 2028 /*find bridge info */ 2029 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 2030 /* some ARM have no bridge_pdev and will crash here 2031 * so we should check if bridge_pdev is NULL 2032 */ 2033 if (bridge_pdev) { 2034 /*find bridge info if available */ 2035 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor; 2036 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { 2037 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { 2038 pcipriv->ndis_adapter.pcibridge_vendor = tmp; 2039 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2040 "Pci Bridge Vendor is found index: %d\n", 2041 tmp); 2042 break; 2043 } 2044 } 2045 } 2046 2047 if (pcipriv->ndis_adapter.pcibridge_vendor != 2048 PCI_BRIDGE_VENDOR_UNKNOWN) { 2049 pcipriv->ndis_adapter.pcibridge_busnum = 2050 bridge_pdev->bus->number; 2051 pcipriv->ndis_adapter.pcibridge_devnum = 2052 PCI_SLOT(bridge_pdev->devfn); 2053 pcipriv->ndis_adapter.pcibridge_funcnum = 2054 PCI_FUNC(bridge_pdev->devfn); 2055 pcipriv->ndis_adapter.pcibridge_pciehdr_offset = 2056 pci_pcie_cap(bridge_pdev); 2057 pcipriv->ndis_adapter.num4bytes = 2058 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4; 2059 2060 rtl_pci_get_linkcontrol_field(hw); 2061 2062 if (pcipriv->ndis_adapter.pcibridge_vendor == 2063 PCI_BRIDGE_VENDOR_AMD) { 2064 pcipriv->ndis_adapter.amd_l1_patch = 2065 rtl_pci_get_amd_l1_patch(hw); 2066 } 2067 } 2068 2069 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2070 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", 2071 pcipriv->ndis_adapter.busnumber, 2072 pcipriv->ndis_adapter.devnumber, 2073 pcipriv->ndis_adapter.funcnumber, 2074 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); 2075 2076 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2077 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n", 2078 pcipriv->ndis_adapter.pcibridge_busnum, 2079 pcipriv->ndis_adapter.pcibridge_devnum, 2080 pcipriv->ndis_adapter.pcibridge_funcnum, 2081 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], 2082 pcipriv->ndis_adapter.pcibridge_pciehdr_offset, 2083 pcipriv->ndis_adapter.pcibridge_linkctrlreg, 2084 pcipriv->ndis_adapter.amd_l1_patch); 2085 2086 rtl_pci_parse_configuration(pdev, hw); 2087 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list); 2088 2089 return true; 2090 } 2091 2092 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw) 2093 { 2094 struct rtl_priv *rtlpriv = rtl_priv(hw); 2095 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2096 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2097 int ret; 2098 2099 ret = pci_enable_msi(rtlpci->pdev); 2100 if (ret < 0) 2101 return ret; 2102 2103 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2104 IRQF_SHARED, KBUILD_MODNAME, hw); 2105 if (ret < 0) { 2106 pci_disable_msi(rtlpci->pdev); 2107 return ret; 2108 } 2109 2110 rtlpci->using_msi = true; 2111 2112 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG, 2113 "MSI Interrupt Mode!\n"); 2114 return 0; 2115 } 2116 2117 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw) 2118 { 2119 struct rtl_priv *rtlpriv = rtl_priv(hw); 2120 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2121 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2122 int ret; 2123 2124 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2125 IRQF_SHARED, KBUILD_MODNAME, hw); 2126 if (ret < 0) 2127 return ret; 2128 2129 rtlpci->using_msi = false; 2130 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG, 2131 "Pin-based Interrupt Mode!\n"); 2132 return 0; 2133 } 2134 2135 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw) 2136 { 2137 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2138 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2139 int ret; 2140 2141 if (rtlpci->msi_support) { 2142 ret = rtl_pci_intr_mode_msi(hw); 2143 if (ret < 0) 2144 ret = rtl_pci_intr_mode_legacy(hw); 2145 } else { 2146 ret = rtl_pci_intr_mode_legacy(hw); 2147 } 2148 return ret; 2149 } 2150 2151 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64) 2152 { 2153 u8 value; 2154 2155 pci_read_config_byte(pdev, 0x719, &value); 2156 2157 /* 0x719 Bit5 is DMA64 bit fetch. */ 2158 if (dma64) 2159 value |= BIT(5); 2160 else 2161 value &= ~BIT(5); 2162 2163 pci_write_config_byte(pdev, 0x719, value); 2164 } 2165 2166 int rtl_pci_probe(struct pci_dev *pdev, 2167 const struct pci_device_id *id) 2168 { 2169 struct ieee80211_hw *hw = NULL; 2170 2171 struct rtl_priv *rtlpriv = NULL; 2172 struct rtl_pci_priv *pcipriv = NULL; 2173 struct rtl_pci *rtlpci; 2174 unsigned long pmem_start, pmem_len, pmem_flags; 2175 int err; 2176 2177 err = pci_enable_device(pdev); 2178 if (err) { 2179 WARN_ONCE(true, "%s : Cannot enable new PCI device\n", 2180 pci_name(pdev)); 2181 return err; 2182 } 2183 2184 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 && 2185 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 2186 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { 2187 WARN_ONCE(true, 2188 "Unable to obtain 64bit DMA for consistent allocations\n"); 2189 err = -ENOMEM; 2190 goto fail1; 2191 } 2192 2193 platform_enable_dma64(pdev, true); 2194 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 2195 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 2196 WARN_ONCE(true, 2197 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n"); 2198 err = -ENOMEM; 2199 goto fail1; 2200 } 2201 2202 platform_enable_dma64(pdev, false); 2203 } 2204 2205 pci_set_master(pdev); 2206 2207 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) + 2208 sizeof(struct rtl_priv), &rtl_ops); 2209 if (!hw) { 2210 WARN_ONCE(true, 2211 "%s : ieee80211 alloc failed\n", pci_name(pdev)); 2212 err = -ENOMEM; 2213 goto fail1; 2214 } 2215 2216 SET_IEEE80211_DEV(hw, &pdev->dev); 2217 pci_set_drvdata(pdev, hw); 2218 2219 rtlpriv = hw->priv; 2220 rtlpriv->hw = hw; 2221 pcipriv = (void *)rtlpriv->priv; 2222 pcipriv->dev.pdev = pdev; 2223 init_completion(&rtlpriv->firmware_loading_complete); 2224 /*proximity init here*/ 2225 rtlpriv->proximity.proxim_on = false; 2226 2227 pcipriv = (void *)rtlpriv->priv; 2228 pcipriv->dev.pdev = pdev; 2229 2230 /* init cfg & intf_ops */ 2231 rtlpriv->rtlhal.interface = INTF_PCI; 2232 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data); 2233 rtlpriv->intf_ops = &rtl_pci_ops; 2234 rtlpriv->glb_var = &rtl_global_var; 2235 2236 /* MEM map */ 2237 err = pci_request_regions(pdev, KBUILD_MODNAME); 2238 if (err) { 2239 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n"); 2240 goto fail1; 2241 } 2242 2243 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id); 2244 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id); 2245 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id); 2246 2247 /*shared mem start */ 2248 rtlpriv->io.pci_mem_start = 2249 (unsigned long)pci_iomap(pdev, 2250 rtlpriv->cfg->bar_id, pmem_len); 2251 if (rtlpriv->io.pci_mem_start == 0) { 2252 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n"); 2253 err = -ENOMEM; 2254 goto fail2; 2255 } 2256 2257 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2258 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", 2259 pmem_start, pmem_len, pmem_flags, 2260 rtlpriv->io.pci_mem_start); 2261 2262 /* Disable Clk Request */ 2263 pci_write_config_byte(pdev, 0x81, 0); 2264 /* leave D3 mode */ 2265 pci_write_config_byte(pdev, 0x44, 0); 2266 pci_write_config_byte(pdev, 0x04, 0x06); 2267 pci_write_config_byte(pdev, 0x04, 0x07); 2268 2269 /* find adapter */ 2270 if (!_rtl_pci_find_adapter(pdev, hw)) { 2271 err = -ENODEV; 2272 goto fail2; 2273 } 2274 2275 /* Init IO handler */ 2276 _rtl_pci_io_handler_init(&pdev->dev, hw); 2277 2278 /*like read eeprom and so on */ 2279 rtlpriv->cfg->ops->read_eeprom_info(hw); 2280 2281 if (rtlpriv->cfg->ops->init_sw_vars(hw)) { 2282 pr_err("Can't init_sw_vars\n"); 2283 err = -ENODEV; 2284 goto fail3; 2285 } 2286 rtlpriv->cfg->ops->init_sw_leds(hw); 2287 2288 /*aspm */ 2289 rtl_pci_init_aspm(hw); 2290 2291 /* Init mac80211 sw */ 2292 err = rtl_init_core(hw); 2293 if (err) { 2294 pr_err("Can't allocate sw for mac80211\n"); 2295 goto fail3; 2296 } 2297 2298 /* Init PCI sw */ 2299 err = rtl_pci_init(hw, pdev); 2300 if (err) { 2301 pr_err("Failed to init PCI\n"); 2302 goto fail3; 2303 } 2304 2305 err = ieee80211_register_hw(hw); 2306 if (err) { 2307 pr_err("Can't register mac80211 hw.\n"); 2308 err = -ENODEV; 2309 goto fail3; 2310 } 2311 rtlpriv->mac80211.mac80211_registered = 1; 2312 2313 /*init rfkill */ 2314 rtl_init_rfkill(hw); /* Init PCI sw */ 2315 2316 rtlpci = rtl_pcidev(pcipriv); 2317 err = rtl_pci_intr_mode_decide(hw); 2318 if (err) { 2319 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2320 "%s: failed to register IRQ handler\n", 2321 wiphy_name(hw->wiphy)); 2322 goto fail3; 2323 } 2324 rtlpci->irq_alloc = 1; 2325 2326 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2327 return 0; 2328 2329 fail3: 2330 pci_set_drvdata(pdev, NULL); 2331 rtl_deinit_core(hw); 2332 2333 fail2: 2334 if (rtlpriv->io.pci_mem_start != 0) 2335 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2336 2337 pci_release_regions(pdev); 2338 complete(&rtlpriv->firmware_loading_complete); 2339 2340 fail1: 2341 if (hw) 2342 ieee80211_free_hw(hw); 2343 pci_disable_device(pdev); 2344 2345 return err; 2346 2347 } 2348 EXPORT_SYMBOL(rtl_pci_probe); 2349 2350 void rtl_pci_disconnect(struct pci_dev *pdev) 2351 { 2352 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2353 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2354 struct rtl_priv *rtlpriv = rtl_priv(hw); 2355 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2356 struct rtl_mac *rtlmac = rtl_mac(rtlpriv); 2357 2358 /* just in case driver is removed before firmware callback */ 2359 wait_for_completion(&rtlpriv->firmware_loading_complete); 2360 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2361 2362 /*ieee80211_unregister_hw will call ops_stop */ 2363 if (rtlmac->mac80211_registered == 1) { 2364 ieee80211_unregister_hw(hw); 2365 rtlmac->mac80211_registered = 0; 2366 } else { 2367 rtl_deinit_deferred_work(hw); 2368 rtlpriv->intf_ops->adapter_stop(hw); 2369 } 2370 rtlpriv->cfg->ops->disable_interrupt(hw); 2371 2372 /*deinit rfkill */ 2373 rtl_deinit_rfkill(hw); 2374 2375 rtl_pci_deinit(hw); 2376 rtl_deinit_core(hw); 2377 rtlpriv->cfg->ops->deinit_sw_vars(hw); 2378 2379 if (rtlpci->irq_alloc) { 2380 free_irq(rtlpci->pdev->irq, hw); 2381 rtlpci->irq_alloc = 0; 2382 } 2383 2384 if (rtlpci->using_msi) 2385 pci_disable_msi(rtlpci->pdev); 2386 2387 list_del(&rtlpriv->list); 2388 if (rtlpriv->io.pci_mem_start != 0) { 2389 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2390 pci_release_regions(pdev); 2391 } 2392 2393 pci_disable_device(pdev); 2394 2395 rtl_pci_disable_aspm(hw); 2396 2397 pci_set_drvdata(pdev, NULL); 2398 2399 ieee80211_free_hw(hw); 2400 } 2401 EXPORT_SYMBOL(rtl_pci_disconnect); 2402 2403 #ifdef CONFIG_PM_SLEEP 2404 /*************************************** 2405 kernel pci power state define: 2406 PCI_D0 ((pci_power_t __force) 0) 2407 PCI_D1 ((pci_power_t __force) 1) 2408 PCI_D2 ((pci_power_t __force) 2) 2409 PCI_D3hot ((pci_power_t __force) 3) 2410 PCI_D3cold ((pci_power_t __force) 4) 2411 PCI_UNKNOWN ((pci_power_t __force) 5) 2412 2413 This function is called when system 2414 goes into suspend state mac80211 will 2415 call rtl_mac_stop() from the mac80211 2416 suspend function first, So there is 2417 no need to call hw_disable here. 2418 ****************************************/ 2419 int rtl_pci_suspend(struct device *dev) 2420 { 2421 struct pci_dev *pdev = to_pci_dev(dev); 2422 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2423 struct rtl_priv *rtlpriv = rtl_priv(hw); 2424 2425 rtlpriv->cfg->ops->hw_suspend(hw); 2426 rtl_deinit_rfkill(hw); 2427 2428 return 0; 2429 } 2430 EXPORT_SYMBOL(rtl_pci_suspend); 2431 2432 int rtl_pci_resume(struct device *dev) 2433 { 2434 struct pci_dev *pdev = to_pci_dev(dev); 2435 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2436 struct rtl_priv *rtlpriv = rtl_priv(hw); 2437 2438 rtlpriv->cfg->ops->hw_resume(hw); 2439 rtl_init_rfkill(hw); 2440 return 0; 2441 } 2442 EXPORT_SYMBOL(rtl_pci_resume); 2443 #endif /* CONFIG_PM_SLEEP */ 2444 2445 const struct rtl_intf_ops rtl_pci_ops = { 2446 .read_efuse_byte = read_efuse_byte, 2447 .adapter_start = rtl_pci_start, 2448 .adapter_stop = rtl_pci_stop, 2449 .check_buddy_priv = rtl_pci_check_buddy_priv, 2450 .adapter_tx = rtl_pci_tx, 2451 .flush = rtl_pci_flush, 2452 .reset_trx_ring = rtl_pci_reset_trx_ring, 2453 .waitq_insert = rtl_pci_tx_chk_waitq_insert, 2454 2455 .disable_aspm = rtl_pci_disable_aspm, 2456 .enable_aspm = rtl_pci_enable_aspm, 2457 }; 2458