1 /****************************************************************************** 2 * 3 * Copyright(c) 2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 /************************************************************** 26 * Description: 27 * 28 * This file is for RTL8192E Co-exist mechanism 29 * 30 * History 31 * 2012/11/15 Cosa first check in. 32 * 33 **************************************************************/ 34 35 /************************************************************** 36 * include files 37 **************************************************************/ 38 #include "halbt_precomp.h" 39 /************************************************************** 40 * Global variables, these are static variables 41 **************************************************************/ 42 static struct coex_dm_8192e_2ant glcoex_dm_8192e_2ant; 43 static struct coex_dm_8192e_2ant *coex_dm = &glcoex_dm_8192e_2ant; 44 static struct coex_sta_8192e_2ant glcoex_sta_8192e_2ant; 45 static struct coex_sta_8192e_2ant *coex_sta = &glcoex_sta_8192e_2ant; 46 47 static const char *const GLBtInfoSrc8192e2Ant[] = { 48 "BT Info[wifi fw]", 49 "BT Info[bt rsp]", 50 "BT Info[bt auto report]", 51 }; 52 53 static u32 glcoex_ver_date_8192e_2ant = 20130902; 54 static u32 glcoex_ver_8192e_2ant = 0x34; 55 56 /************************************************************** 57 * local function proto type if needed 58 **************************************************************/ 59 /************************************************************** 60 * local function start with halbtc8192e2ant_ 61 **************************************************************/ 62 static u8 halbtc8192e2ant_btrssi_state(struct btc_coexist *btcoexist, 63 u8 level_num, u8 rssi_thresh, 64 u8 rssi_thresh1) 65 { 66 struct rtl_priv *rtlpriv = btcoexist->adapter; 67 int btrssi = 0; 68 u8 btrssi_state = coex_sta->pre_bt_rssi_state; 69 70 btrssi = coex_sta->bt_rssi; 71 72 if (level_num == 2) { 73 if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || 74 (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { 75 if (btrssi >= 76 (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) 77 btrssi_state = BTC_RSSI_STATE_HIGH; 78 else 79 btrssi_state = BTC_RSSI_STATE_STAY_LOW; 80 } else { 81 if (btrssi < rssi_thresh) 82 btrssi_state = BTC_RSSI_STATE_LOW; 83 else 84 btrssi_state = BTC_RSSI_STATE_STAY_HIGH; 85 } 86 } else if (level_num == 3) { 87 if (rssi_thresh > rssi_thresh1) { 88 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 89 "[BTCoex], BT Rssi thresh error!!\n"); 90 return coex_sta->pre_bt_rssi_state; 91 } 92 if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || 93 (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { 94 if (btrssi >= 95 (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) 96 btrssi_state = BTC_RSSI_STATE_MEDIUM; 97 else 98 btrssi_state = BTC_RSSI_STATE_STAY_LOW; 99 } else if ((coex_sta->pre_bt_rssi_state == 100 BTC_RSSI_STATE_MEDIUM) || 101 (coex_sta->pre_bt_rssi_state == 102 BTC_RSSI_STATE_STAY_MEDIUM)) { 103 if (btrssi >= (rssi_thresh1 + 104 BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) 105 btrssi_state = BTC_RSSI_STATE_HIGH; 106 else if (btrssi < rssi_thresh) 107 btrssi_state = BTC_RSSI_STATE_LOW; 108 else 109 btrssi_state = BTC_RSSI_STATE_STAY_MEDIUM; 110 } else { 111 if (btrssi < rssi_thresh1) 112 btrssi_state = BTC_RSSI_STATE_MEDIUM; 113 else 114 btrssi_state = BTC_RSSI_STATE_STAY_HIGH; 115 } 116 } 117 118 coex_sta->pre_bt_rssi_state = btrssi_state; 119 120 return btrssi_state; 121 } 122 123 static u8 halbtc8192e2ant_wifirssi_state(struct btc_coexist *btcoexist, 124 u8 index, u8 level_num, u8 rssi_thresh, 125 u8 rssi_thresh1) 126 { 127 struct rtl_priv *rtlpriv = btcoexist->adapter; 128 int wifirssi = 0; 129 u8 wifirssi_state = coex_sta->pre_wifi_rssi_state[index]; 130 131 btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifirssi); 132 133 if (level_num == 2) { 134 if ((coex_sta->pre_wifi_rssi_state[index] == 135 BTC_RSSI_STATE_LOW) || 136 (coex_sta->pre_wifi_rssi_state[index] == 137 BTC_RSSI_STATE_STAY_LOW)) { 138 if (wifirssi >= (rssi_thresh + 139 BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) 140 wifirssi_state = BTC_RSSI_STATE_HIGH; 141 else 142 wifirssi_state = BTC_RSSI_STATE_STAY_LOW; 143 } else { 144 if (wifirssi < rssi_thresh) 145 wifirssi_state = BTC_RSSI_STATE_LOW; 146 else 147 wifirssi_state = BTC_RSSI_STATE_STAY_HIGH; 148 } 149 } else if (level_num == 3) { 150 if (rssi_thresh > rssi_thresh1) { 151 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 152 "[BTCoex], wifi RSSI thresh error!!\n"); 153 return coex_sta->pre_wifi_rssi_state[index]; 154 } 155 156 if ((coex_sta->pre_wifi_rssi_state[index] == 157 BTC_RSSI_STATE_LOW) || 158 (coex_sta->pre_wifi_rssi_state[index] == 159 BTC_RSSI_STATE_STAY_LOW)) { 160 if (wifirssi >= (rssi_thresh + 161 BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) 162 wifirssi_state = BTC_RSSI_STATE_MEDIUM; 163 else 164 wifirssi_state = BTC_RSSI_STATE_STAY_LOW; 165 } else if ((coex_sta->pre_wifi_rssi_state[index] == 166 BTC_RSSI_STATE_MEDIUM) || 167 (coex_sta->pre_wifi_rssi_state[index] == 168 BTC_RSSI_STATE_STAY_MEDIUM)) { 169 if (wifirssi >= (rssi_thresh1 + 170 BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) 171 wifirssi_state = BTC_RSSI_STATE_HIGH; 172 else if (wifirssi < rssi_thresh) 173 wifirssi_state = BTC_RSSI_STATE_LOW; 174 else 175 wifirssi_state = BTC_RSSI_STATE_STAY_MEDIUM; 176 } else { 177 if (wifirssi < rssi_thresh1) 178 wifirssi_state = BTC_RSSI_STATE_MEDIUM; 179 else 180 wifirssi_state = BTC_RSSI_STATE_STAY_HIGH; 181 } 182 } 183 184 coex_sta->pre_wifi_rssi_state[index] = wifirssi_state; 185 186 return wifirssi_state; 187 } 188 189 static void btc8192e2ant_monitor_bt_enable_dis(struct btc_coexist *btcoexist) 190 { 191 struct rtl_priv *rtlpriv = btcoexist->adapter; 192 static bool pre_bt_disabled; 193 static u32 bt_disable_cnt; 194 bool bt_active = true, bt_disabled = false; 195 196 /* This function check if bt is disabled */ 197 198 if (coex_sta->high_priority_tx == 0 && 199 coex_sta->high_priority_rx == 0 && 200 coex_sta->low_priority_tx == 0 && 201 coex_sta->low_priority_rx == 0) 202 bt_active = false; 203 204 if (coex_sta->high_priority_tx == 0xffff && 205 coex_sta->high_priority_rx == 0xffff && 206 coex_sta->low_priority_tx == 0xffff && 207 coex_sta->low_priority_rx == 0xffff) 208 bt_active = false; 209 210 if (bt_active) { 211 bt_disable_cnt = 0; 212 bt_disabled = false; 213 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, 214 &bt_disabled); 215 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 216 "[BTCoex], BT is enabled !!\n"); 217 } else { 218 bt_disable_cnt++; 219 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 220 "[BTCoex], bt all counters = 0, %d times!!\n", 221 bt_disable_cnt); 222 if (bt_disable_cnt >= 2) { 223 bt_disabled = true; 224 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, 225 &bt_disabled); 226 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 227 "[BTCoex], BT is disabled !!\n"); 228 } 229 } 230 if (pre_bt_disabled != bt_disabled) { 231 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 232 "[BTCoex], BT is from %s to %s!!\n", 233 (pre_bt_disabled ? "disabled" : "enabled"), 234 (bt_disabled ? "disabled" : "enabled")); 235 pre_bt_disabled = bt_disabled; 236 } 237 } 238 239 static u32 halbtc8192e2ant_decidera_mask(struct btc_coexist *btcoexist, 240 u8 sstype, u32 ra_masktype) 241 { 242 u32 disra_mask = 0x0; 243 244 switch (ra_masktype) { 245 case 0: /* normal mode */ 246 if (sstype == 2) 247 disra_mask = 0x0; /* enable 2ss */ 248 else 249 disra_mask = 0xfff00000;/* disable 2ss */ 250 break; 251 case 1: /* disable cck 1/2 */ 252 if (sstype == 2) 253 disra_mask = 0x00000003;/* enable 2ss */ 254 else 255 disra_mask = 0xfff00003;/* disable 2ss */ 256 break; 257 case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ 258 if (sstype == 2) 259 disra_mask = 0x0001f1f7;/* enable 2ss */ 260 else 261 disra_mask = 0xfff1f1f7;/* disable 2ss */ 262 break; 263 default: 264 break; 265 } 266 267 return disra_mask; 268 } 269 270 static void halbtc8192e2ant_Updatera_mask(struct btc_coexist *btcoexist, 271 bool force_exec, u32 dis_ratemask) 272 { 273 coex_dm->curra_mask = dis_ratemask; 274 275 if (force_exec || (coex_dm->prera_mask != coex_dm->curra_mask)) 276 btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_ra_mask, 277 &coex_dm->curra_mask); 278 coex_dm->prera_mask = coex_dm->curra_mask; 279 } 280 281 static void btc8192e2ant_autorate_fallback_retry(struct btc_coexist *btcoexist, 282 bool force_exec, u8 type) 283 { 284 bool wifi_under_bmode = false; 285 286 coex_dm->cur_arfrtype = type; 287 288 if (force_exec || (coex_dm->pre_arfrtype != coex_dm->cur_arfrtype)) { 289 switch (coex_dm->cur_arfrtype) { 290 case 0: /* normal mode */ 291 btcoexist->btc_write_4byte(btcoexist, 0x430, 292 coex_dm->backup_arfr_cnt1); 293 btcoexist->btc_write_4byte(btcoexist, 0x434, 294 coex_dm->backup_arfr_cnt2); 295 break; 296 case 1: 297 btcoexist->btc_get(btcoexist, 298 BTC_GET_BL_WIFI_UNDER_B_MODE, 299 &wifi_under_bmode); 300 if (wifi_under_bmode) { 301 btcoexist->btc_write_4byte(btcoexist, 0x430, 302 0x0); 303 btcoexist->btc_write_4byte(btcoexist, 0x434, 304 0x01010101); 305 } else { 306 btcoexist->btc_write_4byte(btcoexist, 0x430, 307 0x0); 308 btcoexist->btc_write_4byte(btcoexist, 0x434, 309 0x04030201); 310 } 311 break; 312 default: 313 break; 314 } 315 } 316 317 coex_dm->pre_arfrtype = coex_dm->cur_arfrtype; 318 } 319 320 static void halbtc8192e2ant_retrylimit(struct btc_coexist *btcoexist, 321 bool force_exec, u8 type) 322 { 323 coex_dm->cur_retrylimit_type = type; 324 325 if (force_exec || (coex_dm->pre_retrylimit_type != 326 coex_dm->cur_retrylimit_type)) { 327 switch (coex_dm->cur_retrylimit_type) { 328 case 0: /* normal mode */ 329 btcoexist->btc_write_2byte(btcoexist, 0x42a, 330 coex_dm->backup_retrylimit); 331 break; 332 case 1: /* retry limit = 8 */ 333 btcoexist->btc_write_2byte(btcoexist, 0x42a, 334 0x0808); 335 break; 336 default: 337 break; 338 } 339 } 340 341 coex_dm->pre_retrylimit_type = coex_dm->cur_retrylimit_type; 342 } 343 344 static void halbtc8192e2ant_ampdu_maxtime(struct btc_coexist *btcoexist, 345 bool force_exec, u8 type) 346 { 347 coex_dm->cur_ampdutime_type = type; 348 349 if (force_exec || (coex_dm->pre_ampdutime_type != 350 coex_dm->cur_ampdutime_type)) { 351 switch (coex_dm->cur_ampdutime_type) { 352 case 0: /* normal mode */ 353 btcoexist->btc_write_1byte(btcoexist, 0x456, 354 coex_dm->backup_ampdu_maxtime); 355 break; 356 case 1: /* AMPDU timw = 0x38 * 32us */ 357 btcoexist->btc_write_1byte(btcoexist, 0x456, 0x38); 358 break; 359 default: 360 break; 361 } 362 } 363 364 coex_dm->pre_ampdutime_type = coex_dm->cur_ampdutime_type; 365 } 366 367 static void halbtc8192e2ant_limited_tx(struct btc_coexist *btcoexist, 368 bool force_exec, u8 ra_masktype, 369 u8 arfr_type, u8 retrylimit_type, 370 u8 ampdutime_type) 371 { 372 u32 disra_mask = 0x0; 373 374 coex_dm->curra_masktype = ra_masktype; 375 disra_mask = halbtc8192e2ant_decidera_mask(btcoexist, 376 coex_dm->cur_sstype, 377 ra_masktype); 378 halbtc8192e2ant_Updatera_mask(btcoexist, force_exec, disra_mask); 379 btc8192e2ant_autorate_fallback_retry(btcoexist, force_exec, arfr_type); 380 halbtc8192e2ant_retrylimit(btcoexist, force_exec, retrylimit_type); 381 halbtc8192e2ant_ampdu_maxtime(btcoexist, force_exec, ampdutime_type); 382 } 383 384 static void halbtc8192e2ant_limited_rx(struct btc_coexist *btcoexist, 385 bool force_exec, bool rej_ap_agg_pkt, 386 bool bt_ctrl_agg_buf_size, 387 u8 agg_buf_size) 388 { 389 bool reject_rx_agg = rej_ap_agg_pkt; 390 bool bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; 391 u8 rx_agg_size = agg_buf_size; 392 393 /********************************************* 394 * Rx Aggregation related setting 395 *********************************************/ 396 btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, 397 &reject_rx_agg); 398 /* decide BT control aggregation buf size or not */ 399 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, 400 &bt_ctrl_rx_agg_size); 401 /* aggregation buf size, only work 402 * when BT control Rx aggregation size. 403 */ 404 btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); 405 /* real update aggregation setting */ 406 btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); 407 } 408 409 static void halbtc8192e2ant_monitor_bt_ctr(struct btc_coexist *btcoexist) 410 { 411 struct rtl_priv *rtlpriv = btcoexist->adapter; 412 u32 reg_hp_txrx, reg_lp_txrx, u32tmp; 413 u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; 414 415 reg_hp_txrx = 0x770; 416 reg_lp_txrx = 0x774; 417 418 u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); 419 reg_hp_tx = u32tmp & MASKLWORD; 420 reg_hp_rx = (u32tmp & MASKHWORD)>>16; 421 422 u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); 423 reg_lp_tx = u32tmp & MASKLWORD; 424 reg_lp_rx = (u32tmp & MASKHWORD)>>16; 425 426 coex_sta->high_priority_tx = reg_hp_tx; 427 coex_sta->high_priority_rx = reg_hp_rx; 428 coex_sta->low_priority_tx = reg_lp_tx; 429 coex_sta->low_priority_rx = reg_lp_rx; 430 431 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 432 "[BTCoex] High Priority Tx/Rx (reg 0x%x) = 0x%x(%d)/0x%x(%d)\n", 433 reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx); 434 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 435 "[BTCoex] Low Priority Tx/Rx (reg 0x%x) = 0x%x(%d)/0x%x(%d)\n", 436 reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx); 437 438 /* reset counter */ 439 btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); 440 } 441 442 static void halbtc8192e2ant_querybt_info(struct btc_coexist *btcoexist) 443 { 444 struct rtl_priv *rtlpriv = btcoexist->adapter; 445 u8 h2c_parameter[1] = {0}; 446 447 coex_sta->c2h_bt_info_req_sent = true; 448 449 h2c_parameter[0] |= BIT0; /* trigger */ 450 451 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 452 "[BTCoex], Query Bt Info, FW write 0x61 = 0x%x\n", 453 h2c_parameter[0]); 454 455 btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); 456 } 457 458 static void halbtc8192e2ant_update_btlink_info(struct btc_coexist *btcoexist) 459 { 460 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; 461 bool bt_hson = false; 462 463 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hson); 464 465 bt_link_info->bt_link_exist = coex_sta->bt_link_exist; 466 bt_link_info->sco_exist = coex_sta->sco_exist; 467 bt_link_info->a2dp_exist = coex_sta->a2dp_exist; 468 bt_link_info->pan_exist = coex_sta->pan_exist; 469 bt_link_info->hid_exist = coex_sta->hid_exist; 470 471 /* work around for HS mode. */ 472 if (bt_hson) { 473 bt_link_info->pan_exist = true; 474 bt_link_info->bt_link_exist = true; 475 } 476 477 /* check if Sco only */ 478 if (bt_link_info->sco_exist && 479 !bt_link_info->a2dp_exist && 480 !bt_link_info->pan_exist && 481 !bt_link_info->hid_exist) 482 bt_link_info->sco_only = true; 483 else 484 bt_link_info->sco_only = false; 485 486 /* check if A2dp only */ 487 if (!bt_link_info->sco_exist && 488 bt_link_info->a2dp_exist && 489 !bt_link_info->pan_exist && 490 !bt_link_info->hid_exist) 491 bt_link_info->a2dp_only = true; 492 else 493 bt_link_info->a2dp_only = false; 494 495 /* check if Pan only */ 496 if (!bt_link_info->sco_exist && 497 !bt_link_info->a2dp_exist && 498 bt_link_info->pan_exist && 499 !bt_link_info->hid_exist) 500 bt_link_info->pan_only = true; 501 else 502 bt_link_info->pan_only = false; 503 504 /* check if Hid only */ 505 if (!bt_link_info->sco_exist && 506 !bt_link_info->a2dp_exist && 507 !bt_link_info->pan_exist && 508 bt_link_info->hid_exist) 509 bt_link_info->hid_only = true; 510 else 511 bt_link_info->hid_only = false; 512 } 513 514 static u8 halbtc8192e2ant_action_algorithm(struct btc_coexist *btcoexist) 515 { 516 struct rtl_priv *rtlpriv = btcoexist->adapter; 517 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; 518 struct btc_stack_info *stack_info = &btcoexist->stack_info; 519 bool bt_hson = false; 520 u8 algorithm = BT_8192E_2ANT_COEX_ALGO_UNDEFINED; 521 u8 numdiffprofile = 0; 522 523 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hson); 524 525 if (!bt_link_info->bt_link_exist) { 526 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 527 "No BT link exists!!!\n"); 528 return algorithm; 529 } 530 531 if (bt_link_info->sco_exist) 532 numdiffprofile++; 533 if (bt_link_info->hid_exist) 534 numdiffprofile++; 535 if (bt_link_info->pan_exist) 536 numdiffprofile++; 537 if (bt_link_info->a2dp_exist) 538 numdiffprofile++; 539 540 if (numdiffprofile == 1) { 541 if (bt_link_info->sco_exist) { 542 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 543 "SCO only\n"); 544 algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; 545 } else { 546 if (bt_link_info->hid_exist) { 547 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 548 "HID only\n"); 549 algorithm = BT_8192E_2ANT_COEX_ALGO_HID; 550 } else if (bt_link_info->a2dp_exist) { 551 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 552 "A2DP only\n"); 553 algorithm = BT_8192E_2ANT_COEX_ALGO_A2DP; 554 } else if (bt_link_info->pan_exist) { 555 if (bt_hson) { 556 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 557 DBG_LOUD, 558 "PAN(HS) only\n"); 559 algorithm = 560 BT_8192E_2ANT_COEX_ALGO_PANHS; 561 } else { 562 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 563 DBG_LOUD, 564 "PAN(EDR) only\n"); 565 algorithm = 566 BT_8192E_2ANT_COEX_ALGO_PANEDR; 567 } 568 } 569 } 570 } else if (numdiffprofile == 2) { 571 if (bt_link_info->sco_exist) { 572 if (bt_link_info->hid_exist) { 573 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 574 "SCO + HID\n"); 575 algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; 576 } else if (bt_link_info->a2dp_exist) { 577 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 578 "SCO + A2DP ==> SCO\n"); 579 algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; 580 } else if (bt_link_info->pan_exist) { 581 if (bt_hson) { 582 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 583 DBG_LOUD, 584 "SCO + PAN(HS)\n"); 585 algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; 586 } else { 587 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 588 DBG_LOUD, 589 "SCO + PAN(EDR)\n"); 590 algorithm = 591 BT_8192E_2ANT_COEX_ALGO_SCO_PAN; 592 } 593 } 594 } else { 595 if (bt_link_info->hid_exist && 596 bt_link_info->a2dp_exist) { 597 if (stack_info->num_of_hid >= 2) { 598 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 599 DBG_LOUD, 600 "HID*2 + A2DP\n"); 601 algorithm = 602 BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR; 603 } else { 604 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 605 DBG_LOUD, 606 "HID + A2DP\n"); 607 algorithm = 608 BT_8192E_2ANT_COEX_ALGO_HID_A2DP; 609 } 610 } else if (bt_link_info->hid_exist && 611 bt_link_info->pan_exist) { 612 if (bt_hson) { 613 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 614 DBG_LOUD, 615 "HID + PAN(HS)\n"); 616 algorithm = BT_8192E_2ANT_COEX_ALGO_HID; 617 } else { 618 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 619 DBG_LOUD, 620 "HID + PAN(EDR)\n"); 621 algorithm = 622 BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; 623 } 624 } else if (bt_link_info->pan_exist && 625 bt_link_info->a2dp_exist) { 626 if (bt_hson) { 627 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 628 DBG_LOUD, 629 "A2DP + PAN(HS)\n"); 630 algorithm = 631 BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS; 632 } else { 633 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 634 DBG_LOUD, 635 "A2DP + PAN(EDR)\n"); 636 algorithm = 637 BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP; 638 } 639 } 640 } 641 } else if (numdiffprofile == 3) { 642 if (bt_link_info->sco_exist) { 643 if (bt_link_info->hid_exist && 644 bt_link_info->a2dp_exist) { 645 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 646 "SCO + HID + A2DP ==> HID\n"); 647 algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; 648 } else if (bt_link_info->hid_exist && 649 bt_link_info->pan_exist) { 650 if (bt_hson) { 651 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 652 DBG_LOUD, 653 "SCO + HID + PAN(HS)\n"); 654 algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; 655 } else { 656 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 657 DBG_LOUD, 658 "SCO + HID + PAN(EDR)\n"); 659 algorithm = 660 BT_8192E_2ANT_COEX_ALGO_SCO_PAN; 661 } 662 } else if (bt_link_info->pan_exist && 663 bt_link_info->a2dp_exist) { 664 if (bt_hson) { 665 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 666 DBG_LOUD, 667 "SCO + A2DP + PAN(HS)\n"); 668 algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; 669 } else { 670 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 671 DBG_LOUD, 672 "SCO + A2DP + PAN(EDR)\n"); 673 algorithm = 674 BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; 675 } 676 } 677 } else { 678 if (bt_link_info->hid_exist && 679 bt_link_info->pan_exist && 680 bt_link_info->a2dp_exist) { 681 if (bt_hson) { 682 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 683 DBG_LOUD, 684 "HID + A2DP + PAN(HS)\n"); 685 algorithm = 686 BT_8192E_2ANT_COEX_ALGO_HID_A2DP; 687 } else { 688 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 689 DBG_LOUD, 690 "HID + A2DP + PAN(EDR)\n"); 691 algorithm = 692 BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR; 693 } 694 } 695 } 696 } else if (numdiffprofile >= 3) { 697 if (bt_link_info->sco_exist) { 698 if (bt_link_info->hid_exist && 699 bt_link_info->pan_exist && 700 bt_link_info->a2dp_exist) { 701 if (bt_hson) { 702 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 703 DBG_LOUD, 704 "ErrorSCO+HID+A2DP+PAN(HS)\n"); 705 706 } else { 707 RT_TRACE(rtlpriv, COMP_BT_COEXIST, 708 DBG_LOUD, 709 "SCO+HID+A2DP+PAN(EDR)\n"); 710 algorithm = 711 BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; 712 } 713 } 714 } 715 } 716 717 return algorithm; 718 } 719 720 static void halbtc8192e2ant_setfw_dac_swinglevel(struct btc_coexist *btcoexist, 721 u8 dac_swinglvl) 722 { 723 struct rtl_priv *rtlpriv = btcoexist->adapter; 724 u8 h2c_parameter[1] = {0}; 725 726 /* There are several type of dacswing 727 * 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 728 */ 729 h2c_parameter[0] = dac_swinglvl; 730 731 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 732 "[BTCoex], Set Dac Swing Level = 0x%x\n", dac_swinglvl); 733 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 734 "[BTCoex], FW write 0x64 = 0x%x\n", h2c_parameter[0]); 735 736 btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); 737 } 738 739 static void halbtc8192e2ant_set_fwdec_btpwr(struct btc_coexist *btcoexist, 740 u8 dec_btpwr_lvl) 741 { 742 struct rtl_priv *rtlpriv = btcoexist->adapter; 743 u8 h2c_parameter[1] = {0}; 744 745 h2c_parameter[0] = dec_btpwr_lvl; 746 747 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 748 "[BTCoex] decrease Bt Power level = %d, FW write 0x62 = 0x%x\n", 749 dec_btpwr_lvl, h2c_parameter[0]); 750 751 btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); 752 } 753 754 static void halbtc8192e2ant_dec_btpwr(struct btc_coexist *btcoexist, 755 bool force_exec, u8 dec_btpwr_lvl) 756 { 757 struct rtl_priv *rtlpriv = btcoexist->adapter; 758 759 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 760 "[BTCoex], %s Dec BT power level = %d\n", 761 force_exec ? "force to" : "", dec_btpwr_lvl); 762 coex_dm->cur_dec_bt_pwr = dec_btpwr_lvl; 763 764 if (!force_exec) { 765 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 766 "[BTCoex], preBtDecPwrLvl=%d, curBtDecPwrLvl=%d\n", 767 coex_dm->pre_dec_bt_pwr, coex_dm->cur_dec_bt_pwr); 768 } 769 halbtc8192e2ant_set_fwdec_btpwr(btcoexist, coex_dm->cur_dec_bt_pwr); 770 771 coex_dm->pre_dec_bt_pwr = coex_dm->cur_dec_bt_pwr; 772 } 773 774 static void halbtc8192e2ant_set_bt_autoreport(struct btc_coexist *btcoexist, 775 bool enable_autoreport) 776 { 777 struct rtl_priv *rtlpriv = btcoexist->adapter; 778 u8 h2c_parameter[1] = {0}; 779 780 h2c_parameter[0] = 0; 781 782 if (enable_autoreport) 783 h2c_parameter[0] |= BIT0; 784 785 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 786 "[BTCoex], BT FW auto report : %s, FW write 0x68 = 0x%x\n", 787 (enable_autoreport ? "Enabled!!" : "Disabled!!"), 788 h2c_parameter[0]); 789 790 btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); 791 } 792 793 static void halbtc8192e2ant_bt_autoreport(struct btc_coexist *btcoexist, 794 bool force_exec, 795 bool enable_autoreport) 796 { 797 struct rtl_priv *rtlpriv = btcoexist->adapter; 798 799 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 800 "[BTCoex], %s BT Auto report = %s\n", 801 (force_exec ? "force to" : ""), 802 ((enable_autoreport) ? "Enabled" : "Disabled")); 803 coex_dm->cur_bt_auto_report = enable_autoreport; 804 805 if (!force_exec) { 806 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 807 "[BTCoex] bPreBtAutoReport=%d, bCurBtAutoReport=%d\n", 808 coex_dm->pre_bt_auto_report, 809 coex_dm->cur_bt_auto_report); 810 811 if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) 812 return; 813 } 814 halbtc8192e2ant_set_bt_autoreport(btcoexist, 815 coex_dm->cur_bt_auto_report); 816 817 coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; 818 } 819 820 static void halbtc8192e2ant_fw_dac_swinglvl(struct btc_coexist *btcoexist, 821 bool force_exec, u8 fw_dac_swinglvl) 822 { 823 struct rtl_priv *rtlpriv = btcoexist->adapter; 824 825 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 826 "[BTCoex], %s set FW Dac Swing level = %d\n", 827 (force_exec ? "force to" : ""), fw_dac_swinglvl); 828 coex_dm->cur_fw_dac_swing_lvl = fw_dac_swinglvl; 829 830 if (!force_exec) { 831 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 832 "[BTCoex] preFwDacSwingLvl=%d, curFwDacSwingLvl=%d\n", 833 coex_dm->pre_fw_dac_swing_lvl, 834 coex_dm->cur_fw_dac_swing_lvl); 835 836 if (coex_dm->pre_fw_dac_swing_lvl == 837 coex_dm->cur_fw_dac_swing_lvl) 838 return; 839 } 840 841 halbtc8192e2ant_setfw_dac_swinglevel(btcoexist, 842 coex_dm->cur_fw_dac_swing_lvl); 843 844 coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; 845 } 846 847 static void btc8192e2ant_set_sw_rf_rx_lpf_corner(struct btc_coexist *btcoexist, 848 bool rx_rf_shrink_on) 849 { 850 struct rtl_priv *rtlpriv = btcoexist->adapter; 851 852 if (rx_rf_shrink_on) { 853 /* Shrink RF Rx LPF corner */ 854 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 855 "[BTCoex], Shrink RF Rx LPF corner!!\n"); 856 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 857 0xfffff, 0xffffc); 858 } else { 859 /* Resume RF Rx LPF corner 860 * After initialized, we can use coex_dm->btRf0x1eBackup 861 */ 862 if (btcoexist->initilized) { 863 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 864 "[BTCoex], Resume RF Rx LPF corner!!\n"); 865 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 866 0xfffff, 867 coex_dm->bt_rf0x1e_backup); 868 } 869 } 870 } 871 872 static void halbtc8192e2ant_rf_shrink(struct btc_coexist *btcoexist, 873 bool force_exec, bool rx_rf_shrink_on) 874 { 875 struct rtl_priv *rtlpriv = btcoexist->adapter; 876 877 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 878 "[BTCoex], %s turn Rx RF Shrink = %s\n", 879 (force_exec ? "force to" : ""), 880 ((rx_rf_shrink_on) ? "ON" : "OFF")); 881 coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on; 882 883 if (!force_exec) { 884 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 885 "[BTCoex]bPreRfRxLpfShrink=%d,bCurRfRxLpfShrink=%d\n", 886 coex_dm->pre_rf_rx_lpf_shrink, 887 coex_dm->cur_rf_rx_lpf_shrink); 888 889 if (coex_dm->pre_rf_rx_lpf_shrink == 890 coex_dm->cur_rf_rx_lpf_shrink) 891 return; 892 } 893 btc8192e2ant_set_sw_rf_rx_lpf_corner(btcoexist, 894 coex_dm->cur_rf_rx_lpf_shrink); 895 896 coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink; 897 } 898 899 static void halbtc8192e2ant_set_dac_swingreg(struct btc_coexist *btcoexist, 900 u32 level) 901 { 902 struct rtl_priv *rtlpriv = btcoexist->adapter; 903 u8 val = (u8)level; 904 905 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 906 "[BTCoex], Write SwDacSwing = 0x%x\n", level); 907 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val); 908 } 909 910 static void btc8192e2ant_setsw_full_swing(struct btc_coexist *btcoexist, 911 bool sw_dac_swingon, 912 u32 sw_dac_swinglvl) 913 { 914 if (sw_dac_swingon) 915 halbtc8192e2ant_set_dac_swingreg(btcoexist, sw_dac_swinglvl); 916 else 917 halbtc8192e2ant_set_dac_swingreg(btcoexist, 0x18); 918 } 919 920 static void halbtc8192e2ant_DacSwing(struct btc_coexist *btcoexist, 921 bool force_exec, bool dac_swingon, 922 u32 dac_swinglvl) 923 { 924 struct rtl_priv *rtlpriv = btcoexist->adapter; 925 926 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 927 "[BTCoex], %s turn DacSwing=%s, dac_swinglvl = 0x%x\n", 928 (force_exec ? "force to" : ""), 929 ((dac_swingon) ? "ON" : "OFF"), dac_swinglvl); 930 coex_dm->cur_dac_swing_on = dac_swingon; 931 coex_dm->cur_dac_swing_lvl = dac_swinglvl; 932 933 if (!force_exec) { 934 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 935 "[BTCoex], bPreDacSwingOn=%d, preDacSwingLvl = 0x%x, ", 936 coex_dm->pre_dac_swing_on, 937 coex_dm->pre_dac_swing_lvl); 938 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 939 "bCurDacSwingOn=%d, curDacSwingLvl = 0x%x\n", 940 coex_dm->cur_dac_swing_on, 941 coex_dm->cur_dac_swing_lvl); 942 943 if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) && 944 (coex_dm->pre_dac_swing_lvl == coex_dm->cur_dac_swing_lvl)) 945 return; 946 } 947 mdelay(30); 948 btc8192e2ant_setsw_full_swing(btcoexist, dac_swingon, dac_swinglvl); 949 950 coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on; 951 coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl; 952 } 953 954 static void halbtc8192e2ant_set_agc_table(struct btc_coexist *btcoexist, 955 bool agc_table_en) 956 { 957 struct rtl_priv *rtlpriv = btcoexist->adapter; 958 959 /* BB AGC Gain Table */ 960 if (agc_table_en) { 961 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 962 "[BTCoex], BB Agc Table On!\n"); 963 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x0a1A0001); 964 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x091B0001); 965 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x081C0001); 966 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x071D0001); 967 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x061E0001); 968 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x051F0001); 969 } else { 970 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 971 "[BTCoex], BB Agc Table Off!\n"); 972 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001); 973 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001); 974 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001); 975 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001); 976 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001); 977 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001); 978 } 979 } 980 981 static void halbtc8192e2ant_AgcTable(struct btc_coexist *btcoexist, 982 bool force_exec, bool agc_table_en) 983 { 984 struct rtl_priv *rtlpriv = btcoexist->adapter; 985 986 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 987 "[BTCoex], %s %s Agc Table\n", 988 (force_exec ? "force to" : ""), 989 ((agc_table_en) ? "Enable" : "Disable")); 990 coex_dm->cur_agc_table_en = agc_table_en; 991 992 if (!force_exec) { 993 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 994 "[BTCoex], bPreAgcTableEn=%d, bCurAgcTableEn=%d\n", 995 coex_dm->pre_agc_table_en, 996 coex_dm->cur_agc_table_en); 997 998 if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) 999 return; 1000 } 1001 halbtc8192e2ant_set_agc_table(btcoexist, agc_table_en); 1002 1003 coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; 1004 } 1005 1006 static void halbtc8192e2ant_set_coex_table(struct btc_coexist *btcoexist, 1007 u32 val0x6c0, u32 val0x6c4, 1008 u32 val0x6c8, u8 val0x6cc) 1009 { 1010 struct rtl_priv *rtlpriv = btcoexist->adapter; 1011 1012 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1013 "[BTCoex], set coex table, set 0x6c0 = 0x%x\n", val0x6c0); 1014 btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); 1015 1016 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1017 "[BTCoex], set coex table, set 0x6c4 = 0x%x\n", val0x6c4); 1018 btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); 1019 1020 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1021 "[BTCoex], set coex table, set 0x6c8 = 0x%x\n", val0x6c8); 1022 btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); 1023 1024 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1025 "[BTCoex], set coex table, set 0x6cc = 0x%x\n", val0x6cc); 1026 btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); 1027 } 1028 1029 static void halbtc8192e2ant_coex_table(struct btc_coexist *btcoexist, 1030 bool force_exec, 1031 u32 val0x6c0, u32 val0x6c4, 1032 u32 val0x6c8, u8 val0x6cc) 1033 { 1034 struct rtl_priv *rtlpriv = btcoexist->adapter; 1035 1036 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1037 "[BTCoex], %s write Coex Table 0x6c0 = 0x%x, ", 1038 (force_exec ? "force to" : ""), val0x6c0); 1039 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1040 "0x6c4 = 0x%x, 0x6c8 = 0x%x, 0x6cc = 0x%x\n", 1041 val0x6c4, val0x6c8, val0x6cc); 1042 coex_dm->cur_val0x6c0 = val0x6c0; 1043 coex_dm->cur_val0x6c4 = val0x6c4; 1044 coex_dm->cur_val0x6c8 = val0x6c8; 1045 coex_dm->cur_val0x6cc = val0x6cc; 1046 1047 if (!force_exec) { 1048 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1049 "[BTCoex], preVal0x6c0 = 0x%x, preVal0x6c4 = 0x%x, ", 1050 coex_dm->pre_val0x6c0, coex_dm->pre_val0x6c4); 1051 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1052 "preVal0x6c8 = 0x%x, preVal0x6cc = 0x%x !!\n", 1053 coex_dm->pre_val0x6c8, coex_dm->pre_val0x6cc); 1054 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1055 "[BTCoex], curVal0x6c0 = 0x%x, curVal0x6c4 = 0x%x\n", 1056 coex_dm->cur_val0x6c0, coex_dm->cur_val0x6c4); 1057 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1058 "curVal0x6c8 = 0x%x, curVal0x6cc = 0x%x !!\n", 1059 coex_dm->cur_val0x6c8, coex_dm->cur_val0x6cc); 1060 1061 if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && 1062 (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && 1063 (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && 1064 (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) 1065 return; 1066 } 1067 halbtc8192e2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, 1068 val0x6c8, val0x6cc); 1069 1070 coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; 1071 coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; 1072 coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; 1073 coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; 1074 } 1075 1076 static void btc8192e2ant_coex_tbl_w_type(struct btc_coexist *btcoexist, 1077 bool force_exec, u8 type) 1078 { 1079 switch (type) { 1080 case 0: 1081 halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555, 1082 0x5a5a5a5a, 0xffffff, 0x3); 1083 break; 1084 case 1: 1085 halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5a5a5a5a, 1086 0x5a5a5a5a, 0xffffff, 0x3); 1087 break; 1088 case 2: 1089 halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555, 1090 0x5ffb5ffb, 0xffffff, 0x3); 1091 break; 1092 case 3: 1093 halbtc8192e2ant_coex_table(btcoexist, force_exec, 0xdfffdfff, 1094 0x5fdb5fdb, 0xffffff, 0x3); 1095 break; 1096 case 4: 1097 halbtc8192e2ant_coex_table(btcoexist, force_exec, 0xdfffdfff, 1098 0x5ffb5ffb, 0xffffff, 0x3); 1099 break; 1100 default: 1101 break; 1102 } 1103 } 1104 1105 static void halbtc8192e2ant_set_fw_ignore_wlanact(struct btc_coexist *btcoexist, 1106 bool enable) 1107 { 1108 struct rtl_priv *rtlpriv = btcoexist->adapter; 1109 u8 h2c_parameter[1] = {0}; 1110 1111 if (enable) 1112 h2c_parameter[0] |= BIT0; /* function enable */ 1113 1114 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1115 "[BTCoex]set FW for BT Ignore Wlan_Act, FW write 0x63 = 0x%x\n", 1116 h2c_parameter[0]); 1117 1118 btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); 1119 } 1120 1121 static void halbtc8192e2ant_IgnoreWlanAct(struct btc_coexist *btcoexist, 1122 bool force_exec, bool enable) 1123 { 1124 struct rtl_priv *rtlpriv = btcoexist->adapter; 1125 1126 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1127 "[BTCoex], %s turn Ignore WlanAct %s\n", 1128 (force_exec ? "force to" : ""), (enable ? "ON" : "OFF")); 1129 coex_dm->cur_ignore_wlan_act = enable; 1130 1131 if (!force_exec) { 1132 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1133 "[BTCoex], bPreIgnoreWlanAct = %d ", 1134 coex_dm->pre_ignore_wlan_act); 1135 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1136 "bCurIgnoreWlanAct = %d!!\n", 1137 coex_dm->cur_ignore_wlan_act); 1138 1139 if (coex_dm->pre_ignore_wlan_act == 1140 coex_dm->cur_ignore_wlan_act) 1141 return; 1142 } 1143 halbtc8192e2ant_set_fw_ignore_wlanact(btcoexist, enable); 1144 1145 coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; 1146 } 1147 1148 static void halbtc8192e2ant_SetFwPstdma(struct btc_coexist *btcoexist, u8 byte1, 1149 u8 byte2, u8 byte3, u8 byte4, u8 byte5) 1150 { 1151 struct rtl_priv *rtlpriv = btcoexist->adapter; 1152 1153 u8 h2c_parameter[5] = {0}; 1154 1155 h2c_parameter[0] = byte1; 1156 h2c_parameter[1] = byte2; 1157 h2c_parameter[2] = byte3; 1158 h2c_parameter[3] = byte4; 1159 h2c_parameter[4] = byte5; 1160 1161 coex_dm->ps_tdma_para[0] = byte1; 1162 coex_dm->ps_tdma_para[1] = byte2; 1163 coex_dm->ps_tdma_para[2] = byte3; 1164 coex_dm->ps_tdma_para[3] = byte4; 1165 coex_dm->ps_tdma_para[4] = byte5; 1166 1167 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1168 "[BTCoex], FW write 0x60(5bytes) = 0x%x%08x\n", 1169 h2c_parameter[0], 1170 h2c_parameter[1] << 24 | h2c_parameter[2] << 16 | 1171 h2c_parameter[3] << 8 | h2c_parameter[4]); 1172 1173 btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); 1174 } 1175 1176 static void btc8192e2ant_sw_mec1(struct btc_coexist *btcoexist, 1177 bool shrink_rx_lpf, bool low_penalty_ra, 1178 bool limited_dig, bool btlan_constrain) 1179 { 1180 halbtc8192e2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); 1181 } 1182 1183 static void btc8192e2ant_sw_mec2(struct btc_coexist *btcoexist, 1184 bool agc_table_shift, bool adc_backoff, 1185 bool sw_dac_swing, u32 dac_swinglvl) 1186 { 1187 halbtc8192e2ant_AgcTable(btcoexist, NORMAL_EXEC, agc_table_shift); 1188 halbtc8192e2ant_DacSwing(btcoexist, NORMAL_EXEC, sw_dac_swing, 1189 dac_swinglvl); 1190 } 1191 1192 static void halbtc8192e2ant_ps_tdma(struct btc_coexist *btcoexist, 1193 bool force_exec, bool turn_on, u8 type) 1194 { 1195 struct rtl_priv *rtlpriv = btcoexist->adapter; 1196 1197 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1198 "[BTCoex], %s turn %s PS TDMA, type=%d\n", 1199 (force_exec ? "force to" : ""), 1200 (turn_on ? "ON" : "OFF"), type); 1201 coex_dm->cur_ps_tdma_on = turn_on; 1202 coex_dm->cur_ps_tdma = type; 1203 1204 if (!force_exec) { 1205 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1206 "[BTCoex], bPrePsTdmaOn = %d, bCurPsTdmaOn = %d!!\n", 1207 coex_dm->pre_ps_tdma_on, coex_dm->cur_ps_tdma_on); 1208 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1209 "[BTCoex], prePsTdma = %d, curPsTdma = %d!!\n", 1210 coex_dm->pre_ps_tdma, coex_dm->cur_ps_tdma); 1211 1212 if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && 1213 (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) 1214 return; 1215 } 1216 if (turn_on) { 1217 switch (type) { 1218 case 1: 1219 default: 1220 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a, 1221 0x1a, 0xe1, 0x90); 1222 break; 1223 case 2: 1224 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12, 1225 0x12, 0xe1, 0x90); 1226 break; 1227 case 3: 1228 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1c, 1229 0x3, 0xf1, 0x90); 1230 break; 1231 case 4: 1232 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x10, 1233 0x3, 0xf1, 0x90); 1234 break; 1235 case 5: 1236 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a, 1237 0x1a, 0x60, 0x90); 1238 break; 1239 case 6: 1240 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12, 1241 0x12, 0x60, 0x90); 1242 break; 1243 case 7: 1244 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1c, 1245 0x3, 0x70, 0x90); 1246 break; 1247 case 8: 1248 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xa3, 0x10, 1249 0x3, 0x70, 0x90); 1250 break; 1251 case 9: 1252 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a, 1253 0x1a, 0xe1, 0x10); 1254 break; 1255 case 10: 1256 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12, 1257 0x12, 0xe1, 0x10); 1258 break; 1259 case 11: 1260 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1c, 1261 0x3, 0xf1, 0x10); 1262 break; 1263 case 12: 1264 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x10, 1265 0x3, 0xf1, 0x10); 1266 break; 1267 case 13: 1268 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a, 1269 0x1a, 0xe0, 0x10); 1270 break; 1271 case 14: 1272 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12, 1273 0x12, 0xe0, 0x10); 1274 break; 1275 case 15: 1276 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1c, 1277 0x3, 0xf0, 0x10); 1278 break; 1279 case 16: 1280 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12, 1281 0x3, 0xf0, 0x10); 1282 break; 1283 case 17: 1284 halbtc8192e2ant_SetFwPstdma(btcoexist, 0x61, 0x20, 1285 0x03, 0x10, 0x10); 1286 break; 1287 case 18: 1288 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x5, 1289 0x5, 0xe1, 0x90); 1290 break; 1291 case 19: 1292 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x25, 1293 0x25, 0xe1, 0x90); 1294 break; 1295 case 20: 1296 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x25, 1297 0x25, 0x60, 0x90); 1298 break; 1299 case 21: 1300 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x15, 1301 0x03, 0x70, 0x90); 1302 break; 1303 case 71: 1304 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a, 1305 0x1a, 0xe1, 0x90); 1306 break; 1307 } 1308 } else { 1309 /* disable PS tdma */ 1310 switch (type) { 1311 default: 1312 case 0: 1313 halbtc8192e2ant_SetFwPstdma(btcoexist, 0x8, 0x0, 0x0, 1314 0x0, 0x0); 1315 btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4); 1316 break; 1317 case 1: 1318 halbtc8192e2ant_SetFwPstdma(btcoexist, 0x0, 0x0, 0x0, 1319 0x8, 0x0); 1320 mdelay(5); 1321 btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20); 1322 break; 1323 } 1324 } 1325 1326 /* update pre state */ 1327 coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; 1328 coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; 1329 } 1330 1331 static void halbtc8192e2ant_set_switch_sstype(struct btc_coexist *btcoexist, 1332 u8 sstype) 1333 { 1334 struct rtl_priv *rtlpriv = btcoexist->adapter; 1335 u8 mimops = BTC_MIMO_PS_DYNAMIC; 1336 u32 disra_mask = 0x0; 1337 1338 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1339 "[BTCoex], REAL set SS Type = %d\n", sstype); 1340 1341 disra_mask = halbtc8192e2ant_decidera_mask(btcoexist, sstype, 1342 coex_dm->curra_masktype); 1343 halbtc8192e2ant_Updatera_mask(btcoexist, FORCE_EXEC, disra_mask); 1344 1345 if (sstype == 1) { 1346 halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1); 1347 /* switch ofdm path */ 1348 btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x11); 1349 btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x1); 1350 btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81111111); 1351 /* switch cck patch */ 1352 btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x1); 1353 btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x81); 1354 mimops = BTC_MIMO_PS_STATIC; 1355 } else if (sstype == 2) { 1356 halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); 1357 btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x33); 1358 btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x3); 1359 btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81121313); 1360 btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x0); 1361 btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x41); 1362 mimops = BTC_MIMO_PS_DYNAMIC; 1363 } 1364 /* set rx 1ss or 2ss */ 1365 btcoexist->btc_set(btcoexist, BTC_SET_ACT_SEND_MIMO_PS, &mimops); 1366 } 1367 1368 static void halbtc8192e2ant_switch_sstype(struct btc_coexist *btcoexist, 1369 bool force_exec, u8 new_sstype) 1370 { 1371 struct rtl_priv *rtlpriv = btcoexist->adapter; 1372 1373 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1374 "[BTCoex], %s Switch SS Type = %d\n", 1375 (force_exec ? "force to" : ""), new_sstype); 1376 coex_dm->cur_sstype = new_sstype; 1377 1378 if (!force_exec) { 1379 if (coex_dm->pre_sstype == coex_dm->cur_sstype) 1380 return; 1381 } 1382 halbtc8192e2ant_set_switch_sstype(btcoexist, coex_dm->cur_sstype); 1383 1384 coex_dm->pre_sstype = coex_dm->cur_sstype; 1385 } 1386 1387 static void halbtc8192e2ant_coex_alloff(struct btc_coexist *btcoexist) 1388 { 1389 /* fw all off */ 1390 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); 1391 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6); 1392 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0); 1393 1394 /* sw all off */ 1395 btc8192e2ant_sw_mec1(btcoexist, false, false, false, false); 1396 btc8192e2ant_sw_mec2(btcoexist, false, false, false, 0x18); 1397 1398 /* hw all off */ 1399 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 0); 1400 } 1401 1402 static void halbtc8192e2ant_init_coex_dm(struct btc_coexist *btcoexist) 1403 { 1404 /* force to reset coex mechanism */ 1405 1406 halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1); 1407 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, FORCE_EXEC, 6); 1408 halbtc8192e2ant_dec_btpwr(btcoexist, FORCE_EXEC, 0); 1409 1410 btc8192e2ant_coex_tbl_w_type(btcoexist, FORCE_EXEC, 0); 1411 halbtc8192e2ant_switch_sstype(btcoexist, FORCE_EXEC, 2); 1412 1413 btc8192e2ant_sw_mec1(btcoexist, false, false, false, false); 1414 btc8192e2ant_sw_mec2(btcoexist, false, false, false, 0x18); 1415 } 1416 1417 static void halbtc8192e2ant_action_bt_inquiry(struct btc_coexist *btcoexist) 1418 { 1419 bool low_pwr_disable = true; 1420 1421 btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, 1422 &low_pwr_disable); 1423 1424 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1); 1425 1426 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2); 1427 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); 1428 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6); 1429 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0); 1430 1431 btc8192e2ant_sw_mec1(btcoexist, false, false, false, false); 1432 btc8192e2ant_sw_mec2(btcoexist, false, false, false, 0x18); 1433 } 1434 1435 static bool halbtc8192e2ant_is_common_action(struct btc_coexist *btcoexist) 1436 { 1437 struct rtl_priv *rtlpriv = btcoexist->adapter; 1438 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; 1439 bool common = false, wifi_connected = false, wifi_busy = false; 1440 bool bt_hson = false, low_pwr_disable = false; 1441 1442 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hson); 1443 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, 1444 &wifi_connected); 1445 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); 1446 1447 if (bt_link_info->sco_exist || bt_link_info->hid_exist) 1448 halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 0, 0, 0); 1449 else 1450 halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); 1451 1452 if (!wifi_connected) { 1453 low_pwr_disable = false; 1454 btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, 1455 &low_pwr_disable); 1456 1457 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1458 "[BTCoex], Wifi non-connected idle!!\n"); 1459 1460 if ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE == 1461 coex_dm->bt_status) || 1462 (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE == 1463 coex_dm->bt_status)) { 1464 halbtc8192e2ant_switch_sstype(btcoexist, 1465 NORMAL_EXEC, 2); 1466 btc8192e2ant_coex_tbl_w_type(btcoexist, 1467 NORMAL_EXEC, 1); 1468 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1469 false, 0); 1470 } else { 1471 halbtc8192e2ant_switch_sstype(btcoexist, 1472 NORMAL_EXEC, 1); 1473 btc8192e2ant_coex_tbl_w_type(btcoexist, 1474 NORMAL_EXEC, 0); 1475 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1476 false, 1); 1477 } 1478 1479 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6); 1480 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0); 1481 1482 btc8192e2ant_sw_mec1(btcoexist, false, false, false, false); 1483 btc8192e2ant_sw_mec2(btcoexist, false, false, false, 0x18); 1484 1485 common = true; 1486 } else { 1487 if (BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE == 1488 coex_dm->bt_status) { 1489 low_pwr_disable = false; 1490 btcoexist->btc_set(btcoexist, 1491 BTC_SET_ACT_DISABLE_LOW_POWER, 1492 &low_pwr_disable); 1493 1494 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1495 "Wifi connected + BT non connected-idle!!\n"); 1496 1497 halbtc8192e2ant_switch_sstype(btcoexist, 1498 NORMAL_EXEC, 2); 1499 btc8192e2ant_coex_tbl_w_type(btcoexist, 1500 NORMAL_EXEC, 1); 1501 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1502 false, 0); 1503 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, 1504 NORMAL_EXEC, 6); 1505 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0); 1506 1507 btc8192e2ant_sw_mec1(btcoexist, false, false, 1508 false, false); 1509 btc8192e2ant_sw_mec2(btcoexist, false, false, 1510 false, 0x18); 1511 1512 common = true; 1513 } else if (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE == 1514 coex_dm->bt_status) { 1515 low_pwr_disable = true; 1516 btcoexist->btc_set(btcoexist, 1517 BTC_SET_ACT_DISABLE_LOW_POWER, 1518 &low_pwr_disable); 1519 1520 if (bt_hson) 1521 return false; 1522 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1523 "Wifi connected + BT connected-idle!!\n"); 1524 1525 halbtc8192e2ant_switch_sstype(btcoexist, 1526 NORMAL_EXEC, 2); 1527 btc8192e2ant_coex_tbl_w_type(btcoexist, 1528 NORMAL_EXEC, 1); 1529 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1530 false, 0); 1531 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, 1532 NORMAL_EXEC, 6); 1533 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0); 1534 1535 btc8192e2ant_sw_mec1(btcoexist, true, false, 1536 false, false); 1537 btc8192e2ant_sw_mec2(btcoexist, false, false, 1538 false, 0x18); 1539 1540 common = true; 1541 } else { 1542 low_pwr_disable = true; 1543 btcoexist->btc_set(btcoexist, 1544 BTC_SET_ACT_DISABLE_LOW_POWER, 1545 &low_pwr_disable); 1546 1547 if (wifi_busy) { 1548 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1549 "Wifi Connected-Busy + BT Busy!!\n"); 1550 common = false; 1551 } else { 1552 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1553 "Wifi Connected-Idle + BT Busy!!\n"); 1554 1555 halbtc8192e2ant_switch_sstype(btcoexist, 1556 NORMAL_EXEC, 1); 1557 btc8192e2ant_coex_tbl_w_type(btcoexist, 1558 NORMAL_EXEC, 2); 1559 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1560 true, 21); 1561 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, 1562 NORMAL_EXEC, 6); 1563 halbtc8192e2ant_dec_btpwr(btcoexist, 1564 NORMAL_EXEC, 0); 1565 btc8192e2ant_sw_mec1(btcoexist, false, 1566 false, false, false); 1567 btc8192e2ant_sw_mec2(btcoexist, false, 1568 false, false, 0x18); 1569 common = true; 1570 } 1571 } 1572 } 1573 return common; 1574 } 1575 1576 static void btc8192e_int1(struct btc_coexist *btcoexist, bool tx_pause, 1577 int result) 1578 { 1579 struct rtl_priv *rtlpriv = btcoexist->adapter; 1580 1581 if (tx_pause) { 1582 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1583 "[BTCoex], TxPause = 1\n"); 1584 1585 if (coex_dm->cur_ps_tdma == 71) { 1586 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1587 true, 5); 1588 coex_dm->tdma_adj_type = 5; 1589 } else if (coex_dm->cur_ps_tdma == 1) { 1590 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1591 true, 5); 1592 coex_dm->tdma_adj_type = 5; 1593 } else if (coex_dm->cur_ps_tdma == 2) { 1594 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1595 true, 6); 1596 coex_dm->tdma_adj_type = 6; 1597 } else if (coex_dm->cur_ps_tdma == 3) { 1598 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1599 true, 7); 1600 coex_dm->tdma_adj_type = 7; 1601 } else if (coex_dm->cur_ps_tdma == 4) { 1602 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1603 true, 8); 1604 coex_dm->tdma_adj_type = 8; 1605 } 1606 if (coex_dm->cur_ps_tdma == 9) { 1607 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1608 true, 13); 1609 coex_dm->tdma_adj_type = 13; 1610 } else if (coex_dm->cur_ps_tdma == 10) { 1611 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1612 true, 14); 1613 coex_dm->tdma_adj_type = 14; 1614 } else if (coex_dm->cur_ps_tdma == 11) { 1615 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1616 true, 15); 1617 coex_dm->tdma_adj_type = 15; 1618 } else if (coex_dm->cur_ps_tdma == 12) { 1619 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1620 true, 16); 1621 coex_dm->tdma_adj_type = 16; 1622 } 1623 1624 if (result == -1) { 1625 if (coex_dm->cur_ps_tdma == 5) { 1626 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1627 true, 6); 1628 coex_dm->tdma_adj_type = 6; 1629 } else if (coex_dm->cur_ps_tdma == 6) { 1630 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1631 true, 7); 1632 coex_dm->tdma_adj_type = 7; 1633 } else if (coex_dm->cur_ps_tdma == 7) { 1634 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1635 true, 8); 1636 coex_dm->tdma_adj_type = 8; 1637 } else if (coex_dm->cur_ps_tdma == 13) { 1638 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1639 true, 14); 1640 coex_dm->tdma_adj_type = 14; 1641 } else if (coex_dm->cur_ps_tdma == 14) { 1642 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1643 true, 15); 1644 coex_dm->tdma_adj_type = 15; 1645 } else if (coex_dm->cur_ps_tdma == 15) { 1646 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1647 true, 16); 1648 coex_dm->tdma_adj_type = 16; 1649 } 1650 } else if (result == 1) { 1651 if (coex_dm->cur_ps_tdma == 8) { 1652 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1653 true, 7); 1654 coex_dm->tdma_adj_type = 7; 1655 } else if (coex_dm->cur_ps_tdma == 7) { 1656 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1657 true, 6); 1658 coex_dm->tdma_adj_type = 6; 1659 } else if (coex_dm->cur_ps_tdma == 6) { 1660 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1661 true, 5); 1662 coex_dm->tdma_adj_type = 5; 1663 } else if (coex_dm->cur_ps_tdma == 16) { 1664 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1665 true, 15); 1666 coex_dm->tdma_adj_type = 15; 1667 } else if (coex_dm->cur_ps_tdma == 15) { 1668 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1669 true, 14); 1670 coex_dm->tdma_adj_type = 14; 1671 } else if (coex_dm->cur_ps_tdma == 14) { 1672 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1673 true, 13); 1674 coex_dm->tdma_adj_type = 13; 1675 } 1676 } 1677 } else { 1678 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1679 "[BTCoex], TxPause = 0\n"); 1680 if (coex_dm->cur_ps_tdma == 5) { 1681 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1682 true, 71); 1683 coex_dm->tdma_adj_type = 71; 1684 } else if (coex_dm->cur_ps_tdma == 6) { 1685 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1686 true, 2); 1687 coex_dm->tdma_adj_type = 2; 1688 } else if (coex_dm->cur_ps_tdma == 7) { 1689 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1690 true, 3); 1691 coex_dm->tdma_adj_type = 3; 1692 } else if (coex_dm->cur_ps_tdma == 8) { 1693 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1694 true, 4); 1695 coex_dm->tdma_adj_type = 4; 1696 } 1697 if (coex_dm->cur_ps_tdma == 13) { 1698 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1699 true, 9); 1700 coex_dm->tdma_adj_type = 9; 1701 } else if (coex_dm->cur_ps_tdma == 14) { 1702 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1703 true, 10); 1704 coex_dm->tdma_adj_type = 10; 1705 } else if (coex_dm->cur_ps_tdma == 15) { 1706 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1707 true, 11); 1708 coex_dm->tdma_adj_type = 11; 1709 } else if (coex_dm->cur_ps_tdma == 16) { 1710 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1711 true, 12); 1712 coex_dm->tdma_adj_type = 12; 1713 } 1714 1715 if (result == -1) { 1716 if (coex_dm->cur_ps_tdma == 71) { 1717 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1718 true, 1); 1719 coex_dm->tdma_adj_type = 1; 1720 } else if (coex_dm->cur_ps_tdma == 1) { 1721 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1722 true, 2); 1723 coex_dm->tdma_adj_type = 2; 1724 } else if (coex_dm->cur_ps_tdma == 2) { 1725 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1726 true, 3); 1727 coex_dm->tdma_adj_type = 3; 1728 } else if (coex_dm->cur_ps_tdma == 3) { 1729 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1730 true, 4); 1731 coex_dm->tdma_adj_type = 4; 1732 } else if (coex_dm->cur_ps_tdma == 9) { 1733 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1734 true, 10); 1735 coex_dm->tdma_adj_type = 10; 1736 } else if (coex_dm->cur_ps_tdma == 10) { 1737 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1738 true, 11); 1739 coex_dm->tdma_adj_type = 11; 1740 } else if (coex_dm->cur_ps_tdma == 11) { 1741 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1742 true, 12); 1743 coex_dm->tdma_adj_type = 12; 1744 } 1745 } else if (result == 1) { 1746 if (coex_dm->cur_ps_tdma == 4) { 1747 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1748 true, 3); 1749 coex_dm->tdma_adj_type = 3; 1750 } else if (coex_dm->cur_ps_tdma == 3) { 1751 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1752 true, 2); 1753 coex_dm->tdma_adj_type = 2; 1754 } else if (coex_dm->cur_ps_tdma == 2) { 1755 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1756 true, 1); 1757 coex_dm->tdma_adj_type = 1; 1758 } else if (coex_dm->cur_ps_tdma == 1) { 1759 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1760 true, 71); 1761 coex_dm->tdma_adj_type = 71; 1762 } else if (coex_dm->cur_ps_tdma == 12) { 1763 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1764 true, 11); 1765 coex_dm->tdma_adj_type = 11; 1766 } else if (coex_dm->cur_ps_tdma == 11) { 1767 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1768 true, 10); 1769 coex_dm->tdma_adj_type = 10; 1770 } else if (coex_dm->cur_ps_tdma == 10) { 1771 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1772 true, 9); 1773 coex_dm->tdma_adj_type = 9; 1774 } 1775 } 1776 } 1777 } 1778 1779 static void btc8192e_int2(struct btc_coexist *btcoexist, bool tx_pause, 1780 int result) 1781 { 1782 struct rtl_priv *rtlpriv = btcoexist->adapter; 1783 1784 if (tx_pause) { 1785 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1786 "[BTCoex], TxPause = 1\n"); 1787 if (coex_dm->cur_ps_tdma == 1) { 1788 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1789 true, 6); 1790 coex_dm->tdma_adj_type = 6; 1791 } else if (coex_dm->cur_ps_tdma == 2) { 1792 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1793 true, 6); 1794 coex_dm->tdma_adj_type = 6; 1795 } else if (coex_dm->cur_ps_tdma == 3) { 1796 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1797 true, 7); 1798 coex_dm->tdma_adj_type = 7; 1799 } else if (coex_dm->cur_ps_tdma == 4) { 1800 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1801 true, 8); 1802 coex_dm->tdma_adj_type = 8; 1803 } 1804 if (coex_dm->cur_ps_tdma == 9) { 1805 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1806 true, 14); 1807 coex_dm->tdma_adj_type = 14; 1808 } else if (coex_dm->cur_ps_tdma == 10) { 1809 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1810 true, 14); 1811 coex_dm->tdma_adj_type = 14; 1812 } else if (coex_dm->cur_ps_tdma == 11) { 1813 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1814 true, 15); 1815 coex_dm->tdma_adj_type = 15; 1816 } else if (coex_dm->cur_ps_tdma == 12) { 1817 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1818 true, 16); 1819 coex_dm->tdma_adj_type = 16; 1820 } 1821 if (result == -1) { 1822 if (coex_dm->cur_ps_tdma == 5) { 1823 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1824 true, 6); 1825 coex_dm->tdma_adj_type = 6; 1826 } else if (coex_dm->cur_ps_tdma == 6) { 1827 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1828 true, 7); 1829 coex_dm->tdma_adj_type = 7; 1830 } else if (coex_dm->cur_ps_tdma == 7) { 1831 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1832 true, 8); 1833 coex_dm->tdma_adj_type = 8; 1834 } else if (coex_dm->cur_ps_tdma == 13) { 1835 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1836 true, 14); 1837 coex_dm->tdma_adj_type = 14; 1838 } else if (coex_dm->cur_ps_tdma == 14) { 1839 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1840 true, 15); 1841 coex_dm->tdma_adj_type = 15; 1842 } else if (coex_dm->cur_ps_tdma == 15) { 1843 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1844 true, 16); 1845 coex_dm->tdma_adj_type = 16; 1846 } 1847 } else if (result == 1) { 1848 if (coex_dm->cur_ps_tdma == 8) { 1849 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1850 true, 7); 1851 coex_dm->tdma_adj_type = 7; 1852 } else if (coex_dm->cur_ps_tdma == 7) { 1853 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1854 true, 6); 1855 coex_dm->tdma_adj_type = 6; 1856 } else if (coex_dm->cur_ps_tdma == 6) { 1857 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1858 true, 6); 1859 coex_dm->tdma_adj_type = 6; 1860 } else if (coex_dm->cur_ps_tdma == 16) { 1861 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1862 true, 15); 1863 coex_dm->tdma_adj_type = 15; 1864 } else if (coex_dm->cur_ps_tdma == 15) { 1865 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1866 true, 14); 1867 coex_dm->tdma_adj_type = 14; 1868 } else if (coex_dm->cur_ps_tdma == 14) { 1869 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1870 true, 14); 1871 coex_dm->tdma_adj_type = 14; 1872 } 1873 } 1874 } else { 1875 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1876 "[BTCoex], TxPause = 0\n"); 1877 if (coex_dm->cur_ps_tdma == 5) { 1878 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1879 true, 2); 1880 coex_dm->tdma_adj_type = 2; 1881 } else if (coex_dm->cur_ps_tdma == 6) { 1882 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1883 true, 2); 1884 coex_dm->tdma_adj_type = 2; 1885 } else if (coex_dm->cur_ps_tdma == 7) { 1886 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1887 true, 3); 1888 coex_dm->tdma_adj_type = 3; 1889 } else if (coex_dm->cur_ps_tdma == 8) { 1890 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1891 true, 4); 1892 coex_dm->tdma_adj_type = 4; 1893 } 1894 if (coex_dm->cur_ps_tdma == 13) { 1895 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1896 true, 10); 1897 coex_dm->tdma_adj_type = 10; 1898 } else if (coex_dm->cur_ps_tdma == 14) { 1899 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1900 true, 10); 1901 coex_dm->tdma_adj_type = 10; 1902 } else if (coex_dm->cur_ps_tdma == 15) { 1903 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1904 true, 11); 1905 coex_dm->tdma_adj_type = 11; 1906 } else if (coex_dm->cur_ps_tdma == 16) { 1907 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1908 true, 12); 1909 coex_dm->tdma_adj_type = 12; 1910 } 1911 if (result == -1) { 1912 if (coex_dm->cur_ps_tdma == 1) { 1913 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1914 true, 2); 1915 coex_dm->tdma_adj_type = 2; 1916 } else if (coex_dm->cur_ps_tdma == 2) { 1917 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1918 true, 3); 1919 coex_dm->tdma_adj_type = 3; 1920 } else if (coex_dm->cur_ps_tdma == 3) { 1921 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1922 true, 4); 1923 coex_dm->tdma_adj_type = 4; 1924 } else if (coex_dm->cur_ps_tdma == 9) { 1925 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1926 true, 10); 1927 coex_dm->tdma_adj_type = 10; 1928 } else if (coex_dm->cur_ps_tdma == 10) { 1929 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1930 true, 11); 1931 coex_dm->tdma_adj_type = 11; 1932 } else if (coex_dm->cur_ps_tdma == 11) { 1933 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1934 true, 12); 1935 coex_dm->tdma_adj_type = 12; 1936 } 1937 } else if (result == 1) { 1938 if (coex_dm->cur_ps_tdma == 4) { 1939 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1940 true, 3); 1941 coex_dm->tdma_adj_type = 3; 1942 } else if (coex_dm->cur_ps_tdma == 3) { 1943 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1944 true, 2); 1945 coex_dm->tdma_adj_type = 2; 1946 } else if (coex_dm->cur_ps_tdma == 2) { 1947 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1948 true, 2); 1949 coex_dm->tdma_adj_type = 2; 1950 } else if (coex_dm->cur_ps_tdma == 12) { 1951 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1952 true, 11); 1953 coex_dm->tdma_adj_type = 11; 1954 } else if (coex_dm->cur_ps_tdma == 11) { 1955 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1956 true, 10); 1957 coex_dm->tdma_adj_type = 10; 1958 } else if (coex_dm->cur_ps_tdma == 10) { 1959 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1960 true, 10); 1961 coex_dm->tdma_adj_type = 10; 1962 } 1963 } 1964 } 1965 } 1966 1967 static void btc8192e_int3(struct btc_coexist *btcoexist, bool tx_pause, 1968 int result) 1969 { 1970 struct rtl_priv *rtlpriv = btcoexist->adapter; 1971 1972 if (tx_pause) { 1973 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 1974 "[BTCoex], TxPause = 1\n"); 1975 if (coex_dm->cur_ps_tdma == 1) { 1976 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1977 true, 7); 1978 coex_dm->tdma_adj_type = 7; 1979 } else if (coex_dm->cur_ps_tdma == 2) { 1980 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1981 true, 7); 1982 coex_dm->tdma_adj_type = 7; 1983 } else if (coex_dm->cur_ps_tdma == 3) { 1984 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1985 true, 7); 1986 coex_dm->tdma_adj_type = 7; 1987 } else if (coex_dm->cur_ps_tdma == 4) { 1988 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1989 true, 8); 1990 coex_dm->tdma_adj_type = 8; 1991 } 1992 if (coex_dm->cur_ps_tdma == 9) { 1993 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1994 true, 15); 1995 coex_dm->tdma_adj_type = 15; 1996 } else if (coex_dm->cur_ps_tdma == 10) { 1997 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 1998 true, 15); 1999 coex_dm->tdma_adj_type = 15; 2000 } else if (coex_dm->cur_ps_tdma == 11) { 2001 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2002 true, 15); 2003 coex_dm->tdma_adj_type = 15; 2004 } else if (coex_dm->cur_ps_tdma == 12) { 2005 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2006 true, 16); 2007 coex_dm->tdma_adj_type = 16; 2008 } 2009 if (result == -1) { 2010 if (coex_dm->cur_ps_tdma == 5) { 2011 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2012 true, 7); 2013 coex_dm->tdma_adj_type = 7; 2014 } else if (coex_dm->cur_ps_tdma == 6) { 2015 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2016 true, 7); 2017 coex_dm->tdma_adj_type = 7; 2018 } else if (coex_dm->cur_ps_tdma == 7) { 2019 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2020 true, 8); 2021 coex_dm->tdma_adj_type = 8; 2022 } else if (coex_dm->cur_ps_tdma == 13) { 2023 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2024 true, 15); 2025 coex_dm->tdma_adj_type = 15; 2026 } else if (coex_dm->cur_ps_tdma == 14) { 2027 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2028 true, 15); 2029 coex_dm->tdma_adj_type = 15; 2030 } else if (coex_dm->cur_ps_tdma == 15) { 2031 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2032 true, 16); 2033 coex_dm->tdma_adj_type = 16; 2034 } 2035 } else if (result == 1) { 2036 if (coex_dm->cur_ps_tdma == 8) { 2037 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2038 true, 7); 2039 coex_dm->tdma_adj_type = 7; 2040 } else if (coex_dm->cur_ps_tdma == 7) { 2041 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2042 true, 7); 2043 coex_dm->tdma_adj_type = 7; 2044 } else if (coex_dm->cur_ps_tdma == 6) { 2045 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2046 true, 7); 2047 coex_dm->tdma_adj_type = 7; 2048 } else if (coex_dm->cur_ps_tdma == 16) { 2049 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2050 true, 15); 2051 coex_dm->tdma_adj_type = 15; 2052 } else if (coex_dm->cur_ps_tdma == 15) { 2053 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2054 true, 15); 2055 coex_dm->tdma_adj_type = 15; 2056 } else if (coex_dm->cur_ps_tdma == 14) { 2057 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2058 true, 15); 2059 coex_dm->tdma_adj_type = 15; 2060 } 2061 } 2062 } else { 2063 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 2064 "[BTCoex], TxPause = 0\n"); 2065 if (coex_dm->cur_ps_tdma == 5) { 2066 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2067 true, 3); 2068 coex_dm->tdma_adj_type = 3; 2069 } else if (coex_dm->cur_ps_tdma == 6) { 2070 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2071 true, 3); 2072 coex_dm->tdma_adj_type = 3; 2073 } else if (coex_dm->cur_ps_tdma == 7) { 2074 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2075 true, 3); 2076 coex_dm->tdma_adj_type = 3; 2077 } else if (coex_dm->cur_ps_tdma == 8) { 2078 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2079 true, 4); 2080 coex_dm->tdma_adj_type = 4; 2081 } 2082 if (coex_dm->cur_ps_tdma == 13) { 2083 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2084 true, 11); 2085 coex_dm->tdma_adj_type = 11; 2086 } else if (coex_dm->cur_ps_tdma == 14) { 2087 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2088 true, 11); 2089 coex_dm->tdma_adj_type = 11; 2090 } else if (coex_dm->cur_ps_tdma == 15) { 2091 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2092 true, 11); 2093 coex_dm->tdma_adj_type = 11; 2094 } else if (coex_dm->cur_ps_tdma == 16) { 2095 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2096 true, 12); 2097 coex_dm->tdma_adj_type = 12; 2098 } 2099 if (result == -1) { 2100 if (coex_dm->cur_ps_tdma == 1) { 2101 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2102 true, 3); 2103 coex_dm->tdma_adj_type = 3; 2104 } else if (coex_dm->cur_ps_tdma == 2) { 2105 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2106 true, 3); 2107 coex_dm->tdma_adj_type = 3; 2108 } else if (coex_dm->cur_ps_tdma == 3) { 2109 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2110 true, 4); 2111 coex_dm->tdma_adj_type = 4; 2112 } else if (coex_dm->cur_ps_tdma == 9) { 2113 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2114 true, 11); 2115 coex_dm->tdma_adj_type = 11; 2116 } else if (coex_dm->cur_ps_tdma == 10) { 2117 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2118 true, 11); 2119 coex_dm->tdma_adj_type = 11; 2120 } else if (coex_dm->cur_ps_tdma == 11) { 2121 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2122 true, 12); 2123 coex_dm->tdma_adj_type = 12; 2124 } 2125 } else if (result == 1) { 2126 if (coex_dm->cur_ps_tdma == 4) { 2127 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2128 true, 3); 2129 coex_dm->tdma_adj_type = 3; 2130 } else if (coex_dm->cur_ps_tdma == 3) { 2131 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2132 true, 3); 2133 coex_dm->tdma_adj_type = 3; 2134 } else if (coex_dm->cur_ps_tdma == 2) { 2135 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2136 true, 3); 2137 coex_dm->tdma_adj_type = 3; 2138 } else if (coex_dm->cur_ps_tdma == 12) { 2139 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2140 true, 11); 2141 coex_dm->tdma_adj_type = 11; 2142 } else if (coex_dm->cur_ps_tdma == 11) { 2143 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2144 true, 11); 2145 coex_dm->tdma_adj_type = 11; 2146 } else if (coex_dm->cur_ps_tdma == 10) { 2147 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2148 true, 11); 2149 coex_dm->tdma_adj_type = 11; 2150 } 2151 } 2152 } 2153 } 2154 2155 static void halbtc8192e2ant_tdma_duration_adjust(struct btc_coexist *btcoexist, 2156 bool sco_hid, bool tx_pause, 2157 u8 max_interval) 2158 { 2159 struct rtl_priv *rtlpriv = btcoexist->adapter; 2160 static int up, dn, m, n, wait_cnt; 2161 /* 0: no change, +1: increase WiFi duration, 2162 * -1: decrease WiFi duration 2163 */ 2164 int result; 2165 u8 retry_cnt = 0; 2166 2167 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 2168 "[BTCoex], TdmaDurationAdjust()\n"); 2169 2170 if (!coex_dm->auto_tdma_adjust) { 2171 coex_dm->auto_tdma_adjust = true; 2172 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 2173 "[BTCoex], first run TdmaDurationAdjust()!!\n"); 2174 if (sco_hid) { 2175 if (tx_pause) { 2176 if (max_interval == 1) { 2177 halbtc8192e2ant_ps_tdma(btcoexist, 2178 NORMAL_EXEC, 2179 true, 13); 2180 coex_dm->tdma_adj_type = 13; 2181 } else if (max_interval == 2) { 2182 halbtc8192e2ant_ps_tdma(btcoexist, 2183 NORMAL_EXEC, 2184 true, 14); 2185 coex_dm->tdma_adj_type = 14; 2186 } else { 2187 halbtc8192e2ant_ps_tdma(btcoexist, 2188 NORMAL_EXEC, 2189 true, 15); 2190 coex_dm->tdma_adj_type = 15; 2191 } 2192 } else { 2193 if (max_interval == 1) { 2194 halbtc8192e2ant_ps_tdma(btcoexist, 2195 NORMAL_EXEC, 2196 true, 9); 2197 coex_dm->tdma_adj_type = 9; 2198 } else if (max_interval == 2) { 2199 halbtc8192e2ant_ps_tdma(btcoexist, 2200 NORMAL_EXEC, 2201 true, 10); 2202 coex_dm->tdma_adj_type = 10; 2203 } else { 2204 halbtc8192e2ant_ps_tdma(btcoexist, 2205 NORMAL_EXEC, 2206 true, 11); 2207 coex_dm->tdma_adj_type = 11; 2208 } 2209 } 2210 } else { 2211 if (tx_pause) { 2212 if (max_interval == 1) { 2213 halbtc8192e2ant_ps_tdma(btcoexist, 2214 NORMAL_EXEC, 2215 true, 5); 2216 coex_dm->tdma_adj_type = 5; 2217 } else if (max_interval == 2) { 2218 halbtc8192e2ant_ps_tdma(btcoexist, 2219 NORMAL_EXEC, 2220 true, 6); 2221 coex_dm->tdma_adj_type = 6; 2222 } else { 2223 halbtc8192e2ant_ps_tdma(btcoexist, 2224 NORMAL_EXEC, 2225 true, 7); 2226 coex_dm->tdma_adj_type = 7; 2227 } 2228 } else { 2229 if (max_interval == 1) { 2230 halbtc8192e2ant_ps_tdma(btcoexist, 2231 NORMAL_EXEC, 2232 true, 1); 2233 coex_dm->tdma_adj_type = 1; 2234 } else if (max_interval == 2) { 2235 halbtc8192e2ant_ps_tdma(btcoexist, 2236 NORMAL_EXEC, 2237 true, 2); 2238 coex_dm->tdma_adj_type = 2; 2239 } else { 2240 halbtc8192e2ant_ps_tdma(btcoexist, 2241 NORMAL_EXEC, 2242 true, 3); 2243 coex_dm->tdma_adj_type = 3; 2244 } 2245 } 2246 } 2247 2248 up = 0; 2249 dn = 0; 2250 m = 1; 2251 n = 3; 2252 result = 0; 2253 wait_cnt = 0; 2254 } else { 2255 /* accquire the BT TRx retry count from BT_Info byte2 */ 2256 retry_cnt = coex_sta->bt_retry_cnt; 2257 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 2258 "[BTCoex], retry_cnt = %d\n", retry_cnt); 2259 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 2260 "[BTCoex], up=%d, dn=%d, m=%d, n=%d, wait_cnt=%d\n", 2261 up, dn, m, n, wait_cnt); 2262 result = 0; 2263 wait_cnt++; 2264 /* no retry in the last 2-second duration */ 2265 if (retry_cnt == 0) { 2266 up++; 2267 dn--; 2268 2269 if (dn <= 0) 2270 dn = 0; 2271 2272 if (up >= n) { 2273 wait_cnt = 0; 2274 n = 3; 2275 up = 0; 2276 dn = 0; 2277 result = 1; 2278 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 2279 "[BTCoex]Increase wifi duration!!\n"); 2280 } 2281 } else if (retry_cnt <= 3) { 2282 up--; 2283 dn++; 2284 2285 if (up <= 0) 2286 up = 0; 2287 2288 if (dn == 2) { 2289 if (wait_cnt <= 2) 2290 m++; 2291 else 2292 m = 1; 2293 2294 if (m >= 20) 2295 m = 20; 2296 2297 n = 3 * m; 2298 up = 0; 2299 dn = 0; 2300 wait_cnt = 0; 2301 result = -1; 2302 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 2303 "Reduce wifi duration for retry<3\n"); 2304 } 2305 } else { 2306 if (wait_cnt == 1) 2307 m++; 2308 else 2309 m = 1; 2310 2311 if (m >= 20) 2312 m = 20; 2313 2314 n = 3*m; 2315 up = 0; 2316 dn = 0; 2317 wait_cnt = 0; 2318 result = -1; 2319 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 2320 "Decrease wifi duration for retryCounter>3!!\n"); 2321 } 2322 2323 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 2324 "[BTCoex], max Interval = %d\n", max_interval); 2325 if (max_interval == 1) 2326 btc8192e_int1(btcoexist, tx_pause, result); 2327 else if (max_interval == 2) 2328 btc8192e_int2(btcoexist, tx_pause, result); 2329 else if (max_interval == 3) 2330 btc8192e_int3(btcoexist, tx_pause, result); 2331 } 2332 2333 /* if current PsTdma not match with 2334 * the recorded one (when scan, dhcp...), 2335 * then we have to adjust it back to the previous record one. 2336 */ 2337 if (coex_dm->cur_ps_tdma != coex_dm->tdma_adj_type) { 2338 bool scan = false, link = false, roam = false; 2339 2340 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 2341 "[BTCoex], PsTdma type dismatch!!!, "); 2342 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 2343 "curPsTdma=%d, recordPsTdma=%d\n", 2344 coex_dm->cur_ps_tdma, coex_dm->tdma_adj_type); 2345 2346 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); 2347 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); 2348 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); 2349 2350 if (!scan && !link && !roam) 2351 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2352 true, 2353 coex_dm->tdma_adj_type); 2354 else 2355 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 2356 "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"); 2357 } 2358 } 2359 2360 /* SCO only or SCO+PAN(HS) */ 2361 static void halbtc8192e2ant_action_sco(struct btc_coexist *btcoexist) 2362 { 2363 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_STAY_LOW; 2364 u32 wifi_bw; 2365 2366 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0); 2367 2368 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1); 2369 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); 2370 2371 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6); 2372 2373 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 4); 2374 2375 btrssi_state = halbtc8192e2ant_btrssi_state(btcoexist, 3, 34, 42); 2376 2377 if ((btrssi_state == BTC_RSSI_STATE_LOW) || 2378 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) { 2379 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0); 2380 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); 2381 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) || 2382 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { 2383 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2); 2384 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); 2385 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) || 2386 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2387 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4); 2388 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); 2389 } 2390 2391 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); 2392 2393 /* sw mechanism */ 2394 if (BTC_WIFI_BW_HT40 == wifi_bw) { 2395 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2396 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2397 btc8192e2ant_sw_mec1(btcoexist, true, true, 2398 false, false); 2399 btc8192e2ant_sw_mec2(btcoexist, true, false, 2400 false, 0x6); 2401 } else { 2402 btc8192e2ant_sw_mec1(btcoexist, true, true, 2403 false, false); 2404 btc8192e2ant_sw_mec2(btcoexist, false, false, 2405 false, 0x6); 2406 } 2407 } else { 2408 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2409 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2410 btc8192e2ant_sw_mec1(btcoexist, false, true, 2411 false, false); 2412 btc8192e2ant_sw_mec2(btcoexist, true, false, 2413 false, 0x6); 2414 } else { 2415 btc8192e2ant_sw_mec1(btcoexist, false, true, 2416 false, false); 2417 btc8192e2ant_sw_mec2(btcoexist, false, false, 2418 false, 0x6); 2419 } 2420 } 2421 } 2422 2423 static void halbtc8192e2ant_action_sco_pan(struct btc_coexist *btcoexist) 2424 { 2425 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_STAY_LOW; 2426 u32 wifi_bw; 2427 2428 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0); 2429 2430 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1); 2431 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); 2432 2433 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6); 2434 2435 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 4); 2436 2437 btrssi_state = halbtc8192e2ant_btrssi_state(btcoexist, 3, 34, 42); 2438 2439 if ((btrssi_state == BTC_RSSI_STATE_LOW) || 2440 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) { 2441 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0); 2442 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); 2443 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) || 2444 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { 2445 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2); 2446 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10); 2447 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) || 2448 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2449 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4); 2450 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10); 2451 } 2452 2453 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); 2454 2455 /* sw mechanism */ 2456 if (BTC_WIFI_BW_HT40 == wifi_bw) { 2457 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2458 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2459 btc8192e2ant_sw_mec1(btcoexist, true, true, 2460 false, false); 2461 btc8192e2ant_sw_mec2(btcoexist, true, false, 2462 false, 0x6); 2463 } else { 2464 btc8192e2ant_sw_mec1(btcoexist, true, true, 2465 false, false); 2466 btc8192e2ant_sw_mec2(btcoexist, false, false, 2467 false, 0x6); 2468 } 2469 } else { 2470 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2471 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2472 btc8192e2ant_sw_mec1(btcoexist, false, true, 2473 false, false); 2474 btc8192e2ant_sw_mec2(btcoexist, true, false, 2475 false, 0x6); 2476 } else { 2477 btc8192e2ant_sw_mec1(btcoexist, false, true, 2478 false, false); 2479 btc8192e2ant_sw_mec2(btcoexist, false, false, 2480 false, 0x6); 2481 } 2482 } 2483 } 2484 2485 static void halbtc8192e2ant_action_hid(struct btc_coexist *btcoexist) 2486 { 2487 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH; 2488 u32 wifi_bw; 2489 2490 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0); 2491 btrssi_state = halbtc8192e2ant_btrssi_state(btcoexist, 3, 34, 42); 2492 2493 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1); 2494 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); 2495 2496 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6); 2497 2498 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); 2499 2500 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 3); 2501 2502 if ((btrssi_state == BTC_RSSI_STATE_LOW) || 2503 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) { 2504 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0); 2505 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); 2506 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) || 2507 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { 2508 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2); 2509 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); 2510 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) || 2511 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2512 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4); 2513 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); 2514 } 2515 2516 /* sw mechanism */ 2517 if (BTC_WIFI_BW_HT40 == wifi_bw) { 2518 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2519 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2520 btc8192e2ant_sw_mec1(btcoexist, true, true, 2521 false, false); 2522 btc8192e2ant_sw_mec2(btcoexist, true, false, 2523 false, 0x18); 2524 } else { 2525 btc8192e2ant_sw_mec1(btcoexist, true, true, 2526 false, false); 2527 btc8192e2ant_sw_mec2(btcoexist, false, false, 2528 false, 0x18); 2529 } 2530 } else { 2531 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2532 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2533 btc8192e2ant_sw_mec1(btcoexist, false, true, 2534 false, false); 2535 btc8192e2ant_sw_mec2(btcoexist, true, false, 2536 false, 0x18); 2537 } else { 2538 btc8192e2ant_sw_mec1(btcoexist, false, true, 2539 false, false); 2540 btc8192e2ant_sw_mec2(btcoexist, false, false, 2541 false, 0x18); 2542 } 2543 } 2544 } 2545 2546 /* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ 2547 static void halbtc8192e2ant_action_a2dp(struct btc_coexist *btcoexist) 2548 { 2549 struct rtl_priv *rtlpriv = btcoexist->adapter; 2550 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH; 2551 u32 wifi_bw; 2552 bool long_dist = false; 2553 2554 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0); 2555 btrssi_state = halbtc8192e2ant_btrssi_state(btcoexist, 3, 34, 42); 2556 2557 if ((btrssi_state == BTC_RSSI_STATE_LOW || 2558 btrssi_state == BTC_RSSI_STATE_STAY_LOW) && 2559 (wifirssi_state == BTC_RSSI_STATE_LOW || 2560 wifirssi_state == BTC_RSSI_STATE_STAY_LOW)) { 2561 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 2562 "[BTCoex], A2dp, wifi/bt rssi both LOW!!\n"); 2563 long_dist = true; 2564 } 2565 if (long_dist) { 2566 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 2); 2567 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 2568 0x4); 2569 } else { 2570 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1); 2571 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 2572 0x8); 2573 } 2574 2575 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6); 2576 2577 if (long_dist) 2578 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 0); 2579 else 2580 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2); 2581 2582 if (long_dist) { 2583 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 17); 2584 coex_dm->auto_tdma_adjust = false; 2585 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0); 2586 } else { 2587 if ((btrssi_state == BTC_RSSI_STATE_LOW) || 2588 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) { 2589 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, 2590 true, 1); 2591 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0); 2592 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) || 2593 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { 2594 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, 2595 false, 1); 2596 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2); 2597 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) || 2598 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2599 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, 2600 false, 1); 2601 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4); 2602 } 2603 } 2604 2605 /* sw mechanism */ 2606 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); 2607 if (BTC_WIFI_BW_HT40 == wifi_bw) { 2608 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2609 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2610 btc8192e2ant_sw_mec1(btcoexist, true, false, 2611 false, false); 2612 btc8192e2ant_sw_mec2(btcoexist, true, false, 2613 false, 0x18); 2614 } else { 2615 btc8192e2ant_sw_mec1(btcoexist, true, false, 2616 false, false); 2617 btc8192e2ant_sw_mec2(btcoexist, false, false, 2618 false, 0x18); 2619 } 2620 } else { 2621 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2622 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2623 btc8192e2ant_sw_mec1(btcoexist, false, false, 2624 false, false); 2625 btc8192e2ant_sw_mec2(btcoexist, true, false, 2626 false, 0x18); 2627 } else { 2628 btc8192e2ant_sw_mec1(btcoexist, false, false, 2629 false, false); 2630 btc8192e2ant_sw_mec2(btcoexist, false, false, 2631 false, 0x18); 2632 } 2633 } 2634 } 2635 2636 static void halbtc8192e2ant_action_a2dp_pan_hs(struct btc_coexist *btcoexist) 2637 { 2638 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH; 2639 u32 wifi_bw; 2640 2641 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0); 2642 btrssi_state = halbtc8192e2ant_btrssi_state(btcoexist, 3, 34, 42); 2643 2644 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1); 2645 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); 2646 2647 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6); 2648 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2); 2649 2650 if ((btrssi_state == BTC_RSSI_STATE_LOW) || 2651 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) { 2652 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 2); 2653 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0); 2654 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) || 2655 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { 2656 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, 2657 false, 2); 2658 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2); 2659 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) || 2660 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2661 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, 2662 false, 2); 2663 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4); 2664 } 2665 2666 /* sw mechanism */ 2667 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); 2668 if (BTC_WIFI_BW_HT40 == wifi_bw) { 2669 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2670 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2671 btc8192e2ant_sw_mec1(btcoexist, true, false, 2672 false, false); 2673 btc8192e2ant_sw_mec2(btcoexist, true, false, 2674 true, 0x6); 2675 } else { 2676 btc8192e2ant_sw_mec1(btcoexist, true, false, 2677 false, false); 2678 btc8192e2ant_sw_mec2(btcoexist, false, false, 2679 true, 0x6); 2680 } 2681 } else { 2682 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2683 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2684 btc8192e2ant_sw_mec1(btcoexist, false, false, 2685 false, false); 2686 btc8192e2ant_sw_mec2(btcoexist, true, false, 2687 true, 0x6); 2688 } else { 2689 btc8192e2ant_sw_mec1(btcoexist, false, false, 2690 false, false); 2691 btc8192e2ant_sw_mec2(btcoexist, false, false, 2692 true, 0x6); 2693 } 2694 } 2695 } 2696 2697 static void halbtc8192e2ant_action_pan_edr(struct btc_coexist *btcoexist) 2698 { 2699 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH; 2700 u32 wifi_bw; 2701 2702 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0); 2703 btrssi_state = halbtc8192e2ant_btrssi_state(btcoexist, 3, 34, 42); 2704 2705 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1); 2706 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); 2707 2708 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6); 2709 2710 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2); 2711 2712 if ((btrssi_state == BTC_RSSI_STATE_LOW) || 2713 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) { 2714 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0); 2715 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); 2716 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) || 2717 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { 2718 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2); 2719 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1); 2720 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) || 2721 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2722 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4); 2723 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1); 2724 } 2725 2726 /* sw mechanism */ 2727 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); 2728 if (BTC_WIFI_BW_HT40 == wifi_bw) { 2729 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2730 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2731 btc8192e2ant_sw_mec1(btcoexist, true, false, 2732 false, false); 2733 btc8192e2ant_sw_mec2(btcoexist, true, false, 2734 false, 0x18); 2735 } else { 2736 btc8192e2ant_sw_mec1(btcoexist, true, false, 2737 false, false); 2738 btc8192e2ant_sw_mec2(btcoexist, false, false, 2739 false, 0x18); 2740 } 2741 } else { 2742 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2743 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2744 btc8192e2ant_sw_mec1(btcoexist, false, false, 2745 false, false); 2746 btc8192e2ant_sw_mec2(btcoexist, true, false, 2747 false, 0x18); 2748 } else { 2749 btc8192e2ant_sw_mec1(btcoexist, false, false, 2750 false, false); 2751 btc8192e2ant_sw_mec2(btcoexist, false, false, 2752 false, 0x18); 2753 } 2754 } 2755 } 2756 2757 /* PAN(HS) only */ 2758 static void halbtc8192e2ant_action_pan_hs(struct btc_coexist *btcoexist) 2759 { 2760 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH; 2761 u32 wifi_bw; 2762 2763 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0); 2764 btrssi_state = halbtc8192e2ant_btrssi_state(btcoexist, 3, 34, 42); 2765 2766 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1); 2767 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); 2768 2769 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6); 2770 2771 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2); 2772 2773 if ((btrssi_state == BTC_RSSI_STATE_LOW) || 2774 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) { 2775 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0); 2776 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) || 2777 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { 2778 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2); 2779 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) || 2780 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2781 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4); 2782 } 2783 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); 2784 2785 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); 2786 if (BTC_WIFI_BW_HT40 == wifi_bw) { 2787 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2788 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2789 btc8192e2ant_sw_mec1(btcoexist, true, false, 2790 false, false); 2791 btc8192e2ant_sw_mec2(btcoexist, true, false, 2792 false, 0x18); 2793 } else { 2794 btc8192e2ant_sw_mec1(btcoexist, true, false, 2795 false, false); 2796 btc8192e2ant_sw_mec2(btcoexist, false, false, 2797 false, 0x18); 2798 } 2799 } else { 2800 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2801 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2802 btc8192e2ant_sw_mec1(btcoexist, false, false, 2803 false, false); 2804 btc8192e2ant_sw_mec2(btcoexist, true, false, 2805 false, 0x18); 2806 } else { 2807 btc8192e2ant_sw_mec1(btcoexist, false, false, 2808 false, false); 2809 btc8192e2ant_sw_mec2(btcoexist, false, false, 2810 false, 0x18); 2811 } 2812 } 2813 } 2814 2815 /* PAN(EDR)+A2DP */ 2816 static void halbtc8192e2ant_action_pan_edr_a2dp(struct btc_coexist *btcoexist) 2817 { 2818 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH; 2819 u32 wifi_bw; 2820 2821 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0); 2822 btrssi_state = halbtc8192e2ant_btrssi_state(btcoexist, 3, 34, 42); 2823 2824 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1); 2825 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); 2826 2827 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6); 2828 2829 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2); 2830 2831 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); 2832 2833 if ((btrssi_state == BTC_RSSI_STATE_LOW) || 2834 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) { 2835 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0); 2836 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 3); 2837 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) || 2838 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { 2839 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2); 2840 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, 2841 false, 3); 2842 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) || 2843 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2844 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4); 2845 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, 2846 false, 3); 2847 } 2848 2849 /* sw mechanism */ 2850 if (BTC_WIFI_BW_HT40 == wifi_bw) { 2851 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2852 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2853 btc8192e2ant_sw_mec1(btcoexist, true, false, 2854 false, false); 2855 btc8192e2ant_sw_mec2(btcoexist, true, false, 2856 false, 0x18); 2857 } else { 2858 btc8192e2ant_sw_mec1(btcoexist, true, false, 2859 false, false); 2860 btc8192e2ant_sw_mec2(btcoexist, false, false, 2861 false, 0x18); 2862 } 2863 } else { 2864 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2865 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2866 btc8192e2ant_sw_mec1(btcoexist, false, false, 2867 false, false); 2868 btc8192e2ant_sw_mec2(btcoexist, true, false, 2869 false, 0x18); 2870 } else { 2871 btc8192e2ant_sw_mec1(btcoexist, false, false, 2872 false, false); 2873 btc8192e2ant_sw_mec2(btcoexist, false, false, 2874 false, 0x18); 2875 } 2876 } 2877 } 2878 2879 static void halbtc8192e2ant_action_pan_edr_hid(struct btc_coexist *btcoexist) 2880 { 2881 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH; 2882 u32 wifi_bw; 2883 2884 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0); 2885 btrssi_state = halbtc8192e2ant_btrssi_state(btcoexist, 3, 34, 42); 2886 2887 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); 2888 2889 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1); 2890 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); 2891 2892 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6); 2893 2894 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 3); 2895 2896 if ((btrssi_state == BTC_RSSI_STATE_LOW) || 2897 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) { 2898 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0); 2899 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); 2900 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) || 2901 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { 2902 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2); 2903 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2904 true, 10); 2905 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) || 2906 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2907 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4); 2908 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, 2909 true, 10); 2910 } 2911 2912 /* sw mechanism */ 2913 if (BTC_WIFI_BW_HT40 == wifi_bw) { 2914 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2915 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2916 btc8192e2ant_sw_mec1(btcoexist, true, true, 2917 false, false); 2918 btc8192e2ant_sw_mec2(btcoexist, true, false, 2919 false, 0x18); 2920 } else { 2921 btc8192e2ant_sw_mec1(btcoexist, true, true, 2922 false, false); 2923 btc8192e2ant_sw_mec2(btcoexist, false, false, 2924 false, 0x18); 2925 } 2926 } else { 2927 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2928 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2929 btc8192e2ant_sw_mec1(btcoexist, false, true, 2930 false, false); 2931 btc8192e2ant_sw_mec2(btcoexist, true, false, 2932 false, 0x18); 2933 } else { 2934 btc8192e2ant_sw_mec1(btcoexist, false, true, 2935 false, false); 2936 btc8192e2ant_sw_mec2(btcoexist, false, false, 2937 false, 0x18); 2938 } 2939 } 2940 } 2941 2942 /* HID+A2DP+PAN(EDR) */ 2943 static void btc8192e2ant_action_hid_a2dp_pan_edr(struct btc_coexist *btcoexist) 2944 { 2945 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH; 2946 u32 wifi_bw; 2947 2948 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0); 2949 btrssi_state = halbtc8192e2ant_btrssi_state(btcoexist, 3, 34, 42); 2950 2951 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1); 2952 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); 2953 2954 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6); 2955 2956 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); 2957 2958 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 3); 2959 2960 if ((btrssi_state == BTC_RSSI_STATE_LOW) || 2961 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) { 2962 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0); 2963 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, true, 3); 2964 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) || 2965 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { 2966 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2); 2967 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 3); 2968 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) || 2969 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2970 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4); 2971 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 3); 2972 } 2973 2974 /* sw mechanism */ 2975 if (BTC_WIFI_BW_HT40 == wifi_bw) { 2976 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2977 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2978 btc8192e2ant_sw_mec1(btcoexist, true, true, 2979 false, false); 2980 btc8192e2ant_sw_mec2(btcoexist, true, false, 2981 false, 0x18); 2982 } else { 2983 btc8192e2ant_sw_mec1(btcoexist, true, true, 2984 false, false); 2985 btc8192e2ant_sw_mec2(btcoexist, false, false, 2986 false, 0x18); 2987 } 2988 } else { 2989 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 2990 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 2991 btc8192e2ant_sw_mec1(btcoexist, false, true, 2992 false, false); 2993 btc8192e2ant_sw_mec2(btcoexist, true, false, 2994 false, 0x18); 2995 } else { 2996 btc8192e2ant_sw_mec1(btcoexist, false, true, 2997 false, false); 2998 btc8192e2ant_sw_mec2(btcoexist, false, false, 2999 false, 0x18); 3000 } 3001 } 3002 } 3003 3004 static void halbtc8192e2ant_action_hid_a2dp(struct btc_coexist *btcoexist) 3005 { 3006 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH; 3007 u32 wifi_bw; 3008 3009 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0); 3010 btrssi_state = halbtc8192e2ant_btrssi_state(btcoexist, 3, 34, 42); 3011 3012 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1); 3013 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); 3014 3015 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); 3016 3017 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 3); 3018 3019 if ((btrssi_state == BTC_RSSI_STATE_LOW) || 3020 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) { 3021 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0); 3022 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, true, 2); 3023 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) || 3024 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { 3025 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2); 3026 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 2); 3027 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) || 3028 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 3029 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4); 3030 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 2); 3031 } 3032 3033 /* sw mechanism */ 3034 if (BTC_WIFI_BW_HT40 == wifi_bw) { 3035 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 3036 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 3037 btc8192e2ant_sw_mec1(btcoexist, true, true, 3038 false, false); 3039 btc8192e2ant_sw_mec2(btcoexist, true, false, 3040 false, 0x18); 3041 } else { 3042 btc8192e2ant_sw_mec1(btcoexist, true, true, 3043 false, false); 3044 btc8192e2ant_sw_mec2(btcoexist, false, false, 3045 false, 0x18); 3046 } 3047 } else { 3048 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) || 3049 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) { 3050 btc8192e2ant_sw_mec1(btcoexist, false, true, 3051 false, false); 3052 btc8192e2ant_sw_mec2(btcoexist, true, false, 3053 false, 0x18); 3054 } else { 3055 btc8192e2ant_sw_mec1(btcoexist, false, true, 3056 false, false); 3057 btc8192e2ant_sw_mec2(btcoexist, false, false, 3058 false, 0x18); 3059 } 3060 } 3061 } 3062 3063 static void halbtc8192e2ant_run_coexist_mechanism(struct btc_coexist *btcoexist) 3064 { 3065 struct rtl_priv *rtlpriv = btcoexist->adapter; 3066 u8 algorithm = 0; 3067 3068 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3069 "[BTCoex], RunCoexistMechanism()===>\n"); 3070 3071 if (btcoexist->manual_control) { 3072 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3073 "[BTCoex], return for Manual CTRL <===\n"); 3074 return; 3075 } 3076 3077 if (coex_sta->under_ips) { 3078 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3079 "[BTCoex], wifi is under IPS !!!\n"); 3080 return; 3081 } 3082 3083 algorithm = halbtc8192e2ant_action_algorithm(btcoexist); 3084 if (coex_sta->c2h_bt_inquiry_page && 3085 (BT_8192E_2ANT_COEX_ALGO_PANHS != algorithm)) { 3086 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3087 "[BTCoex], BT is under inquiry/page scan !!\n"); 3088 halbtc8192e2ant_action_bt_inquiry(btcoexist); 3089 return; 3090 } 3091 3092 coex_dm->cur_algorithm = algorithm; 3093 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3094 "[BTCoex], Algorithm = %d\n", coex_dm->cur_algorithm); 3095 3096 if (halbtc8192e2ant_is_common_action(btcoexist)) { 3097 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3098 "[BTCoex], Action 2-Ant common\n"); 3099 coex_dm->auto_tdma_adjust = false; 3100 } else { 3101 if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) { 3102 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3103 "[BTCoex] preAlgorithm=%d, curAlgorithm=%d\n", 3104 coex_dm->pre_algorithm, 3105 coex_dm->cur_algorithm); 3106 coex_dm->auto_tdma_adjust = false; 3107 } 3108 switch (coex_dm->cur_algorithm) { 3109 case BT_8192E_2ANT_COEX_ALGO_SCO: 3110 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3111 "Action 2-Ant, algorithm = SCO\n"); 3112 halbtc8192e2ant_action_sco(btcoexist); 3113 break; 3114 case BT_8192E_2ANT_COEX_ALGO_SCO_PAN: 3115 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3116 "Action 2-Ant, algorithm = SCO+PAN(EDR)\n"); 3117 halbtc8192e2ant_action_sco_pan(btcoexist); 3118 break; 3119 case BT_8192E_2ANT_COEX_ALGO_HID: 3120 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3121 "Action 2-Ant, algorithm = HID\n"); 3122 halbtc8192e2ant_action_hid(btcoexist); 3123 break; 3124 case BT_8192E_2ANT_COEX_ALGO_A2DP: 3125 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3126 "Action 2-Ant, algorithm = A2DP\n"); 3127 halbtc8192e2ant_action_a2dp(btcoexist); 3128 break; 3129 case BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS: 3130 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3131 "Action 2-Ant, algorithm = A2DP+PAN(HS)\n"); 3132 halbtc8192e2ant_action_a2dp_pan_hs(btcoexist); 3133 break; 3134 case BT_8192E_2ANT_COEX_ALGO_PANEDR: 3135 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3136 "Action 2-Ant, algorithm = PAN(EDR)\n"); 3137 halbtc8192e2ant_action_pan_edr(btcoexist); 3138 break; 3139 case BT_8192E_2ANT_COEX_ALGO_PANHS: 3140 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3141 "Action 2-Ant, algorithm = HS mode\n"); 3142 halbtc8192e2ant_action_pan_hs(btcoexist); 3143 break; 3144 case BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP: 3145 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3146 "Action 2-Ant, algorithm = PAN+A2DP\n"); 3147 halbtc8192e2ant_action_pan_edr_a2dp(btcoexist); 3148 break; 3149 case BT_8192E_2ANT_COEX_ALGO_PANEDR_HID: 3150 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3151 "Action 2-Ant, algorithm = PAN(EDR)+HID\n"); 3152 halbtc8192e2ant_action_pan_edr_hid(btcoexist); 3153 break; 3154 case BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR: 3155 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3156 "Action 2-Ant, algorithm = HID+A2DP+PAN\n"); 3157 btc8192e2ant_action_hid_a2dp_pan_edr(btcoexist); 3158 break; 3159 case BT_8192E_2ANT_COEX_ALGO_HID_A2DP: 3160 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3161 "Action 2-Ant, algorithm = HID+A2DP\n"); 3162 halbtc8192e2ant_action_hid_a2dp(btcoexist); 3163 break; 3164 default: 3165 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3166 "Action 2-Ant, algorithm = unknown!!\n"); 3167 /* halbtc8192e2ant_coex_alloff(btcoexist); */ 3168 break; 3169 } 3170 coex_dm->pre_algorithm = coex_dm->cur_algorithm; 3171 } 3172 } 3173 3174 static void halbtc8192e2ant_init_hwconfig(struct btc_coexist *btcoexist, 3175 bool backup) 3176 { 3177 struct rtl_priv *rtlpriv = btcoexist->adapter; 3178 u16 u16tmp = 0; 3179 u8 u8tmp = 0; 3180 3181 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3182 "[BTCoex], 2Ant Init HW Config!!\n"); 3183 3184 if (backup) { 3185 /* backup rf 0x1e value */ 3186 coex_dm->bt_rf0x1e_backup = 3187 btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 3188 0x1e, 0xfffff); 3189 3190 coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, 3191 0x430); 3192 coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, 3193 0x434); 3194 coex_dm->backup_retrylimit = btcoexist->btc_read_2byte( 3195 btcoexist, 3196 0x42a); 3197 coex_dm->backup_ampdu_maxtime = btcoexist->btc_read_1byte( 3198 btcoexist, 3199 0x456); 3200 } 3201 3202 /* antenna sw ctrl to bt */ 3203 btcoexist->btc_write_1byte(btcoexist, 0x4f, 0x6); 3204 btcoexist->btc_write_1byte(btcoexist, 0x944, 0x24); 3205 btcoexist->btc_write_4byte(btcoexist, 0x930, 0x700700); 3206 btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20); 3207 if (btcoexist->chip_interface == BTC_INTF_USB) 3208 btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004); 3209 else 3210 btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004); 3211 3212 btc8192e2ant_coex_tbl_w_type(btcoexist, FORCE_EXEC, 0); 3213 3214 /* antenna switch control parameter */ 3215 btcoexist->btc_write_4byte(btcoexist, 0x858, 0x55555555); 3216 3217 /* coex parameters */ 3218 btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3); 3219 /* 0x790[5:0] = 0x5 */ 3220 u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); 3221 u8tmp &= 0xc0; 3222 u8tmp |= 0x5; 3223 btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); 3224 3225 /* enable counter statistics */ 3226 btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); 3227 3228 /* enable PTA */ 3229 btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20); 3230 /* enable mailbox interface */ 3231 u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x40); 3232 u16tmp |= BIT9; 3233 btcoexist->btc_write_2byte(btcoexist, 0x40, u16tmp); 3234 3235 /* enable PTA I2C mailbox */ 3236 u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x101); 3237 u8tmp |= BIT4; 3238 btcoexist->btc_write_1byte(btcoexist, 0x101, u8tmp); 3239 3240 /* enable bt clock when wifi is disabled. */ 3241 u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x93); 3242 u8tmp |= BIT0; 3243 btcoexist->btc_write_1byte(btcoexist, 0x93, u8tmp); 3244 /* enable bt clock when suspend. */ 3245 u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7); 3246 u8tmp |= BIT0; 3247 btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp); 3248 } 3249 3250 /************************************************************* 3251 * work around function start with wa_halbtc8192e2ant_ 3252 *************************************************************/ 3253 3254 /************************************************************ 3255 * extern function start with EXhalbtc8192e2ant_ 3256 ************************************************************/ 3257 3258 void ex_halbtc8192e2ant_init_hwconfig(struct btc_coexist *btcoexist) 3259 { 3260 halbtc8192e2ant_init_hwconfig(btcoexist, true); 3261 } 3262 3263 void ex_halbtc8192e2ant_init_coex_dm(struct btc_coexist *btcoexist) 3264 { 3265 struct rtl_priv *rtlpriv = btcoexist->adapter; 3266 3267 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3268 "[BTCoex], Coex Mechanism Init!!\n"); 3269 halbtc8192e2ant_init_coex_dm(btcoexist); 3270 } 3271 3272 void ex_halbtc8192e2ant_display_coex_info(struct btc_coexist *btcoexist) 3273 { 3274 struct btc_board_info *board_info = &btcoexist->board_info; 3275 struct btc_stack_info *stack_info = &btcoexist->stack_info; 3276 struct rtl_priv *rtlpriv = btcoexist->adapter; 3277 u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; 3278 u16 u16tmp[4]; 3279 u32 u32tmp[4]; 3280 bool roam = false, scan = false, link = false, wifi_under_5g = false; 3281 bool bt_hson = false, wifi_busy = false; 3282 int wifirssi = 0, bt_hs_rssi = 0; 3283 u32 wifi_bw, wifi_traffic_dir; 3284 u8 wifi_dot11_chnl, wifi_hs_chnl; 3285 u32 fw_ver = 0, bt_patch_ver = 0; 3286 3287 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 3288 "\r\n ============[BT Coexist info]============"); 3289 3290 if (btcoexist->manual_control) { 3291 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 3292 "\r\n ===========[Under Manual Control]==========="); 3293 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 3294 "\r\n =========================================="); 3295 } 3296 3297 if (!board_info->bt_exist) { 3298 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n BT not exists !!!"); 3299 return; 3300 } 3301 3302 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 3303 "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", 3304 board_info->pg_ant_num, board_info->btdm_ant_num); 3305 3306 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %s / %d", 3307 "BT stack/ hci ext ver", 3308 ((stack_info->profile_notified) ? "Yes" : "No"), 3309 stack_info->hci_version); 3310 3311 btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); 3312 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); 3313 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 3314 "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)", 3315 "CoexVer/ FwVer/ PatchVer", 3316 glcoex_ver_date_8192e_2ant, glcoex_ver_8192e_2ant, 3317 fw_ver, bt_patch_ver, bt_patch_ver); 3318 3319 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hson); 3320 btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_DOT11_CHNL, 3321 &wifi_dot11_chnl); 3322 btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_HS_CHNL, &wifi_hs_chnl); 3323 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d / %d(%d)", 3324 "Dot11 channel / HsMode(HsChnl)", 3325 wifi_dot11_chnl, bt_hson, wifi_hs_chnl); 3326 3327 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %3ph ", 3328 "H2C Wifi inform bt chnl Info", coex_dm->wifi_chnl_info); 3329 3330 btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifirssi); 3331 btcoexist->btc_get(btcoexist, BTC_GET_S4_HS_RSSI, &bt_hs_rssi); 3332 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d", 3333 "Wifi rssi/ HS rssi", wifirssi, bt_hs_rssi); 3334 3335 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); 3336 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); 3337 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); 3338 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d/ %d ", 3339 "Wifi link/ roam/ scan", link, roam, scan); 3340 3341 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); 3342 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); 3343 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); 3344 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, 3345 &wifi_traffic_dir); 3346 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %s / %s/ %s ", 3347 "Wifi status", (wifi_under_5g ? "5G" : "2.4G"), 3348 ((BTC_WIFI_BW_LEGACY == wifi_bw) ? "Legacy" : 3349 (((BTC_WIFI_BW_HT40 == wifi_bw) ? "HT40" : "HT20"))), 3350 ((!wifi_busy) ? "idle" : 3351 ((BTC_WIFI_TRAFFIC_TX == wifi_traffic_dir) ? 3352 "uplink" : "downlink"))); 3353 3354 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = [%s/ %d/ %d] ", 3355 "BT [status/ rssi/ retryCnt]", 3356 ((btcoexist->bt_info.bt_disabled) ? ("disabled") : 3357 ((coex_sta->c2h_bt_inquiry_page) ? 3358 ("inquiry/page scan") : 3359 ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE == 3360 coex_dm->bt_status) ? "non-connected idle" : 3361 ((BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE == 3362 coex_dm->bt_status) ? "connected-idle" : "busy")))), 3363 coex_sta->bt_rssi, coex_sta->bt_retry_cnt); 3364 3365 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d / %d / %d / %d", 3366 "SCO/HID/PAN/A2DP", stack_info->sco_exist, 3367 stack_info->hid_exist, stack_info->pan_exist, 3368 stack_info->a2dp_exist); 3369 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO); 3370 3371 bt_info_ext = coex_sta->bt_info_ext; 3372 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %s", 3373 "BT Info A2DP rate", 3374 (bt_info_ext&BIT0) ? "Basic rate" : "EDR rate"); 3375 3376 for (i = 0; i < BT_INFO_SRC_8192E_2ANT_MAX; i++) { 3377 if (coex_sta->bt_info_c2h_cnt[i]) { 3378 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 3379 "\r\n %-35s = %7ph(%d)", 3380 GLBtInfoSrc8192e2Ant[i], 3381 coex_sta->bt_info_c2h[i], 3382 coex_sta->bt_info_c2h_cnt[i]); 3383 } 3384 } 3385 3386 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %s/%s", 3387 "PS state, IPS/LPS", 3388 ((coex_sta->under_ips ? "IPS ON" : "IPS OFF")), 3389 ((coex_sta->under_lps ? "LPS ON" : "LPS OFF"))); 3390 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_FW_PWR_MODE_CMD); 3391 3392 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x ", "SS Type", 3393 coex_dm->cur_sstype); 3394 3395 /* Sw mechanism */ 3396 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s", 3397 "============[Sw mechanism]============"); 3398 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d/ %d ", 3399 "SM1[ShRf/ LpRA/ LimDig]", coex_dm->cur_rf_rx_lpf_shrink, 3400 coex_dm->cur_low_penalty_ra, coex_dm->limited_dig); 3401 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d/ %d(0x%x) ", 3402 "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", 3403 coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off, 3404 coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl); 3405 3406 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x ", "Rate Mask", 3407 btcoexist->bt_info.ra_mask); 3408 3409 /* Fw mechanism */ 3410 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s", 3411 "============[Fw mechanism]============"); 3412 3413 ps_tdma_case = coex_dm->cur_ps_tdma; 3414 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 3415 "\r\n %-35s = %5ph case-%d (auto:%d)", 3416 "PS TDMA", coex_dm->ps_tdma_para, 3417 ps_tdma_case, coex_dm->auto_tdma_adjust); 3418 3419 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d ", 3420 "DecBtPwr/ IgnWlanAct", 3421 coex_dm->cur_dec_bt_pwr, coex_dm->cur_ignore_wlan_act); 3422 3423 /* Hw setting */ 3424 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s", 3425 "============[Hw setting]============"); 3426 3427 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x", 3428 "RF-A, 0x1e initVal", coex_dm->bt_rf0x1e_backup); 3429 3430 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", 3431 "backup ARFR1/ARFR2/RL/AMaxTime", coex_dm->backup_arfr_cnt1, 3432 coex_dm->backup_arfr_cnt2, coex_dm->backup_retrylimit, 3433 coex_dm->backup_ampdu_maxtime); 3434 3435 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); 3436 u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); 3437 u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); 3438 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); 3439 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", 3440 "0x430/0x434/0x42a/0x456", 3441 u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); 3442 3443 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc04); 3444 u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xd04); 3445 u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x90c); 3446 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", 3447 "0xc04/ 0xd04/ 0x90c", u32tmp[0], u32tmp[1], u32tmp[2]); 3448 3449 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); 3450 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x", "0x778", 3451 u8tmp[0]); 3452 3453 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x92c); 3454 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x930); 3455 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/ 0x%x", 3456 "0x92c/ 0x930", (u8tmp[0]), u32tmp[0]); 3457 3458 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); 3459 u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x4f); 3460 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/ 0x%x", 3461 "0x40/ 0x4f", u8tmp[0], u8tmp[1]); 3462 3463 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); 3464 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); 3465 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/ 0x%x", 3466 "0x550(bcn ctrl)/0x522", u32tmp[0], u8tmp[0]); 3467 3468 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); 3469 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x", "0xc50(dig)", 3470 u32tmp[0]); 3471 3472 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); 3473 u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); 3474 u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); 3475 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); 3476 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 3477 "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", 3478 "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", 3479 u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); 3480 3481 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d", 3482 "0x770(hp rx[31:16]/tx[15:0])", 3483 coex_sta->high_priority_rx, coex_sta->high_priority_tx); 3484 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d", 3485 "0x774(lp rx[31:16]/tx[15:0])", 3486 coex_sta->low_priority_rx, coex_sta->low_priority_tx); 3487 #if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 1) 3488 halbtc8192e2ant_monitor_bt_ctr(btcoexist); 3489 #endif 3490 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); 3491 } 3492 3493 void ex_halbtc8192e2ant_ips_notify(struct btc_coexist *btcoexist, u8 type) 3494 { 3495 struct rtl_priv *rtlpriv = btcoexist->adapter; 3496 3497 if (BTC_IPS_ENTER == type) { 3498 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3499 "[BTCoex], IPS ENTER notify\n"); 3500 coex_sta->under_ips = true; 3501 halbtc8192e2ant_coex_alloff(btcoexist); 3502 } else if (BTC_IPS_LEAVE == type) { 3503 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3504 "[BTCoex], IPS LEAVE notify\n"); 3505 coex_sta->under_ips = false; 3506 } 3507 } 3508 3509 void ex_halbtc8192e2ant_lps_notify(struct btc_coexist *btcoexist, u8 type) 3510 { 3511 struct rtl_priv *rtlpriv = btcoexist->adapter; 3512 3513 if (BTC_LPS_ENABLE == type) { 3514 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3515 "[BTCoex], LPS ENABLE notify\n"); 3516 coex_sta->under_lps = true; 3517 } else if (BTC_LPS_DISABLE == type) { 3518 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3519 "[BTCoex], LPS DISABLE notify\n"); 3520 coex_sta->under_lps = false; 3521 } 3522 } 3523 3524 void ex_halbtc8192e2ant_scan_notify(struct btc_coexist *btcoexist, u8 type) 3525 { 3526 struct rtl_priv *rtlpriv = btcoexist->adapter; 3527 3528 if (BTC_SCAN_START == type) 3529 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3530 "[BTCoex], SCAN START notify\n"); 3531 else if (BTC_SCAN_FINISH == type) 3532 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3533 "[BTCoex], SCAN FINISH notify\n"); 3534 } 3535 3536 void ex_halbtc8192e2ant_connect_notify(struct btc_coexist *btcoexist, u8 type) 3537 { 3538 struct rtl_priv *rtlpriv = btcoexist->adapter; 3539 3540 if (BTC_ASSOCIATE_START == type) 3541 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3542 "[BTCoex], CONNECT START notify\n"); 3543 else if (BTC_ASSOCIATE_FINISH == type) 3544 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3545 "[BTCoex], CONNECT FINISH notify\n"); 3546 } 3547 3548 void ex_halbtc8192e2ant_media_status_notify(struct btc_coexist *btcoexist, 3549 u8 type) 3550 { 3551 struct rtl_priv *rtlpriv = btcoexist->adapter; 3552 u8 h2c_parameter[3] = {0}; 3553 u32 wifi_bw; 3554 u8 wifi_center_chnl; 3555 3556 if (btcoexist->manual_control || 3557 btcoexist->stop_coex_dm || 3558 btcoexist->bt_info.bt_disabled) 3559 return; 3560 3561 if (BTC_MEDIA_CONNECT == type) 3562 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3563 "[BTCoex], MEDIA connect notify\n"); 3564 else 3565 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3566 "[BTCoex], MEDIA disconnect notify\n"); 3567 3568 /* only 2.4G we need to inform bt the chnl mask */ 3569 btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, 3570 &wifi_center_chnl); 3571 if ((BTC_MEDIA_CONNECT == type) && 3572 (wifi_center_chnl <= 14)) { 3573 h2c_parameter[0] = 0x1; 3574 h2c_parameter[1] = wifi_center_chnl; 3575 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); 3576 if (BTC_WIFI_BW_HT40 == wifi_bw) 3577 h2c_parameter[2] = 0x30; 3578 else 3579 h2c_parameter[2] = 0x20; 3580 } 3581 3582 coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; 3583 coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; 3584 coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; 3585 3586 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3587 "[BTCoex], FW write 0x66 = 0x%x\n", 3588 h2c_parameter[0] << 16 | h2c_parameter[1] << 8 | 3589 h2c_parameter[2]); 3590 3591 btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); 3592 } 3593 3594 void ex_halbtc8192e2ant_special_packet_notify(struct btc_coexist *btcoexist, 3595 u8 type) 3596 { 3597 struct rtl_priv *rtlpriv = btcoexist->adapter; 3598 3599 if (type == BTC_PACKET_DHCP) 3600 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3601 "[BTCoex], DHCP Packet notify\n"); 3602 } 3603 3604 void ex_halbtc8192e2ant_bt_info_notify(struct btc_coexist *btcoexist, 3605 u8 *tmp_buf, u8 length) 3606 { 3607 struct rtl_priv *rtlpriv = btcoexist->adapter; 3608 u8 bt_info = 0; 3609 u8 i, rsp_source = 0; 3610 bool bt_busy = false, limited_dig = false; 3611 bool wifi_connected = false; 3612 3613 coex_sta->c2h_bt_info_req_sent = false; 3614 3615 rsp_source = tmp_buf[0] & 0xf; 3616 if (rsp_source >= BT_INFO_SRC_8192E_2ANT_MAX) 3617 rsp_source = BT_INFO_SRC_8192E_2ANT_WIFI_FW; 3618 coex_sta->bt_info_c2h_cnt[rsp_source]++; 3619 3620 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3621 "[BTCoex], Bt info[%d], length=%d, hex data = [", 3622 rsp_source, length); 3623 for (i = 0; i < length; i++) { 3624 coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; 3625 if (i == 1) 3626 bt_info = tmp_buf[i]; 3627 if (i == length-1) 3628 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3629 "0x%02x]\n", tmp_buf[i]); 3630 else 3631 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3632 "0x%02x, ", tmp_buf[i]); 3633 } 3634 3635 if (BT_INFO_SRC_8192E_2ANT_WIFI_FW != rsp_source) { 3636 coex_sta->bt_retry_cnt = /* [3:0] */ 3637 coex_sta->bt_info_c2h[rsp_source][2] & 0xf; 3638 3639 coex_sta->bt_rssi = 3640 coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; 3641 3642 coex_sta->bt_info_ext = 3643 coex_sta->bt_info_c2h[rsp_source][4]; 3644 3645 /* Here we need to resend some wifi info to BT 3646 * because bt is reset and loss of the info. 3647 */ 3648 if ((coex_sta->bt_info_ext & BIT1)) { 3649 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3650 "bit1, send wifi BW&Chnl to BT!!\n"); 3651 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, 3652 &wifi_connected); 3653 if (wifi_connected) 3654 ex_halbtc8192e2ant_media_status_notify( 3655 btcoexist, 3656 BTC_MEDIA_CONNECT); 3657 else 3658 ex_halbtc8192e2ant_media_status_notify( 3659 btcoexist, 3660 BTC_MEDIA_DISCONNECT); 3661 } 3662 3663 if ((coex_sta->bt_info_ext & BIT3)) { 3664 if (!btcoexist->manual_control && 3665 !btcoexist->stop_coex_dm) { 3666 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3667 "bit3, BT NOT ignore Wlan active!\n"); 3668 halbtc8192e2ant_IgnoreWlanAct(btcoexist, 3669 FORCE_EXEC, 3670 false); 3671 } 3672 } else { 3673 /* BT already NOT ignore Wlan active, 3674 * do nothing here. 3675 */ 3676 } 3677 3678 #if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0) 3679 if ((coex_sta->bt_info_ext & BIT4)) { 3680 /* BT auto report already enabled, do nothing */ 3681 } else { 3682 halbtc8192e2ant_bt_autoreport(btcoexist, FORCE_EXEC, 3683 true); 3684 } 3685 #endif 3686 } 3687 3688 /* check BIT2 first ==> check if bt is under inquiry or page scan */ 3689 if (bt_info & BT_INFO_8192E_2ANT_B_INQ_PAGE) 3690 coex_sta->c2h_bt_inquiry_page = true; 3691 else 3692 coex_sta->c2h_bt_inquiry_page = false; 3693 3694 /* set link exist status */ 3695 if (!(bt_info&BT_INFO_8192E_2ANT_B_CONNECTION)) { 3696 coex_sta->bt_link_exist = false; 3697 coex_sta->pan_exist = false; 3698 coex_sta->a2dp_exist = false; 3699 coex_sta->hid_exist = false; 3700 coex_sta->sco_exist = false; 3701 } else {/* connection exists */ 3702 coex_sta->bt_link_exist = true; 3703 if (bt_info & BT_INFO_8192E_2ANT_B_FTP) 3704 coex_sta->pan_exist = true; 3705 else 3706 coex_sta->pan_exist = false; 3707 if (bt_info & BT_INFO_8192E_2ANT_B_A2DP) 3708 coex_sta->a2dp_exist = true; 3709 else 3710 coex_sta->a2dp_exist = false; 3711 if (bt_info & BT_INFO_8192E_2ANT_B_HID) 3712 coex_sta->hid_exist = true; 3713 else 3714 coex_sta->hid_exist = false; 3715 if (bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO) 3716 coex_sta->sco_exist = true; 3717 else 3718 coex_sta->sco_exist = false; 3719 } 3720 3721 halbtc8192e2ant_update_btlink_info(btcoexist); 3722 3723 if (!(bt_info&BT_INFO_8192E_2ANT_B_CONNECTION)) { 3724 coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE; 3725 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3726 "[BTCoex], BT Non-Connected idle!!!\n"); 3727 } else if (bt_info == BT_INFO_8192E_2ANT_B_CONNECTION) { 3728 coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE; 3729 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3730 "[BTCoex], bt_infoNotify(), BT Connected-idle!!!\n"); 3731 } else if ((bt_info&BT_INFO_8192E_2ANT_B_SCO_ESCO) || 3732 (bt_info&BT_INFO_8192E_2ANT_B_SCO_BUSY)) { 3733 coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_SCO_BUSY; 3734 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3735 "[BTCoex], bt_infoNotify(), BT SCO busy!!!\n"); 3736 } else if (bt_info&BT_INFO_8192E_2ANT_B_ACL_BUSY) { 3737 coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_ACL_BUSY; 3738 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3739 "[BTCoex], bt_infoNotify(), BT ACL busy!!!\n"); 3740 } else { 3741 coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_MAX; 3742 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3743 "[BTCoex]bt_infoNotify(), BT Non-Defined state!!!\n"); 3744 } 3745 3746 if ((BT_8192E_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || 3747 (BT_8192E_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || 3748 (BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) { 3749 bt_busy = true; 3750 limited_dig = true; 3751 } else { 3752 bt_busy = false; 3753 limited_dig = false; 3754 } 3755 3756 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); 3757 3758 coex_dm->limited_dig = limited_dig; 3759 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig); 3760 3761 halbtc8192e2ant_run_coexist_mechanism(btcoexist); 3762 } 3763 3764 void ex_halbtc8192e2ant_stack_operation_notify(struct btc_coexist *btcoexist, 3765 u8 type) 3766 { 3767 } 3768 3769 void ex_halbtc8192e2ant_halt_notify(struct btc_coexist *btcoexist) 3770 { 3771 struct rtl_priv *rtlpriv = btcoexist->adapter; 3772 3773 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, "[BTCoex], Halt notify\n"); 3774 3775 halbtc8192e2ant_IgnoreWlanAct(btcoexist, FORCE_EXEC, true); 3776 ex_halbtc8192e2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); 3777 } 3778 3779 void ex_halbtc8192e2ant_periodical(struct btc_coexist *btcoexist) 3780 { 3781 struct rtl_priv *rtlpriv = btcoexist->adapter; 3782 static u8 dis_ver_info_cnt; 3783 u32 fw_ver = 0, bt_patch_ver = 0; 3784 struct btc_board_info *board_info = &btcoexist->board_info; 3785 struct btc_stack_info *stack_info = &btcoexist->stack_info; 3786 3787 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3788 "=======================Periodical=======================\n"); 3789 if (dis_ver_info_cnt <= 5) { 3790 dis_ver_info_cnt += 1; 3791 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3792 "************************************************\n"); 3793 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3794 "Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n", 3795 board_info->pg_ant_num, board_info->btdm_ant_num, 3796 board_info->btdm_ant_pos); 3797 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3798 "BT stack/ hci ext ver = %s / %d\n", 3799 ((stack_info->profile_notified) ? "Yes" : "No"), 3800 stack_info->hci_version); 3801 btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, 3802 &bt_patch_ver); 3803 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); 3804 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3805 "CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n", 3806 glcoex_ver_date_8192e_2ant, glcoex_ver_8192e_2ant, 3807 fw_ver, bt_patch_ver, bt_patch_ver); 3808 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 3809 "************************************************\n"); 3810 } 3811 3812 #if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0) 3813 halbtc8192e2ant_querybt_info(btcoexist); 3814 halbtc8192e2ant_monitor_bt_ctr(btcoexist); 3815 btc8192e2ant_monitor_bt_enable_dis(btcoexist); 3816 #else 3817 if (halbtc8192e2ant_iswifi_status_changed(btcoexist) || 3818 coex_dm->auto_tdma_adjust) 3819 halbtc8192e2ant_run_coexist_mechanism(btcoexist); 3820 #endif 3821 } 3822