1 /* 2 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * Register definitions taken from original Realtek rtl8723au driver 14 */ 15 16 /* 0x0000 ~ 0x00FF System Configuration */ 17 #define REG_SYS_ISO_CTRL 0x0000 18 #define SYS_ISO_MD2PP BIT(0) 19 #define SYS_ISO_ANALOG_IPS BIT(5) 20 #define SYS_ISO_DIOR BIT(9) 21 #define SYS_ISO_PWC_EV25V BIT(14) 22 #define SYS_ISO_PWC_EV12V BIT(15) 23 24 #define REG_SYS_FUNC 0x0002 25 #define SYS_FUNC_BBRSTB BIT(0) 26 #define SYS_FUNC_BB_GLB_RSTN BIT(1) 27 #define SYS_FUNC_USBA BIT(2) 28 #define SYS_FUNC_UPLL BIT(3) 29 #define SYS_FUNC_USBD BIT(4) 30 #define SYS_FUNC_DIO_PCIE BIT(5) 31 #define SYS_FUNC_PCIEA BIT(6) 32 #define SYS_FUNC_PPLL BIT(7) 33 #define SYS_FUNC_PCIED BIT(8) 34 #define SYS_FUNC_DIOE BIT(9) 35 #define SYS_FUNC_CPU_ENABLE BIT(10) 36 #define SYS_FUNC_DCORE BIT(11) 37 #define SYS_FUNC_ELDR BIT(12) 38 #define SYS_FUNC_DIO_RF BIT(13) 39 #define SYS_FUNC_HWPDN BIT(14) 40 #define SYS_FUNC_MREGEN BIT(15) 41 42 #define REG_APS_FSMCO 0x0004 43 #define APS_FSMCO_PFM_ALDN BIT(1) 44 #define APS_FSMCO_PFM_WOWL BIT(3) 45 #define APS_FSMCO_ENABLE_POWERDOWN BIT(4) 46 #define APS_FSMCO_MAC_ENABLE BIT(8) 47 #define APS_FSMCO_MAC_OFF BIT(9) 48 #define APS_FSMCO_SW_LPS BIT(10) 49 #define APS_FSMCO_HW_SUSPEND BIT(11) 50 #define APS_FSMCO_PCIE BIT(12) 51 #define APS_FSMCO_HW_POWERDOWN BIT(15) 52 #define APS_FSMCO_WLON_RESET BIT(16) 53 54 #define REG_SYS_CLKR 0x0008 55 #define SYS_CLK_ANAD16V_ENABLE BIT(0) 56 #define SYS_CLK_ANA8M BIT(1) 57 #define SYS_CLK_MACSLP BIT(4) 58 #define SYS_CLK_LOADER_ENABLE BIT(5) 59 #define SYS_CLK_80M_SSC_DISABLE BIT(7) 60 #define SYS_CLK_80M_SSC_ENABLE_HO BIT(8) 61 #define SYS_CLK_PHY_SSC_RSTB BIT(9) 62 #define SYS_CLK_SEC_CLK_ENABLE BIT(10) 63 #define SYS_CLK_MAC_CLK_ENABLE BIT(11) 64 #define SYS_CLK_ENABLE BIT(12) 65 #define SYS_CLK_RING_CLK_ENABLE BIT(13) 66 67 #define REG_9346CR 0x000a 68 #define EEPROM_BOOT BIT(4) 69 #define EEPROM_ENABLE BIT(5) 70 71 #define REG_EE_VPD 0x000c 72 #define REG_AFE_MISC 0x0010 73 #define AFE_MISC_WL_XTAL_CTRL BIT(6) 74 75 #define REG_SPS0_CTRL 0x0011 76 #define REG_SPS_OCP_CFG 0x0018 77 #define REG_8192E_LDOV12_CTRL 0x0014 78 #define REG_RSV_CTRL 0x001c 79 80 #define REG_RF_CTRL 0x001f 81 #define RF_ENABLE BIT(0) 82 #define RF_RSTB BIT(1) 83 #define RF_SDMRSTB BIT(2) 84 85 #define REG_LDOA15_CTRL 0x0020 86 #define LDOA15_ENABLE BIT(0) 87 #define LDOA15_STANDBY BIT(1) 88 #define LDOA15_OBUF BIT(2) 89 #define LDOA15_REG_VOS BIT(3) 90 #define LDOA15_VOADJ_SHIFT 4 91 92 #define REG_LDOV12D_CTRL 0x0021 93 #define LDOV12D_ENABLE BIT(0) 94 #define LDOV12D_STANDBY BIT(1) 95 #define LDOV12D_VADJ_SHIFT 4 96 97 #define REG_LDOHCI12_CTRL 0x0022 98 99 #define REG_LPLDO_CTRL 0x0023 100 #define LPLDO_HSM BIT(2) 101 #define LPLDO_LSM_DIS BIT(3) 102 103 #define REG_AFE_XTAL_CTRL 0x0024 104 #define AFE_XTAL_ENABLE BIT(0) 105 #define AFE_XTAL_B_SELECT BIT(1) 106 #define AFE_XTAL_GATE_USB BIT(8) 107 #define AFE_XTAL_GATE_AFE BIT(11) 108 #define AFE_XTAL_RF_GATE BIT(14) 109 #define AFE_XTAL_GATE_DIG BIT(17) 110 #define AFE_XTAL_BT_GATE BIT(20) 111 112 /* 113 * 0x0028 is also known as REG_AFE_CTRL2 on 8723bu/8192eu 114 */ 115 #define REG_AFE_PLL_CTRL 0x0028 116 #define AFE_PLL_ENABLE BIT(0) 117 #define AFE_PLL_320_ENABLE BIT(1) 118 #define APE_PLL_FREF_SELECT BIT(2) 119 #define AFE_PLL_EDGE_SELECT BIT(3) 120 #define AFE_PLL_WDOGB BIT(4) 121 #define AFE_PLL_LPF_ENABLE BIT(5) 122 123 #define REG_MAC_PHY_CTRL 0x002c 124 125 #define REG_EFUSE_CTRL 0x0030 126 #define REG_EFUSE_TEST 0x0034 127 #define EFUSE_TRPT BIT(7) 128 /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ 129 #define EFUSE_CELL_SEL (BIT(8) | BIT(9)) 130 #define EFUSE_LDOE25_ENABLE BIT(31) 131 #define EFUSE_SELECT_MASK 0x0300 132 #define EFUSE_WIFI_SELECT 0x0000 133 #define EFUSE_BT0_SELECT 0x0100 134 #define EFUSE_BT1_SELECT 0x0200 135 #define EFUSE_BT2_SELECT 0x0300 136 137 #define EFUSE_ACCESS_ENABLE 0x69 /* RTL8723 only */ 138 #define EFUSE_ACCESS_DISABLE 0x00 /* RTL8723 only */ 139 140 #define REG_PWR_DATA 0x0038 141 #define PWR_DATA_EEPRPAD_RFE_CTRL_EN BIT(11) 142 143 #define REG_CAL_TIMER 0x003c 144 #define REG_ACLK_MON 0x003e 145 #define REG_GPIO_MUXCFG 0x0040 146 #define REG_GPIO_IO_SEL 0x0042 147 #define REG_MAC_PINMUX_CFG 0x0043 148 #define REG_GPIO_PIN_CTRL 0x0044 149 #define REG_GPIO_INTM 0x0048 150 #define GPIO_INTM_EDGE_TRIG_IRQ BIT(9) 151 152 #define REG_LEDCFG0 0x004c 153 #define LEDCFG0_DPDT_SELECT BIT(23) 154 #define REG_LEDCFG1 0x004d 155 #define REG_LEDCFG2 0x004e 156 #define LEDCFG2_DPDT_SELECT BIT(7) 157 #define REG_LEDCFG3 0x004f 158 #define REG_LEDCFG REG_LEDCFG2 159 #define REG_FSIMR 0x0050 160 #define REG_FSISR 0x0054 161 #define REG_HSIMR 0x0058 162 #define REG_HSISR 0x005c 163 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ 164 #define REG_GPIO_PIN_CTRL_2 0x0060 165 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ 166 #define REG_GPIO_IO_SEL_2 0x0062 167 #define GPIO_IO_SEL_2_GPIO09_INPUT BIT(1) 168 #define GPIO_IO_SEL_2_GPIO09_IRQ BIT(9) 169 170 /* RTL8723B */ 171 #define REG_PAD_CTRL1 0x0064 172 #define PAD_CTRL1_SW_DPDT_SEL_DATA BIT(0) 173 174 /* RTL8723 only WIFI/BT/GPS Multi-Function control source. */ 175 #define REG_MULTI_FUNC_CTRL 0x0068 176 177 #define MULTI_FN_WIFI_HW_PWRDOWN_EN BIT(0) /* Enable GPIO[9] as WiFi HW 178 powerdown source */ 179 #define MULTI_FN_WIFI_HW_PWRDOWN_SL BIT(1) /* WiFi HW powerdown polarity 180 control */ 181 #define MULTI_WIFI_FUNC_EN BIT(2) /* WiFi function enable */ 182 183 #define MULTI_WIFI_HW_ROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW 184 powerdown source */ 185 #define MULTI_BT_HW_PWRDOWN_EN BIT(16) /* Enable GPIO[11] as BT HW 186 powerdown source */ 187 #define MULTI_BT_HW_PWRDOWN_SL BIT(17) /* BT HW powerdown polarity 188 control */ 189 #define MULTI_BT_FUNC_EN BIT(18) /* BT function enable */ 190 #define MULTI_BT_HW_ROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS 191 RF HW powerdown source */ 192 #define MULTI_GPS_HW_PWRDOWN_EN BIT(20) /* Enable GPIO[10] as GPS HW 193 powerdown source */ 194 #define MULTI_GPS_HW_PWRDOWN_SL BIT(21) /* GPS HW powerdown polarity 195 control */ 196 #define MULTI_GPS_FUNC_EN BIT(22) /* GPS function enable */ 197 198 #define REG_AFE_CTRL4 0x0078 /* 8192eu/8723bu */ 199 #define REG_LDO_SW_CTRL 0x007c /* 8192eu */ 200 201 #define REG_MCU_FW_DL 0x0080 202 #define MCU_FW_DL_ENABLE BIT(0) 203 #define MCU_FW_DL_READY BIT(1) 204 #define MCU_FW_DL_CSUM_REPORT BIT(2) 205 #define MCU_MAC_INIT_READY BIT(3) 206 #define MCU_BB_INIT_READY BIT(4) 207 #define MCU_RF_INIT_READY BIT(5) 208 #define MCU_WINT_INIT_READY BIT(6) 209 #define MCU_FW_RAM_SEL BIT(7) /* 1: RAM, 0:ROM */ 210 #define MCU_CP_RESET BIT(23) 211 212 #define REG_HMBOX_EXT_0 0x0088 213 #define REG_HMBOX_EXT_1 0x008a 214 #define REG_HMBOX_EXT_2 0x008c 215 #define REG_HMBOX_EXT_3 0x008e 216 217 /* Interrupt registers for 8192e/8723bu/8812 */ 218 #define REG_HIMR0 0x00b0 219 #define IMR0_TXCCK BIT(30) /* TXRPT interrupt when CCX bit 220 of the packet is set */ 221 #define IMR0_PSTIMEOUT BIT(29) /* Power Save Time Out Int */ 222 #define IMR0_GTINT4 BIT(28) /* Set when GTIMER4 expires */ 223 #define IMR0_GTINT3 BIT(27) /* Set when GTIMER3 expires */ 224 #define IMR0_TBDER BIT(26) /* Transmit Beacon0 Error */ 225 #define IMR0_TBDOK BIT(25) /* Transmit Beacon0 OK */ 226 #define IMR0_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle 227 indication interrupt */ 228 #define IMR0_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */ 229 #define IMR0_BCNDERR0 BIT(16) /* Beacon Queue DMA Error 0 */ 230 #define IMR0_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & 231 HSISR is true) */ 232 #define IMR0_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt 233 Extension for Win7 */ 234 #define IMR0_ATIMEND BIT(12) /* CTWidnow End or 235 ATIM Window End */ 236 #define IMR0_HISR1_IND_INT BIT(11) /* HISR1 Indicator 237 (HISR1 & HIMR1 is true) */ 238 #define IMR0_C2HCMD BIT(10) /* CPU to Host Command INT 239 Status, Write 1 to clear */ 240 #define IMR0_CPWM2 BIT(9) /* CPU power Mode exchange INT 241 Status, Write 1 to clear */ 242 #define IMR0_CPWM BIT(8) /* CPU power Mode exchange INT 243 Status, Write 1 to clear */ 244 #define IMR0_HIGHDOK BIT(7) /* High Queue DMA OK */ 245 #define IMR0_MGNTDOK BIT(6) /* Management Queue DMA OK */ 246 #define IMR0_BKDOK BIT(5) /* AC_BK DMA OK */ 247 #define IMR0_BEDOK BIT(4) /* AC_BE DMA OK */ 248 #define IMR0_VIDOK BIT(3) /* AC_VI DMA OK */ 249 #define IMR0_VODOK BIT(2) /* AC_VO DMA OK */ 250 #define IMR0_RDU BIT(1) /* Rx Descriptor Unavailable */ 251 #define IMR0_ROK BIT(0) /* Receive DMA OK */ 252 #define REG_HISR0 0x00b4 253 #define REG_HIMR1 0x00b8 254 #define IMR1_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */ 255 #define IMR1_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */ 256 #define IMR1_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */ 257 #define IMR1_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */ 258 #define IMR1_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */ 259 #define IMR1_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */ 260 #define IMR1_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */ 261 #define IMR1_BCNDERR7 BIT(20) /* Beacon Queue DMA Err Int 7 */ 262 #define IMR1_BCNDERR6 BIT(19) /* Beacon Queue DMA Err Int 6 */ 263 #define IMR1_BCNDERR5 BIT(18) /* Beacon Queue DMA Err Int 5 */ 264 #define IMR1_BCNDERR4 BIT(17) /* Beacon Queue DMA Err Int 4 */ 265 #define IMR1_BCNDERR3 BIT(16) /* Beacon Queue DMA Err Int 3 */ 266 #define IMR1_BCNDERR2 BIT(15) /* Beacon Queue DMA Err Int 2 */ 267 #define IMR1_BCNDERR1 BIT(14) /* Beacon Queue DMA Err Int 1 */ 268 #define IMR1_ATIMEND_E BIT(13) /* ATIM Window End Extension 269 for Win7 */ 270 #define IMR1_TXERR BIT(11) /* Tx Error Flag Int Status, 271 write 1 to clear */ 272 #define IMR1_RXERR BIT(10) /* Rx Error Flag Int Status, 273 write 1 to clear */ 274 #define IMR1_TXFOVW BIT(9) /* Transmit FIFO Overflow */ 275 #define IMR1_RXFOVW BIT(8) /* Receive FIFO Overflow */ 276 #define REG_HISR1 0x00bc 277 278 /* Host suspend counter on FPGA platform */ 279 #define REG_HOST_SUSP_CNT 0x00bc 280 /* Efuse access protection for RTL8723 */ 281 #define REG_EFUSE_ACCESS 0x00cf 282 #define REG_BIST_SCAN 0x00d0 283 #define REG_BIST_RPT 0x00d4 284 #define REG_BIST_ROM_RPT 0x00d8 285 #define REG_USB_SIE_INTF 0x00e0 286 #define REG_PCIE_MIO_INTF 0x00e4 287 #define REG_PCIE_MIO_INTD 0x00e8 288 #define REG_HPON_FSM 0x00ec 289 #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23)) 290 #define HPON_FSM_BONDING_1T2R BIT(22) 291 #define REG_SYS_CFG 0x00f0 292 #define SYS_CFG_XCLK_VLD BIT(0) 293 #define SYS_CFG_ACLK_VLD BIT(1) 294 #define SYS_CFG_UCLK_VLD BIT(2) 295 #define SYS_CFG_PCLK_VLD BIT(3) 296 #define SYS_CFG_PCIRSTB BIT(4) 297 #define SYS_CFG_V15_VLD BIT(5) 298 #define SYS_CFG_TRP_B15V_EN BIT(7) 299 #define SYS_CFG_SW_OFFLOAD_EN BIT(7) /* For chips with IOL support */ 300 #define SYS_CFG_SIC_IDLE BIT(8) 301 #define SYS_CFG_BD_MAC2 BIT(9) 302 #define SYS_CFG_BD_MAC1 BIT(10) 303 #define SYS_CFG_IC_MACPHY_MODE BIT(11) 304 #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15)) 305 #define SYS_CFG_BT_FUNC BIT(16) 306 #define SYS_CFG_VENDOR_ID BIT(19) 307 #define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19)) 308 #define SYS_CFG_VENDOR_ID_TSMC 0 309 #define SYS_CFG_VENDOR_ID_SMIC BIT(18) 310 #define SYS_CFG_VENDOR_ID_UMC BIT(19) 311 #define SYS_CFG_PAD_HWPD_IDN BIT(22) 312 #define SYS_CFG_TRP_VAUX_EN BIT(23) 313 #define SYS_CFG_TRP_BT_EN BIT(24) 314 #define SYS_CFG_SPS_LDO_SEL BIT(24) /* 8192eu */ 315 #define SYS_CFG_BD_PKG_SEL BIT(25) 316 #define SYS_CFG_BD_HCI_SEL BIT(26) 317 #define SYS_CFG_TYPE_ID BIT(27) 318 #define SYS_CFG_RTL_ID BIT(23) /* TestChip ID, 319 1:Test(RLE); 0:MP(RL) */ 320 #define SYS_CFG_SPS_SEL BIT(24) /* 1:LDO regulator mode; 321 0:Switching regulator mode*/ 322 #define SYS_CFG_CHIP_VERSION_MASK 0xf000 /* Bit 12 - 15 */ 323 #define SYS_CFG_CHIP_VERSION_SHIFT 12 324 325 #define REG_GPIO_OUTSTS 0x00f4 /* For RTL8723 only. */ 326 #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1)) 327 #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3)) 328 #define GPIO_HCI_SEL (BIT(4) | BIT(5)) 329 #define GPIO_PKG_SEL_HCI BIT(6) 330 #define GPIO_FEN_GPS BIT(7) 331 #define GPIO_FEN_BT BIT(8) 332 #define GPIO_FEN_WL BIT(9) 333 #define GPIO_FEN_PCI BIT(10) 334 #define GPIO_FEN_USB BIT(11) 335 #define GPIO_BTRF_HWPDN_N BIT(12) 336 #define GPIO_WLRF_HWPDN_N BIT(13) 337 #define GPIO_PDN_BT_N BIT(14) 338 #define GPIO_PDN_GPS_N BIT(15) 339 #define GPIO_BT_CTL_HWPDN BIT(16) 340 #define GPIO_GPS_CTL_HWPDN BIT(17) 341 #define GPIO_PPHY_SUSB BIT(20) 342 #define GPIO_UPHY_SUSB BIT(21) 343 #define GPIO_PCI_SUSEN BIT(22) 344 #define GPIO_USB_SUSEN BIT(23) 345 #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) 346 347 #define REG_SYS_CFG2 0x00fc /* 8192eu */ 348 349 /* 0x0100 ~ 0x01FF MACTOP General Configuration */ 350 #define REG_CR 0x0100 351 #define CR_HCI_TXDMA_ENABLE BIT(0) 352 #define CR_HCI_RXDMA_ENABLE BIT(1) 353 #define CR_TXDMA_ENABLE BIT(2) 354 #define CR_RXDMA_ENABLE BIT(3) 355 #define CR_PROTOCOL_ENABLE BIT(4) 356 #define CR_SCHEDULE_ENABLE BIT(5) 357 #define CR_MAC_TX_ENABLE BIT(6) 358 #define CR_MAC_RX_ENABLE BIT(7) 359 #define CR_SW_BEACON_ENABLE BIT(8) 360 #define CR_SECURITY_ENABLE BIT(9) 361 #define CR_CALTIMER_ENABLE BIT(10) 362 363 /* Media Status Register */ 364 #define REG_MSR 0x0102 365 #define MSR_LINKTYPE_MASK 0x3 366 #define MSR_LINKTYPE_NONE 0x0 367 #define MSR_LINKTYPE_ADHOC 0x1 368 #define MSR_LINKTYPE_STATION 0x2 369 #define MSR_LINKTYPE_AP 0x3 370 371 #define REG_PBP 0x0104 372 #define PBP_PAGE_SIZE_RX_SHIFT 0 373 #define PBP_PAGE_SIZE_TX_SHIFT 4 374 #define PBP_PAGE_SIZE_64 0x0 375 #define PBP_PAGE_SIZE_128 0x1 376 #define PBP_PAGE_SIZE_256 0x2 377 #define PBP_PAGE_SIZE_512 0x3 378 #define PBP_PAGE_SIZE_1024 0x4 379 380 #define REG_TRXDMA_CTRL 0x010c 381 #define TRXDMA_CTRL_RXDMA_AGG_EN BIT(2) 382 #define TRXDMA_CTRL_VOQ_SHIFT 4 383 #define TRXDMA_CTRL_VIQ_SHIFT 6 384 #define TRXDMA_CTRL_BEQ_SHIFT 8 385 #define TRXDMA_CTRL_BKQ_SHIFT 10 386 #define TRXDMA_CTRL_MGQ_SHIFT 12 387 #define TRXDMA_CTRL_HIQ_SHIFT 14 388 #define TRXDMA_QUEUE_LOW 1 389 #define TRXDMA_QUEUE_NORMAL 2 390 #define TRXDMA_QUEUE_HIGH 3 391 392 #define REG_TRXFF_BNDY 0x0114 393 #define REG_TRXFF_STATUS 0x0118 394 #define REG_RXFF_PTR 0x011c 395 #define REG_HIMR 0x0120 396 #define REG_HISR 0x0124 397 #define REG_HIMRE 0x0128 398 #define REG_HISRE 0x012c 399 #define REG_CPWM 0x012f 400 #define REG_FWIMR 0x0130 401 #define REG_FWISR 0x0134 402 #define REG_PKTBUF_DBG_CTRL 0x0140 403 #define REG_PKTBUF_DBG_DATA_L 0x0144 404 #define REG_PKTBUF_DBG_DATA_H 0x0148 405 406 #define REG_TC0_CTRL 0x0150 407 #define REG_TC1_CTRL 0x0154 408 #define REG_TC2_CTRL 0x0158 409 #define REG_TC3_CTRL 0x015c 410 #define REG_TC4_CTRL 0x0160 411 #define REG_TCUNIT_BASE 0x0164 412 #define REG_MBIST_START 0x0174 413 #define REG_MBIST_DONE 0x0178 414 #define REG_MBIST_FAIL 0x017c 415 #define REG_C2HEVT_MSG_NORMAL 0x01a0 416 /* 8192EU/8723BU/8812 */ 417 #define REG_C2HEVT_CMD_ID_8723B 0x01ae 418 #define REG_C2HEVT_CLEAR 0x01af 419 #define REG_C2HEVT_MSG_TEST 0x01b8 420 #define REG_MCUTST_1 0x01c0 421 #define REG_FMTHR 0x01c8 422 #define REG_HMTFR 0x01cc 423 #define REG_HMBOX_0 0x01d0 424 #define REG_HMBOX_1 0x01d4 425 #define REG_HMBOX_2 0x01d8 426 #define REG_HMBOX_3 0x01dc 427 428 #define REG_LLT_INIT 0x01e0 429 #define LLT_OP_INACTIVE 0x0 430 #define LLT_OP_WRITE (0x1 << 30) 431 #define LLT_OP_READ (0x2 << 30) 432 #define LLT_OP_MASK (0x3 << 30) 433 434 #define REG_BB_ACCEESS_CTRL 0x01e8 435 #define REG_BB_ACCESS_DATA 0x01ec 436 437 #define REG_HMBOX_EXT0_8723B 0x01f0 438 #define REG_HMBOX_EXT1_8723B 0x01f4 439 #define REG_HMBOX_EXT2_8723B 0x01f8 440 #define REG_HMBOX_EXT3_8723B 0x01fc 441 442 /* 0x0200 ~ 0x027F TXDMA Configuration */ 443 #define REG_RQPN 0x0200 444 #define RQPN_HI_PQ_SHIFT 0 445 #define RQPN_LO_PQ_SHIFT 8 446 #define RQPN_PUB_PQ_SHIFT 16 447 #define RQPN_LOAD BIT(31) 448 449 #define REG_FIFOPAGE 0x0204 450 #define REG_TDECTRL 0x0208 451 #define REG_TXDMA_OFFSET_CHK 0x020c 452 #define TXDMA_OFFSET_DROP_DATA_EN BIT(9) 453 #define REG_TXDMA_STATUS 0x0210 454 #define REG_RQPN_NPQ 0x0214 455 #define RQPN_NPQ_SHIFT 0 456 #define RQPN_EPQ_SHIFT 16 457 458 #define REG_AUTO_LLT 0x0224 459 #define AUTO_LLT_INIT_LLT BIT(16) 460 461 #define REG_DWBCN1_CTRL_8723B 0x0228 462 463 /* 0x0280 ~ 0x02FF RXDMA Configuration */ 464 #define REG_RXDMA_AGG_PG_TH 0x0280 /* 0-7 : USB DMA size bits 465 8-14: USB DMA timeout 466 15 : Aggregation enable 467 Only seems to be used 468 on 8723bu/8192eu */ 469 #define RXDMA_USB_AGG_ENABLE BIT(31) 470 #define REG_RXPKT_NUM 0x0284 471 #define RXPKT_NUM_RXDMA_IDLE BIT(17) 472 #define RXPKT_NUM_RW_RELEASE_EN BIT(18) 473 #define REG_RXDMA_STATUS 0x0288 474 475 /* Presumably only found on newer chips such as 8723bu */ 476 #define REG_RX_DMA_CTRL_8723B 0x0286 477 #define REG_RXDMA_PRO_8723B 0x0290 478 479 #define REG_RF_BB_CMD_ADDR 0x02c0 480 #define REG_RF_BB_CMD_DATA 0x02c4 481 482 /* spec version 11 */ 483 /* 0x0400 ~ 0x047F Protocol Configuration */ 484 /* 8192c, 8192d */ 485 #define REG_VOQ_INFO 0x0400 486 #define REG_VIQ_INFO 0x0404 487 #define REG_BEQ_INFO 0x0408 488 #define REG_BKQ_INFO 0x040c 489 /* 8188e, 8723a, 8812a, 8821a, 8192e, 8723b */ 490 #define REG_Q0_INFO 0x400 491 #define REG_Q1_INFO 0x404 492 #define REG_Q2_INFO 0x408 493 #define REG_Q3_INFO 0x40c 494 495 #define REG_MGQ_INFO 0x0410 496 #define REG_HGQ_INFO 0x0414 497 #define REG_BCNQ_INFO 0x0418 498 499 #define REG_CPU_MGQ_INFORMATION 0x041c 500 #define REG_FWHW_TXQ_CTRL 0x0420 501 #define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7) 502 #define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12) 503 504 #define REG_HWSEQ_CTRL 0x0423 505 #define REG_TXPKTBUF_BCNQ_BDNY 0x0424 506 #define REG_TXPKTBUF_MGQ_BDNY 0x0425 507 #define REG_LIFETIME_EN 0x0426 508 #define REG_MULTI_BCNQ_OFFSET 0x0427 509 510 #define REG_SPEC_SIFS 0x0428 511 #define SPEC_SIFS_CCK_MASK 0x00ff 512 #define SPEC_SIFS_CCK_SHIFT 0 513 #define SPEC_SIFS_OFDM_MASK 0xff00 514 #define SPEC_SIFS_OFDM_SHIFT 8 515 516 #define REG_RETRY_LIMIT 0x042a 517 #define RETRY_LIMIT_LONG_SHIFT 0 518 #define RETRY_LIMIT_LONG_MASK 0x003f 519 #define RETRY_LIMIT_SHORT_SHIFT 8 520 #define RETRY_LIMIT_SHORT_MASK 0x3f00 521 522 #define REG_DARFRC 0x0430 523 #define REG_RARFRC 0x0438 524 #define REG_RESPONSE_RATE_SET 0x0440 525 #define RESPONSE_RATE_BITMAP_ALL 0xfffff 526 #define RESPONSE_RATE_RRSR_CCK_ONLY_1M 0xffff1 527 #define RSR_1M BIT(0) 528 #define RSR_2M BIT(1) 529 #define RSR_5_5M BIT(2) 530 #define RSR_11M BIT(3) 531 #define RSR_6M BIT(4) 532 #define RSR_9M BIT(5) 533 #define RSR_12M BIT(6) 534 #define RSR_18M BIT(7) 535 #define RSR_24M BIT(8) 536 #define RSR_36M BIT(9) 537 #define RSR_48M BIT(10) 538 #define RSR_54M BIT(11) 539 #define RSR_MCS0 BIT(12) 540 #define RSR_MCS1 BIT(13) 541 #define RSR_MCS2 BIT(14) 542 #define RSR_MCS3 BIT(15) 543 #define RSR_MCS4 BIT(16) 544 #define RSR_MCS5 BIT(17) 545 #define RSR_MCS6 BIT(18) 546 #define RSR_MCS7 BIT(19) 547 #define RSR_RSC_LOWER_SUB_CHANNEL BIT(21) /* 0x200000 */ 548 #define RSR_RSC_UPPER_SUB_CHANNEL BIT(22) /* 0x400000 */ 549 #define RSR_RSC_BANDWIDTH_40M (RSR_RSC_UPPER_SUB_CHANNEL | \ 550 RSR_RSC_LOWER_SUB_CHANNEL) 551 #define RSR_ACK_SHORT_PREAMBLE BIT(23) 552 553 #define REG_ARFR0 0x0444 554 #define REG_ARFR1 0x0448 555 #define REG_ARFR2 0x044c 556 #define REG_ARFR3 0x0450 557 #define REG_AMPDU_MAX_TIME_8723B 0x0456 558 #define REG_AGGLEN_LMT 0x0458 559 #define REG_AMPDU_MIN_SPACE 0x045c 560 #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045d 561 #define REG_FAST_EDCA_CTRL 0x0460 562 #define REG_RD_RESP_PKT_TH 0x0463 563 #define REG_INIRTS_RATE_SEL 0x0480 564 /* 8723bu */ 565 #define REG_DATA_SUBCHANNEL 0x0483 566 /* 8723au */ 567 #define REG_INIDATA_RATE_SEL 0x0484 568 /* MACID_SLEEP_1/3 for 8723b, 8192e, 8812a, 8821a */ 569 #define REG_MACID_SLEEP_3_8732B 0x0484 570 #define REG_MACID_SLEEP_1_8732B 0x0488 571 572 #define REG_POWER_STATUS 0x04a4 573 #define REG_POWER_STAGE1 0x04b4 574 #define REG_POWER_STAGE2 0x04b8 575 #define REG_AMPDU_BURST_MODE_8723B 0x04bc 576 #define REG_PKT_VO_VI_LIFE_TIME 0x04c0 577 #define REG_PKT_BE_BK_LIFE_TIME 0x04c2 578 #define REG_STBC_SETTING 0x04c4 579 #define REG_QUEUE_CTRL 0x04c6 580 #define REG_HT_SINGLE_AMPDU_8723B 0x04c7 581 #define REG_PROT_MODE_CTRL 0x04c8 582 #define REG_MAX_AGGR_NUM 0x04ca 583 #define REG_RTS_MAX_AGGR_NUM 0x04cb 584 #define REG_BAR_MODE_CTRL 0x04cc 585 #define REG_RA_TRY_RATE_AGG_LMT 0x04cf 586 /* MACID_DROP for 8723a */ 587 #define REG_MACID_DROP_8732A 0x04d0 588 /* EARLY_MODE_CONTROL 8188e */ 589 #define REG_EARLY_MODE_CONTROL_8188E 0x04d0 590 /* MACID_SLEEP_2 for 8723b, 8192e, 8812a, 8821a */ 591 #define REG_MACID_SLEEP_2_8732B 0x04d0 592 #define REG_MACID_SLEEP 0x04d4 593 #define REG_NQOS_SEQ 0x04dc 594 #define REG_QOS_SEQ 0x04de 595 #define REG_NEED_CPU_HANDLE 0x04e0 596 #define REG_PKT_LOSE_RPT 0x04e1 597 #define REG_PTCL_ERR_STATUS 0x04e2 598 #define REG_TX_REPORT_CTRL 0x04ec 599 #define TX_REPORT_CTRL_TIMER_ENABLE BIT(1) 600 601 #define REG_TX_REPORT_TIME 0x04f0 602 #define REG_DUMMY 0x04fc 603 604 /* 0x0500 ~ 0x05FF EDCA Configuration */ 605 #define REG_EDCA_VO_PARAM 0x0500 606 #define REG_EDCA_VI_PARAM 0x0504 607 #define REG_EDCA_BE_PARAM 0x0508 608 #define REG_EDCA_BK_PARAM 0x050c 609 #define EDCA_PARAM_ECW_MIN_SHIFT 8 610 #define EDCA_PARAM_ECW_MAX_SHIFT 12 611 #define EDCA_PARAM_TXOP_SHIFT 16 612 #define REG_BEACON_TCFG 0x0510 613 #define REG_PIFS 0x0512 614 #define REG_RDG_PIFS 0x0513 615 #define REG_SIFS_CCK 0x0514 616 #define REG_SIFS_OFDM 0x0516 617 #define REG_TSFTR_SYN_OFFSET 0x0518 618 #define REG_AGGR_BREAK_TIME 0x051a 619 #define REG_SLOT 0x051b 620 #define REG_TX_PTCL_CTRL 0x0520 621 #define REG_TXPAUSE 0x0522 622 #define REG_DIS_TXREQ_CLR 0x0523 623 #define REG_RD_CTRL 0x0524 624 #define REG_TBTT_PROHIBIT 0x0540 625 #define REG_RD_NAV_NXT 0x0544 626 #define REG_NAV_PROT_LEN 0x0546 627 628 #define REG_BEACON_CTRL 0x0550 629 #define REG_BEACON_CTRL_1 0x0551 630 #define BEACON_ATIM BIT(0) 631 #define BEACON_CTRL_MBSSID BIT(1) 632 #define BEACON_CTRL_TX_BEACON_RPT BIT(2) 633 #define BEACON_FUNCTION_ENABLE BIT(3) 634 #define BEACON_DISABLE_TSF_UPDATE BIT(4) 635 636 #define REG_MBID_NUM 0x0552 637 #define REG_DUAL_TSF_RST 0x0553 638 #define DUAL_TSF_RESET_TSF0 BIT(0) 639 #define DUAL_TSF_RESET_TSF1 BIT(1) 640 #define DUAL_TSF_RESET_P2P BIT(4) 641 #define DUAL_TSF_TX_OK BIT(5) 642 643 /* The same as REG_MBSSID_BCN_SPACE */ 644 #define REG_BCN_INTERVAL 0x0554 645 #define REG_MBSSID_BCN_SPACE 0x0554 646 647 #define REG_DRIVER_EARLY_INT 0x0558 648 #define DRIVER_EARLY_INT_TIME 5 649 650 #define REG_BEACON_DMA_TIME 0x0559 651 #define BEACON_DMA_ATIME_INT_TIME 2 652 653 #define REG_ATIMWND 0x055a 654 #define REG_USTIME_TSF_8723B 0x055c 655 #define REG_BCN_MAX_ERR 0x055d 656 #define REG_RXTSF_OFFSET_CCK 0x055e 657 #define REG_RXTSF_OFFSET_OFDM 0x055f 658 #define REG_TSFTR 0x0560 659 #define REG_TSFTR1 0x0568 660 #define REG_INIT_TSFTR 0x0564 661 #define REG_ATIMWND_1 0x0570 662 #define REG_PSTIMER 0x0580 663 #define REG_TIMER0 0x0584 664 #define REG_TIMER1 0x0588 665 #define REG_ACM_HW_CTRL 0x05c0 666 #define ACM_HW_CTRL_BK BIT(0) 667 #define ACM_HW_CTRL_BE BIT(1) 668 #define ACM_HW_CTRL_VI BIT(2) 669 #define ACM_HW_CTRL_VO BIT(3) 670 #define REG_ACM_RST_CTRL 0x05c1 671 #define REG_ACMAVG 0x05c2 672 #define REG_VO_ADMTIME 0x05c4 673 #define REG_VI_ADMTIME 0x05c6 674 #define REG_BE_ADMTIME 0x05c8 675 #define REG_EDCA_RANDOM_GEN 0x05cc 676 #define REG_SCH_TXCMD 0x05d0 677 678 /* define REG_FW_TSF_SYNC_CNT 0x04a0 */ 679 #define REG_SCH_TX_CMD 0x05f8 680 #define REG_FW_RESET_TSF_CNT_1 0x05fc 681 #define REG_FW_RESET_TSF_CNT_0 0x05fd 682 #define REG_FW_BCN_DIS_CNT 0x05fe 683 684 /* 0x0600 ~ 0x07FF WMAC Configuration */ 685 #define REG_APSD_CTRL 0x0600 686 #define APSD_CTRL_OFF BIT(6) 687 #define APSD_CTRL_OFF_STATUS BIT(7) 688 #define REG_BW_OPMODE 0x0603 689 #define BW_OPMODE_20MHZ BIT(2) 690 #define BW_OPMODE_5G BIT(1) 691 #define BW_OPMODE_11J BIT(0) 692 693 #define REG_TCR 0x0604 694 695 /* Receive Configuration Register */ 696 #define REG_RCR 0x0608 697 #define RCR_ACCEPT_AP BIT(0) /* Accept all unicast packet */ 698 #define RCR_ACCEPT_PHYS_MATCH BIT(1) /* Accept phys match packet */ 699 #define RCR_ACCEPT_MCAST BIT(2) 700 #define RCR_ACCEPT_BCAST BIT(3) 701 #define RCR_ACCEPT_ADDR3 BIT(4) /* Accept address 3 match 702 packet */ 703 #define RCR_ACCEPT_PM BIT(5) /* Accept power management 704 packet */ 705 #define RCR_CHECK_BSSID_MATCH BIT(6) /* Accept BSSID match packet */ 706 #define RCR_CHECK_BSSID_BEACON BIT(7) /* Accept BSSID match packet 707 (Rx beacon, probe rsp) */ 708 #define RCR_ACCEPT_CRC32 BIT(8) /* Accept CRC32 error packet */ 709 #define RCR_ACCEPT_ICV BIT(9) /* Accept ICV error packet */ 710 #define RCR_ACCEPT_DATA_FRAME BIT(11) /* Accept all data pkt or use 711 REG_RXFLTMAP2 */ 712 #define RCR_ACCEPT_CTRL_FRAME BIT(12) /* Accept all control pkt or use 713 REG_RXFLTMAP1 */ 714 #define RCR_ACCEPT_MGMT_FRAME BIT(13) /* Accept all mgmt pkt or use 715 REG_RXFLTMAP0 */ 716 #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */ 717 #define RCR_UC_DATA_PKT_INT_ENABLE BIT(16) /* Enable unicast data packet 718 interrupt */ 719 #define RCR_BM_DATA_PKT_INT_ENABLE BIT(17) /* Enable broadcast data packet 720 interrupt */ 721 #define RCR_TIM_PARSER_ENABLE BIT(18) /* Enable RX beacon TIM parser*/ 722 #define RCR_MFBEN BIT(22) 723 #define RCR_LSIG_ENABLE BIT(23) /* Enable LSIG TXOP Protection 724 function. Search KEYCAM for 725 each rx packet to check if 726 LSIGEN bit is set. */ 727 #define RCR_MULTI_BSSID_ENABLE BIT(24) /* Enable Multiple BssId */ 728 #define RCR_FORCE_ACK BIT(26) 729 #define RCR_ACCEPT_BA_SSN BIT(27) /* Accept BA SSN */ 730 #define RCR_APPEND_PHYSTAT BIT(28) 731 #define RCR_APPEND_ICV BIT(29) 732 #define RCR_APPEND_MIC BIT(30) 733 #define RCR_APPEND_FCS BIT(31) /* WMAC append FCS after */ 734 735 #define REG_RX_PKT_LIMIT 0x060c 736 #define REG_RX_DLK_TIME 0x060d 737 #define REG_RX_DRVINFO_SZ 0x060f 738 739 #define REG_MACID 0x0610 740 #define REG_BSSID 0x0618 741 #define REG_MAR 0x0620 742 #define REG_MBIDCAMCFG 0x0628 743 744 #define REG_USTIME_EDCA 0x0638 745 #define REG_MAC_SPEC_SIFS 0x063a 746 747 /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ 748 /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ 749 #define REG_R2T_SIFS 0x063c 750 /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ 751 #define REG_T2T_SIFS 0x063e 752 #define REG_ACKTO 0x0640 753 #define REG_CTS2TO 0x0641 754 #define REG_EIFS 0x0642 755 756 /* WMA, BA, CCX */ 757 #define REG_NAV_CTRL 0x0650 758 /* In units of 128us */ 759 #define REG_NAV_UPPER 0x0652 760 #define NAV_UPPER_UNIT 128 761 762 #define REG_BACAMCMD 0x0654 763 #define REG_BACAMCONTENT 0x0658 764 #define REG_LBDLY 0x0660 765 #define REG_FWDLY 0x0661 766 #define REG_RXERR_RPT 0x0664 767 #define REG_WMAC_TRXPTCL_CTL 0x0668 768 #define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8)) 769 #define WMAC_TRXPTCL_CTL_BW_20 0 770 #define WMAC_TRXPTCL_CTL_BW_40 BIT(7) 771 #define WMAC_TRXPTCL_CTL_BW_80 BIT(8) 772 773 /* Security */ 774 #define REG_CAM_CMD 0x0670 775 #define CAM_CMD_POLLING BIT(31) 776 #define CAM_CMD_WRITE BIT(16) 777 #define CAM_CMD_KEY_SHIFT 3 778 #define REG_CAM_WRITE 0x0674 779 #define CAM_WRITE_VALID BIT(15) 780 #define REG_CAM_READ 0x0678 781 #define REG_CAM_DEBUG 0x067c 782 #define REG_SECURITY_CFG 0x0680 783 #define SEC_CFG_TX_USE_DEFKEY BIT(0) 784 #define SEC_CFG_RX_USE_DEFKEY BIT(1) 785 #define SEC_CFG_TX_SEC_ENABLE BIT(2) 786 #define SEC_CFG_RX_SEC_ENABLE BIT(3) 787 #define SEC_CFG_SKBYA2 BIT(4) 788 #define SEC_CFG_NO_SKMC BIT(5) 789 #define SEC_CFG_TXBC_USE_DEFKEY BIT(6) 790 #define SEC_CFG_RXBC_USE_DEFKEY BIT(7) 791 792 /* Power */ 793 #define REG_WOW_CTRL 0x0690 794 #define REG_PSSTATUS 0x0691 795 #define REG_PS_RX_INFO 0x0692 796 #define REG_LPNAV_CTRL 0x0694 797 #define REG_WKFMCAM_CMD 0x0698 798 #define REG_WKFMCAM_RWD 0x069c 799 800 /* 801 * RX Filters: each bit corresponds to the numerical value of the subtype. 802 * If it is set the subtype frame type is passed. The filter is only used when 803 * the RCR_ACCEPT_DATA_FRAME, RCR_ACCEPT_CTRL_FRAME, RCR_ACCEPT_MGMT_FRAME bit 804 * in the RCR are low. 805 * 806 * Example: Beacon subtype is binary 1000 which is decimal 8 so we have to set 807 * bit 8 (0x100) in REG_RXFLTMAP0 to enable reception. 808 */ 809 #define REG_RXFLTMAP0 0x06a0 /* Management frames */ 810 #define REG_RXFLTMAP1 0x06a2 /* Control frames */ 811 #define REG_RXFLTMAP2 0x06a4 /* Data frames */ 812 813 #define REG_BCN_PSR_RPT 0x06a8 814 #define REG_CALB32K_CTRL 0x06ac 815 #define REG_PKT_MON_CTRL 0x06b4 816 #define REG_BT_COEX_TABLE1 0x06c0 817 #define REG_BT_COEX_TABLE2 0x06c4 818 #define REG_BT_COEX_TABLE3 0x06c8 819 #define REG_BT_COEX_TABLE4 0x06cc 820 #define REG_WMAC_RESP_TXINFO 0x06d8 821 822 #define REG_MACID1 0x0700 823 #define REG_BSSID1 0x0708 824 825 /* 826 * This seems to be 8723bu specific 827 */ 828 #define REG_BT_CONTROL_8723BU 0x0764 829 #define BT_CONTROL_BT_GRANT BIT(12) 830 831 #define REG_WLAN_ACT_CONTROL_8723B 0x076e 832 833 #define REG_FPGA0_RF_MODE 0x0800 834 #define FPGA_RF_MODE BIT(0) 835 #define FPGA_RF_MODE_JAPAN BIT(1) 836 #define FPGA_RF_MODE_CCK BIT(24) 837 #define FPGA_RF_MODE_OFDM BIT(25) 838 839 #define REG_FPGA0_TX_INFO 0x0804 840 #define FPGA0_TX_INFO_OFDM_PATH_A BIT(0) 841 #define FPGA0_TX_INFO_OFDM_PATH_B BIT(1) 842 #define FPGA0_TX_INFO_OFDM_PATH_C BIT(2) 843 #define FPGA0_TX_INFO_OFDM_PATH_D BIT(3) 844 #define REG_FPGA0_PSD_FUNC 0x0808 845 #define REG_FPGA0_TX_GAIN 0x080c 846 #define REG_FPGA0_RF_TIMING1 0x0810 847 #define REG_FPGA0_RF_TIMING2 0x0814 848 #define REG_FPGA0_POWER_SAVE 0x0818 849 #define FPGA0_PS_LOWER_CHANNEL BIT(26) 850 #define FPGA0_PS_UPPER_CHANNEL BIT(27) 851 852 #define REG_FPGA0_XA_HSSI_PARM1 0x0820 /* RF 3 wire register */ 853 #define FPGA0_HSSI_PARM1_PI BIT(8) 854 #define REG_FPGA0_XA_HSSI_PARM2 0x0824 855 #define REG_FPGA0_XB_HSSI_PARM1 0x0828 856 #define REG_FPGA0_XB_HSSI_PARM2 0x082c 857 #define FPGA0_HSSI_3WIRE_DATA_LEN 0x800 858 #define FPGA0_HSSI_3WIRE_ADDR_LEN 0x400 859 #define FPGA0_HSSI_PARM2_ADDR_SHIFT 23 860 #define FPGA0_HSSI_PARM2_ADDR_MASK 0x7f800000 /* 0xff << 23 */ 861 #define FPGA0_HSSI_PARM2_CCK_HIGH_PWR BIT(9) 862 #define FPGA0_HSSI_PARM2_EDGE_READ BIT(31) 863 864 #define REG_TX_AGC_B_RATE18_06 0x0830 865 #define REG_TX_AGC_B_RATE54_24 0x0834 866 #define REG_TX_AGC_B_CCK1_55_MCS32 0x0838 867 #define REG_TX_AGC_B_MCS03_MCS00 0x083c 868 869 #define REG_FPGA0_XA_LSSI_PARM 0x0840 870 #define REG_FPGA0_XB_LSSI_PARM 0x0844 871 #define FPGA0_LSSI_PARM_ADDR_SHIFT 20 872 #define FPGA0_LSSI_PARM_ADDR_MASK 0x0ff00000 873 #define FPGA0_LSSI_PARM_DATA_MASK 0x000fffff 874 875 #define REG_TX_AGC_B_MCS07_MCS04 0x0848 876 #define REG_TX_AGC_B_MCS11_MCS08 0x084c 877 878 #define REG_FPGA0_XCD_SWITCH_CTRL 0x085c 879 880 #define REG_FPGA0_XA_RF_INT_OE 0x0860 /* RF Channel switch */ 881 #define REG_FPGA0_XB_RF_INT_OE 0x0864 882 #define FPGA0_INT_OE_ANTENNA_AB_OPEN 0x000 883 #define FPGA0_INT_OE_ANTENNA_A BIT(8) 884 #define FPGA0_INT_OE_ANTENNA_B BIT(9) 885 #define FPGA0_INT_OE_ANTENNA_MASK (FPGA0_INT_OE_ANTENNA_A | \ 886 FPGA0_INT_OE_ANTENNA_B) 887 888 #define REG_TX_AGC_B_MCS15_MCS12 0x0868 889 #define REG_TX_AGC_B_CCK11_A_CCK2_11 0x086c 890 891 #define REG_FPGA0_XAB_RF_SW_CTRL 0x0870 892 #define REG_FPGA0_XA_RF_SW_CTRL 0x0870 /* 16 bit */ 893 #define REG_FPGA0_XB_RF_SW_CTRL 0x0872 /* 16 bit */ 894 #define REG_FPGA0_XCD_RF_SW_CTRL 0x0874 895 #define REG_FPGA0_XC_RF_SW_CTRL 0x0874 /* 16 bit */ 896 #define REG_FPGA0_XD_RF_SW_CTRL 0x0876 /* 16 bit */ 897 #define FPGA0_RF_3WIRE_DATA BIT(0) 898 #define FPGA0_RF_3WIRE_CLOC BIT(1) 899 #define FPGA0_RF_3WIRE_LOAD BIT(2) 900 #define FPGA0_RF_3WIRE_RW BIT(3) 901 #define FPGA0_RF_3WIRE_MASK 0xf 902 #define FPGA0_RF_RFENV BIT(4) 903 #define FPGA0_RF_TRSW BIT(5) /* Useless now */ 904 #define FPGA0_RF_TRSWB BIT(6) 905 #define FPGA0_RF_ANTSW BIT(8) 906 #define FPGA0_RF_ANTSWB BIT(9) 907 #define FPGA0_RF_PAPE BIT(10) 908 #define FPGA0_RF_PAPE5G BIT(11) 909 #define FPGA0_RF_BD_CTRL_SHIFT 16 910 911 #define REG_FPGA0_XAB_RF_PARM 0x0878 /* Antenna select path in ODM */ 912 #define REG_FPGA0_XA_RF_PARM 0x0878 /* 16 bit */ 913 #define REG_FPGA0_XB_RF_PARM 0x087a /* 16 bit */ 914 #define REG_FPGA0_XCD_RF_PARM 0x087c 915 #define REG_FPGA0_XC_RF_PARM 0x087c /* 16 bit */ 916 #define REG_FPGA0_XD_RF_PARM 0x087e /* 16 bit */ 917 #define FPGA0_RF_PARM_RFA_ENABLE BIT(1) 918 #define FPGA0_RF_PARM_RFB_ENABLE BIT(17) 919 #define FPGA0_RF_PARM_CLK_GATE BIT(31) 920 921 #define REG_FPGA0_ANALOG1 0x0880 922 #define REG_FPGA0_ANALOG2 0x0884 923 #define FPGA0_ANALOG2_20MHZ BIT(10) 924 #define REG_FPGA0_ANALOG3 0x0888 925 #define REG_FPGA0_ANALOG4 0x088c 926 927 #define REG_NHM_TH9_TH10_8723B 0x0890 928 #define REG_NHM_TIMER_8723B 0x0894 929 #define REG_NHM_TH3_TO_TH0_8723B 0x0898 930 #define REG_NHM_TH7_TO_TH4_8723B 0x089c 931 932 #define REG_FPGA0_XA_LSSI_READBACK 0x08a0 /* Tranceiver LSSI Readback */ 933 #define REG_FPGA0_XB_LSSI_READBACK 0x08a4 934 #define REG_HSPI_XA_READBACK 0x08b8 /* Transceiver A HSPI read */ 935 #define REG_HSPI_XB_READBACK 0x08bc /* Transceiver B HSPI read */ 936 937 #define REG_FPGA1_RF_MODE 0x0900 938 939 #define REG_FPGA1_TX_INFO 0x090c 940 #define REG_DPDT_CTRL 0x092c /* 8723BU */ 941 #define REG_RFE_CTRL_ANTA_SRC 0x0930 /* 8723BU */ 942 #define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */ 943 #define REG_RFE_BUFFER 0x0944 /* 8723BU */ 944 #define REG_S0S1_PATH_SWITCH 0x0948 /* 8723BU */ 945 946 #define REG_CCK0_SYSTEM 0x0a00 947 #define CCK0_SIDEBAND BIT(4) 948 949 #define REG_CCK0_AFE_SETTING 0x0a04 950 #define CCK0_AFE_RX_MASK 0x0f000000 951 #define CCK0_AFE_RX_ANT_AB BIT(24) 952 #define CCK0_AFE_RX_ANT_A 0 953 #define CCK0_AFE_RX_ANT_B (BIT(24) | BIT(26)) 954 955 #define REG_CONFIG_ANT_A 0x0b68 956 #define REG_CONFIG_ANT_B 0x0b6c 957 958 #define REG_OFDM0_TRX_PATH_ENABLE 0x0c04 959 #define OFDM_RF_PATH_RX_MASK 0x0f 960 #define OFDM_RF_PATH_RX_A BIT(0) 961 #define OFDM_RF_PATH_RX_B BIT(1) 962 #define OFDM_RF_PATH_RX_C BIT(2) 963 #define OFDM_RF_PATH_RX_D BIT(3) 964 #define OFDM_RF_PATH_TX_MASK 0xf0 965 #define OFDM_RF_PATH_TX_A BIT(4) 966 #define OFDM_RF_PATH_TX_B BIT(5) 967 #define OFDM_RF_PATH_TX_C BIT(6) 968 #define OFDM_RF_PATH_TX_D BIT(7) 969 970 #define REG_OFDM0_TR_MUX_PAR 0x0c08 971 972 #define REG_OFDM0_FA_RSTC 0x0c0c 973 974 #define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14 975 #define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c 976 977 #define REG_OFDM0_ENERGY_CCA_THRES 0x0c4c 978 979 #define REG_OFDM0_RX_D_SYNC_PATH 0x0c40 980 #define OFDM0_SYNC_PATH_NOTCH_FILTER BIT(1) 981 982 #define REG_OFDM0_XA_AGC_CORE1 0x0c50 983 #define REG_OFDM0_XA_AGC_CORE2 0x0c54 984 #define REG_OFDM0_XB_AGC_CORE1 0x0c58 985 #define REG_OFDM0_XB_AGC_CORE2 0x0c5c 986 #define REG_OFDM0_XC_AGC_CORE1 0x0c60 987 #define REG_OFDM0_XC_AGC_CORE2 0x0c64 988 #define REG_OFDM0_XD_AGC_CORE1 0x0c68 989 #define REG_OFDM0_XD_AGC_CORE2 0x0c6c 990 #define OFDM0_X_AGC_CORE1_IGI_MASK 0x0000007F 991 992 #define REG_OFDM0_AGC_PARM1 0x0c70 993 994 #define REG_OFDM0_AGCR_SSI_TABLE 0x0c78 995 996 #define REG_OFDM0_XA_TX_IQ_IMBALANCE 0x0c80 997 #define REG_OFDM0_XB_TX_IQ_IMBALANCE 0x0c88 998 #define REG_OFDM0_XC_TX_IQ_IMBALANCE 0x0c90 999 #define REG_OFDM0_XD_TX_IQ_IMBALANCE 0x0c98 1000 1001 #define REG_OFDM0_XC_TX_AFE 0x0c94 1002 #define REG_OFDM0_XD_TX_AFE 0x0c9c 1003 1004 #define REG_OFDM0_RX_IQ_EXT_ANTA 0x0ca0 1005 1006 /* 8723bu */ 1007 #define REG_OFDM0_TX_PSDO_NOISE_WEIGHT 0x0ce4 1008 1009 #define REG_OFDM1_LSTF 0x0d00 1010 #define OFDM_LSTF_PRIME_CH_LOW BIT(10) 1011 #define OFDM_LSTF_PRIME_CH_HIGH BIT(11) 1012 #define OFDM_LSTF_PRIME_CH_MASK (OFDM_LSTF_PRIME_CH_LOW | \ 1013 OFDM_LSTF_PRIME_CH_HIGH) 1014 #define OFDM_LSTF_CONTINUE_TX BIT(28) 1015 #define OFDM_LSTF_SINGLE_CARRIER BIT(29) 1016 #define OFDM_LSTF_SINGLE_TONE BIT(30) 1017 #define OFDM_LSTF_MASK 0x70000000 1018 1019 #define REG_OFDM1_TRX_PATH_ENABLE 0x0d04 1020 1021 #define REG_TX_AGC_A_RATE18_06 0x0e00 1022 #define REG_TX_AGC_A_RATE54_24 0x0e04 1023 #define REG_TX_AGC_A_CCK1_MCS32 0x0e08 1024 #define REG_TX_AGC_A_MCS03_MCS00 0x0e10 1025 #define REG_TX_AGC_A_MCS07_MCS04 0x0e14 1026 #define REG_TX_AGC_A_MCS11_MCS08 0x0e18 1027 #define REG_TX_AGC_A_MCS15_MCS12 0x0e1c 1028 1029 #define REG_FPGA0_IQK 0x0e28 1030 1031 #define REG_TX_IQK_TONE_A 0x0e30 1032 #define REG_RX_IQK_TONE_A 0x0e34 1033 #define REG_TX_IQK_PI_A 0x0e38 1034 #define REG_RX_IQK_PI_A 0x0e3c 1035 1036 #define REG_TX_IQK 0x0e40 1037 #define REG_RX_IQK 0x0e44 1038 #define REG_IQK_AGC_PTS 0x0e48 1039 #define REG_IQK_AGC_RSP 0x0e4c 1040 #define REG_TX_IQK_TONE_B 0x0e50 1041 #define REG_RX_IQK_TONE_B 0x0e54 1042 #define REG_TX_IQK_PI_B 0x0e58 1043 #define REG_RX_IQK_PI_B 0x0e5c 1044 #define REG_IQK_AGC_CONT 0x0e60 1045 1046 #define REG_BLUETOOTH 0x0e6c 1047 #define REG_RX_WAIT_CCA 0x0e70 1048 #define REG_TX_CCK_RFON 0x0e74 1049 #define REG_TX_CCK_BBON 0x0e78 1050 #define REG_TX_OFDM_RFON 0x0e7c 1051 #define REG_TX_OFDM_BBON 0x0e80 1052 #define REG_TX_TO_RX 0x0e84 1053 #define REG_TX_TO_TX 0x0e88 1054 #define REG_RX_CCK 0x0e8c 1055 1056 #define REG_TX_POWER_BEFORE_IQK_A 0x0e94 1057 #define REG_TX_POWER_AFTER_IQK_A 0x0e9c 1058 1059 #define REG_RX_POWER_BEFORE_IQK_A 0x0ea0 1060 #define REG_RX_POWER_BEFORE_IQK_A_2 0x0ea4 1061 #define REG_RX_POWER_AFTER_IQK_A 0x0ea8 1062 #define REG_RX_POWER_AFTER_IQK_A_2 0x0eac 1063 1064 #define REG_TX_POWER_BEFORE_IQK_B 0x0eb4 1065 #define REG_TX_POWER_AFTER_IQK_B 0x0ebc 1066 1067 #define REG_RX_POWER_BEFORE_IQK_B 0x0ec0 1068 #define REG_RX_POWER_BEFORE_IQK_B_2 0x0ec4 1069 #define REG_RX_POWER_AFTER_IQK_B 0x0ec8 1070 #define REG_RX_POWER_AFTER_IQK_B_2 0x0ecc 1071 1072 #define REG_RX_OFDM 0x0ed0 1073 #define REG_RX_WAIT_RIFS 0x0ed4 1074 #define REG_RX_TO_RX 0x0ed8 1075 #define REG_STANDBY 0x0edc 1076 #define REG_SLEEP 0x0ee0 1077 #define REG_PMPD_ANAEN 0x0eec 1078 1079 #define REG_FW_START_ADDRESS 0x1000 1080 1081 #define REG_USB_INFO 0xfe17 1082 #define REG_USB_HIMR 0xfe38 1083 #define USB_HIMR_TIMEOUT2 BIT(31) 1084 #define USB_HIMR_TIMEOUT1 BIT(30) 1085 #define USB_HIMR_PSTIMEOUT BIT(29) 1086 #define USB_HIMR_GTINT4 BIT(28) 1087 #define USB_HIMR_GTINT3 BIT(27) 1088 #define USB_HIMR_TXBCNERR BIT(26) 1089 #define USB_HIMR_TXBCNOK BIT(25) 1090 #define USB_HIMR_TSF_BIT32_TOGGLE BIT(24) 1091 #define USB_HIMR_BCNDMAINT3 BIT(23) 1092 #define USB_HIMR_BCNDMAINT2 BIT(22) 1093 #define USB_HIMR_BCNDMAINT1 BIT(21) 1094 #define USB_HIMR_BCNDMAINT0 BIT(20) 1095 #define USB_HIMR_BCNDOK3 BIT(19) 1096 #define USB_HIMR_BCNDOK2 BIT(18) 1097 #define USB_HIMR_BCNDOK1 BIT(17) 1098 #define USB_HIMR_BCNDOK0 BIT(16) 1099 #define USB_HIMR_HSISR_IND BIT(15) 1100 #define USB_HIMR_BCNDMAINT_E BIT(14) 1101 /* RSVD BIT(13) */ 1102 #define USB_HIMR_CTW_END BIT(12) 1103 /* RSVD BIT(11) */ 1104 #define USB_HIMR_C2HCMD BIT(10) 1105 #define USB_HIMR_CPWM2 BIT(9) 1106 #define USB_HIMR_CPWM BIT(8) 1107 #define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK 1108 Interrupt */ 1109 #define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK 1110 Interrupt */ 1111 #define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */ 1112 #define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */ 1113 #define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */ 1114 #define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */ 1115 #define USB_HIMR_RDU BIT(1) /* Receive Descriptor 1116 Unavailable */ 1117 #define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */ 1118 1119 #define REG_USB_SPECIAL_OPTION 0xfe55 1120 #define USB_SPEC_USB_AGG_ENABLE BIT(3) /* Enable USB aggregation */ 1121 #define USB_SPEC_INT_BULK_SELECT BIT(4) /* Use interrupt endpoint to 1122 deliver interrupt packet. 1123 0: Use int, 1: use bulk */ 1124 #define REG_USB_HRPWM 0xfe58 1125 #define REG_USB_DMA_AGG_TO 0xfe5b 1126 #define REG_USB_AGG_TIMEOUT 0xfe5c 1127 #define REG_USB_AGG_THRESH 0xfe5d 1128 1129 #define REG_NORMAL_SIE_VID 0xfe60 /* 0xfe60 - 0xfe61 */ 1130 #define REG_NORMAL_SIE_PID 0xfe62 /* 0xfe62 - 0xfe63 */ 1131 #define REG_NORMAL_SIE_OPTIONAL 0xfe64 1132 #define REG_NORMAL_SIE_EP 0xfe65 /* 0xfe65 - 0xfe67 */ 1133 #define REG_NORMAL_SIE_EP_TX 0xfe66 1134 #define NORMAL_SIE_EP_TX_HIGH_MASK 0x000f 1135 #define NORMAL_SIE_EP_TX_NORMAL_MASK 0x00f0 1136 #define NORMAL_SIE_EP_TX_LOW_MASK 0x0f00 1137 1138 #define REG_NORMAL_SIE_PHY 0xfe68 /* 0xfe68 - 0xfe6b */ 1139 #define REG_NORMAL_SIE_OPTIONAL2 0xfe6c 1140 #define REG_NORMAL_SIE_GPS_EP 0xfe6d /* RTL8723 only */ 1141 #define REG_NORMAL_SIE_MAC_ADDR 0xfe70 /* 0xfe70 - 0xfe75 */ 1142 #define REG_NORMAL_SIE_STRING 0xfe80 /* 0xfe80 - 0xfedf */ 1143 1144 /* RF6052 registers */ 1145 #define RF6052_REG_AC 0x00 1146 #define RF6052_REG_IQADJ_G1 0x01 1147 #define RF6052_REG_IQADJ_G2 0x02 1148 #define RF6052_REG_BS_PA_APSET_G1_G4 0x03 1149 #define RF6052_REG_BS_PA_APSET_G5_G8 0x04 1150 #define RF6052_REG_POW_TRSW 0x05 1151 #define RF6052_REG_GAIN_RX 0x06 1152 #define RF6052_REG_GAIN_TX 0x07 1153 #define RF6052_REG_TXM_IDAC 0x08 1154 #define RF6052_REG_IPA_G 0x09 1155 #define RF6052_REG_TXBIAS_G 0x0a 1156 #define RF6052_REG_TXPA_AG 0x0b 1157 #define RF6052_REG_IPA_A 0x0c 1158 #define RF6052_REG_TXBIAS_A 0x0d 1159 #define RF6052_REG_BS_PA_APSET_G9_G11 0x0e 1160 #define RF6052_REG_BS_IQGEN 0x0f 1161 #define RF6052_REG_MODE1 0x10 1162 #define RF6052_REG_MODE2 0x11 1163 #define RF6052_REG_RX_AGC_HP 0x12 1164 #define RF6052_REG_TX_AGC 0x13 1165 #define RF6052_REG_BIAS 0x14 1166 #define RF6052_REG_IPA 0x15 1167 #define RF6052_REG_TXBIAS 0x16 1168 #define RF6052_REG_POW_ABILITY 0x17 1169 #define RF6052_REG_MODE_AG 0x18 /* RF channel and BW switch */ 1170 #define MODE_AG_CHANNEL_MASK 0x3ff 1171 #define MODE_AG_CHANNEL_20MHZ BIT(10) 1172 #define MODE_AG_BW_MASK (BIT(10) | BIT(11)) 1173 #define MODE_AG_BW_20MHZ_8723B (BIT(10) | BIT(11)) 1174 #define MODE_AG_BW_40MHZ_8723B BIT(10) 1175 #define MODE_AG_BW_80MHZ_8723B 0 1176 1177 #define RF6052_REG_TOP 0x19 1178 #define RF6052_REG_RX_G1 0x1a 1179 #define RF6052_REG_RX_G2 0x1b 1180 #define RF6052_REG_RX_BB2 0x1c 1181 #define RF6052_REG_RX_BB1 0x1d 1182 #define RF6052_REG_RCK1 0x1e 1183 #define RF6052_REG_RCK2 0x1f 1184 #define RF6052_REG_TX_G1 0x20 1185 #define RF6052_REG_TX_G2 0x21 1186 #define RF6052_REG_TX_G3 0x22 1187 #define RF6052_REG_TX_BB1 0x23 1188 #define RF6052_REG_T_METER 0x24 1189 #define RF6052_REG_SYN_G1 0x25 /* RF TX Power control */ 1190 #define RF6052_REG_SYN_G2 0x26 /* RF TX Power control */ 1191 #define RF6052_REG_SYN_G3 0x27 /* RF TX Power control */ 1192 #define RF6052_REG_SYN_G4 0x28 /* RF TX Power control */ 1193 #define RF6052_REG_SYN_G5 0x29 /* RF TX Power control */ 1194 #define RF6052_REG_SYN_G6 0x2a /* RF TX Power control */ 1195 #define RF6052_REG_SYN_G7 0x2b /* RF TX Power control */ 1196 #define RF6052_REG_SYN_G8 0x2c /* RF TX Power control */ 1197 1198 #define RF6052_REG_RCK_OS 0x30 /* RF TX PA control */ 1199 1200 #define RF6052_REG_TXPA_G1 0x31 /* RF TX PA control */ 1201 #define RF6052_REG_TXPA_G2 0x32 /* RF TX PA control */ 1202 #define RF6052_REG_TXPA_G3 0x33 /* RF TX PA control */ 1203 1204 /* 1205 * NextGen regs: 8723BU 1206 */ 1207 #define RF6052_REG_T_METER_8723B 0x42 1208 #define RF6052_REG_UNKNOWN_43 0x43 1209 #define RF6052_REG_UNKNOWN_55 0x55 1210 #define RF6052_REG_UNKNOWN_56 0x56 1211 #define RF6052_REG_S0S1 0xb0 1212 #define RF6052_REG_UNKNOWN_DF 0xdf 1213 #define RF6052_REG_UNKNOWN_ED 0xed 1214 #define RF6052_REG_WE_LUT 0xef 1215