1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 4 * 5 * Register definitions taken from original Realtek rtl8723au driver 6 */ 7 8 /* 0x0000 ~ 0x00FF System Configuration */ 9 #define REG_SYS_ISO_CTRL 0x0000 10 #define SYS_ISO_MD2PP BIT(0) 11 #define SYS_ISO_ANALOG_IPS BIT(5) 12 #define SYS_ISO_DIOR BIT(9) 13 #define SYS_ISO_PWC_EV25V BIT(14) 14 #define SYS_ISO_PWC_EV12V BIT(15) 15 16 #define REG_SYS_FUNC 0x0002 17 #define SYS_FUNC_BBRSTB BIT(0) 18 #define SYS_FUNC_BB_GLB_RSTN BIT(1) 19 #define SYS_FUNC_USBA BIT(2) 20 #define SYS_FUNC_UPLL BIT(3) 21 #define SYS_FUNC_USBD BIT(4) 22 #define SYS_FUNC_DIO_PCIE BIT(5) 23 #define SYS_FUNC_PCIEA BIT(6) 24 #define SYS_FUNC_PPLL BIT(7) 25 #define SYS_FUNC_PCIED BIT(8) 26 #define SYS_FUNC_DIOE BIT(9) 27 #define SYS_FUNC_CPU_ENABLE BIT(10) 28 #define SYS_FUNC_DCORE BIT(11) 29 #define SYS_FUNC_ELDR BIT(12) 30 #define SYS_FUNC_DIO_RF BIT(13) 31 #define SYS_FUNC_HWPDN BIT(14) 32 #define SYS_FUNC_MREGEN BIT(15) 33 34 #define REG_APS_FSMCO 0x0004 35 #define APS_FSMCO_PFM_ALDN BIT(1) 36 #define APS_FSMCO_PFM_WOWL BIT(3) 37 #define APS_FSMCO_ENABLE_POWERDOWN BIT(4) 38 #define APS_FSMCO_MAC_ENABLE BIT(8) 39 #define APS_FSMCO_MAC_OFF BIT(9) 40 #define APS_FSMCO_SW_LPS BIT(10) 41 #define APS_FSMCO_HW_SUSPEND BIT(11) 42 #define APS_FSMCO_PCIE BIT(12) 43 #define APS_FSMCO_HW_POWERDOWN BIT(15) 44 #define APS_FSMCO_WLON_RESET BIT(16) 45 46 #define REG_SYS_CLKR 0x0008 47 #define SYS_CLK_ANAD16V_ENABLE BIT(0) 48 #define SYS_CLK_ANA8M BIT(1) 49 #define SYS_CLK_MACSLP BIT(4) 50 #define SYS_CLK_LOADER_ENABLE BIT(5) 51 #define SYS_CLK_80M_SSC_DISABLE BIT(7) 52 #define SYS_CLK_80M_SSC_ENABLE_HO BIT(8) 53 #define SYS_CLK_PHY_SSC_RSTB BIT(9) 54 #define SYS_CLK_SEC_CLK_ENABLE BIT(10) 55 #define SYS_CLK_MAC_CLK_ENABLE BIT(11) 56 #define SYS_CLK_ENABLE BIT(12) 57 #define SYS_CLK_RING_CLK_ENABLE BIT(13) 58 59 #define REG_9346CR 0x000a 60 #define EEPROM_BOOT BIT(4) 61 #define EEPROM_ENABLE BIT(5) 62 63 #define REG_EE_VPD 0x000c 64 #define REG_AFE_MISC 0x0010 65 #define AFE_MISC_WL_XTAL_CTRL BIT(6) 66 67 #define REG_SPS0_CTRL 0x0011 68 #define REG_SPS_OCP_CFG 0x0018 69 #define REG_8192E_LDOV12_CTRL 0x0014 70 #define REG_RSV_CTRL 0x001c 71 72 #define REG_RF_CTRL 0x001f 73 #define RF_ENABLE BIT(0) 74 #define RF_RSTB BIT(1) 75 #define RF_SDMRSTB BIT(2) 76 77 #define REG_LDOA15_CTRL 0x0020 78 #define LDOA15_ENABLE BIT(0) 79 #define LDOA15_STANDBY BIT(1) 80 #define LDOA15_OBUF BIT(2) 81 #define LDOA15_REG_VOS BIT(3) 82 #define LDOA15_VOADJ_SHIFT 4 83 84 #define REG_LDOV12D_CTRL 0x0021 85 #define LDOV12D_ENABLE BIT(0) 86 #define LDOV12D_STANDBY BIT(1) 87 #define LDOV12D_VADJ_SHIFT 4 88 89 #define REG_LDOHCI12_CTRL 0x0022 90 91 #define REG_LPLDO_CTRL 0x0023 92 #define LPLDO_HSM BIT(2) 93 #define LPLDO_LSM_DIS BIT(3) 94 95 #define REG_AFE_XTAL_CTRL 0x0024 96 #define AFE_XTAL_ENABLE BIT(0) 97 #define AFE_XTAL_B_SELECT BIT(1) 98 #define AFE_XTAL_GATE_USB BIT(8) 99 #define AFE_XTAL_GATE_AFE BIT(11) 100 #define AFE_XTAL_RF_GATE BIT(14) 101 #define AFE_XTAL_GATE_DIG BIT(17) 102 #define AFE_XTAL_BT_GATE BIT(20) 103 104 /* 105 * 0x0028 is also known as REG_AFE_CTRL2 on 8723bu/8192eu 106 */ 107 #define REG_AFE_PLL_CTRL 0x0028 108 #define AFE_PLL_ENABLE BIT(0) 109 #define AFE_PLL_320_ENABLE BIT(1) 110 #define APE_PLL_FREF_SELECT BIT(2) 111 #define AFE_PLL_EDGE_SELECT BIT(3) 112 #define AFE_PLL_WDOGB BIT(4) 113 #define AFE_PLL_LPF_ENABLE BIT(5) 114 115 #define REG_MAC_PHY_CTRL 0x002c 116 117 #define REG_EFUSE_CTRL 0x0030 118 #define REG_EFUSE_TEST 0x0034 119 #define EFUSE_TRPT BIT(7) 120 /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ 121 #define EFUSE_CELL_SEL (BIT(8) | BIT(9)) 122 #define EFUSE_LDOE25_ENABLE BIT(31) 123 #define EFUSE_SELECT_MASK 0x0300 124 #define EFUSE_WIFI_SELECT 0x0000 125 #define EFUSE_BT0_SELECT 0x0100 126 #define EFUSE_BT1_SELECT 0x0200 127 #define EFUSE_BT2_SELECT 0x0300 128 129 #define EFUSE_ACCESS_ENABLE 0x69 /* RTL8723 only */ 130 #define EFUSE_ACCESS_DISABLE 0x00 /* RTL8723 only */ 131 132 #define REG_PWR_DATA 0x0038 133 #define PWR_DATA_EEPRPAD_RFE_CTRL_EN BIT(11) 134 135 #define REG_CAL_TIMER 0x003c 136 #define REG_ACLK_MON 0x003e 137 #define REG_GPIO_MUXCFG 0x0040 138 #define GPIO_MUXCFG_IO_SEL_ENBT BIT(5) 139 #define REG_GPIO_IO_SEL 0x0042 140 #define REG_MAC_PINMUX_CFG 0x0043 141 #define REG_GPIO_PIN_CTRL 0x0044 142 #define REG_GPIO_INTM 0x0048 143 #define GPIO_INTM_EDGE_TRIG_IRQ BIT(9) 144 145 #define REG_LEDCFG0 0x004c 146 #define LEDCFG0_DPDT_SELECT BIT(23) 147 #define REG_LEDCFG1 0x004d 148 #define REG_LEDCFG2 0x004e 149 #define LEDCFG2_DPDT_SELECT BIT(7) 150 #define REG_LEDCFG3 0x004f 151 #define REG_LEDCFG REG_LEDCFG2 152 #define REG_FSIMR 0x0050 153 #define REG_FSISR 0x0054 154 #define REG_HSIMR 0x0058 155 #define REG_HSISR 0x005c 156 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ 157 #define REG_GPIO_PIN_CTRL_2 0x0060 158 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ 159 #define REG_GPIO_IO_SEL_2 0x0062 160 #define GPIO_IO_SEL_2_GPIO09_INPUT BIT(1) 161 #define GPIO_IO_SEL_2_GPIO09_IRQ BIT(9) 162 163 /* RTL8723B */ 164 #define REG_PAD_CTRL1 0x0064 165 #define PAD_CTRL1_SW_DPDT_SEL_DATA BIT(0) 166 167 /* RTL8723 only WIFI/BT/GPS Multi-Function control source. */ 168 #define REG_MULTI_FUNC_CTRL 0x0068 169 170 #define MULTI_FN_WIFI_HW_PWRDOWN_EN BIT(0) /* Enable GPIO[9] as WiFi HW 171 powerdown source */ 172 #define MULTI_FN_WIFI_HW_PWRDOWN_SL BIT(1) /* WiFi HW powerdown polarity 173 control */ 174 #define MULTI_WIFI_FUNC_EN BIT(2) /* WiFi function enable */ 175 176 #define MULTI_WIFI_HW_ROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW 177 powerdown source */ 178 #define MULTI_BT_HW_PWRDOWN_EN BIT(16) /* Enable GPIO[11] as BT HW 179 powerdown source */ 180 #define MULTI_BT_HW_PWRDOWN_SL BIT(17) /* BT HW powerdown polarity 181 control */ 182 #define MULTI_BT_FUNC_EN BIT(18) /* BT function enable */ 183 #define MULTI_BT_HW_ROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS 184 RF HW powerdown source */ 185 #define MULTI_GPS_HW_PWRDOWN_EN BIT(20) /* Enable GPIO[10] as GPS HW 186 powerdown source */ 187 #define MULTI_GPS_HW_PWRDOWN_SL BIT(21) /* GPS HW powerdown polarity 188 control */ 189 #define MULTI_GPS_FUNC_EN BIT(22) /* GPS function enable */ 190 191 #define REG_AFE_CTRL4 0x0078 /* 8192eu/8723bu */ 192 #define REG_LDO_SW_CTRL 0x007c /* 8192eu */ 193 194 #define REG_MCU_FW_DL 0x0080 195 #define MCU_FW_DL_ENABLE BIT(0) 196 #define MCU_FW_DL_READY BIT(1) 197 #define MCU_FW_DL_CSUM_REPORT BIT(2) 198 #define MCU_MAC_INIT_READY BIT(3) 199 #define MCU_BB_INIT_READY BIT(4) 200 #define MCU_RF_INIT_READY BIT(5) 201 #define MCU_WINT_INIT_READY BIT(6) 202 #define MCU_FW_RAM_SEL BIT(7) /* 1: RAM, 0:ROM */ 203 #define MCU_CP_RESET BIT(23) 204 205 #define REG_HMBOX_EXT_0 0x0088 206 #define REG_HMBOX_EXT_1 0x008a 207 #define REG_HMBOX_EXT_2 0x008c 208 #define REG_HMBOX_EXT_3 0x008e 209 210 /* Interrupt registers for 8192e/8723bu/8812 */ 211 #define REG_HIMR0 0x00b0 212 #define IMR0_TXCCK BIT(30) /* TXRPT interrupt when CCX bit 213 of the packet is set */ 214 #define IMR0_PSTIMEOUT BIT(29) /* Power Save Time Out Int */ 215 #define IMR0_GTINT4 BIT(28) /* Set when GTIMER4 expires */ 216 #define IMR0_GTINT3 BIT(27) /* Set when GTIMER3 expires */ 217 #define IMR0_TBDER BIT(26) /* Transmit Beacon0 Error */ 218 #define IMR0_TBDOK BIT(25) /* Transmit Beacon0 OK */ 219 #define IMR0_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle 220 indication interrupt */ 221 #define IMR0_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */ 222 #define IMR0_BCNDERR0 BIT(16) /* Beacon Queue DMA Error 0 */ 223 #define IMR0_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & 224 HSISR is true) */ 225 #define IMR0_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt 226 Extension for Win7 */ 227 #define IMR0_ATIMEND BIT(12) /* CTWidnow End or 228 ATIM Window End */ 229 #define IMR0_HISR1_IND_INT BIT(11) /* HISR1 Indicator 230 (HISR1 & HIMR1 is true) */ 231 #define IMR0_C2HCMD BIT(10) /* CPU to Host Command INT 232 Status, Write 1 to clear */ 233 #define IMR0_CPWM2 BIT(9) /* CPU power Mode exchange INT 234 Status, Write 1 to clear */ 235 #define IMR0_CPWM BIT(8) /* CPU power Mode exchange INT 236 Status, Write 1 to clear */ 237 #define IMR0_HIGHDOK BIT(7) /* High Queue DMA OK */ 238 #define IMR0_MGNTDOK BIT(6) /* Management Queue DMA OK */ 239 #define IMR0_BKDOK BIT(5) /* AC_BK DMA OK */ 240 #define IMR0_BEDOK BIT(4) /* AC_BE DMA OK */ 241 #define IMR0_VIDOK BIT(3) /* AC_VI DMA OK */ 242 #define IMR0_VODOK BIT(2) /* AC_VO DMA OK */ 243 #define IMR0_RDU BIT(1) /* Rx Descriptor Unavailable */ 244 #define IMR0_ROK BIT(0) /* Receive DMA OK */ 245 #define REG_HISR0 0x00b4 246 #define REG_HIMR1 0x00b8 247 #define IMR1_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */ 248 #define IMR1_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */ 249 #define IMR1_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */ 250 #define IMR1_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */ 251 #define IMR1_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */ 252 #define IMR1_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */ 253 #define IMR1_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */ 254 #define IMR1_BCNDERR7 BIT(20) /* Beacon Queue DMA Err Int 7 */ 255 #define IMR1_BCNDERR6 BIT(19) /* Beacon Queue DMA Err Int 6 */ 256 #define IMR1_BCNDERR5 BIT(18) /* Beacon Queue DMA Err Int 5 */ 257 #define IMR1_BCNDERR4 BIT(17) /* Beacon Queue DMA Err Int 4 */ 258 #define IMR1_BCNDERR3 BIT(16) /* Beacon Queue DMA Err Int 3 */ 259 #define IMR1_BCNDERR2 BIT(15) /* Beacon Queue DMA Err Int 2 */ 260 #define IMR1_BCNDERR1 BIT(14) /* Beacon Queue DMA Err Int 1 */ 261 #define IMR1_ATIMEND_E BIT(13) /* ATIM Window End Extension 262 for Win7 */ 263 #define IMR1_TXERR BIT(11) /* Tx Error Flag Int Status, 264 write 1 to clear */ 265 #define IMR1_RXERR BIT(10) /* Rx Error Flag Int Status, 266 write 1 to clear */ 267 #define IMR1_TXFOVW BIT(9) /* Transmit FIFO Overflow */ 268 #define IMR1_RXFOVW BIT(8) /* Receive FIFO Overflow */ 269 #define REG_HISR1 0x00bc 270 271 /* Host suspend counter on FPGA platform */ 272 #define REG_HOST_SUSP_CNT 0x00bc 273 /* Efuse access protection for RTL8723 */ 274 #define REG_EFUSE_ACCESS 0x00cf 275 #define REG_BIST_SCAN 0x00d0 276 #define REG_BIST_RPT 0x00d4 277 #define REG_BIST_ROM_RPT 0x00d8 278 #define REG_USB_SIE_INTF 0x00e0 279 #define REG_PCIE_MIO_INTF 0x00e4 280 #define REG_PCIE_MIO_INTD 0x00e8 281 #define REG_HPON_FSM 0x00ec 282 #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23)) 283 #define HPON_FSM_BONDING_1T2R BIT(22) 284 #define REG_SYS_CFG 0x00f0 285 #define SYS_CFG_XCLK_VLD BIT(0) 286 #define SYS_CFG_ACLK_VLD BIT(1) 287 #define SYS_CFG_UCLK_VLD BIT(2) 288 #define SYS_CFG_PCLK_VLD BIT(3) 289 #define SYS_CFG_PCIRSTB BIT(4) 290 #define SYS_CFG_V15_VLD BIT(5) 291 #define SYS_CFG_TRP_B15V_EN BIT(7) 292 #define SYS_CFG_SW_OFFLOAD_EN BIT(7) /* For chips with IOL support */ 293 #define SYS_CFG_SIC_IDLE BIT(8) 294 #define SYS_CFG_BD_MAC2 BIT(9) 295 #define SYS_CFG_BD_MAC1 BIT(10) 296 #define SYS_CFG_IC_MACPHY_MODE BIT(11) 297 #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15)) 298 #define SYS_CFG_BT_FUNC BIT(16) 299 #define SYS_CFG_VENDOR_ID BIT(19) 300 #define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19)) 301 #define SYS_CFG_VENDOR_ID_TSMC 0 302 #define SYS_CFG_VENDOR_ID_SMIC BIT(18) 303 #define SYS_CFG_VENDOR_ID_UMC BIT(19) 304 #define SYS_CFG_PAD_HWPD_IDN BIT(22) 305 #define SYS_CFG_TRP_VAUX_EN BIT(23) 306 #define SYS_CFG_TRP_BT_EN BIT(24) 307 #define SYS_CFG_SPS_LDO_SEL BIT(24) /* 8192eu */ 308 #define SYS_CFG_BD_PKG_SEL BIT(25) 309 #define SYS_CFG_BD_HCI_SEL BIT(26) 310 #define SYS_CFG_TYPE_ID BIT(27) 311 #define SYS_CFG_RTL_ID BIT(23) /* TestChip ID, 312 1:Test(RLE); 0:MP(RL) */ 313 #define SYS_CFG_SPS_SEL BIT(24) /* 1:LDO regulator mode; 314 0:Switching regulator mode*/ 315 #define SYS_CFG_CHIP_VERSION_MASK 0xf000 /* Bit 12 - 15 */ 316 #define SYS_CFG_CHIP_VERSION_SHIFT 12 317 318 #define REG_GPIO_OUTSTS 0x00f4 /* For RTL8723 only. */ 319 #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1)) 320 #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3)) 321 #define GPIO_HCI_SEL (BIT(4) | BIT(5)) 322 #define GPIO_PKG_SEL_HCI BIT(6) 323 #define GPIO_FEN_GPS BIT(7) 324 #define GPIO_FEN_BT BIT(8) 325 #define GPIO_FEN_WL BIT(9) 326 #define GPIO_FEN_PCI BIT(10) 327 #define GPIO_FEN_USB BIT(11) 328 #define GPIO_BTRF_HWPDN_N BIT(12) 329 #define GPIO_WLRF_HWPDN_N BIT(13) 330 #define GPIO_PDN_BT_N BIT(14) 331 #define GPIO_PDN_GPS_N BIT(15) 332 #define GPIO_BT_CTL_HWPDN BIT(16) 333 #define GPIO_GPS_CTL_HWPDN BIT(17) 334 #define GPIO_PPHY_SUSB BIT(20) 335 #define GPIO_UPHY_SUSB BIT(21) 336 #define GPIO_PCI_SUSEN BIT(22) 337 #define GPIO_USB_SUSEN BIT(23) 338 #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) 339 340 #define REG_SYS_CFG2 0x00fc /* 8192eu */ 341 342 /* 0x0100 ~ 0x01FF MACTOP General Configuration */ 343 #define REG_CR 0x0100 344 #define CR_HCI_TXDMA_ENABLE BIT(0) 345 #define CR_HCI_RXDMA_ENABLE BIT(1) 346 #define CR_TXDMA_ENABLE BIT(2) 347 #define CR_RXDMA_ENABLE BIT(3) 348 #define CR_PROTOCOL_ENABLE BIT(4) 349 #define CR_SCHEDULE_ENABLE BIT(5) 350 #define CR_MAC_TX_ENABLE BIT(6) 351 #define CR_MAC_RX_ENABLE BIT(7) 352 #define CR_SW_BEACON_ENABLE BIT(8) 353 #define CR_SECURITY_ENABLE BIT(9) 354 #define CR_CALTIMER_ENABLE BIT(10) 355 356 /* Media Status Register */ 357 #define REG_MSR 0x0102 358 #define MSR_LINKTYPE_MASK 0x3 359 #define MSR_LINKTYPE_NONE 0x0 360 #define MSR_LINKTYPE_ADHOC 0x1 361 #define MSR_LINKTYPE_STATION 0x2 362 #define MSR_LINKTYPE_AP 0x3 363 364 #define REG_PBP 0x0104 365 #define PBP_PAGE_SIZE_RX_SHIFT 0 366 #define PBP_PAGE_SIZE_TX_SHIFT 4 367 #define PBP_PAGE_SIZE_64 0x0 368 #define PBP_PAGE_SIZE_128 0x1 369 #define PBP_PAGE_SIZE_256 0x2 370 #define PBP_PAGE_SIZE_512 0x3 371 #define PBP_PAGE_SIZE_1024 0x4 372 373 #define REG_TRXDMA_CTRL 0x010c 374 #define TRXDMA_CTRL_RXDMA_AGG_EN BIT(2) 375 #define TRXDMA_CTRL_VOQ_SHIFT 4 376 #define TRXDMA_CTRL_VIQ_SHIFT 6 377 #define TRXDMA_CTRL_BEQ_SHIFT 8 378 #define TRXDMA_CTRL_BKQ_SHIFT 10 379 #define TRXDMA_CTRL_MGQ_SHIFT 12 380 #define TRXDMA_CTRL_HIQ_SHIFT 14 381 #define TRXDMA_QUEUE_LOW 1 382 #define TRXDMA_QUEUE_NORMAL 2 383 #define TRXDMA_QUEUE_HIGH 3 384 385 #define REG_TRXFF_BNDY 0x0114 386 #define REG_TRXFF_STATUS 0x0118 387 #define REG_RXFF_PTR 0x011c 388 #define REG_HIMR 0x0120 389 #define REG_HISR 0x0124 390 #define REG_HIMRE 0x0128 391 #define REG_HISRE 0x012c 392 #define REG_CPWM 0x012f 393 #define REG_FWIMR 0x0130 394 #define REG_FWISR 0x0134 395 #define REG_FTIMR 0x0138 396 #define REG_PKTBUF_DBG_CTRL 0x0140 397 #define REG_PKTBUF_DBG_DATA_L 0x0144 398 #define REG_PKTBUF_DBG_DATA_H 0x0148 399 400 #define REG_TC0_CTRL 0x0150 401 #define REG_TC1_CTRL 0x0154 402 #define REG_TC2_CTRL 0x0158 403 #define REG_TC3_CTRL 0x015c 404 #define REG_TC4_CTRL 0x0160 405 #define REG_TCUNIT_BASE 0x0164 406 #define REG_MBIST_START 0x0174 407 #define REG_MBIST_DONE 0x0178 408 #define REG_MBIST_FAIL 0x017c 409 #define REG_C2HEVT_MSG_NORMAL 0x01a0 410 /* 8192EU/8723BU/8812 */ 411 #define REG_C2HEVT_CMD_ID_8723B 0x01ae 412 #define REG_C2HEVT_CLEAR 0x01af 413 #define REG_C2HEVT_MSG_TEST 0x01b8 414 #define REG_MCUTST_1 0x01c0 415 #define REG_FMTHR 0x01c8 416 #define REG_HMTFR 0x01cc 417 #define REG_HMBOX_0 0x01d0 418 #define REG_HMBOX_1 0x01d4 419 #define REG_HMBOX_2 0x01d8 420 #define REG_HMBOX_3 0x01dc 421 422 #define REG_LLT_INIT 0x01e0 423 #define LLT_OP_INACTIVE 0x0 424 #define LLT_OP_WRITE (0x1 << 30) 425 #define LLT_OP_READ (0x2 << 30) 426 #define LLT_OP_MASK (0x3 << 30) 427 428 #define REG_BB_ACCEESS_CTRL 0x01e8 429 #define REG_BB_ACCESS_DATA 0x01ec 430 431 #define REG_HMBOX_EXT0_8723B 0x01f0 432 #define REG_HMBOX_EXT1_8723B 0x01f4 433 #define REG_HMBOX_EXT2_8723B 0x01f8 434 #define REG_HMBOX_EXT3_8723B 0x01fc 435 436 /* 0x0200 ~ 0x027F TXDMA Configuration */ 437 #define REG_RQPN 0x0200 438 #define RQPN_HI_PQ_SHIFT 0 439 #define RQPN_LO_PQ_SHIFT 8 440 #define RQPN_PUB_PQ_SHIFT 16 441 #define RQPN_LOAD BIT(31) 442 443 #define REG_FIFOPAGE 0x0204 444 #define REG_TDECTRL 0x0208 445 446 #define REG_DWBCN0_CTRL_8188F REG_TDECTRL 447 448 #define REG_TXDMA_OFFSET_CHK 0x020c 449 #define TXDMA_OFFSET_DROP_DATA_EN BIT(9) 450 #define REG_TXDMA_STATUS 0x0210 451 #define REG_RQPN_NPQ 0x0214 452 #define RQPN_NPQ_SHIFT 0 453 #define RQPN_EPQ_SHIFT 16 454 455 #define REG_AUTO_LLT 0x0224 456 #define AUTO_LLT_INIT_LLT BIT(16) 457 458 #define REG_DWBCN1_CTRL_8723B 0x0228 459 460 /* 0x0280 ~ 0x02FF RXDMA Configuration */ 461 #define REG_RXDMA_AGG_PG_TH 0x0280 /* 0-7 : USB DMA size bits 462 8-14: USB DMA timeout 463 15 : Aggregation enable 464 Only seems to be used 465 on 8723bu/8192eu */ 466 #define RXDMA_USB_AGG_ENABLE BIT(31) 467 #define REG_RXPKT_NUM 0x0284 468 #define RXPKT_NUM_RXDMA_IDLE BIT(17) 469 #define RXPKT_NUM_RW_RELEASE_EN BIT(18) 470 #define REG_RXDMA_STATUS 0x0288 471 472 /* Presumably only found on newer chips such as 8723bu */ 473 #define REG_RX_DMA_CTRL_8723B 0x0286 474 #define REG_RXDMA_PRO_8723B 0x0290 475 476 #define REG_RF_BB_CMD_ADDR 0x02c0 477 #define REG_RF_BB_CMD_DATA 0x02c4 478 479 /* spec version 11 */ 480 /* 0x0400 ~ 0x047F Protocol Configuration */ 481 /* 8192c, 8192d */ 482 #define REG_VOQ_INFO 0x0400 483 #define REG_VIQ_INFO 0x0404 484 #define REG_BEQ_INFO 0x0408 485 #define REG_BKQ_INFO 0x040c 486 /* 8188e, 8723a, 8812a, 8821a, 8192e, 8723b */ 487 #define REG_Q0_INFO 0x400 488 #define REG_Q1_INFO 0x404 489 #define REG_Q2_INFO 0x408 490 #define REG_Q3_INFO 0x40c 491 492 #define REG_MGQ_INFO 0x0410 493 #define REG_HGQ_INFO 0x0414 494 #define REG_BCNQ_INFO 0x0418 495 496 #define REG_CPU_MGQ_INFORMATION 0x041c 497 #define REG_FWHW_TXQ_CTRL 0x0420 498 #define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7) 499 #define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12) 500 501 #define REG_HWSEQ_CTRL 0x0423 502 #define REG_TXPKTBUF_BCNQ_BDNY 0x0424 503 #define REG_TXPKTBUF_MGQ_BDNY 0x0425 504 #define REG_LIFETIME_EN 0x0426 505 #define REG_MULTI_BCNQ_OFFSET 0x0427 506 507 #define REG_SPEC_SIFS 0x0428 508 #define SPEC_SIFS_CCK_MASK 0x00ff 509 #define SPEC_SIFS_CCK_SHIFT 0 510 #define SPEC_SIFS_OFDM_MASK 0xff00 511 #define SPEC_SIFS_OFDM_SHIFT 8 512 513 #define REG_RETRY_LIMIT 0x042a 514 #define RETRY_LIMIT_LONG_SHIFT 0 515 #define RETRY_LIMIT_LONG_MASK 0x003f 516 #define RETRY_LIMIT_SHORT_SHIFT 8 517 #define RETRY_LIMIT_SHORT_MASK 0x3f00 518 519 #define REG_DARFRC 0x0430 520 #define REG_RARFRC 0x0438 521 #define REG_RESPONSE_RATE_SET 0x0440 522 #define RESPONSE_RATE_BITMAP_ALL 0xfffff 523 #define RESPONSE_RATE_RRSR_CCK_ONLY_1M 0xffff1 524 #define RESPONSE_RATE_RRSR_INIT_2G 0x15f 525 #define RESPONSE_RATE_RRSR_INIT_5G 0x150 526 #define RSR_1M BIT(0) 527 #define RSR_2M BIT(1) 528 #define RSR_5_5M BIT(2) 529 #define RSR_11M BIT(3) 530 #define RSR_6M BIT(4) 531 #define RSR_9M BIT(5) 532 #define RSR_12M BIT(6) 533 #define RSR_18M BIT(7) 534 #define RSR_24M BIT(8) 535 #define RSR_36M BIT(9) 536 #define RSR_48M BIT(10) 537 #define RSR_54M BIT(11) 538 #define RSR_MCS0 BIT(12) 539 #define RSR_MCS1 BIT(13) 540 #define RSR_MCS2 BIT(14) 541 #define RSR_MCS3 BIT(15) 542 #define RSR_MCS4 BIT(16) 543 #define RSR_MCS5 BIT(17) 544 #define RSR_MCS6 BIT(18) 545 #define RSR_MCS7 BIT(19) 546 #define RSR_RSC_LOWER_SUB_CHANNEL BIT(21) /* 0x200000 */ 547 #define RSR_RSC_UPPER_SUB_CHANNEL BIT(22) /* 0x400000 */ 548 #define RSR_RSC_BANDWIDTH_40M (RSR_RSC_UPPER_SUB_CHANNEL | \ 549 RSR_RSC_LOWER_SUB_CHANNEL) 550 #define RSR_ACK_SHORT_PREAMBLE BIT(23) 551 552 #define REG_ARFR0 0x0444 553 #define REG_ARFR1 0x0448 554 #define REG_ARFR2 0x044c 555 #define REG_ARFR3 0x0450 556 #define REG_AMPDU_MAX_TIME_8723B 0x0456 557 #define REG_AGGLEN_LMT 0x0458 558 #define REG_AMPDU_MIN_SPACE 0x045c 559 #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045d 560 #define REG_FAST_EDCA_CTRL 0x0460 561 #define REG_RD_RESP_PKT_TH 0x0463 562 #define REG_INIRTS_RATE_SEL 0x0480 563 /* 8723bu */ 564 #define REG_DATA_SUBCHANNEL 0x0483 565 /* 8723au */ 566 #define REG_INIDATA_RATE_SEL 0x0484 567 /* MACID_SLEEP_1/3 for 8723b, 8192e, 8812a, 8821a */ 568 #define REG_MACID_SLEEP_3_8732B 0x0484 569 #define REG_MACID_SLEEP_1_8732B 0x0488 570 571 #define REG_POWER_STATUS 0x04a4 572 #define REG_POWER_STAGE1 0x04b4 573 #define REG_POWER_STAGE2 0x04b8 574 #define REG_AMPDU_BURST_MODE_8723B 0x04bc 575 #define REG_PKT_VO_VI_LIFE_TIME 0x04c0 576 #define REG_PKT_BE_BK_LIFE_TIME 0x04c2 577 #define REG_STBC_SETTING 0x04c4 578 #define REG_QUEUE_CTRL 0x04c6 579 #define REG_HT_SINGLE_AMPDU_8723B 0x04c7 580 #define REG_PROT_MODE_CTRL 0x04c8 581 #define REG_MAX_AGGR_NUM 0x04ca 582 #define REG_RTS_MAX_AGGR_NUM 0x04cb 583 #define REG_BAR_MODE_CTRL 0x04cc 584 #define REG_RA_TRY_RATE_AGG_LMT 0x04cf 585 /* MACID_DROP for 8723a */ 586 #define REG_MACID_DROP_8732A 0x04d0 587 /* EARLY_MODE_CONTROL 8188e */ 588 #define REG_EARLY_MODE_CONTROL_8188E 0x04d0 589 /* MACID_SLEEP_2 for 8723b, 8192e, 8812a, 8821a */ 590 #define REG_MACID_SLEEP_2_8732B 0x04d0 591 #define REG_MACID_SLEEP 0x04d4 592 #define REG_NQOS_SEQ 0x04dc 593 #define REG_QOS_SEQ 0x04de 594 #define REG_NEED_CPU_HANDLE 0x04e0 595 #define REG_PKT_LOSE_RPT 0x04e1 596 #define REG_PTCL_ERR_STATUS 0x04e2 597 #define REG_TX_REPORT_CTRL 0x04ec 598 #define TX_REPORT_CTRL_TIMER_ENABLE BIT(1) 599 600 #define REG_TX_REPORT_TIME 0x04f0 601 #define REG_DUMMY 0x04fc 602 603 /* 0x0500 ~ 0x05FF EDCA Configuration */ 604 #define REG_EDCA_VO_PARAM 0x0500 605 #define REG_EDCA_VI_PARAM 0x0504 606 #define REG_EDCA_BE_PARAM 0x0508 607 #define REG_EDCA_BK_PARAM 0x050c 608 #define EDCA_PARAM_ECW_MIN_SHIFT 8 609 #define EDCA_PARAM_ECW_MAX_SHIFT 12 610 #define EDCA_PARAM_TXOP_SHIFT 16 611 #define REG_BEACON_TCFG 0x0510 612 #define REG_PIFS 0x0512 613 #define REG_RDG_PIFS 0x0513 614 #define REG_SIFS_CCK 0x0514 615 #define REG_SIFS_OFDM 0x0516 616 #define REG_TSFTR_SYN_OFFSET 0x0518 617 #define REG_AGGR_BREAK_TIME 0x051a 618 #define REG_SLOT 0x051b 619 #define REG_TX_PTCL_CTRL 0x0520 620 #define REG_TXPAUSE 0x0522 621 #define REG_DIS_TXREQ_CLR 0x0523 622 #define REG_RD_CTRL 0x0524 623 #define REG_TBTT_PROHIBIT 0x0540 624 #define REG_RD_NAV_NXT 0x0544 625 #define REG_NAV_PROT_LEN 0x0546 626 627 #define REG_BEACON_CTRL 0x0550 628 #define REG_BEACON_CTRL_1 0x0551 629 #define BEACON_ATIM BIT(0) 630 #define BEACON_CTRL_MBSSID BIT(1) 631 #define BEACON_CTRL_TX_BEACON_RPT BIT(2) 632 #define BEACON_FUNCTION_ENABLE BIT(3) 633 #define BEACON_DISABLE_TSF_UPDATE BIT(4) 634 635 #define REG_MBID_NUM 0x0552 636 #define REG_DUAL_TSF_RST 0x0553 637 #define DUAL_TSF_RESET_TSF0 BIT(0) 638 #define DUAL_TSF_RESET_TSF1 BIT(1) 639 #define DUAL_TSF_RESET_P2P BIT(4) 640 #define DUAL_TSF_TX_OK BIT(5) 641 642 /* The same as REG_MBSSID_BCN_SPACE */ 643 #define REG_BCN_INTERVAL 0x0554 644 #define REG_MBSSID_BCN_SPACE 0x0554 645 646 #define REG_DRIVER_EARLY_INT 0x0558 647 #define DRIVER_EARLY_INT_TIME 5 648 649 #define REG_BEACON_DMA_TIME 0x0559 650 #define BEACON_DMA_ATIME_INT_TIME 2 651 652 #define REG_ATIMWND 0x055a 653 #define REG_USTIME_TSF_8723B 0x055c 654 #define REG_BCN_MAX_ERR 0x055d 655 #define REG_RXTSF_OFFSET_CCK 0x055e 656 #define REG_RXTSF_OFFSET_OFDM 0x055f 657 #define REG_TSFTR 0x0560 658 #define REG_TSFTR1 0x0568 659 #define REG_INIT_TSFTR 0x0564 660 #define REG_ATIMWND_1 0x0570 661 #define REG_PSTIMER 0x0580 662 #define REG_TIMER0 0x0584 663 #define REG_TIMER1 0x0588 664 #define REG_ACM_HW_CTRL 0x05c0 665 #define ACM_HW_CTRL_BK BIT(0) 666 #define ACM_HW_CTRL_BE BIT(1) 667 #define ACM_HW_CTRL_VI BIT(2) 668 #define ACM_HW_CTRL_VO BIT(3) 669 #define REG_ACM_RST_CTRL 0x05c1 670 #define REG_ACMAVG 0x05c2 671 #define REG_VO_ADMTIME 0x05c4 672 #define REG_VI_ADMTIME 0x05c6 673 #define REG_BE_ADMTIME 0x05c8 674 #define REG_EDCA_RANDOM_GEN 0x05cc 675 #define REG_SCH_TXCMD 0x05d0 676 677 /* define REG_FW_TSF_SYNC_CNT 0x04a0 */ 678 #define REG_SCH_TX_CMD 0x05f8 679 #define REG_FW_RESET_TSF_CNT_1 0x05fc 680 #define REG_FW_RESET_TSF_CNT_0 0x05fd 681 #define REG_FW_BCN_DIS_CNT 0x05fe 682 683 /* 0x0600 ~ 0x07FF WMAC Configuration */ 684 #define REG_APSD_CTRL 0x0600 685 #define APSD_CTRL_OFF BIT(6) 686 #define APSD_CTRL_OFF_STATUS BIT(7) 687 #define REG_BW_OPMODE 0x0603 688 #define BW_OPMODE_20MHZ BIT(2) 689 #define BW_OPMODE_5G BIT(1) 690 #define BW_OPMODE_11J BIT(0) 691 692 #define REG_TCR 0x0604 693 694 /* Receive Configuration Register */ 695 #define REG_RCR 0x0608 696 #define RCR_ACCEPT_AP BIT(0) /* Accept all unicast packet */ 697 #define RCR_ACCEPT_PHYS_MATCH BIT(1) /* Accept phys match packet */ 698 #define RCR_ACCEPT_MCAST BIT(2) 699 #define RCR_ACCEPT_BCAST BIT(3) 700 #define RCR_ACCEPT_ADDR3 BIT(4) /* Accept address 3 match 701 packet */ 702 #define RCR_ACCEPT_PM BIT(5) /* Accept power management 703 packet */ 704 #define RCR_CHECK_BSSID_MATCH BIT(6) /* Accept BSSID match packet */ 705 #define RCR_CHECK_BSSID_BEACON BIT(7) /* Accept BSSID match packet 706 (Rx beacon, probe rsp) */ 707 #define RCR_ACCEPT_CRC32 BIT(8) /* Accept CRC32 error packet */ 708 #define RCR_ACCEPT_ICV BIT(9) /* Accept ICV error packet */ 709 #define RCR_ACCEPT_DATA_FRAME BIT(11) /* Accept all data pkt or use 710 REG_RXFLTMAP2 */ 711 #define RCR_ACCEPT_CTRL_FRAME BIT(12) /* Accept all control pkt or use 712 REG_RXFLTMAP1 */ 713 #define RCR_ACCEPT_MGMT_FRAME BIT(13) /* Accept all mgmt pkt or use 714 REG_RXFLTMAP0 */ 715 #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */ 716 #define RCR_UC_DATA_PKT_INT_ENABLE BIT(16) /* Enable unicast data packet 717 interrupt */ 718 #define RCR_BM_DATA_PKT_INT_ENABLE BIT(17) /* Enable broadcast data packet 719 interrupt */ 720 #define RCR_TIM_PARSER_ENABLE BIT(18) /* Enable RX beacon TIM parser*/ 721 #define RCR_MFBEN BIT(22) 722 #define RCR_LSIG_ENABLE BIT(23) /* Enable LSIG TXOP Protection 723 function. Search KEYCAM for 724 each rx packet to check if 725 LSIGEN bit is set. */ 726 #define RCR_MULTI_BSSID_ENABLE BIT(24) /* Enable Multiple BssId */ 727 #define RCR_FORCE_ACK BIT(26) 728 #define RCR_ACCEPT_BA_SSN BIT(27) /* Accept BA SSN */ 729 #define RCR_APPEND_PHYSTAT BIT(28) 730 #define RCR_APPEND_ICV BIT(29) 731 #define RCR_APPEND_MIC BIT(30) 732 #define RCR_APPEND_FCS BIT(31) /* WMAC append FCS after */ 733 734 #define REG_RX_PKT_LIMIT 0x060c 735 #define REG_RX_DLK_TIME 0x060d 736 #define REG_RX_DRVINFO_SZ 0x060f 737 738 #define REG_MACID 0x0610 739 #define REG_BSSID 0x0618 740 #define REG_MAR 0x0620 741 #define REG_MBIDCAMCFG 0x0628 742 743 #define REG_USTIME_EDCA 0x0638 744 #define REG_MAC_SPEC_SIFS 0x063a 745 746 /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ 747 /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ 748 #define REG_R2T_SIFS 0x063c 749 /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ 750 #define REG_T2T_SIFS 0x063e 751 #define REG_ACKTO 0x0640 752 #define REG_CTS2TO 0x0641 753 #define REG_EIFS 0x0642 754 755 /* WMA, BA, CCX */ 756 #define REG_NAV_CTRL 0x0650 757 /* In units of 128us */ 758 #define REG_NAV_UPPER 0x0652 759 #define NAV_UPPER_UNIT 128 760 761 #define REG_BACAMCMD 0x0654 762 #define REG_BACAMCONTENT 0x0658 763 #define REG_LBDLY 0x0660 764 #define REG_FWDLY 0x0661 765 #define REG_RXERR_RPT 0x0664 766 #define REG_WMAC_TRXPTCL_CTL 0x0668 767 #define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8)) 768 #define WMAC_TRXPTCL_CTL_BW_20 0 769 #define WMAC_TRXPTCL_CTL_BW_40 BIT(7) 770 #define WMAC_TRXPTCL_CTL_BW_80 BIT(8) 771 772 /* Security */ 773 #define REG_CAM_CMD 0x0670 774 #define CAM_CMD_POLLING BIT(31) 775 #define CAM_CMD_WRITE BIT(16) 776 #define CAM_CMD_KEY_SHIFT 3 777 #define REG_CAM_WRITE 0x0674 778 #define CAM_WRITE_VALID BIT(15) 779 #define REG_CAM_READ 0x0678 780 #define REG_CAM_DEBUG 0x067c 781 #define REG_SECURITY_CFG 0x0680 782 #define SEC_CFG_TX_USE_DEFKEY BIT(0) 783 #define SEC_CFG_RX_USE_DEFKEY BIT(1) 784 #define SEC_CFG_TX_SEC_ENABLE BIT(2) 785 #define SEC_CFG_RX_SEC_ENABLE BIT(3) 786 #define SEC_CFG_SKBYA2 BIT(4) 787 #define SEC_CFG_NO_SKMC BIT(5) 788 #define SEC_CFG_TXBC_USE_DEFKEY BIT(6) 789 #define SEC_CFG_RXBC_USE_DEFKEY BIT(7) 790 791 /* Power */ 792 #define REG_WOW_CTRL 0x0690 793 #define REG_PSSTATUS 0x0691 794 #define REG_PS_RX_INFO 0x0692 795 #define REG_LPNAV_CTRL 0x0694 796 #define REG_WKFMCAM_CMD 0x0698 797 #define REG_WKFMCAM_RWD 0x069c 798 799 /* 800 * RX Filters: each bit corresponds to the numerical value of the subtype. 801 * If it is set the subtype frame type is passed. The filter is only used when 802 * the RCR_ACCEPT_DATA_FRAME, RCR_ACCEPT_CTRL_FRAME, RCR_ACCEPT_MGMT_FRAME bit 803 * in the RCR are low. 804 * 805 * Example: Beacon subtype is binary 1000 which is decimal 8 so we have to set 806 * bit 8 (0x100) in REG_RXFLTMAP0 to enable reception. 807 */ 808 #define REG_RXFLTMAP0 0x06a0 /* Management frames */ 809 #define REG_RXFLTMAP1 0x06a2 /* Control frames */ 810 #define REG_RXFLTMAP2 0x06a4 /* Data frames */ 811 812 #define REG_BCN_PSR_RPT 0x06a8 813 #define REG_CALB32K_CTRL 0x06ac 814 #define REG_PKT_MON_CTRL 0x06b4 815 #define REG_BT_COEX_TABLE1 0x06c0 816 #define REG_BT_COEX_TABLE2 0x06c4 817 #define REG_BT_COEX_TABLE3 0x06c8 818 #define REG_BT_COEX_TABLE4 0x06cc 819 #define REG_WMAC_RESP_TXINFO 0x06d8 820 821 #define REG_MACID1 0x0700 822 #define REG_BSSID1 0x0708 823 824 /* 825 * This seems to be 8723bu specific 826 */ 827 #define REG_BT_CONTROL_8723BU 0x0764 828 #define BT_CONTROL_BT_GRANT BIT(12) 829 830 #define REG_WLAN_ACT_CONTROL_8723B 0x076e 831 832 #define REG_FPGA0_RF_MODE 0x0800 833 #define FPGA_RF_MODE BIT(0) 834 #define FPGA_RF_MODE_JAPAN BIT(1) 835 #define FPGA_RF_MODE_CCK BIT(24) 836 #define FPGA_RF_MODE_OFDM BIT(25) 837 838 #define REG_FPGA0_TX_INFO 0x0804 839 #define FPGA0_TX_INFO_OFDM_PATH_A BIT(0) 840 #define FPGA0_TX_INFO_OFDM_PATH_B BIT(1) 841 #define FPGA0_TX_INFO_OFDM_PATH_C BIT(2) 842 #define FPGA0_TX_INFO_OFDM_PATH_D BIT(3) 843 #define REG_FPGA0_PSD_FUNC 0x0808 844 #define REG_FPGA0_TX_GAIN 0x080c 845 #define REG_FPGA0_RF_TIMING1 0x0810 846 #define REG_FPGA0_RF_TIMING2 0x0814 847 #define REG_FPGA0_POWER_SAVE 0x0818 848 #define FPGA0_PS_LOWER_CHANNEL BIT(26) 849 #define FPGA0_PS_UPPER_CHANNEL BIT(27) 850 851 #define REG_FPGA0_XA_HSSI_PARM1 0x0820 /* RF 3 wire register */ 852 #define FPGA0_HSSI_PARM1_PI BIT(8) 853 #define REG_FPGA0_XA_HSSI_PARM2 0x0824 854 #define REG_FPGA0_XB_HSSI_PARM1 0x0828 855 #define REG_FPGA0_XB_HSSI_PARM2 0x082c 856 #define FPGA0_HSSI_3WIRE_DATA_LEN 0x800 857 #define FPGA0_HSSI_3WIRE_ADDR_LEN 0x400 858 #define FPGA0_HSSI_PARM2_ADDR_SHIFT 23 859 #define FPGA0_HSSI_PARM2_ADDR_MASK 0x7f800000 /* 0xff << 23 */ 860 #define FPGA0_HSSI_PARM2_CCK_HIGH_PWR BIT(9) 861 #define FPGA0_HSSI_PARM2_EDGE_READ BIT(31) 862 863 #define REG_TX_AGC_B_RATE18_06 0x0830 864 #define REG_TX_AGC_B_RATE54_24 0x0834 865 #define REG_TX_AGC_B_CCK1_55_MCS32 0x0838 866 #define REG_TX_AGC_B_MCS03_MCS00 0x083c 867 868 #define REG_FPGA0_XA_LSSI_PARM 0x0840 869 #define REG_FPGA0_XB_LSSI_PARM 0x0844 870 #define FPGA0_LSSI_PARM_ADDR_SHIFT 20 871 #define FPGA0_LSSI_PARM_ADDR_MASK 0x0ff00000 872 #define FPGA0_LSSI_PARM_DATA_MASK 0x000fffff 873 874 #define REG_TX_AGC_B_MCS07_MCS04 0x0848 875 #define REG_TX_AGC_B_MCS11_MCS08 0x084c 876 877 #define REG_FPGA0_XCD_SWITCH_CTRL 0x085c 878 879 #define REG_FPGA0_XA_RF_INT_OE 0x0860 /* RF Channel switch */ 880 #define REG_FPGA0_XB_RF_INT_OE 0x0864 881 #define FPGA0_INT_OE_ANTENNA_AB_OPEN 0x000 882 #define FPGA0_INT_OE_ANTENNA_A BIT(8) 883 #define FPGA0_INT_OE_ANTENNA_B BIT(9) 884 #define FPGA0_INT_OE_ANTENNA_MASK (FPGA0_INT_OE_ANTENNA_A | \ 885 FPGA0_INT_OE_ANTENNA_B) 886 887 #define REG_TX_AGC_B_MCS15_MCS12 0x0868 888 #define REG_TX_AGC_B_CCK11_A_CCK2_11 0x086c 889 890 #define REG_FPGA0_XAB_RF_SW_CTRL 0x0870 891 #define REG_FPGA0_XA_RF_SW_CTRL 0x0870 /* 16 bit */ 892 #define REG_FPGA0_XB_RF_SW_CTRL 0x0872 /* 16 bit */ 893 #define REG_FPGA0_XCD_RF_SW_CTRL 0x0874 894 #define REG_FPGA0_XC_RF_SW_CTRL 0x0874 /* 16 bit */ 895 #define REG_FPGA0_XD_RF_SW_CTRL 0x0876 /* 16 bit */ 896 #define FPGA0_RF_3WIRE_DATA BIT(0) 897 #define FPGA0_RF_3WIRE_CLOC BIT(1) 898 #define FPGA0_RF_3WIRE_LOAD BIT(2) 899 #define FPGA0_RF_3WIRE_RW BIT(3) 900 #define FPGA0_RF_3WIRE_MASK 0xf 901 #define FPGA0_RF_RFENV BIT(4) 902 #define FPGA0_RF_TRSW BIT(5) /* Useless now */ 903 #define FPGA0_RF_TRSWB BIT(6) 904 #define FPGA0_RF_ANTSW BIT(8) 905 #define FPGA0_RF_ANTSWB BIT(9) 906 #define FPGA0_RF_PAPE BIT(10) 907 #define FPGA0_RF_PAPE5G BIT(11) 908 #define FPGA0_RF_BD_CTRL_SHIFT 16 909 910 #define REG_FPGA0_XAB_RF_PARM 0x0878 /* Antenna select path in ODM */ 911 #define REG_FPGA0_XA_RF_PARM 0x0878 /* 16 bit */ 912 #define REG_FPGA0_XB_RF_PARM 0x087a /* 16 bit */ 913 #define REG_FPGA0_XCD_RF_PARM 0x087c 914 #define REG_FPGA0_XC_RF_PARM 0x087c /* 16 bit */ 915 #define REG_FPGA0_XD_RF_PARM 0x087e /* 16 bit */ 916 #define FPGA0_RF_PARM_RFA_ENABLE BIT(1) 917 #define FPGA0_RF_PARM_RFB_ENABLE BIT(17) 918 #define FPGA0_RF_PARM_CLK_GATE BIT(31) 919 920 #define REG_FPGA0_ANALOG1 0x0880 921 #define REG_FPGA0_ANALOG2 0x0884 922 #define FPGA0_ANALOG2_20MHZ BIT(10) 923 #define REG_FPGA0_ANALOG3 0x0888 924 #define REG_FPGA0_ANALOG4 0x088c 925 926 #define REG_NHM_TH9_TH10_8723B 0x0890 927 #define REG_NHM_TIMER_8723B 0x0894 928 #define REG_NHM_TH3_TO_TH0_8723B 0x0898 929 #define REG_NHM_TH7_TO_TH4_8723B 0x089c 930 931 #define REG_FPGA0_XA_LSSI_READBACK 0x08a0 /* Tranceiver LSSI Readback */ 932 #define REG_FPGA0_XB_LSSI_READBACK 0x08a4 933 #define REG_FPGA0_PSD_REPORT 0x08b4 934 #define REG_HSPI_XA_READBACK 0x08b8 /* Transceiver A HSPI read */ 935 #define REG_HSPI_XB_READBACK 0x08bc /* Transceiver B HSPI read */ 936 937 #define REG_FPGA1_RF_MODE 0x0900 938 939 #define REG_FPGA1_TX_INFO 0x090c 940 #define REG_DPDT_CTRL 0x092c /* 8723BU */ 941 #define REG_RFE_CTRL_ANTA_SRC 0x0930 /* 8723BU */ 942 #define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */ 943 #define REG_RFE_BUFFER 0x0944 /* 8723BU */ 944 #define REG_S0S1_PATH_SWITCH 0x0948 /* 8723BU */ 945 #define REG_OFDM_RX_DFIR 0x954 946 947 #define REG_CCK0_SYSTEM 0x0a00 948 #define CCK0_SIDEBAND BIT(4) 949 950 #define REG_CCK0_AFE_SETTING 0x0a04 951 #define CCK0_AFE_RX_MASK 0x0f000000 952 #define CCK0_AFE_RX_ANT_AB BIT(24) 953 #define CCK0_AFE_RX_ANT_A 0 954 #define CCK0_AFE_RX_ANT_B (BIT(24) | BIT(26)) 955 956 #define REG_CCK_PD_THRESH 0x0a0a 957 #define CCK_PD_TYPE1_LV0_TH 0x40 958 #define CCK_PD_TYPE1_LV1_TH 0x83 959 #define CCK_PD_TYPE1_LV2_TH 0xcd 960 #define CCK_PD_TYPE1_LV3_TH 0xdd 961 #define CCK_PD_TYPE1_LV4_TH 0xed 962 963 #define REG_CONFIG_ANT_A 0x0b68 964 #define REG_CONFIG_ANT_B 0x0b6c 965 966 #define REG_OFDM0_TRX_PATH_ENABLE 0x0c04 967 #define OFDM_RF_PATH_RX_MASK 0x0f 968 #define OFDM_RF_PATH_RX_A BIT(0) 969 #define OFDM_RF_PATH_RX_B BIT(1) 970 #define OFDM_RF_PATH_RX_C BIT(2) 971 #define OFDM_RF_PATH_RX_D BIT(3) 972 #define OFDM_RF_PATH_TX_MASK 0xf0 973 #define OFDM_RF_PATH_TX_A BIT(4) 974 #define OFDM_RF_PATH_TX_B BIT(5) 975 #define OFDM_RF_PATH_TX_C BIT(6) 976 #define OFDM_RF_PATH_TX_D BIT(7) 977 978 #define REG_OFDM0_TR_MUX_PAR 0x0c08 979 980 #define REG_OFDM0_FA_RSTC 0x0c0c 981 982 #define REG_OFDM0_XA_RX_AFE 0x0c10 983 #define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14 984 #define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c 985 986 #define REG_OFDM0_ENERGY_CCA_THRES 0x0c4c 987 988 #define REG_OFDM0_RX_D_SYNC_PATH 0x0c40 989 #define OFDM0_SYNC_PATH_NOTCH_FILTER BIT(1) 990 991 #define REG_OFDM0_XA_AGC_CORE1 0x0c50 992 #define REG_OFDM0_XA_AGC_CORE2 0x0c54 993 #define REG_OFDM0_XB_AGC_CORE1 0x0c58 994 #define REG_OFDM0_XB_AGC_CORE2 0x0c5c 995 #define REG_OFDM0_XC_AGC_CORE1 0x0c60 996 #define REG_OFDM0_XC_AGC_CORE2 0x0c64 997 #define REG_OFDM0_XD_AGC_CORE1 0x0c68 998 #define REG_OFDM0_XD_AGC_CORE2 0x0c6c 999 #define OFDM0_X_AGC_CORE1_IGI_MASK 0x0000007F 1000 1001 #define REG_OFDM0_AGC_PARM1 0x0c70 1002 1003 #define REG_OFDM0_AGCR_SSI_TABLE 0x0c78 1004 1005 #define REG_OFDM0_XA_TX_IQ_IMBALANCE 0x0c80 1006 #define REG_OFDM0_XB_TX_IQ_IMBALANCE 0x0c88 1007 #define REG_OFDM0_XC_TX_IQ_IMBALANCE 0x0c90 1008 #define REG_OFDM0_XD_TX_IQ_IMBALANCE 0x0c98 1009 1010 #define REG_OFDM0_XC_TX_AFE 0x0c94 1011 #define REG_OFDM0_XD_TX_AFE 0x0c9c 1012 1013 #define REG_OFDM0_RX_IQ_EXT_ANTA 0x0ca0 1014 1015 /* 8723bu */ 1016 #define REG_OFDM0_TX_PSDO_NOISE_WEIGHT 0x0ce4 1017 1018 #define REG_OFDM1_LSTF 0x0d00 1019 #define OFDM_LSTF_PRIME_CH_LOW BIT(10) 1020 #define OFDM_LSTF_PRIME_CH_HIGH BIT(11) 1021 #define OFDM_LSTF_PRIME_CH_MASK (OFDM_LSTF_PRIME_CH_LOW | \ 1022 OFDM_LSTF_PRIME_CH_HIGH) 1023 #define OFDM_LSTF_CONTINUE_TX BIT(28) 1024 #define OFDM_LSTF_SINGLE_CARRIER BIT(29) 1025 #define OFDM_LSTF_SINGLE_TONE BIT(30) 1026 #define OFDM_LSTF_MASK 0x70000000 1027 1028 #define REG_OFDM1_TRX_PATH_ENABLE 0x0d04 1029 #define REG_OFDM1_CFO_TRACKING 0x0d2c 1030 #define REG_OFDM1_CSI_FIX_MASK1 0x0d40 1031 #define REG_OFDM1_CSI_FIX_MASK2 0x0d44 1032 1033 #define REG_TX_AGC_A_RATE18_06 0x0e00 1034 #define REG_TX_AGC_A_RATE54_24 0x0e04 1035 #define REG_TX_AGC_A_CCK1_MCS32 0x0e08 1036 #define REG_TX_AGC_A_MCS03_MCS00 0x0e10 1037 #define REG_TX_AGC_A_MCS07_MCS04 0x0e14 1038 #define REG_TX_AGC_A_MCS11_MCS08 0x0e18 1039 #define REG_TX_AGC_A_MCS15_MCS12 0x0e1c 1040 1041 #define REG_FPGA0_IQK 0x0e28 1042 1043 #define REG_TX_IQK_TONE_A 0x0e30 1044 #define REG_RX_IQK_TONE_A 0x0e34 1045 #define REG_TX_IQK_PI_A 0x0e38 1046 #define REG_RX_IQK_PI_A 0x0e3c 1047 1048 #define REG_TX_IQK 0x0e40 1049 #define REG_RX_IQK 0x0e44 1050 #define REG_IQK_AGC_PTS 0x0e48 1051 #define REG_IQK_AGC_RSP 0x0e4c 1052 #define REG_TX_IQK_TONE_B 0x0e50 1053 #define REG_RX_IQK_TONE_B 0x0e54 1054 #define REG_TX_IQK_PI_B 0x0e58 1055 #define REG_RX_IQK_PI_B 0x0e5c 1056 #define REG_IQK_AGC_CONT 0x0e60 1057 1058 #define REG_BLUETOOTH 0x0e6c 1059 #define REG_RX_WAIT_CCA 0x0e70 1060 #define REG_TX_CCK_RFON 0x0e74 1061 #define REG_TX_CCK_BBON 0x0e78 1062 #define REG_TX_OFDM_RFON 0x0e7c 1063 #define REG_TX_OFDM_BBON 0x0e80 1064 #define REG_TX_TO_RX 0x0e84 1065 #define REG_TX_TO_TX 0x0e88 1066 #define REG_RX_CCK 0x0e8c 1067 1068 #define REG_TX_POWER_BEFORE_IQK_A 0x0e94 1069 #define REG_TX_POWER_AFTER_IQK_A 0x0e9c 1070 1071 #define REG_RX_POWER_BEFORE_IQK_A 0x0ea0 1072 #define REG_RX_POWER_BEFORE_IQK_A_2 0x0ea4 1073 #define REG_RX_POWER_AFTER_IQK_A 0x0ea8 1074 #define REG_RX_POWER_AFTER_IQK_A_2 0x0eac 1075 1076 #define REG_TX_POWER_BEFORE_IQK_B 0x0eb4 1077 #define REG_TX_POWER_AFTER_IQK_B 0x0ebc 1078 1079 #define REG_RX_POWER_BEFORE_IQK_B 0x0ec0 1080 #define REG_RX_POWER_BEFORE_IQK_B_2 0x0ec4 1081 #define REG_RX_POWER_AFTER_IQK_B 0x0ec8 1082 #define REG_RX_POWER_AFTER_IQK_B_2 0x0ecc 1083 1084 #define REG_RX_OFDM 0x0ed0 1085 #define REG_RX_WAIT_RIFS 0x0ed4 1086 #define REG_RX_TO_RX 0x0ed8 1087 #define REG_STANDBY 0x0edc 1088 #define REG_SLEEP 0x0ee0 1089 #define REG_PMPD_ANAEN 0x0eec 1090 1091 #define REG_FW_START_ADDRESS 0x1000 1092 1093 #define REG_USB_INFO 0xfe17 1094 #define REG_USB_HIMR 0xfe38 1095 #define USB_HIMR_TIMEOUT2 BIT(31) 1096 #define USB_HIMR_TIMEOUT1 BIT(30) 1097 #define USB_HIMR_PSTIMEOUT BIT(29) 1098 #define USB_HIMR_GTINT4 BIT(28) 1099 #define USB_HIMR_GTINT3 BIT(27) 1100 #define USB_HIMR_TXBCNERR BIT(26) 1101 #define USB_HIMR_TXBCNOK BIT(25) 1102 #define USB_HIMR_TSF_BIT32_TOGGLE BIT(24) 1103 #define USB_HIMR_BCNDMAINT3 BIT(23) 1104 #define USB_HIMR_BCNDMAINT2 BIT(22) 1105 #define USB_HIMR_BCNDMAINT1 BIT(21) 1106 #define USB_HIMR_BCNDMAINT0 BIT(20) 1107 #define USB_HIMR_BCNDOK3 BIT(19) 1108 #define USB_HIMR_BCNDOK2 BIT(18) 1109 #define USB_HIMR_BCNDOK1 BIT(17) 1110 #define USB_HIMR_BCNDOK0 BIT(16) 1111 #define USB_HIMR_HSISR_IND BIT(15) 1112 #define USB_HIMR_BCNDMAINT_E BIT(14) 1113 /* RSVD BIT(13) */ 1114 #define USB_HIMR_CTW_END BIT(12) 1115 /* RSVD BIT(11) */ 1116 #define USB_HIMR_C2HCMD BIT(10) 1117 #define USB_HIMR_CPWM2 BIT(9) 1118 #define USB_HIMR_CPWM BIT(8) 1119 #define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK 1120 Interrupt */ 1121 #define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK 1122 Interrupt */ 1123 #define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */ 1124 #define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */ 1125 #define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */ 1126 #define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */ 1127 #define USB_HIMR_RDU BIT(1) /* Receive Descriptor 1128 Unavailable */ 1129 #define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */ 1130 1131 #define REG_USB_SPECIAL_OPTION 0xfe55 1132 #define USB_SPEC_USB_AGG_ENABLE BIT(3) /* Enable USB aggregation */ 1133 #define USB_SPEC_INT_BULK_SELECT BIT(4) /* Use interrupt endpoint to 1134 deliver interrupt packet. 1135 0: Use int, 1: use bulk */ 1136 #define REG_USB_HRPWM 0xfe58 1137 #define REG_USB_DMA_AGG_TO 0xfe5b 1138 #define REG_USB_AGG_TIMEOUT 0xfe5c 1139 #define REG_USB_AGG_THRESH 0xfe5d 1140 1141 #define REG_NORMAL_SIE_VID 0xfe60 /* 0xfe60 - 0xfe61 */ 1142 #define REG_NORMAL_SIE_PID 0xfe62 /* 0xfe62 - 0xfe63 */ 1143 #define REG_NORMAL_SIE_OPTIONAL 0xfe64 1144 #define REG_NORMAL_SIE_EP 0xfe65 /* 0xfe65 - 0xfe67 */ 1145 #define REG_NORMAL_SIE_EP_TX 0xfe66 1146 #define NORMAL_SIE_EP_TX_HIGH_MASK 0x000f 1147 #define NORMAL_SIE_EP_TX_NORMAL_MASK 0x00f0 1148 #define NORMAL_SIE_EP_TX_LOW_MASK 0x0f00 1149 1150 #define REG_NORMAL_SIE_PHY 0xfe68 /* 0xfe68 - 0xfe6b */ 1151 #define REG_NORMAL_SIE_OPTIONAL2 0xfe6c 1152 #define REG_NORMAL_SIE_GPS_EP 0xfe6d /* RTL8723 only */ 1153 #define REG_NORMAL_SIE_MAC_ADDR 0xfe70 /* 0xfe70 - 0xfe75 */ 1154 #define REG_NORMAL_SIE_STRING 0xfe80 /* 0xfe80 - 0xfedf */ 1155 1156 /* RF6052 registers */ 1157 #define RF6052_REG_AC 0x00 1158 #define RF6052_REG_IQADJ_G1 0x01 1159 #define RF6052_REG_IQADJ_G2 0x02 1160 #define RF6052_REG_BS_PA_APSET_G1_G4 0x03 1161 #define RF6052_REG_BS_PA_APSET_G5_G8 0x04 1162 #define RF6052_REG_POW_TRSW 0x05 1163 #define RF6052_REG_GAIN_RX 0x06 1164 #define RF6052_REG_GAIN_TX 0x07 1165 #define RF6052_REG_TXM_IDAC 0x08 1166 #define RF6052_REG_IPA_G 0x09 1167 #define RF6052_REG_TXBIAS_G 0x0a 1168 #define RF6052_REG_TXPA_AG 0x0b 1169 #define RF6052_REG_IPA_A 0x0c 1170 #define RF6052_REG_TXBIAS_A 0x0d 1171 #define RF6052_REG_BS_PA_APSET_G9_G11 0x0e 1172 #define RF6052_REG_BS_IQGEN 0x0f 1173 #define RF6052_REG_MODE1 0x10 1174 #define RF6052_REG_MODE2 0x11 1175 #define RF6052_REG_RX_AGC_HP 0x12 1176 #define RF6052_REG_TX_AGC 0x13 1177 #define RF6052_REG_BIAS 0x14 1178 #define RF6052_REG_IPA 0x15 1179 #define RF6052_REG_TXBIAS 0x16 1180 #define RF6052_REG_POW_ABILITY 0x17 1181 #define RF6052_REG_MODE_AG 0x18 /* RF channel and BW switch */ 1182 #define MODE_AG_CHANNEL_MASK 0x3ff 1183 #define MODE_AG_CHANNEL_20MHZ BIT(10) 1184 #define MODE_AG_BW_MASK (BIT(10) | BIT(11)) 1185 #define MODE_AG_BW_20MHZ_8723B (BIT(10) | BIT(11)) 1186 #define MODE_AG_BW_40MHZ_8723B BIT(10) 1187 #define MODE_AG_BW_80MHZ_8723B 0 1188 1189 #define RF6052_REG_TOP 0x19 1190 #define RF6052_REG_RX_G1 0x1a 1191 #define RF6052_REG_RX_G2 0x1b 1192 #define RF6052_REG_RX_BB2 0x1c 1193 #define RF6052_REG_RX_BB1 0x1d 1194 #define RF6052_REG_RCK1 0x1e 1195 #define RF6052_REG_RCK2 0x1f 1196 #define RF6052_REG_TX_G1 0x20 1197 #define RF6052_REG_TX_G2 0x21 1198 #define RF6052_REG_TX_G3 0x22 1199 #define RF6052_REG_TX_BB1 0x23 1200 #define RF6052_REG_T_METER 0x24 1201 #define RF6052_REG_SYN_G1 0x25 /* RF TX Power control */ 1202 #define RF6052_REG_SYN_G2 0x26 /* RF TX Power control */ 1203 #define RF6052_REG_SYN_G3 0x27 /* RF TX Power control */ 1204 #define RF6052_REG_SYN_G4 0x28 /* RF TX Power control */ 1205 #define RF6052_REG_SYN_G5 0x29 /* RF TX Power control */ 1206 #define RF6052_REG_SYN_G6 0x2a /* RF TX Power control */ 1207 #define RF6052_REG_SYN_G7 0x2b /* RF TX Power control */ 1208 #define RF6052_REG_SYN_G8 0x2c /* RF TX Power control */ 1209 1210 #define RF6052_REG_RCK_OS 0x30 /* RF TX PA control */ 1211 1212 #define RF6052_REG_TXPA_G1 0x31 /* RF TX PA control */ 1213 #define RF6052_REG_TXPA_G2 0x32 /* RF TX PA control */ 1214 #define RF6052_REG_TXPA_G3 0x33 /* RF TX PA control */ 1215 1216 /* 1217 * NextGen regs: 8723BU 1218 */ 1219 #define RF6052_REG_T_METER_8723B 0x42 1220 #define RF6052_REG_UNKNOWN_43 0x43 1221 #define RF6052_REG_UNKNOWN_55 0x55 1222 #define RF6052_REG_UNKNOWN_56 0x56 1223 #define RF6052_REG_RXG_MIX_SWBW 0x87 1224 #define RF6052_REG_S0S1 0xb0 1225 #define RF6052_REG_UNKNOWN_DF 0xdf 1226 #define RF6052_REG_UNKNOWN_ED 0xed 1227 #define RF6052_REG_WE_LUT 0xef 1228