1 /* 2 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com> 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * Register definitions taken from original Realtek rtl8723au driver 14 */ 15 16 /* 0x0000 ~ 0x00FF System Configuration */ 17 #define REG_SYS_ISO_CTRL 0x0000 18 #define SYS_ISO_MD2PP BIT(0) 19 #define SYS_ISO_ANALOG_IPS BIT(5) 20 #define SYS_ISO_DIOR BIT(9) 21 #define SYS_ISO_PWC_EV25V BIT(14) 22 #define SYS_ISO_PWC_EV12V BIT(15) 23 24 #define REG_SYS_FUNC 0x0002 25 #define SYS_FUNC_BBRSTB BIT(0) 26 #define SYS_FUNC_BB_GLB_RSTN BIT(1) 27 #define SYS_FUNC_USBA BIT(2) 28 #define SYS_FUNC_UPLL BIT(3) 29 #define SYS_FUNC_USBD BIT(4) 30 #define SYS_FUNC_DIO_PCIE BIT(5) 31 #define SYS_FUNC_PCIEA BIT(6) 32 #define SYS_FUNC_PPLL BIT(7) 33 #define SYS_FUNC_PCIED BIT(8) 34 #define SYS_FUNC_DIOE BIT(9) 35 #define SYS_FUNC_CPU_ENABLE BIT(10) 36 #define SYS_FUNC_DCORE BIT(11) 37 #define SYS_FUNC_ELDR BIT(12) 38 #define SYS_FUNC_DIO_RF BIT(13) 39 #define SYS_FUNC_HWPDN BIT(14) 40 #define SYS_FUNC_MREGEN BIT(15) 41 42 #define REG_APS_FSMCO 0x0004 43 #define APS_FSMCO_PFM_ALDN BIT(1) 44 #define APS_FSMCO_PFM_WOWL BIT(3) 45 #define APS_FSMCO_ENABLE_POWERDOWN BIT(4) 46 #define APS_FSMCO_MAC_ENABLE BIT(8) 47 #define APS_FSMCO_MAC_OFF BIT(9) 48 #define APS_FSMCO_HW_SUSPEND BIT(11) 49 #define APS_FSMCO_PCIE BIT(12) 50 #define APS_FSMCO_HW_POWERDOWN BIT(15) 51 #define APS_FSMCO_WLON_RESET BIT(16) 52 53 #define REG_SYS_CLKR 0x0008 54 #define SYS_CLK_ANAD16V_ENABLE BIT(0) 55 #define SYS_CLK_ANA8M BIT(1) 56 #define SYS_CLK_MACSLP BIT(4) 57 #define SYS_CLK_LOADER_ENABLE BIT(5) 58 #define SYS_CLK_80M_SSC_DISABLE BIT(7) 59 #define SYS_CLK_80M_SSC_ENABLE_HO BIT(8) 60 #define SYS_CLK_PHY_SSC_RSTB BIT(9) 61 #define SYS_CLK_SEC_CLK_ENABLE BIT(10) 62 #define SYS_CLK_MAC_CLK_ENABLE BIT(11) 63 #define SYS_CLK_ENABLE BIT(12) 64 #define SYS_CLK_RING_CLK_ENABLE BIT(13) 65 66 #define REG_9346CR 0x000a 67 #define EEPROM_BOOT BIT(4) 68 #define EEPROM_ENABLE BIT(5) 69 70 #define REG_EE_VPD 0x000c 71 #define REG_AFE_MISC 0x0010 72 #define REG_SPS0_CTRL 0x0011 73 #define REG_SPS_OCP_CFG 0x0018 74 #define REG_RSV_CTRL 0x001c 75 76 #define REG_RF_CTRL 0x001f 77 #define RF_ENABLE BIT(0) 78 #define RF_RSTB BIT(1) 79 #define RF_SDMRSTB BIT(2) 80 81 #define REG_LDOA15_CTRL 0x0020 82 #define LDOA15_ENABLE BIT(0) 83 #define LDOA15_STANDBY BIT(1) 84 #define LDOA15_OBUF BIT(2) 85 #define LDOA15_REG_VOS BIT(3) 86 #define LDOA15_VOADJ_SHIFT 4 87 88 #define REG_LDOV12D_CTRL 0x0021 89 #define LDOV12D_ENABLE BIT(0) 90 #define LDOV12D_STANDBY BIT(1) 91 #define LDOV12D_VADJ_SHIFT 4 92 93 #define REG_LDOHCI12_CTRL 0x0022 94 95 #define REG_LPLDO_CTRL 0x0023 96 #define LPLDO_HSM BIT(2) 97 #define LPLDO_LSM_DIS BIT(3) 98 99 #define REG_AFE_XTAL_CTRL 0x0024 100 #define AFE_XTAL_ENABLE BIT(0) 101 #define AFE_XTAL_B_SELECT BIT(1) 102 #define AFE_XTAL_GATE_USB BIT(8) 103 #define AFE_XTAL_GATE_AFE BIT(11) 104 #define AFE_XTAL_RF_GATE BIT(14) 105 #define AFE_XTAL_GATE_DIG BIT(17) 106 #define AFE_XTAL_BT_GATE BIT(20) 107 108 #define REG_AFE_PLL_CTRL 0x0028 109 #define AFE_PLL_ENABLE BIT(0) 110 #define AFE_PLL_320_ENABLE BIT(1) 111 #define APE_PLL_FREF_SELECT BIT(2) 112 #define AFE_PLL_EDGE_SELECT BIT(3) 113 #define AFE_PLL_WDOGB BIT(4) 114 #define AFE_PLL_LPF_ENABLE BIT(5) 115 116 #define REG_MAC_PHY_CTRL 0x002c 117 118 #define REG_EFUSE_CTRL 0x0030 119 #define REG_EFUSE_TEST 0x0034 120 #define EFUSE_TRPT BIT(7) 121 /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ 122 #define EFUSE_CELL_SEL (BIT(8) | BIT(9)) 123 #define EFUSE_LDOE25_ENABLE BIT(31) 124 #define EFUSE_SELECT_MASK 0x0300 125 #define EFUSE_WIFI_SELECT 0x0000 126 #define EFUSE_BT0_SELECT 0x0100 127 #define EFUSE_BT1_SELECT 0x0200 128 #define EFUSE_BT2_SELECT 0x0300 129 130 #define EFUSE_ACCESS_ENABLE 0x69 /* RTL8723 only */ 131 #define EFUSE_ACCESS_DISABLE 0x00 /* RTL8723 only */ 132 133 #define REG_PWR_DATA 0x0038 134 #define REG_CAL_TIMER 0x003c 135 #define REG_ACLK_MON 0x003e 136 #define REG_GPIO_MUXCFG 0x0040 137 #define REG_GPIO_IO_SEL 0x0042 138 #define REG_MAC_PINMUX_CFG 0x0043 139 #define REG_GPIO_PIN_CTRL 0x0044 140 #define REG_GPIO_INTM 0x0048 141 #define REG_LEDCFG0 0x004c 142 #define REG_LEDCFG1 0x004d 143 #define REG_LEDCFG2 0x004e 144 #define LEDCFG2_DPDT_SELECT BIT(7) 145 #define REG_LEDCFG3 0x004f 146 #define REG_LEDCFG REG_LEDCFG2 147 #define REG_FSIMR 0x0050 148 #define REG_FSISR 0x0054 149 #define REG_HSIMR 0x0058 150 #define REG_HSISR 0x005c 151 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ 152 #define REG_GPIO_PIN_CTRL_2 0x0060 153 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ 154 #define REG_GPIO_IO_SEL_2 0x0062 155 156 /* RTL8723 only WIFI/BT/GPS Multi-Function control source. */ 157 #define REG_MULTI_FUNC_CTRL 0x0068 158 159 #define MULTI_FN_WIFI_HW_PWRDOWN_EN BIT(0) /* Enable GPIO[9] as WiFi HW 160 powerdown source */ 161 #define MULTI_FN_WIFI_HW_PWRDOWN_SL BIT(1) /* WiFi HW powerdown polarity 162 control */ 163 #define MULTI_WIFI_FUNC_EN BIT(2) /* WiFi function enable */ 164 165 #define MULTI_WIFI_HW_ROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW 166 powerdown source */ 167 #define MULTI_BT_HW_PWRDOWN_EN BIT(16) /* Enable GPIO[11] as BT HW 168 powerdown source */ 169 #define MULTI_BT_HW_PWRDOWN_SL BIT(17) /* BT HW powerdown polarity 170 control */ 171 #define MULTI_BT_FUNC_EN BIT(18) /* BT function enable */ 172 #define MULTI_BT_HW_ROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS 173 RF HW powerdown source */ 174 #define MULTI_GPS_HW_PWRDOWN_EN BIT(20) /* Enable GPIO[10] as GPS HW 175 powerdown source */ 176 #define MULTI_GPS_HW_PWRDOWN_SL BIT(21) /* GPS HW powerdown polarity 177 control */ 178 #define MULTI_GPS_FUNC_EN BIT(22) /* GPS function enable */ 179 180 #define REG_MCU_FW_DL 0x0080 181 #define MCU_FW_DL_ENABLE BIT(0) 182 #define MCU_FW_DL_READY BIT(1) 183 #define MCU_FW_DL_CSUM_REPORT BIT(2) 184 #define MCU_MAC_INIT_READY BIT(3) 185 #define MCU_BB_INIT_READY BIT(4) 186 #define MCU_RF_INIT_READY BIT(5) 187 #define MCU_WINT_INIT_READY BIT(6) 188 #define MCU_FW_RAM_SEL BIT(7) /* 1: RAM, 0:ROM */ 189 #define MCU_CP_RESET BIT(23) 190 191 #define REG_HMBOX_EXT_0 0x0088 192 #define REG_HMBOX_EXT_1 0x008a 193 #define REG_HMBOX_EXT_2 0x008c 194 #define REG_HMBOX_EXT_3 0x008e 195 /* Host suspend counter on FPGA platform */ 196 #define REG_HOST_SUSP_CNT 0x00bc 197 /* Efuse access protection for RTL8723 */ 198 #define REG_EFUSE_ACCESS 0x00cf 199 #define REG_BIST_SCAN 0x00d0 200 #define REG_BIST_RPT 0x00d4 201 #define REG_BIST_ROM_RPT 0x00d8 202 #define REG_USB_SIE_INTF 0x00e0 203 #define REG_PCIE_MIO_INTF 0x00e4 204 #define REG_PCIE_MIO_INTD 0x00e8 205 #define REG_HPON_FSM 0x00ec 206 #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23)) 207 #define HPON_FSM_BONDING_1T2R BIT(22) 208 #define REG_SYS_CFG 0x00f0 209 #define SYS_CFG_XCLK_VLD BIT(0) 210 #define SYS_CFG_ACLK_VLD BIT(1) 211 #define SYS_CFG_UCLK_VLD BIT(2) 212 #define SYS_CFG_PCLK_VLD BIT(3) 213 #define SYS_CFG_PCIRSTB BIT(4) 214 #define SYS_CFG_V15_VLD BIT(5) 215 #define SYS_CFG_TRP_B15V_EN BIT(7) 216 #define SYS_CFG_SIC_IDLE BIT(8) 217 #define SYS_CFG_BD_MAC2 BIT(9) 218 #define SYS_CFG_BD_MAC1 BIT(10) 219 #define SYS_CFG_IC_MACPHY_MODE BIT(11) 220 #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15)) 221 #define SYS_CFG_BT_FUNC BIT(16) 222 #define SYS_CFG_VENDOR_ID BIT(19) 223 #define SYS_CFG_PAD_HWPD_IDN BIT(22) 224 #define SYS_CFG_TRP_VAUX_EN BIT(23) 225 #define SYS_CFG_TRP_BT_EN BIT(24) 226 #define SYS_CFG_BD_PKG_SEL BIT(25) 227 #define SYS_CFG_BD_HCI_SEL BIT(26) 228 #define SYS_CFG_TYPE_ID BIT(27) 229 #define SYS_CFG_RTL_ID BIT(23) /* TestChip ID, 230 1:Test(RLE); 0:MP(RL) */ 231 #define SYS_CFG_SPS_SEL BIT(24) /* 1:LDO regulator mode; 232 0:Switching regulator mode*/ 233 #define SYS_CFG_CHIP_VERSION_MASK 0xf000 /* Bit 12 - 15 */ 234 #define SYS_CFG_CHIP_VERSION_SHIFT 12 235 236 #define REG_GPIO_OUTSTS 0x00f4 /* For RTL8723 only. */ 237 #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1)) 238 #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3)) 239 #define GPIO_HCI_SEL (BIT(4) | BIT(5)) 240 #define GPIO_PKG_SEL_HCI BIT(6) 241 #define GPIO_FEN_GPS BIT(7) 242 #define GPIO_FEN_BT BIT(8) 243 #define GPIO_FEN_WL BIT(9) 244 #define GPIO_FEN_PCI BIT(10) 245 #define GPIO_FEN_USB BIT(11) 246 #define GPIO_BTRF_HWPDN_N BIT(12) 247 #define GPIO_WLRF_HWPDN_N BIT(13) 248 #define GPIO_PDN_BT_N BIT(14) 249 #define GPIO_PDN_GPS_N BIT(15) 250 #define GPIO_BT_CTL_HWPDN BIT(16) 251 #define GPIO_GPS_CTL_HWPDN BIT(17) 252 #define GPIO_PPHY_SUSB BIT(20) 253 #define GPIO_UPHY_SUSB BIT(21) 254 #define GPIO_PCI_SUSEN BIT(22) 255 #define GPIO_USB_SUSEN BIT(23) 256 #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) 257 258 /* 0x0100 ~ 0x01FF MACTOP General Configuration */ 259 #define REG_CR 0x0100 260 #define CR_HCI_TXDMA_ENABLE BIT(0) 261 #define CR_HCI_RXDMA_ENABLE BIT(1) 262 #define CR_TXDMA_ENABLE BIT(2) 263 #define CR_RXDMA_ENABLE BIT(3) 264 #define CR_PROTOCOL_ENABLE BIT(4) 265 #define CR_SCHEDULE_ENABLE BIT(5) 266 #define CR_MAC_TX_ENABLE BIT(6) 267 #define CR_MAC_RX_ENABLE BIT(7) 268 #define CR_SW_BEACON_ENABLE BIT(8) 269 #define CR_SECURITY_ENABLE BIT(9) 270 #define CR_CALTIMER_ENABLE BIT(10) 271 272 /* Media Status Register */ 273 #define REG_MSR 0x0102 274 #define MSR_LINKTYPE_MASK 0x3 275 #define MSR_LINKTYPE_NONE 0x0 276 #define MSR_LINKTYPE_ADHOC 0x1 277 #define MSR_LINKTYPE_STATION 0x2 278 #define MSR_LINKTYPE_AP 0x3 279 280 #define REG_PBP 0x0104 281 #define PBP_PAGE_SIZE_RX_SHIFT 0 282 #define PBP_PAGE_SIZE_TX_SHIFT 4 283 #define PBP_PAGE_SIZE_64 0x0 284 #define PBP_PAGE_SIZE_128 0x1 285 #define PBP_PAGE_SIZE_256 0x2 286 #define PBP_PAGE_SIZE_512 0x3 287 #define PBP_PAGE_SIZE_1024 0x4 288 289 #define REG_TRXDMA_CTRL 0x010c 290 #define TRXDMA_CTRL_VOQ_SHIFT 4 291 #define TRXDMA_CTRL_VIQ_SHIFT 6 292 #define TRXDMA_CTRL_BEQ_SHIFT 8 293 #define TRXDMA_CTRL_BKQ_SHIFT 10 294 #define TRXDMA_CTRL_MGQ_SHIFT 12 295 #define TRXDMA_CTRL_HIQ_SHIFT 14 296 #define TRXDMA_QUEUE_LOW 1 297 #define TRXDMA_QUEUE_NORMAL 2 298 #define TRXDMA_QUEUE_HIGH 3 299 300 #define REG_TRXFF_BNDY 0x0114 301 #define REG_TRXFF_STATUS 0x0118 302 #define REG_RXFF_PTR 0x011c 303 #define REG_HIMR 0x0120 304 #define REG_HISR 0x0124 305 #define REG_HIMRE 0x0128 306 #define REG_HISRE 0x012c 307 #define REG_CPWM 0x012f 308 #define REG_FWIMR 0x0130 309 #define REG_FWISR 0x0134 310 #define REG_PKTBUF_DBG_CTRL 0x0140 311 #define REG_PKTBUF_DBG_DATA_L 0x0144 312 #define REG_PKTBUF_DBG_DATA_H 0x0148 313 314 #define REG_TC0_CTRL 0x0150 315 #define REG_TC1_CTRL 0x0154 316 #define REG_TC2_CTRL 0x0158 317 #define REG_TC3_CTRL 0x015c 318 #define REG_TC4_CTRL 0x0160 319 #define REG_TCUNIT_BASE 0x0164 320 #define REG_MBIST_START 0x0174 321 #define REG_MBIST_DONE 0x0178 322 #define REG_MBIST_FAIL 0x017c 323 #define REG_C2HEVT_MSG_NORMAL 0x01a0 324 #define REG_C2HEVT_CLEAR 0x01af 325 #define REG_C2HEVT_MSG_TEST 0x01b8 326 #define REG_MCUTST_1 0x01c0 327 #define REG_FMTHR 0x01c8 328 #define REG_HMTFR 0x01cc 329 #define REG_HMBOX_0 0x01d0 330 #define REG_HMBOX_1 0x01d4 331 #define REG_HMBOX_2 0x01d8 332 #define REG_HMBOX_3 0x01dc 333 334 #define REG_LLT_INIT 0x01e0 335 #define LLT_OP_INACTIVE 0x0 336 #define LLT_OP_WRITE (0x1 << 30) 337 #define LLT_OP_READ (0x2 << 30) 338 #define LLT_OP_MASK (0x3 << 30) 339 340 #define REG_BB_ACCEESS_CTRL 0x01e8 341 #define REG_BB_ACCESS_DATA 0x01ec 342 343 /* 0x0200 ~ 0x027F TXDMA Configuration */ 344 #define REG_RQPN 0x0200 345 #define RQPN_HI_PQ_SHIFT 0 346 #define RQPN_LO_PQ_SHIFT 8 347 #define RQPN_NORM_PQ_SHIFT 16 348 #define RQPN_LOAD BIT(31) 349 350 #define REG_FIFOPAGE 0x0204 351 #define REG_TDECTRL 0x0208 352 #define REG_TXDMA_OFFSET_CHK 0x020c 353 #define REG_TXDMA_STATUS 0x0210 354 #define REG_RQPN_NPQ 0x0214 355 356 /* 0x0280 ~ 0x02FF RXDMA Configuration */ 357 #define REG_RXDMA_AGG_PG_TH 0x0280 358 #define REG_RXPKT_NUM 0x0284 359 #define REG_RXDMA_STATUS 0x0288 360 361 #define REG_RF_BB_CMD_ADDR 0x02c0 362 #define REG_RF_BB_CMD_DATA 0x02c4 363 364 /* spec version 11 */ 365 /* 0x0400 ~ 0x047F Protocol Configuration */ 366 #define REG_VOQ_INFORMATION 0x0400 367 #define REG_VIQ_INFORMATION 0x0404 368 #define REG_BEQ_INFORMATION 0x0408 369 #define REG_BKQ_INFORMATION 0x040c 370 #define REG_MGQ_INFORMATION 0x0410 371 #define REG_HGQ_INFORMATION 0x0414 372 #define REG_BCNQ_INFORMATION 0x0418 373 374 #define REG_CPU_MGQ_INFORMATION 0x041c 375 #define REG_FWHW_TXQ_CTRL 0x0420 376 #define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7) 377 #define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12) 378 379 #define REG_HWSEQ_CTRL 0x0423 380 #define REG_TXPKTBUF_BCNQ_BDNY 0x0424 381 #define REG_TXPKTBUF_MGQ_BDNY 0x0425 382 #define REG_LIFETIME_EN 0x0426 383 #define REG_MULTI_BCNQ_OFFSET 0x0427 384 385 #define REG_SPEC_SIFS 0x0428 386 #define SPEC_SIFS_CCK_MASK 0x00ff 387 #define SPEC_SIFS_CCK_SHIFT 0 388 #define SPEC_SIFS_OFDM_MASK 0xff00 389 #define SPEC_SIFS_OFDM_SHIFT 8 390 391 #define REG_RETRY_LIMIT 0x042a 392 #define RETRY_LIMIT_LONG_SHIFT 0 393 #define RETRY_LIMIT_LONG_MASK 0x003f 394 #define RETRY_LIMIT_SHORT_SHIFT 8 395 #define RETRY_LIMIT_SHORT_MASK 0x3f00 396 397 #define REG_DARFRC 0x0430 398 #define REG_RARFRC 0x0438 399 #define REG_RESPONSE_RATE_SET 0x0440 400 #define RESPONSE_RATE_BITMAP_ALL 0xfffff 401 #define RESPONSE_RATE_RRSR_CCK_ONLY_1M 0xffff1 402 #define RSR_1M BIT(0) 403 #define RSR_2M BIT(1) 404 #define RSR_5_5M BIT(2) 405 #define RSR_11M BIT(3) 406 #define RSR_6M BIT(4) 407 #define RSR_9M BIT(5) 408 #define RSR_12M BIT(6) 409 #define RSR_18M BIT(7) 410 #define RSR_24M BIT(8) 411 #define RSR_36M BIT(9) 412 #define RSR_48M BIT(10) 413 #define RSR_54M BIT(11) 414 #define RSR_MCS0 BIT(12) 415 #define RSR_MCS1 BIT(13) 416 #define RSR_MCS2 BIT(14) 417 #define RSR_MCS3 BIT(15) 418 #define RSR_MCS4 BIT(16) 419 #define RSR_MCS5 BIT(17) 420 #define RSR_MCS6 BIT(18) 421 #define RSR_MCS7 BIT(19) 422 #define RSR_RSC_LOWER_SUB_CHANNEL BIT(21) /* 0x200000 */ 423 #define RSR_RSC_UPPER_SUB_CHANNEL BIT(22) /* 0x400000 */ 424 #define RSR_RSC_BANDWIDTH_40M (RSR_RSC_UPPER_SUB_CHANNEL | \ 425 RSR_RSC_LOWER_SUB_CHANNEL) 426 #define RSR_ACK_SHORT_PREAMBLE BIT(23) 427 428 #define REG_ARFR0 0x0444 429 #define REG_ARFR1 0x0448 430 #define REG_ARFR2 0x044c 431 #define REG_ARFR3 0x0450 432 #define REG_AGGLEN_LMT 0x0458 433 #define REG_AMPDU_MIN_SPACE 0x045c 434 #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045d 435 #define REG_FAST_EDCA_CTRL 0x0460 436 #define REG_RD_RESP_PKT_TH 0x0463 437 #define REG_INIRTS_RATE_SEL 0x0480 438 #define REG_INIDATA_RATE_SEL 0x0484 439 440 #define REG_POWER_STATUS 0x04a4 441 #define REG_POWER_STAGE1 0x04b4 442 #define REG_POWER_STAGE2 0x04b8 443 #define REG_PKT_VO_VI_LIFE_TIME 0x04c0 444 #define REG_PKT_BE_BK_LIFE_TIME 0x04c2 445 #define REG_STBC_SETTING 0x04c4 446 #define REG_PROT_MODE_CTRL 0x04c8 447 #define REG_MAX_AGGR_NUM 0x04ca 448 #define REG_RTS_MAX_AGGR_NUM 0x04cb 449 #define REG_BAR_MODE_CTRL 0x04cc 450 #define REG_RA_TRY_RATE_AGG_LMT 0x04cf 451 #define REG_NQOS_SEQ 0x04dc 452 #define REG_QOS_SEQ 0x04de 453 #define REG_NEED_CPU_HANDLE 0x04e0 454 #define REG_PKT_LOSE_RPT 0x04e1 455 #define REG_PTCL_ERR_STATUS 0x04e2 456 #define REG_DUMMY 0x04fc 457 458 /* 0x0500 ~ 0x05FF EDCA Configuration */ 459 #define REG_EDCA_VO_PARAM 0x0500 460 #define REG_EDCA_VI_PARAM 0x0504 461 #define REG_EDCA_BE_PARAM 0x0508 462 #define REG_EDCA_BK_PARAM 0x050c 463 #define EDCA_PARAM_ECW_MIN_SHIFT 8 464 #define EDCA_PARAM_ECW_MAX_SHIFT 12 465 #define EDCA_PARAM_TXOP_SHIFT 16 466 #define REG_BEACON_TCFG 0x0510 467 #define REG_PIFS 0x0512 468 #define REG_RDG_PIFS 0x0513 469 #define REG_SIFS_CCK 0x0514 470 #define REG_SIFS_OFDM 0x0516 471 #define REG_TSFTR_SYN_OFFSET 0x0518 472 #define REG_AGGR_BREAK_TIME 0x051a 473 #define REG_SLOT 0x051b 474 #define REG_TX_PTCL_CTRL 0x0520 475 #define REG_TXPAUSE 0x0522 476 #define REG_DIS_TXREQ_CLR 0x0523 477 #define REG_RD_CTRL 0x0524 478 #define REG_TBTT_PROHIBIT 0x0540 479 #define REG_RD_NAV_NXT 0x0544 480 #define REG_NAV_PROT_LEN 0x0546 481 482 #define REG_BEACON_CTRL 0x0550 483 #define REG_BEACON_CTRL_1 0x0551 484 #define BEACON_ATIM BIT(0) 485 #define BEACON_CTRL_MBSSID BIT(1) 486 #define BEACON_CTRL_TX_BEACON_RPT BIT(2) 487 #define BEACON_FUNCTION_ENABLE BIT(3) 488 #define BEACON_DISABLE_TSF_UPDATE BIT(4) 489 490 #define REG_MBID_NUM 0x0552 491 #define REG_DUAL_TSF_RST 0x0553 492 #define DUAL_TSF_RESET_TSF0 BIT(0) 493 #define DUAL_TSF_RESET_TSF1 BIT(1) 494 #define DUAL_TSF_RESET_P2P BIT(4) 495 #define DUAL_TSF_TX_OK BIT(5) 496 497 /* The same as REG_MBSSID_BCN_SPACE */ 498 #define REG_BCN_INTERVAL 0x0554 499 #define REG_MBSSID_BCN_SPACE 0x0554 500 501 #define REG_DRIVER_EARLY_INT 0x0558 502 #define DRIVER_EARLY_INT_TIME 5 503 504 #define REG_BEACON_DMA_TIME 0x0559 505 #define BEACON_DMA_ATIME_INT_TIME 2 506 507 #define REG_ATIMWND 0x055a 508 #define REG_BCN_MAX_ERR 0x055d 509 #define REG_RXTSF_OFFSET_CCK 0x055e 510 #define REG_RXTSF_OFFSET_OFDM 0x055f 511 #define REG_TSFTR 0x0560 512 #define REG_TSFTR1 0x0568 513 #define REG_INIT_TSFTR 0x0564 514 #define REG_ATIMWND_1 0x0570 515 #define REG_PSTIMER 0x0580 516 #define REG_TIMER0 0x0584 517 #define REG_TIMER1 0x0588 518 #define REG_ACM_HW_CTRL 0x05c0 519 #define ACM_HW_CTRL_BK BIT(0) 520 #define ACM_HW_CTRL_BE BIT(1) 521 #define ACM_HW_CTRL_VI BIT(2) 522 #define ACM_HW_CTRL_VO BIT(3) 523 #define REG_ACM_RST_CTRL 0x05c1 524 #define REG_ACMAVG 0x05c2 525 #define REG_VO_ADMTIME 0x05c4 526 #define REG_VI_ADMTIME 0x05c6 527 #define REG_BE_ADMTIME 0x05c8 528 #define REG_EDCA_RANDOM_GEN 0x05cc 529 #define REG_SCH_TXCMD 0x05d0 530 531 /* define REG_FW_TSF_SYNC_CNT 0x04a0 */ 532 #define REG_FW_RESET_TSF_CNT_1 0x05fc 533 #define REG_FW_RESET_TSF_CNT_0 0x05fd 534 #define REG_FW_BCN_DIS_CNT 0x05fe 535 536 /* 0x0600 ~ 0x07FF WMAC Configuration */ 537 #define REG_APSD_CTRL 0x0600 538 #define APSD_CTRL_OFF BIT(6) 539 #define APSD_CTRL_OFF_STATUS BIT(7) 540 #define REG_BW_OPMODE 0x0603 541 #define BW_OPMODE_20MHZ BIT(2) 542 #define BW_OPMODE_5G BIT(1) 543 #define BW_OPMODE_11J BIT(0) 544 545 #define REG_TCR 0x0604 546 547 /* Receive Configuration Register */ 548 #define REG_RCR 0x0608 549 #define RCR_ACCEPT_AP BIT(0) /* Accept all unicast packet */ 550 #define RCR_ACCEPT_PHYS_MATCH BIT(1) /* Accept phys match packet */ 551 #define RCR_ACCEPT_MCAST BIT(2) 552 #define RCR_ACCEPT_BCAST BIT(3) 553 #define RCR_ACCEPT_ADDR3 BIT(4) /* Accept address 3 match 554 packet */ 555 #define RCR_ACCEPT_PM BIT(5) /* Accept power management 556 packet */ 557 #define RCR_CHECK_BSSID_MATCH BIT(6) /* Accept BSSID match packet */ 558 #define RCR_CHECK_BSSID_BEACON BIT(7) /* Accept BSSID match packet 559 (Rx beacon, probe rsp) */ 560 #define RCR_ACCEPT_CRC32 BIT(8) /* Accept CRC32 error packet */ 561 #define RCR_ACCEPT_ICV BIT(9) /* Accept ICV error packet */ 562 #define RCR_ACCEPT_DATA_FRAME BIT(11) 563 #define RCR_ACCEPT_CTRL_FRAME BIT(12) 564 #define RCR_ACCEPT_MGMT_FRAME BIT(13) 565 #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */ 566 #define RCR_MFBEN BIT(22) 567 #define RCR_LSIGEN BIT(23) 568 #define RCR_MULTI_BSSID_ENABLE BIT(24) /* Enable Multiple BssId */ 569 #define RCR_ACCEPT_BA_SSN BIT(27) /* Accept BA SSN */ 570 #define RCR_APPEND_PHYSTAT BIT(28) 571 #define RCR_APPEND_ICV BIT(29) 572 #define RCR_APPEND_MIC BIT(30) 573 #define RCR_APPEND_FCS BIT(31) /* WMAC append FCS after */ 574 575 #define REG_RX_PKT_LIMIT 0x060c 576 #define REG_RX_DLK_TIME 0x060d 577 #define REG_RX_DRVINFO_SZ 0x060f 578 579 #define REG_MACID 0x0610 580 #define REG_BSSID 0x0618 581 #define REG_MAR 0x0620 582 #define REG_MBIDCAMCFG 0x0628 583 584 #define REG_USTIME_EDCA 0x0638 585 #define REG_MAC_SPEC_SIFS 0x063a 586 587 /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ 588 /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ 589 #define REG_R2T_SIFS 0x063c 590 /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ 591 #define REG_T2T_SIFS 0x063e 592 #define REG_ACKTO 0x0640 593 #define REG_CTS2TO 0x0641 594 #define REG_EIFS 0x0642 595 596 /* WMA, BA, CCX */ 597 #define REG_NAV_CTRL 0x0650 598 /* In units of 128us */ 599 #define REG_NAV_UPPER 0x0652 600 #define NAV_UPPER_UNIT 128 601 602 #define REG_BACAMCMD 0x0654 603 #define REG_BACAMCONTENT 0x0658 604 #define REG_LBDLY 0x0660 605 #define REG_FWDLY 0x0661 606 #define REG_RXERR_RPT 0x0664 607 #define REG_WMAC_TRXPTCL_CTL 0x0668 608 609 /* Security */ 610 #define REG_CAM_CMD 0x0670 611 #define CAM_CMD_POLLING BIT(31) 612 #define CAM_CMD_WRITE BIT(16) 613 #define CAM_CMD_KEY_SHIFT 3 614 #define REG_CAM_WRITE 0x0674 615 #define CAM_WRITE_VALID BIT(15) 616 #define REG_CAM_READ 0x0678 617 #define REG_CAM_DEBUG 0x067c 618 #define REG_SECURITY_CFG 0x0680 619 #define SEC_CFG_TX_USE_DEFKEY BIT(0) 620 #define SEC_CFG_RX_USE_DEFKEY BIT(1) 621 #define SEC_CFG_TX_SEC_ENABLE BIT(2) 622 #define SEC_CFG_RX_SEC_ENABLE BIT(3) 623 #define SEC_CFG_SKBYA2 BIT(4) 624 #define SEC_CFG_NO_SKMC BIT(5) 625 #define SEC_CFG_TXBC_USE_DEFKEY BIT(6) 626 #define SEC_CFG_RXBC_USE_DEFKEY BIT(7) 627 628 /* Power */ 629 #define REG_WOW_CTRL 0x0690 630 #define REG_PSSTATUS 0x0691 631 #define REG_PS_RX_INFO 0x0692 632 #define REG_LPNAV_CTRL 0x0694 633 #define REG_WKFMCAM_CMD 0x0698 634 #define REG_WKFMCAM_RWD 0x069c 635 #define REG_RXFLTMAP0 0x06a0 636 #define REG_RXFLTMAP1 0x06a2 637 #define REG_RXFLTMAP2 0x06a4 638 #define REG_BCN_PSR_RPT 0x06a8 639 #define REG_CALB32K_CTRL 0x06ac 640 #define REG_PKT_MON_CTRL 0x06b4 641 #define REG_BT_COEX_TABLE 0x06c0 642 #define REG_WMAC_RESP_TXINFO 0x06d8 643 644 #define REG_MACID1 0x0700 645 #define REG_BSSID1 0x0708 646 647 #define REG_FPGA0_RF_MODE 0x0800 648 #define FPGA_RF_MODE BIT(0) 649 #define FPGA_RF_MODE_JAPAN BIT(1) 650 #define FPGA_RF_MODE_CCK BIT(24) 651 #define FPGA_RF_MODE_OFDM BIT(25) 652 653 #define REG_FPGA0_TX_INFO 0x0804 654 #define REG_FPGA0_PSD_FUNC 0x0808 655 #define REG_FPGA0_TX_GAIN 0x080c 656 #define REG_FPGA0_RF_TIMING1 0x0810 657 #define REG_FPGA0_RF_TIMING2 0x0814 658 #define REG_FPGA0_POWER_SAVE 0x0818 659 #define FPGA0_PS_LOWER_CHANNEL BIT(26) 660 #define FPGA0_PS_UPPER_CHANNEL BIT(27) 661 662 #define REG_FPGA0_XA_HSSI_PARM1 0x0820 /* RF 3 wire register */ 663 #define FPGA0_HSSI_PARM1_PI BIT(8) 664 #define REG_FPGA0_XA_HSSI_PARM2 0x0824 665 #define REG_FPGA0_XB_HSSI_PARM1 0x0828 666 #define REG_FPGA0_XB_HSSI_PARM2 0x082c 667 #define FPGA0_HSSI_3WIRE_DATA_LEN 0x800 668 #define FPGA0_HSSI_3WIRE_ADDR_LEN 0x400 669 #define FPGA0_HSSI_PARM2_ADDR_SHIFT 23 670 #define FPGA0_HSSI_PARM2_ADDR_MASK 0x7f800000 /* 0xff << 23 */ 671 #define FPGA0_HSSI_PARM2_CCK_HIGH_PWR BIT(9) 672 #define FPGA0_HSSI_PARM2_EDGE_READ BIT(31) 673 674 #define REG_TX_AGC_B_RATE18_06 0x0830 675 #define REG_TX_AGC_B_RATE54_24 0x0834 676 #define REG_TX_AGC_B_CCK1_55_MCS32 0x0838 677 #define REG_TX_AGC_B_MCS03_MCS00 0x083c 678 679 #define REG_FPGA0_XA_LSSI_PARM 0x0840 680 #define REG_FPGA0_XB_LSSI_PARM 0x0844 681 #define FPGA0_LSSI_PARM_ADDR_SHIFT 20 682 #define FPGA0_LSSI_PARM_ADDR_MASK 0x0ff00000 683 #define FPGA0_LSSI_PARM_DATA_MASK 0x000fffff 684 685 #define REG_TX_AGC_B_MCS07_MCS04 0x0848 686 #define REG_TX_AGC_B_MCS11_MCS08 0x084c 687 688 #define REG_FPGA0_XCD_SWITCH_CTRL 0x085c 689 690 #define REG_FPGA0_XA_RF_INT_OE 0x0860 /* RF Channel switch */ 691 #define REG_FPGA0_XB_RF_INT_OE 0x0864 692 #define FPGA0_INT_OE_ANTENNA_AB_OPEN 0x000 693 #define FPGA0_INT_OE_ANTENNA_A BIT(8) 694 #define FPGA0_INT_OE_ANTENNA_B BIT(9) 695 #define FPGA0_INT_OE_ANTENNA_MASK (FPGA0_INT_OE_ANTENNA_A | \ 696 FPGA0_INT_OE_ANTENNA_B) 697 698 #define REG_TX_AGC_B_MCS15_MCS12 0x0868 699 #define REG_TX_AGC_B_CCK11_A_CCK2_11 0x086c 700 701 #define REG_FPGA0_XAB_RF_SW_CTRL 0x0870 702 #define REG_FPGA0_XA_RF_SW_CTRL 0x0870 /* 16 bit */ 703 #define REG_FPGA0_XB_RF_SW_CTRL 0x0872 /* 16 bit */ 704 #define REG_FPGA0_XCD_RF_SW_CTRL 0x0874 705 #define REG_FPGA0_XC_RF_SW_CTRL 0x0874 /* 16 bit */ 706 #define REG_FPGA0_XD_RF_SW_CTRL 0x0876 /* 16 bit */ 707 #define FPGA0_RF_3WIRE_DATA BIT(0) 708 #define FPGA0_RF_3WIRE_CLOC BIT(1) 709 #define FPGA0_RF_3WIRE_LOAD BIT(2) 710 #define FPGA0_RF_3WIRE_RW BIT(3) 711 #define FPGA0_RF_3WIRE_MASK 0xf 712 #define FPGA0_RF_RFENV BIT(4) 713 #define FPGA0_RF_TRSW BIT(5) /* Useless now */ 714 #define FPGA0_RF_TRSWB BIT(6) 715 #define FPGA0_RF_ANTSW BIT(8) 716 #define FPGA0_RF_ANTSWB BIT(9) 717 #define FPGA0_RF_PAPE BIT(10) 718 #define FPGA0_RF_PAPE5G BIT(11) 719 #define FPGA0_RF_BD_CTRL_SHIFT 16 720 721 #define REG_FPGA0_XAB_RF_PARM 0x0878 /* Antenna select path in ODM */ 722 #define REG_FPGA0_XA_RF_PARM 0x0878 /* 16 bit */ 723 #define REG_FPGA0_XB_RF_PARM 0x087a /* 16 bit */ 724 #define REG_FPGA0_XCD_RF_PARM 0x087c 725 #define REG_FPGA0_XC_RF_PARM 0x087c /* 16 bit */ 726 #define REG_FPGA0_XD_RF_PARM 0x087e /* 16 bit */ 727 #define FPGA0_RF_PARM_RFA_ENABLE BIT(1) 728 #define FPGA0_RF_PARM_RFB_ENABLE BIT(17) 729 #define FPGA0_RF_PARM_CLK_GATE BIT(31) 730 731 #define REG_FPGA0_ANALOG1 0x0880 732 #define REG_FPGA0_ANALOG2 0x0884 733 #define FPGA0_ANALOG2_20MHZ BIT(10) 734 #define REG_FPGA0_ANALOG3 0x0888 735 #define REG_FPGA0_ANALOG4 0x088c 736 737 #define REG_FPGA0_XA_LSSI_READBACK 0x08a0 /* Tranceiver LSSI Readback */ 738 #define REG_FPGA0_XB_LSSI_READBACK 0x08a4 739 #define REG_HSPI_XA_READBACK 0x08b8 /* Transceiver A HSPI read */ 740 #define REG_HSPI_XB_READBACK 0x08bc /* Transceiver B HSPI read */ 741 742 #define REG_FPGA1_RF_MODE 0x0900 743 744 #define REG_FPGA1_TX_INFO 0x090c 745 746 #define REG_CCK0_SYSTEM 0x0a00 747 #define CCK0_SIDEBAND BIT(4) 748 749 #define REG_CCK0_AFE_SETTING 0x0a04 750 751 #define REG_CONFIG_ANT_A 0x0b68 752 #define REG_CONFIG_ANT_B 0x0b6c 753 754 #define REG_OFDM0_TRX_PATH_ENABLE 0x0c04 755 #define OFDM_RF_PATH_RX_MASK 0x0f 756 #define OFDM_RF_PATH_RX_A BIT(0) 757 #define OFDM_RF_PATH_RX_B BIT(1) 758 #define OFDM_RF_PATH_RX_C BIT(2) 759 #define OFDM_RF_PATH_RX_D BIT(3) 760 #define OFDM_RF_PATH_TX_MASK 0xf0 761 #define OFDM_RF_PATH_TX_A BIT(4) 762 #define OFDM_RF_PATH_TX_B BIT(5) 763 #define OFDM_RF_PATH_TX_C BIT(6) 764 #define OFDM_RF_PATH_TX_D BIT(7) 765 766 #define REG_OFDM0_TR_MUX_PAR 0x0c08 767 768 #define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14 769 #define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c 770 771 #define REG_OFDM0_ENERGY_CCA_THRES 0x0c4c 772 773 #define REG_OFDM0_XA_AGC_CORE1 0x0c50 774 #define REG_OFDM0_XA_AGC_CORE2 0x0c54 775 #define REG_OFDM0_XB_AGC_CORE1 0x0c58 776 #define REG_OFDM0_XB_AGC_CORE2 0x0c5c 777 #define REG_OFDM0_XC_AGC_CORE1 0x0c60 778 #define REG_OFDM0_XC_AGC_CORE2 0x0c64 779 #define REG_OFDM0_XD_AGC_CORE1 0x0c68 780 #define REG_OFDM0_XD_AGC_CORE2 0x0c6c 781 #define OFDM0_X_AGC_CORE1_IGI_MASK 0x0000007F 782 783 #define REG_OFDM0_AGC_PARM1 0x0c70 784 785 #define REG_OFDM0_AGCR_SSI_TABLE 0x0c78 786 787 #define REG_OFDM0_XA_TX_IQ_IMBALANCE 0x0c80 788 #define REG_OFDM0_XB_TX_IQ_IMBALANCE 0x0c88 789 #define REG_OFDM0_XC_TX_IQ_IMBALANCE 0x0c90 790 #define REG_OFDM0_XD_TX_IQ_IMBALANCE 0x0c98 791 792 #define REG_OFDM0_XC_TX_AFE 0x0c94 793 #define REG_OFDM0_XD_TX_AFE 0x0c9c 794 795 #define REG_OFDM0_RX_IQ_EXT_ANTA 0x0ca0 796 797 #define REG_OFDM1_LSTF 0x0d00 798 #define OFDM_LSTF_PRIME_CH_LOW BIT(10) 799 #define OFDM_LSTF_PRIME_CH_HIGH BIT(11) 800 #define OFDM_LSTF_PRIME_CH_MASK (OFDM_LSTF_PRIME_CH_LOW | \ 801 OFDM_LSTF_PRIME_CH_HIGH) 802 #define OFDM_LSTF_CONTINUE_TX BIT(28) 803 #define OFDM_LSTF_SINGLE_CARRIER BIT(29) 804 #define OFDM_LSTF_SINGLE_TONE BIT(30) 805 #define OFDM_LSTF_MASK 0x70000000 806 807 #define REG_OFDM1_TRX_PATH_ENABLE 0x0d04 808 809 #define REG_TX_AGC_A_RATE18_06 0x0e00 810 #define REG_TX_AGC_A_RATE54_24 0x0e04 811 #define REG_TX_AGC_A_CCK1_MCS32 0x0e08 812 #define REG_TX_AGC_A_MCS03_MCS00 0x0e10 813 #define REG_TX_AGC_A_MCS07_MCS04 0x0e14 814 #define REG_TX_AGC_A_MCS11_MCS08 0x0e18 815 #define REG_TX_AGC_A_MCS15_MCS12 0x0e1c 816 817 #define REG_FPGA0_IQK 0x0e28 818 819 #define REG_TX_IQK_TONE_A 0x0e30 820 #define REG_RX_IQK_TONE_A 0x0e34 821 #define REG_TX_IQK_PI_A 0x0e38 822 #define REG_RX_IQK_PI_A 0x0e3c 823 824 #define REG_TX_IQK 0x0e40 825 #define REG_RX_IQK 0x0e44 826 #define REG_IQK_AGC_PTS 0x0e48 827 #define REG_IQK_AGC_RSP 0x0e4c 828 #define REG_TX_IQK_TONE_B 0x0e50 829 #define REG_RX_IQK_TONE_B 0x0e54 830 #define REG_TX_IQK_PI_B 0x0e58 831 #define REG_RX_IQK_PI_B 0x0e5c 832 #define REG_IQK_AGC_CONT 0x0e60 833 834 #define REG_BLUETOOTH 0x0e6c 835 #define REG_RX_WAIT_CCA 0x0e70 836 #define REG_TX_CCK_RFON 0x0e74 837 #define REG_TX_CCK_BBON 0x0e78 838 #define REG_TX_OFDM_RFON 0x0e7c 839 #define REG_TX_OFDM_BBON 0x0e80 840 #define REG_TX_TO_RX 0x0e84 841 #define REG_TX_TO_TX 0x0e88 842 #define REG_RX_CCK 0x0e8c 843 844 #define REG_TX_POWER_BEFORE_IQK_A 0x0e94 845 #define REG_TX_POWER_AFTER_IQK_A 0x0e9c 846 847 #define REG_RX_POWER_BEFORE_IQK_A 0x0ea0 848 #define REG_RX_POWER_BEFORE_IQK_A_2 0x0ea4 849 #define REG_RX_POWER_AFTER_IQK_A 0x0ea8 850 #define REG_RX_POWER_AFTER_IQK_A_2 0x0eac 851 852 #define REG_TX_POWER_BEFORE_IQK_B 0x0eb4 853 #define REG_TX_POWER_AFTER_IQK_B 0x0ebc 854 855 #define REG_RX_POWER_BEFORE_IQK_B 0x0ec0 856 #define REG_RX_POWER_BEFORE_IQK_B_2 0x0ec4 857 #define REG_RX_POWER_AFTER_IQK_B 0x0ec8 858 #define REG_RX_POWER_AFTER_IQK_B_2 0x0ecc 859 860 #define REG_RX_OFDM 0x0ed0 861 #define REG_RX_WAIT_RIFS 0x0ed4 862 #define REG_RX_TO_RX 0x0ed8 863 #define REG_STANDBY 0x0edc 864 #define REG_SLEEP 0x0ee0 865 #define REG_PMPD_ANAEN 0x0eec 866 867 #define REG_FW_START_ADDRESS 0x1000 868 869 #define REG_USB_INFO 0xfe17 870 #define REG_USB_HIMR 0xfe38 871 #define USB_HIMR_TIMEOUT2 BIT(31) 872 #define USB_HIMR_TIMEOUT1 BIT(30) 873 #define USB_HIMR_PSTIMEOUT BIT(29) 874 #define USB_HIMR_GTINT4 BIT(28) 875 #define USB_HIMR_GTINT3 BIT(27) 876 #define USB_HIMR_TXBCNERR BIT(26) 877 #define USB_HIMR_TXBCNOK BIT(25) 878 #define USB_HIMR_TSF_BIT32_TOGGLE BIT(24) 879 #define USB_HIMR_BCNDMAINT3 BIT(23) 880 #define USB_HIMR_BCNDMAINT2 BIT(22) 881 #define USB_HIMR_BCNDMAINT1 BIT(21) 882 #define USB_HIMR_BCNDMAINT0 BIT(20) 883 #define USB_HIMR_BCNDOK3 BIT(19) 884 #define USB_HIMR_BCNDOK2 BIT(18) 885 #define USB_HIMR_BCNDOK1 BIT(17) 886 #define USB_HIMR_BCNDOK0 BIT(16) 887 #define USB_HIMR_HSISR_IND BIT(15) 888 #define USB_HIMR_BCNDMAINT_E BIT(14) 889 /* RSVD BIT(13) */ 890 #define USB_HIMR_CTW_END BIT(12) 891 /* RSVD BIT(11) */ 892 #define USB_HIMR_C2HCMD BIT(10) 893 #define USB_HIMR_CPWM2 BIT(9) 894 #define USB_HIMR_CPWM BIT(8) 895 #define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK 896 Interrupt */ 897 #define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK 898 Interrupt */ 899 #define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */ 900 #define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */ 901 #define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */ 902 #define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */ 903 #define USB_HIMR_RDU BIT(1) /* Receive Descriptor 904 Unavailable */ 905 #define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */ 906 907 #define REG_USB_SPECIAL_OPTION 0xfe55 908 #define REG_USB_DMA_AGG_TO 0xfe5b 909 #define REG_USB_AGG_TO 0xfe5c 910 #define REG_USB_AGG_TH 0xfe5d 911 912 #define REG_NORMAL_SIE_VID 0xfe60 /* 0xfe60 - 0xfe61 */ 913 #define REG_NORMAL_SIE_PID 0xfe62 /* 0xfe62 - 0xfe63 */ 914 #define REG_NORMAL_SIE_OPTIONAL 0xfe64 915 #define REG_NORMAL_SIE_EP 0xfe65 /* 0xfe65 - 0xfe67 */ 916 #define REG_NORMAL_SIE_EP_TX 0xfe66 917 #define NORMAL_SIE_EP_TX_HIGH_MASK 0x000f 918 #define NORMAL_SIE_EP_TX_NORMAL_MASK 0x00f0 919 #define NORMAL_SIE_EP_TX_LOW_MASK 0x0f00 920 921 #define REG_NORMAL_SIE_PHY 0xfe68 /* 0xfe68 - 0xfe6b */ 922 #define REG_NORMAL_SIE_OPTIONAL2 0xfe6c 923 #define REG_NORMAL_SIE_GPS_EP 0xfe6d /* RTL8723 only */ 924 #define REG_NORMAL_SIE_MAC_ADDR 0xfe70 /* 0xfe70 - 0xfe75 */ 925 #define REG_NORMAL_SIE_STRING 0xfe80 /* 0xfe80 - 0xfedf */ 926 927 /* RF6052 registers */ 928 #define RF6052_REG_AC 0x00 929 #define RF6052_REG_IQADJ_G1 0x01 930 #define RF6052_REG_IQADJ_G2 0x02 931 #define RF6052_REG_BS_PA_APSET_G1_G4 0x03 932 #define RF6052_REG_BS_PA_APSET_G5_G8 0x04 933 #define RF6052_REG_POW_TRSW 0x05 934 #define RF6052_REG_GAIN_RX 0x06 935 #define RF6052_REG_GAIN_TX 0x07 936 #define RF6052_REG_TXM_IDAC 0x08 937 #define RF6052_REG_IPA_G 0x09 938 #define RF6052_REG_TXBIAS_G 0x0a 939 #define RF6052_REG_TXPA_AG 0x0b 940 #define RF6052_REG_IPA_A 0x0c 941 #define RF6052_REG_TXBIAS_A 0x0d 942 #define RF6052_REG_BS_PA_APSET_G9_G11 0x0e 943 #define RF6052_REG_BS_IQGEN 0x0f 944 #define RF6052_REG_MODE1 0x10 945 #define RF6052_REG_MODE2 0x11 946 #define RF6052_REG_RX_AGC_HP 0x12 947 #define RF6052_REG_TX_AGC 0x13 948 #define RF6052_REG_BIAS 0x14 949 #define RF6052_REG_IPA 0x15 950 #define RF6052_REG_TXBIAS 0x16 951 #define RF6052_REG_POW_ABILITY 0x17 952 #define RF6052_REG_MODE_AG 0x18 /* RF channel and BW switch */ 953 #define MODE_AG_CHANNEL_MASK 0x3ff 954 #define MODE_AG_CHANNEL_20MHZ BIT(10) 955 956 #define RF6052_REG_TOP 0x19 957 #define RF6052_REG_RX_G1 0x1a 958 #define RF6052_REG_RX_G2 0x1b 959 #define RF6052_REG_RX_BB2 0x1c 960 #define RF6052_REG_RX_BB1 0x1d 961 #define RF6052_REG_RCK1 0x1e 962 #define RF6052_REG_RCK2 0x1f 963 #define RF6052_REG_TX_G1 0x20 964 #define RF6052_REG_TX_G2 0x21 965 #define RF6052_REG_TX_G3 0x22 966 #define RF6052_REG_TX_BB1 0x23 967 #define RF6052_REG_T_METER 0x24 968 #define RF6052_REG_SYN_G1 0x25 /* RF TX Power control */ 969 #define RF6052_REG_SYN_G2 0x26 /* RF TX Power control */ 970 #define RF6052_REG_SYN_G3 0x27 /* RF TX Power control */ 971 #define RF6052_REG_SYN_G4 0x28 /* RF TX Power control */ 972 #define RF6052_REG_SYN_G5 0x29 /* RF TX Power control */ 973 #define RF6052_REG_SYN_G6 0x2a /* RF TX Power control */ 974 #define RF6052_REG_SYN_G7 0x2b /* RF TX Power control */ 975 #define RF6052_REG_SYN_G8 0x2c /* RF TX Power control */ 976 977 #define RF6052_REG_RCK_OS 0x30 /* RF TX PA control */ 978 979 #define RF6052_REG_TXPA_G1 0x31 /* RF TX PA control */ 980 #define RF6052_REG_TXPA_G2 0x32 /* RF TX PA control */ 981 #define RF6052_REG_TXPA_G3 0x33 /* RF TX PA control */ 982