1 /* 2 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com> 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * Register definitions taken from original Realtek rtl8723au driver 14 */ 15 16 /* 0x0000 ~ 0x00FF System Configuration */ 17 #define REG_SYS_ISO_CTRL 0x0000 18 #define SYS_ISO_MD2PP BIT(0) 19 #define SYS_ISO_ANALOG_IPS BIT(5) 20 #define SYS_ISO_DIOR BIT(9) 21 #define SYS_ISO_PWC_EV25V BIT(14) 22 #define SYS_ISO_PWC_EV12V BIT(15) 23 24 #define REG_SYS_FUNC 0x0002 25 #define SYS_FUNC_BBRSTB BIT(0) 26 #define SYS_FUNC_BB_GLB_RSTN BIT(1) 27 #define SYS_FUNC_USBA BIT(2) 28 #define SYS_FUNC_UPLL BIT(3) 29 #define SYS_FUNC_USBD BIT(4) 30 #define SYS_FUNC_DIO_PCIE BIT(5) 31 #define SYS_FUNC_PCIEA BIT(6) 32 #define SYS_FUNC_PPLL BIT(7) 33 #define SYS_FUNC_PCIED BIT(8) 34 #define SYS_FUNC_DIOE BIT(9) 35 #define SYS_FUNC_CPU_ENABLE BIT(10) 36 #define SYS_FUNC_DCORE BIT(11) 37 #define SYS_FUNC_ELDR BIT(12) 38 #define SYS_FUNC_DIO_RF BIT(13) 39 #define SYS_FUNC_HWPDN BIT(14) 40 #define SYS_FUNC_MREGEN BIT(15) 41 42 #define REG_APS_FSMCO 0x0004 43 #define APS_FSMCO_PFM_ALDN BIT(1) 44 #define APS_FSMCO_PFM_WOWL BIT(3) 45 #define APS_FSMCO_ENABLE_POWERDOWN BIT(4) 46 #define APS_FSMCO_MAC_ENABLE BIT(8) 47 #define APS_FSMCO_MAC_OFF BIT(9) 48 #define APS_FSMCO_SW_LPS BIT(10) 49 #define APS_FSMCO_HW_SUSPEND BIT(11) 50 #define APS_FSMCO_PCIE BIT(12) 51 #define APS_FSMCO_HW_POWERDOWN BIT(15) 52 #define APS_FSMCO_WLON_RESET BIT(16) 53 54 #define REG_SYS_CLKR 0x0008 55 #define SYS_CLK_ANAD16V_ENABLE BIT(0) 56 #define SYS_CLK_ANA8M BIT(1) 57 #define SYS_CLK_MACSLP BIT(4) 58 #define SYS_CLK_LOADER_ENABLE BIT(5) 59 #define SYS_CLK_80M_SSC_DISABLE BIT(7) 60 #define SYS_CLK_80M_SSC_ENABLE_HO BIT(8) 61 #define SYS_CLK_PHY_SSC_RSTB BIT(9) 62 #define SYS_CLK_SEC_CLK_ENABLE BIT(10) 63 #define SYS_CLK_MAC_CLK_ENABLE BIT(11) 64 #define SYS_CLK_ENABLE BIT(12) 65 #define SYS_CLK_RING_CLK_ENABLE BIT(13) 66 67 #define REG_9346CR 0x000a 68 #define EEPROM_BOOT BIT(4) 69 #define EEPROM_ENABLE BIT(5) 70 71 #define REG_EE_VPD 0x000c 72 #define REG_AFE_MISC 0x0010 73 #define AFE_MISC_WL_XTAL_CTRL BIT(6) 74 75 #define REG_SPS0_CTRL 0x0011 76 #define REG_SPS_OCP_CFG 0x0018 77 #define REG_8192E_LDOV12_CTRL 0x0014 78 #define REG_RSV_CTRL 0x001c 79 80 #define REG_RF_CTRL 0x001f 81 #define RF_ENABLE BIT(0) 82 #define RF_RSTB BIT(1) 83 #define RF_SDMRSTB BIT(2) 84 85 #define REG_LDOA15_CTRL 0x0020 86 #define LDOA15_ENABLE BIT(0) 87 #define LDOA15_STANDBY BIT(1) 88 #define LDOA15_OBUF BIT(2) 89 #define LDOA15_REG_VOS BIT(3) 90 #define LDOA15_VOADJ_SHIFT 4 91 92 #define REG_LDOV12D_CTRL 0x0021 93 #define LDOV12D_ENABLE BIT(0) 94 #define LDOV12D_STANDBY BIT(1) 95 #define LDOV12D_VADJ_SHIFT 4 96 97 #define REG_LDOHCI12_CTRL 0x0022 98 99 #define REG_LPLDO_CTRL 0x0023 100 #define LPLDO_HSM BIT(2) 101 #define LPLDO_LSM_DIS BIT(3) 102 103 #define REG_AFE_XTAL_CTRL 0x0024 104 #define AFE_XTAL_ENABLE BIT(0) 105 #define AFE_XTAL_B_SELECT BIT(1) 106 #define AFE_XTAL_GATE_USB BIT(8) 107 #define AFE_XTAL_GATE_AFE BIT(11) 108 #define AFE_XTAL_RF_GATE BIT(14) 109 #define AFE_XTAL_GATE_DIG BIT(17) 110 #define AFE_XTAL_BT_GATE BIT(20) 111 112 #define REG_AFE_PLL_CTRL 0x0028 113 #define AFE_PLL_ENABLE BIT(0) 114 #define AFE_PLL_320_ENABLE BIT(1) 115 #define APE_PLL_FREF_SELECT BIT(2) 116 #define AFE_PLL_EDGE_SELECT BIT(3) 117 #define AFE_PLL_WDOGB BIT(4) 118 #define AFE_PLL_LPF_ENABLE BIT(5) 119 120 #define REG_MAC_PHY_CTRL 0x002c 121 122 #define REG_EFUSE_CTRL 0x0030 123 #define REG_EFUSE_TEST 0x0034 124 #define EFUSE_TRPT BIT(7) 125 /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ 126 #define EFUSE_CELL_SEL (BIT(8) | BIT(9)) 127 #define EFUSE_LDOE25_ENABLE BIT(31) 128 #define EFUSE_SELECT_MASK 0x0300 129 #define EFUSE_WIFI_SELECT 0x0000 130 #define EFUSE_BT0_SELECT 0x0100 131 #define EFUSE_BT1_SELECT 0x0200 132 #define EFUSE_BT2_SELECT 0x0300 133 134 #define EFUSE_ACCESS_ENABLE 0x69 /* RTL8723 only */ 135 #define EFUSE_ACCESS_DISABLE 0x00 /* RTL8723 only */ 136 137 #define REG_PWR_DATA 0x0038 138 #define PWR_DATA_EEPRPAD_RFE_CTRL_EN BIT(11) 139 140 #define REG_CAL_TIMER 0x003c 141 #define REG_ACLK_MON 0x003e 142 #define REG_GPIO_MUXCFG 0x0040 143 #define REG_GPIO_IO_SEL 0x0042 144 #define REG_MAC_PINMUX_CFG 0x0043 145 #define REG_GPIO_PIN_CTRL 0x0044 146 #define REG_GPIO_INTM 0x0048 147 #define GPIO_INTM_EDGE_TRIG_IRQ BIT(9) 148 149 #define REG_LEDCFG0 0x004c 150 #define LEDCFG0_DPDT_SELECT BIT(23) 151 #define REG_LEDCFG1 0x004d 152 #define REG_LEDCFG2 0x004e 153 #define LEDCFG2_DPDT_SELECT BIT(7) 154 #define REG_LEDCFG3 0x004f 155 #define REG_LEDCFG REG_LEDCFG2 156 #define REG_FSIMR 0x0050 157 #define REG_FSISR 0x0054 158 #define REG_HSIMR 0x0058 159 #define REG_HSISR 0x005c 160 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ 161 #define REG_GPIO_PIN_CTRL_2 0x0060 162 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ 163 #define REG_GPIO_IO_SEL_2 0x0062 164 #define GPIO_IO_SEL_2_GPIO09_INPUT BIT(1) 165 #define GPIO_IO_SEL_2_GPIO09_IRQ BIT(9) 166 167 /* RTL8723B */ 168 #define REG_PAD_CTRL1 0x0064 169 #define PAD_CTRL1_SW_DPDT_SEL_DATA BIT(0) 170 171 /* RTL8723 only WIFI/BT/GPS Multi-Function control source. */ 172 #define REG_MULTI_FUNC_CTRL 0x0068 173 174 #define MULTI_FN_WIFI_HW_PWRDOWN_EN BIT(0) /* Enable GPIO[9] as WiFi HW 175 powerdown source */ 176 #define MULTI_FN_WIFI_HW_PWRDOWN_SL BIT(1) /* WiFi HW powerdown polarity 177 control */ 178 #define MULTI_WIFI_FUNC_EN BIT(2) /* WiFi function enable */ 179 180 #define MULTI_WIFI_HW_ROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW 181 powerdown source */ 182 #define MULTI_BT_HW_PWRDOWN_EN BIT(16) /* Enable GPIO[11] as BT HW 183 powerdown source */ 184 #define MULTI_BT_HW_PWRDOWN_SL BIT(17) /* BT HW powerdown polarity 185 control */ 186 #define MULTI_BT_FUNC_EN BIT(18) /* BT function enable */ 187 #define MULTI_BT_HW_ROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS 188 RF HW powerdown source */ 189 #define MULTI_GPS_HW_PWRDOWN_EN BIT(20) /* Enable GPIO[10] as GPS HW 190 powerdown source */ 191 #define MULTI_GPS_HW_PWRDOWN_SL BIT(21) /* GPS HW powerdown polarity 192 control */ 193 #define MULTI_GPS_FUNC_EN BIT(22) /* GPS function enable */ 194 195 #define REG_LDO_SW_CTRL 0x007c /* 8192eu */ 196 197 #define REG_MCU_FW_DL 0x0080 198 #define MCU_FW_DL_ENABLE BIT(0) 199 #define MCU_FW_DL_READY BIT(1) 200 #define MCU_FW_DL_CSUM_REPORT BIT(2) 201 #define MCU_MAC_INIT_READY BIT(3) 202 #define MCU_BB_INIT_READY BIT(4) 203 #define MCU_RF_INIT_READY BIT(5) 204 #define MCU_WINT_INIT_READY BIT(6) 205 #define MCU_FW_RAM_SEL BIT(7) /* 1: RAM, 0:ROM */ 206 #define MCU_CP_RESET BIT(23) 207 208 #define REG_HMBOX_EXT_0 0x0088 209 #define REG_HMBOX_EXT_1 0x008a 210 #define REG_HMBOX_EXT_2 0x008c 211 #define REG_HMBOX_EXT_3 0x008e 212 /* Interrupt registers for 8192e/8723bu/8812 */ 213 #define REG_HIMR0 0x00b0 214 #define REG_HISR0 0x00b4 215 #define REG_HIMR1 0x00b8 216 #define REG_HISR1 0x00bc 217 218 /* Host suspend counter on FPGA platform */ 219 #define REG_HOST_SUSP_CNT 0x00bc 220 /* Efuse access protection for RTL8723 */ 221 #define REG_EFUSE_ACCESS 0x00cf 222 #define REG_BIST_SCAN 0x00d0 223 #define REG_BIST_RPT 0x00d4 224 #define REG_BIST_ROM_RPT 0x00d8 225 #define REG_USB_SIE_INTF 0x00e0 226 #define REG_PCIE_MIO_INTF 0x00e4 227 #define REG_PCIE_MIO_INTD 0x00e8 228 #define REG_HPON_FSM 0x00ec 229 #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23)) 230 #define HPON_FSM_BONDING_1T2R BIT(22) 231 #define REG_SYS_CFG 0x00f0 232 #define SYS_CFG_XCLK_VLD BIT(0) 233 #define SYS_CFG_ACLK_VLD BIT(1) 234 #define SYS_CFG_UCLK_VLD BIT(2) 235 #define SYS_CFG_PCLK_VLD BIT(3) 236 #define SYS_CFG_PCIRSTB BIT(4) 237 #define SYS_CFG_V15_VLD BIT(5) 238 #define SYS_CFG_TRP_B15V_EN BIT(7) 239 #define SYS_CFG_SW_OFFLOAD_EN BIT(7) /* For chips with IOL support */ 240 #define SYS_CFG_SIC_IDLE BIT(8) 241 #define SYS_CFG_BD_MAC2 BIT(9) 242 #define SYS_CFG_BD_MAC1 BIT(10) 243 #define SYS_CFG_IC_MACPHY_MODE BIT(11) 244 #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15)) 245 #define SYS_CFG_BT_FUNC BIT(16) 246 #define SYS_CFG_VENDOR_ID BIT(19) 247 #define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19)) 248 #define SYS_CFG_VENDOR_ID_TSMC 0 249 #define SYS_CFG_VENDOR_ID_SMIC BIT(18) 250 #define SYS_CFG_VENDOR_ID_UMC BIT(19) 251 #define SYS_CFG_PAD_HWPD_IDN BIT(22) 252 #define SYS_CFG_TRP_VAUX_EN BIT(23) 253 #define SYS_CFG_TRP_BT_EN BIT(24) 254 #define SYS_CFG_SPS_LDO_SEL BIT(24) /* 8192eu */ 255 #define SYS_CFG_BD_PKG_SEL BIT(25) 256 #define SYS_CFG_BD_HCI_SEL BIT(26) 257 #define SYS_CFG_TYPE_ID BIT(27) 258 #define SYS_CFG_RTL_ID BIT(23) /* TestChip ID, 259 1:Test(RLE); 0:MP(RL) */ 260 #define SYS_CFG_SPS_SEL BIT(24) /* 1:LDO regulator mode; 261 0:Switching regulator mode*/ 262 #define SYS_CFG_CHIP_VERSION_MASK 0xf000 /* Bit 12 - 15 */ 263 #define SYS_CFG_CHIP_VERSION_SHIFT 12 264 265 #define REG_GPIO_OUTSTS 0x00f4 /* For RTL8723 only. */ 266 #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1)) 267 #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3)) 268 #define GPIO_HCI_SEL (BIT(4) | BIT(5)) 269 #define GPIO_PKG_SEL_HCI BIT(6) 270 #define GPIO_FEN_GPS BIT(7) 271 #define GPIO_FEN_BT BIT(8) 272 #define GPIO_FEN_WL BIT(9) 273 #define GPIO_FEN_PCI BIT(10) 274 #define GPIO_FEN_USB BIT(11) 275 #define GPIO_BTRF_HWPDN_N BIT(12) 276 #define GPIO_WLRF_HWPDN_N BIT(13) 277 #define GPIO_PDN_BT_N BIT(14) 278 #define GPIO_PDN_GPS_N BIT(15) 279 #define GPIO_BT_CTL_HWPDN BIT(16) 280 #define GPIO_GPS_CTL_HWPDN BIT(17) 281 #define GPIO_PPHY_SUSB BIT(20) 282 #define GPIO_UPHY_SUSB BIT(21) 283 #define GPIO_PCI_SUSEN BIT(22) 284 #define GPIO_USB_SUSEN BIT(23) 285 #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) 286 287 #define REG_SYS_CFG2 0x00fc /* 8192eu */ 288 289 /* 0x0100 ~ 0x01FF MACTOP General Configuration */ 290 #define REG_CR 0x0100 291 #define CR_HCI_TXDMA_ENABLE BIT(0) 292 #define CR_HCI_RXDMA_ENABLE BIT(1) 293 #define CR_TXDMA_ENABLE BIT(2) 294 #define CR_RXDMA_ENABLE BIT(3) 295 #define CR_PROTOCOL_ENABLE BIT(4) 296 #define CR_SCHEDULE_ENABLE BIT(5) 297 #define CR_MAC_TX_ENABLE BIT(6) 298 #define CR_MAC_RX_ENABLE BIT(7) 299 #define CR_SW_BEACON_ENABLE BIT(8) 300 #define CR_SECURITY_ENABLE BIT(9) 301 #define CR_CALTIMER_ENABLE BIT(10) 302 303 /* Media Status Register */ 304 #define REG_MSR 0x0102 305 #define MSR_LINKTYPE_MASK 0x3 306 #define MSR_LINKTYPE_NONE 0x0 307 #define MSR_LINKTYPE_ADHOC 0x1 308 #define MSR_LINKTYPE_STATION 0x2 309 #define MSR_LINKTYPE_AP 0x3 310 311 #define REG_PBP 0x0104 312 #define PBP_PAGE_SIZE_RX_SHIFT 0 313 #define PBP_PAGE_SIZE_TX_SHIFT 4 314 #define PBP_PAGE_SIZE_64 0x0 315 #define PBP_PAGE_SIZE_128 0x1 316 #define PBP_PAGE_SIZE_256 0x2 317 #define PBP_PAGE_SIZE_512 0x3 318 #define PBP_PAGE_SIZE_1024 0x4 319 320 #define REG_TRXDMA_CTRL 0x010c 321 #define TRXDMA_CTRL_RXDMA_AGG_EN BIT(2) 322 #define TRXDMA_CTRL_VOQ_SHIFT 4 323 #define TRXDMA_CTRL_VIQ_SHIFT 6 324 #define TRXDMA_CTRL_BEQ_SHIFT 8 325 #define TRXDMA_CTRL_BKQ_SHIFT 10 326 #define TRXDMA_CTRL_MGQ_SHIFT 12 327 #define TRXDMA_CTRL_HIQ_SHIFT 14 328 #define TRXDMA_QUEUE_LOW 1 329 #define TRXDMA_QUEUE_NORMAL 2 330 #define TRXDMA_QUEUE_HIGH 3 331 332 #define REG_TRXFF_BNDY 0x0114 333 #define REG_TRXFF_STATUS 0x0118 334 #define REG_RXFF_PTR 0x011c 335 #define REG_HIMR 0x0120 336 #define REG_HISR 0x0124 337 #define REG_HIMRE 0x0128 338 #define REG_HISRE 0x012c 339 #define REG_CPWM 0x012f 340 #define REG_FWIMR 0x0130 341 #define REG_FWISR 0x0134 342 #define REG_PKTBUF_DBG_CTRL 0x0140 343 #define REG_PKTBUF_DBG_DATA_L 0x0144 344 #define REG_PKTBUF_DBG_DATA_H 0x0148 345 346 #define REG_TC0_CTRL 0x0150 347 #define REG_TC1_CTRL 0x0154 348 #define REG_TC2_CTRL 0x0158 349 #define REG_TC3_CTRL 0x015c 350 #define REG_TC4_CTRL 0x0160 351 #define REG_TCUNIT_BASE 0x0164 352 #define REG_MBIST_START 0x0174 353 #define REG_MBIST_DONE 0x0178 354 #define REG_MBIST_FAIL 0x017c 355 #define REG_C2HEVT_MSG_NORMAL 0x01a0 356 /* 8192EU/8723BU/8812 */ 357 #define REG_C2HEVT_CMD_ID_8723B 0x01ae 358 #define REG_C2HEVT_CLEAR 0x01af 359 #define REG_C2HEVT_MSG_TEST 0x01b8 360 #define REG_MCUTST_1 0x01c0 361 #define REG_FMTHR 0x01c8 362 #define REG_HMTFR 0x01cc 363 #define REG_HMBOX_0 0x01d0 364 #define REG_HMBOX_1 0x01d4 365 #define REG_HMBOX_2 0x01d8 366 #define REG_HMBOX_3 0x01dc 367 368 #define REG_LLT_INIT 0x01e0 369 #define LLT_OP_INACTIVE 0x0 370 #define LLT_OP_WRITE (0x1 << 30) 371 #define LLT_OP_READ (0x2 << 30) 372 #define LLT_OP_MASK (0x3 << 30) 373 374 #define REG_BB_ACCEESS_CTRL 0x01e8 375 #define REG_BB_ACCESS_DATA 0x01ec 376 377 #define REG_HMBOX_EXT0_8723B 0x01f0 378 #define REG_HMBOX_EXT1_8723B 0x01f4 379 #define REG_HMBOX_EXT2_8723B 0x01f8 380 #define REG_HMBOX_EXT3_8723B 0x01fc 381 382 /* 0x0200 ~ 0x027F TXDMA Configuration */ 383 #define REG_RQPN 0x0200 384 #define RQPN_HI_PQ_SHIFT 0 385 #define RQPN_LO_PQ_SHIFT 8 386 #define RQPN_NORM_PQ_SHIFT 16 387 #define RQPN_LOAD BIT(31) 388 389 #define REG_FIFOPAGE 0x0204 390 #define REG_TDECTRL 0x0208 391 #define REG_TXDMA_OFFSET_CHK 0x020c 392 #define TXDMA_OFFSET_DROP_DATA_EN BIT(9) 393 #define REG_TXDMA_STATUS 0x0210 394 #define REG_RQPN_NPQ 0x0214 395 #define RQPN_NPQ_SHIFT 0 396 #define RQPN_EPQ_SHIFT 16 397 398 #define REG_AUTO_LLT 0x0224 399 #define AUTO_LLT_INIT_LLT BIT(16) 400 401 #define REG_DWBCN1_CTRL_8723B 0x0228 402 403 /* 0x0280 ~ 0x02FF RXDMA Configuration */ 404 #define REG_RXDMA_AGG_PG_TH 0x0280 405 #define RXDMA_USB_AGG_ENABLE BIT(31) 406 #define REG_RXPKT_NUM 0x0284 407 #define RXPKT_NUM_RXDMA_IDLE BIT(17) 408 #define RXPKT_NUM_RW_RELEASE_EN BIT(18) 409 #define REG_RXDMA_STATUS 0x0288 410 411 /* Presumably only found on newer chips such as 8723bu */ 412 #define REG_RX_DMA_CTRL_8723B 0x0286 413 #define REG_RXDMA_PRO_8723B 0x0290 414 415 #define REG_RF_BB_CMD_ADDR 0x02c0 416 #define REG_RF_BB_CMD_DATA 0x02c4 417 418 /* spec version 11 */ 419 /* 0x0400 ~ 0x047F Protocol Configuration */ 420 #define REG_VOQ_INFORMATION 0x0400 421 #define REG_VIQ_INFORMATION 0x0404 422 #define REG_BEQ_INFORMATION 0x0408 423 #define REG_BKQ_INFORMATION 0x040c 424 #define REG_MGQ_INFORMATION 0x0410 425 #define REG_HGQ_INFORMATION 0x0414 426 #define REG_BCNQ_INFORMATION 0x0418 427 428 #define REG_CPU_MGQ_INFORMATION 0x041c 429 #define REG_FWHW_TXQ_CTRL 0x0420 430 #define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7) 431 #define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12) 432 433 #define REG_HWSEQ_CTRL 0x0423 434 #define REG_TXPKTBUF_BCNQ_BDNY 0x0424 435 #define REG_TXPKTBUF_MGQ_BDNY 0x0425 436 #define REG_LIFETIME_EN 0x0426 437 #define REG_MULTI_BCNQ_OFFSET 0x0427 438 439 #define REG_SPEC_SIFS 0x0428 440 #define SPEC_SIFS_CCK_MASK 0x00ff 441 #define SPEC_SIFS_CCK_SHIFT 0 442 #define SPEC_SIFS_OFDM_MASK 0xff00 443 #define SPEC_SIFS_OFDM_SHIFT 8 444 445 #define REG_RETRY_LIMIT 0x042a 446 #define RETRY_LIMIT_LONG_SHIFT 0 447 #define RETRY_LIMIT_LONG_MASK 0x003f 448 #define RETRY_LIMIT_SHORT_SHIFT 8 449 #define RETRY_LIMIT_SHORT_MASK 0x3f00 450 451 #define REG_DARFRC 0x0430 452 #define REG_RARFRC 0x0438 453 #define REG_RESPONSE_RATE_SET 0x0440 454 #define RESPONSE_RATE_BITMAP_ALL 0xfffff 455 #define RESPONSE_RATE_RRSR_CCK_ONLY_1M 0xffff1 456 #define RSR_1M BIT(0) 457 #define RSR_2M BIT(1) 458 #define RSR_5_5M BIT(2) 459 #define RSR_11M BIT(3) 460 #define RSR_6M BIT(4) 461 #define RSR_9M BIT(5) 462 #define RSR_12M BIT(6) 463 #define RSR_18M BIT(7) 464 #define RSR_24M BIT(8) 465 #define RSR_36M BIT(9) 466 #define RSR_48M BIT(10) 467 #define RSR_54M BIT(11) 468 #define RSR_MCS0 BIT(12) 469 #define RSR_MCS1 BIT(13) 470 #define RSR_MCS2 BIT(14) 471 #define RSR_MCS3 BIT(15) 472 #define RSR_MCS4 BIT(16) 473 #define RSR_MCS5 BIT(17) 474 #define RSR_MCS6 BIT(18) 475 #define RSR_MCS7 BIT(19) 476 #define RSR_RSC_LOWER_SUB_CHANNEL BIT(21) /* 0x200000 */ 477 #define RSR_RSC_UPPER_SUB_CHANNEL BIT(22) /* 0x400000 */ 478 #define RSR_RSC_BANDWIDTH_40M (RSR_RSC_UPPER_SUB_CHANNEL | \ 479 RSR_RSC_LOWER_SUB_CHANNEL) 480 #define RSR_ACK_SHORT_PREAMBLE BIT(23) 481 482 #define REG_ARFR0 0x0444 483 #define REG_ARFR1 0x0448 484 #define REG_ARFR2 0x044c 485 #define REG_ARFR3 0x0450 486 #define REG_AMPDU_MAX_TIME_8723B 0x0456 487 #define REG_AGGLEN_LMT 0x0458 488 #define REG_AMPDU_MIN_SPACE 0x045c 489 #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045d 490 #define REG_FAST_EDCA_CTRL 0x0460 491 #define REG_RD_RESP_PKT_TH 0x0463 492 #define REG_INIRTS_RATE_SEL 0x0480 493 /* 8723bu */ 494 #define REG_DATA_SUBCHANNEL 0x0483 495 /* 8723au */ 496 #define REG_INIDATA_RATE_SEL 0x0484 497 498 #define REG_POWER_STATUS 0x04a4 499 #define REG_POWER_STAGE1 0x04b4 500 #define REG_POWER_STAGE2 0x04b8 501 #define REG_AMPDU_BURST_MODE_8723B 0x04bc 502 #define REG_PKT_VO_VI_LIFE_TIME 0x04c0 503 #define REG_PKT_BE_BK_LIFE_TIME 0x04c2 504 #define REG_STBC_SETTING 0x04c4 505 #define REG_HT_SINGLE_AMPDU_8723B 0x04c7 506 #define REG_PROT_MODE_CTRL 0x04c8 507 #define REG_MAX_AGGR_NUM 0x04ca 508 #define REG_RTS_MAX_AGGR_NUM 0x04cb 509 #define REG_BAR_MODE_CTRL 0x04cc 510 #define REG_RA_TRY_RATE_AGG_LMT 0x04cf 511 #define REG_NQOS_SEQ 0x04dc 512 #define REG_QOS_SEQ 0x04de 513 #define REG_NEED_CPU_HANDLE 0x04e0 514 #define REG_PKT_LOSE_RPT 0x04e1 515 #define REG_PTCL_ERR_STATUS 0x04e2 516 #define REG_TX_REPORT_CTRL 0x04ec 517 #define TX_REPORT_CTRL_TIMER_ENABLE BIT(1) 518 519 #define REG_TX_REPORT_TIME 0x04f0 520 #define REG_DUMMY 0x04fc 521 522 /* 0x0500 ~ 0x05FF EDCA Configuration */ 523 #define REG_EDCA_VO_PARAM 0x0500 524 #define REG_EDCA_VI_PARAM 0x0504 525 #define REG_EDCA_BE_PARAM 0x0508 526 #define REG_EDCA_BK_PARAM 0x050c 527 #define EDCA_PARAM_ECW_MIN_SHIFT 8 528 #define EDCA_PARAM_ECW_MAX_SHIFT 12 529 #define EDCA_PARAM_TXOP_SHIFT 16 530 #define REG_BEACON_TCFG 0x0510 531 #define REG_PIFS 0x0512 532 #define REG_RDG_PIFS 0x0513 533 #define REG_SIFS_CCK 0x0514 534 #define REG_SIFS_OFDM 0x0516 535 #define REG_TSFTR_SYN_OFFSET 0x0518 536 #define REG_AGGR_BREAK_TIME 0x051a 537 #define REG_SLOT 0x051b 538 #define REG_TX_PTCL_CTRL 0x0520 539 #define REG_TXPAUSE 0x0522 540 #define REG_DIS_TXREQ_CLR 0x0523 541 #define REG_RD_CTRL 0x0524 542 #define REG_TBTT_PROHIBIT 0x0540 543 #define REG_RD_NAV_NXT 0x0544 544 #define REG_NAV_PROT_LEN 0x0546 545 546 #define REG_BEACON_CTRL 0x0550 547 #define REG_BEACON_CTRL_1 0x0551 548 #define BEACON_ATIM BIT(0) 549 #define BEACON_CTRL_MBSSID BIT(1) 550 #define BEACON_CTRL_TX_BEACON_RPT BIT(2) 551 #define BEACON_FUNCTION_ENABLE BIT(3) 552 #define BEACON_DISABLE_TSF_UPDATE BIT(4) 553 554 #define REG_MBID_NUM 0x0552 555 #define REG_DUAL_TSF_RST 0x0553 556 #define DUAL_TSF_RESET_TSF0 BIT(0) 557 #define DUAL_TSF_RESET_TSF1 BIT(1) 558 #define DUAL_TSF_RESET_P2P BIT(4) 559 #define DUAL_TSF_TX_OK BIT(5) 560 561 /* The same as REG_MBSSID_BCN_SPACE */ 562 #define REG_BCN_INTERVAL 0x0554 563 #define REG_MBSSID_BCN_SPACE 0x0554 564 565 #define REG_DRIVER_EARLY_INT 0x0558 566 #define DRIVER_EARLY_INT_TIME 5 567 568 #define REG_BEACON_DMA_TIME 0x0559 569 #define BEACON_DMA_ATIME_INT_TIME 2 570 571 #define REG_ATIMWND 0x055a 572 #define REG_USTIME_TSF_8723B 0x055c 573 #define REG_BCN_MAX_ERR 0x055d 574 #define REG_RXTSF_OFFSET_CCK 0x055e 575 #define REG_RXTSF_OFFSET_OFDM 0x055f 576 #define REG_TSFTR 0x0560 577 #define REG_TSFTR1 0x0568 578 #define REG_INIT_TSFTR 0x0564 579 #define REG_ATIMWND_1 0x0570 580 #define REG_PSTIMER 0x0580 581 #define REG_TIMER0 0x0584 582 #define REG_TIMER1 0x0588 583 #define REG_ACM_HW_CTRL 0x05c0 584 #define ACM_HW_CTRL_BK BIT(0) 585 #define ACM_HW_CTRL_BE BIT(1) 586 #define ACM_HW_CTRL_VI BIT(2) 587 #define ACM_HW_CTRL_VO BIT(3) 588 #define REG_ACM_RST_CTRL 0x05c1 589 #define REG_ACMAVG 0x05c2 590 #define REG_VO_ADMTIME 0x05c4 591 #define REG_VI_ADMTIME 0x05c6 592 #define REG_BE_ADMTIME 0x05c8 593 #define REG_EDCA_RANDOM_GEN 0x05cc 594 #define REG_SCH_TXCMD 0x05d0 595 596 /* define REG_FW_TSF_SYNC_CNT 0x04a0 */ 597 #define REG_FW_RESET_TSF_CNT_1 0x05fc 598 #define REG_FW_RESET_TSF_CNT_0 0x05fd 599 #define REG_FW_BCN_DIS_CNT 0x05fe 600 601 /* 0x0600 ~ 0x07FF WMAC Configuration */ 602 #define REG_APSD_CTRL 0x0600 603 #define APSD_CTRL_OFF BIT(6) 604 #define APSD_CTRL_OFF_STATUS BIT(7) 605 #define REG_BW_OPMODE 0x0603 606 #define BW_OPMODE_20MHZ BIT(2) 607 #define BW_OPMODE_5G BIT(1) 608 #define BW_OPMODE_11J BIT(0) 609 610 #define REG_TCR 0x0604 611 612 /* Receive Configuration Register */ 613 #define REG_RCR 0x0608 614 #define RCR_ACCEPT_AP BIT(0) /* Accept all unicast packet */ 615 #define RCR_ACCEPT_PHYS_MATCH BIT(1) /* Accept phys match packet */ 616 #define RCR_ACCEPT_MCAST BIT(2) 617 #define RCR_ACCEPT_BCAST BIT(3) 618 #define RCR_ACCEPT_ADDR3 BIT(4) /* Accept address 3 match 619 packet */ 620 #define RCR_ACCEPT_PM BIT(5) /* Accept power management 621 packet */ 622 #define RCR_CHECK_BSSID_MATCH BIT(6) /* Accept BSSID match packet */ 623 #define RCR_CHECK_BSSID_BEACON BIT(7) /* Accept BSSID match packet 624 (Rx beacon, probe rsp) */ 625 #define RCR_ACCEPT_CRC32 BIT(8) /* Accept CRC32 error packet */ 626 #define RCR_ACCEPT_ICV BIT(9) /* Accept ICV error packet */ 627 #define RCR_ACCEPT_DATA_FRAME BIT(11) /* Accept all data pkt or use 628 REG_RXFLTMAP2 */ 629 #define RCR_ACCEPT_CTRL_FRAME BIT(12) /* Accept all control pkt or use 630 REG_RXFLTMAP1 */ 631 #define RCR_ACCEPT_MGMT_FRAME BIT(13) /* Accept all mgmt pkt or use 632 REG_RXFLTMAP0 */ 633 #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */ 634 #define RCR_UC_DATA_PKT_INT_ENABLE BIT(16) /* Enable unicast data packet 635 interrupt */ 636 #define RCR_BM_DATA_PKT_INT_ENABLE BIT(17) /* Enable broadcast data packet 637 interrupt */ 638 #define RCR_TIM_PARSER_ENABLE BIT(18) /* Enable RX beacon TIM parser*/ 639 #define RCR_MFBEN BIT(22) 640 #define RCR_LSIG_ENABLE BIT(23) /* Enable LSIG TXOP Protection 641 function. Search KEYCAM for 642 each rx packet to check if 643 LSIGEN bit is set. */ 644 #define RCR_MULTI_BSSID_ENABLE BIT(24) /* Enable Multiple BssId */ 645 #define RCR_FORCE_ACK BIT(26) 646 #define RCR_ACCEPT_BA_SSN BIT(27) /* Accept BA SSN */ 647 #define RCR_APPEND_PHYSTAT BIT(28) 648 #define RCR_APPEND_ICV BIT(29) 649 #define RCR_APPEND_MIC BIT(30) 650 #define RCR_APPEND_FCS BIT(31) /* WMAC append FCS after */ 651 652 #define REG_RX_PKT_LIMIT 0x060c 653 #define REG_RX_DLK_TIME 0x060d 654 #define REG_RX_DRVINFO_SZ 0x060f 655 656 #define REG_MACID 0x0610 657 #define REG_BSSID 0x0618 658 #define REG_MAR 0x0620 659 #define REG_MBIDCAMCFG 0x0628 660 661 #define REG_USTIME_EDCA 0x0638 662 #define REG_MAC_SPEC_SIFS 0x063a 663 664 /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ 665 /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ 666 #define REG_R2T_SIFS 0x063c 667 /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ 668 #define REG_T2T_SIFS 0x063e 669 #define REG_ACKTO 0x0640 670 #define REG_CTS2TO 0x0641 671 #define REG_EIFS 0x0642 672 673 /* WMA, BA, CCX */ 674 #define REG_NAV_CTRL 0x0650 675 /* In units of 128us */ 676 #define REG_NAV_UPPER 0x0652 677 #define NAV_UPPER_UNIT 128 678 679 #define REG_BACAMCMD 0x0654 680 #define REG_BACAMCONTENT 0x0658 681 #define REG_LBDLY 0x0660 682 #define REG_FWDLY 0x0661 683 #define REG_RXERR_RPT 0x0664 684 #define REG_WMAC_TRXPTCL_CTL 0x0668 685 #define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8)) 686 #define WMAC_TRXPTCL_CTL_BW_20 0 687 #define WMAC_TRXPTCL_CTL_BW_40 BIT(7) 688 #define WMAC_TRXPTCL_CTL_BW_80 BIT(8) 689 690 /* Security */ 691 #define REG_CAM_CMD 0x0670 692 #define CAM_CMD_POLLING BIT(31) 693 #define CAM_CMD_WRITE BIT(16) 694 #define CAM_CMD_KEY_SHIFT 3 695 #define REG_CAM_WRITE 0x0674 696 #define CAM_WRITE_VALID BIT(15) 697 #define REG_CAM_READ 0x0678 698 #define REG_CAM_DEBUG 0x067c 699 #define REG_SECURITY_CFG 0x0680 700 #define SEC_CFG_TX_USE_DEFKEY BIT(0) 701 #define SEC_CFG_RX_USE_DEFKEY BIT(1) 702 #define SEC_CFG_TX_SEC_ENABLE BIT(2) 703 #define SEC_CFG_RX_SEC_ENABLE BIT(3) 704 #define SEC_CFG_SKBYA2 BIT(4) 705 #define SEC_CFG_NO_SKMC BIT(5) 706 #define SEC_CFG_TXBC_USE_DEFKEY BIT(6) 707 #define SEC_CFG_RXBC_USE_DEFKEY BIT(7) 708 709 /* Power */ 710 #define REG_WOW_CTRL 0x0690 711 #define REG_PSSTATUS 0x0691 712 #define REG_PS_RX_INFO 0x0692 713 #define REG_LPNAV_CTRL 0x0694 714 #define REG_WKFMCAM_CMD 0x0698 715 #define REG_WKFMCAM_RWD 0x069c 716 717 /* 718 * RX Filters: each bit corresponds to the numerical value of the subtype. 719 * If it is set the subtype frame type is passed. The filter is only used when 720 * the RCR_ACCEPT_DATA_FRAME, RCR_ACCEPT_CTRL_FRAME, RCR_ACCEPT_MGMT_FRAME bit 721 * in the RCR are low. 722 * 723 * Example: Beacon subtype is binary 1000 which is decimal 8 so we have to set 724 * bit 8 (0x100) in REG_RXFLTMAP0 to enable reception. 725 */ 726 #define REG_RXFLTMAP0 0x06a0 /* Management frames */ 727 #define REG_RXFLTMAP1 0x06a2 /* Control frames */ 728 #define REG_RXFLTMAP2 0x06a4 /* Data frames */ 729 730 #define REG_BCN_PSR_RPT 0x06a8 731 #define REG_CALB32K_CTRL 0x06ac 732 #define REG_PKT_MON_CTRL 0x06b4 733 #define REG_BT_COEX_TABLE1 0x06c0 734 #define REG_BT_COEX_TABLE2 0x06c4 735 #define REG_BT_COEX_TABLE3 0x06c8 736 #define REG_BT_COEX_TABLE4 0x06cc 737 #define REG_WMAC_RESP_TXINFO 0x06d8 738 739 #define REG_MACID1 0x0700 740 #define REG_BSSID1 0x0708 741 742 /* 743 * This seems to be 8723bu specific 744 */ 745 #define REG_BT_CONTROL_8723BU 0x0764 746 #define BT_CONTROL_BT_GRANT BIT(12) 747 748 #define REG_WLAN_ACT_CONTROL_8723B 0x076e 749 750 #define REG_FPGA0_RF_MODE 0x0800 751 #define FPGA_RF_MODE BIT(0) 752 #define FPGA_RF_MODE_JAPAN BIT(1) 753 #define FPGA_RF_MODE_CCK BIT(24) 754 #define FPGA_RF_MODE_OFDM BIT(25) 755 756 #define REG_FPGA0_TX_INFO 0x0804 757 #define REG_FPGA0_PSD_FUNC 0x0808 758 #define REG_FPGA0_TX_GAIN 0x080c 759 #define REG_FPGA0_RF_TIMING1 0x0810 760 #define REG_FPGA0_RF_TIMING2 0x0814 761 #define REG_FPGA0_POWER_SAVE 0x0818 762 #define FPGA0_PS_LOWER_CHANNEL BIT(26) 763 #define FPGA0_PS_UPPER_CHANNEL BIT(27) 764 765 #define REG_FPGA0_XA_HSSI_PARM1 0x0820 /* RF 3 wire register */ 766 #define FPGA0_HSSI_PARM1_PI BIT(8) 767 #define REG_FPGA0_XA_HSSI_PARM2 0x0824 768 #define REG_FPGA0_XB_HSSI_PARM1 0x0828 769 #define REG_FPGA0_XB_HSSI_PARM2 0x082c 770 #define FPGA0_HSSI_3WIRE_DATA_LEN 0x800 771 #define FPGA0_HSSI_3WIRE_ADDR_LEN 0x400 772 #define FPGA0_HSSI_PARM2_ADDR_SHIFT 23 773 #define FPGA0_HSSI_PARM2_ADDR_MASK 0x7f800000 /* 0xff << 23 */ 774 #define FPGA0_HSSI_PARM2_CCK_HIGH_PWR BIT(9) 775 #define FPGA0_HSSI_PARM2_EDGE_READ BIT(31) 776 777 #define REG_TX_AGC_B_RATE18_06 0x0830 778 #define REG_TX_AGC_B_RATE54_24 0x0834 779 #define REG_TX_AGC_B_CCK1_55_MCS32 0x0838 780 #define REG_TX_AGC_B_MCS03_MCS00 0x083c 781 782 #define REG_FPGA0_XA_LSSI_PARM 0x0840 783 #define REG_FPGA0_XB_LSSI_PARM 0x0844 784 #define FPGA0_LSSI_PARM_ADDR_SHIFT 20 785 #define FPGA0_LSSI_PARM_ADDR_MASK 0x0ff00000 786 #define FPGA0_LSSI_PARM_DATA_MASK 0x000fffff 787 788 #define REG_TX_AGC_B_MCS07_MCS04 0x0848 789 #define REG_TX_AGC_B_MCS11_MCS08 0x084c 790 791 #define REG_FPGA0_XCD_SWITCH_CTRL 0x085c 792 793 #define REG_FPGA0_XA_RF_INT_OE 0x0860 /* RF Channel switch */ 794 #define REG_FPGA0_XB_RF_INT_OE 0x0864 795 #define FPGA0_INT_OE_ANTENNA_AB_OPEN 0x000 796 #define FPGA0_INT_OE_ANTENNA_A BIT(8) 797 #define FPGA0_INT_OE_ANTENNA_B BIT(9) 798 #define FPGA0_INT_OE_ANTENNA_MASK (FPGA0_INT_OE_ANTENNA_A | \ 799 FPGA0_INT_OE_ANTENNA_B) 800 801 #define REG_TX_AGC_B_MCS15_MCS12 0x0868 802 #define REG_TX_AGC_B_CCK11_A_CCK2_11 0x086c 803 804 #define REG_FPGA0_XAB_RF_SW_CTRL 0x0870 805 #define REG_FPGA0_XA_RF_SW_CTRL 0x0870 /* 16 bit */ 806 #define REG_FPGA0_XB_RF_SW_CTRL 0x0872 /* 16 bit */ 807 #define REG_FPGA0_XCD_RF_SW_CTRL 0x0874 808 #define REG_FPGA0_XC_RF_SW_CTRL 0x0874 /* 16 bit */ 809 #define REG_FPGA0_XD_RF_SW_CTRL 0x0876 /* 16 bit */ 810 #define FPGA0_RF_3WIRE_DATA BIT(0) 811 #define FPGA0_RF_3WIRE_CLOC BIT(1) 812 #define FPGA0_RF_3WIRE_LOAD BIT(2) 813 #define FPGA0_RF_3WIRE_RW BIT(3) 814 #define FPGA0_RF_3WIRE_MASK 0xf 815 #define FPGA0_RF_RFENV BIT(4) 816 #define FPGA0_RF_TRSW BIT(5) /* Useless now */ 817 #define FPGA0_RF_TRSWB BIT(6) 818 #define FPGA0_RF_ANTSW BIT(8) 819 #define FPGA0_RF_ANTSWB BIT(9) 820 #define FPGA0_RF_PAPE BIT(10) 821 #define FPGA0_RF_PAPE5G BIT(11) 822 #define FPGA0_RF_BD_CTRL_SHIFT 16 823 824 #define REG_FPGA0_XAB_RF_PARM 0x0878 /* Antenna select path in ODM */ 825 #define REG_FPGA0_XA_RF_PARM 0x0878 /* 16 bit */ 826 #define REG_FPGA0_XB_RF_PARM 0x087a /* 16 bit */ 827 #define REG_FPGA0_XCD_RF_PARM 0x087c 828 #define REG_FPGA0_XC_RF_PARM 0x087c /* 16 bit */ 829 #define REG_FPGA0_XD_RF_PARM 0x087e /* 16 bit */ 830 #define FPGA0_RF_PARM_RFA_ENABLE BIT(1) 831 #define FPGA0_RF_PARM_RFB_ENABLE BIT(17) 832 #define FPGA0_RF_PARM_CLK_GATE BIT(31) 833 834 #define REG_FPGA0_ANALOG1 0x0880 835 #define REG_FPGA0_ANALOG2 0x0884 836 #define FPGA0_ANALOG2_20MHZ BIT(10) 837 #define REG_FPGA0_ANALOG3 0x0888 838 #define REG_FPGA0_ANALOG4 0x088c 839 840 #define REG_NHM_TH9_TH10_8723B 0x0890 841 #define REG_NHM_TIMER_8723B 0x0894 842 #define REG_NHM_TH3_TO_TH0_8723B 0x0898 843 #define REG_NHM_TH7_TO_TH4_8723B 0x089c 844 845 #define REG_FPGA0_XA_LSSI_READBACK 0x08a0 /* Tranceiver LSSI Readback */ 846 #define REG_FPGA0_XB_LSSI_READBACK 0x08a4 847 #define REG_HSPI_XA_READBACK 0x08b8 /* Transceiver A HSPI read */ 848 #define REG_HSPI_XB_READBACK 0x08bc /* Transceiver B HSPI read */ 849 850 #define REG_FPGA1_RF_MODE 0x0900 851 852 #define REG_FPGA1_TX_INFO 0x090c 853 #define REG_DPDT_CTRL 0x092c /* 8723BU */ 854 #define REG_RFE_CTRL_ANTA_SRC 0x0930 /* 8723BU */ 855 #define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */ 856 #define REG_RFE_BUFFER 0x0944 /* 8723BU */ 857 #define REG_S0S1_PATH_SWITCH 0x0948 /* 8723BU */ 858 859 #define REG_CCK0_SYSTEM 0x0a00 860 #define CCK0_SIDEBAND BIT(4) 861 862 #define REG_CCK0_AFE_SETTING 0x0a04 863 864 #define REG_CONFIG_ANT_A 0x0b68 865 #define REG_CONFIG_ANT_B 0x0b6c 866 867 #define REG_OFDM0_TRX_PATH_ENABLE 0x0c04 868 #define OFDM_RF_PATH_RX_MASK 0x0f 869 #define OFDM_RF_PATH_RX_A BIT(0) 870 #define OFDM_RF_PATH_RX_B BIT(1) 871 #define OFDM_RF_PATH_RX_C BIT(2) 872 #define OFDM_RF_PATH_RX_D BIT(3) 873 #define OFDM_RF_PATH_TX_MASK 0xf0 874 #define OFDM_RF_PATH_TX_A BIT(4) 875 #define OFDM_RF_PATH_TX_B BIT(5) 876 #define OFDM_RF_PATH_TX_C BIT(6) 877 #define OFDM_RF_PATH_TX_D BIT(7) 878 879 #define REG_OFDM0_TR_MUX_PAR 0x0c08 880 881 #define REG_OFDM0_FA_RSTC 0x0c0c 882 883 #define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14 884 #define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c 885 886 #define REG_OFDM0_ENERGY_CCA_THRES 0x0c4c 887 888 #define REG_OFDM0_RX_D_SYNC_PATH 0x0c40 889 #define OFDM0_SYNC_PATH_NOTCH_FILTER BIT(1) 890 891 #define REG_OFDM0_XA_AGC_CORE1 0x0c50 892 #define REG_OFDM0_XA_AGC_CORE2 0x0c54 893 #define REG_OFDM0_XB_AGC_CORE1 0x0c58 894 #define REG_OFDM0_XB_AGC_CORE2 0x0c5c 895 #define REG_OFDM0_XC_AGC_CORE1 0x0c60 896 #define REG_OFDM0_XC_AGC_CORE2 0x0c64 897 #define REG_OFDM0_XD_AGC_CORE1 0x0c68 898 #define REG_OFDM0_XD_AGC_CORE2 0x0c6c 899 #define OFDM0_X_AGC_CORE1_IGI_MASK 0x0000007F 900 901 #define REG_OFDM0_AGC_PARM1 0x0c70 902 903 #define REG_OFDM0_AGCR_SSI_TABLE 0x0c78 904 905 #define REG_OFDM0_XA_TX_IQ_IMBALANCE 0x0c80 906 #define REG_OFDM0_XB_TX_IQ_IMBALANCE 0x0c88 907 #define REG_OFDM0_XC_TX_IQ_IMBALANCE 0x0c90 908 #define REG_OFDM0_XD_TX_IQ_IMBALANCE 0x0c98 909 910 #define REG_OFDM0_XC_TX_AFE 0x0c94 911 #define REG_OFDM0_XD_TX_AFE 0x0c9c 912 913 #define REG_OFDM0_RX_IQ_EXT_ANTA 0x0ca0 914 915 /* 8723bu */ 916 #define REG_OFDM0_TX_PSDO_NOISE_WEIGHT 0x0ce4 917 918 #define REG_OFDM1_LSTF 0x0d00 919 #define OFDM_LSTF_PRIME_CH_LOW BIT(10) 920 #define OFDM_LSTF_PRIME_CH_HIGH BIT(11) 921 #define OFDM_LSTF_PRIME_CH_MASK (OFDM_LSTF_PRIME_CH_LOW | \ 922 OFDM_LSTF_PRIME_CH_HIGH) 923 #define OFDM_LSTF_CONTINUE_TX BIT(28) 924 #define OFDM_LSTF_SINGLE_CARRIER BIT(29) 925 #define OFDM_LSTF_SINGLE_TONE BIT(30) 926 #define OFDM_LSTF_MASK 0x70000000 927 928 #define REG_OFDM1_TRX_PATH_ENABLE 0x0d04 929 930 #define REG_TX_AGC_A_RATE18_06 0x0e00 931 #define REG_TX_AGC_A_RATE54_24 0x0e04 932 #define REG_TX_AGC_A_CCK1_MCS32 0x0e08 933 #define REG_TX_AGC_A_MCS03_MCS00 0x0e10 934 #define REG_TX_AGC_A_MCS07_MCS04 0x0e14 935 #define REG_TX_AGC_A_MCS11_MCS08 0x0e18 936 #define REG_TX_AGC_A_MCS15_MCS12 0x0e1c 937 938 #define REG_FPGA0_IQK 0x0e28 939 940 #define REG_TX_IQK_TONE_A 0x0e30 941 #define REG_RX_IQK_TONE_A 0x0e34 942 #define REG_TX_IQK_PI_A 0x0e38 943 #define REG_RX_IQK_PI_A 0x0e3c 944 945 #define REG_TX_IQK 0x0e40 946 #define REG_RX_IQK 0x0e44 947 #define REG_IQK_AGC_PTS 0x0e48 948 #define REG_IQK_AGC_RSP 0x0e4c 949 #define REG_TX_IQK_TONE_B 0x0e50 950 #define REG_RX_IQK_TONE_B 0x0e54 951 #define REG_TX_IQK_PI_B 0x0e58 952 #define REG_RX_IQK_PI_B 0x0e5c 953 #define REG_IQK_AGC_CONT 0x0e60 954 955 #define REG_BLUETOOTH 0x0e6c 956 #define REG_RX_WAIT_CCA 0x0e70 957 #define REG_TX_CCK_RFON 0x0e74 958 #define REG_TX_CCK_BBON 0x0e78 959 #define REG_TX_OFDM_RFON 0x0e7c 960 #define REG_TX_OFDM_BBON 0x0e80 961 #define REG_TX_TO_RX 0x0e84 962 #define REG_TX_TO_TX 0x0e88 963 #define REG_RX_CCK 0x0e8c 964 965 #define REG_TX_POWER_BEFORE_IQK_A 0x0e94 966 #define REG_TX_POWER_AFTER_IQK_A 0x0e9c 967 968 #define REG_RX_POWER_BEFORE_IQK_A 0x0ea0 969 #define REG_RX_POWER_BEFORE_IQK_A_2 0x0ea4 970 #define REG_RX_POWER_AFTER_IQK_A 0x0ea8 971 #define REG_RX_POWER_AFTER_IQK_A_2 0x0eac 972 973 #define REG_TX_POWER_BEFORE_IQK_B 0x0eb4 974 #define REG_TX_POWER_AFTER_IQK_B 0x0ebc 975 976 #define REG_RX_POWER_BEFORE_IQK_B 0x0ec0 977 #define REG_RX_POWER_BEFORE_IQK_B_2 0x0ec4 978 #define REG_RX_POWER_AFTER_IQK_B 0x0ec8 979 #define REG_RX_POWER_AFTER_IQK_B_2 0x0ecc 980 981 #define REG_RX_OFDM 0x0ed0 982 #define REG_RX_WAIT_RIFS 0x0ed4 983 #define REG_RX_TO_RX 0x0ed8 984 #define REG_STANDBY 0x0edc 985 #define REG_SLEEP 0x0ee0 986 #define REG_PMPD_ANAEN 0x0eec 987 988 #define REG_FW_START_ADDRESS 0x1000 989 990 #define REG_USB_INFO 0xfe17 991 #define REG_USB_HIMR 0xfe38 992 #define USB_HIMR_TIMEOUT2 BIT(31) 993 #define USB_HIMR_TIMEOUT1 BIT(30) 994 #define USB_HIMR_PSTIMEOUT BIT(29) 995 #define USB_HIMR_GTINT4 BIT(28) 996 #define USB_HIMR_GTINT3 BIT(27) 997 #define USB_HIMR_TXBCNERR BIT(26) 998 #define USB_HIMR_TXBCNOK BIT(25) 999 #define USB_HIMR_TSF_BIT32_TOGGLE BIT(24) 1000 #define USB_HIMR_BCNDMAINT3 BIT(23) 1001 #define USB_HIMR_BCNDMAINT2 BIT(22) 1002 #define USB_HIMR_BCNDMAINT1 BIT(21) 1003 #define USB_HIMR_BCNDMAINT0 BIT(20) 1004 #define USB_HIMR_BCNDOK3 BIT(19) 1005 #define USB_HIMR_BCNDOK2 BIT(18) 1006 #define USB_HIMR_BCNDOK1 BIT(17) 1007 #define USB_HIMR_BCNDOK0 BIT(16) 1008 #define USB_HIMR_HSISR_IND BIT(15) 1009 #define USB_HIMR_BCNDMAINT_E BIT(14) 1010 /* RSVD BIT(13) */ 1011 #define USB_HIMR_CTW_END BIT(12) 1012 /* RSVD BIT(11) */ 1013 #define USB_HIMR_C2HCMD BIT(10) 1014 #define USB_HIMR_CPWM2 BIT(9) 1015 #define USB_HIMR_CPWM BIT(8) 1016 #define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK 1017 Interrupt */ 1018 #define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK 1019 Interrupt */ 1020 #define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */ 1021 #define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */ 1022 #define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */ 1023 #define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */ 1024 #define USB_HIMR_RDU BIT(1) /* Receive Descriptor 1025 Unavailable */ 1026 #define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */ 1027 1028 #define REG_USB_SPECIAL_OPTION 0xfe55 1029 #define REG_USB_DMA_AGG_TO 0xfe5b 1030 #define REG_USB_AGG_TO 0xfe5c 1031 #define REG_USB_AGG_TH 0xfe5d 1032 1033 #define REG_NORMAL_SIE_VID 0xfe60 /* 0xfe60 - 0xfe61 */ 1034 #define REG_NORMAL_SIE_PID 0xfe62 /* 0xfe62 - 0xfe63 */ 1035 #define REG_NORMAL_SIE_OPTIONAL 0xfe64 1036 #define REG_NORMAL_SIE_EP 0xfe65 /* 0xfe65 - 0xfe67 */ 1037 #define REG_NORMAL_SIE_EP_TX 0xfe66 1038 #define NORMAL_SIE_EP_TX_HIGH_MASK 0x000f 1039 #define NORMAL_SIE_EP_TX_NORMAL_MASK 0x00f0 1040 #define NORMAL_SIE_EP_TX_LOW_MASK 0x0f00 1041 1042 #define REG_NORMAL_SIE_PHY 0xfe68 /* 0xfe68 - 0xfe6b */ 1043 #define REG_NORMAL_SIE_OPTIONAL2 0xfe6c 1044 #define REG_NORMAL_SIE_GPS_EP 0xfe6d /* RTL8723 only */ 1045 #define REG_NORMAL_SIE_MAC_ADDR 0xfe70 /* 0xfe70 - 0xfe75 */ 1046 #define REG_NORMAL_SIE_STRING 0xfe80 /* 0xfe80 - 0xfedf */ 1047 1048 /* RF6052 registers */ 1049 #define RF6052_REG_AC 0x00 1050 #define RF6052_REG_IQADJ_G1 0x01 1051 #define RF6052_REG_IQADJ_G2 0x02 1052 #define RF6052_REG_BS_PA_APSET_G1_G4 0x03 1053 #define RF6052_REG_BS_PA_APSET_G5_G8 0x04 1054 #define RF6052_REG_POW_TRSW 0x05 1055 #define RF6052_REG_GAIN_RX 0x06 1056 #define RF6052_REG_GAIN_TX 0x07 1057 #define RF6052_REG_TXM_IDAC 0x08 1058 #define RF6052_REG_IPA_G 0x09 1059 #define RF6052_REG_TXBIAS_G 0x0a 1060 #define RF6052_REG_TXPA_AG 0x0b 1061 #define RF6052_REG_IPA_A 0x0c 1062 #define RF6052_REG_TXBIAS_A 0x0d 1063 #define RF6052_REG_BS_PA_APSET_G9_G11 0x0e 1064 #define RF6052_REG_BS_IQGEN 0x0f 1065 #define RF6052_REG_MODE1 0x10 1066 #define RF6052_REG_MODE2 0x11 1067 #define RF6052_REG_RX_AGC_HP 0x12 1068 #define RF6052_REG_TX_AGC 0x13 1069 #define RF6052_REG_BIAS 0x14 1070 #define RF6052_REG_IPA 0x15 1071 #define RF6052_REG_TXBIAS 0x16 1072 #define RF6052_REG_POW_ABILITY 0x17 1073 #define RF6052_REG_MODE_AG 0x18 /* RF channel and BW switch */ 1074 #define MODE_AG_CHANNEL_MASK 0x3ff 1075 #define MODE_AG_CHANNEL_20MHZ BIT(10) 1076 #define MODE_AG_BW_MASK (BIT(10) | BIT(11)) 1077 #define MODE_AG_BW_20MHZ_8723B (BIT(10) | BIT(11)) 1078 #define MODE_AG_BW_40MHZ_8723B BIT(10) 1079 #define MODE_AG_BW_80MHZ_8723B 0 1080 1081 #define RF6052_REG_TOP 0x19 1082 #define RF6052_REG_RX_G1 0x1a 1083 #define RF6052_REG_RX_G2 0x1b 1084 #define RF6052_REG_RX_BB2 0x1c 1085 #define RF6052_REG_RX_BB1 0x1d 1086 #define RF6052_REG_RCK1 0x1e 1087 #define RF6052_REG_RCK2 0x1f 1088 #define RF6052_REG_TX_G1 0x20 1089 #define RF6052_REG_TX_G2 0x21 1090 #define RF6052_REG_TX_G3 0x22 1091 #define RF6052_REG_TX_BB1 0x23 1092 #define RF6052_REG_T_METER 0x24 1093 #define RF6052_REG_SYN_G1 0x25 /* RF TX Power control */ 1094 #define RF6052_REG_SYN_G2 0x26 /* RF TX Power control */ 1095 #define RF6052_REG_SYN_G3 0x27 /* RF TX Power control */ 1096 #define RF6052_REG_SYN_G4 0x28 /* RF TX Power control */ 1097 #define RF6052_REG_SYN_G5 0x29 /* RF TX Power control */ 1098 #define RF6052_REG_SYN_G6 0x2a /* RF TX Power control */ 1099 #define RF6052_REG_SYN_G7 0x2b /* RF TX Power control */ 1100 #define RF6052_REG_SYN_G8 0x2c /* RF TX Power control */ 1101 1102 #define RF6052_REG_RCK_OS 0x30 /* RF TX PA control */ 1103 1104 #define RF6052_REG_TXPA_G1 0x31 /* RF TX PA control */ 1105 #define RF6052_REG_TXPA_G2 0x32 /* RF TX PA control */ 1106 #define RF6052_REG_TXPA_G3 0x33 /* RF TX PA control */ 1107 1108 /* 1109 * NextGen regs: 8723BU 1110 */ 1111 #define RF6052_REG_T_METER_8723B 0x42 1112 #define RF6052_REG_UNKNOWN_43 0x43 1113 #define RF6052_REG_UNKNOWN_55 0x55 1114 #define RF6052_REG_S0S1 0xb0 1115 #define RF6052_REG_UNKNOWN_DF 0xdf 1116 #define RF6052_REG_UNKNOWN_ED 0xed 1117 #define RF6052_REG_WE_LUT 0xef 1118