1 /* 2 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com> 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * Register definitions taken from original Realtek rtl8723au driver 14 */ 15 16 /* 0x0000 ~ 0x00FF System Configuration */ 17 #define REG_SYS_ISO_CTRL 0x0000 18 #define SYS_ISO_MD2PP BIT(0) 19 #define SYS_ISO_ANALOG_IPS BIT(5) 20 #define SYS_ISO_DIOR BIT(9) 21 #define SYS_ISO_PWC_EV25V BIT(14) 22 #define SYS_ISO_PWC_EV12V BIT(15) 23 24 #define REG_SYS_FUNC 0x0002 25 #define SYS_FUNC_BBRSTB BIT(0) 26 #define SYS_FUNC_BB_GLB_RSTN BIT(1) 27 #define SYS_FUNC_USBA BIT(2) 28 #define SYS_FUNC_UPLL BIT(3) 29 #define SYS_FUNC_USBD BIT(4) 30 #define SYS_FUNC_DIO_PCIE BIT(5) 31 #define SYS_FUNC_PCIEA BIT(6) 32 #define SYS_FUNC_PPLL BIT(7) 33 #define SYS_FUNC_PCIED BIT(8) 34 #define SYS_FUNC_DIOE BIT(9) 35 #define SYS_FUNC_CPU_ENABLE BIT(10) 36 #define SYS_FUNC_DCORE BIT(11) 37 #define SYS_FUNC_ELDR BIT(12) 38 #define SYS_FUNC_DIO_RF BIT(13) 39 #define SYS_FUNC_HWPDN BIT(14) 40 #define SYS_FUNC_MREGEN BIT(15) 41 42 #define REG_APS_FSMCO 0x0004 43 #define APS_FSMCO_PFM_ALDN BIT(1) 44 #define APS_FSMCO_PFM_WOWL BIT(3) 45 #define APS_FSMCO_ENABLE_POWERDOWN BIT(4) 46 #define APS_FSMCO_MAC_ENABLE BIT(8) 47 #define APS_FSMCO_MAC_OFF BIT(9) 48 #define APS_FSMCO_SW_LPS BIT(10) 49 #define APS_FSMCO_HW_SUSPEND BIT(11) 50 #define APS_FSMCO_PCIE BIT(12) 51 #define APS_FSMCO_HW_POWERDOWN BIT(15) 52 #define APS_FSMCO_WLON_RESET BIT(16) 53 54 #define REG_SYS_CLKR 0x0008 55 #define SYS_CLK_ANAD16V_ENABLE BIT(0) 56 #define SYS_CLK_ANA8M BIT(1) 57 #define SYS_CLK_MACSLP BIT(4) 58 #define SYS_CLK_LOADER_ENABLE BIT(5) 59 #define SYS_CLK_80M_SSC_DISABLE BIT(7) 60 #define SYS_CLK_80M_SSC_ENABLE_HO BIT(8) 61 #define SYS_CLK_PHY_SSC_RSTB BIT(9) 62 #define SYS_CLK_SEC_CLK_ENABLE BIT(10) 63 #define SYS_CLK_MAC_CLK_ENABLE BIT(11) 64 #define SYS_CLK_ENABLE BIT(12) 65 #define SYS_CLK_RING_CLK_ENABLE BIT(13) 66 67 #define REG_9346CR 0x000a 68 #define EEPROM_BOOT BIT(4) 69 #define EEPROM_ENABLE BIT(5) 70 71 #define REG_EE_VPD 0x000c 72 #define REG_AFE_MISC 0x0010 73 #define AFE_MISC_WL_XTAL_CTRL BIT(6) 74 75 #define REG_SPS0_CTRL 0x0011 76 #define REG_SPS_OCP_CFG 0x0018 77 #define REG_8192E_LDOV12_CTRL 0x0014 78 #define REG_RSV_CTRL 0x001c 79 80 #define REG_RF_CTRL 0x001f 81 #define RF_ENABLE BIT(0) 82 #define RF_RSTB BIT(1) 83 #define RF_SDMRSTB BIT(2) 84 85 #define REG_LDOA15_CTRL 0x0020 86 #define LDOA15_ENABLE BIT(0) 87 #define LDOA15_STANDBY BIT(1) 88 #define LDOA15_OBUF BIT(2) 89 #define LDOA15_REG_VOS BIT(3) 90 #define LDOA15_VOADJ_SHIFT 4 91 92 #define REG_LDOV12D_CTRL 0x0021 93 #define LDOV12D_ENABLE BIT(0) 94 #define LDOV12D_STANDBY BIT(1) 95 #define LDOV12D_VADJ_SHIFT 4 96 97 #define REG_LDOHCI12_CTRL 0x0022 98 99 #define REG_LPLDO_CTRL 0x0023 100 #define LPLDO_HSM BIT(2) 101 #define LPLDO_LSM_DIS BIT(3) 102 103 #define REG_AFE_XTAL_CTRL 0x0024 104 #define AFE_XTAL_ENABLE BIT(0) 105 #define AFE_XTAL_B_SELECT BIT(1) 106 #define AFE_XTAL_GATE_USB BIT(8) 107 #define AFE_XTAL_GATE_AFE BIT(11) 108 #define AFE_XTAL_RF_GATE BIT(14) 109 #define AFE_XTAL_GATE_DIG BIT(17) 110 #define AFE_XTAL_BT_GATE BIT(20) 111 112 /* 113 * 0x0028 is also known as REG_AFE_CTRL2 on 8723bu/8192eu 114 */ 115 #define REG_AFE_PLL_CTRL 0x0028 116 #define AFE_PLL_ENABLE BIT(0) 117 #define AFE_PLL_320_ENABLE BIT(1) 118 #define APE_PLL_FREF_SELECT BIT(2) 119 #define AFE_PLL_EDGE_SELECT BIT(3) 120 #define AFE_PLL_WDOGB BIT(4) 121 #define AFE_PLL_LPF_ENABLE BIT(5) 122 123 #define REG_MAC_PHY_CTRL 0x002c 124 125 #define REG_EFUSE_CTRL 0x0030 126 #define REG_EFUSE_TEST 0x0034 127 #define EFUSE_TRPT BIT(7) 128 /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ 129 #define EFUSE_CELL_SEL (BIT(8) | BIT(9)) 130 #define EFUSE_LDOE25_ENABLE BIT(31) 131 #define EFUSE_SELECT_MASK 0x0300 132 #define EFUSE_WIFI_SELECT 0x0000 133 #define EFUSE_BT0_SELECT 0x0100 134 #define EFUSE_BT1_SELECT 0x0200 135 #define EFUSE_BT2_SELECT 0x0300 136 137 #define EFUSE_ACCESS_ENABLE 0x69 /* RTL8723 only */ 138 #define EFUSE_ACCESS_DISABLE 0x00 /* RTL8723 only */ 139 140 #define REG_PWR_DATA 0x0038 141 #define PWR_DATA_EEPRPAD_RFE_CTRL_EN BIT(11) 142 143 #define REG_CAL_TIMER 0x003c 144 #define REG_ACLK_MON 0x003e 145 #define REG_GPIO_MUXCFG 0x0040 146 #define REG_GPIO_IO_SEL 0x0042 147 #define REG_MAC_PINMUX_CFG 0x0043 148 #define REG_GPIO_PIN_CTRL 0x0044 149 #define REG_GPIO_INTM 0x0048 150 #define GPIO_INTM_EDGE_TRIG_IRQ BIT(9) 151 152 #define REG_LEDCFG0 0x004c 153 #define LEDCFG0_DPDT_SELECT BIT(23) 154 #define REG_LEDCFG1 0x004d 155 #define REG_LEDCFG2 0x004e 156 #define LEDCFG2_DPDT_SELECT BIT(7) 157 #define REG_LEDCFG3 0x004f 158 #define REG_LEDCFG REG_LEDCFG2 159 #define REG_FSIMR 0x0050 160 #define REG_FSISR 0x0054 161 #define REG_HSIMR 0x0058 162 #define REG_HSISR 0x005c 163 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ 164 #define REG_GPIO_PIN_CTRL_2 0x0060 165 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ 166 #define REG_GPIO_IO_SEL_2 0x0062 167 #define GPIO_IO_SEL_2_GPIO09_INPUT BIT(1) 168 #define GPIO_IO_SEL_2_GPIO09_IRQ BIT(9) 169 170 /* RTL8723B */ 171 #define REG_PAD_CTRL1 0x0064 172 #define PAD_CTRL1_SW_DPDT_SEL_DATA BIT(0) 173 174 /* RTL8723 only WIFI/BT/GPS Multi-Function control source. */ 175 #define REG_MULTI_FUNC_CTRL 0x0068 176 177 #define MULTI_FN_WIFI_HW_PWRDOWN_EN BIT(0) /* Enable GPIO[9] as WiFi HW 178 powerdown source */ 179 #define MULTI_FN_WIFI_HW_PWRDOWN_SL BIT(1) /* WiFi HW powerdown polarity 180 control */ 181 #define MULTI_WIFI_FUNC_EN BIT(2) /* WiFi function enable */ 182 183 #define MULTI_WIFI_HW_ROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW 184 powerdown source */ 185 #define MULTI_BT_HW_PWRDOWN_EN BIT(16) /* Enable GPIO[11] as BT HW 186 powerdown source */ 187 #define MULTI_BT_HW_PWRDOWN_SL BIT(17) /* BT HW powerdown polarity 188 control */ 189 #define MULTI_BT_FUNC_EN BIT(18) /* BT function enable */ 190 #define MULTI_BT_HW_ROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS 191 RF HW powerdown source */ 192 #define MULTI_GPS_HW_PWRDOWN_EN BIT(20) /* Enable GPIO[10] as GPS HW 193 powerdown source */ 194 #define MULTI_GPS_HW_PWRDOWN_SL BIT(21) /* GPS HW powerdown polarity 195 control */ 196 #define MULTI_GPS_FUNC_EN BIT(22) /* GPS function enable */ 197 198 #define REG_AFE_CTRL4 0x0078 /* 8192eu/8723bu */ 199 #define REG_LDO_SW_CTRL 0x007c /* 8192eu */ 200 201 #define REG_MCU_FW_DL 0x0080 202 #define MCU_FW_DL_ENABLE BIT(0) 203 #define MCU_FW_DL_READY BIT(1) 204 #define MCU_FW_DL_CSUM_REPORT BIT(2) 205 #define MCU_MAC_INIT_READY BIT(3) 206 #define MCU_BB_INIT_READY BIT(4) 207 #define MCU_RF_INIT_READY BIT(5) 208 #define MCU_WINT_INIT_READY BIT(6) 209 #define MCU_FW_RAM_SEL BIT(7) /* 1: RAM, 0:ROM */ 210 #define MCU_CP_RESET BIT(23) 211 212 #define REG_HMBOX_EXT_0 0x0088 213 #define REG_HMBOX_EXT_1 0x008a 214 #define REG_HMBOX_EXT_2 0x008c 215 #define REG_HMBOX_EXT_3 0x008e 216 /* Interrupt registers for 8192e/8723bu/8812 */ 217 #define REG_HIMR0 0x00b0 218 #define REG_HISR0 0x00b4 219 #define REG_HIMR1 0x00b8 220 #define REG_HISR1 0x00bc 221 222 /* Host suspend counter on FPGA platform */ 223 #define REG_HOST_SUSP_CNT 0x00bc 224 /* Efuse access protection for RTL8723 */ 225 #define REG_EFUSE_ACCESS 0x00cf 226 #define REG_BIST_SCAN 0x00d0 227 #define REG_BIST_RPT 0x00d4 228 #define REG_BIST_ROM_RPT 0x00d8 229 #define REG_USB_SIE_INTF 0x00e0 230 #define REG_PCIE_MIO_INTF 0x00e4 231 #define REG_PCIE_MIO_INTD 0x00e8 232 #define REG_HPON_FSM 0x00ec 233 #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23)) 234 #define HPON_FSM_BONDING_1T2R BIT(22) 235 #define REG_SYS_CFG 0x00f0 236 #define SYS_CFG_XCLK_VLD BIT(0) 237 #define SYS_CFG_ACLK_VLD BIT(1) 238 #define SYS_CFG_UCLK_VLD BIT(2) 239 #define SYS_CFG_PCLK_VLD BIT(3) 240 #define SYS_CFG_PCIRSTB BIT(4) 241 #define SYS_CFG_V15_VLD BIT(5) 242 #define SYS_CFG_TRP_B15V_EN BIT(7) 243 #define SYS_CFG_SW_OFFLOAD_EN BIT(7) /* For chips with IOL support */ 244 #define SYS_CFG_SIC_IDLE BIT(8) 245 #define SYS_CFG_BD_MAC2 BIT(9) 246 #define SYS_CFG_BD_MAC1 BIT(10) 247 #define SYS_CFG_IC_MACPHY_MODE BIT(11) 248 #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15)) 249 #define SYS_CFG_BT_FUNC BIT(16) 250 #define SYS_CFG_VENDOR_ID BIT(19) 251 #define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19)) 252 #define SYS_CFG_VENDOR_ID_TSMC 0 253 #define SYS_CFG_VENDOR_ID_SMIC BIT(18) 254 #define SYS_CFG_VENDOR_ID_UMC BIT(19) 255 #define SYS_CFG_PAD_HWPD_IDN BIT(22) 256 #define SYS_CFG_TRP_VAUX_EN BIT(23) 257 #define SYS_CFG_TRP_BT_EN BIT(24) 258 #define SYS_CFG_SPS_LDO_SEL BIT(24) /* 8192eu */ 259 #define SYS_CFG_BD_PKG_SEL BIT(25) 260 #define SYS_CFG_BD_HCI_SEL BIT(26) 261 #define SYS_CFG_TYPE_ID BIT(27) 262 #define SYS_CFG_RTL_ID BIT(23) /* TestChip ID, 263 1:Test(RLE); 0:MP(RL) */ 264 #define SYS_CFG_SPS_SEL BIT(24) /* 1:LDO regulator mode; 265 0:Switching regulator mode*/ 266 #define SYS_CFG_CHIP_VERSION_MASK 0xf000 /* Bit 12 - 15 */ 267 #define SYS_CFG_CHIP_VERSION_SHIFT 12 268 269 #define REG_GPIO_OUTSTS 0x00f4 /* For RTL8723 only. */ 270 #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1)) 271 #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3)) 272 #define GPIO_HCI_SEL (BIT(4) | BIT(5)) 273 #define GPIO_PKG_SEL_HCI BIT(6) 274 #define GPIO_FEN_GPS BIT(7) 275 #define GPIO_FEN_BT BIT(8) 276 #define GPIO_FEN_WL BIT(9) 277 #define GPIO_FEN_PCI BIT(10) 278 #define GPIO_FEN_USB BIT(11) 279 #define GPIO_BTRF_HWPDN_N BIT(12) 280 #define GPIO_WLRF_HWPDN_N BIT(13) 281 #define GPIO_PDN_BT_N BIT(14) 282 #define GPIO_PDN_GPS_N BIT(15) 283 #define GPIO_BT_CTL_HWPDN BIT(16) 284 #define GPIO_GPS_CTL_HWPDN BIT(17) 285 #define GPIO_PPHY_SUSB BIT(20) 286 #define GPIO_UPHY_SUSB BIT(21) 287 #define GPIO_PCI_SUSEN BIT(22) 288 #define GPIO_USB_SUSEN BIT(23) 289 #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) 290 291 #define REG_SYS_CFG2 0x00fc /* 8192eu */ 292 293 /* 0x0100 ~ 0x01FF MACTOP General Configuration */ 294 #define REG_CR 0x0100 295 #define CR_HCI_TXDMA_ENABLE BIT(0) 296 #define CR_HCI_RXDMA_ENABLE BIT(1) 297 #define CR_TXDMA_ENABLE BIT(2) 298 #define CR_RXDMA_ENABLE BIT(3) 299 #define CR_PROTOCOL_ENABLE BIT(4) 300 #define CR_SCHEDULE_ENABLE BIT(5) 301 #define CR_MAC_TX_ENABLE BIT(6) 302 #define CR_MAC_RX_ENABLE BIT(7) 303 #define CR_SW_BEACON_ENABLE BIT(8) 304 #define CR_SECURITY_ENABLE BIT(9) 305 #define CR_CALTIMER_ENABLE BIT(10) 306 307 /* Media Status Register */ 308 #define REG_MSR 0x0102 309 #define MSR_LINKTYPE_MASK 0x3 310 #define MSR_LINKTYPE_NONE 0x0 311 #define MSR_LINKTYPE_ADHOC 0x1 312 #define MSR_LINKTYPE_STATION 0x2 313 #define MSR_LINKTYPE_AP 0x3 314 315 #define REG_PBP 0x0104 316 #define PBP_PAGE_SIZE_RX_SHIFT 0 317 #define PBP_PAGE_SIZE_TX_SHIFT 4 318 #define PBP_PAGE_SIZE_64 0x0 319 #define PBP_PAGE_SIZE_128 0x1 320 #define PBP_PAGE_SIZE_256 0x2 321 #define PBP_PAGE_SIZE_512 0x3 322 #define PBP_PAGE_SIZE_1024 0x4 323 324 #define REG_TRXDMA_CTRL 0x010c 325 #define TRXDMA_CTRL_RXDMA_AGG_EN BIT(2) 326 #define TRXDMA_CTRL_VOQ_SHIFT 4 327 #define TRXDMA_CTRL_VIQ_SHIFT 6 328 #define TRXDMA_CTRL_BEQ_SHIFT 8 329 #define TRXDMA_CTRL_BKQ_SHIFT 10 330 #define TRXDMA_CTRL_MGQ_SHIFT 12 331 #define TRXDMA_CTRL_HIQ_SHIFT 14 332 #define TRXDMA_QUEUE_LOW 1 333 #define TRXDMA_QUEUE_NORMAL 2 334 #define TRXDMA_QUEUE_HIGH 3 335 336 #define REG_TRXFF_BNDY 0x0114 337 #define REG_TRXFF_STATUS 0x0118 338 #define REG_RXFF_PTR 0x011c 339 #define REG_HIMR 0x0120 340 #define REG_HISR 0x0124 341 #define REG_HIMRE 0x0128 342 #define REG_HISRE 0x012c 343 #define REG_CPWM 0x012f 344 #define REG_FWIMR 0x0130 345 #define REG_FWISR 0x0134 346 #define REG_PKTBUF_DBG_CTRL 0x0140 347 #define REG_PKTBUF_DBG_DATA_L 0x0144 348 #define REG_PKTBUF_DBG_DATA_H 0x0148 349 350 #define REG_TC0_CTRL 0x0150 351 #define REG_TC1_CTRL 0x0154 352 #define REG_TC2_CTRL 0x0158 353 #define REG_TC3_CTRL 0x015c 354 #define REG_TC4_CTRL 0x0160 355 #define REG_TCUNIT_BASE 0x0164 356 #define REG_MBIST_START 0x0174 357 #define REG_MBIST_DONE 0x0178 358 #define REG_MBIST_FAIL 0x017c 359 #define REG_C2HEVT_MSG_NORMAL 0x01a0 360 /* 8192EU/8723BU/8812 */ 361 #define REG_C2HEVT_CMD_ID_8723B 0x01ae 362 #define REG_C2HEVT_CLEAR 0x01af 363 #define REG_C2HEVT_MSG_TEST 0x01b8 364 #define REG_MCUTST_1 0x01c0 365 #define REG_FMTHR 0x01c8 366 #define REG_HMTFR 0x01cc 367 #define REG_HMBOX_0 0x01d0 368 #define REG_HMBOX_1 0x01d4 369 #define REG_HMBOX_2 0x01d8 370 #define REG_HMBOX_3 0x01dc 371 372 #define REG_LLT_INIT 0x01e0 373 #define LLT_OP_INACTIVE 0x0 374 #define LLT_OP_WRITE (0x1 << 30) 375 #define LLT_OP_READ (0x2 << 30) 376 #define LLT_OP_MASK (0x3 << 30) 377 378 #define REG_BB_ACCEESS_CTRL 0x01e8 379 #define REG_BB_ACCESS_DATA 0x01ec 380 381 #define REG_HMBOX_EXT0_8723B 0x01f0 382 #define REG_HMBOX_EXT1_8723B 0x01f4 383 #define REG_HMBOX_EXT2_8723B 0x01f8 384 #define REG_HMBOX_EXT3_8723B 0x01fc 385 386 /* 0x0200 ~ 0x027F TXDMA Configuration */ 387 #define REG_RQPN 0x0200 388 #define RQPN_HI_PQ_SHIFT 0 389 #define RQPN_LO_PQ_SHIFT 8 390 #define RQPN_NORM_PQ_SHIFT 16 391 #define RQPN_LOAD BIT(31) 392 393 #define REG_FIFOPAGE 0x0204 394 #define REG_TDECTRL 0x0208 395 #define REG_TXDMA_OFFSET_CHK 0x020c 396 #define TXDMA_OFFSET_DROP_DATA_EN BIT(9) 397 #define REG_TXDMA_STATUS 0x0210 398 #define REG_RQPN_NPQ 0x0214 399 #define RQPN_NPQ_SHIFT 0 400 #define RQPN_EPQ_SHIFT 16 401 402 #define REG_AUTO_LLT 0x0224 403 #define AUTO_LLT_INIT_LLT BIT(16) 404 405 #define REG_DWBCN1_CTRL_8723B 0x0228 406 407 /* 0x0280 ~ 0x02FF RXDMA Configuration */ 408 #define REG_RXDMA_AGG_PG_TH 0x0280 409 #define RXDMA_USB_AGG_ENABLE BIT(31) 410 #define REG_RXPKT_NUM 0x0284 411 #define RXPKT_NUM_RXDMA_IDLE BIT(17) 412 #define RXPKT_NUM_RW_RELEASE_EN BIT(18) 413 #define REG_RXDMA_STATUS 0x0288 414 415 /* Presumably only found on newer chips such as 8723bu */ 416 #define REG_RX_DMA_CTRL_8723B 0x0286 417 #define REG_RXDMA_PRO_8723B 0x0290 418 419 #define REG_RF_BB_CMD_ADDR 0x02c0 420 #define REG_RF_BB_CMD_DATA 0x02c4 421 422 /* spec version 11 */ 423 /* 0x0400 ~ 0x047F Protocol Configuration */ 424 /* 8192c, 8192d */ 425 #define REG_VOQ_INFO 0x0400 426 #define REG_VIQ_INFO 0x0404 427 #define REG_BEQ_INFO 0x0408 428 #define REG_BKQ_INFO 0x040c 429 /* 8188e, 8723a, 8812a, 8821a, 8192e, 8723b */ 430 #define REG_Q0_INFO 0x400 431 #define REG_Q1_INFO 0x404 432 #define REG_Q2_INFO 0x408 433 #define REG_Q3_INFO 0x40c 434 435 #define REG_MGQ_INFO 0x0410 436 #define REG_HGQ_INFO 0x0414 437 #define REG_BCNQ_INFO 0x0418 438 439 #define REG_CPU_MGQ_INFORMATION 0x041c 440 #define REG_FWHW_TXQ_CTRL 0x0420 441 #define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7) 442 #define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12) 443 444 #define REG_HWSEQ_CTRL 0x0423 445 #define REG_TXPKTBUF_BCNQ_BDNY 0x0424 446 #define REG_TXPKTBUF_MGQ_BDNY 0x0425 447 #define REG_LIFETIME_EN 0x0426 448 #define REG_MULTI_BCNQ_OFFSET 0x0427 449 450 #define REG_SPEC_SIFS 0x0428 451 #define SPEC_SIFS_CCK_MASK 0x00ff 452 #define SPEC_SIFS_CCK_SHIFT 0 453 #define SPEC_SIFS_OFDM_MASK 0xff00 454 #define SPEC_SIFS_OFDM_SHIFT 8 455 456 #define REG_RETRY_LIMIT 0x042a 457 #define RETRY_LIMIT_LONG_SHIFT 0 458 #define RETRY_LIMIT_LONG_MASK 0x003f 459 #define RETRY_LIMIT_SHORT_SHIFT 8 460 #define RETRY_LIMIT_SHORT_MASK 0x3f00 461 462 #define REG_DARFRC 0x0430 463 #define REG_RARFRC 0x0438 464 #define REG_RESPONSE_RATE_SET 0x0440 465 #define RESPONSE_RATE_BITMAP_ALL 0xfffff 466 #define RESPONSE_RATE_RRSR_CCK_ONLY_1M 0xffff1 467 #define RSR_1M BIT(0) 468 #define RSR_2M BIT(1) 469 #define RSR_5_5M BIT(2) 470 #define RSR_11M BIT(3) 471 #define RSR_6M BIT(4) 472 #define RSR_9M BIT(5) 473 #define RSR_12M BIT(6) 474 #define RSR_18M BIT(7) 475 #define RSR_24M BIT(8) 476 #define RSR_36M BIT(9) 477 #define RSR_48M BIT(10) 478 #define RSR_54M BIT(11) 479 #define RSR_MCS0 BIT(12) 480 #define RSR_MCS1 BIT(13) 481 #define RSR_MCS2 BIT(14) 482 #define RSR_MCS3 BIT(15) 483 #define RSR_MCS4 BIT(16) 484 #define RSR_MCS5 BIT(17) 485 #define RSR_MCS6 BIT(18) 486 #define RSR_MCS7 BIT(19) 487 #define RSR_RSC_LOWER_SUB_CHANNEL BIT(21) /* 0x200000 */ 488 #define RSR_RSC_UPPER_SUB_CHANNEL BIT(22) /* 0x400000 */ 489 #define RSR_RSC_BANDWIDTH_40M (RSR_RSC_UPPER_SUB_CHANNEL | \ 490 RSR_RSC_LOWER_SUB_CHANNEL) 491 #define RSR_ACK_SHORT_PREAMBLE BIT(23) 492 493 #define REG_ARFR0 0x0444 494 #define REG_ARFR1 0x0448 495 #define REG_ARFR2 0x044c 496 #define REG_ARFR3 0x0450 497 #define REG_AMPDU_MAX_TIME_8723B 0x0456 498 #define REG_AGGLEN_LMT 0x0458 499 #define REG_AMPDU_MIN_SPACE 0x045c 500 #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045d 501 #define REG_FAST_EDCA_CTRL 0x0460 502 #define REG_RD_RESP_PKT_TH 0x0463 503 #define REG_INIRTS_RATE_SEL 0x0480 504 /* 8723bu */ 505 #define REG_DATA_SUBCHANNEL 0x0483 506 /* 8723au */ 507 #define REG_INIDATA_RATE_SEL 0x0484 508 /* MACID_SLEEP_1/3 for 8723b, 8192e, 8812a, 8821a */ 509 #define REG_MACID_SLEEP_3_8732B 0x0484 510 #define REG_MACID_SLEEP_1_8732B 0x0488 511 512 #define REG_POWER_STATUS 0x04a4 513 #define REG_POWER_STAGE1 0x04b4 514 #define REG_POWER_STAGE2 0x04b8 515 #define REG_AMPDU_BURST_MODE_8723B 0x04bc 516 #define REG_PKT_VO_VI_LIFE_TIME 0x04c0 517 #define REG_PKT_BE_BK_LIFE_TIME 0x04c2 518 #define REG_STBC_SETTING 0x04c4 519 #define REG_QUEUE_CTRL 0x04c6 520 #define REG_HT_SINGLE_AMPDU_8723B 0x04c7 521 #define REG_PROT_MODE_CTRL 0x04c8 522 #define REG_MAX_AGGR_NUM 0x04ca 523 #define REG_RTS_MAX_AGGR_NUM 0x04cb 524 #define REG_BAR_MODE_CTRL 0x04cc 525 #define REG_RA_TRY_RATE_AGG_LMT 0x04cf 526 /* MACID_DROP for 8723a */ 527 #define REG_MACID_DROP_8732A 0x04d0 528 /* EARLY_MODE_CONTROL 8188e */ 529 #define REG_EARLY_MODE_CONTROL_8188E 0x04d0 530 /* MACID_SLEEP_2 for 8723b, 8192e, 8812a, 8821a */ 531 #define REG_MACID_SLEEP_2_8732B 0x04d0 532 #define REG_MACID_SLEEP 0x04d4 533 #define REG_NQOS_SEQ 0x04dc 534 #define REG_QOS_SEQ 0x04de 535 #define REG_NEED_CPU_HANDLE 0x04e0 536 #define REG_PKT_LOSE_RPT 0x04e1 537 #define REG_PTCL_ERR_STATUS 0x04e2 538 #define REG_TX_REPORT_CTRL 0x04ec 539 #define TX_REPORT_CTRL_TIMER_ENABLE BIT(1) 540 541 #define REG_TX_REPORT_TIME 0x04f0 542 #define REG_DUMMY 0x04fc 543 544 /* 0x0500 ~ 0x05FF EDCA Configuration */ 545 #define REG_EDCA_VO_PARAM 0x0500 546 #define REG_EDCA_VI_PARAM 0x0504 547 #define REG_EDCA_BE_PARAM 0x0508 548 #define REG_EDCA_BK_PARAM 0x050c 549 #define EDCA_PARAM_ECW_MIN_SHIFT 8 550 #define EDCA_PARAM_ECW_MAX_SHIFT 12 551 #define EDCA_PARAM_TXOP_SHIFT 16 552 #define REG_BEACON_TCFG 0x0510 553 #define REG_PIFS 0x0512 554 #define REG_RDG_PIFS 0x0513 555 #define REG_SIFS_CCK 0x0514 556 #define REG_SIFS_OFDM 0x0516 557 #define REG_TSFTR_SYN_OFFSET 0x0518 558 #define REG_AGGR_BREAK_TIME 0x051a 559 #define REG_SLOT 0x051b 560 #define REG_TX_PTCL_CTRL 0x0520 561 #define REG_TXPAUSE 0x0522 562 #define REG_DIS_TXREQ_CLR 0x0523 563 #define REG_RD_CTRL 0x0524 564 #define REG_TBTT_PROHIBIT 0x0540 565 #define REG_RD_NAV_NXT 0x0544 566 #define REG_NAV_PROT_LEN 0x0546 567 568 #define REG_BEACON_CTRL 0x0550 569 #define REG_BEACON_CTRL_1 0x0551 570 #define BEACON_ATIM BIT(0) 571 #define BEACON_CTRL_MBSSID BIT(1) 572 #define BEACON_CTRL_TX_BEACON_RPT BIT(2) 573 #define BEACON_FUNCTION_ENABLE BIT(3) 574 #define BEACON_DISABLE_TSF_UPDATE BIT(4) 575 576 #define REG_MBID_NUM 0x0552 577 #define REG_DUAL_TSF_RST 0x0553 578 #define DUAL_TSF_RESET_TSF0 BIT(0) 579 #define DUAL_TSF_RESET_TSF1 BIT(1) 580 #define DUAL_TSF_RESET_P2P BIT(4) 581 #define DUAL_TSF_TX_OK BIT(5) 582 583 /* The same as REG_MBSSID_BCN_SPACE */ 584 #define REG_BCN_INTERVAL 0x0554 585 #define REG_MBSSID_BCN_SPACE 0x0554 586 587 #define REG_DRIVER_EARLY_INT 0x0558 588 #define DRIVER_EARLY_INT_TIME 5 589 590 #define REG_BEACON_DMA_TIME 0x0559 591 #define BEACON_DMA_ATIME_INT_TIME 2 592 593 #define REG_ATIMWND 0x055a 594 #define REG_USTIME_TSF_8723B 0x055c 595 #define REG_BCN_MAX_ERR 0x055d 596 #define REG_RXTSF_OFFSET_CCK 0x055e 597 #define REG_RXTSF_OFFSET_OFDM 0x055f 598 #define REG_TSFTR 0x0560 599 #define REG_TSFTR1 0x0568 600 #define REG_INIT_TSFTR 0x0564 601 #define REG_ATIMWND_1 0x0570 602 #define REG_PSTIMER 0x0580 603 #define REG_TIMER0 0x0584 604 #define REG_TIMER1 0x0588 605 #define REG_ACM_HW_CTRL 0x05c0 606 #define ACM_HW_CTRL_BK BIT(0) 607 #define ACM_HW_CTRL_BE BIT(1) 608 #define ACM_HW_CTRL_VI BIT(2) 609 #define ACM_HW_CTRL_VO BIT(3) 610 #define REG_ACM_RST_CTRL 0x05c1 611 #define REG_ACMAVG 0x05c2 612 #define REG_VO_ADMTIME 0x05c4 613 #define REG_VI_ADMTIME 0x05c6 614 #define REG_BE_ADMTIME 0x05c8 615 #define REG_EDCA_RANDOM_GEN 0x05cc 616 #define REG_SCH_TXCMD 0x05d0 617 618 /* define REG_FW_TSF_SYNC_CNT 0x04a0 */ 619 #define REG_FW_RESET_TSF_CNT_1 0x05fc 620 #define REG_FW_RESET_TSF_CNT_0 0x05fd 621 #define REG_FW_BCN_DIS_CNT 0x05fe 622 623 /* 0x0600 ~ 0x07FF WMAC Configuration */ 624 #define REG_APSD_CTRL 0x0600 625 #define APSD_CTRL_OFF BIT(6) 626 #define APSD_CTRL_OFF_STATUS BIT(7) 627 #define REG_BW_OPMODE 0x0603 628 #define BW_OPMODE_20MHZ BIT(2) 629 #define BW_OPMODE_5G BIT(1) 630 #define BW_OPMODE_11J BIT(0) 631 632 #define REG_TCR 0x0604 633 634 /* Receive Configuration Register */ 635 #define REG_RCR 0x0608 636 #define RCR_ACCEPT_AP BIT(0) /* Accept all unicast packet */ 637 #define RCR_ACCEPT_PHYS_MATCH BIT(1) /* Accept phys match packet */ 638 #define RCR_ACCEPT_MCAST BIT(2) 639 #define RCR_ACCEPT_BCAST BIT(3) 640 #define RCR_ACCEPT_ADDR3 BIT(4) /* Accept address 3 match 641 packet */ 642 #define RCR_ACCEPT_PM BIT(5) /* Accept power management 643 packet */ 644 #define RCR_CHECK_BSSID_MATCH BIT(6) /* Accept BSSID match packet */ 645 #define RCR_CHECK_BSSID_BEACON BIT(7) /* Accept BSSID match packet 646 (Rx beacon, probe rsp) */ 647 #define RCR_ACCEPT_CRC32 BIT(8) /* Accept CRC32 error packet */ 648 #define RCR_ACCEPT_ICV BIT(9) /* Accept ICV error packet */ 649 #define RCR_ACCEPT_DATA_FRAME BIT(11) /* Accept all data pkt or use 650 REG_RXFLTMAP2 */ 651 #define RCR_ACCEPT_CTRL_FRAME BIT(12) /* Accept all control pkt or use 652 REG_RXFLTMAP1 */ 653 #define RCR_ACCEPT_MGMT_FRAME BIT(13) /* Accept all mgmt pkt or use 654 REG_RXFLTMAP0 */ 655 #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */ 656 #define RCR_UC_DATA_PKT_INT_ENABLE BIT(16) /* Enable unicast data packet 657 interrupt */ 658 #define RCR_BM_DATA_PKT_INT_ENABLE BIT(17) /* Enable broadcast data packet 659 interrupt */ 660 #define RCR_TIM_PARSER_ENABLE BIT(18) /* Enable RX beacon TIM parser*/ 661 #define RCR_MFBEN BIT(22) 662 #define RCR_LSIG_ENABLE BIT(23) /* Enable LSIG TXOP Protection 663 function. Search KEYCAM for 664 each rx packet to check if 665 LSIGEN bit is set. */ 666 #define RCR_MULTI_BSSID_ENABLE BIT(24) /* Enable Multiple BssId */ 667 #define RCR_FORCE_ACK BIT(26) 668 #define RCR_ACCEPT_BA_SSN BIT(27) /* Accept BA SSN */ 669 #define RCR_APPEND_PHYSTAT BIT(28) 670 #define RCR_APPEND_ICV BIT(29) 671 #define RCR_APPEND_MIC BIT(30) 672 #define RCR_APPEND_FCS BIT(31) /* WMAC append FCS after */ 673 674 #define REG_RX_PKT_LIMIT 0x060c 675 #define REG_RX_DLK_TIME 0x060d 676 #define REG_RX_DRVINFO_SZ 0x060f 677 678 #define REG_MACID 0x0610 679 #define REG_BSSID 0x0618 680 #define REG_MAR 0x0620 681 #define REG_MBIDCAMCFG 0x0628 682 683 #define REG_USTIME_EDCA 0x0638 684 #define REG_MAC_SPEC_SIFS 0x063a 685 686 /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ 687 /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ 688 #define REG_R2T_SIFS 0x063c 689 /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ 690 #define REG_T2T_SIFS 0x063e 691 #define REG_ACKTO 0x0640 692 #define REG_CTS2TO 0x0641 693 #define REG_EIFS 0x0642 694 695 /* WMA, BA, CCX */ 696 #define REG_NAV_CTRL 0x0650 697 /* In units of 128us */ 698 #define REG_NAV_UPPER 0x0652 699 #define NAV_UPPER_UNIT 128 700 701 #define REG_BACAMCMD 0x0654 702 #define REG_BACAMCONTENT 0x0658 703 #define REG_LBDLY 0x0660 704 #define REG_FWDLY 0x0661 705 #define REG_RXERR_RPT 0x0664 706 #define REG_WMAC_TRXPTCL_CTL 0x0668 707 #define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8)) 708 #define WMAC_TRXPTCL_CTL_BW_20 0 709 #define WMAC_TRXPTCL_CTL_BW_40 BIT(7) 710 #define WMAC_TRXPTCL_CTL_BW_80 BIT(8) 711 712 /* Security */ 713 #define REG_CAM_CMD 0x0670 714 #define CAM_CMD_POLLING BIT(31) 715 #define CAM_CMD_WRITE BIT(16) 716 #define CAM_CMD_KEY_SHIFT 3 717 #define REG_CAM_WRITE 0x0674 718 #define CAM_WRITE_VALID BIT(15) 719 #define REG_CAM_READ 0x0678 720 #define REG_CAM_DEBUG 0x067c 721 #define REG_SECURITY_CFG 0x0680 722 #define SEC_CFG_TX_USE_DEFKEY BIT(0) 723 #define SEC_CFG_RX_USE_DEFKEY BIT(1) 724 #define SEC_CFG_TX_SEC_ENABLE BIT(2) 725 #define SEC_CFG_RX_SEC_ENABLE BIT(3) 726 #define SEC_CFG_SKBYA2 BIT(4) 727 #define SEC_CFG_NO_SKMC BIT(5) 728 #define SEC_CFG_TXBC_USE_DEFKEY BIT(6) 729 #define SEC_CFG_RXBC_USE_DEFKEY BIT(7) 730 731 /* Power */ 732 #define REG_WOW_CTRL 0x0690 733 #define REG_PSSTATUS 0x0691 734 #define REG_PS_RX_INFO 0x0692 735 #define REG_LPNAV_CTRL 0x0694 736 #define REG_WKFMCAM_CMD 0x0698 737 #define REG_WKFMCAM_RWD 0x069c 738 739 /* 740 * RX Filters: each bit corresponds to the numerical value of the subtype. 741 * If it is set the subtype frame type is passed. The filter is only used when 742 * the RCR_ACCEPT_DATA_FRAME, RCR_ACCEPT_CTRL_FRAME, RCR_ACCEPT_MGMT_FRAME bit 743 * in the RCR are low. 744 * 745 * Example: Beacon subtype is binary 1000 which is decimal 8 so we have to set 746 * bit 8 (0x100) in REG_RXFLTMAP0 to enable reception. 747 */ 748 #define REG_RXFLTMAP0 0x06a0 /* Management frames */ 749 #define REG_RXFLTMAP1 0x06a2 /* Control frames */ 750 #define REG_RXFLTMAP2 0x06a4 /* Data frames */ 751 752 #define REG_BCN_PSR_RPT 0x06a8 753 #define REG_CALB32K_CTRL 0x06ac 754 #define REG_PKT_MON_CTRL 0x06b4 755 #define REG_BT_COEX_TABLE1 0x06c0 756 #define REG_BT_COEX_TABLE2 0x06c4 757 #define REG_BT_COEX_TABLE3 0x06c8 758 #define REG_BT_COEX_TABLE4 0x06cc 759 #define REG_WMAC_RESP_TXINFO 0x06d8 760 761 #define REG_MACID1 0x0700 762 #define REG_BSSID1 0x0708 763 764 /* 765 * This seems to be 8723bu specific 766 */ 767 #define REG_BT_CONTROL_8723BU 0x0764 768 #define BT_CONTROL_BT_GRANT BIT(12) 769 770 #define REG_WLAN_ACT_CONTROL_8723B 0x076e 771 772 #define REG_FPGA0_RF_MODE 0x0800 773 #define FPGA_RF_MODE BIT(0) 774 #define FPGA_RF_MODE_JAPAN BIT(1) 775 #define FPGA_RF_MODE_CCK BIT(24) 776 #define FPGA_RF_MODE_OFDM BIT(25) 777 778 #define REG_FPGA0_TX_INFO 0x0804 779 #define REG_FPGA0_PSD_FUNC 0x0808 780 #define REG_FPGA0_TX_GAIN 0x080c 781 #define REG_FPGA0_RF_TIMING1 0x0810 782 #define REG_FPGA0_RF_TIMING2 0x0814 783 #define REG_FPGA0_POWER_SAVE 0x0818 784 #define FPGA0_PS_LOWER_CHANNEL BIT(26) 785 #define FPGA0_PS_UPPER_CHANNEL BIT(27) 786 787 #define REG_FPGA0_XA_HSSI_PARM1 0x0820 /* RF 3 wire register */ 788 #define FPGA0_HSSI_PARM1_PI BIT(8) 789 #define REG_FPGA0_XA_HSSI_PARM2 0x0824 790 #define REG_FPGA0_XB_HSSI_PARM1 0x0828 791 #define REG_FPGA0_XB_HSSI_PARM2 0x082c 792 #define FPGA0_HSSI_3WIRE_DATA_LEN 0x800 793 #define FPGA0_HSSI_3WIRE_ADDR_LEN 0x400 794 #define FPGA0_HSSI_PARM2_ADDR_SHIFT 23 795 #define FPGA0_HSSI_PARM2_ADDR_MASK 0x7f800000 /* 0xff << 23 */ 796 #define FPGA0_HSSI_PARM2_CCK_HIGH_PWR BIT(9) 797 #define FPGA0_HSSI_PARM2_EDGE_READ BIT(31) 798 799 #define REG_TX_AGC_B_RATE18_06 0x0830 800 #define REG_TX_AGC_B_RATE54_24 0x0834 801 #define REG_TX_AGC_B_CCK1_55_MCS32 0x0838 802 #define REG_TX_AGC_B_MCS03_MCS00 0x083c 803 804 #define REG_FPGA0_XA_LSSI_PARM 0x0840 805 #define REG_FPGA0_XB_LSSI_PARM 0x0844 806 #define FPGA0_LSSI_PARM_ADDR_SHIFT 20 807 #define FPGA0_LSSI_PARM_ADDR_MASK 0x0ff00000 808 #define FPGA0_LSSI_PARM_DATA_MASK 0x000fffff 809 810 #define REG_TX_AGC_B_MCS07_MCS04 0x0848 811 #define REG_TX_AGC_B_MCS11_MCS08 0x084c 812 813 #define REG_FPGA0_XCD_SWITCH_CTRL 0x085c 814 815 #define REG_FPGA0_XA_RF_INT_OE 0x0860 /* RF Channel switch */ 816 #define REG_FPGA0_XB_RF_INT_OE 0x0864 817 #define FPGA0_INT_OE_ANTENNA_AB_OPEN 0x000 818 #define FPGA0_INT_OE_ANTENNA_A BIT(8) 819 #define FPGA0_INT_OE_ANTENNA_B BIT(9) 820 #define FPGA0_INT_OE_ANTENNA_MASK (FPGA0_INT_OE_ANTENNA_A | \ 821 FPGA0_INT_OE_ANTENNA_B) 822 823 #define REG_TX_AGC_B_MCS15_MCS12 0x0868 824 #define REG_TX_AGC_B_CCK11_A_CCK2_11 0x086c 825 826 #define REG_FPGA0_XAB_RF_SW_CTRL 0x0870 827 #define REG_FPGA0_XA_RF_SW_CTRL 0x0870 /* 16 bit */ 828 #define REG_FPGA0_XB_RF_SW_CTRL 0x0872 /* 16 bit */ 829 #define REG_FPGA0_XCD_RF_SW_CTRL 0x0874 830 #define REG_FPGA0_XC_RF_SW_CTRL 0x0874 /* 16 bit */ 831 #define REG_FPGA0_XD_RF_SW_CTRL 0x0876 /* 16 bit */ 832 #define FPGA0_RF_3WIRE_DATA BIT(0) 833 #define FPGA0_RF_3WIRE_CLOC BIT(1) 834 #define FPGA0_RF_3WIRE_LOAD BIT(2) 835 #define FPGA0_RF_3WIRE_RW BIT(3) 836 #define FPGA0_RF_3WIRE_MASK 0xf 837 #define FPGA0_RF_RFENV BIT(4) 838 #define FPGA0_RF_TRSW BIT(5) /* Useless now */ 839 #define FPGA0_RF_TRSWB BIT(6) 840 #define FPGA0_RF_ANTSW BIT(8) 841 #define FPGA0_RF_ANTSWB BIT(9) 842 #define FPGA0_RF_PAPE BIT(10) 843 #define FPGA0_RF_PAPE5G BIT(11) 844 #define FPGA0_RF_BD_CTRL_SHIFT 16 845 846 #define REG_FPGA0_XAB_RF_PARM 0x0878 /* Antenna select path in ODM */ 847 #define REG_FPGA0_XA_RF_PARM 0x0878 /* 16 bit */ 848 #define REG_FPGA0_XB_RF_PARM 0x087a /* 16 bit */ 849 #define REG_FPGA0_XCD_RF_PARM 0x087c 850 #define REG_FPGA0_XC_RF_PARM 0x087c /* 16 bit */ 851 #define REG_FPGA0_XD_RF_PARM 0x087e /* 16 bit */ 852 #define FPGA0_RF_PARM_RFA_ENABLE BIT(1) 853 #define FPGA0_RF_PARM_RFB_ENABLE BIT(17) 854 #define FPGA0_RF_PARM_CLK_GATE BIT(31) 855 856 #define REG_FPGA0_ANALOG1 0x0880 857 #define REG_FPGA0_ANALOG2 0x0884 858 #define FPGA0_ANALOG2_20MHZ BIT(10) 859 #define REG_FPGA0_ANALOG3 0x0888 860 #define REG_FPGA0_ANALOG4 0x088c 861 862 #define REG_NHM_TH9_TH10_8723B 0x0890 863 #define REG_NHM_TIMER_8723B 0x0894 864 #define REG_NHM_TH3_TO_TH0_8723B 0x0898 865 #define REG_NHM_TH7_TO_TH4_8723B 0x089c 866 867 #define REG_FPGA0_XA_LSSI_READBACK 0x08a0 /* Tranceiver LSSI Readback */ 868 #define REG_FPGA0_XB_LSSI_READBACK 0x08a4 869 #define REG_HSPI_XA_READBACK 0x08b8 /* Transceiver A HSPI read */ 870 #define REG_HSPI_XB_READBACK 0x08bc /* Transceiver B HSPI read */ 871 872 #define REG_FPGA1_RF_MODE 0x0900 873 874 #define REG_FPGA1_TX_INFO 0x090c 875 #define REG_DPDT_CTRL 0x092c /* 8723BU */ 876 #define REG_RFE_CTRL_ANTA_SRC 0x0930 /* 8723BU */ 877 #define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */ 878 #define REG_RFE_BUFFER 0x0944 /* 8723BU */ 879 #define REG_S0S1_PATH_SWITCH 0x0948 /* 8723BU */ 880 881 #define REG_CCK0_SYSTEM 0x0a00 882 #define CCK0_SIDEBAND BIT(4) 883 884 #define REG_CCK0_AFE_SETTING 0x0a04 885 886 #define REG_CONFIG_ANT_A 0x0b68 887 #define REG_CONFIG_ANT_B 0x0b6c 888 889 #define REG_OFDM0_TRX_PATH_ENABLE 0x0c04 890 #define OFDM_RF_PATH_RX_MASK 0x0f 891 #define OFDM_RF_PATH_RX_A BIT(0) 892 #define OFDM_RF_PATH_RX_B BIT(1) 893 #define OFDM_RF_PATH_RX_C BIT(2) 894 #define OFDM_RF_PATH_RX_D BIT(3) 895 #define OFDM_RF_PATH_TX_MASK 0xf0 896 #define OFDM_RF_PATH_TX_A BIT(4) 897 #define OFDM_RF_PATH_TX_B BIT(5) 898 #define OFDM_RF_PATH_TX_C BIT(6) 899 #define OFDM_RF_PATH_TX_D BIT(7) 900 901 #define REG_OFDM0_TR_MUX_PAR 0x0c08 902 903 #define REG_OFDM0_FA_RSTC 0x0c0c 904 905 #define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14 906 #define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c 907 908 #define REG_OFDM0_ENERGY_CCA_THRES 0x0c4c 909 910 #define REG_OFDM0_RX_D_SYNC_PATH 0x0c40 911 #define OFDM0_SYNC_PATH_NOTCH_FILTER BIT(1) 912 913 #define REG_OFDM0_XA_AGC_CORE1 0x0c50 914 #define REG_OFDM0_XA_AGC_CORE2 0x0c54 915 #define REG_OFDM0_XB_AGC_CORE1 0x0c58 916 #define REG_OFDM0_XB_AGC_CORE2 0x0c5c 917 #define REG_OFDM0_XC_AGC_CORE1 0x0c60 918 #define REG_OFDM0_XC_AGC_CORE2 0x0c64 919 #define REG_OFDM0_XD_AGC_CORE1 0x0c68 920 #define REG_OFDM0_XD_AGC_CORE2 0x0c6c 921 #define OFDM0_X_AGC_CORE1_IGI_MASK 0x0000007F 922 923 #define REG_OFDM0_AGC_PARM1 0x0c70 924 925 #define REG_OFDM0_AGCR_SSI_TABLE 0x0c78 926 927 #define REG_OFDM0_XA_TX_IQ_IMBALANCE 0x0c80 928 #define REG_OFDM0_XB_TX_IQ_IMBALANCE 0x0c88 929 #define REG_OFDM0_XC_TX_IQ_IMBALANCE 0x0c90 930 #define REG_OFDM0_XD_TX_IQ_IMBALANCE 0x0c98 931 932 #define REG_OFDM0_XC_TX_AFE 0x0c94 933 #define REG_OFDM0_XD_TX_AFE 0x0c9c 934 935 #define REG_OFDM0_RX_IQ_EXT_ANTA 0x0ca0 936 937 /* 8723bu */ 938 #define REG_OFDM0_TX_PSDO_NOISE_WEIGHT 0x0ce4 939 940 #define REG_OFDM1_LSTF 0x0d00 941 #define OFDM_LSTF_PRIME_CH_LOW BIT(10) 942 #define OFDM_LSTF_PRIME_CH_HIGH BIT(11) 943 #define OFDM_LSTF_PRIME_CH_MASK (OFDM_LSTF_PRIME_CH_LOW | \ 944 OFDM_LSTF_PRIME_CH_HIGH) 945 #define OFDM_LSTF_CONTINUE_TX BIT(28) 946 #define OFDM_LSTF_SINGLE_CARRIER BIT(29) 947 #define OFDM_LSTF_SINGLE_TONE BIT(30) 948 #define OFDM_LSTF_MASK 0x70000000 949 950 #define REG_OFDM1_TRX_PATH_ENABLE 0x0d04 951 952 #define REG_TX_AGC_A_RATE18_06 0x0e00 953 #define REG_TX_AGC_A_RATE54_24 0x0e04 954 #define REG_TX_AGC_A_CCK1_MCS32 0x0e08 955 #define REG_TX_AGC_A_MCS03_MCS00 0x0e10 956 #define REG_TX_AGC_A_MCS07_MCS04 0x0e14 957 #define REG_TX_AGC_A_MCS11_MCS08 0x0e18 958 #define REG_TX_AGC_A_MCS15_MCS12 0x0e1c 959 960 #define REG_FPGA0_IQK 0x0e28 961 962 #define REG_TX_IQK_TONE_A 0x0e30 963 #define REG_RX_IQK_TONE_A 0x0e34 964 #define REG_TX_IQK_PI_A 0x0e38 965 #define REG_RX_IQK_PI_A 0x0e3c 966 967 #define REG_TX_IQK 0x0e40 968 #define REG_RX_IQK 0x0e44 969 #define REG_IQK_AGC_PTS 0x0e48 970 #define REG_IQK_AGC_RSP 0x0e4c 971 #define REG_TX_IQK_TONE_B 0x0e50 972 #define REG_RX_IQK_TONE_B 0x0e54 973 #define REG_TX_IQK_PI_B 0x0e58 974 #define REG_RX_IQK_PI_B 0x0e5c 975 #define REG_IQK_AGC_CONT 0x0e60 976 977 #define REG_BLUETOOTH 0x0e6c 978 #define REG_RX_WAIT_CCA 0x0e70 979 #define REG_TX_CCK_RFON 0x0e74 980 #define REG_TX_CCK_BBON 0x0e78 981 #define REG_TX_OFDM_RFON 0x0e7c 982 #define REG_TX_OFDM_BBON 0x0e80 983 #define REG_TX_TO_RX 0x0e84 984 #define REG_TX_TO_TX 0x0e88 985 #define REG_RX_CCK 0x0e8c 986 987 #define REG_TX_POWER_BEFORE_IQK_A 0x0e94 988 #define REG_TX_POWER_AFTER_IQK_A 0x0e9c 989 990 #define REG_RX_POWER_BEFORE_IQK_A 0x0ea0 991 #define REG_RX_POWER_BEFORE_IQK_A_2 0x0ea4 992 #define REG_RX_POWER_AFTER_IQK_A 0x0ea8 993 #define REG_RX_POWER_AFTER_IQK_A_2 0x0eac 994 995 #define REG_TX_POWER_BEFORE_IQK_B 0x0eb4 996 #define REG_TX_POWER_AFTER_IQK_B 0x0ebc 997 998 #define REG_RX_POWER_BEFORE_IQK_B 0x0ec0 999 #define REG_RX_POWER_BEFORE_IQK_B_2 0x0ec4 1000 #define REG_RX_POWER_AFTER_IQK_B 0x0ec8 1001 #define REG_RX_POWER_AFTER_IQK_B_2 0x0ecc 1002 1003 #define REG_RX_OFDM 0x0ed0 1004 #define REG_RX_WAIT_RIFS 0x0ed4 1005 #define REG_RX_TO_RX 0x0ed8 1006 #define REG_STANDBY 0x0edc 1007 #define REG_SLEEP 0x0ee0 1008 #define REG_PMPD_ANAEN 0x0eec 1009 1010 #define REG_FW_START_ADDRESS 0x1000 1011 1012 #define REG_USB_INFO 0xfe17 1013 #define REG_USB_HIMR 0xfe38 1014 #define USB_HIMR_TIMEOUT2 BIT(31) 1015 #define USB_HIMR_TIMEOUT1 BIT(30) 1016 #define USB_HIMR_PSTIMEOUT BIT(29) 1017 #define USB_HIMR_GTINT4 BIT(28) 1018 #define USB_HIMR_GTINT3 BIT(27) 1019 #define USB_HIMR_TXBCNERR BIT(26) 1020 #define USB_HIMR_TXBCNOK BIT(25) 1021 #define USB_HIMR_TSF_BIT32_TOGGLE BIT(24) 1022 #define USB_HIMR_BCNDMAINT3 BIT(23) 1023 #define USB_HIMR_BCNDMAINT2 BIT(22) 1024 #define USB_HIMR_BCNDMAINT1 BIT(21) 1025 #define USB_HIMR_BCNDMAINT0 BIT(20) 1026 #define USB_HIMR_BCNDOK3 BIT(19) 1027 #define USB_HIMR_BCNDOK2 BIT(18) 1028 #define USB_HIMR_BCNDOK1 BIT(17) 1029 #define USB_HIMR_BCNDOK0 BIT(16) 1030 #define USB_HIMR_HSISR_IND BIT(15) 1031 #define USB_HIMR_BCNDMAINT_E BIT(14) 1032 /* RSVD BIT(13) */ 1033 #define USB_HIMR_CTW_END BIT(12) 1034 /* RSVD BIT(11) */ 1035 #define USB_HIMR_C2HCMD BIT(10) 1036 #define USB_HIMR_CPWM2 BIT(9) 1037 #define USB_HIMR_CPWM BIT(8) 1038 #define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK 1039 Interrupt */ 1040 #define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK 1041 Interrupt */ 1042 #define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */ 1043 #define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */ 1044 #define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */ 1045 #define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */ 1046 #define USB_HIMR_RDU BIT(1) /* Receive Descriptor 1047 Unavailable */ 1048 #define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */ 1049 1050 #define REG_USB_SPECIAL_OPTION 0xfe55 1051 #define REG_USB_HRPWM 0xfe58 1052 #define REG_USB_DMA_AGG_TO 0xfe5b 1053 #define REG_USB_AGG_TO 0xfe5c 1054 #define REG_USB_AGG_TH 0xfe5d 1055 1056 #define REG_NORMAL_SIE_VID 0xfe60 /* 0xfe60 - 0xfe61 */ 1057 #define REG_NORMAL_SIE_PID 0xfe62 /* 0xfe62 - 0xfe63 */ 1058 #define REG_NORMAL_SIE_OPTIONAL 0xfe64 1059 #define REG_NORMAL_SIE_EP 0xfe65 /* 0xfe65 - 0xfe67 */ 1060 #define REG_NORMAL_SIE_EP_TX 0xfe66 1061 #define NORMAL_SIE_EP_TX_HIGH_MASK 0x000f 1062 #define NORMAL_SIE_EP_TX_NORMAL_MASK 0x00f0 1063 #define NORMAL_SIE_EP_TX_LOW_MASK 0x0f00 1064 1065 #define REG_NORMAL_SIE_PHY 0xfe68 /* 0xfe68 - 0xfe6b */ 1066 #define REG_NORMAL_SIE_OPTIONAL2 0xfe6c 1067 #define REG_NORMAL_SIE_GPS_EP 0xfe6d /* RTL8723 only */ 1068 #define REG_NORMAL_SIE_MAC_ADDR 0xfe70 /* 0xfe70 - 0xfe75 */ 1069 #define REG_NORMAL_SIE_STRING 0xfe80 /* 0xfe80 - 0xfedf */ 1070 1071 /* RF6052 registers */ 1072 #define RF6052_REG_AC 0x00 1073 #define RF6052_REG_IQADJ_G1 0x01 1074 #define RF6052_REG_IQADJ_G2 0x02 1075 #define RF6052_REG_BS_PA_APSET_G1_G4 0x03 1076 #define RF6052_REG_BS_PA_APSET_G5_G8 0x04 1077 #define RF6052_REG_POW_TRSW 0x05 1078 #define RF6052_REG_GAIN_RX 0x06 1079 #define RF6052_REG_GAIN_TX 0x07 1080 #define RF6052_REG_TXM_IDAC 0x08 1081 #define RF6052_REG_IPA_G 0x09 1082 #define RF6052_REG_TXBIAS_G 0x0a 1083 #define RF6052_REG_TXPA_AG 0x0b 1084 #define RF6052_REG_IPA_A 0x0c 1085 #define RF6052_REG_TXBIAS_A 0x0d 1086 #define RF6052_REG_BS_PA_APSET_G9_G11 0x0e 1087 #define RF6052_REG_BS_IQGEN 0x0f 1088 #define RF6052_REG_MODE1 0x10 1089 #define RF6052_REG_MODE2 0x11 1090 #define RF6052_REG_RX_AGC_HP 0x12 1091 #define RF6052_REG_TX_AGC 0x13 1092 #define RF6052_REG_BIAS 0x14 1093 #define RF6052_REG_IPA 0x15 1094 #define RF6052_REG_TXBIAS 0x16 1095 #define RF6052_REG_POW_ABILITY 0x17 1096 #define RF6052_REG_MODE_AG 0x18 /* RF channel and BW switch */ 1097 #define MODE_AG_CHANNEL_MASK 0x3ff 1098 #define MODE_AG_CHANNEL_20MHZ BIT(10) 1099 #define MODE_AG_BW_MASK (BIT(10) | BIT(11)) 1100 #define MODE_AG_BW_20MHZ_8723B (BIT(10) | BIT(11)) 1101 #define MODE_AG_BW_40MHZ_8723B BIT(10) 1102 #define MODE_AG_BW_80MHZ_8723B 0 1103 1104 #define RF6052_REG_TOP 0x19 1105 #define RF6052_REG_RX_G1 0x1a 1106 #define RF6052_REG_RX_G2 0x1b 1107 #define RF6052_REG_RX_BB2 0x1c 1108 #define RF6052_REG_RX_BB1 0x1d 1109 #define RF6052_REG_RCK1 0x1e 1110 #define RF6052_REG_RCK2 0x1f 1111 #define RF6052_REG_TX_G1 0x20 1112 #define RF6052_REG_TX_G2 0x21 1113 #define RF6052_REG_TX_G3 0x22 1114 #define RF6052_REG_TX_BB1 0x23 1115 #define RF6052_REG_T_METER 0x24 1116 #define RF6052_REG_SYN_G1 0x25 /* RF TX Power control */ 1117 #define RF6052_REG_SYN_G2 0x26 /* RF TX Power control */ 1118 #define RF6052_REG_SYN_G3 0x27 /* RF TX Power control */ 1119 #define RF6052_REG_SYN_G4 0x28 /* RF TX Power control */ 1120 #define RF6052_REG_SYN_G5 0x29 /* RF TX Power control */ 1121 #define RF6052_REG_SYN_G6 0x2a /* RF TX Power control */ 1122 #define RF6052_REG_SYN_G7 0x2b /* RF TX Power control */ 1123 #define RF6052_REG_SYN_G8 0x2c /* RF TX Power control */ 1124 1125 #define RF6052_REG_RCK_OS 0x30 /* RF TX PA control */ 1126 1127 #define RF6052_REG_TXPA_G1 0x31 /* RF TX PA control */ 1128 #define RF6052_REG_TXPA_G2 0x32 /* RF TX PA control */ 1129 #define RF6052_REG_TXPA_G3 0x33 /* RF TX PA control */ 1130 1131 /* 1132 * NextGen regs: 8723BU 1133 */ 1134 #define RF6052_REG_T_METER_8723B 0x42 1135 #define RF6052_REG_UNKNOWN_43 0x43 1136 #define RF6052_REG_UNKNOWN_55 0x55 1137 #define RF6052_REG_UNKNOWN_56 0x56 1138 #define RF6052_REG_S0S1 0xb0 1139 #define RF6052_REG_UNKNOWN_DF 0xdf 1140 #define RF6052_REG_UNKNOWN_ED 0xed 1141 #define RF6052_REG_WE_LUT 0xef 1142