1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * RTL8XXXU mac80211 USB driver - 8723b specific subdriver 4 * 5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 6 * 7 * Portions, notably calibration code: 8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 9 * 10 * This driver was written as a replacement for the vendor provided 11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in 12 * their programming interface, I have started adding support for 13 * additional 8xxx chips like the 8192cu, 8188cus, etc. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/kernel.h> 18 #include <linux/sched.h> 19 #include <linux/errno.h> 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/spinlock.h> 23 #include <linux/list.h> 24 #include <linux/usb.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/ethtool.h> 28 #include <linux/wireless.h> 29 #include <linux/firmware.h> 30 #include <linux/moduleparam.h> 31 #include <net/mac80211.h> 32 #include "rtl8xxxu.h" 33 #include "rtl8xxxu_regs.h" 34 35 static const struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = { 36 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0}, 37 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10}, 38 {0x430, 0x00}, {0x431, 0x00}, 39 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, 40 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05}, 41 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01}, 42 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00}, 43 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f}, 44 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00}, 45 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f}, 46 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66}, 47 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, 48 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, 49 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, 50 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, 51 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, 52 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, 53 {0x516, 0x0a}, {0x525, 0x4f}, 54 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, 55 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, 56 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, 57 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, 58 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, 59 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, 60 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, 61 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, 62 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04}, 63 {0xffff, 0xff}, 64 }; 65 66 static const struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = { 67 {0x800, 0x80040000}, {0x804, 0x00000003}, 68 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 69 {0x810, 0x10001331}, {0x814, 0x020c3d10}, 70 {0x818, 0x02200385}, {0x81c, 0x00000000}, 71 {0x820, 0x01000100}, {0x824, 0x00190204}, 72 {0x828, 0x00000000}, {0x82c, 0x00000000}, 73 {0x830, 0x00000000}, {0x834, 0x00000000}, 74 {0x838, 0x00000000}, {0x83c, 0x00000000}, 75 {0x840, 0x00010000}, {0x844, 0x00000000}, 76 {0x848, 0x00000000}, {0x84c, 0x00000000}, 77 {0x850, 0x00000000}, {0x854, 0x00000000}, 78 {0x858, 0x569a11a9}, {0x85c, 0x01000014}, 79 {0x860, 0x66f60110}, {0x864, 0x061f0649}, 80 {0x868, 0x00000000}, {0x86c, 0x27272700}, 81 {0x870, 0x07000760}, {0x874, 0x25004000}, 82 {0x878, 0x00000808}, {0x87c, 0x00000000}, 83 {0x880, 0xb0000c1c}, {0x884, 0x00000001}, 84 {0x888, 0x00000000}, {0x88c, 0xccc000c0}, 85 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 86 {0x898, 0x40302010}, {0x89c, 0x00706050}, 87 {0x900, 0x00000000}, {0x904, 0x00000023}, 88 {0x908, 0x00000000}, {0x90c, 0x81121111}, 89 {0x910, 0x00000002}, {0x914, 0x00000201}, 90 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c}, 91 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f}, 92 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028}, 93 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 94 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 95 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 96 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 97 {0xa78, 0x00000900}, {0xa7c, 0x225b0606}, 98 {0xa80, 0x21806490}, {0xb2c, 0x00000000}, 99 {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, 100 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 101 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 102 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 103 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 104 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 105 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, 106 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 107 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 108 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 109 {0xc50, 0x69553420}, {0xc54, 0x43bc0094}, 110 {0xc58, 0x00013149}, {0xc5c, 0x00250492}, 111 {0xc60, 0x00000000}, {0xc64, 0x7112848b}, 112 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 113 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db}, 114 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, 115 {0xc80, 0x390000e4}, {0xc84, 0x20f60000}, 116 {0xc88, 0x40000100}, {0xc8c, 0x20200000}, 117 {0xc90, 0x00020e1a}, {0xc94, 0x00000000}, 118 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f}, 119 {0xca0, 0x00000000}, {0xca4, 0x000300a0}, 120 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 121 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 122 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 123 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 124 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 125 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 126 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 127 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 128 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 129 {0xd00, 0x00000740}, {0xd04, 0x40020401}, 130 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 131 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53}, 132 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975}, 133 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 134 {0xd38, 0x00000000}, {0xd3c, 0x00127353}, 135 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 136 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 137 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 138 {0xd58, 0x00000282}, {0xd5c, 0x30032064}, 139 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 140 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 141 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 142 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d}, 143 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d}, 144 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d}, 145 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d}, 146 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 147 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 148 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 149 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 150 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 151 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 152 {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, 153 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096}, 154 {0xe70, 0x00c00096}, {0xe74, 0x01000056}, 155 {0xe78, 0x01000014}, {0xe7c, 0x01000056}, 156 {0xe80, 0x01000014}, {0xe84, 0x00c00096}, 157 {0xe88, 0x01000056}, {0xe8c, 0x00c00096}, 158 {0xed0, 0x00c00096}, {0xed4, 0x00c00096}, 159 {0xed8, 0x00c00096}, {0xedc, 0x000000d6}, 160 {0xee0, 0x000000d6}, {0xeec, 0x01c00016}, 161 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 162 {0xf00, 0x00000300}, 163 {0x820, 0x01000100}, {0x800, 0x83040000}, 164 {0xffff, 0xffffffff}, 165 }; 166 167 static const struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = { 168 {0xc78, 0xfd000001}, {0xc78, 0xfc010001}, 169 {0xc78, 0xfb020001}, {0xc78, 0xfa030001}, 170 {0xc78, 0xf9040001}, {0xc78, 0xf8050001}, 171 {0xc78, 0xf7060001}, {0xc78, 0xf6070001}, 172 {0xc78, 0xf5080001}, {0xc78, 0xf4090001}, 173 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001}, 174 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001}, 175 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001}, 176 {0xc78, 0xed100001}, {0xc78, 0xec110001}, 177 {0xc78, 0xeb120001}, {0xc78, 0xea130001}, 178 {0xc78, 0xe9140001}, {0xc78, 0xe8150001}, 179 {0xc78, 0xe7160001}, {0xc78, 0xe6170001}, 180 {0xc78, 0xe5180001}, {0xc78, 0xe4190001}, 181 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001}, 182 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001}, 183 {0xc78, 0x671e0001}, {0xc78, 0x661f0001}, 184 {0xc78, 0x65200001}, {0xc78, 0x64210001}, 185 {0xc78, 0x63220001}, {0xc78, 0x4a230001}, 186 {0xc78, 0x49240001}, {0xc78, 0x48250001}, 187 {0xc78, 0x47260001}, {0xc78, 0x46270001}, 188 {0xc78, 0x45280001}, {0xc78, 0x44290001}, 189 {0xc78, 0x432a0001}, {0xc78, 0x422b0001}, 190 {0xc78, 0x292c0001}, {0xc78, 0x282d0001}, 191 {0xc78, 0x272e0001}, {0xc78, 0x262f0001}, 192 {0xc78, 0x0a300001}, {0xc78, 0x09310001}, 193 {0xc78, 0x08320001}, {0xc78, 0x07330001}, 194 {0xc78, 0x06340001}, {0xc78, 0x05350001}, 195 {0xc78, 0x04360001}, {0xc78, 0x03370001}, 196 {0xc78, 0x02380001}, {0xc78, 0x01390001}, 197 {0xc78, 0x013a0001}, {0xc78, 0x013b0001}, 198 {0xc78, 0x013c0001}, {0xc78, 0x013d0001}, 199 {0xc78, 0x013e0001}, {0xc78, 0x013f0001}, 200 {0xc78, 0xfc400001}, {0xc78, 0xfb410001}, 201 {0xc78, 0xfa420001}, {0xc78, 0xf9430001}, 202 {0xc78, 0xf8440001}, {0xc78, 0xf7450001}, 203 {0xc78, 0xf6460001}, {0xc78, 0xf5470001}, 204 {0xc78, 0xf4480001}, {0xc78, 0xf3490001}, 205 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001}, 206 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001}, 207 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001}, 208 {0xc78, 0xec500001}, {0xc78, 0xeb510001}, 209 {0xc78, 0xea520001}, {0xc78, 0xe9530001}, 210 {0xc78, 0xe8540001}, {0xc78, 0xe7550001}, 211 {0xc78, 0xe6560001}, {0xc78, 0xe5570001}, 212 {0xc78, 0xe4580001}, {0xc78, 0xe3590001}, 213 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001}, 214 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001}, 215 {0xc78, 0x675e0001}, {0xc78, 0x665f0001}, 216 {0xc78, 0x65600001}, {0xc78, 0x64610001}, 217 {0xc78, 0x63620001}, {0xc78, 0x62630001}, 218 {0xc78, 0x61640001}, {0xc78, 0x48650001}, 219 {0xc78, 0x47660001}, {0xc78, 0x46670001}, 220 {0xc78, 0x45680001}, {0xc78, 0x44690001}, 221 {0xc78, 0x436a0001}, {0xc78, 0x426b0001}, 222 {0xc78, 0x286c0001}, {0xc78, 0x276d0001}, 223 {0xc78, 0x266e0001}, {0xc78, 0x256f0001}, 224 {0xc78, 0x24700001}, {0xc78, 0x09710001}, 225 {0xc78, 0x08720001}, {0xc78, 0x07730001}, 226 {0xc78, 0x06740001}, {0xc78, 0x05750001}, 227 {0xc78, 0x04760001}, {0xc78, 0x03770001}, 228 {0xc78, 0x02780001}, {0xc78, 0x01790001}, 229 {0xc78, 0x017a0001}, {0xc78, 0x017b0001}, 230 {0xc78, 0x017c0001}, {0xc78, 0x017d0001}, 231 {0xc78, 0x017e0001}, {0xc78, 0x017f0001}, 232 {0xc50, 0x69553422}, 233 {0xc50, 0x69553420}, 234 {0x824, 0x00390204}, 235 {0xffff, 0xffffffff} 236 }; 237 238 static const struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = { 239 {0x00, 0x00010000}, {0xb0, 0x000dffe0}, 240 {0xfe, 0x00000000}, {0xfe, 0x00000000}, 241 {0xfe, 0x00000000}, {0xb1, 0x00000018}, 242 {0xfe, 0x00000000}, {0xfe, 0x00000000}, 243 {0xfe, 0x00000000}, {0xb2, 0x00084c00}, 244 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa}, 245 {0xb7, 0x00000010}, {0xb8, 0x0000907f}, 246 {0x5c, 0x00000002}, {0x7c, 0x00000002}, 247 {0x7e, 0x00000005}, {0x8b, 0x0006fc00}, 248 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2}, 249 {0x1e, 0x00000000}, {0xdf, 0x00000780}, 250 {0x50, 0x00067435}, 251 /* 252 * The 8723bu vendor driver indicates that bit 8 should be set in 253 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However 254 * they never actually check the package type - and just default 255 * to not setting it. 256 */ 257 {0x51, 0x0006b04e}, 258 {0x52, 0x000007d2}, {0x53, 0x00000000}, 259 {0x54, 0x00050400}, {0x55, 0x0004026e}, 260 {0xdd, 0x0000004c}, {0x70, 0x00067435}, 261 /* 262 * 0x71 has same package type condition as for register 0x51 263 */ 264 {0x71, 0x0006b04e}, 265 {0x72, 0x000007d2}, {0x73, 0x00000000}, 266 {0x74, 0x00050400}, {0x75, 0x0004026e}, 267 {0xef, 0x00000100}, {0x34, 0x0000add7}, 268 {0x35, 0x00005c00}, {0x34, 0x00009dd4}, 269 {0x35, 0x00005000}, {0x34, 0x00008dd1}, 270 {0x35, 0x00004400}, {0x34, 0x00007dce}, 271 {0x35, 0x00003800}, {0x34, 0x00006cd1}, 272 {0x35, 0x00004400}, {0x34, 0x00005cce}, 273 {0x35, 0x00003800}, {0x34, 0x000048ce}, 274 {0x35, 0x00004400}, {0x34, 0x000034ce}, 275 {0x35, 0x00003800}, {0x34, 0x00002451}, 276 {0x35, 0x00004400}, {0x34, 0x0000144e}, 277 {0x35, 0x00003800}, {0x34, 0x00000051}, 278 {0x35, 0x00004400}, {0xef, 0x00000000}, 279 {0xef, 0x00000100}, {0xed, 0x00000010}, 280 {0x44, 0x0000add7}, {0x44, 0x00009dd4}, 281 {0x44, 0x00008dd1}, {0x44, 0x00007dce}, 282 {0x44, 0x00006cc1}, {0x44, 0x00005cce}, 283 {0x44, 0x000044d1}, {0x44, 0x000034ce}, 284 {0x44, 0x00002451}, {0x44, 0x0000144e}, 285 {0x44, 0x00000051}, {0xef, 0x00000000}, 286 {0xed, 0x00000000}, {0x7f, 0x00020080}, 287 {0xef, 0x00002000}, {0x3b, 0x000380ef}, 288 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6}, 289 {0x3b, 0x000200bc}, {0x3b, 0x000188a5}, 290 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71}, 291 {0x3b, 0x00000900}, {0xef, 0x00000000}, 292 {0xed, 0x00000001}, {0x40, 0x000380ef}, 293 {0x40, 0x000302fe}, {0x40, 0x00028ce6}, 294 {0x40, 0x000200bc}, {0x40, 0x000188a5}, 295 {0x40, 0x00010fbc}, {0x40, 0x00008f71}, 296 {0x40, 0x00000900}, {0xed, 0x00000000}, 297 {0x82, 0x00080000}, {0x83, 0x00008000}, 298 {0x84, 0x00048d80}, {0x85, 0x00068000}, 299 {0xa2, 0x00080000}, {0xa3, 0x00008000}, 300 {0xa4, 0x00048d80}, {0xa5, 0x00068000}, 301 {0xed, 0x00000002}, {0xef, 0x00000002}, 302 {0x56, 0x00000032}, {0x76, 0x00000032}, 303 {0x01, 0x00000780}, 304 {0xff, 0xffffffff} 305 }; 306 307 static int rtl8723bu_identify_chip(struct rtl8xxxu_priv *priv) 308 { 309 struct device *dev = &priv->udev->dev; 310 u32 val32, sys_cfg, vendor; 311 int ret = 0; 312 313 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); 314 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); 315 if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { 316 dev_info(dev, "Unsupported test chip\n"); 317 ret = -ENOTSUPP; 318 goto out; 319 } 320 321 strscpy(priv->chip_name, "8723BU", sizeof(priv->chip_name)); 322 priv->rtl_chip = RTL8723B; 323 priv->rf_paths = 1; 324 priv->rx_paths = 1; 325 priv->tx_paths = 1; 326 327 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); 328 if (val32 & MULTI_WIFI_FUNC_EN) 329 priv->has_wifi = 1; 330 if (val32 & MULTI_BT_FUNC_EN) 331 priv->has_bluetooth = 1; 332 if (val32 & MULTI_GPS_FUNC_EN) 333 priv->has_gps = 1; 334 priv->is_multi_func = 1; 335 336 vendor = sys_cfg & SYS_CFG_VENDOR_EXT_MASK; 337 rtl8xxxu_identify_vendor_2bits(priv, vendor); 338 339 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); 340 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); 341 342 rtl8xxxu_config_endpoints_sie(priv); 343 344 /* 345 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX 346 */ 347 if (!priv->ep_tx_count) 348 ret = rtl8xxxu_config_endpoints_no_sie(priv); 349 350 out: 351 return ret; 352 } 353 354 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data) 355 { 356 struct h2c_cmd h2c; 357 int reqnum = 0; 358 359 memset(&h2c, 0, sizeof(struct h2c_cmd)); 360 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER; 361 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4); 362 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE; 363 h2c.bt_mp_oper.data = data; 364 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); 365 366 reqnum++; 367 memset(&h2c, 0, sizeof(struct h2c_cmd)); 368 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER; 369 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4); 370 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE; 371 h2c.bt_mp_oper.addr = reg; 372 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); 373 } 374 375 static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv) 376 { 377 u8 val8; 378 u16 sys_func; 379 380 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); 381 val8 &= ~BIT(1); 382 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); 383 384 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 385 val8 &= ~BIT(0); 386 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 387 388 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); 389 sys_func &= ~SYS_FUNC_CPU_ENABLE; 390 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 391 392 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); 393 val8 &= ~BIT(1); 394 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); 395 396 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 397 val8 |= BIT(0); 398 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 399 400 sys_func |= SYS_FUNC_CPU_ENABLE; 401 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 402 } 403 404 static void 405 rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) 406 { 407 u32 val32, ofdm, mcs; 408 u8 cck, ofdmbase, mcsbase; 409 int group, tx_idx; 410 411 tx_idx = 0; 412 group = rtl8xxxu_gen2_channel_to_group(channel); 413 414 cck = priv->cck_tx_power_index_B[group]; 415 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); 416 val32 &= 0xffff00ff; 417 val32 |= (cck << 8); 418 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); 419 420 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 421 val32 &= 0xff; 422 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); 423 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 424 425 ofdmbase = priv->ht40_1s_tx_power_index_B[group]; 426 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; 427 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; 428 429 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); 430 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); 431 432 mcsbase = priv->ht40_1s_tx_power_index_B[group]; 433 if (ht40) 434 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; 435 else 436 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; 437 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; 438 439 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); 440 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); 441 } 442 443 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv) 444 { 445 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu; 446 int i; 447 448 if (efuse->rtl_id != cpu_to_le16(0x8129)) 449 return -EINVAL; 450 451 ether_addr_copy(priv->mac_addr, efuse->mac_addr); 452 453 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, 454 sizeof(efuse->tx_power_index_A.cck_base)); 455 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, 456 sizeof(efuse->tx_power_index_B.cck_base)); 457 458 memcpy(priv->ht40_1s_tx_power_index_A, 459 efuse->tx_power_index_A.ht40_base, 460 sizeof(efuse->tx_power_index_A.ht40_base)); 461 memcpy(priv->ht40_1s_tx_power_index_B, 462 efuse->tx_power_index_B.ht40_base, 463 sizeof(efuse->tx_power_index_B.ht40_base)); 464 465 priv->ofdm_tx_power_diff[0].a = 466 efuse->tx_power_index_A.ht20_ofdm_1s_diff.a; 467 priv->ofdm_tx_power_diff[0].b = 468 efuse->tx_power_index_B.ht20_ofdm_1s_diff.a; 469 470 priv->ht20_tx_power_diff[0].a = 471 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; 472 priv->ht20_tx_power_diff[0].b = 473 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b; 474 475 priv->ht40_tx_power_diff[0].a = 0; 476 priv->ht40_tx_power_diff[0].b = 0; 477 478 for (i = 1; i < RTL8723B_TX_COUNT; i++) { 479 priv->ofdm_tx_power_diff[i].a = 480 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm; 481 priv->ofdm_tx_power_diff[i].b = 482 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm; 483 484 priv->ht20_tx_power_diff[i].a = 485 efuse->tx_power_index_A.pwr_diff[i - 1].ht20; 486 priv->ht20_tx_power_diff[i].b = 487 efuse->tx_power_index_B.pwr_diff[i - 1].ht20; 488 489 priv->ht40_tx_power_diff[i].a = 490 efuse->tx_power_index_A.pwr_diff[i - 1].ht40; 491 priv->ht40_tx_power_diff[i].b = 492 efuse->tx_power_index_B.pwr_diff[i - 1].ht40; 493 } 494 495 priv->default_crystal_cap = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f; 496 497 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name); 498 dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name); 499 500 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) { 501 int i; 502 unsigned char *raw = priv->efuse_wifi.raw; 503 504 dev_info(&priv->udev->dev, 505 "%s: dumping efuse (0x%02zx bytes):\n", 506 __func__, sizeof(struct rtl8723bu_efuse)); 507 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) 508 dev_info(&priv->udev->dev, "%02x: %8ph\n", i, &raw[i]); 509 } 510 511 return 0; 512 } 513 514 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv) 515 { 516 char *fw_name; 517 int ret; 518 519 if (priv->enable_bluetooth) 520 fw_name = "rtlwifi/rtl8723bu_bt.bin"; 521 else 522 fw_name = "rtlwifi/rtl8723bu_nic.bin"; 523 524 ret = rtl8xxxu_load_firmware(priv, fw_name); 525 return ret; 526 } 527 528 static void rtl8723bu_init_phy_bb(struct rtl8xxxu_priv *priv) 529 { 530 u8 val8; 531 u16 val16; 532 533 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 534 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; 535 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 536 537 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); 538 539 /* 6. 0x1f[7:0] = 0x07 */ 540 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; 541 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 542 543 /* Why? */ 544 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3); 545 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80); 546 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table); 547 548 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table); 549 } 550 551 static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv) 552 { 553 int ret; 554 555 ret = rtl8xxxu_init_phy_rf(priv, rtl8723bu_radioa_1t_init_table, RF_A); 556 /* 557 * PHY LCK 558 */ 559 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0); 560 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01); 561 msleep(200); 562 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0); 563 564 return ret; 565 } 566 567 void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv) 568 { 569 u32 val32; 570 571 val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1); 572 val32 &= ~(BIT(20) | BIT(24)); 573 rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32); 574 575 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); 576 val32 &= ~BIT(4); 577 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); 578 579 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); 580 val32 |= BIT(3); 581 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); 582 583 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); 584 val32 |= BIT(24); 585 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); 586 587 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); 588 val32 &= ~BIT(23); 589 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); 590 591 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); 592 val32 |= (BIT(0) | BIT(1)); 593 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); 594 595 val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC); 596 val32 &= 0xffffff00; 597 val32 |= 0x77; 598 rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32); 599 600 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); 601 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; 602 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); 603 } 604 605 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv) 606 { 607 u32 reg_eac, reg_e94, reg_e9c, path_sel, val32; 608 int result = 0; 609 610 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); 611 612 /* 613 * Leave IQK mode 614 */ 615 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 616 val32 &= 0x000000ff; 617 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 618 619 /* 620 * Enable path A PA in TX IQK mode 621 */ 622 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 623 val32 |= 0x80000; 624 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 625 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); 626 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f); 627 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87); 628 629 /* 630 * Tx IQK setting 631 */ 632 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 633 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 634 635 /* path-A IQK setting */ 636 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); 637 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 638 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); 639 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); 640 641 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea); 642 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); 643 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); 644 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); 645 646 /* LO calibration setting */ 647 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); 648 649 /* 650 * Enter IQK mode 651 */ 652 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 653 val32 &= 0x000000ff; 654 val32 |= 0x80800000; 655 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 656 657 /* 658 * The vendor driver indicates the USB module is always using 659 * S0S1 path 1 for the 8723bu. This may be different for 8192eu 660 */ 661 if (priv->rf_paths > 1) 662 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); 663 else 664 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); 665 666 /* 667 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu. 668 * No trace of this in the 8192eu or 8188eu vendor drivers. 669 */ 670 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); 671 672 /* One shot, path A LOK & IQK */ 673 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 674 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 675 676 mdelay(1); 677 678 /* Restore Ant Path */ 679 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); 680 #ifdef RTL8723BU_BT 681 /* GNT_BT = 1 */ 682 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); 683 #endif 684 685 /* 686 * Leave IQK mode 687 */ 688 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 689 val32 &= 0x000000ff; 690 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 691 692 /* Check failed */ 693 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 694 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 695 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 696 697 val32 = (reg_e9c >> 16) & 0x3ff; 698 if (val32 & 0x200) 699 val32 = 0x400 - val32; 700 701 if (!(reg_eac & BIT(28)) && 702 ((reg_e94 & 0x03ff0000) != 0x01420000) && 703 ((reg_e9c & 0x03ff0000) != 0x00420000) && 704 ((reg_e94 & 0x03ff0000) < 0x01100000) && 705 ((reg_e94 & 0x03ff0000) > 0x00f00000) && 706 val32 < 0xf) 707 result |= 0x01; 708 else /* If TX not OK, ignore RX */ 709 goto out; 710 711 out: 712 return result; 713 } 714 715 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) 716 { 717 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32; 718 int result = 0; 719 720 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); 721 722 /* 723 * Leave IQK mode 724 */ 725 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 726 val32 &= 0x000000ff; 727 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 728 729 /* 730 * Enable path A PA in TX IQK mode 731 */ 732 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 733 val32 |= 0x80000; 734 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 735 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 736 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); 737 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); 738 739 /* 740 * Tx IQK setting 741 */ 742 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 743 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 744 745 /* path-A IQK setting */ 746 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); 747 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 748 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); 749 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); 750 751 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0); 752 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); 753 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); 754 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); 755 756 /* LO calibration setting */ 757 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); 758 759 /* 760 * Enter IQK mode 761 */ 762 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 763 val32 &= 0x000000ff; 764 val32 |= 0x80800000; 765 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 766 767 /* 768 * The vendor driver indicates the USB module is always using 769 * S0S1 path 1 for the 8723bu. This may be different for 8192eu 770 */ 771 if (priv->rf_paths > 1) 772 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); 773 else 774 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); 775 776 /* 777 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu. 778 * No trace of this in the 8192eu or 8188eu vendor drivers. 779 */ 780 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); 781 782 /* One shot, path A LOK & IQK */ 783 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 784 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 785 786 mdelay(1); 787 788 /* Restore Ant Path */ 789 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); 790 #ifdef RTL8723BU_BT 791 /* GNT_BT = 1 */ 792 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); 793 #endif 794 795 /* 796 * Leave IQK mode 797 */ 798 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 799 val32 &= 0x000000ff; 800 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 801 802 /* Check failed */ 803 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 804 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 805 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 806 807 val32 = (reg_e9c >> 16) & 0x3ff; 808 if (val32 & 0x200) 809 val32 = 0x400 - val32; 810 811 if (!(reg_eac & BIT(28)) && 812 ((reg_e94 & 0x03ff0000) != 0x01420000) && 813 ((reg_e9c & 0x03ff0000) != 0x00420000) && 814 ((reg_e94 & 0x03ff0000) < 0x01100000) && 815 ((reg_e94 & 0x03ff0000) > 0x00f00000) && 816 val32 < 0xf) 817 result |= 0x01; 818 else /* If TX not OK, ignore RX */ 819 goto out; 820 821 val32 = 0x80007c00 | (reg_e94 &0x3ff0000) | 822 ((reg_e9c & 0x3ff0000) >> 16); 823 rtl8xxxu_write32(priv, REG_TX_IQK, val32); 824 825 /* 826 * Modify RX IQK mode 827 */ 828 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 829 val32 &= 0x000000ff; 830 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 831 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 832 val32 |= 0x80000; 833 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 834 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 835 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); 836 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77); 837 838 /* 839 * PA, PAD setting 840 */ 841 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80); 842 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f); 843 844 /* 845 * RX IQK setting 846 */ 847 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 848 849 /* path-A IQK setting */ 850 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); 851 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); 852 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); 853 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); 854 855 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000); 856 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f); 857 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); 858 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); 859 860 /* LO calibration setting */ 861 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1); 862 863 /* 864 * Enter IQK mode 865 */ 866 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 867 val32 &= 0x000000ff; 868 val32 |= 0x80800000; 869 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 870 871 if (priv->rf_paths > 1) 872 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); 873 else 874 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); 875 876 /* 877 * Disable BT 878 */ 879 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); 880 881 /* One shot, path A LOK & IQK */ 882 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 883 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 884 885 mdelay(1); 886 887 /* Restore Ant Path */ 888 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); 889 #ifdef RTL8723BU_BT 890 /* GNT_BT = 1 */ 891 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); 892 #endif 893 894 /* 895 * Leave IQK mode 896 */ 897 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 898 val32 &= 0x000000ff; 899 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 900 901 /* Check failed */ 902 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 903 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 904 905 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780); 906 907 val32 = (reg_eac >> 16) & 0x3ff; 908 if (val32 & 0x200) 909 val32 = 0x400 - val32; 910 911 if (!(reg_eac & BIT(27)) && 912 ((reg_ea4 & 0x03ff0000) != 0x01320000) && 913 ((reg_eac & 0x03ff0000) != 0x00360000) && 914 ((reg_ea4 & 0x03ff0000) < 0x01100000) && 915 ((reg_ea4 & 0x03ff0000) > 0x00f00000) && 916 val32 < 0xf) 917 result |= 0x02; 918 else /* If TX not OK, ignore RX */ 919 goto out; 920 out: 921 return result; 922 } 923 924 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, 925 int result[][8], int t) 926 { 927 struct device *dev = &priv->udev->dev; 928 u32 i, val32; 929 int path_a_ok /*, path_b_ok */; 930 int retry = 2; 931 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { 932 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, 933 REG_RX_WAIT_CCA, REG_TX_CCK_RFON, 934 REG_TX_CCK_BBON, REG_TX_OFDM_RFON, 935 REG_TX_OFDM_BBON, REG_TX_TO_RX, 936 REG_TX_TO_TX, REG_RX_CCK, 937 REG_RX_OFDM, REG_RX_WAIT_RIFS, 938 REG_RX_TO_RX, REG_STANDBY, 939 REG_SLEEP, REG_PMPD_ANAEN 940 }; 941 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { 942 REG_TXPAUSE, REG_BEACON_CTRL, 943 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG 944 }; 945 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { 946 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, 947 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, 948 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, 949 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE 950 }; 951 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; 952 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; 953 954 /* 955 * Note: IQ calibration must be performed after loading 956 * PHY_REG.txt , and radio_a, radio_b.txt 957 */ 958 959 if (t == 0) { 960 /* Save ADDA parameters, turn Path A ADDA on */ 961 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, 962 RTL8XXXU_ADDA_REGS); 963 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 964 rtl8xxxu_save_regs(priv, iqk_bb_regs, 965 priv->bb_backup, RTL8XXXU_BB_REGS); 966 } 967 968 rtl8xxxu_path_adda_on(priv, adda_regs, true); 969 970 /* MAC settings */ 971 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); 972 973 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); 974 val32 |= 0x0f000000; 975 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); 976 977 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); 978 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); 979 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); 980 981 /* 982 * RX IQ calibration setting for 8723B D cut large current issue 983 * when leaving IPS 984 */ 985 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 986 val32 &= 0x000000ff; 987 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 988 989 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 990 val32 |= 0x80000; 991 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 992 993 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 994 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); 995 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); 996 997 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); 998 val32 |= 0x20; 999 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); 1000 1001 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd); 1002 1003 for (i = 0; i < retry; i++) { 1004 path_a_ok = rtl8723bu_iqk_path_a(priv); 1005 if (path_a_ok == 0x01) { 1006 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1007 val32 &= 0x000000ff; 1008 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1009 1010 val32 = rtl8xxxu_read32(priv, 1011 REG_TX_POWER_BEFORE_IQK_A); 1012 result[t][0] = (val32 >> 16) & 0x3ff; 1013 val32 = rtl8xxxu_read32(priv, 1014 REG_TX_POWER_AFTER_IQK_A); 1015 result[t][1] = (val32 >> 16) & 0x3ff; 1016 1017 break; 1018 } 1019 } 1020 1021 if (!path_a_ok) 1022 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__); 1023 1024 for (i = 0; i < retry; i++) { 1025 path_a_ok = rtl8723bu_rx_iqk_path_a(priv); 1026 if (path_a_ok == 0x03) { 1027 val32 = rtl8xxxu_read32(priv, 1028 REG_RX_POWER_BEFORE_IQK_A_2); 1029 result[t][2] = (val32 >> 16) & 0x3ff; 1030 val32 = rtl8xxxu_read32(priv, 1031 REG_RX_POWER_AFTER_IQK_A_2); 1032 result[t][3] = (val32 >> 16) & 0x3ff; 1033 1034 break; 1035 } 1036 } 1037 1038 if (!path_a_ok) 1039 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__); 1040 1041 if (priv->tx_paths > 1) { 1042 #if 1 1043 dev_warn(dev, "%s: Path B not supported\n", __func__); 1044 #else 1045 1046 /* 1047 * Path A into standby 1048 */ 1049 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1050 val32 &= 0x000000ff; 1051 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1052 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); 1053 1054 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1055 val32 &= 0x000000ff; 1056 val32 |= 0x80800000; 1057 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1058 1059 /* Turn Path B ADDA on */ 1060 rtl8xxxu_path_adda_on(priv, adda_regs, false); 1061 1062 for (i = 0; i < retry; i++) { 1063 path_b_ok = rtl8xxxu_iqk_path_b(priv); 1064 if (path_b_ok == 0x03) { 1065 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 1066 result[t][4] = (val32 >> 16) & 0x3ff; 1067 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 1068 result[t][5] = (val32 >> 16) & 0x3ff; 1069 break; 1070 } 1071 } 1072 1073 if (!path_b_ok) 1074 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); 1075 1076 for (i = 0; i < retry; i++) { 1077 path_b_ok = rtl8723bu_rx_iqk_path_b(priv); 1078 if (path_a_ok == 0x03) { 1079 val32 = rtl8xxxu_read32(priv, 1080 REG_RX_POWER_BEFORE_IQK_B_2); 1081 result[t][6] = (val32 >> 16) & 0x3ff; 1082 val32 = rtl8xxxu_read32(priv, 1083 REG_RX_POWER_AFTER_IQK_B_2); 1084 result[t][7] = (val32 >> 16) & 0x3ff; 1085 break; 1086 } 1087 } 1088 1089 if (!path_b_ok) 1090 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__); 1091 #endif 1092 } 1093 1094 /* Back to BB mode, load original value */ 1095 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1096 val32 &= 0x000000ff; 1097 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1098 1099 if (t) { 1100 /* Reload ADDA power saving parameters */ 1101 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, 1102 RTL8XXXU_ADDA_REGS); 1103 1104 /* Reload MAC parameters */ 1105 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 1106 1107 /* Reload BB parameters */ 1108 rtl8xxxu_restore_regs(priv, iqk_bb_regs, 1109 priv->bb_backup, RTL8XXXU_BB_REGS); 1110 1111 /* Restore RX initial gain */ 1112 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 1113 val32 &= 0xffffff00; 1114 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); 1115 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); 1116 1117 if (priv->tx_paths > 1) { 1118 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); 1119 val32 &= 0xffffff00; 1120 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, 1121 val32 | 0x50); 1122 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, 1123 val32 | xb_agc); 1124 } 1125 1126 /* Load 0xe30 IQC default value */ 1127 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); 1128 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); 1129 } 1130 } 1131 1132 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) 1133 { 1134 struct device *dev = &priv->udev->dev; 1135 int result[4][8]; /* last is final result */ 1136 int i, candidate; 1137 bool path_a_ok, path_b_ok; 1138 u32 reg_e94, reg_e9c, reg_ea4, reg_eac; 1139 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; 1140 u32 val32, bt_control; 1141 s32 reg_tmp = 0; 1142 bool simu; 1143 1144 rtl8xxxu_gen2_prepare_calibrate(priv, 1); 1145 1146 memset(result, 0, sizeof(result)); 1147 candidate = -1; 1148 1149 path_a_ok = false; 1150 path_b_ok = false; 1151 1152 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU); 1153 1154 for (i = 0; i < 3; i++) { 1155 rtl8723bu_phy_iqcalibrate(priv, result, i); 1156 1157 if (i == 1) { 1158 simu = rtl8xxxu_gen2_simularity_compare(priv, 1159 result, 0, 1); 1160 if (simu) { 1161 candidate = 0; 1162 break; 1163 } 1164 } 1165 1166 if (i == 2) { 1167 simu = rtl8xxxu_gen2_simularity_compare(priv, 1168 result, 0, 2); 1169 if (simu) { 1170 candidate = 0; 1171 break; 1172 } 1173 1174 simu = rtl8xxxu_gen2_simularity_compare(priv, 1175 result, 1, 2); 1176 if (simu) { 1177 candidate = 1; 1178 } else { 1179 for (i = 0; i < 8; i++) 1180 reg_tmp += result[3][i]; 1181 1182 if (reg_tmp) 1183 candidate = 3; 1184 else 1185 candidate = -1; 1186 } 1187 } 1188 } 1189 1190 for (i = 0; i < 4; i++) { 1191 reg_e94 = result[i][0]; 1192 reg_e9c = result[i][1]; 1193 reg_ea4 = result[i][2]; 1194 reg_eac = result[i][3]; 1195 reg_eb4 = result[i][4]; 1196 reg_ebc = result[i][5]; 1197 reg_ec4 = result[i][6]; 1198 reg_ecc = result[i][7]; 1199 } 1200 1201 if (candidate >= 0) { 1202 reg_e94 = result[candidate][0]; 1203 priv->rege94 = reg_e94; 1204 reg_e9c = result[candidate][1]; 1205 priv->rege9c = reg_e9c; 1206 reg_ea4 = result[candidate][2]; 1207 reg_eac = result[candidate][3]; 1208 reg_eb4 = result[candidate][4]; 1209 priv->regeb4 = reg_eb4; 1210 reg_ebc = result[candidate][5]; 1211 priv->regebc = reg_ebc; 1212 reg_ec4 = result[candidate][6]; 1213 reg_ecc = result[candidate][7]; 1214 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); 1215 dev_dbg(dev, 1216 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", 1217 __func__, reg_e94, reg_e9c, 1218 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); 1219 path_a_ok = true; 1220 path_b_ok = true; 1221 } else { 1222 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; 1223 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; 1224 } 1225 1226 if (reg_e94 && candidate >= 0) 1227 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, 1228 candidate, (reg_ea4 == 0)); 1229 1230 if (priv->tx_paths > 1 && reg_eb4) 1231 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, 1232 candidate, (reg_ec4 == 0)); 1233 1234 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, 1235 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); 1236 1237 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control); 1238 1239 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 1240 val32 |= 0x80000; 1241 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 1242 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000); 1243 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); 1244 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177); 1245 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); 1246 val32 |= 0x20; 1247 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); 1248 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd); 1249 1250 if (priv->rf_paths > 1) 1251 dev_dbg(dev, "%s: 8723BU 2T not supported\n", __func__); 1252 1253 rtl8xxxu_gen2_prepare_calibrate(priv, 0); 1254 } 1255 1256 static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv) 1257 { 1258 u8 val8; 1259 u16 val16; 1260 u32 val32; 1261 int count, ret = 0; 1262 1263 /* Turn off RF */ 1264 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); 1265 1266 /* Enable rising edge triggering interrupt */ 1267 val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM); 1268 val16 &= ~GPIO_INTM_EDGE_TRIG_IRQ; 1269 rtl8xxxu_write16(priv, REG_GPIO_INTM, val16); 1270 1271 /* Release WLON reset 0x04[16]= 1*/ 1272 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1273 val32 |= APS_FSMCO_WLON_RESET; 1274 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); 1275 1276 /* 0x0005[1] = 1 turn off MAC by HW state machine*/ 1277 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1278 val8 |= BIT(1); 1279 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1280 1281 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1282 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1283 if ((val8 & BIT(1)) == 0) 1284 break; 1285 udelay(10); 1286 } 1287 1288 if (!count) { 1289 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", 1290 __func__); 1291 ret = -EBUSY; 1292 goto exit; 1293 } 1294 1295 /* Enable BT control XTAL setting */ 1296 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); 1297 val8 &= ~AFE_MISC_WL_XTAL_CTRL; 1298 rtl8xxxu_write8(priv, REG_AFE_MISC, val8); 1299 1300 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ 1301 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); 1302 val8 |= SYS_ISO_ANALOG_IPS; 1303 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); 1304 1305 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ 1306 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); 1307 val8 &= ~LDOA15_ENABLE; 1308 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); 1309 1310 exit: 1311 return ret; 1312 } 1313 1314 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv) 1315 { 1316 u8 val8; 1317 u32 val32; 1318 int count, ret = 0; 1319 1320 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */ 1321 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); 1322 val8 |= LDOA15_ENABLE; 1323 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); 1324 1325 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/ 1326 val8 = rtl8xxxu_read8(priv, 0x0067); 1327 val8 &= ~BIT(4); 1328 rtl8xxxu_write8(priv, 0x0067, val8); 1329 1330 mdelay(1); 1331 1332 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */ 1333 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); 1334 val8 &= ~SYS_ISO_ANALOG_IPS; 1335 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); 1336 1337 /* Disable SW LPS 0x04[10]= 0 */ 1338 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO); 1339 val32 &= ~APS_FSMCO_SW_LPS; 1340 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); 1341 1342 /* Wait until 0x04[17] = 1 power ready */ 1343 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1344 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1345 if (val32 & BIT(17)) 1346 break; 1347 1348 udelay(10); 1349 } 1350 1351 if (!count) { 1352 ret = -EBUSY; 1353 goto exit; 1354 } 1355 1356 /* We should be able to optimize the following three entries into one */ 1357 1358 /* Release WLON reset 0x04[16]= 1*/ 1359 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1360 val32 |= APS_FSMCO_WLON_RESET; 1361 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); 1362 1363 /* Disable HWPDN 0x04[15]= 0*/ 1364 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1365 val32 &= ~APS_FSMCO_HW_POWERDOWN; 1366 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); 1367 1368 /* Disable WL suspend*/ 1369 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1370 val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE); 1371 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); 1372 1373 /* Set, then poll until 0 */ 1374 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1375 val32 |= APS_FSMCO_MAC_ENABLE; 1376 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); 1377 1378 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1379 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1380 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { 1381 ret = 0; 1382 break; 1383 } 1384 udelay(10); 1385 } 1386 1387 if (!count) { 1388 ret = -EBUSY; 1389 goto exit; 1390 } 1391 1392 /* Enable WL control XTAL setting */ 1393 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); 1394 val8 |= AFE_MISC_WL_XTAL_CTRL; 1395 rtl8xxxu_write8(priv, REG_AFE_MISC, val8); 1396 1397 /* Enable falling edge triggering interrupt */ 1398 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1); 1399 val8 |= BIT(1); 1400 rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8); 1401 1402 /* Enable GPIO9 interrupt mode */ 1403 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1); 1404 val8 |= BIT(1); 1405 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8); 1406 1407 /* Enable GPIO9 input mode */ 1408 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2); 1409 val8 &= ~BIT(1); 1410 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8); 1411 1412 /* Enable HSISR GPIO[C:0] interrupt */ 1413 val8 = rtl8xxxu_read8(priv, REG_HSIMR); 1414 val8 |= BIT(0); 1415 rtl8xxxu_write8(priv, REG_HSIMR, val8); 1416 1417 /* Enable HSISR GPIO9 interrupt */ 1418 val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2); 1419 val8 |= BIT(1); 1420 rtl8xxxu_write8(priv, REG_HSIMR + 2, val8); 1421 1422 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL); 1423 val8 |= MULTI_WIFI_HW_ROF_EN; 1424 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8); 1425 1426 /* For GPIO9 internal pull high setting BIT(14) */ 1427 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1); 1428 val8 |= BIT(6); 1429 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8); 1430 1431 exit: 1432 return ret; 1433 } 1434 1435 static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv) 1436 { 1437 u8 val8; 1438 u16 val16; 1439 u32 val32; 1440 int ret; 1441 1442 rtl8xxxu_disabled_to_emu(priv); 1443 1444 ret = rtl8723b_emu_to_active(priv); 1445 if (ret) 1446 goto exit; 1447 1448 /* 1449 * Enable MAC DMA/WMAC/SCHEDULE/SEC block 1450 * Set CR bit10 to enable 32k calibration. 1451 */ 1452 val16 = rtl8xxxu_read16(priv, REG_CR); 1453 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | 1454 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | 1455 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | 1456 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | 1457 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); 1458 rtl8xxxu_write16(priv, REG_CR, val16); 1459 1460 /* 1461 * BT coexist power on settings. This is identical for 1 and 2 1462 * antenna parts. 1463 */ 1464 rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20); 1465 1466 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1467 val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN; 1468 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1469 1470 rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18); 1471 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); 1472 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); 1473 /* Antenna inverse */ 1474 rtl8xxxu_write8(priv, 0xfe08, 0x01); 1475 1476 val16 = rtl8xxxu_read16(priv, REG_PWR_DATA); 1477 val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; 1478 rtl8xxxu_write16(priv, REG_PWR_DATA, val16); 1479 1480 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); 1481 val32 |= LEDCFG0_DPDT_SELECT; 1482 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); 1483 1484 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); 1485 val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA; 1486 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); 1487 exit: 1488 return ret; 1489 } 1490 1491 static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv) 1492 { 1493 u8 val8; 1494 u16 val16; 1495 1496 rtl8xxxu_flush_fifo(priv); 1497 1498 /* 1499 * Disable TX report timer 1500 */ 1501 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); 1502 val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; 1503 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); 1504 1505 rtl8xxxu_write8(priv, REG_CR, 0x0000); 1506 1507 rtl8xxxu_active_to_lps(priv); 1508 1509 /* Reset Firmware if running in RAM */ 1510 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) 1511 rtl8xxxu_firmware_self_reset(priv); 1512 1513 /* Reset MCU */ 1514 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1515 val16 &= ~SYS_FUNC_CPU_ENABLE; 1516 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1517 1518 /* Reset MCU ready status */ 1519 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 1520 1521 rtl8723bu_active_to_emu(priv); 1522 1523 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1524 val8 |= BIT(3); /* APS_FSMCO_HW_SUSPEND */ 1525 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1526 1527 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */ 1528 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); 1529 val8 |= BIT(0); 1530 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); 1531 } 1532 1533 static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv) 1534 { 1535 struct h2c_cmd h2c; 1536 u32 val32; 1537 u8 val8; 1538 1539 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); 1540 val32 |= (BIT(22) | BIT(23)); 1541 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); 1542 1543 /* 1544 * No indication anywhere as to what 0x0790 does. The 2 antenna 1545 * vendor code preserves bits 6-7 here. 1546 */ 1547 rtl8xxxu_write8(priv, 0x0790, 0x05); 1548 /* 1549 * 0x0778 seems to be related to enabling the number of antennas 1550 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it 1551 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01 1552 */ 1553 rtl8xxxu_write8(priv, 0x0778, 0x01); 1554 1555 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); 1556 val8 |= BIT(5); 1557 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); 1558 1559 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); 1560 1561 rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */ 1562 1563 /* 1564 * Set BT grant to low 1565 */ 1566 memset(&h2c, 0, sizeof(struct h2c_cmd)); 1567 h2c.bt_grant.cmd = H2C_8723B_BT_GRANT; 1568 h2c.bt_grant.data = 0; 1569 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant)); 1570 1571 /* 1572 * WLAN action by PTA 1573 */ 1574 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x0c); 1575 1576 /* 1577 * BT select S0/S1 controlled by WiFi 1578 */ 1579 val8 = rtl8xxxu_read8(priv, 0x0067); 1580 val8 |= BIT(5); 1581 rtl8xxxu_write8(priv, 0x0067, val8); 1582 1583 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); 1584 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; 1585 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); 1586 1587 /* 1588 * Bits 6/7 are marked in/out ... but for what? 1589 */ 1590 rtl8xxxu_write8(priv, 0x0974, 0xff); 1591 1592 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); 1593 val32 |= (BIT(0) | BIT(1)); 1594 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); 1595 1596 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77); 1597 1598 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); 1599 val32 &= ~BIT(24); 1600 val32 |= BIT(23); 1601 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); 1602 1603 /* 1604 * Fix external switch Main->S1, Aux->S0 1605 */ 1606 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); 1607 val8 &= ~BIT(0); 1608 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); 1609 1610 memset(&h2c, 0, sizeof(struct h2c_cmd)); 1611 h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV; 1612 h2c.ant_sel_rsv.ant_inverse = 1; 1613 h2c.ant_sel_rsv.int_switch_type = 0; 1614 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv)); 1615 1616 /* 1617 * Different settings per different antenna position. 1618 * Antenna Position: | Normal Inverse 1619 * -------------------------------------------------- 1620 * Antenna switch to BT: | 0x280, 0x00 1621 * Antenna switch to WiFi: | 0x0, 0x280 1622 * Antenna switch to PTA: | 0x200, 0x80 1623 */ 1624 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x80); 1625 1626 /* 1627 * Software control, antenna at WiFi side 1628 */ 1629 rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00); 1630 1631 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 1632 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); 1633 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 1634 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 1635 1636 memset(&h2c, 0, sizeof(struct h2c_cmd)); 1637 h2c.bt_info.cmd = H2C_8723B_BT_INFO; 1638 h2c.bt_info.data = BIT(0); 1639 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info)); 1640 1641 memset(&h2c, 0, sizeof(struct h2c_cmd)); 1642 h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT; 1643 h2c.ignore_wlan.data = 0; 1644 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan)); 1645 } 1646 1647 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv) 1648 { 1649 u32 agg_rx; 1650 u8 agg_ctrl; 1651 1652 /* 1653 * For now simply disable RX aggregation 1654 */ 1655 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); 1656 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; 1657 1658 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); 1659 agg_rx &= ~RXDMA_USB_AGG_ENABLE; 1660 agg_rx &= ~0xff0f; 1661 1662 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 1663 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); 1664 } 1665 1666 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv) 1667 { 1668 u32 val32; 1669 1670 /* Time duration for NHM unit: 4us, 0x2710=40ms */ 1671 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710); 1672 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); 1673 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52); 1674 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); 1675 /* TH8 */ 1676 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1677 val32 |= 0xff; 1678 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1679 /* Enable CCK */ 1680 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); 1681 val32 |= BIT(8) | BIT(9) | BIT(10); 1682 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); 1683 /* Max power amongst all RX antennas */ 1684 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); 1685 val32 |= BIT(7); 1686 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); 1687 } 1688 1689 static s8 rtl8723b_cck_rssi(struct rtl8xxxu_priv *priv, u8 cck_agc_rpt) 1690 { 1691 s8 rx_pwr_all = 0x00; 1692 u8 vga_idx, lna_idx; 1693 1694 lna_idx = (cck_agc_rpt & 0xE0) >> 5; 1695 vga_idx = cck_agc_rpt & 0x1F; 1696 1697 switch (lna_idx) { 1698 case 6: 1699 rx_pwr_all = -34 - (2 * vga_idx); 1700 break; 1701 case 4: 1702 rx_pwr_all = -14 - (2 * vga_idx); 1703 break; 1704 case 1: 1705 rx_pwr_all = 6 - (2 * vga_idx); 1706 break; 1707 case 0: 1708 rx_pwr_all = 16 - (2 * vga_idx); 1709 break; 1710 default: 1711 break; 1712 } 1713 1714 return rx_pwr_all; 1715 } 1716 1717 struct rtl8xxxu_fileops rtl8723bu_fops = { 1718 .identify_chip = rtl8723bu_identify_chip, 1719 .parse_efuse = rtl8723bu_parse_efuse, 1720 .load_firmware = rtl8723bu_load_firmware, 1721 .power_on = rtl8723bu_power_on, 1722 .power_off = rtl8723bu_power_off, 1723 .reset_8051 = rtl8723bu_reset_8051, 1724 .llt_init = rtl8xxxu_auto_llt_table, 1725 .init_phy_bb = rtl8723bu_init_phy_bb, 1726 .init_phy_rf = rtl8723bu_init_phy_rf, 1727 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection, 1728 .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, 1729 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate, 1730 .config_channel = rtl8xxxu_gen2_config_channel, 1731 .parse_rx_desc = rtl8xxxu_parse_rxdesc24, 1732 .init_aggregation = rtl8723bu_init_aggregation, 1733 .init_statistics = rtl8723bu_init_statistics, 1734 .init_burst = rtl8xxxu_init_burst, 1735 .enable_rf = rtl8723b_enable_rf, 1736 .disable_rf = rtl8xxxu_gen2_disable_rf, 1737 .usb_quirks = rtl8xxxu_gen2_usb_quirks, 1738 .set_tx_power = rtl8723b_set_tx_power, 1739 .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, 1740 .report_connect = rtl8xxxu_gen2_report_connect, 1741 .fill_txdesc = rtl8xxxu_fill_txdesc_v2, 1742 .set_crystal_cap = rtl8723a_set_crystal_cap, 1743 .cck_rssi = rtl8723b_cck_rssi, 1744 .writeN_block_size = 1024, 1745 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), 1746 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), 1747 .has_s0s1 = 1, 1748 .has_tx_report = 1, 1749 .gen2_thermal_meter = 1, 1750 .needs_full_init = 1, 1751 .adda_1t_init = 0x01c00014, 1752 .adda_1t_path_on = 0x01c00014, 1753 .adda_2t_path_on_a = 0x01c00014, 1754 .adda_2t_path_on_b = 0x01c00014, 1755 .trxff_boundary = 0x3f7f, 1756 .pbp_rx = PBP_PAGE_SIZE_256, 1757 .pbp_tx = PBP_PAGE_SIZE_256, 1758 .mactable = rtl8723b_mac_init_table, 1759 .total_page_num = TX_TOTAL_PAGE_NUM_8723B, 1760 .page_num_hi = TX_PAGE_NUM_HI_PQ_8723B, 1761 .page_num_lo = TX_PAGE_NUM_LO_PQ_8723B, 1762 .page_num_norm = TX_PAGE_NUM_NORM_PQ_8723B, 1763 }; 1764