1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * RTL8XXXU mac80211 USB driver - 8723b specific subdriver 4 * 5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 6 * 7 * Portions, notably calibration code: 8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 9 * 10 * This driver was written as a replacement for the vendor provided 11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in 12 * their programming interface, I have started adding support for 13 * additional 8xxx chips like the 8192cu, 8188cus, etc. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/kernel.h> 18 #include <linux/sched.h> 19 #include <linux/errno.h> 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/spinlock.h> 23 #include <linux/list.h> 24 #include <linux/usb.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/ethtool.h> 28 #include <linux/wireless.h> 29 #include <linux/firmware.h> 30 #include <linux/moduleparam.h> 31 #include <net/mac80211.h> 32 #include "rtl8xxxu.h" 33 #include "rtl8xxxu_regs.h" 34 35 static const struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = { 36 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0}, 37 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10}, 38 {0x430, 0x00}, {0x431, 0x00}, 39 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, 40 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05}, 41 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01}, 42 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00}, 43 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f}, 44 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00}, 45 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f}, 46 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66}, 47 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, 48 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, 49 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, 50 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, 51 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, 52 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, 53 {0x516, 0x0a}, {0x525, 0x4f}, 54 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, 55 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, 56 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, 57 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, 58 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, 59 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, 60 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, 61 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, 62 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04}, 63 {0xffff, 0xff}, 64 }; 65 66 static const struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = { 67 {0x800, 0x80040000}, {0x804, 0x00000003}, 68 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 69 {0x810, 0x10001331}, {0x814, 0x020c3d10}, 70 {0x818, 0x02200385}, {0x81c, 0x00000000}, 71 {0x820, 0x01000100}, {0x824, 0x00190204}, 72 {0x828, 0x00000000}, {0x82c, 0x00000000}, 73 {0x830, 0x00000000}, {0x834, 0x00000000}, 74 {0x838, 0x00000000}, {0x83c, 0x00000000}, 75 {0x840, 0x00010000}, {0x844, 0x00000000}, 76 {0x848, 0x00000000}, {0x84c, 0x00000000}, 77 {0x850, 0x00000000}, {0x854, 0x00000000}, 78 {0x858, 0x569a11a9}, {0x85c, 0x01000014}, 79 {0x860, 0x66f60110}, {0x864, 0x061f0649}, 80 {0x868, 0x00000000}, {0x86c, 0x27272700}, 81 {0x870, 0x07000760}, {0x874, 0x25004000}, 82 {0x878, 0x00000808}, {0x87c, 0x00000000}, 83 {0x880, 0xb0000c1c}, {0x884, 0x00000001}, 84 {0x888, 0x00000000}, {0x88c, 0xccc000c0}, 85 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 86 {0x898, 0x40302010}, {0x89c, 0x00706050}, 87 {0x900, 0x00000000}, {0x904, 0x00000023}, 88 {0x908, 0x00000000}, {0x90c, 0x81121111}, 89 {0x910, 0x00000002}, {0x914, 0x00000201}, 90 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c}, 91 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f}, 92 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028}, 93 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 94 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 95 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 96 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 97 {0xa78, 0x00000900}, {0xa7c, 0x225b0606}, 98 {0xa80, 0x21806490}, {0xb2c, 0x00000000}, 99 {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, 100 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 101 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 102 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 103 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 104 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 105 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, 106 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 107 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 108 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 109 {0xc50, 0x69553420}, {0xc54, 0x43bc0094}, 110 {0xc58, 0x00013149}, {0xc5c, 0x00250492}, 111 {0xc60, 0x00000000}, {0xc64, 0x7112848b}, 112 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 113 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db}, 114 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, 115 {0xc80, 0x390000e4}, {0xc84, 0x20f60000}, 116 {0xc88, 0x40000100}, {0xc8c, 0x20200000}, 117 {0xc90, 0x00020e1a}, {0xc94, 0x00000000}, 118 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f}, 119 {0xca0, 0x00000000}, {0xca4, 0x000300a0}, 120 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 121 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 122 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 123 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 124 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 125 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 126 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 127 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 128 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 129 {0xd00, 0x00000740}, {0xd04, 0x40020401}, 130 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 131 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53}, 132 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975}, 133 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 134 {0xd38, 0x00000000}, {0xd3c, 0x00127353}, 135 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 136 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 137 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 138 {0xd58, 0x00000282}, {0xd5c, 0x30032064}, 139 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 140 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 141 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 142 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d}, 143 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d}, 144 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d}, 145 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d}, 146 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 147 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 148 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 149 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 150 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 151 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 152 {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, 153 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096}, 154 {0xe70, 0x00c00096}, {0xe74, 0x01000056}, 155 {0xe78, 0x01000014}, {0xe7c, 0x01000056}, 156 {0xe80, 0x01000014}, {0xe84, 0x00c00096}, 157 {0xe88, 0x01000056}, {0xe8c, 0x00c00096}, 158 {0xed0, 0x00c00096}, {0xed4, 0x00c00096}, 159 {0xed8, 0x00c00096}, {0xedc, 0x000000d6}, 160 {0xee0, 0x000000d6}, {0xeec, 0x01c00016}, 161 {0xf14, 0x00000003}, {0xf4c, 0x00000000}, 162 {0xf00, 0x00000300}, 163 {0x820, 0x01000100}, {0x800, 0x83040000}, 164 {0xffff, 0xffffffff}, 165 }; 166 167 static const struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = { 168 {0xc78, 0xfd000001}, {0xc78, 0xfc010001}, 169 {0xc78, 0xfb020001}, {0xc78, 0xfa030001}, 170 {0xc78, 0xf9040001}, {0xc78, 0xf8050001}, 171 {0xc78, 0xf7060001}, {0xc78, 0xf6070001}, 172 {0xc78, 0xf5080001}, {0xc78, 0xf4090001}, 173 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001}, 174 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001}, 175 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001}, 176 {0xc78, 0xed100001}, {0xc78, 0xec110001}, 177 {0xc78, 0xeb120001}, {0xc78, 0xea130001}, 178 {0xc78, 0xe9140001}, {0xc78, 0xe8150001}, 179 {0xc78, 0xe7160001}, {0xc78, 0xe6170001}, 180 {0xc78, 0xe5180001}, {0xc78, 0xe4190001}, 181 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001}, 182 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001}, 183 {0xc78, 0x671e0001}, {0xc78, 0x661f0001}, 184 {0xc78, 0x65200001}, {0xc78, 0x64210001}, 185 {0xc78, 0x63220001}, {0xc78, 0x4a230001}, 186 {0xc78, 0x49240001}, {0xc78, 0x48250001}, 187 {0xc78, 0x47260001}, {0xc78, 0x46270001}, 188 {0xc78, 0x45280001}, {0xc78, 0x44290001}, 189 {0xc78, 0x432a0001}, {0xc78, 0x422b0001}, 190 {0xc78, 0x292c0001}, {0xc78, 0x282d0001}, 191 {0xc78, 0x272e0001}, {0xc78, 0x262f0001}, 192 {0xc78, 0x0a300001}, {0xc78, 0x09310001}, 193 {0xc78, 0x08320001}, {0xc78, 0x07330001}, 194 {0xc78, 0x06340001}, {0xc78, 0x05350001}, 195 {0xc78, 0x04360001}, {0xc78, 0x03370001}, 196 {0xc78, 0x02380001}, {0xc78, 0x01390001}, 197 {0xc78, 0x013a0001}, {0xc78, 0x013b0001}, 198 {0xc78, 0x013c0001}, {0xc78, 0x013d0001}, 199 {0xc78, 0x013e0001}, {0xc78, 0x013f0001}, 200 {0xc78, 0xfc400001}, {0xc78, 0xfb410001}, 201 {0xc78, 0xfa420001}, {0xc78, 0xf9430001}, 202 {0xc78, 0xf8440001}, {0xc78, 0xf7450001}, 203 {0xc78, 0xf6460001}, {0xc78, 0xf5470001}, 204 {0xc78, 0xf4480001}, {0xc78, 0xf3490001}, 205 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001}, 206 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001}, 207 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001}, 208 {0xc78, 0xec500001}, {0xc78, 0xeb510001}, 209 {0xc78, 0xea520001}, {0xc78, 0xe9530001}, 210 {0xc78, 0xe8540001}, {0xc78, 0xe7550001}, 211 {0xc78, 0xe6560001}, {0xc78, 0xe5570001}, 212 {0xc78, 0xe4580001}, {0xc78, 0xe3590001}, 213 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001}, 214 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001}, 215 {0xc78, 0x675e0001}, {0xc78, 0x665f0001}, 216 {0xc78, 0x65600001}, {0xc78, 0x64610001}, 217 {0xc78, 0x63620001}, {0xc78, 0x62630001}, 218 {0xc78, 0x61640001}, {0xc78, 0x48650001}, 219 {0xc78, 0x47660001}, {0xc78, 0x46670001}, 220 {0xc78, 0x45680001}, {0xc78, 0x44690001}, 221 {0xc78, 0x436a0001}, {0xc78, 0x426b0001}, 222 {0xc78, 0x286c0001}, {0xc78, 0x276d0001}, 223 {0xc78, 0x266e0001}, {0xc78, 0x256f0001}, 224 {0xc78, 0x24700001}, {0xc78, 0x09710001}, 225 {0xc78, 0x08720001}, {0xc78, 0x07730001}, 226 {0xc78, 0x06740001}, {0xc78, 0x05750001}, 227 {0xc78, 0x04760001}, {0xc78, 0x03770001}, 228 {0xc78, 0x02780001}, {0xc78, 0x01790001}, 229 {0xc78, 0x017a0001}, {0xc78, 0x017b0001}, 230 {0xc78, 0x017c0001}, {0xc78, 0x017d0001}, 231 {0xc78, 0x017e0001}, {0xc78, 0x017f0001}, 232 {0xc50, 0x69553422}, 233 {0xc50, 0x69553420}, 234 {0x824, 0x00390204}, 235 {0xffff, 0xffffffff} 236 }; 237 238 static const struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = { 239 {0x00, 0x00010000}, {0xb0, 0x000dffe0}, 240 {0xfe, 0x00000000}, {0xfe, 0x00000000}, 241 {0xfe, 0x00000000}, {0xb1, 0x00000018}, 242 {0xfe, 0x00000000}, {0xfe, 0x00000000}, 243 {0xfe, 0x00000000}, {0xb2, 0x00084c00}, 244 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa}, 245 {0xb7, 0x00000010}, {0xb8, 0x0000907f}, 246 {0x5c, 0x00000002}, {0x7c, 0x00000002}, 247 {0x7e, 0x00000005}, {0x8b, 0x0006fc00}, 248 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2}, 249 {0x1e, 0x00000000}, {0xdf, 0x00000780}, 250 {0x50, 0x00067435}, 251 /* 252 * The 8723bu vendor driver indicates that bit 8 should be set in 253 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However 254 * they never actually check the package type - and just default 255 * to not setting it. 256 */ 257 {0x51, 0x0006b04e}, 258 {0x52, 0x000007d2}, {0x53, 0x00000000}, 259 {0x54, 0x00050400}, {0x55, 0x0004026e}, 260 {0xdd, 0x0000004c}, {0x70, 0x00067435}, 261 /* 262 * 0x71 has same package type condition as for register 0x51 263 */ 264 {0x71, 0x0006b04e}, 265 {0x72, 0x000007d2}, {0x73, 0x00000000}, 266 {0x74, 0x00050400}, {0x75, 0x0004026e}, 267 {0xef, 0x00000100}, {0x34, 0x0000add7}, 268 {0x35, 0x00005c00}, {0x34, 0x00009dd4}, 269 {0x35, 0x00005000}, {0x34, 0x00008dd1}, 270 {0x35, 0x00004400}, {0x34, 0x00007dce}, 271 {0x35, 0x00003800}, {0x34, 0x00006cd1}, 272 {0x35, 0x00004400}, {0x34, 0x00005cce}, 273 {0x35, 0x00003800}, {0x34, 0x000048ce}, 274 {0x35, 0x00004400}, {0x34, 0x000034ce}, 275 {0x35, 0x00003800}, {0x34, 0x00002451}, 276 {0x35, 0x00004400}, {0x34, 0x0000144e}, 277 {0x35, 0x00003800}, {0x34, 0x00000051}, 278 {0x35, 0x00004400}, {0xef, 0x00000000}, 279 {0xef, 0x00000100}, {0xed, 0x00000010}, 280 {0x44, 0x0000add7}, {0x44, 0x00009dd4}, 281 {0x44, 0x00008dd1}, {0x44, 0x00007dce}, 282 {0x44, 0x00006cc1}, {0x44, 0x00005cce}, 283 {0x44, 0x000044d1}, {0x44, 0x000034ce}, 284 {0x44, 0x00002451}, {0x44, 0x0000144e}, 285 {0x44, 0x00000051}, {0xef, 0x00000000}, 286 {0xed, 0x00000000}, {0x7f, 0x00020080}, 287 {0xef, 0x00002000}, {0x3b, 0x000380ef}, 288 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6}, 289 {0x3b, 0x000200bc}, {0x3b, 0x000188a5}, 290 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71}, 291 {0x3b, 0x00000900}, {0xef, 0x00000000}, 292 {0xed, 0x00000001}, {0x40, 0x000380ef}, 293 {0x40, 0x000302fe}, {0x40, 0x00028ce6}, 294 {0x40, 0x000200bc}, {0x40, 0x000188a5}, 295 {0x40, 0x00010fbc}, {0x40, 0x00008f71}, 296 {0x40, 0x00000900}, {0xed, 0x00000000}, 297 {0x82, 0x00080000}, {0x83, 0x00008000}, 298 {0x84, 0x00048d80}, {0x85, 0x00068000}, 299 {0xa2, 0x00080000}, {0xa3, 0x00008000}, 300 {0xa4, 0x00048d80}, {0xa5, 0x00068000}, 301 {0xed, 0x00000002}, {0xef, 0x00000002}, 302 {0x56, 0x00000032}, {0x76, 0x00000032}, 303 {0x01, 0x00000780}, 304 {0xff, 0xffffffff} 305 }; 306 307 static int rtl8723bu_identify_chip(struct rtl8xxxu_priv *priv) 308 { 309 struct device *dev = &priv->udev->dev; 310 u32 val32, sys_cfg, vendor; 311 int ret = 0; 312 313 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); 314 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); 315 if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { 316 dev_info(dev, "Unsupported test chip\n"); 317 ret = -ENOTSUPP; 318 goto out; 319 } 320 321 strscpy(priv->chip_name, "8723BU", sizeof(priv->chip_name)); 322 priv->rtl_chip = RTL8723B; 323 priv->rf_paths = 1; 324 priv->rx_paths = 1; 325 priv->tx_paths = 1; 326 327 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); 328 if (val32 & MULTI_WIFI_FUNC_EN) 329 priv->has_wifi = 1; 330 if (val32 & MULTI_BT_FUNC_EN) 331 priv->has_bluetooth = 1; 332 if (val32 & MULTI_GPS_FUNC_EN) 333 priv->has_gps = 1; 334 priv->is_multi_func = 1; 335 336 vendor = sys_cfg & SYS_CFG_VENDOR_EXT_MASK; 337 rtl8xxxu_identify_vendor_2bits(priv, vendor); 338 339 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); 340 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); 341 342 rtl8xxxu_config_endpoints_sie(priv); 343 344 /* 345 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX 346 */ 347 if (!priv->ep_tx_count) 348 ret = rtl8xxxu_config_endpoints_no_sie(priv); 349 350 out: 351 return ret; 352 } 353 354 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data) 355 { 356 struct h2c_cmd h2c; 357 int reqnum = 0; 358 359 memset(&h2c, 0, sizeof(struct h2c_cmd)); 360 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER; 361 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4); 362 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE; 363 h2c.bt_mp_oper.data = data; 364 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); 365 366 reqnum++; 367 memset(&h2c, 0, sizeof(struct h2c_cmd)); 368 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER; 369 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4); 370 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE; 371 h2c.bt_mp_oper.addr = reg; 372 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); 373 } 374 375 static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv) 376 { 377 u8 val8; 378 u16 sys_func; 379 380 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); 381 val8 &= ~BIT(1); 382 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); 383 384 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 385 val8 &= ~BIT(0); 386 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 387 388 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); 389 sys_func &= ~SYS_FUNC_CPU_ENABLE; 390 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 391 392 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); 393 val8 &= ~BIT(1); 394 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); 395 396 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 397 val8 |= BIT(0); 398 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 399 400 sys_func |= SYS_FUNC_CPU_ENABLE; 401 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 402 } 403 404 static void 405 rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) 406 { 407 u32 val32, ofdm, mcs; 408 u8 cck, ofdmbase, mcsbase; 409 int group, tx_idx; 410 411 tx_idx = 0; 412 group = rtl8xxxu_gen2_channel_to_group(channel); 413 414 cck = priv->cck_tx_power_index_B[group]; 415 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); 416 val32 &= 0xffff00ff; 417 val32 |= (cck << 8); 418 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); 419 420 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 421 val32 &= 0xff; 422 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); 423 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 424 425 ofdmbase = priv->ht40_1s_tx_power_index_B[group]; 426 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; 427 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; 428 429 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); 430 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); 431 432 mcsbase = priv->ht40_1s_tx_power_index_B[group]; 433 if (ht40) 434 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; 435 else 436 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; 437 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; 438 439 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); 440 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); 441 } 442 443 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv) 444 { 445 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu; 446 int i; 447 448 if (efuse->rtl_id != cpu_to_le16(0x8129)) 449 return -EINVAL; 450 451 ether_addr_copy(priv->mac_addr, efuse->mac_addr); 452 453 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, 454 sizeof(efuse->tx_power_index_A.cck_base)); 455 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, 456 sizeof(efuse->tx_power_index_B.cck_base)); 457 458 memcpy(priv->ht40_1s_tx_power_index_A, 459 efuse->tx_power_index_A.ht40_base, 460 sizeof(efuse->tx_power_index_A.ht40_base)); 461 memcpy(priv->ht40_1s_tx_power_index_B, 462 efuse->tx_power_index_B.ht40_base, 463 sizeof(efuse->tx_power_index_B.ht40_base)); 464 465 priv->ofdm_tx_power_diff[0].a = 466 efuse->tx_power_index_A.ht20_ofdm_1s_diff.a; 467 priv->ofdm_tx_power_diff[0].b = 468 efuse->tx_power_index_B.ht20_ofdm_1s_diff.a; 469 470 priv->ht20_tx_power_diff[0].a = 471 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; 472 priv->ht20_tx_power_diff[0].b = 473 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b; 474 475 priv->ht40_tx_power_diff[0].a = 0; 476 priv->ht40_tx_power_diff[0].b = 0; 477 478 for (i = 1; i < RTL8723B_TX_COUNT; i++) { 479 priv->ofdm_tx_power_diff[i].a = 480 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm; 481 priv->ofdm_tx_power_diff[i].b = 482 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm; 483 484 priv->ht20_tx_power_diff[i].a = 485 efuse->tx_power_index_A.pwr_diff[i - 1].ht20; 486 priv->ht20_tx_power_diff[i].b = 487 efuse->tx_power_index_B.pwr_diff[i - 1].ht20; 488 489 priv->ht40_tx_power_diff[i].a = 490 efuse->tx_power_index_A.pwr_diff[i - 1].ht40; 491 priv->ht40_tx_power_diff[i].b = 492 efuse->tx_power_index_B.pwr_diff[i - 1].ht40; 493 } 494 495 priv->default_crystal_cap = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f; 496 497 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name); 498 dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name); 499 500 return 0; 501 } 502 503 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv) 504 { 505 const char *fw_name; 506 int ret; 507 508 if (priv->enable_bluetooth) 509 fw_name = "rtlwifi/rtl8723bu_bt.bin"; 510 else 511 fw_name = "rtlwifi/rtl8723bu_nic.bin"; 512 513 ret = rtl8xxxu_load_firmware(priv, fw_name); 514 return ret; 515 } 516 517 static void rtl8723bu_init_phy_bb(struct rtl8xxxu_priv *priv) 518 { 519 u8 val8; 520 u16 val16; 521 522 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 523 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; 524 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 525 526 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); 527 528 /* 6. 0x1f[7:0] = 0x07 */ 529 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; 530 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 531 532 /* Why? */ 533 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3); 534 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80); 535 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table); 536 537 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table); 538 } 539 540 static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv) 541 { 542 int ret; 543 544 ret = rtl8xxxu_init_phy_rf(priv, rtl8723bu_radioa_1t_init_table, RF_A); 545 /* 546 * PHY LCK 547 */ 548 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0); 549 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01); 550 msleep(200); 551 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0); 552 553 return ret; 554 } 555 556 void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv) 557 { 558 u32 val32; 559 560 val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1); 561 val32 &= ~(BIT(20) | BIT(24)); 562 rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32); 563 564 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); 565 val32 &= ~BIT(4); 566 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); 567 568 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); 569 val32 |= BIT(3); 570 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); 571 572 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); 573 val32 |= BIT(24); 574 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); 575 576 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); 577 val32 &= ~BIT(23); 578 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); 579 580 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); 581 val32 |= (BIT(0) | BIT(1)); 582 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); 583 584 val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC); 585 val32 &= 0xffffff00; 586 val32 |= 0x77; 587 rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32); 588 589 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); 590 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; 591 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); 592 } 593 594 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv) 595 { 596 u32 reg_eac, reg_e94, reg_e9c, path_sel, val32; 597 int result = 0; 598 599 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); 600 601 /* 602 * Leave IQK mode 603 */ 604 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 605 val32 &= 0x000000ff; 606 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 607 608 /* 609 * Enable path A PA in TX IQK mode 610 */ 611 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 612 val32 |= 0x80000; 613 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 614 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); 615 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f); 616 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87); 617 618 /* 619 * Tx IQK setting 620 */ 621 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 622 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 623 624 /* path-A IQK setting */ 625 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); 626 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 627 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); 628 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); 629 630 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea); 631 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); 632 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); 633 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); 634 635 /* LO calibration setting */ 636 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); 637 638 /* 639 * Enter IQK mode 640 */ 641 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 642 val32 &= 0x000000ff; 643 val32 |= 0x80800000; 644 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 645 646 /* 647 * The vendor driver indicates the USB module is always using 648 * S0S1 path 1 for the 8723bu. This may be different for 8192eu 649 */ 650 if (priv->rf_paths > 1) 651 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); 652 else 653 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); 654 655 /* 656 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu. 657 * No trace of this in the 8192eu or 8188eu vendor drivers. 658 */ 659 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); 660 661 /* One shot, path A LOK & IQK */ 662 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 663 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 664 665 mdelay(1); 666 667 /* Restore Ant Path */ 668 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); 669 #ifdef RTL8723BU_BT 670 /* GNT_BT = 1 */ 671 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); 672 #endif 673 674 /* 675 * Leave IQK mode 676 */ 677 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 678 val32 &= 0x000000ff; 679 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 680 681 /* Check failed */ 682 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 683 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 684 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 685 686 val32 = (reg_e9c >> 16) & 0x3ff; 687 if (val32 & 0x200) 688 val32 = 0x400 - val32; 689 690 if (!(reg_eac & BIT(28)) && 691 ((reg_e94 & 0x03ff0000) != 0x01420000) && 692 ((reg_e9c & 0x03ff0000) != 0x00420000) && 693 ((reg_e94 & 0x03ff0000) < 0x01100000) && 694 ((reg_e94 & 0x03ff0000) > 0x00f00000) && 695 val32 < 0xf) 696 result |= 0x01; 697 else /* If TX not OK, ignore RX */ 698 goto out; 699 700 out: 701 return result; 702 } 703 704 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) 705 { 706 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32; 707 int result = 0; 708 709 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); 710 711 /* 712 * Leave IQK mode 713 */ 714 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 715 val32 &= 0x000000ff; 716 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 717 718 /* 719 * Enable path A PA in TX IQK mode 720 */ 721 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 722 val32 |= 0x80000; 723 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 724 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 725 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); 726 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); 727 728 /* 729 * Tx IQK setting 730 */ 731 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 732 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 733 734 /* path-A IQK setting */ 735 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); 736 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 737 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); 738 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); 739 740 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0); 741 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); 742 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); 743 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); 744 745 /* LO calibration setting */ 746 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); 747 748 /* 749 * Enter IQK mode 750 */ 751 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 752 val32 &= 0x000000ff; 753 val32 |= 0x80800000; 754 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 755 756 /* 757 * The vendor driver indicates the USB module is always using 758 * S0S1 path 1 for the 8723bu. This may be different for 8192eu 759 */ 760 if (priv->rf_paths > 1) 761 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); 762 else 763 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); 764 765 /* 766 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu. 767 * No trace of this in the 8192eu or 8188eu vendor drivers. 768 */ 769 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); 770 771 /* One shot, path A LOK & IQK */ 772 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 773 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 774 775 mdelay(1); 776 777 /* Restore Ant Path */ 778 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); 779 #ifdef RTL8723BU_BT 780 /* GNT_BT = 1 */ 781 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); 782 #endif 783 784 /* 785 * Leave IQK mode 786 */ 787 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 788 val32 &= 0x000000ff; 789 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 790 791 /* Check failed */ 792 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 793 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 794 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 795 796 val32 = (reg_e9c >> 16) & 0x3ff; 797 if (val32 & 0x200) 798 val32 = 0x400 - val32; 799 800 if (!(reg_eac & BIT(28)) && 801 ((reg_e94 & 0x03ff0000) != 0x01420000) && 802 ((reg_e9c & 0x03ff0000) != 0x00420000) && 803 ((reg_e94 & 0x03ff0000) < 0x01100000) && 804 ((reg_e94 & 0x03ff0000) > 0x00f00000) && 805 val32 < 0xf) 806 result |= 0x01; 807 else /* If TX not OK, ignore RX */ 808 goto out; 809 810 val32 = 0x80007c00 | (reg_e94 &0x3ff0000) | 811 ((reg_e9c & 0x3ff0000) >> 16); 812 rtl8xxxu_write32(priv, REG_TX_IQK, val32); 813 814 /* 815 * Modify RX IQK mode 816 */ 817 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 818 val32 &= 0x000000ff; 819 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 820 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 821 val32 |= 0x80000; 822 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 823 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 824 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); 825 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77); 826 827 /* 828 * PA, PAD setting 829 */ 830 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80); 831 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f); 832 833 /* 834 * RX IQK setting 835 */ 836 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 837 838 /* path-A IQK setting */ 839 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); 840 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); 841 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); 842 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); 843 844 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000); 845 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f); 846 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); 847 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); 848 849 /* LO calibration setting */ 850 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1); 851 852 /* 853 * Enter IQK mode 854 */ 855 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 856 val32 &= 0x000000ff; 857 val32 |= 0x80800000; 858 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 859 860 if (priv->rf_paths > 1) 861 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); 862 else 863 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); 864 865 /* 866 * Disable BT 867 */ 868 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); 869 870 /* One shot, path A LOK & IQK */ 871 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 872 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 873 874 mdelay(1); 875 876 /* Restore Ant Path */ 877 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); 878 #ifdef RTL8723BU_BT 879 /* GNT_BT = 1 */ 880 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); 881 #endif 882 883 /* 884 * Leave IQK mode 885 */ 886 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 887 val32 &= 0x000000ff; 888 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 889 890 /* Check failed */ 891 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 892 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 893 894 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780); 895 896 val32 = (reg_eac >> 16) & 0x3ff; 897 if (val32 & 0x200) 898 val32 = 0x400 - val32; 899 900 if (!(reg_eac & BIT(27)) && 901 ((reg_ea4 & 0x03ff0000) != 0x01320000) && 902 ((reg_eac & 0x03ff0000) != 0x00360000) && 903 ((reg_ea4 & 0x03ff0000) < 0x01100000) && 904 ((reg_ea4 & 0x03ff0000) > 0x00f00000) && 905 val32 < 0xf) 906 result |= 0x02; 907 else /* If TX not OK, ignore RX */ 908 goto out; 909 out: 910 return result; 911 } 912 913 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, 914 int result[][8], int t) 915 { 916 struct device *dev = &priv->udev->dev; 917 u32 i, val32; 918 int path_a_ok /*, path_b_ok */; 919 int retry = 2; 920 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { 921 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, 922 REG_RX_WAIT_CCA, REG_TX_CCK_RFON, 923 REG_TX_CCK_BBON, REG_TX_OFDM_RFON, 924 REG_TX_OFDM_BBON, REG_TX_TO_RX, 925 REG_TX_TO_TX, REG_RX_CCK, 926 REG_RX_OFDM, REG_RX_WAIT_RIFS, 927 REG_RX_TO_RX, REG_STANDBY, 928 REG_SLEEP, REG_PMPD_ANAEN 929 }; 930 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { 931 REG_TXPAUSE, REG_BEACON_CTRL, 932 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG 933 }; 934 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { 935 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, 936 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, 937 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, 938 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE 939 }; 940 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; 941 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; 942 943 /* 944 * Note: IQ calibration must be performed after loading 945 * PHY_REG.txt , and radio_a, radio_b.txt 946 */ 947 948 if (t == 0) { 949 /* Save ADDA parameters, turn Path A ADDA on */ 950 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, 951 RTL8XXXU_ADDA_REGS); 952 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 953 rtl8xxxu_save_regs(priv, iqk_bb_regs, 954 priv->bb_backup, RTL8XXXU_BB_REGS); 955 } 956 957 rtl8xxxu_path_adda_on(priv, adda_regs, true); 958 959 /* MAC settings */ 960 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); 961 962 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); 963 val32 |= 0x0f000000; 964 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); 965 966 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); 967 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); 968 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); 969 970 /* 971 * RX IQ calibration setting for 8723B D cut large current issue 972 * when leaving IPS 973 */ 974 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 975 val32 &= 0x000000ff; 976 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 977 978 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 979 val32 |= 0x80000; 980 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 981 982 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 983 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); 984 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); 985 986 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); 987 val32 |= 0x20; 988 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); 989 990 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd); 991 992 for (i = 0; i < retry; i++) { 993 path_a_ok = rtl8723bu_iqk_path_a(priv); 994 if (path_a_ok == 0x01) { 995 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 996 val32 &= 0x000000ff; 997 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 998 999 val32 = rtl8xxxu_read32(priv, 1000 REG_TX_POWER_BEFORE_IQK_A); 1001 result[t][0] = (val32 >> 16) & 0x3ff; 1002 val32 = rtl8xxxu_read32(priv, 1003 REG_TX_POWER_AFTER_IQK_A); 1004 result[t][1] = (val32 >> 16) & 0x3ff; 1005 1006 break; 1007 } 1008 } 1009 1010 if (!path_a_ok) 1011 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__); 1012 1013 for (i = 0; i < retry; i++) { 1014 path_a_ok = rtl8723bu_rx_iqk_path_a(priv); 1015 if (path_a_ok == 0x03) { 1016 val32 = rtl8xxxu_read32(priv, 1017 REG_RX_POWER_BEFORE_IQK_A_2); 1018 result[t][2] = (val32 >> 16) & 0x3ff; 1019 val32 = rtl8xxxu_read32(priv, 1020 REG_RX_POWER_AFTER_IQK_A_2); 1021 result[t][3] = (val32 >> 16) & 0x3ff; 1022 1023 break; 1024 } 1025 } 1026 1027 if (!path_a_ok) 1028 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__); 1029 1030 if (priv->tx_paths > 1) { 1031 #if 1 1032 dev_warn(dev, "%s: Path B not supported\n", __func__); 1033 #else 1034 1035 /* 1036 * Path A into standby 1037 */ 1038 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1039 val32 &= 0x000000ff; 1040 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1041 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); 1042 1043 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1044 val32 &= 0x000000ff; 1045 val32 |= 0x80800000; 1046 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1047 1048 /* Turn Path B ADDA on */ 1049 rtl8xxxu_path_adda_on(priv, adda_regs, false); 1050 1051 for (i = 0; i < retry; i++) { 1052 path_b_ok = rtl8xxxu_iqk_path_b(priv); 1053 if (path_b_ok == 0x03) { 1054 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 1055 result[t][4] = (val32 >> 16) & 0x3ff; 1056 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 1057 result[t][5] = (val32 >> 16) & 0x3ff; 1058 break; 1059 } 1060 } 1061 1062 if (!path_b_ok) 1063 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); 1064 1065 for (i = 0; i < retry; i++) { 1066 path_b_ok = rtl8723bu_rx_iqk_path_b(priv); 1067 if (path_a_ok == 0x03) { 1068 val32 = rtl8xxxu_read32(priv, 1069 REG_RX_POWER_BEFORE_IQK_B_2); 1070 result[t][6] = (val32 >> 16) & 0x3ff; 1071 val32 = rtl8xxxu_read32(priv, 1072 REG_RX_POWER_AFTER_IQK_B_2); 1073 result[t][7] = (val32 >> 16) & 0x3ff; 1074 break; 1075 } 1076 } 1077 1078 if (!path_b_ok) 1079 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__); 1080 #endif 1081 } 1082 1083 /* Back to BB mode, load original value */ 1084 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1085 val32 &= 0x000000ff; 1086 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1087 1088 if (t) { 1089 /* Reload ADDA power saving parameters */ 1090 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, 1091 RTL8XXXU_ADDA_REGS); 1092 1093 /* Reload MAC parameters */ 1094 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 1095 1096 /* Reload BB parameters */ 1097 rtl8xxxu_restore_regs(priv, iqk_bb_regs, 1098 priv->bb_backup, RTL8XXXU_BB_REGS); 1099 1100 /* Restore RX initial gain */ 1101 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 1102 val32 &= 0xffffff00; 1103 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); 1104 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); 1105 1106 if (priv->tx_paths > 1) { 1107 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); 1108 val32 &= 0xffffff00; 1109 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, 1110 val32 | 0x50); 1111 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, 1112 val32 | xb_agc); 1113 } 1114 1115 /* Load 0xe30 IQC default value */ 1116 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); 1117 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); 1118 } 1119 } 1120 1121 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) 1122 { 1123 struct device *dev = &priv->udev->dev; 1124 int result[4][8]; /* last is final result */ 1125 int i, candidate; 1126 bool path_a_ok, path_b_ok; 1127 u32 reg_e94, reg_e9c, reg_ea4, reg_eac; 1128 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; 1129 u32 val32, bt_control; 1130 s32 reg_tmp = 0; 1131 bool simu; 1132 1133 rtl8xxxu_gen2_prepare_calibrate(priv, 1); 1134 1135 memset(result, 0, sizeof(result)); 1136 candidate = -1; 1137 1138 path_a_ok = false; 1139 path_b_ok = false; 1140 1141 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU); 1142 1143 for (i = 0; i < 3; i++) { 1144 rtl8723bu_phy_iqcalibrate(priv, result, i); 1145 1146 if (i == 1) { 1147 simu = rtl8xxxu_gen2_simularity_compare(priv, 1148 result, 0, 1); 1149 if (simu) { 1150 candidate = 0; 1151 break; 1152 } 1153 } 1154 1155 if (i == 2) { 1156 simu = rtl8xxxu_gen2_simularity_compare(priv, 1157 result, 0, 2); 1158 if (simu) { 1159 candidate = 0; 1160 break; 1161 } 1162 1163 simu = rtl8xxxu_gen2_simularity_compare(priv, 1164 result, 1, 2); 1165 if (simu) { 1166 candidate = 1; 1167 } else { 1168 for (i = 0; i < 8; i++) 1169 reg_tmp += result[3][i]; 1170 1171 if (reg_tmp) 1172 candidate = 3; 1173 else 1174 candidate = -1; 1175 } 1176 } 1177 } 1178 1179 for (i = 0; i < 4; i++) { 1180 reg_e94 = result[i][0]; 1181 reg_e9c = result[i][1]; 1182 reg_ea4 = result[i][2]; 1183 reg_eac = result[i][3]; 1184 reg_eb4 = result[i][4]; 1185 reg_ebc = result[i][5]; 1186 reg_ec4 = result[i][6]; 1187 reg_ecc = result[i][7]; 1188 } 1189 1190 if (candidate >= 0) { 1191 reg_e94 = result[candidate][0]; 1192 priv->rege94 = reg_e94; 1193 reg_e9c = result[candidate][1]; 1194 priv->rege9c = reg_e9c; 1195 reg_ea4 = result[candidate][2]; 1196 reg_eac = result[candidate][3]; 1197 reg_eb4 = result[candidate][4]; 1198 priv->regeb4 = reg_eb4; 1199 reg_ebc = result[candidate][5]; 1200 priv->regebc = reg_ebc; 1201 reg_ec4 = result[candidate][6]; 1202 reg_ecc = result[candidate][7]; 1203 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); 1204 dev_dbg(dev, 1205 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", 1206 __func__, reg_e94, reg_e9c, 1207 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); 1208 path_a_ok = true; 1209 path_b_ok = true; 1210 } else { 1211 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; 1212 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; 1213 } 1214 1215 if (reg_e94 && candidate >= 0) 1216 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, 1217 candidate, (reg_ea4 == 0)); 1218 1219 if (priv->tx_paths > 1 && reg_eb4) 1220 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, 1221 candidate, (reg_ec4 == 0)); 1222 1223 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, 1224 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); 1225 1226 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control); 1227 1228 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 1229 val32 |= 0x80000; 1230 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 1231 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000); 1232 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); 1233 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177); 1234 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); 1235 val32 |= 0x20; 1236 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); 1237 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd); 1238 1239 if (priv->rf_paths > 1) 1240 dev_dbg(dev, "%s: 8723BU 2T not supported\n", __func__); 1241 1242 rtl8xxxu_gen2_prepare_calibrate(priv, 0); 1243 } 1244 1245 static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv) 1246 { 1247 u8 val8; 1248 u16 val16; 1249 u32 val32; 1250 int count, ret = 0; 1251 1252 /* Turn off RF */ 1253 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); 1254 1255 /* Enable rising edge triggering interrupt */ 1256 val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM); 1257 val16 &= ~GPIO_INTM_EDGE_TRIG_IRQ; 1258 rtl8xxxu_write16(priv, REG_GPIO_INTM, val16); 1259 1260 /* Release WLON reset 0x04[16]= 1*/ 1261 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1262 val32 |= APS_FSMCO_WLON_RESET; 1263 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); 1264 1265 /* 0x0005[1] = 1 turn off MAC by HW state machine*/ 1266 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1267 val8 |= BIT(1); 1268 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1269 1270 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1271 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1272 if ((val8 & BIT(1)) == 0) 1273 break; 1274 udelay(10); 1275 } 1276 1277 if (!count) { 1278 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", 1279 __func__); 1280 ret = -EBUSY; 1281 goto exit; 1282 } 1283 1284 /* Enable BT control XTAL setting */ 1285 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); 1286 val8 &= ~AFE_MISC_WL_XTAL_CTRL; 1287 rtl8xxxu_write8(priv, REG_AFE_MISC, val8); 1288 1289 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ 1290 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); 1291 val8 |= SYS_ISO_ANALOG_IPS; 1292 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); 1293 1294 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ 1295 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); 1296 val8 &= ~LDOA15_ENABLE; 1297 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); 1298 1299 exit: 1300 return ret; 1301 } 1302 1303 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv) 1304 { 1305 u8 val8; 1306 u32 val32; 1307 int count, ret = 0; 1308 1309 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */ 1310 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); 1311 val8 |= LDOA15_ENABLE; 1312 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); 1313 1314 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/ 1315 val8 = rtl8xxxu_read8(priv, 0x0067); 1316 val8 &= ~BIT(4); 1317 rtl8xxxu_write8(priv, 0x0067, val8); 1318 1319 mdelay(1); 1320 1321 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */ 1322 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); 1323 val8 &= ~SYS_ISO_ANALOG_IPS; 1324 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); 1325 1326 /* Disable SW LPS 0x04[10]= 0 */ 1327 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO); 1328 val32 &= ~APS_FSMCO_SW_LPS; 1329 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); 1330 1331 /* Wait until 0x04[17] = 1 power ready */ 1332 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1333 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1334 if (val32 & BIT(17)) 1335 break; 1336 1337 udelay(10); 1338 } 1339 1340 if (!count) { 1341 ret = -EBUSY; 1342 goto exit; 1343 } 1344 1345 /* We should be able to optimize the following three entries into one */ 1346 1347 /* Release WLON reset 0x04[16]= 1*/ 1348 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1349 val32 |= APS_FSMCO_WLON_RESET; 1350 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); 1351 1352 /* Disable HWPDN 0x04[15]= 0*/ 1353 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1354 val32 &= ~APS_FSMCO_HW_POWERDOWN; 1355 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); 1356 1357 /* Disable WL suspend*/ 1358 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1359 val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE); 1360 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); 1361 1362 /* Set, then poll until 0 */ 1363 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1364 val32 |= APS_FSMCO_MAC_ENABLE; 1365 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); 1366 1367 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1368 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1369 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { 1370 ret = 0; 1371 break; 1372 } 1373 udelay(10); 1374 } 1375 1376 if (!count) { 1377 ret = -EBUSY; 1378 goto exit; 1379 } 1380 1381 /* Enable WL control XTAL setting */ 1382 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); 1383 val8 |= AFE_MISC_WL_XTAL_CTRL; 1384 rtl8xxxu_write8(priv, REG_AFE_MISC, val8); 1385 1386 /* Enable falling edge triggering interrupt */ 1387 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1); 1388 val8 |= BIT(1); 1389 rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8); 1390 1391 /* Enable GPIO9 interrupt mode */ 1392 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1); 1393 val8 |= BIT(1); 1394 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8); 1395 1396 /* Enable GPIO9 input mode */ 1397 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2); 1398 val8 &= ~BIT(1); 1399 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8); 1400 1401 /* Enable HSISR GPIO[C:0] interrupt */ 1402 val8 = rtl8xxxu_read8(priv, REG_HSIMR); 1403 val8 |= BIT(0); 1404 rtl8xxxu_write8(priv, REG_HSIMR, val8); 1405 1406 /* Enable HSISR GPIO9 interrupt */ 1407 val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2); 1408 val8 |= BIT(1); 1409 rtl8xxxu_write8(priv, REG_HSIMR + 2, val8); 1410 1411 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL); 1412 val8 |= MULTI_WIFI_HW_ROF_EN; 1413 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8); 1414 1415 /* For GPIO9 internal pull high setting BIT(14) */ 1416 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1); 1417 val8 |= BIT(6); 1418 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8); 1419 1420 exit: 1421 return ret; 1422 } 1423 1424 static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv) 1425 { 1426 u8 val8; 1427 u16 val16; 1428 u32 val32; 1429 int ret; 1430 1431 rtl8xxxu_disabled_to_emu(priv); 1432 1433 ret = rtl8723b_emu_to_active(priv); 1434 if (ret) 1435 goto exit; 1436 1437 /* 1438 * Enable MAC DMA/WMAC/SCHEDULE/SEC block 1439 * Set CR bit10 to enable 32k calibration. 1440 */ 1441 val16 = rtl8xxxu_read16(priv, REG_CR); 1442 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | 1443 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | 1444 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | 1445 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | 1446 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); 1447 rtl8xxxu_write16(priv, REG_CR, val16); 1448 1449 /* 1450 * BT coexist power on settings. This is identical for 1 and 2 1451 * antenna parts. 1452 */ 1453 rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20); 1454 1455 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1456 val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN; 1457 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1458 1459 rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18); 1460 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); 1461 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); 1462 /* Antenna inverse */ 1463 rtl8xxxu_write8(priv, 0xfe08, 0x01); 1464 1465 val16 = rtl8xxxu_read16(priv, REG_PWR_DATA); 1466 val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; 1467 rtl8xxxu_write16(priv, REG_PWR_DATA, val16); 1468 1469 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); 1470 val32 |= LEDCFG0_DPDT_SELECT; 1471 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); 1472 1473 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); 1474 val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA; 1475 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); 1476 exit: 1477 return ret; 1478 } 1479 1480 static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv) 1481 { 1482 u8 val8; 1483 u16 val16; 1484 1485 rtl8xxxu_flush_fifo(priv); 1486 1487 /* 1488 * Disable TX report timer 1489 */ 1490 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); 1491 val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; 1492 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); 1493 1494 rtl8xxxu_write8(priv, REG_CR, 0x0000); 1495 1496 rtl8xxxu_active_to_lps(priv); 1497 1498 /* Reset Firmware if running in RAM */ 1499 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) 1500 rtl8xxxu_firmware_self_reset(priv); 1501 1502 /* Reset MCU */ 1503 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1504 val16 &= ~SYS_FUNC_CPU_ENABLE; 1505 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1506 1507 /* Reset MCU ready status */ 1508 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 1509 1510 rtl8723bu_active_to_emu(priv); 1511 1512 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1513 val8 |= BIT(3); /* APS_FSMCO_HW_SUSPEND */ 1514 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1515 1516 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */ 1517 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); 1518 val8 |= BIT(0); 1519 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); 1520 } 1521 1522 static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv) 1523 { 1524 struct h2c_cmd h2c; 1525 u32 val32; 1526 u8 val8; 1527 1528 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); 1529 val32 |= (BIT(22) | BIT(23)); 1530 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); 1531 1532 /* 1533 * No indication anywhere as to what 0x0790 does. The 2 antenna 1534 * vendor code preserves bits 6-7 here. 1535 */ 1536 rtl8xxxu_write8(priv, 0x0790, 0x05); 1537 /* 1538 * 0x0778 seems to be related to enabling the number of antennas 1539 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it 1540 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01 1541 */ 1542 rtl8xxxu_write8(priv, 0x0778, 0x01); 1543 1544 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); 1545 val8 |= BIT(5); 1546 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); 1547 1548 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); 1549 1550 rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */ 1551 1552 /* 1553 * Set BT grant to low 1554 */ 1555 memset(&h2c, 0, sizeof(struct h2c_cmd)); 1556 h2c.bt_grant.cmd = H2C_8723B_BT_GRANT; 1557 h2c.bt_grant.data = 0; 1558 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant)); 1559 1560 /* 1561 * WLAN action by PTA 1562 */ 1563 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x0c); 1564 1565 /* 1566 * BT select S0/S1 controlled by WiFi 1567 */ 1568 val8 = rtl8xxxu_read8(priv, 0x0067); 1569 val8 |= BIT(5); 1570 rtl8xxxu_write8(priv, 0x0067, val8); 1571 1572 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); 1573 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; 1574 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); 1575 1576 /* 1577 * Bits 6/7 are marked in/out ... but for what? 1578 */ 1579 rtl8xxxu_write8(priv, 0x0974, 0xff); 1580 1581 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); 1582 val32 |= (BIT(0) | BIT(1)); 1583 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); 1584 1585 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77); 1586 1587 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); 1588 val32 &= ~BIT(24); 1589 val32 |= BIT(23); 1590 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); 1591 1592 /* 1593 * Fix external switch Main->S1, Aux->S0 1594 */ 1595 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); 1596 val8 &= ~BIT(0); 1597 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); 1598 1599 memset(&h2c, 0, sizeof(struct h2c_cmd)); 1600 h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV; 1601 h2c.ant_sel_rsv.ant_inverse = 1; 1602 h2c.ant_sel_rsv.int_switch_type = 0; 1603 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv)); 1604 1605 /* 1606 * Different settings per different antenna position. 1607 * Antenna Position: | Normal Inverse 1608 * -------------------------------------------------- 1609 * Antenna switch to BT: | 0x280, 0x00 1610 * Antenna switch to WiFi: | 0x0, 0x280 1611 * Antenna switch to PTA: | 0x200, 0x80 1612 */ 1613 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x80); 1614 1615 /* 1616 * Software control, antenna at WiFi side 1617 */ 1618 rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00); 1619 1620 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); 1621 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); 1622 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); 1623 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); 1624 1625 memset(&h2c, 0, sizeof(struct h2c_cmd)); 1626 h2c.bt_info.cmd = H2C_8723B_BT_INFO; 1627 h2c.bt_info.data = BIT(0); 1628 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info)); 1629 1630 memset(&h2c, 0, sizeof(struct h2c_cmd)); 1631 h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT; 1632 h2c.ignore_wlan.data = 0; 1633 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan)); 1634 } 1635 1636 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv) 1637 { 1638 u32 agg_rx; 1639 u8 agg_ctrl; 1640 1641 /* 1642 * For now simply disable RX aggregation 1643 */ 1644 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); 1645 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; 1646 1647 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); 1648 agg_rx &= ~RXDMA_USB_AGG_ENABLE; 1649 agg_rx &= ~0xff0f; 1650 1651 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 1652 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); 1653 } 1654 1655 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv) 1656 { 1657 u32 val32; 1658 1659 /* Time duration for NHM unit: 4us, 0x2710=40ms */ 1660 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710); 1661 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); 1662 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52); 1663 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); 1664 /* TH8 */ 1665 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1666 val32 |= 0xff; 1667 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1668 /* Enable CCK */ 1669 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); 1670 val32 |= BIT(8) | BIT(9) | BIT(10); 1671 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); 1672 /* Max power amongst all RX antennas */ 1673 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); 1674 val32 |= BIT(7); 1675 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); 1676 } 1677 1678 static s8 rtl8723b_cck_rssi(struct rtl8xxxu_priv *priv, u8 cck_agc_rpt) 1679 { 1680 s8 rx_pwr_all = 0x00; 1681 u8 vga_idx, lna_idx; 1682 1683 lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK); 1684 vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK); 1685 1686 switch (lna_idx) { 1687 case 6: 1688 rx_pwr_all = -34 - (2 * vga_idx); 1689 break; 1690 case 4: 1691 rx_pwr_all = -14 - (2 * vga_idx); 1692 break; 1693 case 1: 1694 rx_pwr_all = 6 - (2 * vga_idx); 1695 break; 1696 case 0: 1697 rx_pwr_all = 16 - (2 * vga_idx); 1698 break; 1699 default: 1700 break; 1701 } 1702 1703 return rx_pwr_all; 1704 } 1705 1706 struct rtl8xxxu_fileops rtl8723bu_fops = { 1707 .identify_chip = rtl8723bu_identify_chip, 1708 .parse_efuse = rtl8723bu_parse_efuse, 1709 .load_firmware = rtl8723bu_load_firmware, 1710 .power_on = rtl8723bu_power_on, 1711 .power_off = rtl8723bu_power_off, 1712 .reset_8051 = rtl8723bu_reset_8051, 1713 .llt_init = rtl8xxxu_auto_llt_table, 1714 .init_phy_bb = rtl8723bu_init_phy_bb, 1715 .init_phy_rf = rtl8723bu_init_phy_rf, 1716 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection, 1717 .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, 1718 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate, 1719 .config_channel = rtl8xxxu_gen2_config_channel, 1720 .parse_rx_desc = rtl8xxxu_parse_rxdesc24, 1721 .init_aggregation = rtl8723bu_init_aggregation, 1722 .init_statistics = rtl8723bu_init_statistics, 1723 .init_burst = rtl8xxxu_init_burst, 1724 .enable_rf = rtl8723b_enable_rf, 1725 .disable_rf = rtl8xxxu_gen2_disable_rf, 1726 .usb_quirks = rtl8xxxu_gen2_usb_quirks, 1727 .set_tx_power = rtl8723b_set_tx_power, 1728 .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, 1729 .report_connect = rtl8xxxu_gen2_report_connect, 1730 .report_rssi = rtl8xxxu_gen2_report_rssi, 1731 .fill_txdesc = rtl8xxxu_fill_txdesc_v2, 1732 .set_crystal_cap = rtl8723a_set_crystal_cap, 1733 .cck_rssi = rtl8723b_cck_rssi, 1734 .writeN_block_size = 1024, 1735 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), 1736 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), 1737 .has_s0s1 = 1, 1738 .has_tx_report = 1, 1739 .gen2_thermal_meter = 1, 1740 .needs_full_init = 1, 1741 .adda_1t_init = 0x01c00014, 1742 .adda_1t_path_on = 0x01c00014, 1743 .adda_2t_path_on_a = 0x01c00014, 1744 .adda_2t_path_on_b = 0x01c00014, 1745 .trxff_boundary = 0x3f7f, 1746 .pbp_rx = PBP_PAGE_SIZE_256, 1747 .pbp_tx = PBP_PAGE_SIZE_256, 1748 .mactable = rtl8723b_mac_init_table, 1749 .total_page_num = TX_TOTAL_PAGE_NUM_8723B, 1750 .page_num_hi = TX_PAGE_NUM_HI_PQ_8723B, 1751 .page_num_lo = TX_PAGE_NUM_LO_PQ_8723B, 1752 .page_num_norm = TX_PAGE_NUM_NORM_PQ_8723B, 1753 }; 1754