1 /*
2  * RTL8XXXU mac80211 USB driver - 8723a specific subdriver
3  *
4  * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
5  *
6  * Portions, notably calibration code:
7  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8  *
9  * This driver was written as a replacement for the vendor provided
10  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11  * their programming interface, I have started adding support for
12  * additional 8xxx chips like the 8192cu, 8188cus, etc.
13  *
14  * This program is free software; you can redistribute it and/or modify it
15  * under the terms of version 2 of the GNU General Public License as
16  * published by the Free Software Foundation.
17  *
18  * This program is distributed in the hope that it will be useful, but WITHOUT
19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21  * more details.
22  */
23 
24 #include <linux/init.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/spinlock.h>
31 #include <linux/list.h>
32 #include <linux/usb.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/moduleparam.h>
39 #include <net/mac80211.h>
40 #include "rtl8xxxu.h"
41 #include "rtl8xxxu_regs.h"
42 
43 static struct rtl8xxxu_power_base rtl8723a_power_base = {
44 	.reg_0e00 = 0x0a0c0c0c,
45 	.reg_0e04 = 0x02040608,
46 	.reg_0e08 = 0x00000000,
47 	.reg_086c = 0x00000000,
48 
49 	.reg_0e10 = 0x0a0c0d0e,
50 	.reg_0e14 = 0x02040608,
51 	.reg_0e18 = 0x0a0c0d0e,
52 	.reg_0e1c = 0x02040608,
53 
54 	.reg_0830 = 0x0a0c0c0c,
55 	.reg_0834 = 0x02040608,
56 	.reg_0838 = 0x00000000,
57 	.reg_086c_2 = 0x00000000,
58 
59 	.reg_083c = 0x0a0c0d0e,
60 	.reg_0848 = 0x02040608,
61 	.reg_084c = 0x0a0c0d0e,
62 	.reg_0868 = 0x02040608,
63 };
64 
65 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
66 	{0x00, 0x00030159}, {0x01, 0x00031284},
67 	{0x02, 0x00098000}, {0x03, 0x00039c63},
68 	{0x04, 0x000210e7}, {0x09, 0x0002044f},
69 	{0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
70 	{0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
71 	{0x0e, 0x00039ce7}, {0x0f, 0x00000451},
72 	{0x19, 0x00000000}, {0x1a, 0x00030355},
73 	{0x1b, 0x00060a00}, {0x1c, 0x000fc378},
74 	{0x1d, 0x000a1250}, {0x1e, 0x0000024f},
75 	{0x1f, 0x00000000}, {0x20, 0x0000b614},
76 	{0x21, 0x0006c000}, {0x22, 0x00000000},
77 	{0x23, 0x00001558}, {0x24, 0x00000060},
78 	{0x25, 0x00000483}, {0x26, 0x0004f000},
79 	{0x27, 0x000ec7d9}, {0x28, 0x00057730},
80 	{0x29, 0x00004783}, {0x2a, 0x00000001},
81 	{0x2b, 0x00021334}, {0x2a, 0x00000000},
82 	{0x2b, 0x00000054}, {0x2a, 0x00000001},
83 	{0x2b, 0x00000808}, {0x2b, 0x00053333},
84 	{0x2c, 0x0000000c}, {0x2a, 0x00000002},
85 	{0x2b, 0x00000808}, {0x2b, 0x0005b333},
86 	{0x2c, 0x0000000d}, {0x2a, 0x00000003},
87 	{0x2b, 0x00000808}, {0x2b, 0x00063333},
88 	{0x2c, 0x0000000d}, {0x2a, 0x00000004},
89 	{0x2b, 0x00000808}, {0x2b, 0x0006b333},
90 	{0x2c, 0x0000000d}, {0x2a, 0x00000005},
91 	{0x2b, 0x00000808}, {0x2b, 0x00073333},
92 	{0x2c, 0x0000000d}, {0x2a, 0x00000006},
93 	{0x2b, 0x00000709}, {0x2b, 0x0005b333},
94 	{0x2c, 0x0000000d}, {0x2a, 0x00000007},
95 	{0x2b, 0x00000709}, {0x2b, 0x00063333},
96 	{0x2c, 0x0000000d}, {0x2a, 0x00000008},
97 	{0x2b, 0x0000060a}, {0x2b, 0x0004b333},
98 	{0x2c, 0x0000000d}, {0x2a, 0x00000009},
99 	{0x2b, 0x0000060a}, {0x2b, 0x00053333},
100 	{0x2c, 0x0000000d}, {0x2a, 0x0000000a},
101 	{0x2b, 0x0000060a}, {0x2b, 0x0005b333},
102 	{0x2c, 0x0000000d}, {0x2a, 0x0000000b},
103 	{0x2b, 0x0000060a}, {0x2b, 0x00063333},
104 	{0x2c, 0x0000000d}, {0x2a, 0x0000000c},
105 	{0x2b, 0x0000060a}, {0x2b, 0x0006b333},
106 	{0x2c, 0x0000000d}, {0x2a, 0x0000000d},
107 	{0x2b, 0x0000060a}, {0x2b, 0x00073333},
108 	{0x2c, 0x0000000d}, {0x2a, 0x0000000e},
109 	{0x2b, 0x0000050b}, {0x2b, 0x00066666},
110 	{0x2c, 0x0000001a}, {0x2a, 0x000e0000},
111 	{0x10, 0x0004000f}, {0x11, 0x000e31fc},
112 	{0x10, 0x0006000f}, {0x11, 0x000ff9f8},
113 	{0x10, 0x0002000f}, {0x11, 0x000203f9},
114 	{0x10, 0x0003000f}, {0x11, 0x000ff500},
115 	{0x10, 0x00000000}, {0x11, 0x00000000},
116 	{0x10, 0x0008000f}, {0x11, 0x0003f100},
117 	{0x10, 0x0009000f}, {0x11, 0x00023100},
118 	{0x12, 0x00032000}, {0x12, 0x00071000},
119 	{0x12, 0x000b0000}, {0x12, 0x000fc000},
120 	{0x13, 0x000287b3}, {0x13, 0x000244b7},
121 	{0x13, 0x000204ab}, {0x13, 0x0001c49f},
122 	{0x13, 0x00018493}, {0x13, 0x0001429b},
123 	{0x13, 0x00010299}, {0x13, 0x0000c29c},
124 	{0x13, 0x000081a0}, {0x13, 0x000040ac},
125 	{0x13, 0x00000020}, {0x14, 0x0001944c},
126 	{0x14, 0x00059444}, {0x14, 0x0009944c},
127 	{0x14, 0x000d9444}, {0x15, 0x0000f474},
128 	{0x15, 0x0004f477}, {0x15, 0x0008f455},
129 	{0x15, 0x000cf455}, {0x16, 0x00000339},
130 	{0x16, 0x00040339}, {0x16, 0x00080339},
131 	{0x16, 0x000c0366}, {0x00, 0x00010159},
132 	{0x18, 0x0000f401}, {0xfe, 0x00000000},
133 	{0xfe, 0x00000000}, {0x1f, 0x00000003},
134 	{0xfe, 0x00000000}, {0xfe, 0x00000000},
135 	{0x1e, 0x00000247}, {0x1f, 0x00000000},
136 	{0x00, 0x00030159},
137 	{0xff, 0xffffffff}
138 };
139 
140 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
141 {
142 	struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
143 
144 	if (efuse->rtl_id != cpu_to_le16(0x8129))
145 		return -EINVAL;
146 
147 	ether_addr_copy(priv->mac_addr, efuse->mac_addr);
148 
149 	memcpy(priv->cck_tx_power_index_A,
150 	       efuse->cck_tx_power_index_A,
151 	       sizeof(efuse->cck_tx_power_index_A));
152 	memcpy(priv->cck_tx_power_index_B,
153 	       efuse->cck_tx_power_index_B,
154 	       sizeof(efuse->cck_tx_power_index_B));
155 
156 	memcpy(priv->ht40_1s_tx_power_index_A,
157 	       efuse->ht40_1s_tx_power_index_A,
158 	       sizeof(efuse->ht40_1s_tx_power_index_A));
159 	memcpy(priv->ht40_1s_tx_power_index_B,
160 	       efuse->ht40_1s_tx_power_index_B,
161 	       sizeof(efuse->ht40_1s_tx_power_index_B));
162 
163 	memcpy(priv->ht20_tx_power_index_diff,
164 	       efuse->ht20_tx_power_index_diff,
165 	       sizeof(efuse->ht20_tx_power_index_diff));
166 	memcpy(priv->ofdm_tx_power_index_diff,
167 	       efuse->ofdm_tx_power_index_diff,
168 	       sizeof(efuse->ofdm_tx_power_index_diff));
169 
170 	memcpy(priv->ht40_max_power_offset,
171 	       efuse->ht40_max_power_offset,
172 	       sizeof(efuse->ht40_max_power_offset));
173 	memcpy(priv->ht20_max_power_offset,
174 	       efuse->ht20_max_power_offset,
175 	       sizeof(efuse->ht20_max_power_offset));
176 
177 	if (priv->efuse_wifi.efuse8723.version >= 0x01) {
178 		priv->has_xtalk = 1;
179 		priv->xtalk = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
180 	}
181 
182 	priv->power_base = &rtl8723a_power_base;
183 
184 	dev_info(&priv->udev->dev, "Vendor: %.7s\n",
185 		 efuse->vendor_name);
186 	dev_info(&priv->udev->dev, "Product: %.41s\n",
187 		 efuse->device_name);
188 	return 0;
189 }
190 
191 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
192 {
193 	char *fw_name;
194 	int ret;
195 
196 	switch (priv->chip_cut) {
197 	case 0:
198 		fw_name = "rtlwifi/rtl8723aufw_A.bin";
199 		break;
200 	case 1:
201 		if (priv->enable_bluetooth)
202 			fw_name = "rtlwifi/rtl8723aufw_B.bin";
203 		else
204 			fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
205 
206 		break;
207 	default:
208 		return -EINVAL;
209 	}
210 
211 	ret = rtl8xxxu_load_firmware(priv, fw_name);
212 	return ret;
213 }
214 
215 static int rtl8723au_init_phy_rf(struct rtl8xxxu_priv *priv)
216 {
217 	int ret;
218 
219 	ret = rtl8xxxu_init_phy_rf(priv, rtl8723au_radioa_1t_init_table, RF_A);
220 
221 	/* Reduce 80M spur */
222 	rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
223 	rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
224 	rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
225 	rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
226 
227 	return ret;
228 }
229 
230 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
231 {
232 	u8 val8;
233 	u32 val32;
234 	int count, ret = 0;
235 
236 	/* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
237 	val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
238 	val8 |= LDOA15_ENABLE;
239 	rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
240 
241 	/* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
242 	val8 = rtl8xxxu_read8(priv, 0x0067);
243 	val8 &= ~BIT(4);
244 	rtl8xxxu_write8(priv, 0x0067, val8);
245 
246 	mdelay(1);
247 
248 	/* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
249 	val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
250 	val8 &= ~SYS_ISO_ANALOG_IPS;
251 	rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
252 
253 	/* disable SW LPS 0x04[10]= 0 */
254 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
255 	val8 &= ~BIT(2);
256 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
257 
258 	/* wait till 0x04[17] = 1 power ready*/
259 	for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
260 		val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
261 		if (val32 & BIT(17))
262 			break;
263 
264 		udelay(10);
265 	}
266 
267 	if (!count) {
268 		ret = -EBUSY;
269 		goto exit;
270 	}
271 
272 	/* We should be able to optimize the following three entries into one */
273 
274 	/* release WLON reset 0x04[16]= 1*/
275 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
276 	val8 |= BIT(0);
277 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
278 
279 	/* disable HWPDN 0x04[15]= 0*/
280 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
281 	val8 &= ~BIT(7);
282 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
283 
284 	/* disable WL suspend*/
285 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
286 	val8 &= ~(BIT(3) | BIT(4));
287 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
288 
289 	/* set, then poll until 0 */
290 	val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
291 	val32 |= APS_FSMCO_MAC_ENABLE;
292 	rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
293 
294 	for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
295 		val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
296 		if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
297 			ret = 0;
298 			break;
299 		}
300 		udelay(10);
301 	}
302 
303 	if (!count) {
304 		ret = -EBUSY;
305 		goto exit;
306 	}
307 
308 	/* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
309 	/*
310 	 * Note: Vendor driver actually clears this bit, despite the
311 	 * documentation claims it's being set!
312 	 */
313 	val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
314 	val8 |= LEDCFG2_DPDT_SELECT;
315 	val8 &= ~LEDCFG2_DPDT_SELECT;
316 	rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
317 
318 exit:
319 	return ret;
320 }
321 
322 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
323 {
324 	u8 val8;
325 	u16 val16;
326 	u32 val32;
327 	int ret;
328 
329 	/*
330 	 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
331 	 */
332 	rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
333 
334 	rtl8xxxu_disabled_to_emu(priv);
335 
336 	ret = rtl8723a_emu_to_active(priv);
337 	if (ret)
338 		goto exit;
339 
340 	/*
341 	 * 0x0004[19] = 1, reset 8051
342 	 */
343 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
344 	val8 |= BIT(3);
345 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
346 
347 	/*
348 	 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
349 	 * Set CR bit10 to enable 32k calibration.
350 	 */
351 	val16 = rtl8xxxu_read16(priv, REG_CR);
352 	val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
353 		  CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
354 		  CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
355 		  CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
356 		  CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
357 	rtl8xxxu_write16(priv, REG_CR, val16);
358 
359 	/* For EFuse PG */
360 	val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
361 	val32 &= ~(BIT(28) | BIT(29) | BIT(30));
362 	val32 |= (0x06 << 28);
363 	rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
364 exit:
365 	return ret;
366 }
367 
368 struct rtl8xxxu_fileops rtl8723au_fops = {
369 	.parse_efuse = rtl8723au_parse_efuse,
370 	.load_firmware = rtl8723au_load_firmware,
371 	.power_on = rtl8723au_power_on,
372 	.power_off = rtl8xxxu_power_off,
373 	.reset_8051 = rtl8xxxu_reset_8051,
374 	.llt_init = rtl8xxxu_init_llt_table,
375 	.init_phy_bb = rtl8xxxu_gen1_init_phy_bb,
376 	.init_phy_rf = rtl8723au_init_phy_rf,
377 	.phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate,
378 	.config_channel = rtl8xxxu_gen1_config_channel,
379 	.parse_rx_desc = rtl8xxxu_parse_rxdesc16,
380 	.init_aggregation = rtl8xxxu_gen1_init_aggregation,
381 	.enable_rf = rtl8xxxu_gen1_enable_rf,
382 	.disable_rf = rtl8xxxu_gen1_disable_rf,
383 	.usb_quirks = rtl8xxxu_gen1_usb_quirks,
384 	.set_tx_power = rtl8xxxu_gen1_set_tx_power,
385 	.update_rate_mask = rtl8xxxu_update_rate_mask,
386 	.report_connect = rtl8xxxu_gen1_report_connect,
387 	.fill_txdesc = rtl8xxxu_fill_txdesc_v1,
388 	.writeN_block_size = 1024,
389 	.rx_agg_buf_size = 16000,
390 	.tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
391 	.rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16),
392 	.adda_1t_init = 0x0b1b25a0,
393 	.adda_1t_path_on = 0x0bdb25a0,
394 	.adda_2t_path_on_a = 0x04db25a4,
395 	.adda_2t_path_on_b = 0x0b1b25a4,
396 	.trxff_boundary = 0x27ff,
397 	.pbp_rx = PBP_PAGE_SIZE_128,
398 	.pbp_tx = PBP_PAGE_SIZE_128,
399 	.mactable = rtl8xxxu_gen1_mac_init_table,
400 	.total_page_num = TX_TOTAL_PAGE_NUM,
401 	.page_num_hi = TX_PAGE_NUM_HI_PQ,
402 	.page_num_lo = TX_PAGE_NUM_LO_PQ,
403 	.page_num_norm = TX_PAGE_NUM_NORM_PQ,
404 };
405