1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * RTL8XXXU mac80211 USB driver - 8192e specific subdriver 4 * 5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 6 * 7 * Portions, notably calibration code: 8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 9 * 10 * This driver was written as a replacement for the vendor provided 11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in 12 * their programming interface, I have started adding support for 13 * additional 8xxx chips like the 8192cu, 8188cus, etc. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/kernel.h> 18 #include <linux/sched.h> 19 #include <linux/errno.h> 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/spinlock.h> 23 #include <linux/list.h> 24 #include <linux/usb.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/ethtool.h> 28 #include <linux/wireless.h> 29 #include <linux/firmware.h> 30 #include <linux/moduleparam.h> 31 #include <net/mac80211.h> 32 #include "rtl8xxxu.h" 33 #include "rtl8xxxu_regs.h" 34 35 static struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = { 36 {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7}, 37 {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00}, 38 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, 39 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05}, 40 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01}, 41 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00}, 42 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f}, 43 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00}, 44 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f}, 45 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66}, 46 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff}, 47 {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f}, 48 {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e}, 49 {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e}, 50 {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00}, 51 {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a}, 52 {0x525, 0x4f}, {0x540, 0x12}, {0x541, 0x64}, {0x550, 0x10}, 53 {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, {0x55d, 0xff}, 54 {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, {0x620, 0xff}, 55 {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff}, 56 {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50}, 57 {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e}, 58 {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8}, 59 {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, 60 {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65}, 61 {0x70b, 0x87}, 62 {0xffff, 0xff}, 63 }; 64 65 static struct rtl8xxxu_reg32val rtl8192eu_phy_init_table[] = { 66 {0x800, 0x80040000}, {0x804, 0x00000003}, 67 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 68 {0x810, 0x10001331}, {0x814, 0x020c3d10}, 69 {0x818, 0x02220385}, {0x81c, 0x00000000}, 70 {0x820, 0x01000100}, {0x824, 0x00390204}, 71 {0x828, 0x01000100}, {0x82c, 0x00390204}, 72 {0x830, 0x32323232}, {0x834, 0x30303030}, 73 {0x838, 0x30303030}, {0x83c, 0x30303030}, 74 {0x840, 0x00010000}, {0x844, 0x00010000}, 75 {0x848, 0x28282828}, {0x84c, 0x28282828}, 76 {0x850, 0x00000000}, {0x854, 0x00000000}, 77 {0x858, 0x009a009a}, {0x85c, 0x01000014}, 78 {0x860, 0x66f60000}, {0x864, 0x061f0000}, 79 {0x868, 0x30303030}, {0x86c, 0x30303030}, 80 {0x870, 0x00000000}, {0x874, 0x55004200}, 81 {0x878, 0x08080808}, {0x87c, 0x00000000}, 82 {0x880, 0xb0000c1c}, {0x884, 0x00000001}, 83 {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, 84 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 85 {0x898, 0x40302010}, {0x900, 0x00000000}, 86 {0x904, 0x00000023}, {0x908, 0x00000000}, 87 {0x90c, 0x81121313}, {0x910, 0x806c0001}, 88 {0x914, 0x00000001}, {0x918, 0x00000000}, 89 {0x91c, 0x00010000}, {0x924, 0x00000001}, 90 {0x928, 0x00000000}, {0x92c, 0x00000000}, 91 {0x930, 0x00000000}, {0x934, 0x00000000}, 92 {0x938, 0x00000000}, {0x93c, 0x00000000}, 93 {0x940, 0x00000000}, {0x944, 0x00000000}, 94 {0x94c, 0x00000008}, {0xa00, 0x00d0c7c8}, 95 {0xa04, 0x81ff000c}, {0xa08, 0x8c838300}, 96 {0xa0c, 0x2e68120f}, {0xa10, 0x95009b78}, 97 {0xa14, 0x1114d028}, {0xa18, 0x00881117}, 98 {0xa1c, 0x89140f00}, {0xa20, 0x1a1b0000}, 99 {0xa24, 0x090e1317}, {0xa28, 0x00000204}, 100 {0xa2c, 0x00d30000}, {0xa70, 0x101fff00}, 101 {0xa74, 0x00000007}, {0xa78, 0x00000900}, 102 {0xa7c, 0x225b0606}, {0xa80, 0x218075b1}, 103 {0xb38, 0x00000000}, {0xc00, 0x48071d40}, 104 {0xc04, 0x03a05633}, {0xc08, 0x000000e4}, 105 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, 106 {0xc14, 0x40000100}, {0xc18, 0x08800000}, 107 {0xc1c, 0x40000100}, {0xc20, 0x00000000}, 108 {0xc24, 0x00000000}, {0xc28, 0x00000000}, 109 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac47}, 110 {0xc34, 0x469652af}, {0xc38, 0x49795994}, 111 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, 112 {0xc44, 0x000100b7}, {0xc48, 0xec020107}, 113 {0xc4c, 0x007f037f}, 114 #ifdef EXT_PA_8192EU 115 /* External PA or external LNA */ 116 {0xc50, 0x00340220}, 117 #else 118 {0xc50, 0x00340020}, 119 #endif 120 {0xc54, 0x0080801f}, 121 #ifdef EXT_PA_8192EU 122 /* External PA or external LNA */ 123 {0xc58, 0x00000220}, 124 #else 125 {0xc58, 0x00000020}, 126 #endif 127 {0xc5c, 0x00248492}, {0xc60, 0x00000000}, 128 {0xc64, 0x7112848b}, {0xc68, 0x47c00bff}, 129 {0xc6c, 0x00000036}, {0xc70, 0x00000600}, 130 {0xc74, 0x02013169}, {0xc78, 0x0000001f}, 131 {0xc7c, 0x00b91612}, 132 #ifdef EXT_PA_8192EU 133 /* External PA or external LNA */ 134 {0xc80, 0x2d4000b5}, 135 #else 136 {0xc80, 0x40000100}, 137 #endif 138 {0xc84, 0x21f60000}, 139 #ifdef EXT_PA_8192EU 140 /* External PA or external LNA */ 141 {0xc88, 0x2d4000b5}, 142 #else 143 {0xc88, 0x40000100}, 144 #endif 145 {0xc8c, 0xa0e40000}, {0xc90, 0x00121820}, 146 {0xc94, 0x00000000}, {0xc98, 0x00121820}, 147 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, 148 {0xca4, 0x000300a0}, {0xca8, 0x00000000}, 149 {0xcac, 0x00000000}, {0xcb0, 0x00000000}, 150 {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, 151 {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, 152 {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, 153 {0xccc, 0x00000000}, {0xcd0, 0x00000000}, 154 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, 155 {0xcdc, 0x00766932}, {0xce0, 0x00222222}, 156 {0xce4, 0x00040000}, {0xce8, 0x77644302}, 157 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, 158 {0xd04, 0x00020403}, {0xd08, 0x0000907f}, 159 {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, 160 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, 161 {0xd1c, 0x0000007f}, {0xd2c, 0xcc979975}, 162 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 163 {0xd38, 0x00000000}, {0xd3c, 0x00127353}, 164 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 165 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 166 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 167 {0xd58, 0x00000282}, {0xd5c, 0x30032064}, 168 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 169 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 170 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 171 {0xd78, 0x000e3c24}, {0xd80, 0x01081008}, 172 {0xd84, 0x00000800}, {0xd88, 0xf0b50000}, 173 {0xe00, 0x30303030}, {0xe04, 0x30303030}, 174 {0xe08, 0x03903030}, {0xe10, 0x30303030}, 175 {0xe14, 0x30303030}, {0xe18, 0x30303030}, 176 {0xe1c, 0x30303030}, {0xe28, 0x00000000}, 177 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, 178 {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, 179 {0xe40, 0x01007c00}, {0xe44, 0x01004800}, 180 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, 181 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, 182 {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, 183 {0xe60, 0x00000008}, {0xe68, 0x0fc05656}, 184 {0xe6c, 0x03c09696}, {0xe70, 0x03c09696}, 185 {0xe74, 0x0c005656}, {0xe78, 0x0c005656}, 186 {0xe7c, 0x0c005656}, {0xe80, 0x0c005656}, 187 {0xe84, 0x03c09696}, {0xe88, 0x0c005656}, 188 {0xe8c, 0x03c09696}, {0xed0, 0x03c09696}, 189 {0xed4, 0x03c09696}, {0xed8, 0x03c09696}, 190 {0xedc, 0x0000d6d6}, {0xee0, 0x0000d6d6}, 191 {0xeec, 0x0fc01616}, {0xee4, 0xb0000c1c}, 192 {0xee8, 0x00000001}, {0xf14, 0x00000003}, 193 {0xf4c, 0x00000000}, {0xf00, 0x00000300}, 194 {0xffff, 0xffffffff}, 195 }; 196 197 static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table[] = { 198 {0xc78, 0xfb000001}, {0xc78, 0xfb010001}, 199 {0xc78, 0xfb020001}, {0xc78, 0xfb030001}, 200 {0xc78, 0xfb040001}, {0xc78, 0xfb050001}, 201 {0xc78, 0xfa060001}, {0xc78, 0xf9070001}, 202 {0xc78, 0xf8080001}, {0xc78, 0xf7090001}, 203 {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001}, 204 {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001}, 205 {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001}, 206 {0xc78, 0xf0100001}, {0xc78, 0xef110001}, 207 {0xc78, 0xee120001}, {0xc78, 0xed130001}, 208 {0xc78, 0xec140001}, {0xc78, 0xeb150001}, 209 {0xc78, 0xea160001}, {0xc78, 0xe9170001}, 210 {0xc78, 0xe8180001}, {0xc78, 0xe7190001}, 211 {0xc78, 0xc81a0001}, {0xc78, 0xc71b0001}, 212 {0xc78, 0xc61c0001}, {0xc78, 0x071d0001}, 213 {0xc78, 0x061e0001}, {0xc78, 0x051f0001}, 214 {0xc78, 0x04200001}, {0xc78, 0x03210001}, 215 {0xc78, 0xaa220001}, {0xc78, 0xa9230001}, 216 {0xc78, 0xa8240001}, {0xc78, 0xa7250001}, 217 {0xc78, 0xa6260001}, {0xc78, 0x85270001}, 218 {0xc78, 0x84280001}, {0xc78, 0x83290001}, 219 {0xc78, 0x252a0001}, {0xc78, 0x242b0001}, 220 {0xc78, 0x232c0001}, {0xc78, 0x222d0001}, 221 {0xc78, 0x672e0001}, {0xc78, 0x662f0001}, 222 {0xc78, 0x65300001}, {0xc78, 0x64310001}, 223 {0xc78, 0x63320001}, {0xc78, 0x62330001}, 224 {0xc78, 0x61340001}, {0xc78, 0x45350001}, 225 {0xc78, 0x44360001}, {0xc78, 0x43370001}, 226 {0xc78, 0x42380001}, {0xc78, 0x41390001}, 227 {0xc78, 0x403a0001}, {0xc78, 0x403b0001}, 228 {0xc78, 0x403c0001}, {0xc78, 0x403d0001}, 229 {0xc78, 0x403e0001}, {0xc78, 0x403f0001}, 230 {0xc78, 0xfb400001}, {0xc78, 0xfb410001}, 231 {0xc78, 0xfb420001}, {0xc78, 0xfb430001}, 232 {0xc78, 0xfb440001}, {0xc78, 0xfb450001}, 233 {0xc78, 0xfa460001}, {0xc78, 0xf9470001}, 234 {0xc78, 0xf8480001}, {0xc78, 0xf7490001}, 235 {0xc78, 0xf64a0001}, {0xc78, 0xf54b0001}, 236 {0xc78, 0xf44c0001}, {0xc78, 0xf34d0001}, 237 {0xc78, 0xf24e0001}, {0xc78, 0xf14f0001}, 238 {0xc78, 0xf0500001}, {0xc78, 0xef510001}, 239 {0xc78, 0xee520001}, {0xc78, 0xed530001}, 240 {0xc78, 0xec540001}, {0xc78, 0xeb550001}, 241 {0xc78, 0xea560001}, {0xc78, 0xe9570001}, 242 {0xc78, 0xe8580001}, {0xc78, 0xe7590001}, 243 {0xc78, 0xe65a0001}, {0xc78, 0xe55b0001}, 244 {0xc78, 0xe45c0001}, {0xc78, 0xe35d0001}, 245 {0xc78, 0xe25e0001}, {0xc78, 0xe15f0001}, 246 {0xc78, 0x8a600001}, {0xc78, 0x89610001}, 247 {0xc78, 0x88620001}, {0xc78, 0x87630001}, 248 {0xc78, 0x86640001}, {0xc78, 0x85650001}, 249 {0xc78, 0x84660001}, {0xc78, 0x83670001}, 250 {0xc78, 0x82680001}, {0xc78, 0x6b690001}, 251 {0xc78, 0x6a6a0001}, {0xc78, 0x696b0001}, 252 {0xc78, 0x686c0001}, {0xc78, 0x676d0001}, 253 {0xc78, 0x666e0001}, {0xc78, 0x656f0001}, 254 {0xc78, 0x64700001}, {0xc78, 0x63710001}, 255 {0xc78, 0x62720001}, {0xc78, 0x61730001}, 256 {0xc78, 0x49740001}, {0xc78, 0x48750001}, 257 {0xc78, 0x47760001}, {0xc78, 0x46770001}, 258 {0xc78, 0x45780001}, {0xc78, 0x44790001}, 259 {0xc78, 0x437a0001}, {0xc78, 0x427b0001}, 260 {0xc78, 0x417c0001}, {0xc78, 0x407d0001}, 261 {0xc78, 0x407e0001}, {0xc78, 0x407f0001}, 262 {0xc50, 0x00040022}, {0xc50, 0x00040020}, 263 {0xffff, 0xffffffff} 264 }; 265 266 static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table[] = { 267 {0xc78, 0xfa000001}, {0xc78, 0xf9010001}, 268 {0xc78, 0xf8020001}, {0xc78, 0xf7030001}, 269 {0xc78, 0xf6040001}, {0xc78, 0xf5050001}, 270 {0xc78, 0xf4060001}, {0xc78, 0xf3070001}, 271 {0xc78, 0xf2080001}, {0xc78, 0xf1090001}, 272 {0xc78, 0xf00a0001}, {0xc78, 0xef0b0001}, 273 {0xc78, 0xee0c0001}, {0xc78, 0xed0d0001}, 274 {0xc78, 0xec0e0001}, {0xc78, 0xeb0f0001}, 275 {0xc78, 0xea100001}, {0xc78, 0xe9110001}, 276 {0xc78, 0xe8120001}, {0xc78, 0xe7130001}, 277 {0xc78, 0xe6140001}, {0xc78, 0xe5150001}, 278 {0xc78, 0xe4160001}, {0xc78, 0xe3170001}, 279 {0xc78, 0xe2180001}, {0xc78, 0xe1190001}, 280 {0xc78, 0x8a1a0001}, {0xc78, 0x891b0001}, 281 {0xc78, 0x881c0001}, {0xc78, 0x871d0001}, 282 {0xc78, 0x861e0001}, {0xc78, 0x851f0001}, 283 {0xc78, 0x84200001}, {0xc78, 0x83210001}, 284 {0xc78, 0x82220001}, {0xc78, 0x6a230001}, 285 {0xc78, 0x69240001}, {0xc78, 0x68250001}, 286 {0xc78, 0x67260001}, {0xc78, 0x66270001}, 287 {0xc78, 0x65280001}, {0xc78, 0x64290001}, 288 {0xc78, 0x632a0001}, {0xc78, 0x622b0001}, 289 {0xc78, 0x612c0001}, {0xc78, 0x602d0001}, 290 {0xc78, 0x472e0001}, {0xc78, 0x462f0001}, 291 {0xc78, 0x45300001}, {0xc78, 0x44310001}, 292 {0xc78, 0x43320001}, {0xc78, 0x42330001}, 293 {0xc78, 0x41340001}, {0xc78, 0x40350001}, 294 {0xc78, 0x40360001}, {0xc78, 0x40370001}, 295 {0xc78, 0x40380001}, {0xc78, 0x40390001}, 296 {0xc78, 0x403a0001}, {0xc78, 0x403b0001}, 297 {0xc78, 0x403c0001}, {0xc78, 0x403d0001}, 298 {0xc78, 0x403e0001}, {0xc78, 0x403f0001}, 299 {0xc78, 0xfa400001}, {0xc78, 0xf9410001}, 300 {0xc78, 0xf8420001}, {0xc78, 0xf7430001}, 301 {0xc78, 0xf6440001}, {0xc78, 0xf5450001}, 302 {0xc78, 0xf4460001}, {0xc78, 0xf3470001}, 303 {0xc78, 0xf2480001}, {0xc78, 0xf1490001}, 304 {0xc78, 0xf04a0001}, {0xc78, 0xef4b0001}, 305 {0xc78, 0xee4c0001}, {0xc78, 0xed4d0001}, 306 {0xc78, 0xec4e0001}, {0xc78, 0xeb4f0001}, 307 {0xc78, 0xea500001}, {0xc78, 0xe9510001}, 308 {0xc78, 0xe8520001}, {0xc78, 0xe7530001}, 309 {0xc78, 0xe6540001}, {0xc78, 0xe5550001}, 310 {0xc78, 0xe4560001}, {0xc78, 0xe3570001}, 311 {0xc78, 0xe2580001}, {0xc78, 0xe1590001}, 312 {0xc78, 0x8a5a0001}, {0xc78, 0x895b0001}, 313 {0xc78, 0x885c0001}, {0xc78, 0x875d0001}, 314 {0xc78, 0x865e0001}, {0xc78, 0x855f0001}, 315 {0xc78, 0x84600001}, {0xc78, 0x83610001}, 316 {0xc78, 0x82620001}, {0xc78, 0x6a630001}, 317 {0xc78, 0x69640001}, {0xc78, 0x68650001}, 318 {0xc78, 0x67660001}, {0xc78, 0x66670001}, 319 {0xc78, 0x65680001}, {0xc78, 0x64690001}, 320 {0xc78, 0x636a0001}, {0xc78, 0x626b0001}, 321 {0xc78, 0x616c0001}, {0xc78, 0x606d0001}, 322 {0xc78, 0x476e0001}, {0xc78, 0x466f0001}, 323 {0xc78, 0x45700001}, {0xc78, 0x44710001}, 324 {0xc78, 0x43720001}, {0xc78, 0x42730001}, 325 {0xc78, 0x41740001}, {0xc78, 0x40750001}, 326 {0xc78, 0x40760001}, {0xc78, 0x40770001}, 327 {0xc78, 0x40780001}, {0xc78, 0x40790001}, 328 {0xc78, 0x407a0001}, {0xc78, 0x407b0001}, 329 {0xc78, 0x407c0001}, {0xc78, 0x407d0001}, 330 {0xc78, 0x407e0001}, {0xc78, 0x407f0001}, 331 {0xc50, 0x00040222}, {0xc50, 0x00040220}, 332 {0xffff, 0xffffffff} 333 }; 334 335 static struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = { 336 {0x7f, 0x00000082}, {0x81, 0x0003fc00}, 337 {0x00, 0x00030000}, {0x08, 0x00008400}, 338 {0x18, 0x00000407}, {0x19, 0x00000012}, 339 {0x1b, 0x00000064}, {0x1e, 0x00080009}, 340 {0x1f, 0x00000880}, {0x2f, 0x0001a060}, 341 {0x3f, 0x00000000}, {0x42, 0x000060c0}, 342 {0x57, 0x000d0000}, {0x58, 0x000be180}, 343 {0x67, 0x00001552}, {0x83, 0x00000000}, 344 {0xb0, 0x000ff9f1}, {0xb1, 0x00055418}, 345 {0xb2, 0x0008cc00}, {0xb4, 0x00043083}, 346 {0xb5, 0x00008166}, {0xb6, 0x0000803e}, 347 {0xb7, 0x0001c69f}, {0xb8, 0x0000407f}, 348 {0xb9, 0x00080001}, {0xba, 0x00040001}, 349 {0xbb, 0x00000400}, {0xbf, 0x000c0000}, 350 {0xc2, 0x00002400}, {0xc3, 0x00000009}, 351 {0xc4, 0x00040c91}, {0xc5, 0x00099999}, 352 {0xc6, 0x000000a3}, {0xc7, 0x00088820}, 353 {0xc8, 0x00076c06}, {0xc9, 0x00000000}, 354 {0xca, 0x00080000}, {0xdf, 0x00000180}, 355 {0xef, 0x000001a0}, {0x51, 0x00069545}, 356 {0x52, 0x0007e45e}, {0x53, 0x00000071}, 357 {0x56, 0x00051ff3}, {0x35, 0x000000a8}, 358 {0x35, 0x000001e2}, {0x35, 0x000002a8}, 359 {0x36, 0x00001c24}, {0x36, 0x00009c24}, 360 {0x36, 0x00011c24}, {0x36, 0x00019c24}, 361 {0x18, 0x00000c07}, {0x5a, 0x00048000}, 362 {0x19, 0x000739d0}, 363 #ifdef EXT_PA_8192EU 364 /* External PA or external LNA */ 365 {0x34, 0x0000a093}, {0x34, 0x0000908f}, 366 {0x34, 0x0000808c}, {0x34, 0x0000704d}, 367 {0x34, 0x0000604a}, {0x34, 0x00005047}, 368 {0x34, 0x0000400a}, {0x34, 0x00003007}, 369 {0x34, 0x00002004}, {0x34, 0x00001001}, 370 {0x34, 0x00000000}, 371 #else 372 /* Regular */ 373 {0x34, 0x0000add7}, {0x34, 0x00009dd4}, 374 {0x34, 0x00008dd1}, {0x34, 0x00007dce}, 375 {0x34, 0x00006dcb}, {0x34, 0x00005dc8}, 376 {0x34, 0x00004dc5}, {0x34, 0x000034cc}, 377 {0x34, 0x0000244f}, {0x34, 0x0000144c}, 378 {0x34, 0x00000014}, 379 #endif 380 {0x00, 0x00030159}, 381 {0x84, 0x00068180}, 382 {0x86, 0x0000014e}, 383 {0x87, 0x00048e00}, 384 {0x8e, 0x00065540}, 385 {0x8f, 0x00088000}, 386 {0xef, 0x000020a0}, 387 #ifdef EXT_PA_8192EU 388 /* External PA or external LNA */ 389 {0x3b, 0x000f07b0}, 390 #else 391 {0x3b, 0x000f02b0}, 392 #endif 393 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0}, 394 {0x3b, 0x000cf060}, {0x3b, 0x000b0090}, 395 {0x3b, 0x000a0080}, {0x3b, 0x00090080}, 396 {0x3b, 0x0008f780}, 397 #ifdef EXT_PA_8192EU 398 /* External PA or external LNA */ 399 {0x3b, 0x000787b0}, 400 #else 401 {0x3b, 0x00078730}, 402 #endif 403 {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0}, 404 {0x3b, 0x00040620}, {0x3b, 0x00037090}, 405 {0x3b, 0x00020080}, {0x3b, 0x0001f060}, 406 {0x3b, 0x0000ffb0}, {0xef, 0x000000a0}, 407 {0xfe, 0x00000000}, {0x18, 0x0000fc07}, 408 {0xfe, 0x00000000}, {0xfe, 0x00000000}, 409 {0xfe, 0x00000000}, {0xfe, 0x00000000}, 410 {0x1e, 0x00000001}, {0x1f, 0x00080000}, 411 {0x00, 0x00033e70}, 412 {0xff, 0xffffffff} 413 }; 414 415 static struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table[] = { 416 {0x7f, 0x00000082}, {0x81, 0x0003fc00}, 417 {0x00, 0x00030000}, {0x08, 0x00008400}, 418 {0x18, 0x00000407}, {0x19, 0x00000012}, 419 {0x1b, 0x00000064}, {0x1e, 0x00080009}, 420 {0x1f, 0x00000880}, {0x2f, 0x0001a060}, 421 {0x3f, 0x00000000}, {0x42, 0x000060c0}, 422 {0x57, 0x000d0000}, {0x58, 0x000be180}, 423 {0x67, 0x00001552}, {0x7f, 0x00000082}, 424 {0x81, 0x0003f000}, {0x83, 0x00000000}, 425 {0xdf, 0x00000180}, {0xef, 0x000001a0}, 426 {0x51, 0x00069545}, {0x52, 0x0007e42e}, 427 {0x53, 0x00000071}, {0x56, 0x00051ff3}, 428 {0x35, 0x000000a8}, {0x35, 0x000001e0}, 429 {0x35, 0x000002a8}, {0x36, 0x00001ca8}, 430 {0x36, 0x00009c24}, {0x36, 0x00011c24}, 431 {0x36, 0x00019c24}, {0x18, 0x00000c07}, 432 {0x5a, 0x00048000}, {0x19, 0x000739d0}, 433 #ifdef EXT_PA_8192EU 434 /* External PA or external LNA */ 435 {0x34, 0x0000a093}, {0x34, 0x0000908f}, 436 {0x34, 0x0000808c}, {0x34, 0x0000704d}, 437 {0x34, 0x0000604a}, {0x34, 0x00005047}, 438 {0x34, 0x0000400a}, {0x34, 0x00003007}, 439 {0x34, 0x00002004}, {0x34, 0x00001001}, 440 {0x34, 0x00000000}, 441 #else 442 {0x34, 0x0000add7}, {0x34, 0x00009dd4}, 443 {0x34, 0x00008dd1}, {0x34, 0x00007dce}, 444 {0x34, 0x00006dcb}, {0x34, 0x00005dc8}, 445 {0x34, 0x00004dc5}, {0x34, 0x000034cc}, 446 {0x34, 0x0000244f}, {0x34, 0x0000144c}, 447 {0x34, 0x00000014}, 448 #endif 449 {0x00, 0x00030159}, {0x84, 0x00068180}, 450 {0x86, 0x000000ce}, {0x87, 0x00048a00}, 451 {0x8e, 0x00065540}, {0x8f, 0x00088000}, 452 {0xef, 0x000020a0}, 453 #ifdef EXT_PA_8192EU 454 /* External PA or external LNA */ 455 {0x3b, 0x000f07b0}, 456 #else 457 {0x3b, 0x000f02b0}, 458 #endif 459 460 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0}, 461 {0x3b, 0x000cf060}, {0x3b, 0x000b0090}, 462 {0x3b, 0x000a0080}, {0x3b, 0x00090080}, 463 {0x3b, 0x0008f780}, 464 #ifdef EXT_PA_8192EU 465 /* External PA or external LNA */ 466 {0x3b, 0x000787b0}, 467 #else 468 {0x3b, 0x00078730}, 469 #endif 470 {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0}, 471 {0x3b, 0x00040620}, {0x3b, 0x00037090}, 472 {0x3b, 0x00020080}, {0x3b, 0x0001f060}, 473 {0x3b, 0x0000ffb0}, {0xef, 0x000000a0}, 474 {0x00, 0x00010159}, {0xfe, 0x00000000}, 475 {0xfe, 0x00000000}, {0xfe, 0x00000000}, 476 {0xfe, 0x00000000}, {0x1e, 0x00000001}, 477 {0x1f, 0x00080000}, {0x00, 0x00033e70}, 478 {0xff, 0xffffffff} 479 }; 480 481 static void 482 rtl8192e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) 483 { 484 u32 val32, ofdm, mcs; 485 u8 cck, ofdmbase, mcsbase; 486 int group, tx_idx; 487 488 tx_idx = 0; 489 group = rtl8xxxu_gen2_channel_to_group(channel); 490 491 cck = priv->cck_tx_power_index_A[group]; 492 493 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); 494 val32 &= 0xffff00ff; 495 val32 |= (cck << 8); 496 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); 497 498 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 499 val32 &= 0xff; 500 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); 501 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 502 503 ofdmbase = priv->ht40_1s_tx_power_index_A[group]; 504 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a; 505 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; 506 507 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); 508 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); 509 510 mcsbase = priv->ht40_1s_tx_power_index_A[group]; 511 if (ht40) 512 mcsbase += priv->ht40_tx_power_diff[tx_idx++].a; 513 else 514 mcsbase += priv->ht20_tx_power_diff[tx_idx++].a; 515 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; 516 517 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); 518 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); 519 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); 520 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); 521 522 if (priv->tx_paths > 1) { 523 cck = priv->cck_tx_power_index_B[group]; 524 525 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); 526 val32 &= 0xff; 527 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); 528 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); 529 530 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 531 val32 &= 0xffffff00; 532 val32 |= cck; 533 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 534 535 ofdmbase = priv->ht40_1s_tx_power_index_B[group]; 536 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; 537 ofdm = ofdmbase | ofdmbase << 8 | 538 ofdmbase << 16 | ofdmbase << 24; 539 540 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm); 541 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm); 542 543 mcsbase = priv->ht40_1s_tx_power_index_B[group]; 544 if (ht40) 545 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; 546 else 547 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; 548 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; 549 550 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs); 551 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs); 552 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs); 553 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs); 554 } 555 } 556 557 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv) 558 { 559 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu; 560 int i; 561 562 if (efuse->rtl_id != cpu_to_le16(0x8129)) 563 return -EINVAL; 564 565 ether_addr_copy(priv->mac_addr, efuse->mac_addr); 566 567 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, 568 sizeof(efuse->tx_power_index_A.cck_base)); 569 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, 570 sizeof(efuse->tx_power_index_B.cck_base)); 571 572 memcpy(priv->ht40_1s_tx_power_index_A, 573 efuse->tx_power_index_A.ht40_base, 574 sizeof(efuse->tx_power_index_A.ht40_base)); 575 memcpy(priv->ht40_1s_tx_power_index_B, 576 efuse->tx_power_index_B.ht40_base, 577 sizeof(efuse->tx_power_index_B.ht40_base)); 578 579 priv->ht20_tx_power_diff[0].a = 580 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; 581 priv->ht20_tx_power_diff[0].b = 582 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b; 583 584 priv->ht40_tx_power_diff[0].a = 0; 585 priv->ht40_tx_power_diff[0].b = 0; 586 587 for (i = 1; i < RTL8723B_TX_COUNT; i++) { 588 priv->ofdm_tx_power_diff[i].a = 589 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm; 590 priv->ofdm_tx_power_diff[i].b = 591 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm; 592 593 priv->ht20_tx_power_diff[i].a = 594 efuse->tx_power_index_A.pwr_diff[i - 1].ht20; 595 priv->ht20_tx_power_diff[i].b = 596 efuse->tx_power_index_B.pwr_diff[i - 1].ht20; 597 598 priv->ht40_tx_power_diff[i].a = 599 efuse->tx_power_index_A.pwr_diff[i - 1].ht40; 600 priv->ht40_tx_power_diff[i].b = 601 efuse->tx_power_index_B.pwr_diff[i - 1].ht40; 602 } 603 604 priv->has_xtalk = 1; 605 priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f; 606 607 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name); 608 dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name); 609 if (memchr_inv(efuse->serial, 0xff, 11)) 610 dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial); 611 else 612 dev_info(&priv->udev->dev, "Serial not available.\n"); 613 614 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) { 615 unsigned char *raw = priv->efuse_wifi.raw; 616 617 dev_info(&priv->udev->dev, 618 "%s: dumping efuse (0x%02zx bytes):\n", 619 __func__, sizeof(struct rtl8192eu_efuse)); 620 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) 621 dev_info(&priv->udev->dev, "%02x: %8ph\n", i, &raw[i]); 622 } 623 return 0; 624 } 625 626 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv) 627 { 628 char *fw_name; 629 int ret; 630 631 fw_name = "rtlwifi/rtl8192eu_nic.bin"; 632 633 ret = rtl8xxxu_load_firmware(priv, fw_name); 634 635 return ret; 636 } 637 638 static void rtl8192eu_init_phy_bb(struct rtl8xxxu_priv *priv) 639 { 640 u8 val8; 641 u16 val16; 642 643 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 644 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; 645 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 646 647 /* 6. 0x1f[7:0] = 0x07 */ 648 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; 649 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 650 651 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 652 val16 |= (SYS_FUNC_USBA | SYS_FUNC_USBD | SYS_FUNC_DIO_RF | 653 SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB); 654 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 655 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; 656 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 657 rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table); 658 659 if (priv->hi_pa) 660 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_highpa_table); 661 else 662 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_std_table); 663 } 664 665 static int rtl8192eu_init_phy_rf(struct rtl8xxxu_priv *priv) 666 { 667 int ret; 668 669 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radioa_init_table, RF_A); 670 if (ret) 671 goto exit; 672 673 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radiob_init_table, RF_B); 674 675 exit: 676 return ret; 677 } 678 679 static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv) 680 { 681 u32 reg_eac, reg_e94, reg_e9c; 682 int result = 0; 683 684 /* 685 * TX IQK 686 * PA/PAD controlled by 0x0 687 */ 688 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); 689 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00180); 690 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 691 692 /* Path A IQK setting */ 693 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); 694 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 695 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); 696 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); 697 698 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140303); 699 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160000); 700 701 /* LO calibration setting */ 702 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); 703 704 /* One shot, path A LOK & IQK */ 705 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 706 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 707 708 mdelay(10); 709 710 /* Check failed */ 711 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 712 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 713 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 714 715 if (!(reg_eac & BIT(28)) && 716 ((reg_e94 & 0x03ff0000) != 0x01420000) && 717 ((reg_e9c & 0x03ff0000) != 0x00420000)) 718 result |= 0x01; 719 720 return result; 721 } 722 723 static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) 724 { 725 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; 726 int result = 0; 727 728 /* Leave IQK mode */ 729 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00); 730 731 /* Enable path A PA in TX IQK mode */ 732 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); 733 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 734 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); 735 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf117b); 736 737 /* PA/PAD control by 0x56, and set = 0x0 */ 738 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980); 739 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000); 740 741 /* Enter IQK mode */ 742 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 743 744 /* TX IQK setting */ 745 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 746 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 747 748 /* path-A IQK setting */ 749 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); 750 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 751 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); 752 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); 753 754 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f); 755 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160c1f); 756 757 /* LO calibration setting */ 758 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); 759 760 /* One shot, path A LOK & IQK */ 761 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); 762 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 763 764 mdelay(10); 765 766 /* Check failed */ 767 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 768 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 769 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 770 771 if (!(reg_eac & BIT(28)) && 772 ((reg_e94 & 0x03ff0000) != 0x01420000) && 773 ((reg_e9c & 0x03ff0000) != 0x00420000)) { 774 result |= 0x01; 775 } else { 776 /* PA/PAD controlled by 0x0 */ 777 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); 778 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); 779 goto out; 780 } 781 782 val32 = 0x80007c00 | 783 (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff); 784 rtl8xxxu_write32(priv, REG_TX_IQK, val32); 785 786 /* Modify RX IQK mode table */ 787 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); 788 789 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); 790 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 791 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); 792 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ffa); 793 794 /* PA/PAD control by 0x56, and set = 0x0 */ 795 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980); 796 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000); 797 798 /* Enter IQK mode */ 799 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 800 801 /* IQK setting */ 802 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 803 804 /* Path A IQK setting */ 805 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); 806 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); 807 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); 808 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); 809 810 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f); 811 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f); 812 813 /* LO calibration setting */ 814 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); 815 816 /* One shot, path A LOK & IQK */ 817 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); 818 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 819 820 mdelay(10); 821 822 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 823 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 824 825 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); 826 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); 827 828 if (!(reg_eac & BIT(27)) && 829 ((reg_ea4 & 0x03ff0000) != 0x01320000) && 830 ((reg_eac & 0x03ff0000) != 0x00360000)) 831 result |= 0x02; 832 else 833 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", 834 __func__); 835 836 out: 837 return result; 838 } 839 840 static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv) 841 { 842 u32 reg_eac, reg_eb4, reg_ebc; 843 int result = 0; 844 845 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); 846 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00180); 847 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 848 849 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); 850 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 851 852 /* Path B IQK setting */ 853 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); 854 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 855 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); 856 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); 857 858 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x821403e2); 859 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000); 860 861 /* LO calibration setting */ 862 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00492911); 863 864 /* One shot, path A LOK & IQK */ 865 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); 866 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 867 868 mdelay(1); 869 870 /* Check failed */ 871 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 872 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 873 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 874 875 if (!(reg_eac & BIT(31)) && 876 ((reg_eb4 & 0x03ff0000) != 0x01420000) && 877 ((reg_ebc & 0x03ff0000) != 0x00420000)) 878 result |= 0x01; 879 else 880 dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n", 881 __func__); 882 883 return result; 884 } 885 886 static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) 887 { 888 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32; 889 int result = 0; 890 891 /* Leave IQK mode */ 892 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); 893 894 /* Enable path A PA in TX IQK mode */ 895 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); 896 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); 897 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); 898 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf117b); 899 900 /* PA/PAD control by 0x56, and set = 0x0 */ 901 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980); 902 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000); 903 904 /* Enter IQK mode */ 905 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 906 907 /* TX IQK setting */ 908 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 909 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 910 911 /* path-A IQK setting */ 912 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); 913 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 914 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); 915 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); 916 917 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160c1f); 918 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160c1f); 919 920 /* LO calibration setting */ 921 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); 922 923 /* One shot, path A LOK & IQK */ 924 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); 925 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 926 927 mdelay(10); 928 929 /* Check failed */ 930 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 931 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 932 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 933 934 if (!(reg_eac & BIT(31)) && 935 ((reg_eb4 & 0x03ff0000) != 0x01420000) && 936 ((reg_ebc & 0x03ff0000) != 0x00420000)) { 937 result |= 0x01; 938 } else { 939 /* 940 * PA/PAD controlled by 0x0 941 * Vendor driver restores RF_A here which I believe is a bug 942 */ 943 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); 944 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180); 945 goto out; 946 } 947 948 val32 = 0x80007c00 | 949 (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff); 950 rtl8xxxu_write32(priv, REG_TX_IQK, val32); 951 952 /* Modify RX IQK mode table */ 953 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); 954 955 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); 956 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); 957 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); 958 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ffa); 959 960 /* PA/PAD control by 0x56, and set = 0x0 */ 961 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980); 962 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000); 963 964 /* Enter IQK mode */ 965 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 966 967 /* IQK setting */ 968 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 969 970 /* Path A IQK setting */ 971 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); 972 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 973 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); 974 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c); 975 976 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f); 977 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f); 978 979 /* LO calibration setting */ 980 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); 981 982 /* One shot, path A LOK & IQK */ 983 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); 984 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 985 986 mdelay(10); 987 988 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 989 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 990 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 991 992 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); 993 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180); 994 995 if (!(reg_eac & BIT(30)) && 996 ((reg_ec4 & 0x03ff0000) != 0x01320000) && 997 ((reg_ecc & 0x03ff0000) != 0x00360000)) 998 result |= 0x02; 999 else 1000 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", 1001 __func__); 1002 1003 out: 1004 return result; 1005 } 1006 1007 static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, 1008 int result[][8], int t) 1009 { 1010 struct device *dev = &priv->udev->dev; 1011 u32 i, val32; 1012 int path_a_ok, path_b_ok; 1013 int retry = 2; 1014 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { 1015 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, 1016 REG_RX_WAIT_CCA, REG_TX_CCK_RFON, 1017 REG_TX_CCK_BBON, REG_TX_OFDM_RFON, 1018 REG_TX_OFDM_BBON, REG_TX_TO_RX, 1019 REG_TX_TO_TX, REG_RX_CCK, 1020 REG_RX_OFDM, REG_RX_WAIT_RIFS, 1021 REG_RX_TO_RX, REG_STANDBY, 1022 REG_SLEEP, REG_PMPD_ANAEN 1023 }; 1024 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { 1025 REG_TXPAUSE, REG_BEACON_CTRL, 1026 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG 1027 }; 1028 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { 1029 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, 1030 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, 1031 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, 1032 REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING 1033 }; 1034 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; 1035 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; 1036 1037 /* 1038 * Note: IQ calibration must be performed after loading 1039 * PHY_REG.txt , and radio_a, radio_b.txt 1040 */ 1041 1042 if (t == 0) { 1043 /* Save ADDA parameters, turn Path A ADDA on */ 1044 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, 1045 RTL8XXXU_ADDA_REGS); 1046 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 1047 rtl8xxxu_save_regs(priv, iqk_bb_regs, 1048 priv->bb_backup, RTL8XXXU_BB_REGS); 1049 } 1050 1051 rtl8xxxu_path_adda_on(priv, adda_regs, true); 1052 1053 /* MAC settings */ 1054 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); 1055 1056 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); 1057 val32 |= 0x0f000000; 1058 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); 1059 1060 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); 1061 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); 1062 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200); 1063 1064 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); 1065 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 1066 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 1067 1068 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); 1069 val32 |= BIT(10); 1070 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); 1071 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); 1072 val32 |= BIT(10); 1073 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); 1074 1075 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 1076 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 1077 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 1078 1079 for (i = 0; i < retry; i++) { 1080 path_a_ok = rtl8192eu_iqk_path_a(priv); 1081 if (path_a_ok == 0x01) { 1082 val32 = rtl8xxxu_read32(priv, 1083 REG_TX_POWER_BEFORE_IQK_A); 1084 result[t][0] = (val32 >> 16) & 0x3ff; 1085 val32 = rtl8xxxu_read32(priv, 1086 REG_TX_POWER_AFTER_IQK_A); 1087 result[t][1] = (val32 >> 16) & 0x3ff; 1088 1089 break; 1090 } 1091 } 1092 1093 if (!path_a_ok) 1094 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__); 1095 1096 for (i = 0; i < retry; i++) { 1097 path_a_ok = rtl8192eu_rx_iqk_path_a(priv); 1098 if (path_a_ok == 0x03) { 1099 val32 = rtl8xxxu_read32(priv, 1100 REG_RX_POWER_BEFORE_IQK_A_2); 1101 result[t][2] = (val32 >> 16) & 0x3ff; 1102 val32 = rtl8xxxu_read32(priv, 1103 REG_RX_POWER_AFTER_IQK_A_2); 1104 result[t][3] = (val32 >> 16) & 0x3ff; 1105 1106 break; 1107 } 1108 } 1109 1110 if (!path_a_ok) 1111 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__); 1112 1113 if (priv->rf_paths > 1) { 1114 /* Path A into standby */ 1115 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); 1116 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); 1117 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 1118 1119 /* Turn Path B ADDA on */ 1120 rtl8xxxu_path_adda_on(priv, adda_regs, false); 1121 1122 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); 1123 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 1124 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 1125 1126 for (i = 0; i < retry; i++) { 1127 path_b_ok = rtl8192eu_iqk_path_b(priv); 1128 if (path_b_ok == 0x01) { 1129 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 1130 result[t][4] = (val32 >> 16) & 0x3ff; 1131 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 1132 result[t][5] = (val32 >> 16) & 0x3ff; 1133 break; 1134 } 1135 } 1136 1137 if (!path_b_ok) 1138 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); 1139 1140 for (i = 0; i < retry; i++) { 1141 path_b_ok = rtl8192eu_rx_iqk_path_b(priv); 1142 if (path_b_ok == 0x03) { 1143 val32 = rtl8xxxu_read32(priv, 1144 REG_RX_POWER_BEFORE_IQK_B_2); 1145 result[t][6] = (val32 >> 16) & 0x3ff; 1146 val32 = rtl8xxxu_read32(priv, 1147 REG_RX_POWER_AFTER_IQK_B_2); 1148 result[t][7] = (val32 >> 16) & 0x3ff; 1149 break; 1150 } 1151 } 1152 1153 if (!path_b_ok) 1154 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__); 1155 } 1156 1157 /* Back to BB mode, load original value */ 1158 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); 1159 1160 if (t) { 1161 /* Reload ADDA power saving parameters */ 1162 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, 1163 RTL8XXXU_ADDA_REGS); 1164 1165 /* Reload MAC parameters */ 1166 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 1167 1168 /* Reload BB parameters */ 1169 rtl8xxxu_restore_regs(priv, iqk_bb_regs, 1170 priv->bb_backup, RTL8XXXU_BB_REGS); 1171 1172 /* Restore RX initial gain */ 1173 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 1174 val32 &= 0xffffff00; 1175 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); 1176 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); 1177 1178 if (priv->rf_paths > 1) { 1179 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); 1180 val32 &= 0xffffff00; 1181 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, 1182 val32 | 0x50); 1183 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, 1184 val32 | xb_agc); 1185 } 1186 1187 /* Load 0xe30 IQC default value */ 1188 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); 1189 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); 1190 } 1191 } 1192 1193 static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) 1194 { 1195 struct device *dev = &priv->udev->dev; 1196 int result[4][8]; /* last is final result */ 1197 int i, candidate; 1198 bool path_a_ok, path_b_ok; 1199 u32 reg_e94, reg_e9c, reg_ea4, reg_eac; 1200 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; 1201 bool simu; 1202 1203 memset(result, 0, sizeof(result)); 1204 candidate = -1; 1205 1206 path_a_ok = false; 1207 path_b_ok = false; 1208 1209 for (i = 0; i < 3; i++) { 1210 rtl8192eu_phy_iqcalibrate(priv, result, i); 1211 1212 if (i == 1) { 1213 simu = rtl8xxxu_gen2_simularity_compare(priv, 1214 result, 0, 1); 1215 if (simu) { 1216 candidate = 0; 1217 break; 1218 } 1219 } 1220 1221 if (i == 2) { 1222 simu = rtl8xxxu_gen2_simularity_compare(priv, 1223 result, 0, 2); 1224 if (simu) { 1225 candidate = 0; 1226 break; 1227 } 1228 1229 simu = rtl8xxxu_gen2_simularity_compare(priv, 1230 result, 1, 2); 1231 if (simu) 1232 candidate = 1; 1233 else 1234 candidate = 3; 1235 } 1236 } 1237 1238 for (i = 0; i < 4; i++) { 1239 reg_e94 = result[i][0]; 1240 reg_e9c = result[i][1]; 1241 reg_ea4 = result[i][2]; 1242 reg_eb4 = result[i][4]; 1243 reg_ebc = result[i][5]; 1244 reg_ec4 = result[i][6]; 1245 } 1246 1247 if (candidate >= 0) { 1248 reg_e94 = result[candidate][0]; 1249 priv->rege94 = reg_e94; 1250 reg_e9c = result[candidate][1]; 1251 priv->rege9c = reg_e9c; 1252 reg_ea4 = result[candidate][2]; 1253 reg_eac = result[candidate][3]; 1254 reg_eb4 = result[candidate][4]; 1255 priv->regeb4 = reg_eb4; 1256 reg_ebc = result[candidate][5]; 1257 priv->regebc = reg_ebc; 1258 reg_ec4 = result[candidate][6]; 1259 reg_ecc = result[candidate][7]; 1260 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); 1261 dev_dbg(dev, 1262 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", 1263 __func__, reg_e94, reg_e9c, 1264 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); 1265 path_a_ok = true; 1266 path_b_ok = true; 1267 } else { 1268 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; 1269 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; 1270 } 1271 1272 if (reg_e94 && candidate >= 0) 1273 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, 1274 candidate, (reg_ea4 == 0)); 1275 1276 if (priv->rf_paths > 1) 1277 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, 1278 candidate, (reg_ec4 == 0)); 1279 1280 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, 1281 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); 1282 } 1283 1284 /* 1285 * This is needed for 8723bu as well, presumable 1286 */ 1287 static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv) 1288 { 1289 u8 val8; 1290 u32 val32; 1291 1292 /* 1293 * 40Mhz crystal source, MAC 0x28[2]=0 1294 */ 1295 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); 1296 val8 &= 0xfb; 1297 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); 1298 1299 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); 1300 val32 &= 0xfffffc7f; 1301 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); 1302 1303 /* 1304 * 92e AFE parameter 1305 * AFE PLL KVCO selection, MAC 0x28[6]=1 1306 */ 1307 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); 1308 val8 &= 0xbf; 1309 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); 1310 1311 /* 1312 * AFE PLL KVCO selection, MAC 0x78[21]=0 1313 */ 1314 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); 1315 val32 &= 0xffdfffff; 1316 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); 1317 } 1318 1319 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv) 1320 { 1321 u8 val8; 1322 1323 /* Clear suspend enable and power down enable*/ 1324 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1325 val8 &= ~(BIT(3) | BIT(4)); 1326 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1327 } 1328 1329 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv) 1330 { 1331 u8 val8; 1332 u32 val32; 1333 int count, ret = 0; 1334 1335 /* disable HWPDN 0x04[15]=0*/ 1336 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1337 val8 &= ~BIT(7); 1338 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1339 1340 /* disable SW LPS 0x04[10]= 0 */ 1341 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1342 val8 &= ~BIT(2); 1343 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1344 1345 /* disable WL suspend*/ 1346 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1347 val8 &= ~(BIT(3) | BIT(4)); 1348 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1349 1350 /* wait till 0x04[17] = 1 power ready*/ 1351 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1352 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1353 if (val32 & BIT(17)) 1354 break; 1355 1356 udelay(10); 1357 } 1358 1359 if (!count) { 1360 ret = -EBUSY; 1361 goto exit; 1362 } 1363 1364 /* We should be able to optimize the following three entries into one */ 1365 1366 /* release WLON reset 0x04[16]= 1*/ 1367 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); 1368 val8 |= BIT(0); 1369 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); 1370 1371 /* set, then poll until 0 */ 1372 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1373 val32 |= APS_FSMCO_MAC_ENABLE; 1374 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); 1375 1376 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1377 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1378 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { 1379 ret = 0; 1380 break; 1381 } 1382 udelay(10); 1383 } 1384 1385 if (!count) { 1386 ret = -EBUSY; 1387 goto exit; 1388 } 1389 1390 exit: 1391 return ret; 1392 } 1393 1394 static int rtl8192eu_active_to_lps(struct rtl8xxxu_priv *priv) 1395 { 1396 struct device *dev = &priv->udev->dev; 1397 u8 val8; 1398 u16 val16; 1399 u32 val32; 1400 int retry, retval; 1401 1402 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 1403 1404 retry = 100; 1405 retval = -EBUSY; 1406 /* 1407 * Poll 32 bit wide 0x05f8 for 0x00000000 to ensure no TX is pending. 1408 */ 1409 do { 1410 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); 1411 if (!val32) { 1412 retval = 0; 1413 break; 1414 } 1415 } while (retry--); 1416 1417 if (!retry) { 1418 dev_warn(dev, "Failed to flush TX queue\n"); 1419 retval = -EBUSY; 1420 goto out; 1421 } 1422 1423 /* Disable CCK and OFDM, clock gated */ 1424 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 1425 val8 &= ~SYS_FUNC_BBRSTB; 1426 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 1427 1428 udelay(2); 1429 1430 /* Reset whole BB */ 1431 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 1432 val8 &= ~SYS_FUNC_BB_GLB_RSTN; 1433 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 1434 1435 /* Reset MAC TRX */ 1436 val16 = rtl8xxxu_read16(priv, REG_CR); 1437 val16 &= 0xff00; 1438 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE); 1439 rtl8xxxu_write16(priv, REG_CR, val16); 1440 1441 val16 = rtl8xxxu_read16(priv, REG_CR); 1442 val16 &= ~CR_SECURITY_ENABLE; 1443 rtl8xxxu_write16(priv, REG_CR, val16); 1444 1445 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); 1446 val8 |= DUAL_TSF_TX_OK; 1447 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); 1448 1449 out: 1450 return retval; 1451 } 1452 1453 static int rtl8192eu_active_to_emu(struct rtl8xxxu_priv *priv) 1454 { 1455 u8 val8; 1456 int count, ret = 0; 1457 1458 /* Turn off RF */ 1459 val8 = rtl8xxxu_read8(priv, REG_RF_CTRL); 1460 val8 &= ~RF_ENABLE; 1461 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 1462 1463 /* Switch DPDT_SEL_P output from register 0x65[2] */ 1464 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 1465 val8 &= ~LEDCFG2_DPDT_SELECT; 1466 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 1467 1468 /* 0x0005[1] = 1 turn off MAC by HW state machine*/ 1469 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1470 val8 |= BIT(1); 1471 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1472 1473 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1474 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1475 if ((val8 & BIT(1)) == 0) 1476 break; 1477 udelay(10); 1478 } 1479 1480 if (!count) { 1481 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", 1482 __func__); 1483 ret = -EBUSY; 1484 goto exit; 1485 } 1486 1487 exit: 1488 return ret; 1489 } 1490 1491 static int rtl8192eu_emu_to_disabled(struct rtl8xxxu_priv *priv) 1492 { 1493 u8 val8; 1494 1495 /* 0x04[12:11] = 01 enable WL suspend */ 1496 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1497 val8 &= ~(BIT(3) | BIT(4)); 1498 val8 |= BIT(3); 1499 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1500 1501 return 0; 1502 } 1503 1504 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv) 1505 { 1506 u16 val16; 1507 u32 val32; 1508 int ret; 1509 1510 ret = 0; 1511 1512 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); 1513 if (val32 & SYS_CFG_SPS_LDO_SEL) { 1514 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3); 1515 } else { 1516 /* 1517 * Raise 1.2V voltage 1518 */ 1519 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL); 1520 val32 &= 0xff0fffff; 1521 val32 |= 0x00500000; 1522 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32); 1523 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83); 1524 } 1525 1526 /* 1527 * Adjust AFE before enabling PLL 1528 */ 1529 rtl8192e_crystal_afe_adjust(priv); 1530 rtl8192e_disabled_to_emu(priv); 1531 1532 ret = rtl8192e_emu_to_active(priv); 1533 if (ret) 1534 goto exit; 1535 1536 rtl8xxxu_write16(priv, REG_CR, 0x0000); 1537 1538 /* 1539 * Enable MAC DMA/WMAC/SCHEDULE/SEC block 1540 * Set CR bit10 to enable 32k calibration. 1541 */ 1542 val16 = rtl8xxxu_read16(priv, REG_CR); 1543 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | 1544 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | 1545 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | 1546 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | 1547 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); 1548 rtl8xxxu_write16(priv, REG_CR, val16); 1549 1550 exit: 1551 return ret; 1552 } 1553 1554 static void rtl8192eu_power_off(struct rtl8xxxu_priv *priv) 1555 { 1556 u8 val8; 1557 u16 val16; 1558 1559 rtl8xxxu_flush_fifo(priv); 1560 1561 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); 1562 val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; 1563 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); 1564 1565 /* Turn off RF */ 1566 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); 1567 1568 rtl8192eu_active_to_lps(priv); 1569 1570 /* Reset Firmware if running in RAM */ 1571 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) 1572 rtl8xxxu_firmware_self_reset(priv); 1573 1574 /* Reset MCU */ 1575 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1576 val16 &= ~SYS_FUNC_CPU_ENABLE; 1577 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1578 1579 /* Reset MCU ready status */ 1580 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 1581 1582 rtl8xxxu_reset_8051(priv); 1583 1584 rtl8192eu_active_to_emu(priv); 1585 rtl8192eu_emu_to_disabled(priv); 1586 } 1587 1588 static void rtl8192e_enable_rf(struct rtl8xxxu_priv *priv) 1589 { 1590 u32 val32; 1591 u8 val8; 1592 1593 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); 1594 val32 |= (BIT(22) | BIT(23)); 1595 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); 1596 1597 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); 1598 val8 |= BIT(5); 1599 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); 1600 1601 /* 1602 * WLAN action by PTA 1603 */ 1604 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); 1605 1606 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); 1607 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; 1608 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); 1609 1610 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); 1611 val32 |= (BIT(0) | BIT(1)); 1612 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); 1613 1614 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77); 1615 1616 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); 1617 val32 &= ~BIT(24); 1618 val32 |= BIT(23); 1619 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); 1620 1621 /* 1622 * Fix external switch Main->S1, Aux->S0 1623 */ 1624 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); 1625 val8 &= ~BIT(0); 1626 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); 1627 } 1628 1629 struct rtl8xxxu_fileops rtl8192eu_fops = { 1630 .parse_efuse = rtl8192eu_parse_efuse, 1631 .load_firmware = rtl8192eu_load_firmware, 1632 .power_on = rtl8192eu_power_on, 1633 .power_off = rtl8192eu_power_off, 1634 .reset_8051 = rtl8xxxu_reset_8051, 1635 .llt_init = rtl8xxxu_auto_llt_table, 1636 .init_phy_bb = rtl8192eu_init_phy_bb, 1637 .init_phy_rf = rtl8192eu_init_phy_rf, 1638 .phy_iq_calibrate = rtl8192eu_phy_iq_calibrate, 1639 .config_channel = rtl8xxxu_gen2_config_channel, 1640 .parse_rx_desc = rtl8xxxu_parse_rxdesc24, 1641 .enable_rf = rtl8192e_enable_rf, 1642 .disable_rf = rtl8xxxu_gen2_disable_rf, 1643 .usb_quirks = rtl8xxxu_gen2_usb_quirks, 1644 .set_tx_power = rtl8192e_set_tx_power, 1645 .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, 1646 .report_connect = rtl8xxxu_gen2_report_connect, 1647 .fill_txdesc = rtl8xxxu_fill_txdesc_v2, 1648 .writeN_block_size = 128, 1649 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), 1650 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), 1651 .has_s0s1 = 0, 1652 .gen2_thermal_meter = 1, 1653 .adda_1t_init = 0x0fc01616, 1654 .adda_1t_path_on = 0x0fc01616, 1655 .adda_2t_path_on_a = 0x0fc01616, 1656 .adda_2t_path_on_b = 0x0fc01616, 1657 .trxff_boundary = 0x3cff, 1658 .mactable = rtl8192e_mac_init_table, 1659 .total_page_num = TX_TOTAL_PAGE_NUM_8192E, 1660 .page_num_hi = TX_PAGE_NUM_HI_PQ_8192E, 1661 .page_num_lo = TX_PAGE_NUM_LO_PQ_8192E, 1662 .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192E, 1663 }; 1664