1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * RTL8XXXU mac80211 USB driver - 8188f specific subdriver 4 * 5 * Copyright (c) 2022 Bitterblue Smith <rtl8821cerfe2@gmail.com> 6 * 7 * Portions copied from existing rtl8xxxu code: 8 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 9 * 10 * Portions, notably calibration code: 11 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 12 */ 13 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/sched.h> 17 #include <linux/errno.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <linux/spinlock.h> 21 #include <linux/list.h> 22 #include <linux/usb.h> 23 #include <linux/netdevice.h> 24 #include <linux/etherdevice.h> 25 #include <linux/ethtool.h> 26 #include <linux/wireless.h> 27 #include <linux/firmware.h> 28 #include <linux/moduleparam.h> 29 #include <net/mac80211.h> 30 #include "rtl8xxxu.h" 31 #include "rtl8xxxu_regs.h" 32 33 static const struct rtl8xxxu_reg8val rtl8188f_mac_init_table[] = { 34 {0x024, 0xDF}, {0x025, 0x07}, {0x02B, 0x1C}, {0x283, 0x20}, 35 {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00}, 36 {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, 37 {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04}, 38 {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D}, 39 {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, 40 {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0}, 41 {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00}, 42 {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0}, 43 {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x44}, 44 {0x461, 0x44}, {0x4BC, 0xC0}, {0x4C8, 0xFF}, {0x4C9, 0x08}, 45 {0x4CC, 0xFF}, {0x4CD, 0xFF}, {0x4CE, 0x01}, {0x500, 0x26}, 46 {0x501, 0xA2}, {0x502, 0x2F}, {0x503, 0x00}, {0x504, 0x28}, 47 {0x505, 0xA3}, {0x506, 0x5E}, {0x507, 0x00}, {0x508, 0x2B}, 48 {0x509, 0xA4}, {0x50A, 0x5E}, {0x50B, 0x00}, {0x50C, 0x4F}, 49 {0x50D, 0xA4}, {0x50E, 0x00}, {0x50F, 0x00}, {0x512, 0x1C}, 50 {0x514, 0x0A}, {0x516, 0x0A}, {0x525, 0x4F}, {0x550, 0x10}, 51 {0x551, 0x10}, {0x559, 0x02}, {0x55C, 0x28}, {0x55D, 0xFF}, 52 {0x605, 0x30}, {0x608, 0x0E}, {0x609, 0x2A}, {0x620, 0xFF}, 53 {0x621, 0xFF}, {0x622, 0xFF}, {0x623, 0xFF}, {0x624, 0xFF}, 54 {0x625, 0xFF}, {0x626, 0xFF}, {0x627, 0xFF}, {0x638, 0x28}, 55 {0x63C, 0x0A}, {0x63D, 0x0A}, {0x63E, 0x0E}, {0x63F, 0x0E}, 56 {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xC8}, 57 {0x66E, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, 58 {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70A, 0x65}, 59 {0x70B, 0x87}, 60 {0xffff, 0xff}, 61 }; 62 63 static const struct rtl8xxxu_reg32val rtl8188fu_phy_init_table[] = { 64 {0x800, 0x80045700}, {0x804, 0x00000001}, 65 {0x808, 0x0000FC00}, {0x80C, 0x0000000A}, 66 {0x810, 0x10001331}, {0x814, 0x020C3D10}, 67 {0x818, 0x00200385}, {0x81C, 0x00000000}, 68 {0x820, 0x01000100}, {0x824, 0x00390204}, 69 {0x828, 0x00000000}, {0x82C, 0x00000000}, 70 {0x830, 0x00000000}, {0x834, 0x00000000}, 71 {0x838, 0x00000000}, {0x83C, 0x00000000}, 72 {0x840, 0x00010000}, {0x844, 0x00000000}, 73 {0x848, 0x00000000}, {0x84C, 0x00000000}, 74 {0x850, 0x00030000}, {0x854, 0x00000000}, 75 {0x858, 0x569A569A}, {0x85C, 0x569A569A}, 76 {0x860, 0x00000130}, {0x864, 0x00000000}, 77 {0x868, 0x00000000}, {0x86C, 0x27272700}, 78 {0x870, 0x00000000}, {0x874, 0x25004000}, 79 {0x878, 0x00000808}, {0x87C, 0x004F0201}, 80 {0x880, 0xB0000B1E}, {0x884, 0x00000007}, 81 {0x888, 0x00000000}, {0x88C, 0xCCC000C0}, 82 {0x890, 0x00000800}, {0x894, 0xFFFFFFFE}, 83 {0x898, 0x40302010}, {0x89C, 0x00706050}, 84 {0x900, 0x00000000}, {0x904, 0x00000023}, 85 {0x908, 0x00000000}, {0x90C, 0x81121111}, 86 {0x910, 0x00000002}, {0x914, 0x00000201}, 87 {0x948, 0x99000000}, {0x94C, 0x00000010}, 88 {0x950, 0x20003000}, {0x954, 0x4A880000}, 89 {0x958, 0x4BC5D87A}, {0x95C, 0x04EB9B79}, 90 {0x96C, 0x00000003}, {0xA00, 0x00D047C8}, 91 {0xA04, 0x80FF800C}, {0xA08, 0x8C898300}, 92 {0xA0C, 0x2E7F120F}, {0xA10, 0x9500BB78}, 93 {0xA14, 0x1114D028}, {0xA18, 0x00881117}, 94 {0xA1C, 0x89140F00}, {0xA20, 0xD1D80000}, 95 {0xA24, 0x5A7DA0BD}, {0xA28, 0x0000223B}, 96 {0xA2C, 0x00D30000}, {0xA70, 0x101FBF00}, 97 {0xA74, 0x00000007}, {0xA78, 0x00000900}, 98 {0xA7C, 0x225B0606}, {0xA80, 0x218075B1}, 99 {0xA84, 0x00120000}, {0xA88, 0x040C0000}, 100 {0xA8C, 0x12345678}, {0xA90, 0xABCDEF00}, 101 {0xA94, 0x001B1B89}, {0xA98, 0x05100000}, 102 {0xA9C, 0x3F000000}, {0xAA0, 0x00000000}, 103 {0xB2C, 0x00000000}, {0xC00, 0x48071D40}, 104 {0xC04, 0x03A05611}, {0xC08, 0x000000E4}, 105 {0xC0C, 0x6C6C6C6C}, {0xC10, 0x18800000}, 106 {0xC14, 0x40000100}, {0xC18, 0x08800000}, 107 {0xC1C, 0x40000100}, {0xC20, 0x00000000}, 108 {0xC24, 0x00000000}, {0xC28, 0x00000000}, 109 {0xC2C, 0x00000000}, {0xC30, 0x69E9CC4A}, 110 {0xC34, 0x31000040}, {0xC38, 0x21688080}, 111 {0xC3C, 0x00001714}, {0xC40, 0x1F78403F}, 112 {0xC44, 0x00010036}, {0xC48, 0xEC020107}, 113 {0xC4C, 0x007F037F}, {0xC50, 0x69553420}, 114 {0xC54, 0x43BC0094}, {0xC58, 0x00013169}, 115 {0xC5C, 0x00250492}, {0xC60, 0x00000000}, 116 {0xC64, 0x7112848B}, {0xC68, 0x47C07BFF}, 117 {0xC6C, 0x00000036}, {0xC70, 0x2C7F000D}, 118 {0xC74, 0x020600DB}, {0xC78, 0x0000001F}, 119 {0xC7C, 0x00B91612}, {0xC80, 0x390000E4}, 120 {0xC84, 0x11F60000}, 121 {0xC88, 0x40000100}, {0xC8C, 0x20200000}, 122 {0xC90, 0x00091521}, {0xC94, 0x00000000}, 123 {0xC98, 0x00121820}, {0xC9C, 0x00007F7F}, 124 {0xCA0, 0x00000000}, {0xCA4, 0x000300A0}, 125 {0xCA8, 0x00000000}, {0xCAC, 0x00000000}, 126 {0xCB0, 0x00000000}, {0xCB4, 0x00000000}, 127 {0xCB8, 0x00000000}, {0xCBC, 0x28000000}, 128 {0xCC0, 0x00000000}, {0xCC4, 0x00000000}, 129 {0xCC8, 0x00000000}, {0xCCC, 0x00000000}, 130 {0xCD0, 0x00000000}, {0xCD4, 0x00000000}, 131 {0xCD8, 0x64B22427}, {0xCDC, 0x00766932}, 132 {0xCE0, 0x00222222}, {0xCE4, 0x10000000}, 133 {0xCE8, 0x37644302}, {0xCEC, 0x2F97D40C}, 134 {0xD00, 0x04030740}, {0xD04, 0x40020401}, 135 {0xD08, 0x0000907F}, {0xD0C, 0x20010201}, 136 {0xD10, 0xA0633333}, {0xD14, 0x3333BC53}, 137 {0xD18, 0x7A8F5B6F}, {0xD2C, 0xCB979975}, 138 {0xD30, 0x00000000}, {0xD34, 0x80608000}, 139 {0xD38, 0x98000000}, {0xD3C, 0x40127353}, 140 {0xD40, 0x00000000}, {0xD44, 0x00000000}, 141 {0xD48, 0x00000000}, {0xD4C, 0x00000000}, 142 {0xD50, 0x6437140A}, {0xD54, 0x00000000}, 143 {0xD58, 0x00000282}, {0xD5C, 0x30032064}, 144 {0xD60, 0x4653DE68}, {0xD64, 0x04518A3C}, 145 {0xD68, 0x00002101}, {0xD6C, 0x2A201C16}, 146 {0xD70, 0x1812362E}, {0xD74, 0x322C2220}, 147 {0xD78, 0x000E3C24}, {0xE00, 0x2D2D2D2D}, 148 {0xE04, 0x2D2D2D2D}, {0xE08, 0x0390272D}, 149 {0xE10, 0x2D2D2D2D}, {0xE14, 0x2D2D2D2D}, 150 {0xE18, 0x2D2D2D2D}, {0xE1C, 0x2D2D2D2D}, 151 {0xE28, 0x00000000}, {0xE30, 0x1000DC1F}, 152 {0xE34, 0x10008C1F}, {0xE38, 0x02140102}, 153 {0xE3C, 0x681604C2}, {0xE40, 0x01007C00}, 154 {0xE44, 0x01004800}, {0xE48, 0xFB000000}, 155 {0xE4C, 0x000028D1}, {0xE50, 0x1000DC1F}, 156 {0xE54, 0x10008C1F}, {0xE58, 0x02140102}, 157 {0xE5C, 0x28160D05}, {0xE60, 0x00000008}, 158 {0xE60, 0x021400A0}, {0xE64, 0x281600A0}, 159 {0xE6C, 0x01C00010}, {0xE70, 0x01C00010}, 160 {0xE74, 0x02000010}, {0xE78, 0x02000010}, 161 {0xE7C, 0x02000010}, {0xE80, 0x02000010}, 162 {0xE84, 0x01C00010}, {0xE88, 0x02000010}, 163 {0xE8C, 0x01C00010}, {0xED0, 0x01C00010}, 164 {0xED4, 0x01C00010}, {0xED8, 0x01C00010}, 165 {0xEDC, 0x00000010}, {0xEE0, 0x00000010}, 166 {0xEEC, 0x03C00010}, {0xF14, 0x00000003}, 167 {0xF4C, 0x00000000}, {0xF00, 0x00000300}, 168 {0xffff, 0xffffffff}, 169 }; 170 171 static const struct rtl8xxxu_reg32val rtl8188f_agc_table[] = { 172 {0xC78, 0xFC000001}, {0xC78, 0xFB010001}, 173 {0xC78, 0xFA020001}, {0xC78, 0xF9030001}, 174 {0xC78, 0xF8040001}, {0xC78, 0xF7050001}, 175 {0xC78, 0xF6060001}, {0xC78, 0xF5070001}, 176 {0xC78, 0xF4080001}, {0xC78, 0xF3090001}, 177 {0xC78, 0xF20A0001}, {0xC78, 0xF10B0001}, 178 {0xC78, 0xF00C0001}, {0xC78, 0xEF0D0001}, 179 {0xC78, 0xEE0E0001}, {0xC78, 0xED0F0001}, 180 {0xC78, 0xEC100001}, {0xC78, 0xEB110001}, 181 {0xC78, 0xEA120001}, {0xC78, 0xE9130001}, 182 {0xC78, 0xE8140001}, {0xC78, 0xE7150001}, 183 {0xC78, 0xE6160001}, {0xC78, 0xE5170001}, 184 {0xC78, 0xE4180001}, {0xC78, 0xE3190001}, 185 {0xC78, 0xE21A0001}, {0xC78, 0xE11B0001}, 186 {0xC78, 0xE01C0001}, {0xC78, 0xC21D0001}, 187 {0xC78, 0xC11E0001}, {0xC78, 0xC01F0001}, 188 {0xC78, 0xA5200001}, {0xC78, 0xA4210001}, 189 {0xC78, 0xA3220001}, {0xC78, 0xA2230001}, 190 {0xC78, 0xA1240001}, {0xC78, 0xA0250001}, 191 {0xC78, 0x65260001}, {0xC78, 0x64270001}, 192 {0xC78, 0x63280001}, {0xC78, 0x62290001}, 193 {0xC78, 0x612A0001}, {0xC78, 0x442B0001}, 194 {0xC78, 0x432C0001}, {0xC78, 0x422D0001}, 195 {0xC78, 0x412E0001}, {0xC78, 0x402F0001}, 196 {0xC78, 0x21300001}, {0xC78, 0x20310001}, 197 {0xC78, 0x05320001}, {0xC78, 0x04330001}, 198 {0xC78, 0x03340001}, {0xC78, 0x02350001}, 199 {0xC78, 0x01360001}, {0xC78, 0x00370001}, 200 {0xC78, 0x00380001}, {0xC78, 0x00390001}, 201 {0xC78, 0x003A0001}, {0xC78, 0x003B0001}, 202 {0xC78, 0x003C0001}, {0xC78, 0x003D0001}, 203 {0xC78, 0x003E0001}, {0xC78, 0x003F0001}, 204 {0xC50, 0x69553422}, {0xC50, 0x69553420}, 205 {0xffff, 0xffffffff} 206 }; 207 208 static const struct rtl8xxxu_rfregval rtl8188fu_radioa_init_table[] = { 209 {0x00, 0x00030000}, {0x08, 0x00008400}, 210 {0x18, 0x00000407}, {0x19, 0x00000012}, 211 {0x1B, 0x00001C6C}, 212 {0x1E, 0x00080009}, {0x1F, 0x00000880}, 213 {0x2F, 0x0001A060}, {0x3F, 0x00028000}, 214 {0x42, 0x000060C0}, {0x57, 0x000D0000}, 215 {0x58, 0x000C0160}, {0x67, 0x00001552}, 216 {0x83, 0x00000000}, {0xB0, 0x000FF9F0}, 217 {0xB1, 0x00022218}, {0xB2, 0x00034C00}, 218 {0xB4, 0x0004484B}, {0xB5, 0x0000112A}, 219 {0xB6, 0x0000053E}, {0xB7, 0x00010408}, 220 {0xB8, 0x00010200}, {0xB9, 0x00080001}, 221 {0xBA, 0x00040001}, {0xBB, 0x00000400}, 222 {0xBF, 0x000C0000}, {0xC2, 0x00002400}, 223 {0xC3, 0x00000009}, {0xC4, 0x00040C91}, 224 {0xC5, 0x00099999}, {0xC6, 0x000000A3}, 225 {0xC7, 0x0008F820}, {0xC8, 0x00076C06}, 226 {0xC9, 0x00000000}, {0xCA, 0x00080000}, 227 {0xDF, 0x00000180}, {0xEF, 0x000001A0}, 228 {0x51, 0x000E8333}, {0x52, 0x000FAC2C}, 229 {0x53, 0x00000103}, {0x56, 0x000517F0}, 230 {0x35, 0x00000099}, {0x35, 0x00000199}, 231 {0x35, 0x00000299}, {0x36, 0x00000064}, 232 {0x36, 0x00008064}, {0x36, 0x00010064}, 233 {0x36, 0x00018064}, {0x18, 0x00000C07}, 234 {0x5A, 0x00048000}, {0x19, 0x000739D0}, 235 {0x34, 0x0000ADD6}, {0x34, 0x00009DD3}, 236 {0x34, 0x00008CF4}, {0x34, 0x00007CF1}, 237 {0x34, 0x00006CEE}, {0x34, 0x00005CEB}, 238 {0x34, 0x00004CCE}, {0x34, 0x00003CCB}, 239 {0x34, 0x00002CC8}, {0x34, 0x00001C4B}, 240 {0x34, 0x00000C48}, 241 {0x00, 0x00030159}, {0x84, 0x00048000}, 242 {0x86, 0x0000002A}, {0x87, 0x00000025}, 243 {0x8E, 0x00065540}, {0x8F, 0x00088000}, 244 {0xEF, 0x000020A0}, {0x3B, 0x000F0F00}, 245 {0x3B, 0x000E0B00}, {0x3B, 0x000D0900}, 246 {0x3B, 0x000C0700}, {0x3B, 0x000B0600}, 247 {0x3B, 0x000A0400}, {0x3B, 0x00090200}, 248 {0x3B, 0x00080000}, {0x3B, 0x0007BF00}, 249 {0x3B, 0x00060B00}, {0x3B, 0x0005C900}, 250 {0x3B, 0x00040700}, {0x3B, 0x00030600}, 251 {0x3B, 0x0002D500}, {0x3B, 0x00010200}, 252 {0x3B, 0x0000E000}, {0xEF, 0x000000A0}, 253 {0xEF, 0x00000010}, {0x3B, 0x0000C0A8}, 254 {0x3B, 0x00010400}, {0xEF, 0x00000000}, 255 {0xEF, 0x00080000}, {0x30, 0x00010000}, 256 {0x31, 0x0000000F}, {0x32, 0x00007EFE}, 257 {0xEF, 0x00000000}, {0x00, 0x00010159}, 258 {0x18, 0x0000FC07}, {0xFE, 0x00000000}, 259 {0xFE, 0x00000000}, {0x1F, 0x00080003}, 260 {0xFE, 0x00000000}, {0xFE, 0x00000000}, 261 {0x1E, 0x00000001}, {0x1F, 0x00080000}, 262 {0x00, 0x00033D95}, 263 {0xff, 0xffffffff} 264 }; 265 266 static const struct rtl8xxxu_rfregval rtl8188fu_cut_b_radioa_init_table[] = { 267 {0x00, 0x00030000}, {0x08, 0x00008400}, 268 {0x18, 0x00000407}, {0x19, 0x00000012}, 269 {0x1B, 0x00001C6C}, 270 {0x1E, 0x00080009}, {0x1F, 0x00000880}, 271 {0x2F, 0x0001A060}, {0x3F, 0x00028000}, 272 {0x42, 0x000060C0}, {0x57, 0x000D0000}, 273 {0x58, 0x000C0160}, {0x67, 0x00001552}, 274 {0x83, 0x00000000}, {0xB0, 0x000FF9F0}, 275 {0xB1, 0x00022218}, {0xB2, 0x00034C00}, 276 {0xB4, 0x0004484B}, {0xB5, 0x0000112A}, 277 {0xB6, 0x0000053E}, {0xB7, 0x00010408}, 278 {0xB8, 0x00010200}, {0xB9, 0x00080001}, 279 {0xBA, 0x00040001}, {0xBB, 0x00000400}, 280 {0xBF, 0x000C0000}, {0xC2, 0x00002400}, 281 {0xC3, 0x00000009}, {0xC4, 0x00040C91}, 282 {0xC5, 0x00099999}, {0xC6, 0x000000A3}, 283 {0xC7, 0x0008F820}, {0xC8, 0x00076C06}, 284 {0xC9, 0x00000000}, {0xCA, 0x00080000}, 285 {0xDF, 0x00000180}, {0xEF, 0x000001A0}, 286 {0x51, 0x000E8231}, {0x52, 0x000FAC2C}, 287 {0x53, 0x00000141}, {0x56, 0x000517F0}, 288 {0x35, 0x00000090}, {0x35, 0x00000190}, 289 {0x35, 0x00000290}, {0x36, 0x00001064}, 290 {0x36, 0x00009064}, {0x36, 0x00011064}, 291 {0x36, 0x00019064}, {0x18, 0x00000C07}, 292 {0x5A, 0x00048000}, {0x19, 0x000739D0}, 293 {0x34, 0x0000ADD2}, {0x34, 0x00009DD0}, 294 {0x34, 0x00008CF3}, {0x34, 0x00007CF0}, 295 {0x34, 0x00006CED}, {0x34, 0x00005CD2}, 296 {0x34, 0x00004CCF}, {0x34, 0x00003CCC}, 297 {0x34, 0x00002CC9}, {0x34, 0x00001C4C}, 298 {0x34, 0x00000C49}, 299 {0x00, 0x00030159}, {0x84, 0x00048000}, 300 {0x86, 0x0000002A}, {0x87, 0x00000025}, 301 {0x8E, 0x00065540}, {0x8F, 0x00088000}, 302 {0xEF, 0x000020A0}, {0x3B, 0x000F0F00}, 303 {0x3B, 0x000E0B00}, {0x3B, 0x000D0900}, 304 {0x3B, 0x000C0700}, {0x3B, 0x000B0600}, 305 {0x3B, 0x000A0400}, {0x3B, 0x00090200}, 306 {0x3B, 0x00080000}, {0x3B, 0x0007BF00}, 307 {0x3B, 0x00060B00}, {0x3B, 0x0005C900}, 308 {0x3B, 0x00040700}, {0x3B, 0x00030600}, 309 {0x3B, 0x0002D500}, {0x3B, 0x00010200}, 310 {0x3B, 0x0000E000}, {0xEF, 0x000000A0}, 311 {0xEF, 0x00000010}, {0x3B, 0x0000C0A8}, 312 {0x3B, 0x00010400}, {0xEF, 0x00000000}, 313 {0xEF, 0x00080000}, {0x30, 0x00010000}, 314 {0x31, 0x0000000F}, {0x32, 0x00007EFE}, 315 {0xEF, 0x00000000}, {0x00, 0x00010159}, 316 {0x18, 0x0000FC07}, {0xFE, 0x00000000}, 317 {0xFE, 0x00000000}, {0x1F, 0x00080003}, 318 {0xFE, 0x00000000}, {0xFE, 0x00000000}, 319 {0x1E, 0x00000001}, {0x1F, 0x00080000}, 320 {0x00, 0x00033D95}, 321 {0xff, 0xffffffff} 322 }; 323 324 static void rtl8xxxu_8188f_channel_to_group(int channel, int *group, int *cck_group) 325 { 326 if (channel < 3) 327 *group = 0; 328 else if (channel < 6) 329 *group = 1; 330 else if (channel < 9) 331 *group = 2; 332 else if (channel < 12) 333 *group = 3; 334 else 335 *group = 4; 336 337 if (channel == 14) 338 *cck_group = 5; 339 else 340 *cck_group = *group; 341 } 342 343 static void 344 rtl8188f_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) 345 { 346 u32 val32, ofdm, mcs; 347 u8 cck, ofdmbase, mcsbase; 348 int group, cck_group; 349 350 rtl8xxxu_8188f_channel_to_group(channel, &group, &cck_group); 351 352 cck = priv->cck_tx_power_index_A[cck_group]; 353 354 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); 355 val32 &= 0xffff00ff; 356 val32 |= (cck << 8); 357 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); 358 359 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); 360 val32 &= 0xff; 361 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); 362 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); 363 364 ofdmbase = priv->ht40_1s_tx_power_index_A[group]; 365 ofdmbase += priv->ofdm_tx_power_diff[0].a; 366 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; 367 368 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); 369 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); 370 371 mcsbase = priv->ht40_1s_tx_power_index_A[group]; 372 if (ht40) 373 /* This diff is always 0 - not used in 8188FU. */ 374 mcsbase += priv->ht40_tx_power_diff[0].a; 375 else 376 mcsbase += priv->ht20_tx_power_diff[0].a; 377 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; 378 379 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); 380 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); 381 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); 382 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); 383 } 384 385 /* A workaround to eliminate the 2400MHz, 2440MHz, 2480MHz spur of 8188F. */ 386 static void rtl8188f_spur_calibration(struct rtl8xxxu_priv *priv, u8 channel) 387 { 388 static const u32 frequencies[14 + 1] = { 389 [5] = 0xFCCD, 390 [6] = 0xFC4D, 391 [7] = 0xFFCD, 392 [8] = 0xFF4D, 393 [11] = 0xFDCD, 394 [13] = 0xFCCD, 395 [14] = 0xFF9A 396 }; 397 398 static const u32 reg_d40[14 + 1] = { 399 [5] = 0x06000000, 400 [6] = 0x00000600, 401 [13] = 0x06000000 402 }; 403 404 static const u32 reg_d44[14 + 1] = { 405 [11] = 0x04000000 406 }; 407 408 static const u32 reg_d4c[14 + 1] = { 409 [7] = 0x06000000, 410 [8] = 0x00000380, 411 [14] = 0x00180000 412 }; 413 414 const u8 threshold = 0x16; 415 bool do_notch, hw_ctrl, sw_ctrl, hw_ctrl_s1 = 0, sw_ctrl_s1 = 0; 416 u32 val32, initial_gain, reg948; 417 418 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); 419 val32 |= GENMASK(28, 24); 420 rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); 421 422 /* enable notch filter */ 423 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); 424 val32 |= BIT(9); 425 rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); 426 427 if (channel <= 14 && frequencies[channel] > 0) { 428 reg948 = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); 429 hw_ctrl = reg948 & BIT(6); 430 sw_ctrl = !hw_ctrl; 431 432 if (hw_ctrl) { 433 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); 434 val32 &= GENMASK(5, 3); 435 hw_ctrl_s1 = val32 == BIT(3); 436 } else if (sw_ctrl) { 437 sw_ctrl_s1 = !(reg948 & BIT(9)); 438 } 439 440 if (hw_ctrl_s1 || sw_ctrl_s1) { 441 initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 442 443 /* Disable CCK block */ 444 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 445 val32 &= ~FPGA_RF_MODE_CCK; 446 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 447 448 val32 = initial_gain & ~OFDM0_X_AGC_CORE1_IGI_MASK; 449 val32 |= 0x30; 450 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); 451 452 /* disable 3-wire */ 453 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); 454 455 /* Setup PSD */ 456 rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); 457 458 /* Start PSD */ 459 rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, 0x400000 | frequencies[channel]); 460 461 msleep(30); 462 463 do_notch = rtl8xxxu_read32(priv, REG_FPGA0_PSD_REPORT) >= threshold; 464 465 /* turn off PSD */ 466 rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); 467 468 /* enable 3-wire */ 469 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccc000c0); 470 471 /* Enable CCK block */ 472 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 473 val32 |= FPGA_RF_MODE_CCK; 474 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 475 476 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, initial_gain); 477 478 if (do_notch) { 479 rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK1, reg_d40[channel]); 480 rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK2, reg_d44[channel]); 481 rtl8xxxu_write32(priv, 0xd48, 0x0); 482 rtl8xxxu_write32(priv, 0xd4c, reg_d4c[channel]); 483 484 /* enable CSI mask */ 485 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 486 val32 |= BIT(28); 487 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); 488 489 return; 490 } 491 } 492 } 493 494 /* disable CSI mask function */ 495 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); 496 val32 &= ~BIT(28); 497 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); 498 } 499 500 static void rtl8188fu_config_channel(struct ieee80211_hw *hw) 501 { 502 struct rtl8xxxu_priv *priv = hw->priv; 503 u32 val32; 504 u8 channel, subchannel; 505 bool sec_ch_above; 506 507 channel = (u8)hw->conf.chandef.chan->hw_value; 508 509 /* Set channel */ 510 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 511 val32 &= ~MODE_AG_CHANNEL_MASK; 512 val32 |= channel; 513 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 514 515 /* Spur calibration */ 516 rtl8188f_spur_calibration(priv, channel); 517 518 /* Set bandwidth mode */ 519 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 520 val32 &= ~FPGA_RF_MODE; 521 val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; 522 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 523 524 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 525 val32 &= ~FPGA_RF_MODE; 526 val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; 527 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 528 529 /* RXADC CLK */ 530 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 531 val32 |= GENMASK(10, 8); 532 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 533 534 /* TXDAC CLK */ 535 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 536 val32 |= BIT(14) | BIT(12); 537 val32 &= ~BIT(13); 538 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 539 540 /* small BW */ 541 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 542 val32 &= ~GENMASK(31, 30); 543 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 544 545 /* adc buffer clk */ 546 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 547 val32 &= ~BIT(29); 548 val32 |= BIT(28); 549 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 550 551 /* adc buffer clk */ 552 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_AFE); 553 val32 &= ~BIT(29); 554 val32 |= BIT(28); 555 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_AFE, val32); 556 557 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); 558 val32 &= ~BIT(19); 559 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); 560 561 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); 562 val32 &= ~GENMASK(23, 20); 563 val32 |= BIT(21); 564 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || 565 hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) 566 val32 |= BIT(20); 567 else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 568 val32 |= BIT(22); 569 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); 570 571 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) { 572 if (hw->conf.chandef.center_freq1 > 573 hw->conf.chandef.chan->center_freq) { 574 sec_ch_above = 1; 575 channel += 2; 576 } else { 577 sec_ch_above = 0; 578 channel -= 2; 579 } 580 581 /* Set Control channel to upper or lower. */ 582 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 583 val32 &= ~CCK0_SIDEBAND; 584 if (!sec_ch_above) 585 val32 |= CCK0_SIDEBAND; 586 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 587 588 val32 = rtl8xxxu_read32(priv, REG_DATA_SUBCHANNEL); 589 val32 &= ~GENMASK(3, 0); 590 if (sec_ch_above) 591 subchannel = 2; 592 else 593 subchannel = 1; 594 val32 |= subchannel; 595 rtl8xxxu_write32(priv, REG_DATA_SUBCHANNEL, val32); 596 597 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 598 val32 &= ~RSR_RSC_BANDWIDTH_40M; 599 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); 600 } 601 602 /* RF TRX_BW */ 603 val32 = channel; 604 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || 605 hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) 606 val32 |= MODE_AG_BW_20MHZ_8723B; 607 else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 608 val32 |= MODE_AG_BW_40MHZ_8723B; 609 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 610 611 /* FILTER BW&RC Corner (ACPR) */ 612 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || 613 hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) 614 val32 = 0x00065; 615 else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 616 val32 = 0x00025; 617 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RXG_MIX_SWBW, val32); 618 619 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || 620 hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) 621 val32 = 0x0; 622 else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 623 val32 = 0x01000; 624 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_BB2, val32); 625 626 /* RC Corner */ 627 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00140); 628 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_G2, 0x01c6c); 629 } 630 631 static void rtl8188fu_init_aggregation(struct rtl8xxxu_priv *priv) 632 { 633 u8 agg_ctrl, rxdma_mode, usb_tx_agg_desc_num = 6; 634 u32 agg_rx, val32; 635 636 /* TX aggregation */ 637 val32 = rtl8xxxu_read32(priv, REG_DWBCN0_CTRL_8188F); 638 val32 &= ~(0xf << 4); 639 val32 |= usb_tx_agg_desc_num << 4; 640 rtl8xxxu_write32(priv, REG_DWBCN0_CTRL_8188F, val32); 641 rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B, usb_tx_agg_desc_num << 1); 642 643 /* RX aggregation */ 644 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); 645 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; 646 647 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); 648 agg_rx &= ~RXDMA_USB_AGG_ENABLE; 649 agg_rx &= ~0xFF0F; /* reset agg size and timeout */ 650 651 rxdma_mode = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); 652 rxdma_mode &= ~BIT(1); 653 654 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 655 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); 656 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, rxdma_mode); 657 } 658 659 static void rtl8188fu_init_statistics(struct rtl8xxxu_priv *priv) 660 { 661 u32 val32; 662 663 /* Time duration for NHM unit: 4us, 0xc350=200ms */ 664 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0xc350); 665 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); 666 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff50); 667 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); 668 669 /* TH8 */ 670 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 671 val32 |= 0xff; 672 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 673 674 /* Enable CCK */ 675 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); 676 val32 &= ~(BIT(8) | BIT(9) | BIT(10)); 677 val32 |= BIT(8); 678 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); 679 680 /* Max power amongst all RX antennas */ 681 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); 682 val32 |= BIT(7); 683 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); 684 } 685 686 static int rtl8188fu_parse_efuse(struct rtl8xxxu_priv *priv) 687 { 688 struct rtl8188fu_efuse *efuse = &priv->efuse_wifi.efuse8188fu; 689 int i; 690 691 if (efuse->rtl_id != cpu_to_le16(0x8129)) 692 return -EINVAL; 693 694 ether_addr_copy(priv->mac_addr, efuse->mac_addr); 695 696 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, 697 sizeof(efuse->tx_power_index_A.cck_base)); 698 699 memcpy(priv->ht40_1s_tx_power_index_A, 700 efuse->tx_power_index_A.ht40_base, 701 sizeof(efuse->tx_power_index_A.ht40_base)); 702 703 priv->ofdm_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.a; 704 priv->ht20_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; 705 706 priv->xtalk = efuse->xtal_k & 0x3f; 707 708 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name); 709 dev_info(&priv->udev->dev, "Product: %.7s\n", efuse->device_name); 710 711 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) { 712 unsigned char *raw = priv->efuse_wifi.raw; 713 714 dev_info(&priv->udev->dev, 715 "%s: dumping efuse (0x%02zx bytes):\n", 716 __func__, sizeof(struct rtl8188fu_efuse)); 717 for (i = 0; i < sizeof(struct rtl8188fu_efuse); i += 8) 718 dev_info(&priv->udev->dev, "%02x: %8ph\n", i, &raw[i]); 719 } 720 721 return 0; 722 } 723 724 static int rtl8188fu_load_firmware(struct rtl8xxxu_priv *priv) 725 { 726 char *fw_name; 727 int ret; 728 729 fw_name = "rtlwifi/rtl8188fufw.bin"; 730 731 ret = rtl8xxxu_load_firmware(priv, fw_name); 732 733 return ret; 734 } 735 736 static void rtl8188fu_init_phy_bb(struct rtl8xxxu_priv *priv) 737 { 738 u8 val8; 739 u16 val16; 740 u32 val32; 741 742 /* Enable BB and RF */ 743 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 744 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; 745 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 746 747 /* 748 * Per vendor driver, run power sequence before init of RF 749 */ 750 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; 751 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 752 753 usleep_range(10, 20); 754 755 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); 756 757 val8 = SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_USBA | SYS_FUNC_USBD; 758 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 759 760 rtl8xxxu_init_phy_regs(priv, rtl8188fu_phy_init_table); 761 rtl8xxxu_init_phy_regs(priv, rtl8188f_agc_table); 762 763 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); 764 val8 = priv->xtalk; 765 val32 &= ~0x007FF800; 766 val32 |= ((val8 | (val8 << 6)) << 11); 767 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); 768 } 769 770 static int rtl8188fu_init_phy_rf(struct rtl8xxxu_priv *priv) 771 { 772 int ret; 773 774 if (priv->chip_cut == 1) 775 ret = rtl8xxxu_init_phy_rf(priv, rtl8188fu_cut_b_radioa_init_table, RF_A); 776 else 777 ret = rtl8xxxu_init_phy_rf(priv, rtl8188fu_radioa_init_table, RF_A); 778 779 return ret; 780 } 781 782 static void rtl8188f_phy_lc_calibrate(struct rtl8xxxu_priv *priv) 783 { 784 u32 val32; 785 u32 rf_amode, lstf; 786 int i; 787 788 /* Check continuous TX and Packet TX */ 789 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 790 791 if (lstf & OFDM_LSTF_MASK) { 792 /* Disable all continuous TX */ 793 val32 = lstf & ~OFDM_LSTF_MASK; 794 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 795 } else { 796 /* Deal with Packet TX case */ 797 /* block all queues */ 798 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 799 } 800 801 /* Read original RF mode Path A */ 802 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 803 804 /* Start LC calibration */ 805 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, rf_amode | 0x08000); 806 807 for (i = 0; i < 100; i++) { 808 if ((rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG) & 0x08000) == 0) 809 break; 810 msleep(10); 811 } 812 813 if (i == 100) 814 dev_warn(&priv->udev->dev, "LC calibration timed out.\n"); 815 816 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, rf_amode); 817 818 /* Restore original parameters */ 819 if (lstf & OFDM_LSTF_MASK) 820 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); 821 else /* Deal with Packet TX case */ 822 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 823 } 824 825 static int rtl8188fu_iqk_path_a(struct rtl8xxxu_priv *priv, u32 *lok_result) 826 { 827 u32 reg_eac, reg_e94, reg_e9c, val32; 828 int result = 0; 829 830 /* 831 * Leave IQK mode 832 */ 833 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 834 val32 &= 0x000000ff; 835 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 836 837 /* 838 * Enable path A PA in TX IQK mode 839 */ 840 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 841 val32 |= 0x80000; 842 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 843 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); 844 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); 845 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07ff7); 846 847 /* PA,PAD gain adjust */ 848 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x980); 849 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x5102a); 850 851 /* enter IQK mode */ 852 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 853 val32 &= 0x000000ff; 854 val32 |= 0x80800000; 855 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 856 857 /* path-A IQK setting */ 858 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); 859 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 860 861 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ff); 862 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); 863 864 /* LO calibration setting */ 865 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); 866 867 /* One shot, path A LOK & IQK */ 868 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 869 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 870 871 mdelay(25); 872 873 /* 874 * Leave IQK mode 875 */ 876 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 877 val32 &= 0x000000ff; 878 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 879 880 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); 881 882 /* save LOK result */ 883 *lok_result = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC); 884 885 /* Check failed */ 886 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 887 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 888 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 889 890 if (!(reg_eac & BIT(28)) && 891 ((reg_e94 & 0x03ff0000) != 0x01420000) && 892 ((reg_e9c & 0x03ff0000) != 0x00420000)) 893 result |= 0x01; 894 895 return result; 896 } 897 898 static int rtl8188fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result) 899 { 900 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; 901 int result = 0; 902 903 /* 904 * Leave IQK mode 905 */ 906 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 907 val32 &= 0x000000ff; 908 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 909 910 /* 911 * Enable path A PA in TX IQK mode 912 */ 913 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 914 val32 |= 0x80000; 915 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 916 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 917 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); 918 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); 919 920 /* PA,PAD gain adjust */ 921 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x980); 922 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x5102a); 923 924 /* 925 * Enter IQK mode 926 */ 927 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 928 val32 &= 0x000000ff; 929 val32 |= 0x80800000; 930 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 931 932 /* 933 * Tx IQK setting 934 */ 935 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 936 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 937 938 /* path-A IQK setting */ 939 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c); 940 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c); 941 942 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160fff); 943 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); 944 945 /* LO calibration setting */ 946 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); 947 948 /* One shot, path A LOK & IQK */ 949 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 950 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 951 952 mdelay(25); 953 954 /* 955 * Leave IQK mode 956 */ 957 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 958 val32 &= 0x000000ff; 959 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 960 961 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); 962 963 /* Check failed */ 964 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 965 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 966 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 967 968 if (!(reg_eac & BIT(28)) && 969 ((reg_e94 & 0x03ff0000) != 0x01420000) && 970 ((reg_e9c & 0x03ff0000) != 0x00420000)) 971 result |= 0x01; 972 else /* If TX not OK, ignore RX */ 973 goto out; 974 975 val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | 976 ((reg_e9c & 0x3ff0000) >> 16); 977 rtl8xxxu_write32(priv, REG_TX_IQK, val32); 978 979 /* 980 * Modify RX IQK mode table 981 */ 982 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 983 val32 &= 0x000000ff; 984 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 985 986 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); 987 val32 |= 0x80000; 988 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); 989 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 990 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); 991 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); 992 993 /* 994 * PA, PAD setting 995 */ 996 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x980); 997 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000); 998 999 /* 1000 * Enter IQK mode 1001 */ 1002 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1003 val32 &= 0x000000ff; 1004 val32 |= 0x80800000; 1005 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1006 1007 /* 1008 * RX IQK setting 1009 */ 1010 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 1011 1012 /* path-A IQK setting */ 1013 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x30008c1c); 1014 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1c); 1015 1016 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160000); 1017 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281613ff); 1018 1019 /* LO calibration setting */ 1020 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); 1021 1022 /* One shot, path A LOK & IQK */ 1023 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 1024 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 1025 1026 mdelay(25); 1027 1028 /* 1029 * Leave IQK mode 1030 */ 1031 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1032 val32 &= 0x000000ff; 1033 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1034 1035 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); 1036 1037 /* reload LOK value */ 1038 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC, lok_result); 1039 1040 /* Check failed */ 1041 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 1042 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 1043 1044 if (!(reg_eac & BIT(27)) && 1045 ((reg_ea4 & 0x03ff0000) != 0x01320000) && 1046 ((reg_eac & 0x03ff0000) != 0x00360000)) 1047 result |= 0x02; 1048 1049 out: 1050 return result; 1051 } 1052 1053 static void rtl8188fu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, 1054 int result[][8], int t) 1055 { 1056 struct device *dev = &priv->udev->dev; 1057 u32 i, val32, rx_initial_gain, lok_result; 1058 u32 path_sel_bb, path_sel_rf; 1059 int path_a_ok; 1060 int retry = 2; 1061 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { 1062 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, 1063 REG_RX_WAIT_CCA, REG_TX_CCK_RFON, 1064 REG_TX_CCK_BBON, REG_TX_OFDM_RFON, 1065 REG_TX_OFDM_BBON, REG_TX_TO_RX, 1066 REG_TX_TO_TX, REG_RX_CCK, 1067 REG_RX_OFDM, REG_RX_WAIT_RIFS, 1068 REG_RX_TO_RX, REG_STANDBY, 1069 REG_SLEEP, REG_PMPD_ANAEN 1070 }; 1071 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { 1072 REG_TXPAUSE, REG_BEACON_CTRL, 1073 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG 1074 }; 1075 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { 1076 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, 1077 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, 1078 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, 1079 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE 1080 }; 1081 1082 /* 1083 * Note: IQ calibration must be performed after loading 1084 * PHY_REG.txt , and radio_a, radio_b.txt 1085 */ 1086 1087 rx_initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 1088 1089 if (t == 0) { 1090 /* Save ADDA parameters, turn Path A ADDA on */ 1091 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, 1092 RTL8XXXU_ADDA_REGS); 1093 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 1094 rtl8xxxu_save_regs(priv, iqk_bb_regs, 1095 priv->bb_backup, RTL8XXXU_BB_REGS); 1096 } 1097 1098 rtl8xxxu_path_adda_on(priv, adda_regs, true); 1099 1100 if (t == 0) { 1101 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); 1102 priv->pi_enabled = val32 & FPGA0_HSSI_PARM1_PI; 1103 } 1104 1105 /* save RF path */ 1106 path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); 1107 path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); 1108 1109 /* BB setting */ 1110 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); 1111 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); 1112 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x25204000); 1113 1114 /* MAC settings */ 1115 val32 = rtl8xxxu_read32(priv, REG_TX_PTCL_CTRL); 1116 val32 |= 0x00ff0000; 1117 rtl8xxxu_write32(priv, REG_TX_PTCL_CTRL, val32); 1118 1119 /* IQ calibration setting */ 1120 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1121 val32 &= 0xff; 1122 val32 |= 0x80800000; 1123 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1124 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 1125 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 1126 1127 for (i = 0; i < retry; i++) { 1128 path_a_ok = rtl8188fu_iqk_path_a(priv, &lok_result); 1129 if (path_a_ok == 0x01) { 1130 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1131 val32 &= 0xff; 1132 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1133 1134 val32 = rtl8xxxu_read32(priv, 1135 REG_TX_POWER_BEFORE_IQK_A); 1136 result[t][0] = (val32 >> 16) & 0x3ff; 1137 1138 val32 = rtl8xxxu_read32(priv, 1139 REG_TX_POWER_AFTER_IQK_A); 1140 result[t][1] = (val32 >> 16) & 0x3ff; 1141 break; 1142 } 1143 } 1144 1145 for (i = 0; i < retry; i++) { 1146 path_a_ok = rtl8188fu_rx_iqk_path_a(priv, lok_result); 1147 if (path_a_ok == 0x03) { 1148 val32 = rtl8xxxu_read32(priv, 1149 REG_RX_POWER_BEFORE_IQK_A_2); 1150 result[t][2] = (val32 >> 16) & 0x3ff; 1151 1152 val32 = rtl8xxxu_read32(priv, 1153 REG_RX_POWER_AFTER_IQK_A_2); 1154 result[t][3] = (val32 >> 16) & 0x3ff; 1155 break; 1156 } 1157 } 1158 1159 if (!path_a_ok) 1160 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); 1161 1162 /* Back to BB mode, load original value */ 1163 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 1164 val32 &= 0xff; 1165 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 1166 1167 if (t == 0) 1168 return; 1169 1170 if (!priv->pi_enabled) { 1171 /* 1172 * Switch back BB to SI mode after finishing 1173 * IQ Calibration 1174 */ 1175 val32 = 0x01000000; 1176 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); 1177 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); 1178 } 1179 1180 /* Reload ADDA power saving parameters */ 1181 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, 1182 RTL8XXXU_ADDA_REGS); 1183 1184 /* Reload MAC parameters */ 1185 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 1186 1187 /* Reload BB parameters */ 1188 rtl8xxxu_restore_regs(priv, iqk_bb_regs, 1189 priv->bb_backup, RTL8XXXU_BB_REGS); 1190 1191 /* Reload RF path */ 1192 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); 1193 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); 1194 1195 /* Restore RX initial gain */ 1196 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 1197 val32 &= 0xffffff00; 1198 val32 |= 0x50; 1199 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); 1200 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 1201 val32 &= 0xffffff00; 1202 val32 |= rx_initial_gain & 0xff; 1203 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); 1204 1205 /* Load 0xe30 IQC default value */ 1206 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); 1207 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); 1208 } 1209 1210 static void rtl8188fu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) 1211 { 1212 struct device *dev = &priv->udev->dev; 1213 int result[4][8]; /* last is final result */ 1214 int i, candidate; 1215 bool path_a_ok; 1216 u32 reg_e94, reg_e9c, reg_ea4, reg_eac; 1217 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; 1218 s32 reg_tmp = 0; 1219 bool simu; 1220 u32 path_sel_bb, path_sel_rf; 1221 1222 /* Save RF path */ 1223 path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); 1224 path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); 1225 1226 memset(result, 0, sizeof(result)); 1227 candidate = -1; 1228 1229 path_a_ok = false; 1230 1231 for (i = 0; i < 3; i++) { 1232 rtl8188fu_phy_iqcalibrate(priv, result, i); 1233 1234 if (i == 1) { 1235 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1); 1236 if (simu) { 1237 candidate = 0; 1238 break; 1239 } 1240 } 1241 1242 if (i == 2) { 1243 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2); 1244 if (simu) { 1245 candidate = 0; 1246 break; 1247 } 1248 1249 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 1, 2); 1250 if (simu) { 1251 candidate = 1; 1252 } else { 1253 for (i = 0; i < 8; i++) 1254 reg_tmp += result[3][i]; 1255 1256 if (reg_tmp) 1257 candidate = 3; 1258 else 1259 candidate = -1; 1260 } 1261 } 1262 } 1263 1264 for (i = 0; i < 4; i++) { 1265 reg_e94 = result[i][0]; 1266 reg_e9c = result[i][1]; 1267 reg_ea4 = result[i][2]; 1268 reg_eac = result[i][3]; 1269 reg_eb4 = result[i][4]; 1270 reg_ebc = result[i][5]; 1271 reg_ec4 = result[i][6]; 1272 reg_ecc = result[i][7]; 1273 } 1274 1275 if (candidate >= 0) { 1276 reg_e94 = result[candidate][0]; 1277 priv->rege94 = reg_e94; 1278 reg_e9c = result[candidate][1]; 1279 priv->rege9c = reg_e9c; 1280 reg_ea4 = result[candidate][2]; 1281 reg_eac = result[candidate][3]; 1282 reg_eb4 = result[candidate][4]; 1283 priv->regeb4 = reg_eb4; 1284 reg_ebc = result[candidate][5]; 1285 priv->regebc = reg_ebc; 1286 reg_ec4 = result[candidate][6]; 1287 reg_ecc = result[candidate][7]; 1288 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); 1289 dev_dbg(dev, 1290 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", 1291 __func__, reg_e94, reg_e9c, 1292 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); 1293 path_a_ok = true; 1294 } else { 1295 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; 1296 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; 1297 } 1298 1299 if (reg_e94 && candidate >= 0) 1300 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, 1301 candidate, (reg_ea4 == 0)); 1302 1303 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, 1304 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); 1305 1306 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); 1307 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); 1308 } 1309 1310 static void rtl8188f_disabled_to_emu(struct rtl8xxxu_priv *priv) 1311 { 1312 u16 val8; 1313 1314 /* 0x04[12:11] = 2b'01enable WL suspend */ 1315 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1316 val8 &= ~((APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND) >> 8); 1317 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1318 1319 /* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode */ 1320 val8 = rtl8xxxu_read8(priv, 0xc4); 1321 val8 &= ~BIT(4); 1322 rtl8xxxu_write8(priv, 0xc4, val8); 1323 } 1324 1325 static int rtl8188f_emu_to_active(struct rtl8xxxu_priv *priv) 1326 { 1327 u8 val8; 1328 u32 val32; 1329 int count, ret = 0; 1330 1331 /* Disable SW LPS */ 1332 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1333 val8 &= ~(APS_FSMCO_SW_LPS >> 8); 1334 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1335 1336 /* wait till 0x04[17] = 1 power ready */ 1337 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1338 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1339 if (val32 & BIT(17)) 1340 break; 1341 1342 udelay(10); 1343 } 1344 1345 if (!count) { 1346 ret = -EBUSY; 1347 goto exit; 1348 } 1349 1350 /* Disable HWPDN */ 1351 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1352 val8 &= ~(APS_FSMCO_HW_POWERDOWN >> 8); 1353 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1354 1355 /* Disable WL suspend */ 1356 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1357 val8 &= ~(APS_FSMCO_HW_SUSPEND >> 8); 1358 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1359 1360 /* set, then poll until 0 */ 1361 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1362 val8 |= APS_FSMCO_MAC_ENABLE >> 8; 1363 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1364 1365 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1366 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1367 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { 1368 ret = 0; 1369 break; 1370 } 1371 udelay(10); 1372 } 1373 1374 if (!count) { 1375 ret = -EBUSY; 1376 goto exit; 1377 } 1378 1379 /* 0x27<=35 to reduce RF noise */ 1380 val8 = rtl8xxxu_write8(priv, 0x27, 0x35); 1381 exit: 1382 return ret; 1383 } 1384 1385 static int rtl8188fu_active_to_emu(struct rtl8xxxu_priv *priv) 1386 { 1387 u8 val8; 1388 u32 val32; 1389 int count, ret = 0; 1390 1391 /* Turn off RF */ 1392 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); 1393 1394 /* 0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ 1395 val8 = rtl8xxxu_read8(priv, 0x4e); 1396 val8 &= ~BIT(7); 1397 rtl8xxxu_write8(priv, 0x4e, val8); 1398 1399 /* 0x27 <= 34, xtal_qsel = 0 to xtal bring up */ 1400 rtl8xxxu_write8(priv, 0x27, 0x34); 1401 1402 /* 0x04[9] = 1 turn off MAC by HW state machine */ 1403 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1404 val8 |= APS_FSMCO_MAC_OFF >> 8; 1405 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1406 1407 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1408 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1409 if ((val32 & APS_FSMCO_MAC_OFF) == 0) { 1410 ret = 0; 1411 break; 1412 } 1413 udelay(10); 1414 } 1415 1416 if (!count) { 1417 ret = -EBUSY; 1418 goto exit; 1419 } 1420 1421 exit: 1422 return ret; 1423 } 1424 1425 static int rtl8188fu_emu_to_disabled(struct rtl8xxxu_priv *priv) 1426 { 1427 u8 val8; 1428 1429 /* 0x04[12:11] = 2b'01 enable WL suspend */ 1430 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 1431 val8 &= ~((APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND) >> 8); 1432 val8 |= APS_FSMCO_HW_SUSPEND >> 8; 1433 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 1434 1435 /* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode */ 1436 val8 = rtl8xxxu_read8(priv, 0xc4); 1437 val8 |= BIT(4); 1438 rtl8xxxu_write8(priv, 0xc4, val8); 1439 1440 return 0; 1441 } 1442 1443 static int rtl8188fu_active_to_lps(struct rtl8xxxu_priv *priv) 1444 { 1445 struct device *dev = &priv->udev->dev; 1446 u8 val8; 1447 u16 val16; 1448 u32 val32; 1449 int retry, retval; 1450 1451 /* set RPWM IMR */ 1452 val8 = rtl8xxxu_read8(priv, REG_FTIMR + 1); 1453 val8 |= IMR0_CPWM >> 8; 1454 rtl8xxxu_write8(priv, REG_FTIMR + 1, val8); 1455 1456 /* Tx Pause */ 1457 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 1458 1459 retry = 100; 1460 retval = -EBUSY; 1461 1462 /* 1463 * Poll 32 bit wide REG_SCH_TX_CMD for 0x00000000 to ensure no TX is pending. 1464 */ 1465 do { 1466 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); 1467 if (!val32) { 1468 retval = 0; 1469 break; 1470 } 1471 } while (retry--); 1472 1473 if (!retry) { 1474 dev_warn(dev, "Failed to flush TX queue\n"); 1475 retval = -EBUSY; 1476 goto out; 1477 } 1478 1479 /* Disable CCK and OFDM, clock gated */ 1480 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 1481 val8 &= ~SYS_FUNC_BBRSTB; 1482 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 1483 1484 udelay(2); 1485 1486 /* Whole BB is reset */ 1487 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 1488 val8 &= ~SYS_FUNC_BB_GLB_RSTN; 1489 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 1490 1491 /* Reset MAC TRX */ 1492 val16 = rtl8xxxu_read16(priv, REG_CR); 1493 val16 |= 0x3f; 1494 val16 &= ~(CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | CR_SECURITY_ENABLE); 1495 rtl8xxxu_write16(priv, REG_CR, val16); 1496 1497 /* Respond TxOK to scheduler */ 1498 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); 1499 val8 |= DUAL_TSF_TX_OK; 1500 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); 1501 1502 out: 1503 return retval; 1504 } 1505 1506 static int rtl8188fu_power_on(struct rtl8xxxu_priv *priv) 1507 { 1508 u16 val16; 1509 int ret; 1510 1511 rtl8188f_disabled_to_emu(priv); 1512 1513 ret = rtl8188f_emu_to_active(priv); 1514 if (ret) 1515 goto exit; 1516 1517 rtl8xxxu_write8(priv, REG_CR, 0); 1518 1519 val16 = rtl8xxxu_read16(priv, REG_CR); 1520 1521 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | 1522 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | 1523 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | 1524 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); 1525 rtl8xxxu_write16(priv, REG_CR, val16); 1526 1527 exit: 1528 return ret; 1529 } 1530 1531 static void rtl8188fu_power_off(struct rtl8xxxu_priv *priv) 1532 { 1533 u8 val8; 1534 u16 val16; 1535 1536 rtl8xxxu_flush_fifo(priv); 1537 1538 val16 = rtl8xxxu_read16(priv, REG_GPIO_MUXCFG); 1539 val16 &= ~BIT(12); 1540 rtl8xxxu_write16(priv, REG_GPIO_MUXCFG, val16); 1541 1542 rtl8xxxu_write32(priv, REG_HISR0, 0xFFFFFFFF); 1543 rtl8xxxu_write32(priv, REG_HISR1, 0xFFFFFFFF); 1544 1545 /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */ 1546 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); 1547 val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; 1548 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); 1549 1550 /* Turn off RF */ 1551 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); 1552 1553 /* Reset Firmware if running in RAM */ 1554 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) 1555 rtl8xxxu_firmware_self_reset(priv); 1556 1557 rtl8188fu_active_to_lps(priv); 1558 1559 /* Reset MCU */ 1560 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1561 val16 &= ~SYS_FUNC_CPU_ENABLE; 1562 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1563 1564 /* Reset MCU ready status */ 1565 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 1566 1567 rtl8188fu_active_to_emu(priv); 1568 rtl8188fu_emu_to_disabled(priv); 1569 } 1570 1571 #define PPG_BB_GAIN_2G_TXA_OFFSET_8188F 0xee 1572 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0f 1573 1574 static void rtl8188f_enable_rf(struct rtl8xxxu_priv *priv) 1575 { 1576 u32 val32; 1577 u8 pg_pwrtrim = 0xff, val8; 1578 s8 bb_gain; 1579 1580 /* Somehow this is not found in the efuse we read earlier. */ 1581 rtl8xxxu_read_efuse8(priv, PPG_BB_GAIN_2G_TXA_OFFSET_8188F, &pg_pwrtrim); 1582 1583 if (pg_pwrtrim != 0xff) { 1584 bb_gain = pg_pwrtrim & PPG_BB_GAIN_2G_TX_OFFSET_MASK; 1585 1586 if (bb_gain == PPG_BB_GAIN_2G_TX_OFFSET_MASK) 1587 bb_gain = 0; 1588 else if (bb_gain & 1) 1589 bb_gain = bb_gain >> 1; 1590 else 1591 bb_gain = -(bb_gain >> 1); 1592 1593 val8 = abs(bb_gain); 1594 if (bb_gain > 0) 1595 val8 |= BIT(5); 1596 1597 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55); 1598 val32 &= ~0xfc000; 1599 val32 |= val8 << 14; 1600 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, val32); 1601 } 1602 1603 rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); 1604 1605 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1606 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); 1607 val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A; 1608 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1609 1610 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 1611 } 1612 1613 static void rtl8188f_disable_rf(struct rtl8xxxu_priv *priv) 1614 { 1615 u32 val32; 1616 1617 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1618 val32 &= ~OFDM_RF_PATH_TX_MASK; 1619 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1620 1621 /* Power down RF module */ 1622 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); 1623 } 1624 1625 static void rtl8188f_usb_quirks(struct rtl8xxxu_priv *priv) 1626 { 1627 u16 val16; 1628 u32 val32; 1629 1630 val16 = rtl8xxxu_read16(priv, REG_CR); 1631 val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE); 1632 rtl8xxxu_write16(priv, REG_CR, val16); 1633 1634 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); 1635 val32 |= TXDMA_OFFSET_DROP_DATA_EN; 1636 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); 1637 } 1638 1639 struct rtl8xxxu_fileops rtl8188fu_fops = { 1640 .parse_efuse = rtl8188fu_parse_efuse, 1641 .load_firmware = rtl8188fu_load_firmware, 1642 .power_on = rtl8188fu_power_on, 1643 .power_off = rtl8188fu_power_off, 1644 .reset_8051 = rtl8xxxu_reset_8051, 1645 .llt_init = rtl8xxxu_auto_llt_table, 1646 .init_phy_bb = rtl8188fu_init_phy_bb, 1647 .init_phy_rf = rtl8188fu_init_phy_rf, 1648 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection, 1649 .phy_lc_calibrate = rtl8188f_phy_lc_calibrate, 1650 .phy_iq_calibrate = rtl8188fu_phy_iq_calibrate, 1651 .config_channel = rtl8188fu_config_channel, 1652 .parse_rx_desc = rtl8xxxu_parse_rxdesc24, 1653 .init_aggregation = rtl8188fu_init_aggregation, 1654 .init_statistics = rtl8188fu_init_statistics, 1655 .enable_rf = rtl8188f_enable_rf, 1656 .disable_rf = rtl8188f_disable_rf, 1657 .usb_quirks = rtl8188f_usb_quirks, 1658 .set_tx_power = rtl8188f_set_tx_power, 1659 .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, 1660 .report_connect = rtl8xxxu_gen2_report_connect, 1661 .fill_txdesc = rtl8xxxu_fill_txdesc_v2, 1662 .writeN_block_size = 128, 1663 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), 1664 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), 1665 .has_s0s1 = 1, 1666 .has_tx_report = 1, 1667 .gen2_thermal_meter = 1, 1668 .needs_full_init = 1, 1669 .adda_1t_init = 0x03c00014, 1670 .adda_1t_path_on = 0x03c00014, 1671 .trxff_boundary = 0x3f7f, 1672 .pbp_rx = PBP_PAGE_SIZE_256, 1673 .pbp_tx = PBP_PAGE_SIZE_256, 1674 .mactable = rtl8188f_mac_init_table, 1675 .total_page_num = TX_TOTAL_PAGE_NUM_8188F, 1676 .page_num_hi = TX_PAGE_NUM_HI_PQ_8188F, 1677 .page_num_lo = TX_PAGE_NUM_LO_PQ_8188F, 1678 .page_num_norm = TX_PAGE_NUM_NORM_PQ_8188F, 1679 }; 1680