1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * RTL8XXXU mac80211 USB driver - 8188e specific subdriver 4 * 5 * Copyright (c) 2014 - 2016 Jes Sorensen <Jes.Sorensen@gmail.com> 6 * 7 * Portions, notably calibration code: 8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 9 * 10 * This driver was written as a replacement for the vendor provided 11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in 12 * their programming interface, I have started adding support for 13 * additional 8xxx chips like the 8192cu, 8188cus, etc. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/kernel.h> 18 #include <linux/sched.h> 19 #include <linux/errno.h> 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/spinlock.h> 23 #include <linux/list.h> 24 #include <linux/usb.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/ethtool.h> 28 #include <linux/wireless.h> 29 #include <linux/firmware.h> 30 #include <linux/moduleparam.h> 31 #include <net/mac80211.h> 32 #include "rtl8xxxu.h" 33 #include "rtl8xxxu_regs.h" 34 35 static const struct rtl8xxxu_reg8val rtl8188e_mac_init_table[] = { 36 {0x026, 0x41}, {0x027, 0x35}, {0x040, 0x00}, {0x421, 0x0f}, 37 {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x01}, 38 {0x432, 0x02}, {0x433, 0x04}, {0x434, 0x05}, {0x435, 0x06}, 39 {0x436, 0x07}, {0x437, 0x08}, {0x438, 0x00}, {0x439, 0x00}, 40 {0x43a, 0x01}, {0x43b, 0x02}, {0x43c, 0x04}, {0x43d, 0x05}, 41 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, 42 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, 43 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, 44 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x480, 0x08}, 45 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff}, 46 {0x4ce, 0x01}, {0x4d3, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, 47 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, 48 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, 49 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, 50 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, 51 {0x516, 0x0a}, {0x525, 0x4f}, {0x550, 0x10}, {0x551, 0x10}, 52 {0x559, 0x02}, {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, 53 {0x609, 0x2a}, {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, 54 {0x623, 0xff}, {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, 55 {0x627, 0xff}, {0x63c, 0x08}, {0x63d, 0x08}, {0x63e, 0x0c}, 56 {0x63f, 0x0c}, {0x640, 0x40}, {0x652, 0x20}, {0x66e, 0x05}, 57 {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, {0x703, 0x87}, 58 {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65}, {0x70b, 0x87}, 59 {0xffff, 0xff}, 60 }; 61 62 static const struct rtl8xxxu_reg32val rtl8188eu_phy_init_table[] = { 63 {0x800, 0x80040000}, {0x804, 0x00000003}, 64 {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, 65 {0x810, 0x10001331}, {0x814, 0x020c3d10}, 66 {0x818, 0x02200385}, {0x81c, 0x00000000}, 67 {0x820, 0x01000100}, {0x824, 0x00390204}, 68 {0x828, 0x00000000}, {0x82c, 0x00000000}, 69 {0x830, 0x00000000}, {0x834, 0x00000000}, 70 {0x838, 0x00000000}, {0x83c, 0x00000000}, 71 {0x840, 0x00010000}, {0x844, 0x00000000}, 72 {0x848, 0x00000000}, {0x84c, 0x00000000}, 73 {0x850, 0x00000000}, {0x854, 0x00000000}, 74 {0x858, 0x569a11a9}, {0x85c, 0x01000014}, 75 {0x860, 0x66f60110}, {0x864, 0x061f0649}, 76 {0x868, 0x00000000}, {0x86c, 0x27272700}, 77 {0x870, 0x07000760}, {0x874, 0x25004000}, 78 {0x878, 0x00000808}, {0x87c, 0x00000000}, 79 {0x880, 0xb0000c1c}, {0x884, 0x00000001}, 80 {0x888, 0x00000000}, {0x88c, 0xccc000c0}, 81 {0x890, 0x00000800}, {0x894, 0xfffffffe}, 82 {0x898, 0x40302010}, {0x89c, 0x00706050}, 83 {0x900, 0x00000000}, {0x904, 0x00000023}, 84 {0x908, 0x00000000}, {0x90c, 0x81121111}, 85 {0x910, 0x00000002}, {0x914, 0x00000201}, 86 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c}, 87 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f}, 88 {0xa10, 0x9500bb7e}, {0xa14, 0x1114d028}, 89 {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, 90 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, 91 {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, 92 {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, 93 {0xa78, 0x00000900}, {0xa7c, 0x225b0606}, 94 {0xa80, 0x218075b1}, {0xb2c, 0x80000000}, 95 {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, 96 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, 97 {0xc10, 0x08800000}, {0xc14, 0x40000100}, 98 {0xc18, 0x08800000}, {0xc1c, 0x40000100}, 99 {0xc20, 0x00000000}, {0xc24, 0x00000000}, 100 {0xc28, 0x00000000}, {0xc2c, 0x00000000}, 101 {0xc30, 0x69e9ac47}, {0xc34, 0x469652af}, 102 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, 103 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, 104 {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, 105 {0xc50, 0x69553420}, {0xc54, 0x43bc0094}, 106 {0xc58, 0x00013169}, {0xc5c, 0x00250492}, 107 {0xc60, 0x00000000}, {0xc64, 0x7112848b}, 108 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, 109 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db}, 110 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, 111 {0xc80, 0x390000e4}, {0xc84, 0x21f60000}, 112 {0xc88, 0x40000100}, {0xc8c, 0x20200000}, 113 {0xc90, 0x00091521}, {0xc94, 0x00000000}, 114 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, 115 {0xca0, 0x00000000}, {0xca4, 0x000300a0}, 116 {0xca8, 0x00000000}, {0xcac, 0x00000000}, 117 {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, 118 {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, 119 {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, 120 {0xcc8, 0x00000000}, {0xccc, 0x00000000}, 121 {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, 122 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, 123 {0xce0, 0x00222222}, {0xce4, 0x00000000}, 124 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, 125 {0xd00, 0x00000740}, {0xd04, 0x00020401}, 126 {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, 127 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, 128 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975}, 129 {0xd30, 0x00000000}, {0xd34, 0x80608000}, 130 {0xd38, 0x00000000}, {0xd3c, 0x00127353}, 131 {0xd40, 0x00000000}, {0xd44, 0x00000000}, 132 {0xd48, 0x00000000}, {0xd4c, 0x00000000}, 133 {0xd50, 0x6437140a}, {0xd54, 0x00000000}, 134 {0xd58, 0x00000282}, {0xd5c, 0x30032064}, 135 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, 136 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, 137 {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, 138 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d}, 139 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d}, 140 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d}, 141 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d}, 142 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, 143 {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, 144 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, 145 {0xe44, 0x01004800}, {0xe48, 0xfb000000}, 146 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, 147 {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, 148 {0xe5c, 0x28160d05}, {0xe60, 0x00000048}, 149 {0xe68, 0x001b25a4}, {0xe6c, 0x00c00014}, 150 {0xe70, 0x00c00014}, {0xe74, 0x01000014}, 151 {0xe78, 0x01000014}, {0xe7c, 0x01000014}, 152 {0xe80, 0x01000014}, {0xe84, 0x00c00014}, 153 {0xe88, 0x01000014}, {0xe8c, 0x00c00014}, 154 {0xed0, 0x00c00014}, {0xed4, 0x00c00014}, 155 {0xed8, 0x00c00014}, {0xedc, 0x00000014}, 156 {0xee0, 0x00000014}, {0xee8, 0x21555448}, 157 {0xeec, 0x01c00014}, {0xf14, 0x00000003}, 158 {0xf4c, 0x00000000}, {0xf00, 0x00000300}, 159 {0xffff, 0xffffffff}, 160 }; 161 162 static const struct rtl8xxxu_reg32val rtl8188e_agc_table[] = { 163 {0xc78, 0xfb000001}, {0xc78, 0xfb010001}, 164 {0xc78, 0xfb020001}, {0xc78, 0xfb030001}, 165 {0xc78, 0xfb040001}, {0xc78, 0xfb050001}, 166 {0xc78, 0xfa060001}, {0xc78, 0xf9070001}, 167 {0xc78, 0xf8080001}, {0xc78, 0xf7090001}, 168 {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001}, 169 {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001}, 170 {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001}, 171 {0xc78, 0xf0100001}, {0xc78, 0xef110001}, 172 {0xc78, 0xee120001}, {0xc78, 0xed130001}, 173 {0xc78, 0xec140001}, {0xc78, 0xeb150001}, 174 {0xc78, 0xea160001}, {0xc78, 0xe9170001}, 175 {0xc78, 0xe8180001}, {0xc78, 0xe7190001}, 176 {0xc78, 0xe61a0001}, {0xc78, 0xe51b0001}, 177 {0xc78, 0xe41c0001}, {0xc78, 0xe31d0001}, 178 {0xc78, 0xe21e0001}, {0xc78, 0xe11f0001}, 179 {0xc78, 0x8a200001}, {0xc78, 0x89210001}, 180 {0xc78, 0x88220001}, {0xc78, 0x87230001}, 181 {0xc78, 0x86240001}, {0xc78, 0x85250001}, 182 {0xc78, 0x84260001}, {0xc78, 0x83270001}, 183 {0xc78, 0x82280001}, {0xc78, 0x6b290001}, 184 {0xc78, 0x6a2a0001}, {0xc78, 0x692b0001}, 185 {0xc78, 0x682c0001}, {0xc78, 0x672d0001}, 186 {0xc78, 0x662e0001}, {0xc78, 0x652f0001}, 187 {0xc78, 0x64300001}, {0xc78, 0x63310001}, 188 {0xc78, 0x62320001}, {0xc78, 0x61330001}, 189 {0xc78, 0x46340001}, {0xc78, 0x45350001}, 190 {0xc78, 0x44360001}, {0xc78, 0x43370001}, 191 {0xc78, 0x42380001}, {0xc78, 0x41390001}, 192 {0xc78, 0x403a0001}, {0xc78, 0x403b0001}, 193 {0xc78, 0x403c0001}, {0xc78, 0x403d0001}, 194 {0xc78, 0x403e0001}, {0xc78, 0x403f0001}, 195 {0xc78, 0xfb400001}, {0xc78, 0xfb410001}, 196 {0xc78, 0xfb420001}, {0xc78, 0xfb430001}, 197 {0xc78, 0xfb440001}, {0xc78, 0xfb450001}, 198 {0xc78, 0xfb460001}, {0xc78, 0xfb470001}, 199 {0xc78, 0xfb480001}, {0xc78, 0xfa490001}, 200 {0xc78, 0xf94a0001}, {0xc78, 0xf84b0001}, 201 {0xc78, 0xf74c0001}, {0xc78, 0xf64d0001}, 202 {0xc78, 0xf54e0001}, {0xc78, 0xf44f0001}, 203 {0xc78, 0xf3500001}, {0xc78, 0xf2510001}, 204 {0xc78, 0xf1520001}, {0xc78, 0xf0530001}, 205 {0xc78, 0xef540001}, {0xc78, 0xee550001}, 206 {0xc78, 0xed560001}, {0xc78, 0xec570001}, 207 {0xc78, 0xeb580001}, {0xc78, 0xea590001}, 208 {0xc78, 0xe95a0001}, {0xc78, 0xe85b0001}, 209 {0xc78, 0xe75c0001}, {0xc78, 0xe65d0001}, 210 {0xc78, 0xe55e0001}, {0xc78, 0xe45f0001}, 211 {0xc78, 0xe3600001}, {0xc78, 0xe2610001}, 212 {0xc78, 0xc3620001}, {0xc78, 0xc2630001}, 213 {0xc78, 0xc1640001}, {0xc78, 0x8b650001}, 214 {0xc78, 0x8a660001}, {0xc78, 0x89670001}, 215 {0xc78, 0x88680001}, {0xc78, 0x87690001}, 216 {0xc78, 0x866a0001}, {0xc78, 0x856b0001}, 217 {0xc78, 0x846c0001}, {0xc78, 0x676d0001}, 218 {0xc78, 0x666e0001}, {0xc78, 0x656f0001}, 219 {0xc78, 0x64700001}, {0xc78, 0x63710001}, 220 {0xc78, 0x62720001}, {0xc78, 0x61730001}, 221 {0xc78, 0x60740001}, {0xc78, 0x46750001}, 222 {0xc78, 0x45760001}, {0xc78, 0x44770001}, 223 {0xc78, 0x43780001}, {0xc78, 0x42790001}, 224 {0xc78, 0x417a0001}, {0xc78, 0x407b0001}, 225 {0xc78, 0x407c0001}, {0xc78, 0x407d0001}, 226 {0xc78, 0x407e0001}, {0xc78, 0x407f0001}, 227 {0xc50, 0x69553422}, {0xc50, 0x69553420}, 228 {0xffff, 0xffffffff} 229 }; 230 231 static const struct rtl8xxxu_rfregval rtl8188eu_radioa_init_table[] = { 232 {0x00, 0x00030000}, {0x08, 0x00084000}, 233 {0x18, 0x00000407}, {0x19, 0x00000012}, 234 {0x1e, 0x00080009}, {0x1f, 0x00000880}, 235 {0x2f, 0x0001a060}, {0x3f, 0x00000000}, 236 {0x42, 0x000060c0}, {0x57, 0x000d0000}, 237 {0x58, 0x000be180}, {0x67, 0x00001552}, 238 {0x83, 0x00000000}, {0xb0, 0x000ff8fc}, 239 {0xb1, 0x00054400}, {0xb2, 0x000ccc19}, 240 {0xb4, 0x00043003}, {0xb6, 0x0004953e}, 241 {0xb7, 0x0001c718}, {0xb8, 0x000060ff}, 242 {0xb9, 0x00080001}, {0xba, 0x00040000}, 243 {0xbb, 0x00000400}, {0xbf, 0x000c0000}, 244 {0xc2, 0x00002400}, {0xc3, 0x00000009}, 245 {0xc4, 0x00040c91}, {0xc5, 0x00099999}, 246 {0xc6, 0x000000a3}, {0xc7, 0x00088820}, 247 {0xc8, 0x00076c06}, {0xc9, 0x00000000}, 248 {0xca, 0x00080000}, {0xdf, 0x00000180}, 249 {0xef, 0x000001a0}, {0x51, 0x0006b27d}, 250 {0x52, 0x0007e49d}, /* Set to 0x0007e4dd for SDIO */ 251 {0x53, 0x00000073}, {0x56, 0x00051ff3}, 252 {0x35, 0x00000086}, {0x35, 0x00000186}, 253 {0x35, 0x00000286}, {0x36, 0x00001c25}, 254 {0x36, 0x00009c25}, {0x36, 0x00011c25}, 255 {0x36, 0x00019c25}, {0xb6, 0x00048538}, 256 {0x18, 0x00000c07}, {0x5a, 0x0004bd00}, 257 {0x19, 0x000739d0}, {0x34, 0x0000adf3}, 258 {0x34, 0x00009df0}, {0x34, 0x00008ded}, 259 {0x34, 0x00007dea}, {0x34, 0x00006de7}, 260 {0x34, 0x000054ee}, {0x34, 0x000044eb}, 261 {0x34, 0x000034e8}, {0x34, 0x0000246b}, 262 {0x34, 0x00001468}, {0x34, 0x0000006d}, 263 {0x00, 0x00030159}, {0x84, 0x00068200}, 264 {0x86, 0x000000ce}, {0x87, 0x00048a00}, 265 {0x8e, 0x00065540}, {0x8f, 0x00088000}, 266 {0xef, 0x000020a0}, {0x3b, 0x000f02b0}, 267 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0}, 268 {0x3b, 0x000cf060}, {0x3b, 0x000b0090}, 269 {0x3b, 0x000a0080}, {0x3b, 0x00090080}, 270 {0x3b, 0x0008f780}, {0x3b, 0x000722b0}, 271 {0x3b, 0x0006f7b0}, {0x3b, 0x00054fb0}, 272 {0x3b, 0x0004f060}, {0x3b, 0x00030090}, 273 {0x3b, 0x00020080}, {0x3b, 0x00010080}, 274 {0x3b, 0x0000f780}, {0xef, 0x000000a0}, 275 {0x00, 0x00010159}, {0x18, 0x0000f407}, 276 {0xFE, 0x00000000}, {0xFE, 0x00000000}, 277 {0x1F, 0x00080003}, {0xFE, 0x00000000}, 278 {0xFE, 0x00000000}, {0x1E, 0x00000001}, 279 {0x1F, 0x00080000}, {0x00, 0x00033e60}, 280 {0xff, 0xffffffff} 281 }; 282 283 #define PERENTRY 23 284 #define RETRYSIZE 5 285 #define RATESIZE 28 286 #define TX_RPT2_ITEM_SIZE 8 287 288 static const u8 retry_penalty[PERENTRY][RETRYSIZE + 1] = { 289 {5, 4, 3, 2, 0, 3}, /* 92 , idx=0 */ 290 {6, 5, 4, 3, 0, 4}, /* 86 , idx=1 */ 291 {6, 5, 4, 2, 0, 4}, /* 81 , idx=2 */ 292 {8, 7, 6, 4, 0, 6}, /* 75 , idx=3 */ 293 {10, 9, 8, 6, 0, 8}, /* 71 , idx=4 */ 294 {10, 9, 8, 4, 0, 8}, /* 66 , idx=5 */ 295 {10, 9, 8, 2, 0, 8}, /* 62 , idx=6 */ 296 {10, 9, 8, 0, 0, 8}, /* 59 , idx=7 */ 297 {18, 17, 16, 8, 0, 16}, /* 53 , idx=8 */ 298 {26, 25, 24, 16, 0, 24}, /* 50 , idx=9 */ 299 {34, 33, 32, 24, 0, 32}, /* 47 , idx=0x0a */ 300 {34, 31, 28, 20, 0, 32}, /* 43 , idx=0x0b */ 301 {34, 31, 27, 18, 0, 32}, /* 40 , idx=0x0c */ 302 {34, 31, 26, 16, 0, 32}, /* 37 , idx=0x0d */ 303 {34, 30, 22, 16, 0, 32}, /* 32 , idx=0x0e */ 304 {34, 30, 24, 16, 0, 32}, /* 26 , idx=0x0f */ 305 {49, 46, 40, 16, 0, 48}, /* 20 , idx=0x10 */ 306 {49, 45, 32, 0, 0, 48}, /* 17 , idx=0x11 */ 307 {49, 45, 22, 18, 0, 48}, /* 15 , idx=0x12 */ 308 {49, 40, 24, 16, 0, 48}, /* 12 , idx=0x13 */ 309 {49, 32, 18, 12, 0, 48}, /* 9 , idx=0x14 */ 310 {49, 22, 18, 14, 0, 48}, /* 6 , idx=0x15 */ 311 {49, 16, 16, 0, 0, 48} /* 3, idx=0x16 */ 312 }; 313 314 static const u8 pt_penalty[RETRYSIZE + 1] = {34, 31, 30, 24, 0, 32}; 315 316 static const u8 retry_penalty_idx_normal[2][RATESIZE] = { 317 { /* RSSI>TH */ 318 4, 4, 4, 5, 319 4, 4, 5, 7, 7, 7, 8, 0x0a, 320 4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d, 321 5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f 322 }, 323 { /* RSSI<TH */ 324 0x0a, 0x0a, 0x0b, 0x0c, 325 0x0a, 0x0a, 0x0b, 0x0c, 0x0d, 0x10, 0x13, 0x13, 326 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x11, 0x13, 0x13, 327 9, 9, 9, 9, 0x0c, 0x0e, 0x11, 0x13 328 } 329 }; 330 331 static const u8 retry_penalty_idx_cut_i[2][RATESIZE] = { 332 { /* RSSI>TH */ 333 4, 4, 4, 5, 334 4, 4, 5, 7, 7, 7, 8, 0x0a, 335 4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d, 336 5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f 337 }, 338 { /* RSSI<TH */ 339 0x0a, 0x0a, 0x0b, 0x0c, 340 0x0a, 0x0a, 0x0b, 0x0c, 0x0d, 0x10, 0x13, 0x13, 341 0x06, 0x07, 0x08, 0x0d, 0x0e, 0x11, 0x11, 0x11, 342 9, 9, 9, 9, 0x0c, 0x0e, 0x11, 0x13 343 } 344 }; 345 346 static const u8 retry_penalty_up_idx_normal[RATESIZE] = { 347 0x0c, 0x0d, 0x0d, 0x0f, 348 0x0d, 0x0e, 0x0f, 0x0f, 0x10, 0x12, 0x13, 0x14, 349 0x0f, 0x10, 0x10, 0x12, 0x12, 0x13, 0x14, 0x15, 350 0x11, 0x11, 0x12, 0x13, 0x13, 0x13, 0x14, 0x15 351 }; 352 353 static const u8 retry_penalty_up_idx_cut_i[RATESIZE] = { 354 0x0c, 0x0d, 0x0d, 0x0f, 355 0x0d, 0x0e, 0x0f, 0x0f, 0x10, 0x12, 0x13, 0x14, 356 0x0b, 0x0b, 0x11, 0x11, 0x12, 0x12, 0x12, 0x12, 357 0x11, 0x11, 0x12, 0x13, 0x13, 0x13, 0x14, 0x15 358 }; 359 360 static const u8 rssi_threshold[RATESIZE] = { 361 0, 0, 0, 0, 362 0, 0, 0, 0, 0, 0x24, 0x26, 0x2a, 363 0x18, 0x1a, 0x1d, 0x1f, 0x21, 0x27, 0x29, 0x2a, 364 0, 0, 0, 0x1f, 0x23, 0x28, 0x2a, 0x2c 365 }; 366 367 static const u16 n_threshold_high[RATESIZE] = { 368 4, 4, 8, 16, 369 24, 36, 48, 72, 96, 144, 192, 216, 370 60, 80, 100, 160, 240, 400, 600, 800, 371 300, 320, 480, 720, 1000, 1200, 1600, 2000 372 }; 373 374 static const u16 n_threshold_low[RATESIZE] = { 375 2, 2, 4, 8, 376 12, 18, 24, 36, 48, 72, 96, 108, 377 30, 40, 50, 80, 120, 200, 300, 400, 378 150, 160, 240, 360, 500, 600, 800, 1000 379 }; 380 381 static const u8 dropping_necessary[RATESIZE] = { 382 1, 1, 1, 1, 383 1, 2, 3, 4, 5, 6, 7, 8, 384 1, 2, 3, 4, 5, 6, 7, 8, 385 5, 6, 7, 8, 9, 10, 11, 12 386 }; 387 388 static const u8 pending_for_rate_up_fail[5] = {2, 10, 24, 40, 60}; 389 390 static const u16 dynamic_tx_rpt_timing[6] = { 391 0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12, 0x927c /* 200ms-1200ms */ 392 }; 393 394 enum rtl8188e_tx_rpt_timing { 395 DEFAULT_TIMING = 0, 396 INCREASE_TIMING, 397 DECREASE_TIMING 398 }; 399 400 static int rtl8188eu_identify_chip(struct rtl8xxxu_priv *priv) 401 { 402 struct device *dev = &priv->udev->dev; 403 u32 sys_cfg, vendor; 404 int ret = 0; 405 406 strscpy(priv->chip_name, "8188EU", sizeof(priv->chip_name)); 407 priv->rtl_chip = RTL8188E; 408 priv->rf_paths = 1; 409 priv->rx_paths = 1; 410 priv->tx_paths = 1; 411 priv->has_wifi = 1; 412 413 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); 414 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); 415 if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { 416 dev_info(dev, "Unsupported test chip\n"); 417 return -EOPNOTSUPP; 418 } 419 420 /* 421 * TODO: At a glance, I cut requires a different firmware, 422 * different initialisation tables, and no software rate 423 * control. The vendor driver is not configured to handle 424 * I cut chips by default. Are there any in the wild? 425 */ 426 if (priv->chip_cut == 8) { 427 dev_info(dev, "RTL8188EU cut I is not supported. Please complain about it at linux-wireless@vger.kernel.org.\n"); 428 return -EOPNOTSUPP; 429 } 430 431 vendor = sys_cfg & SYS_CFG_VENDOR_ID; 432 rtl8xxxu_identify_vendor_1bit(priv, vendor); 433 434 ret = rtl8xxxu_config_endpoints_no_sie(priv); 435 436 return ret; 437 } 438 439 static void rtl8188eu_config_channel(struct ieee80211_hw *hw) 440 { 441 struct rtl8xxxu_priv *priv = hw->priv; 442 u32 val32, rsr; 443 u8 opmode; 444 int sec_ch_above, channel; 445 int i; 446 447 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE); 448 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); 449 channel = hw->conf.chandef.chan->hw_value; 450 451 switch (hw->conf.chandef.width) { 452 case NL80211_CHAN_WIDTH_20_NOHT: 453 case NL80211_CHAN_WIDTH_20: 454 opmode |= BW_OPMODE_20MHZ; 455 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 456 457 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 458 val32 &= ~FPGA_RF_MODE; 459 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 460 461 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 462 val32 &= ~FPGA_RF_MODE; 463 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 464 break; 465 case NL80211_CHAN_WIDTH_40: 466 if (hw->conf.chandef.center_freq1 > 467 hw->conf.chandef.chan->center_freq) { 468 sec_ch_above = 1; 469 channel += 2; 470 } else { 471 sec_ch_above = 0; 472 channel -= 2; 473 } 474 475 opmode &= ~BW_OPMODE_20MHZ; 476 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); 477 rsr &= ~RSR_RSC_BANDWIDTH_40M; 478 if (sec_ch_above) 479 rsr |= RSR_RSC_LOWER_SUB_CHANNEL; 480 else 481 rsr |= RSR_RSC_UPPER_SUB_CHANNEL; 482 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); 483 484 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); 485 val32 |= FPGA_RF_MODE; 486 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); 487 488 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); 489 val32 |= FPGA_RF_MODE; 490 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); 491 492 /* 493 * Set Control channel to upper or lower. These settings 494 * are required only for 40MHz 495 */ 496 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); 497 val32 &= ~CCK0_SIDEBAND; 498 if (!sec_ch_above) 499 val32 |= CCK0_SIDEBAND; 500 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); 501 502 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); 503 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ 504 if (sec_ch_above) 505 val32 |= OFDM_LSTF_PRIME_CH_LOW; 506 else 507 val32 |= OFDM_LSTF_PRIME_CH_HIGH; 508 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); 509 510 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); 511 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); 512 if (sec_ch_above) 513 val32 |= FPGA0_PS_UPPER_CHANNEL; 514 else 515 val32 |= FPGA0_PS_LOWER_CHANNEL; 516 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); 517 break; 518 519 default: 520 break; 521 } 522 523 for (i = RF_A; i < priv->rf_paths; i++) { 524 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 525 u32p_replace_bits(&val32, channel, MODE_AG_CHANNEL_MASK); 526 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 527 } 528 529 for (i = RF_A; i < priv->rf_paths; i++) { 530 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); 531 val32 &= ~MODE_AG_BW_MASK; 532 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) 533 val32 |= MODE_AG_BW_40MHZ_8723B; 534 else 535 val32 |= MODE_AG_BW_20MHZ_8723B; 536 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); 537 } 538 } 539 540 static void rtl8188eu_init_aggregation(struct rtl8xxxu_priv *priv) 541 { 542 u8 agg_ctrl, usb_spec; 543 544 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); 545 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE; 546 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec); 547 548 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); 549 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; 550 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 551 } 552 553 static int rtl8188eu_parse_efuse(struct rtl8xxxu_priv *priv) 554 { 555 struct rtl8188eu_efuse *efuse = &priv->efuse_wifi.efuse8188eu; 556 557 if (efuse->rtl_id != cpu_to_le16(0x8129)) 558 return -EINVAL; 559 560 ether_addr_copy(priv->mac_addr, efuse->mac_addr); 561 562 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, 563 sizeof(efuse->tx_power_index_A.cck_base)); 564 565 memcpy(priv->ht40_1s_tx_power_index_A, 566 efuse->tx_power_index_A.ht40_base, 567 sizeof(efuse->tx_power_index_A.ht40_base)); 568 569 priv->default_crystal_cap = efuse->xtal_k & 0x3f; 570 571 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name); 572 dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name); 573 dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial); 574 575 return 0; 576 } 577 578 static void rtl8188eu_reset_8051(struct rtl8xxxu_priv *priv) 579 { 580 u16 sys_func; 581 582 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); 583 sys_func &= ~SYS_FUNC_CPU_ENABLE; 584 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 585 586 sys_func |= SYS_FUNC_CPU_ENABLE; 587 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); 588 } 589 590 static int rtl8188eu_load_firmware(struct rtl8xxxu_priv *priv) 591 { 592 const char *fw_name; 593 int ret; 594 595 fw_name = "rtlwifi/rtl8188eufw.bin"; 596 597 ret = rtl8xxxu_load_firmware(priv, fw_name); 598 599 return ret; 600 } 601 602 static void rtl8188eu_init_phy_bb(struct rtl8xxxu_priv *priv) 603 { 604 u8 val8; 605 u16 val16; 606 607 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 608 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; 609 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 610 611 /* 612 * Per vendor driver, run power sequence before init of RF 613 */ 614 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; 615 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 616 617 val8 = SYS_FUNC_USBA | SYS_FUNC_USBD | 618 SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB; 619 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 620 621 rtl8xxxu_init_phy_regs(priv, rtl8188eu_phy_init_table); 622 rtl8xxxu_init_phy_regs(priv, rtl8188e_agc_table); 623 } 624 625 static int rtl8188eu_init_phy_rf(struct rtl8xxxu_priv *priv) 626 { 627 return rtl8xxxu_init_phy_rf(priv, rtl8188eu_radioa_init_table, RF_A); 628 } 629 630 static int rtl8188eu_iqk_path_a(struct rtl8xxxu_priv *priv) 631 { 632 u32 reg_eac, reg_e94, reg_e9c; 633 int result = 0; 634 635 /* Path A IQK setting */ 636 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c); 637 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c); 638 639 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8214032a); 640 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); 641 642 /* LO calibration setting */ 643 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); 644 645 /* One shot, path A LOK & IQK */ 646 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 647 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 648 649 mdelay(10); 650 651 /* Check failed */ 652 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 653 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 654 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 655 656 if (!(reg_eac & BIT(28)) && 657 ((reg_e94 & 0x03ff0000) != 0x01420000) && 658 ((reg_e9c & 0x03ff0000) != 0x00420000)) 659 result |= 0x01; 660 661 return result; 662 } 663 664 static int rtl8188eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) 665 { 666 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; 667 int result = 0; 668 669 /* Leave IQK mode */ 670 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 671 u32p_replace_bits(&val32, 0, 0xffffff00); 672 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 673 674 /* Enable path A PA in TX IQK mode */ 675 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); 676 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 677 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); 678 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf117b); 679 680 /* Enter IQK mode */ 681 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 682 u32p_replace_bits(&val32, 0x808000, 0xffffff00); 683 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 684 685 /* TX IQK setting */ 686 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 687 rtl8xxxu_write32(priv, REG_RX_IQK, 0x81004800); 688 689 /* path-A IQK setting */ 690 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c); 691 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c); 692 693 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160804); 694 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); 695 696 /* LO calibration setting */ 697 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); 698 699 /* One shot, path A LOK & IQK */ 700 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 701 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 702 703 mdelay(10); 704 705 /* Check failed */ 706 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 707 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 708 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 709 710 if (!(reg_eac & BIT(28)) && 711 ((reg_e94 & 0x03ff0000) != 0x01420000) && 712 ((reg_e9c & 0x03ff0000) != 0x00420000)) 713 result |= 0x01; 714 else 715 goto out; 716 717 val32 = 0x80007c00 | 718 (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff); 719 rtl8xxxu_write32(priv, REG_TX_IQK, val32); 720 721 /* Modify RX IQK mode table */ 722 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 723 u32p_replace_bits(&val32, 0, 0xffffff00); 724 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 725 726 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); 727 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); 728 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); 729 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ffa); 730 731 /* Enter IQK mode */ 732 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 733 u32p_replace_bits(&val32, 0x808000, 0xffffff00); 734 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 735 736 /* IQK setting */ 737 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 738 739 /* Path A IQK setting */ 740 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x30008c1c); 741 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1c); 742 743 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c05); 744 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c05); 745 746 /* LO calibration setting */ 747 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); 748 749 /* One shot, path A LOK & IQK */ 750 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); 751 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); 752 753 mdelay(10); 754 755 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 756 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 757 758 if (!(reg_eac & BIT(27)) && 759 ((reg_ea4 & 0x03ff0000) != 0x01320000) && 760 ((reg_eac & 0x03ff0000) != 0x00360000)) 761 result |= 0x02; 762 else 763 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", 764 __func__); 765 766 out: 767 return result; 768 } 769 770 static void rtl8188eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, 771 int result[][8], int t) 772 { 773 struct device *dev = &priv->udev->dev; 774 u32 i, val32; 775 int path_a_ok; 776 int retry = 2; 777 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { 778 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, 779 REG_RX_WAIT_CCA, REG_TX_CCK_RFON, 780 REG_TX_CCK_BBON, REG_TX_OFDM_RFON, 781 REG_TX_OFDM_BBON, REG_TX_TO_RX, 782 REG_TX_TO_TX, REG_RX_CCK, 783 REG_RX_OFDM, REG_RX_WAIT_RIFS, 784 REG_RX_TO_RX, REG_STANDBY, 785 REG_SLEEP, REG_PMPD_ANAEN 786 }; 787 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { 788 REG_TXPAUSE, REG_BEACON_CTRL, 789 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG 790 }; 791 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { 792 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, 793 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, 794 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, 795 REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING 796 }; 797 798 /* 799 * Note: IQ calibration must be performed after loading 800 * PHY_REG.txt , and radio_a, radio_b.txt 801 */ 802 803 if (t == 0) { 804 /* Save ADDA parameters, turn Path A ADDA on */ 805 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, 806 RTL8XXXU_ADDA_REGS); 807 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 808 rtl8xxxu_save_regs(priv, iqk_bb_regs, 809 priv->bb_backup, RTL8XXXU_BB_REGS); 810 } 811 812 rtl8xxxu_path_adda_on(priv, adda_regs, true); 813 814 if (t == 0) { 815 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); 816 priv->pi_enabled = u32_get_bits(val32, FPGA0_HSSI_PARM1_PI); 817 } 818 819 if (!priv->pi_enabled) { 820 /* Switch BB to PI mode to do IQ Calibration. */ 821 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); 822 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); 823 } 824 825 /* MAC settings */ 826 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); 827 828 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); 829 u32p_replace_bits(&val32, 0xf, 0x0f000000); 830 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); 831 832 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); 833 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); 834 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); 835 836 if (!priv->no_pape) { 837 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); 838 val32 |= (FPGA0_RF_PAPE | 839 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); 840 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); 841 } 842 843 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); 844 val32 &= ~BIT(10); 845 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); 846 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); 847 val32 &= ~BIT(10); 848 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); 849 850 /* Page B init */ 851 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000); 852 853 /* IQ calibration setting */ 854 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 855 u32p_replace_bits(&val32, 0x808000, 0xffffff00); 856 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 857 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 858 rtl8xxxu_write32(priv, REG_RX_IQK, 0x81004800); 859 860 for (i = 0; i < retry; i++) { 861 path_a_ok = rtl8188eu_iqk_path_a(priv); 862 if (path_a_ok == 0x01) { 863 val32 = rtl8xxxu_read32(priv, 864 REG_TX_POWER_BEFORE_IQK_A); 865 result[t][0] = (val32 >> 16) & 0x3ff; 866 val32 = rtl8xxxu_read32(priv, 867 REG_TX_POWER_AFTER_IQK_A); 868 result[t][1] = (val32 >> 16) & 0x3ff; 869 break; 870 } 871 } 872 873 if (!path_a_ok) 874 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__); 875 876 for (i = 0; i < retry; i++) { 877 path_a_ok = rtl8188eu_rx_iqk_path_a(priv); 878 if (path_a_ok == 0x03) { 879 val32 = rtl8xxxu_read32(priv, 880 REG_RX_POWER_BEFORE_IQK_A_2); 881 result[t][2] = (val32 >> 16) & 0x3ff; 882 val32 = rtl8xxxu_read32(priv, 883 REG_RX_POWER_AFTER_IQK_A_2); 884 result[t][3] = (val32 >> 16) & 0x3ff; 885 886 break; 887 } 888 } 889 890 if (!path_a_ok) 891 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__); 892 893 /* Back to BB mode, load original value */ 894 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); 895 u32p_replace_bits(&val32, 0, 0xffffff00); 896 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); 897 898 if (t == 0) 899 return; 900 901 if (!priv->pi_enabled) { 902 /* Switch back BB to SI mode after finishing IQ Calibration */ 903 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000); 904 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000000); 905 } 906 907 /* Reload ADDA power saving parameters */ 908 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, 909 RTL8XXXU_ADDA_REGS); 910 911 /* Reload MAC parameters */ 912 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 913 914 /* Reload BB parameters */ 915 rtl8xxxu_restore_regs(priv, iqk_bb_regs, 916 priv->bb_backup, RTL8XXXU_BB_REGS); 917 918 /* Restore RX initial gain */ 919 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3); 920 921 /* Load 0xe30 IQC default value */ 922 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); 923 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); 924 } 925 926 static void rtl8188eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) 927 { 928 struct device *dev = &priv->udev->dev; 929 int result[4][8]; /* last is final result */ 930 int i, candidate; 931 bool path_a_ok; 932 u32 reg_e94, reg_e9c, reg_ea4, reg_eac; 933 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; 934 bool simu; 935 936 memset(result, 0, sizeof(result)); 937 result[3][0] = 0x100; 938 result[3][2] = 0x100; 939 result[3][4] = 0x100; 940 result[3][6] = 0x100; 941 942 candidate = -1; 943 944 path_a_ok = false; 945 946 for (i = 0; i < 3; i++) { 947 rtl8188eu_phy_iqcalibrate(priv, result, i); 948 949 if (i == 1) { 950 simu = rtl8xxxu_simularity_compare(priv, 951 result, 0, 1); 952 if (simu) { 953 candidate = 0; 954 break; 955 } 956 } 957 958 if (i == 2) { 959 simu = rtl8xxxu_simularity_compare(priv, 960 result, 0, 2); 961 if (simu) { 962 candidate = 0; 963 break; 964 } 965 966 simu = rtl8xxxu_simularity_compare(priv, 967 result, 1, 2); 968 if (simu) 969 candidate = 1; 970 else 971 candidate = 3; 972 } 973 } 974 975 if (candidate >= 0) { 976 reg_e94 = result[candidate][0]; 977 priv->rege94 = reg_e94; 978 reg_e9c = result[candidate][1]; 979 priv->rege9c = reg_e9c; 980 reg_ea4 = result[candidate][2]; 981 reg_eac = result[candidate][3]; 982 reg_eb4 = result[candidate][4]; 983 priv->regeb4 = reg_eb4; 984 reg_ebc = result[candidate][5]; 985 priv->regebc = reg_ebc; 986 reg_ec4 = result[candidate][6]; 987 reg_ecc = result[candidate][7]; 988 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); 989 dev_dbg(dev, 990 "%s: e94=%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", 991 __func__, reg_e94, reg_e9c, reg_ea4, reg_eac, 992 reg_eb4, reg_ebc, reg_ec4, reg_ecc); 993 path_a_ok = true; 994 } else { 995 reg_e94 = 0x100; 996 reg_eb4 = 0x100; 997 priv->rege94 = 0x100; 998 priv->regeb4 = 0x100; 999 reg_e9c = 0x0; 1000 reg_ebc = 0x0; 1001 priv->rege9c = 0x0; 1002 priv->regebc = 0x0; 1003 } 1004 1005 if (reg_e94 && candidate >= 0) 1006 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, 1007 candidate, (reg_ea4 == 0)); 1008 1009 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, 1010 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); 1011 } 1012 1013 static void rtl8188e_disabled_to_emu(struct rtl8xxxu_priv *priv) 1014 { 1015 u16 val16; 1016 1017 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); 1018 val16 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE); 1019 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); 1020 } 1021 1022 static int rtl8188e_emu_to_active(struct rtl8xxxu_priv *priv) 1023 { 1024 u8 val8; 1025 u32 val32; 1026 u16 val16; 1027 int count, ret = 0; 1028 1029 /* wait till 0x04[17] = 1 power ready*/ 1030 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1031 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1032 if (val32 & BIT(17)) 1033 break; 1034 1035 udelay(10); 1036 } 1037 1038 if (!count) { 1039 ret = -EBUSY; 1040 goto exit; 1041 } 1042 1043 /* reset baseband */ 1044 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 1045 val8 &= ~(SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN); 1046 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 1047 1048 /*0x24[23] = 2b'01 schmit trigger */ 1049 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); 1050 val32 |= BIT(23); 1051 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); 1052 1053 /* 0x04[15] = 0 disable HWPDN (control by DRV)*/ 1054 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); 1055 val16 &= ~APS_FSMCO_HW_POWERDOWN; 1056 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); 1057 1058 /*0x04[12:11] = 2b'00 disable WL suspend*/ 1059 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); 1060 val16 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE); 1061 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); 1062 1063 /* set, then poll until 0 */ 1064 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1065 val32 |= APS_FSMCO_MAC_ENABLE; 1066 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); 1067 1068 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1069 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1070 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { 1071 ret = 0; 1072 break; 1073 } 1074 udelay(10); 1075 } 1076 1077 if (!count) { 1078 ret = -EBUSY; 1079 goto exit; 1080 } 1081 1082 /* LDO normal mode*/ 1083 val8 = rtl8xxxu_read8(priv, REG_LPLDO_CTRL); 1084 val8 &= ~BIT(4); 1085 rtl8xxxu_write8(priv, REG_LPLDO_CTRL, val8); 1086 1087 exit: 1088 return ret; 1089 } 1090 1091 static int rtl8188eu_active_to_emu(struct rtl8xxxu_priv *priv) 1092 { 1093 u8 val8; 1094 1095 /* Turn off RF */ 1096 val8 = rtl8xxxu_read8(priv, REG_RF_CTRL); 1097 val8 &= ~RF_ENABLE; 1098 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); 1099 1100 /* LDO Sleep mode */ 1101 val8 = rtl8xxxu_read8(priv, REG_LPLDO_CTRL); 1102 val8 |= BIT(4); 1103 rtl8xxxu_write8(priv, REG_LPLDO_CTRL, val8); 1104 1105 return 0; 1106 } 1107 1108 static int rtl8188eu_emu_to_disabled(struct rtl8xxxu_priv *priv) 1109 { 1110 u32 val32; 1111 u16 val16; 1112 u8 val8; 1113 1114 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); 1115 val32 |= BIT(23); 1116 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); 1117 1118 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); 1119 val16 &= ~APS_FSMCO_PCIE; 1120 val16 |= APS_FSMCO_HW_SUSPEND; 1121 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); 1122 1123 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x00); 1124 1125 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG + 1); 1126 val8 &= ~BIT(4); 1127 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG + 1, val8); 1128 1129 /* Set USB suspend enable local register 0xfe10[4]=1 */ 1130 val8 = rtl8xxxu_read8(priv, 0xfe10); 1131 val8 |= BIT(4); 1132 rtl8xxxu_write8(priv, 0xfe10, val8); 1133 1134 return 0; 1135 } 1136 1137 static int rtl8188eu_active_to_lps(struct rtl8xxxu_priv *priv) 1138 { 1139 struct device *dev = &priv->udev->dev; 1140 u8 val8; 1141 u16 val16; 1142 u32 val32; 1143 int retry, retval; 1144 1145 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x7f); 1146 1147 retry = 100; 1148 retval = -EBUSY; 1149 /* Poll 32 bit wide REG_SCH_TX_CMD for 0 to ensure no TX is pending. */ 1150 do { 1151 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); 1152 if (!val32) { 1153 retval = 0; 1154 break; 1155 } 1156 } while (retry--); 1157 1158 if (!retry) { 1159 dev_warn(dev, "Failed to flush TX queue\n"); 1160 retval = -EBUSY; 1161 goto out; 1162 } 1163 1164 /* Disable CCK and OFDM, clock gated */ 1165 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); 1166 val8 &= ~SYS_FUNC_BBRSTB; 1167 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); 1168 1169 udelay(2); 1170 1171 /* Reset MAC TRX */ 1172 val16 = rtl8xxxu_read16(priv, REG_CR); 1173 val16 |= 0xff; 1174 val16 &= ~(CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | CR_SECURITY_ENABLE); 1175 rtl8xxxu_write16(priv, REG_CR, val16); 1176 1177 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); 1178 val8 |= DUAL_TSF_TX_OK; 1179 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); 1180 1181 out: 1182 return retval; 1183 } 1184 1185 static int rtl8188eu_power_on(struct rtl8xxxu_priv *priv) 1186 { 1187 u16 val16; 1188 int ret; 1189 1190 rtl8188e_disabled_to_emu(priv); 1191 1192 ret = rtl8188e_emu_to_active(priv); 1193 if (ret) 1194 goto exit; 1195 1196 /* 1197 * Enable MAC DMA/WMAC/SCHEDULE/SEC block 1198 * Set CR bit10 to enable 32k calibration. 1199 * We do not set CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE here 1200 * due to a hardware bug in the 88E, requiring those to be 1201 * set after REG_TRXFF_BNDY is set. If not the RXFF bundary 1202 * will get set to a larger buffer size than the real buffer 1203 * size. 1204 */ 1205 val16 = (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | 1206 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | 1207 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | 1208 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); 1209 rtl8xxxu_write16(priv, REG_CR, val16); 1210 1211 exit: 1212 return ret; 1213 } 1214 1215 static void rtl8188eu_power_off(struct rtl8xxxu_priv *priv) 1216 { 1217 u8 val8; 1218 u16 val16; 1219 1220 rtl8xxxu_flush_fifo(priv); 1221 1222 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); 1223 val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; 1224 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); 1225 1226 /* Turn off RF */ 1227 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); 1228 1229 rtl8188eu_active_to_lps(priv); 1230 1231 /* Reset Firmware if running in RAM */ 1232 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) 1233 rtl8xxxu_firmware_self_reset(priv); 1234 1235 /* Reset MCU */ 1236 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); 1237 val16 &= ~SYS_FUNC_CPU_ENABLE; 1238 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); 1239 1240 /* Reset MCU ready status */ 1241 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 1242 1243 /* 32K_CTRL looks to be very 8188e specific */ 1244 val8 = rtl8xxxu_read8(priv, REG_32K_CTRL); 1245 val8 &= ~BIT(0); 1246 rtl8xxxu_write8(priv, REG_32K_CTRL, val8); 1247 1248 rtl8188eu_active_to_emu(priv); 1249 rtl8188eu_emu_to_disabled(priv); 1250 1251 /* Reset MCU IO Wrapper */ 1252 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1253 val8 &= ~BIT(3); 1254 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1255 1256 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); 1257 val8 |= BIT(3); 1258 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); 1259 1260 /* Vendor driver refers to GPIO_IN */ 1261 val8 = rtl8xxxu_read8(priv, REG_GPIO_PIN_CTRL); 1262 /* Vendor driver refers to GPIO_OUT */ 1263 rtl8xxxu_write8(priv, REG_GPIO_PIN_CTRL + 1, val8); 1264 rtl8xxxu_write8(priv, REG_GPIO_PIN_CTRL + 2, 0xff); 1265 1266 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL); 1267 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL, val8 << 4); 1268 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL + 1); 1269 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL + 1, val8 | 0x0f); 1270 1271 /* 1272 * Set LNA, TRSW, EX_PA Pin to output mode 1273 * Referred to as REG_BB_PAD_CTRL in 8188eu vendor driver 1274 */ 1275 rtl8xxxu_write32(priv, REG_PAD_CTRL1, 0x00080808); 1276 1277 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x00); 1278 1279 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, 0x00000000); 1280 } 1281 1282 static void rtl8188e_enable_rf(struct rtl8xxxu_priv *priv) 1283 { 1284 u32 val32; 1285 1286 rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); 1287 1288 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1289 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); 1290 val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A; 1291 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1292 1293 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 1294 } 1295 1296 static void rtl8188e_disable_rf(struct rtl8xxxu_priv *priv) 1297 { 1298 u32 val32; 1299 1300 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1301 val32 &= ~OFDM_RF_PATH_TX_MASK; 1302 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1303 1304 /* Power down RF module */ 1305 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); 1306 1307 rtl8188eu_active_to_emu(priv); 1308 } 1309 1310 static void rtl8188e_usb_quirks(struct rtl8xxxu_priv *priv) 1311 { 1312 u16 val16; 1313 1314 /* 1315 * Technically this is not a USB quirk, but a chip quirk. 1316 * This has to be done after REG_TRXFF_BNDY is set, see 1317 * rtl8188eu_power_on() for details. 1318 */ 1319 val16 = rtl8xxxu_read16(priv, REG_CR); 1320 val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE); 1321 rtl8xxxu_write16(priv, REG_CR, val16); 1322 1323 rtl8xxxu_gen2_usb_quirks(priv); 1324 1325 /* Pre-TX enable WEP/TKIP security */ 1326 rtl8xxxu_write8(priv, REG_EARLY_MODE_CONTROL_8188E + 3, 0x01); 1327 } 1328 1329 static s8 rtl8188e_cck_rssi(struct rtl8xxxu_priv *priv, u8 cck_agc_rpt) 1330 { 1331 /* only use lna 0/1/2/3/7 */ 1332 static const s8 lna_gain_table_0[8] = {17, -1, -13, -29, -32, -35, -38, -41}; 1333 /* only use lna 3/7 */ 1334 static const s8 lna_gain_table_1[8] = {29, 20, 12, 3, -6, -15, -24, -33}; 1335 1336 s8 rx_pwr_all = 0x00; 1337 u8 vga_idx, lna_idx; 1338 s8 lna_gain = 0; 1339 1340 lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK); 1341 vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK); 1342 1343 if (priv->chip_cut >= 8) /* cut I */ /* SMIC */ 1344 lna_gain = lna_gain_table_0[lna_idx]; 1345 else /* TSMC */ 1346 lna_gain = lna_gain_table_1[lna_idx]; 1347 1348 rx_pwr_all = lna_gain - (2 * vga_idx); 1349 1350 return rx_pwr_all; 1351 } 1352 1353 static int rtl8188eu_led_brightness_set(struct led_classdev *led_cdev, 1354 enum led_brightness brightness) 1355 { 1356 struct rtl8xxxu_priv *priv = container_of(led_cdev, 1357 struct rtl8xxxu_priv, 1358 led_cdev); 1359 u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG2); 1360 1361 if (brightness == LED_OFF) { 1362 ledcfg &= ~LEDCFG2_HW_LED_CONTROL; 1363 ledcfg |= LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE; 1364 } else if (brightness == LED_ON) { 1365 ledcfg &= ~(LEDCFG2_HW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE); 1366 ledcfg |= LEDCFG2_SW_LED_CONTROL; 1367 } else if (brightness == RTL8XXXU_HW_LED_CONTROL) { 1368 ledcfg &= ~LEDCFG2_SW_LED_DISABLE; 1369 ledcfg |= LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE; 1370 } 1371 1372 rtl8xxxu_write8(priv, REG_LEDCFG2, ledcfg); 1373 1374 return 0; 1375 } 1376 1377 static void rtl8188e_set_tx_rpt_timing(struct rtl8xxxu_ra_info *ra, u8 timing) 1378 { 1379 u8 idx; 1380 1381 for (idx = 0; idx < 5; idx++) 1382 if (dynamic_tx_rpt_timing[idx] == ra->rpt_time) 1383 break; 1384 1385 if (timing == DEFAULT_TIMING) { 1386 idx = 0; /* 200ms */ 1387 } else if (timing == INCREASE_TIMING) { 1388 if (idx < 5) 1389 idx++; 1390 } else if (timing == DECREASE_TIMING) { 1391 if (idx > 0) 1392 idx--; 1393 } 1394 1395 ra->rpt_time = dynamic_tx_rpt_timing[idx]; 1396 } 1397 1398 static void rtl8188e_rate_down(struct rtl8xxxu_ra_info *ra) 1399 { 1400 u8 rate_id = ra->pre_rate; 1401 u8 lowest_rate = ra->lowest_rate; 1402 u8 highest_rate = ra->highest_rate; 1403 s8 i; 1404 1405 if (rate_id > highest_rate) { 1406 rate_id = highest_rate; 1407 } else if (ra->rate_sgi) { 1408 ra->rate_sgi = 0; 1409 } else if (rate_id > lowest_rate) { 1410 if (rate_id > 0) { 1411 for (i = rate_id - 1; i >= lowest_rate; i--) { 1412 if (ra->ra_use_rate & BIT(i)) { 1413 rate_id = i; 1414 goto rate_down_finish; 1415 } 1416 } 1417 } 1418 } else if (rate_id <= lowest_rate) { 1419 rate_id = lowest_rate; 1420 } 1421 1422 rate_down_finish: 1423 if (ra->ra_waiting_counter == 1) { 1424 ra->ra_waiting_counter++; 1425 ra->ra_pending_counter++; 1426 } else if (ra->ra_waiting_counter > 1) { 1427 ra->ra_waiting_counter = 0; 1428 ra->ra_pending_counter = 0; 1429 } 1430 1431 if (ra->ra_pending_counter >= 4) 1432 ra->ra_pending_counter = 4; 1433 1434 ra->ra_drop_after_down = 1; 1435 1436 ra->decision_rate = rate_id; 1437 1438 rtl8188e_set_tx_rpt_timing(ra, DECREASE_TIMING); 1439 } 1440 1441 static void rtl8188e_rate_up(struct rtl8xxxu_ra_info *ra) 1442 { 1443 u8 rate_id = ra->pre_rate; 1444 u8 highest_rate = ra->highest_rate; 1445 u8 i; 1446 1447 if (ra->ra_waiting_counter == 1) { 1448 ra->ra_waiting_counter = 0; 1449 ra->ra_pending_counter = 0; 1450 } else if (ra->ra_waiting_counter > 1) { 1451 ra->pre_rssi_sta_ra = ra->rssi_sta_ra; 1452 goto rate_up_finish; 1453 } 1454 1455 rtl8188e_set_tx_rpt_timing(ra, DEFAULT_TIMING); 1456 1457 if (rate_id < highest_rate) { 1458 for (i = rate_id + 1; i <= highest_rate; i++) { 1459 if (ra->ra_use_rate & BIT(i)) { 1460 rate_id = i; 1461 goto rate_up_finish; 1462 } 1463 } 1464 } else if (rate_id == highest_rate) { 1465 if (ra->sgi_enable && !ra->rate_sgi) 1466 ra->rate_sgi = 1; 1467 else if (!ra->sgi_enable) 1468 ra->rate_sgi = 0; 1469 } else { /* rate_id > ra->highest_rate */ 1470 rate_id = highest_rate; 1471 } 1472 1473 rate_up_finish: 1474 if (ra->ra_waiting_counter == (4 + pending_for_rate_up_fail[ra->ra_pending_counter])) 1475 ra->ra_waiting_counter = 0; 1476 else 1477 ra->ra_waiting_counter++; 1478 1479 ra->decision_rate = rate_id; 1480 } 1481 1482 static void rtl8188e_reset_ra_counter(struct rtl8xxxu_ra_info *ra) 1483 { 1484 u8 rate_id = ra->decision_rate; 1485 1486 ra->nsc_up = (n_threshold_high[rate_id] + n_threshold_low[rate_id]) >> 1; 1487 ra->nsc_down = (n_threshold_high[rate_id] + n_threshold_low[rate_id]) >> 1; 1488 } 1489 1490 static void rtl8188e_rate_decision(struct rtl8xxxu_ra_info *ra) 1491 { 1492 struct rtl8xxxu_priv *priv = container_of(ra, struct rtl8xxxu_priv, ra_info); 1493 const u8 *retry_penalty_idx_0; 1494 const u8 *retry_penalty_idx_1; 1495 const u8 *retry_penalty_up_idx; 1496 u8 rate_id, penalty_id1, penalty_id2; 1497 int i; 1498 1499 if (ra->total == 0) 1500 return; 1501 1502 if (ra->ra_drop_after_down) { 1503 ra->ra_drop_after_down--; 1504 1505 rtl8188e_reset_ra_counter(ra); 1506 1507 return; 1508 } 1509 1510 if (priv->chip_cut == 8) { /* cut I */ 1511 retry_penalty_idx_0 = retry_penalty_idx_cut_i[0]; 1512 retry_penalty_idx_1 = retry_penalty_idx_cut_i[1]; 1513 retry_penalty_up_idx = retry_penalty_up_idx_cut_i; 1514 } else { 1515 retry_penalty_idx_0 = retry_penalty_idx_normal[0]; 1516 retry_penalty_idx_1 = retry_penalty_idx_normal[1]; 1517 retry_penalty_up_idx = retry_penalty_up_idx_normal; 1518 } 1519 1520 if (ra->rssi_sta_ra < (ra->pre_rssi_sta_ra - 3) || 1521 ra->rssi_sta_ra > (ra->pre_rssi_sta_ra + 3)) { 1522 ra->pre_rssi_sta_ra = ra->rssi_sta_ra; 1523 ra->ra_waiting_counter = 0; 1524 ra->ra_pending_counter = 0; 1525 } 1526 1527 /* Start RA decision */ 1528 if (ra->pre_rate > ra->highest_rate) 1529 rate_id = ra->highest_rate; 1530 else 1531 rate_id = ra->pre_rate; 1532 1533 /* rate down */ 1534 if (ra->rssi_sta_ra > rssi_threshold[rate_id]) 1535 penalty_id1 = retry_penalty_idx_0[rate_id]; 1536 else 1537 penalty_id1 = retry_penalty_idx_1[rate_id]; 1538 1539 for (i = 0; i < 5; i++) 1540 ra->nsc_down += ra->retry[i] * retry_penalty[penalty_id1][i]; 1541 1542 if (ra->nsc_down > (ra->total * retry_penalty[penalty_id1][5])) 1543 ra->nsc_down -= ra->total * retry_penalty[penalty_id1][5]; 1544 else 1545 ra->nsc_down = 0; 1546 1547 /* rate up */ 1548 penalty_id2 = retry_penalty_up_idx[rate_id]; 1549 1550 for (i = 0; i < 5; i++) 1551 ra->nsc_up += ra->retry[i] * retry_penalty[penalty_id2][i]; 1552 1553 if (ra->nsc_up > (ra->total * retry_penalty[penalty_id2][5])) 1554 ra->nsc_up -= ra->total * retry_penalty[penalty_id2][5]; 1555 else 1556 ra->nsc_up = 0; 1557 1558 if (ra->nsc_down < n_threshold_low[rate_id] || 1559 ra->drop > dropping_necessary[rate_id]) { 1560 rtl8188e_rate_down(ra); 1561 1562 rtl8xxxu_update_ra_report(&priv->ra_report, ra->decision_rate, 1563 ra->rate_sgi, priv->ra_report.txrate.bw); 1564 } else if (ra->nsc_up > n_threshold_high[rate_id]) { 1565 rtl8188e_rate_up(ra); 1566 1567 rtl8xxxu_update_ra_report(&priv->ra_report, ra->decision_rate, 1568 ra->rate_sgi, priv->ra_report.txrate.bw); 1569 } 1570 1571 if (ra->decision_rate == ra->pre_rate) 1572 ra->dynamic_tx_rpt_timing_counter++; 1573 else 1574 ra->dynamic_tx_rpt_timing_counter = 0; 1575 1576 if (ra->dynamic_tx_rpt_timing_counter >= 4) { 1577 /* Rate didn't change 4 times, extend RPT timing */ 1578 rtl8188e_set_tx_rpt_timing(ra, INCREASE_TIMING); 1579 ra->dynamic_tx_rpt_timing_counter = 0; 1580 } 1581 1582 ra->pre_rate = ra->decision_rate; 1583 1584 rtl8188e_reset_ra_counter(ra); 1585 } 1586 1587 static void rtl8188e_power_training_try_state(struct rtl8xxxu_ra_info *ra) 1588 { 1589 ra->pt_try_state = 0; 1590 switch (ra->pt_mode_ss) { 1591 case 3: 1592 if (ra->decision_rate >= DESC_RATE_MCS13) 1593 ra->pt_try_state = 1; 1594 break; 1595 case 2: 1596 if (ra->decision_rate >= DESC_RATE_MCS5) 1597 ra->pt_try_state = 1; 1598 break; 1599 case 1: 1600 if (ra->decision_rate >= DESC_RATE_48M) 1601 ra->pt_try_state = 1; 1602 break; 1603 case 0: 1604 if (ra->decision_rate >= DESC_RATE_11M) 1605 ra->pt_try_state = 1; 1606 break; 1607 default: 1608 break; 1609 } 1610 1611 if (ra->rssi_sta_ra < 48) { 1612 ra->pt_stage = 0; 1613 } else if (ra->pt_try_state == 1) { 1614 if ((ra->pt_stop_count >= 10) || 1615 (ra->pt_pre_rssi > ra->rssi_sta_ra + 5) || 1616 (ra->pt_pre_rssi < ra->rssi_sta_ra - 5) || 1617 (ra->decision_rate != ra->pt_pre_rate)) { 1618 if (ra->pt_stage == 0) 1619 ra->pt_stage = 1; 1620 else if (ra->pt_stage == 1) 1621 ra->pt_stage = 3; 1622 else 1623 ra->pt_stage = 5; 1624 1625 ra->pt_pre_rssi = ra->rssi_sta_ra; 1626 ra->pt_stop_count = 0; 1627 } else { 1628 ra->ra_stage = 0; 1629 ra->pt_stop_count++; 1630 } 1631 } else { 1632 ra->pt_stage = 0; 1633 ra->ra_stage = 0; 1634 } 1635 1636 ra->pt_pre_rate = ra->decision_rate; 1637 1638 /* TODO: implement the "false alarm" statistics for this */ 1639 /* Disable power training when noisy environment */ 1640 /* if (p_dm_odm->is_disable_power_training) { */ 1641 if (1) { 1642 ra->pt_stage = 0; 1643 ra->ra_stage = 0; 1644 ra->pt_stop_count = 0; 1645 } 1646 } 1647 1648 static void rtl8188e_power_training_decision(struct rtl8xxxu_ra_info *ra) 1649 { 1650 u8 temp_stage; 1651 u32 numsc; 1652 u32 num_total; 1653 u8 stage_id; 1654 u8 j; 1655 1656 numsc = 0; 1657 num_total = ra->total * pt_penalty[5]; 1658 for (j = 0; j <= 4; j++) { 1659 numsc += ra->retry[j] * pt_penalty[j]; 1660 1661 if (numsc > num_total) 1662 break; 1663 } 1664 1665 j >>= 1; 1666 temp_stage = (ra->pt_stage + 1) >> 1; 1667 if (temp_stage > j) 1668 stage_id = temp_stage - j; 1669 else 1670 stage_id = 0; 1671 1672 ra->pt_smooth_factor = (ra->pt_smooth_factor >> 1) + 1673 (ra->pt_smooth_factor >> 2) + 1674 stage_id * 16 + 2; 1675 if (ra->pt_smooth_factor > 192) 1676 ra->pt_smooth_factor = 192; 1677 stage_id = ra->pt_smooth_factor >> 6; 1678 temp_stage = stage_id * 2; 1679 if (temp_stage != 0) 1680 temp_stage--; 1681 if (ra->drop > 3) 1682 temp_stage = 0; 1683 ra->pt_stage = temp_stage; 1684 } 1685 1686 void rtl8188e_handle_ra_tx_report2(struct rtl8xxxu_priv *priv, struct sk_buff *skb) 1687 { 1688 u32 *_rx_desc = (u32 *)(skb->data - sizeof(struct rtl8xxxu_rxdesc16)); 1689 struct rtl8xxxu_rxdesc16 *rx_desc = (struct rtl8xxxu_rxdesc16 *)_rx_desc; 1690 struct device *dev = &priv->udev->dev; 1691 struct rtl8xxxu_ra_info *ra = &priv->ra_info; 1692 u32 tx_rpt_len = rx_desc->pktlen & 0x3ff; 1693 u32 items = tx_rpt_len / TX_RPT2_ITEM_SIZE; 1694 u64 macid_valid = ((u64)_rx_desc[5] << 32) | _rx_desc[4]; 1695 u32 macid; 1696 u8 *rpt = skb->data; 1697 bool valid; 1698 u16 min_rpt_time = 0x927c; 1699 1700 dev_dbg(dev, "%s: len: %d items: %d\n", __func__, tx_rpt_len, items); 1701 1702 for (macid = 0; macid < items; macid++) { 1703 valid = false; 1704 1705 if (macid < 64) 1706 valid = macid_valid & BIT(macid); 1707 1708 if (valid) { 1709 ra->retry[0] = le16_to_cpu(*(__le16 *)rpt); 1710 ra->retry[1] = rpt[2]; 1711 ra->retry[2] = rpt[3]; 1712 ra->retry[3] = rpt[4]; 1713 ra->retry[4] = rpt[5]; 1714 ra->drop = rpt[6]; 1715 ra->total = ra->retry[0] + ra->retry[1] + ra->retry[2] + 1716 ra->retry[3] + ra->retry[4] + ra->drop; 1717 1718 if (ra->total > 0) { 1719 if (ra->ra_stage < 5) 1720 rtl8188e_rate_decision(ra); 1721 else if (ra->ra_stage == 5) 1722 rtl8188e_power_training_try_state(ra); 1723 else /* ra->ra_stage == 6 */ 1724 rtl8188e_power_training_decision(ra); 1725 1726 if (ra->ra_stage <= 5) 1727 ra->ra_stage++; 1728 else 1729 ra->ra_stage = 0; 1730 } 1731 } else if (macid == 0) { 1732 dev_warn(dev, "%s: TX report item 0 not valid\n", __func__); 1733 } 1734 1735 dev_dbg(dev, "%s: valid: %d retry: %d %d %d %d %d drop: %d\n", 1736 __func__, valid, 1737 ra->retry[0], ra->retry[1], ra->retry[2], 1738 ra->retry[3], ra->retry[4], ra->drop); 1739 1740 if (min_rpt_time > ra->rpt_time) 1741 min_rpt_time = ra->rpt_time; 1742 1743 rpt += TX_RPT2_ITEM_SIZE; 1744 1745 /* 1746 * We only use macid 0, so only the first item is relevant. 1747 * AP mode will use more of them if it's ever implemented. 1748 */ 1749 break; 1750 } 1751 1752 if (min_rpt_time != ra->pre_min_rpt_time) { 1753 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, min_rpt_time); 1754 ra->pre_min_rpt_time = min_rpt_time; 1755 } 1756 } 1757 1758 static void rtl8188e_arfb_refresh(struct rtl8xxxu_ra_info *ra) 1759 { 1760 s8 i; 1761 1762 ra->ra_use_rate = ra->rate_mask; 1763 1764 /* Highest rate */ 1765 if (ra->ra_use_rate) { 1766 for (i = RATESIZE; i >= 0; i--) { 1767 if (ra->ra_use_rate & BIT(i)) { 1768 ra->highest_rate = i; 1769 break; 1770 } 1771 } 1772 } else { 1773 ra->highest_rate = 0; 1774 } 1775 1776 /* Lowest rate */ 1777 if (ra->ra_use_rate) { 1778 for (i = 0; i < RATESIZE; i++) { 1779 if (ra->ra_use_rate & BIT(i)) { 1780 ra->lowest_rate = i; 1781 break; 1782 } 1783 } 1784 } else { 1785 ra->lowest_rate = 0; 1786 } 1787 1788 if (ra->highest_rate > DESC_RATE_MCS7) 1789 ra->pt_mode_ss = 3; 1790 else if (ra->highest_rate > DESC_RATE_54M) 1791 ra->pt_mode_ss = 2; 1792 else if (ra->highest_rate > DESC_RATE_11M) 1793 ra->pt_mode_ss = 1; 1794 else 1795 ra->pt_mode_ss = 0; 1796 } 1797 1798 static void 1799 rtl8188e_update_rate_mask(struct rtl8xxxu_priv *priv, 1800 u32 ramask, u8 rateid, int sgi, int txbw_40mhz) 1801 { 1802 struct rtl8xxxu_ra_info *ra = &priv->ra_info; 1803 1804 ra->rate_id = rateid; 1805 ra->rate_mask = ramask; 1806 ra->sgi_enable = sgi; 1807 1808 rtl8188e_arfb_refresh(ra); 1809 } 1810 1811 static void rtl8188e_ra_set_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi) 1812 { 1813 priv->ra_info.rssi_sta_ra = rssi; 1814 } 1815 1816 void rtl8188e_ra_info_init_all(struct rtl8xxxu_ra_info *ra) 1817 { 1818 ra->decision_rate = DESC_RATE_MCS7; 1819 ra->pre_rate = DESC_RATE_MCS7; 1820 ra->highest_rate = DESC_RATE_MCS7; 1821 ra->lowest_rate = 0; 1822 ra->rate_id = 0; 1823 ra->rate_mask = 0xfffff; 1824 ra->rssi_sta_ra = 0; 1825 ra->pre_rssi_sta_ra = 0; 1826 ra->sgi_enable = 0; 1827 ra->ra_use_rate = 0xfffff; 1828 ra->nsc_down = (n_threshold_high[DESC_RATE_MCS7] + n_threshold_low[DESC_RATE_MCS7]) / 2; 1829 ra->nsc_up = (n_threshold_high[DESC_RATE_MCS7] + n_threshold_low[DESC_RATE_MCS7]) / 2; 1830 ra->rate_sgi = 0; 1831 ra->rpt_time = 0x927c; 1832 ra->drop = 0; 1833 ra->retry[0] = 0; 1834 ra->retry[1] = 0; 1835 ra->retry[2] = 0; 1836 ra->retry[3] = 0; 1837 ra->retry[4] = 0; 1838 ra->total = 0; 1839 ra->ra_waiting_counter = 0; 1840 ra->ra_pending_counter = 0; 1841 ra->ra_drop_after_down = 0; 1842 1843 ra->pt_try_state = 0; 1844 ra->pt_stage = 5; 1845 ra->pt_smooth_factor = 192; 1846 ra->pt_stop_count = 0; 1847 ra->pt_pre_rate = 0; 1848 ra->pt_pre_rssi = 0; 1849 ra->pt_mode_ss = 0; 1850 ra->ra_stage = 0; 1851 } 1852 1853 struct rtl8xxxu_fileops rtl8188eu_fops = { 1854 .identify_chip = rtl8188eu_identify_chip, 1855 .parse_efuse = rtl8188eu_parse_efuse, 1856 .load_firmware = rtl8188eu_load_firmware, 1857 .power_on = rtl8188eu_power_on, 1858 .power_off = rtl8188eu_power_off, 1859 .reset_8051 = rtl8188eu_reset_8051, 1860 .llt_init = rtl8xxxu_init_llt_table, 1861 .init_phy_bb = rtl8188eu_init_phy_bb, 1862 .init_phy_rf = rtl8188eu_init_phy_rf, 1863 .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, 1864 .phy_iq_calibrate = rtl8188eu_phy_iq_calibrate, 1865 .config_channel = rtl8188eu_config_channel, 1866 .parse_rx_desc = rtl8xxxu_parse_rxdesc16, 1867 .init_aggregation = rtl8188eu_init_aggregation, 1868 .enable_rf = rtl8188e_enable_rf, 1869 .disable_rf = rtl8188e_disable_rf, 1870 .usb_quirks = rtl8188e_usb_quirks, 1871 .set_tx_power = rtl8188f_set_tx_power, 1872 .update_rate_mask = rtl8188e_update_rate_mask, 1873 .report_connect = rtl8xxxu_gen2_report_connect, 1874 .report_rssi = rtl8188e_ra_set_rssi, 1875 .fill_txdesc = rtl8xxxu_fill_txdesc_v3, 1876 .set_crystal_cap = rtl8188f_set_crystal_cap, 1877 .cck_rssi = rtl8188e_cck_rssi, 1878 .led_classdev_brightness_set = rtl8188eu_led_brightness_set, 1879 .writeN_block_size = 128, 1880 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16), 1881 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32), 1882 .has_tx_report = 1, 1883 .gen2_thermal_meter = 1, 1884 .adda_1t_init = 0x0b1b25a0, 1885 .adda_1t_path_on = 0x0bdb25a0, 1886 /* 1887 * Use 9K for 8188e normal chip 1888 * Max RX buffer = 10K - max(TxReportSize(64*8), WOLPattern(16*24)) 1889 */ 1890 .trxff_boundary = 0x25ff, 1891 .pbp_rx = PBP_PAGE_SIZE_128, 1892 .pbp_tx = PBP_PAGE_SIZE_128, 1893 .mactable = rtl8188e_mac_init_table, 1894 .total_page_num = TX_TOTAL_PAGE_NUM_8188E, 1895 .page_num_hi = TX_PAGE_NUM_HI_PQ_8188E, 1896 .page_num_lo = TX_PAGE_NUM_LO_PQ_8188E, 1897 .page_num_norm = TX_PAGE_NUM_NORM_PQ_8188E, 1898 .last_llt_entry = 175, 1899 }; 1900