1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 4 * 5 * Register definitions taken from original Realtek rtl8723au driver 6 */ 7 8 #include <asm/byteorder.h> 9 10 #define RTL8XXXU_DEBUG_REG_WRITE 0x01 11 #define RTL8XXXU_DEBUG_REG_READ 0x02 12 #define RTL8XXXU_DEBUG_RFREG_WRITE 0x04 13 #define RTL8XXXU_DEBUG_RFREG_READ 0x08 14 #define RTL8XXXU_DEBUG_CHANNEL 0x10 15 #define RTL8XXXU_DEBUG_TX 0x20 16 #define RTL8XXXU_DEBUG_TX_DUMP 0x40 17 #define RTL8XXXU_DEBUG_RX 0x80 18 #define RTL8XXXU_DEBUG_RX_DUMP 0x100 19 #define RTL8XXXU_DEBUG_USB 0x200 20 #define RTL8XXXU_DEBUG_KEY 0x400 21 #define RTL8XXXU_DEBUG_H2C 0x800 22 #define RTL8XXXU_DEBUG_ACTION 0x1000 23 #define RTL8XXXU_DEBUG_EFUSE 0x2000 24 #define RTL8XXXU_DEBUG_INTERRUPT 0x4000 25 26 #define RTW_USB_CONTROL_MSG_TIMEOUT 500 27 #define RTL8XXXU_MAX_REG_POLL 500 28 #define USB_INTR_CONTENT_LENGTH 56 29 30 #define RTL8XXXU_OUT_ENDPOINTS 4 31 32 #define REALTEK_USB_READ 0xc0 33 #define REALTEK_USB_WRITE 0x40 34 #define REALTEK_USB_CMD_REQ 0x05 35 #define REALTEK_USB_CMD_IDX 0x00 36 37 #define TX_TOTAL_PAGE_NUM 0xf8 38 #define TX_TOTAL_PAGE_NUM_8192E 0xf3 39 #define TX_TOTAL_PAGE_NUM_8723B 0xf7 40 /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */ 41 #define TX_PAGE_NUM_PUBQ 0xe7 42 #define TX_PAGE_NUM_HI_PQ 0x0c 43 #define TX_PAGE_NUM_LO_PQ 0x02 44 #define TX_PAGE_NUM_NORM_PQ 0x02 45 46 #define TX_PAGE_NUM_PUBQ_8192E 0xe7 47 #define TX_PAGE_NUM_HI_PQ_8192E 0x08 48 #define TX_PAGE_NUM_LO_PQ_8192E 0x0c 49 #define TX_PAGE_NUM_NORM_PQ_8192E 0x00 50 51 #define TX_PAGE_NUM_PUBQ_8723B 0xe7 52 #define TX_PAGE_NUM_HI_PQ_8723B 0x0c 53 #define TX_PAGE_NUM_LO_PQ_8723B 0x02 54 #define TX_PAGE_NUM_NORM_PQ_8723B 0x02 55 56 #define RTL_FW_PAGE_SIZE 4096 57 #define RTL8XXXU_FIRMWARE_POLL_MAX 1000 58 59 #define RTL8723A_CHANNEL_GROUPS 3 60 #define RTL8723A_MAX_RF_PATHS 2 61 #define RTL8723B_CHANNEL_GROUPS 6 62 #define RTL8723B_TX_COUNT 4 63 #define RTL8723B_MAX_RF_PATHS 4 64 #define RTL8XXXU_MAX_CHANNEL_GROUPS 6 65 #define RF6052_MAX_TX_PWR 0x3f 66 67 #define EFUSE_MAP_LEN 512 68 #define EFUSE_MAX_SECTION_8723A 64 69 #define EFUSE_REAL_CONTENT_LEN_8723A 512 70 #define EFUSE_BT_MAP_LEN_8723A 1024 71 #define EFUSE_MAX_WORD_UNIT 4 72 73 enum rtl8xxxu_rtl_chip { 74 RTL8192S = 0x81920, 75 RTL8191S = 0x81910, 76 RTL8192C = 0x8192c, 77 RTL8191C = 0x8191c, 78 RTL8188C = 0x8188c, 79 RTL8188R = 0x81889, 80 RTL8192D = 0x8192d, 81 RTL8723A = 0x8723a, 82 RTL8188E = 0x8188e, 83 RTL8812 = 0x88120, 84 RTL8821 = 0x88210, 85 RTL8192E = 0x8192e, 86 RTL8191E = 0x8191e, 87 RTL8723B = 0x8723b, 88 RTL8814A = 0x8814a, 89 RTL8881A = 0x8881a, 90 RTL8821B = 0x8821b, 91 RTL8822B = 0x8822b, 92 RTL8703B = 0x8703b, 93 RTL8195A = 0x8195a, 94 RTL8188F = 0x8188f 95 }; 96 97 enum rtl8xxxu_rx_type { 98 RX_TYPE_DATA_PKT = 0, 99 RX_TYPE_C2H = 1, 100 RX_TYPE_ERROR = -1 101 }; 102 103 struct rtl8xxxu_rxdesc16 { 104 #ifdef __LITTLE_ENDIAN 105 u32 pktlen:14; 106 u32 crc32:1; 107 u32 icverr:1; 108 u32 drvinfo_sz:4; 109 u32 security:3; 110 u32 qos:1; 111 u32 shift:2; 112 u32 phy_stats:1; 113 u32 swdec:1; 114 u32 ls:1; 115 u32 fs:1; 116 u32 eor:1; 117 u32 own:1; 118 119 u32 macid:5; 120 u32 tid:4; 121 u32 hwrsvd:4; 122 u32 amsdu:1; 123 u32 paggr:1; 124 u32 faggr:1; 125 u32 a1fit:4; 126 u32 a2fit:4; 127 u32 pam:1; 128 u32 pwr:1; 129 u32 md:1; 130 u32 mf:1; 131 u32 type:2; 132 u32 mc:1; 133 u32 bc:1; 134 135 u32 seq:12; 136 u32 frag:4; 137 u32 pkt_cnt:8; 138 u32 reserved:6; 139 u32 nextind:1; 140 u32 reserved0:1; 141 142 u32 rxmcs:6; 143 u32 rxht:1; 144 u32 gf:1; 145 u32 splcp:1; 146 u32 bw:1; 147 u32 htc:1; 148 u32 eosp:1; 149 u32 bssidfit:2; 150 u32 reserved1:16; 151 u32 unicastwake:1; 152 u32 magicwake:1; 153 154 u32 pattern0match:1; 155 u32 pattern1match:1; 156 u32 pattern2match:1; 157 u32 pattern3match:1; 158 u32 pattern4match:1; 159 u32 pattern5match:1; 160 u32 pattern6match:1; 161 u32 pattern7match:1; 162 u32 pattern8match:1; 163 u32 pattern9match:1; 164 u32 patternamatch:1; 165 u32 patternbmatch:1; 166 u32 patterncmatch:1; 167 u32 reserved2:19; 168 #else 169 u32 own:1; 170 u32 eor:1; 171 u32 fs:1; 172 u32 ls:1; 173 u32 swdec:1; 174 u32 phy_stats:1; 175 u32 shift:2; 176 u32 qos:1; 177 u32 security:3; 178 u32 drvinfo_sz:4; 179 u32 icverr:1; 180 u32 crc32:1; 181 u32 pktlen:14; 182 183 u32 bc:1; 184 u32 mc:1; 185 u32 type:2; 186 u32 mf:1; 187 u32 md:1; 188 u32 pwr:1; 189 u32 pam:1; 190 u32 a2fit:4; 191 u32 a1fit:4; 192 u32 faggr:1; 193 u32 paggr:1; 194 u32 amsdu:1; 195 u32 hwrsvd:4; 196 u32 tid:4; 197 u32 macid:5; 198 199 u32 reserved0:1; 200 u32 nextind:1; 201 u32 reserved:6; 202 u32 pkt_cnt:8; 203 u32 frag:4; 204 u32 seq:12; 205 206 u32 magicwake:1; 207 u32 unicastwake:1; 208 u32 reserved1:16; 209 u32 bssidfit:2; 210 u32 eosp:1; 211 u32 htc:1; 212 u32 bw:1; 213 u32 splcp:1; 214 u32 gf:1; 215 u32 rxht:1; 216 u32 rxmcs:6; 217 218 u32 reserved2:19; 219 u32 patterncmatch:1; 220 u32 patternbmatch:1; 221 u32 patternamatch:1; 222 u32 pattern9match:1; 223 u32 pattern8match:1; 224 u32 pattern7match:1; 225 u32 pattern6match:1; 226 u32 pattern5match:1; 227 u32 pattern4match:1; 228 u32 pattern3match:1; 229 u32 pattern2match:1; 230 u32 pattern1match:1; 231 u32 pattern0match:1; 232 #endif 233 u32 tsfl; 234 #if 0 235 u32 bassn:12; 236 u32 bavld:1; 237 u32 reserved3:19; 238 #endif 239 }; 240 241 struct rtl8xxxu_rxdesc24 { 242 #ifdef __LITTLE_ENDIAN 243 u32 pktlen:14; 244 u32 crc32:1; 245 u32 icverr:1; 246 u32 drvinfo_sz:4; 247 u32 security:3; 248 u32 qos:1; 249 u32 shift:2; 250 u32 phy_stats:1; 251 u32 swdec:1; 252 u32 ls:1; 253 u32 fs:1; 254 u32 eor:1; 255 u32 own:1; 256 257 u32 macid:7; 258 u32 dummy1_0:1; 259 u32 tid:4; 260 u32 dummy1_1:1; 261 u32 amsdu:1; 262 u32 rxid_match:1; 263 u32 paggr:1; 264 u32 a1fit:4; /* 16 */ 265 u32 chkerr:1; 266 u32 ipver:1; 267 u32 tcpudp:1; 268 u32 chkvld:1; 269 u32 pam:1; 270 u32 pwr:1; 271 u32 more_data:1; 272 u32 more_frag:1; 273 u32 type:2; 274 u32 mc:1; 275 u32 bc:1; 276 277 u32 seq:12; 278 u32 frag:4; 279 u32 rx_is_qos:1; /* 16 */ 280 u32 dummy2_0:1; 281 u32 wlanhd_iv_len:6; 282 u32 dummy2_1:4; 283 u32 rpt_sel:1; 284 u32 dummy2_2:3; 285 286 u32 rxmcs:7; 287 u32 dummy3_0:3; 288 u32 htc:1; 289 u32 eosp:1; 290 u32 bssidfit:2; 291 u32 dummy3_1:2; 292 u32 usb_agg_pktnum:8; /* 16 */ 293 u32 dummy3_2:5; 294 u32 pattern_match:1; 295 u32 unicast_match:1; 296 u32 magic_match:1; 297 298 u32 splcp:1; 299 u32 ldcp:1; 300 u32 stbc:1; 301 u32 dummy4_0:1; 302 u32 bw:2; 303 u32 dummy4_1:26; 304 #else 305 u32 own:1; 306 u32 eor:1; 307 u32 fs:1; 308 u32 ls:1; 309 u32 swdec:1; 310 u32 phy_stats:1; 311 u32 shift:2; 312 u32 qos:1; 313 u32 security:3; 314 u32 drvinfo_sz:4; 315 u32 icverr:1; 316 u32 crc32:1; 317 u32 pktlen:14; 318 319 u32 bc:1; 320 u32 mc:1; 321 u32 type:2; 322 u32 mf:1; 323 u32 md:1; 324 u32 pwr:1; 325 u32 pam:1; 326 u32 a2fit:4; 327 u32 a1fit:4; 328 u32 faggr:1; 329 u32 paggr:1; 330 u32 amsdu:1; 331 u32 hwrsvd:4; 332 u32 tid:4; 333 u32 macid:5; 334 335 u32 dummy2_2:3; 336 u32 rpt_sel:1; 337 u32 dummy2_1:4; 338 u32 wlanhd_iv_len:6; 339 u32 dummy2_0:1; 340 u32 rx_is_qos:1; 341 u32 frag:4; /* 16 */ 342 u32 seq:12; 343 344 u32 magic_match:1; 345 u32 unicast_match:1; 346 u32 pattern_match:1; 347 u32 dummy3_2:5; 348 u32 usb_agg_pktnum:8; 349 u32 dummy3_1:2; /* 16 */ 350 u32 bssidfit:2; 351 u32 eosp:1; 352 u32 htc:1; 353 u32 dummy3_0:3; 354 u32 rxmcs:7; 355 356 u32 dumm4_1:26; 357 u32 bw:2; 358 u32 dummy4_0:1; 359 u32 stbc:1; 360 u32 ldcp:1; 361 u32 splcp:1; 362 #endif 363 u32 tsfl; 364 }; 365 366 struct rtl8xxxu_txdesc32 { 367 __le16 pkt_size; 368 u8 pkt_offset; 369 u8 txdw0; 370 __le32 txdw1; 371 __le32 txdw2; 372 __le32 txdw3; 373 __le32 txdw4; 374 __le32 txdw5; 375 __le32 txdw6; 376 __le16 csum; 377 __le16 txdw7; 378 }; 379 380 struct rtl8xxxu_txdesc40 { 381 __le16 pkt_size; 382 u8 pkt_offset; 383 u8 txdw0; 384 __le32 txdw1; 385 __le32 txdw2; 386 __le32 txdw3; 387 __le32 txdw4; 388 __le32 txdw5; 389 __le32 txdw6; 390 __le16 csum; 391 __le16 txdw7; 392 __le32 txdw8; 393 __le32 txdw9; 394 }; 395 396 /* CCK Rates, TxHT = 0 */ 397 #define DESC_RATE_1M 0x00 398 #define DESC_RATE_2M 0x01 399 #define DESC_RATE_5_5M 0x02 400 #define DESC_RATE_11M 0x03 401 402 /* OFDM Rates, TxHT = 0 */ 403 #define DESC_RATE_6M 0x04 404 #define DESC_RATE_9M 0x05 405 #define DESC_RATE_12M 0x06 406 #define DESC_RATE_18M 0x07 407 #define DESC_RATE_24M 0x08 408 #define DESC_RATE_36M 0x09 409 #define DESC_RATE_48M 0x0a 410 #define DESC_RATE_54M 0x0b 411 412 /* MCS Rates, TxHT = 1 */ 413 #define DESC_RATE_MCS0 0x0c 414 #define DESC_RATE_MCS1 0x0d 415 #define DESC_RATE_MCS2 0x0e 416 #define DESC_RATE_MCS3 0x0f 417 #define DESC_RATE_MCS4 0x10 418 #define DESC_RATE_MCS5 0x11 419 #define DESC_RATE_MCS6 0x12 420 #define DESC_RATE_MCS7 0x13 421 #define DESC_RATE_MCS8 0x14 422 #define DESC_RATE_MCS9 0x15 423 #define DESC_RATE_MCS10 0x16 424 #define DESC_RATE_MCS11 0x17 425 #define DESC_RATE_MCS12 0x18 426 #define DESC_RATE_MCS13 0x19 427 #define DESC_RATE_MCS14 0x1a 428 #define DESC_RATE_MCS15 0x1b 429 #define DESC_RATE_MCS15_SG 0x1c 430 #define DESC_RATE_MCS32 0x20 431 432 #define TXDESC_OFFSET_SZ 0 433 #define TXDESC_OFFSET_SHT 16 434 #if 0 435 #define TXDESC_BMC BIT(24) 436 #define TXDESC_LSG BIT(26) 437 #define TXDESC_FSG BIT(27) 438 #define TXDESC_OWN BIT(31) 439 #else 440 #define TXDESC_BROADMULTICAST BIT(0) 441 #define TXDESC_HTC BIT(1) 442 #define TXDESC_LAST_SEGMENT BIT(2) 443 #define TXDESC_FIRST_SEGMENT BIT(3) 444 #define TXDESC_LINIP BIT(4) 445 #define TXDESC_NO_ACM BIT(5) 446 #define TXDESC_GF BIT(6) 447 #define TXDESC_OWN BIT(7) 448 #endif 449 450 /* Word 1 */ 451 /* 452 * Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are 453 * aggregation enable and break respectively. For 8723bu, bits 0-7 are macid. 454 */ 455 #define TXDESC_PKT_OFFSET_SZ 0 456 #define TXDESC32_AGG_ENABLE BIT(5) 457 #define TXDESC32_AGG_BREAK BIT(6) 458 #define TXDESC40_MACID_SHIFT 0 459 #define TXDESC40_MACID_MASK 0x00f0 460 #define TXDESC_QUEUE_SHIFT 8 461 #define TXDESC_QUEUE_MASK 0x1f00 462 #define TXDESC_QUEUE_BK 0x2 463 #define TXDESC_QUEUE_BE 0x0 464 #define TXDESC_QUEUE_VI 0x5 465 #define TXDESC_QUEUE_VO 0x7 466 #define TXDESC_QUEUE_BEACON 0x10 467 #define TXDESC_QUEUE_HIGH 0x11 468 #define TXDESC_QUEUE_MGNT 0x12 469 #define TXDESC_QUEUE_CMD 0x13 470 #define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1) 471 #define TXDESC40_RDG_NAV_EXT BIT(13) 472 #define TXDESC40_LSIG_TXOP_ENABLE BIT(14) 473 #define TXDESC40_PIFS BIT(15) 474 475 #define DESC_RATE_ID_SHIFT 16 476 #define DESC_RATE_ID_MASK 0xf 477 #define TXDESC_NAVUSEHDR BIT(20) 478 #define TXDESC_SEC_RC4 0x00400000 479 #define TXDESC_SEC_AES 0x00c00000 480 #define TXDESC_PKT_OFFSET_SHIFT 26 481 #define TXDESC_AGG_EN BIT(29) 482 #define TXDESC_HWPC BIT(31) 483 484 /* Word 2 */ 485 #define TXDESC40_PAID_SHIFT 0 486 #define TXDESC40_PAID_MASK 0x1ff 487 #define TXDESC40_CCA_RTS_SHIFT 10 488 #define TXDESC40_CCA_RTS_MASK 0xc00 489 #define TXDESC40_AGG_ENABLE BIT(12) 490 #define TXDESC40_RDG_ENABLE BIT(13) 491 #define TXDESC40_AGG_BREAK BIT(16) 492 #define TXDESC40_MORE_FRAG BIT(17) 493 #define TXDESC40_RAW BIT(18) 494 #define TXDESC32_ACK_REPORT BIT(19) 495 #define TXDESC40_SPE_RPT BIT(19) 496 #define TXDESC_AMPDU_DENSITY_SHIFT 20 497 #define TXDESC40_BT_INT BIT(23) 498 #define TXDESC40_GID_SHIFT 24 499 500 /* Word 3 */ 501 #define TXDESC40_USE_DRIVER_RATE BIT(8) 502 #define TXDESC40_CTS_SELF_ENABLE BIT(11) 503 #define TXDESC40_RTS_CTS_ENABLE BIT(12) 504 #define TXDESC40_HW_RTS_ENABLE BIT(13) 505 #define TXDESC32_SEQ_SHIFT 16 506 #define TXDESC32_SEQ_MASK 0x0fff0000 507 508 /* Word 4 */ 509 #define TXDESC32_RTS_RATE_SHIFT 0 510 #define TXDESC32_RTS_RATE_MASK 0x3f 511 #define TXDESC32_QOS BIT(6) 512 #define TXDESC32_HW_SEQ_ENABLE BIT(7) 513 #define TXDESC32_USE_DRIVER_RATE BIT(8) 514 #define TXDESC_DISABLE_DATA_FB BIT(10) 515 #define TXDESC32_CTS_SELF_ENABLE BIT(11) 516 #define TXDESC32_RTS_CTS_ENABLE BIT(12) 517 #define TXDESC32_HW_RTS_ENABLE BIT(13) 518 #define TXDESC_PRIME_CH_OFF_LOWER BIT(20) 519 #define TXDESC_PRIME_CH_OFF_UPPER BIT(21) 520 #define TXDESC32_SHORT_PREAMBLE BIT(24) 521 #define TXDESC_DATA_BW BIT(25) 522 #define TXDESC_RTS_DATA_BW BIT(27) 523 #define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28) 524 #define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29) 525 #define TXDESC40_DATA_RATE_FB_SHIFT 8 526 #define TXDESC40_DATA_RATE_FB_MASK 0x00001f00 527 #define TXDESC40_RETRY_LIMIT_ENABLE BIT(17) 528 #define TXDESC40_RETRY_LIMIT_SHIFT 18 529 #define TXDESC40_RETRY_LIMIT_MASK 0x00fc0000 530 #define TXDESC40_RTS_RATE_SHIFT 24 531 #define TXDESC40_RTS_RATE_MASK 0x3f000000 532 533 /* Word 5 */ 534 #define TXDESC40_SHORT_PREAMBLE BIT(4) 535 #define TXDESC32_SHORT_GI BIT(6) 536 #define TXDESC_CCX_TAG BIT(7) 537 #define TXDESC32_RETRY_LIMIT_ENABLE BIT(17) 538 #define TXDESC32_RETRY_LIMIT_SHIFT 18 539 #define TXDESC32_RETRY_LIMIT_MASK 0x00fc0000 540 541 /* Word 6 */ 542 #define TXDESC_MAX_AGG_SHIFT 11 543 544 /* Word 8 */ 545 #define TXDESC40_HW_SEQ_ENABLE BIT(15) 546 547 /* Word 9 */ 548 #define TXDESC40_SEQ_SHIFT 12 549 #define TXDESC40_SEQ_MASK 0x00fff000 550 551 struct phy_rx_agc_info { 552 #ifdef __LITTLE_ENDIAN 553 u8 gain:7, trsw:1; 554 #else 555 u8 trsw:1, gain:7; 556 #endif 557 }; 558 559 struct rtl8723au_phy_stats { 560 struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS]; 561 u8 ch_corr[RTL8723A_MAX_RF_PATHS]; 562 u8 cck_sig_qual_ofdm_pwdb_all; 563 u8 cck_agc_rpt_ofdm_cfosho_a; 564 u8 cck_rpt_b_ofdm_cfosho_b; 565 u8 reserved_1; 566 u8 noise_power_db_msb; 567 u8 path_cfotail[RTL8723A_MAX_RF_PATHS]; 568 u8 pcts_mask[RTL8723A_MAX_RF_PATHS]; 569 s8 stream_rxevm[RTL8723A_MAX_RF_PATHS]; 570 u8 path_rxsnr[RTL8723A_MAX_RF_PATHS]; 571 u8 noise_power_db_lsb; 572 u8 reserved_2[3]; 573 u8 stream_csi[RTL8723A_MAX_RF_PATHS]; 574 u8 stream_target_csi[RTL8723A_MAX_RF_PATHS]; 575 s8 sig_evm; 576 u8 reserved_3; 577 578 #ifdef __LITTLE_ENDIAN 579 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 580 u8 sgi_en:1; 581 u8 rxsc:2; 582 u8 idle_long:1; 583 u8 r_ant_train_en:1; 584 u8 antenna_select_b:1; 585 u8 antenna_select:1; 586 #else /* _BIG_ENDIAN_ */ 587 u8 antenna_select:1; 588 u8 antenna_select_b:1; 589 u8 r_ant_train_en:1; 590 u8 idle_long:1; 591 u8 rxsc:2; 592 u8 sgi_en:1; 593 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 594 #endif 595 }; 596 597 /* 598 * Regs to backup 599 */ 600 #define RTL8XXXU_ADDA_REGS 16 601 #define RTL8XXXU_MAC_REGS 4 602 #define RTL8XXXU_BB_REGS 9 603 604 struct rtl8xxxu_firmware_header { 605 __le16 signature; /* 92C0: test chip; 92C, 606 88C0: test chip; 607 88C1: MP A-cut; 608 92C1: MP A-cut */ 609 u8 category; /* AP/NIC and USB/PCI */ 610 u8 function; 611 612 __le16 major_version; /* FW Version */ 613 u8 minor_version; /* FW Subversion, default 0x00 */ 614 u8 reserved1; 615 616 u8 month; /* Release time Month field */ 617 u8 date; /* Release time Date field */ 618 u8 hour; /* Release time Hour field */ 619 u8 minute; /* Release time Minute field */ 620 621 __le16 ramcodesize; /* Size of RAM code */ 622 u16 reserved2; 623 624 __le32 svn_idx; /* SVN entry index */ 625 u32 reserved3; 626 627 u32 reserved4; 628 u32 reserved5; 629 630 u8 data[]; 631 }; 632 633 /* 634 * 8723au/8192cu/8188ru required base power index offset tables. 635 */ 636 struct rtl8xxxu_power_base { 637 u32 reg_0e00; 638 u32 reg_0e04; 639 u32 reg_0e08; 640 u32 reg_086c; 641 642 u32 reg_0e10; 643 u32 reg_0e14; 644 u32 reg_0e18; 645 u32 reg_0e1c; 646 647 u32 reg_0830; 648 u32 reg_0834; 649 u32 reg_0838; 650 u32 reg_086c_2; 651 652 u32 reg_083c; 653 u32 reg_0848; 654 u32 reg_084c; 655 u32 reg_0868; 656 }; 657 658 /* 659 * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14 660 */ 661 struct rtl8723au_idx { 662 #ifdef __LITTLE_ENDIAN 663 int a:4; 664 int b:4; 665 #else 666 int b:4; 667 int a:4; 668 #endif 669 } __attribute__((packed)); 670 671 struct rtl8723au_efuse { 672 __le16 rtl_id; 673 u8 res0[0xe]; 674 u8 cck_tx_power_index_A[3]; /* 0x10 */ 675 u8 cck_tx_power_index_B[3]; 676 u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */ 677 u8 ht40_1s_tx_power_index_B[3]; 678 /* 679 * The following entries are half-bytes split as: 680 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 681 */ 682 struct rtl8723au_idx ht20_tx_power_index_diff[3]; 683 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 684 struct rtl8723au_idx ht40_max_power_offset[3]; 685 struct rtl8723au_idx ht20_max_power_offset[3]; 686 u8 channel_plan; /* 0x28 */ 687 u8 tssi_a; 688 u8 thermal_meter; 689 u8 rf_regulatory; 690 u8 rf_option_2; 691 u8 rf_option_3; 692 u8 rf_option_4; 693 u8 res7; 694 u8 version /* 0x30 */; 695 u8 customer_id_major; 696 u8 customer_id_minor; 697 u8 xtal_k; 698 u8 chipset; /* 0x34 */ 699 u8 res8[0x82]; 700 u8 vid; /* 0xb7 */ 701 u8 res9; 702 u8 pid; /* 0xb9 */ 703 u8 res10[0x0c]; 704 u8 mac_addr[ETH_ALEN]; /* 0xc6 */ 705 u8 res11[2]; 706 u8 vendor_name[7]; 707 u8 res12[2]; 708 u8 device_name[0x29]; /* 0xd7 */ 709 }; 710 711 struct rtl8192cu_efuse { 712 __le16 rtl_id; 713 __le16 hpon; 714 u8 res0[2]; 715 __le16 clk; 716 __le16 testr; 717 __le16 vid; 718 __le16 did; 719 __le16 svid; 720 __le16 smid; /* 0x10 */ 721 u8 res1[4]; 722 u8 mac_addr[ETH_ALEN]; /* 0x16 */ 723 u8 res2[2]; 724 u8 vendor_name[7]; 725 u8 res3[3]; 726 u8 device_name[0x14]; /* 0x28 */ 727 u8 res4[0x1e]; /* 0x3c */ 728 u8 cck_tx_power_index_A[3]; /* 0x5a */ 729 u8 cck_tx_power_index_B[3]; 730 u8 ht40_1s_tx_power_index_A[3]; /* 0x60 */ 731 u8 ht40_1s_tx_power_index_B[3]; 732 /* 733 * The following entries are half-bytes split as: 734 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 735 */ 736 struct rtl8723au_idx ht40_2s_tx_power_index_diff[3]; 737 struct rtl8723au_idx ht20_tx_power_index_diff[3]; /* 0x69 */ 738 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 739 struct rtl8723au_idx ht40_max_power_offset[3]; /* 0x6f */ 740 struct rtl8723au_idx ht20_max_power_offset[3]; 741 u8 channel_plan; /* 0x75 */ 742 u8 tssi_a; 743 u8 tssi_b; 744 u8 thermal_meter; /* xtal_k */ /* 0x78 */ 745 u8 rf_regulatory; 746 u8 rf_option_2; 747 u8 rf_option_3; 748 u8 rf_option_4; 749 u8 res5[1]; /* 0x7d */ 750 u8 version; 751 u8 customer_id; 752 }; 753 754 struct rtl8723bu_pwr_idx { 755 #ifdef __LITTLE_ENDIAN 756 int ht20:4; 757 int ht40:4; 758 int ofdm:4; 759 int cck:4; 760 #else 761 int cck:4; 762 int ofdm:4; 763 int ht40:4; 764 int ht20:4; 765 #endif 766 } __attribute__((packed)); 767 768 struct rtl8723bu_efuse_tx_power { 769 u8 cck_base[6]; 770 u8 ht40_base[5]; 771 struct rtl8723au_idx ht20_ofdm_1s_diff; 772 struct rtl8723bu_pwr_idx pwr_diff[3]; 773 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ 774 }; 775 776 struct rtl8723bu_efuse { 777 __le16 rtl_id; 778 u8 res0[0x0e]; 779 struct rtl8723bu_efuse_tx_power tx_power_index_A; /* 0x10 */ 780 struct rtl8723bu_efuse_tx_power tx_power_index_B; /* 0x3a */ 781 struct rtl8723bu_efuse_tx_power tx_power_index_C; /* 0x64 */ 782 struct rtl8723bu_efuse_tx_power tx_power_index_D; /* 0x8e */ 783 u8 channel_plan; /* 0xb8 */ 784 u8 xtal_k; 785 u8 thermal_meter; 786 u8 iqk_lck; 787 u8 pa_type; /* 0xbc */ 788 u8 lna_type_2g; /* 0xbd */ 789 u8 res2[3]; 790 u8 rf_board_option; 791 u8 rf_feature_option; 792 u8 rf_bt_setting; 793 u8 eeprom_version; 794 u8 eeprom_customer_id; 795 u8 res3[2]; 796 u8 tx_pwr_calibrate_rate; 797 u8 rf_antenna_option; /* 0xc9 */ 798 u8 rfe_option; 799 u8 res4[9]; 800 u8 usb_optional_function; 801 u8 res5[0x1e]; 802 u8 res6[2]; 803 u8 serial[0x0b]; /* 0xf5 */ 804 u8 vid; /* 0x100 */ 805 u8 res7; 806 u8 pid; 807 u8 res8[4]; 808 u8 mac_addr[ETH_ALEN]; /* 0x107 */ 809 u8 res9[2]; 810 u8 vendor_name[0x07]; 811 u8 res10[2]; 812 u8 device_name[0x14]; 813 u8 res11[0xcf]; 814 u8 package_type; /* 0x1fb */ 815 u8 res12[0x4]; 816 }; 817 818 struct rtl8192eu_efuse_tx_power { 819 u8 cck_base[6]; 820 u8 ht40_base[5]; 821 struct rtl8723au_idx ht20_ofdm_1s_diff; 822 struct rtl8723bu_pwr_idx pwr_diff[3]; 823 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ 824 }; 825 826 struct rtl8192eu_efuse { 827 __le16 rtl_id; 828 u8 res0[0x0e]; 829 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 830 struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x3a */ 831 u8 res2[0x54]; 832 u8 channel_plan; /* 0xb8 */ 833 u8 xtal_k; 834 u8 thermal_meter; 835 u8 iqk_lck; 836 u8 pa_type; /* 0xbc */ 837 u8 lna_type_2g; /* 0xbd */ 838 u8 res3[1]; 839 u8 lna_type_5g; /* 0xbf */ 840 u8 res4[1]; 841 u8 rf_board_option; 842 u8 rf_feature_option; 843 u8 rf_bt_setting; 844 u8 eeprom_version; 845 u8 eeprom_customer_id; 846 u8 res5[3]; 847 u8 rf_antenna_option; /* 0xc9 */ 848 u8 res6[6]; 849 u8 vid; /* 0xd0 */ 850 u8 res7[1]; 851 u8 pid; /* 0xd2 */ 852 u8 res8[1]; 853 u8 usb_optional_function; 854 u8 res9[2]; 855 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 856 u8 device_info[80]; 857 u8 res11[3]; 858 u8 unknown[0x0d]; /* 0x130 */ 859 u8 res12[0xc3]; 860 }; 861 862 struct rtl8xxxu_reg8val { 863 u16 reg; 864 u8 val; 865 }; 866 867 struct rtl8xxxu_reg32val { 868 u16 reg; 869 u32 val; 870 }; 871 872 struct rtl8xxxu_rfregval { 873 u8 reg; 874 u32 val; 875 }; 876 877 enum rtl8xxxu_rfpath { 878 RF_A = 0, 879 RF_B = 1, 880 }; 881 882 struct rtl8xxxu_rfregs { 883 u16 hssiparm1; 884 u16 hssiparm2; 885 u16 lssiparm; 886 u16 hspiread; 887 u16 lssiread; 888 u16 rf_sw_ctrl; 889 }; 890 891 #define H2C_MAX_MBOX 4 892 #define H2C_EXT BIT(7) 893 #define H2C_JOIN_BSS_DISCONNECT 0 894 #define H2C_JOIN_BSS_CONNECT 1 895 896 /* 897 * H2C (firmware) commands differ between the older generation chips 898 * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu, 899 * 8192[de]u, 8192eu, and 8812. 900 */ 901 enum h2c_cmd_8723a { 902 H2C_SET_POWER_MODE = 1, 903 H2C_JOIN_BSS_REPORT = 2, 904 H2C_SET_RSSI = 5, 905 H2C_SET_RATE_MASK = (6 | H2C_EXT), 906 }; 907 908 enum h2c_cmd_8723b { 909 /* 910 * Common Class: 000 911 */ 912 H2C_8723B_RSVD_PAGE = 0x00, 913 H2C_8723B_MEDIA_STATUS_RPT = 0x01, 914 H2C_8723B_SCAN_ENABLE = 0x02, 915 H2C_8723B_KEEP_ALIVE = 0x03, 916 H2C_8723B_DISCON_DECISION = 0x04, 917 H2C_8723B_PSD_OFFLOAD = 0x05, 918 H2C_8723B_AP_OFFLOAD = 0x08, 919 H2C_8723B_BCN_RSVDPAGE = 0x09, 920 H2C_8723B_PROBERSP_RSVDPAGE = 0x0A, 921 H2C_8723B_FCS_RSVDPAGE = 0x10, 922 H2C_8723B_FCS_INFO = 0x11, 923 H2C_8723B_AP_WOW_GPIO_CTRL = 0x13, 924 925 /* 926 * PoweSave Class: 001 927 */ 928 H2C_8723B_SET_PWR_MODE = 0x20, 929 H2C_8723B_PS_TUNING_PARA = 0x21, 930 H2C_8723B_PS_TUNING_PARA2 = 0x22, 931 H2C_8723B_P2P_LPS_PARAM = 0x23, 932 H2C_8723B_P2P_PS_OFFLOAD = 0x24, 933 H2C_8723B_PS_SCAN_ENABLE = 0x25, 934 H2C_8723B_SAP_PS_ = 0x26, 935 H2C_8723B_INACTIVE_PS_ = 0x27, 936 H2C_8723B_FWLPS_IN_IPS_ = 0x28, 937 938 /* 939 * Dynamic Mechanism Class: 010 940 */ 941 H2C_8723B_MACID_CFG_RAID = 0x40, 942 H2C_8723B_TXBF = 0x41, 943 H2C_8723B_RSSI_SETTING = 0x42, 944 H2C_8723B_AP_REQ_TXRPT = 0x43, 945 H2C_8723B_INIT_RATE_COLLECT = 0x44, 946 947 /* 948 * BT Class: 011 949 */ 950 H2C_8723B_B_TYPE_TDMA = 0x60, 951 H2C_8723B_BT_INFO = 0x61, 952 H2C_8723B_FORCE_BT_TXPWR = 0x62, 953 H2C_8723B_BT_IGNORE_WLANACT = 0x63, 954 H2C_8723B_DAC_SWING_VALUE = 0x64, 955 H2C_8723B_ANT_SEL_RSV = 0x65, 956 H2C_8723B_WL_OPMODE = 0x66, 957 H2C_8723B_BT_MP_OPER = 0x67, 958 H2C_8723B_BT_CONTROL = 0x68, 959 H2C_8723B_BT_WIFI_CTRL = 0x69, 960 H2C_8723B_BT_FW_PATCH = 0x6a, 961 H2C_8723B_BT_WLAN_CALIBRATION = 0x6d, 962 H2C_8723B_BT_GRANT = 0x6e, 963 964 /* 965 * WOWLAN Class: 100 966 */ 967 H2C_8723B_WOWLAN = 0x80, 968 H2C_8723B_REMOTE_WAKE_CTRL = 0x81, 969 H2C_8723B_AOAC_GLOBAL_INFO = 0x82, 970 H2C_8723B_AOAC_RSVD_PAGE = 0x83, 971 H2C_8723B_AOAC_RSVD_PAGE2 = 0x84, 972 H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85, 973 H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86, 974 H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87, 975 976 H2C_8723B_RESET_TSF = 0xC0, 977 }; 978 979 980 struct h2c_cmd { 981 union { 982 struct { 983 u8 cmd; 984 u8 data[7]; 985 } __packed cmd; 986 struct { 987 __le32 data; 988 __le16 ext; 989 } __packed raw; 990 struct { 991 __le32 data; 992 __le32 ext; 993 } __packed raw_wide; 994 struct { 995 u8 cmd; 996 u8 data; 997 } __packed joinbss; 998 struct { 999 u8 cmd; 1000 __le16 mask_hi; 1001 u8 arg; 1002 __le16 mask_lo; 1003 } __packed ramask; 1004 struct { 1005 u8 cmd; 1006 u8 parm; 1007 u8 macid; 1008 u8 macid_end; 1009 } __packed media_status_rpt; 1010 struct { 1011 u8 cmd; 1012 u8 macid; 1013 /* 1014 * [0:4] - RAID 1015 * [7] - SGI 1016 */ 1017 u8 data1; 1018 /* 1019 * [0:1] - Bandwidth 1020 * [3] - No Update 1021 * [4:5] - VHT enable 1022 * [6] - DISPT 1023 * [7] - DISRA 1024 */ 1025 u8 data2; 1026 u8 ramask0; 1027 u8 ramask1; 1028 u8 ramask2; 1029 u8 ramask3; 1030 } __packed b_macid_cfg; 1031 struct { 1032 u8 cmd; 1033 u8 data1; 1034 u8 data2; 1035 u8 data3; 1036 u8 data4; 1037 u8 data5; 1038 } __packed b_type_dma; 1039 struct { 1040 u8 cmd; 1041 u8 data; 1042 } __packed bt_info; 1043 struct { 1044 u8 cmd; 1045 u8 operreq; 1046 u8 opcode; 1047 u8 data; 1048 u8 addr; 1049 } __packed bt_mp_oper; 1050 struct { 1051 u8 cmd; 1052 u8 data; 1053 } __packed bt_wlan_calibration; 1054 struct { 1055 u8 cmd; 1056 u8 data; 1057 } __packed ignore_wlan; 1058 struct { 1059 u8 cmd; 1060 u8 ant_inverse; 1061 u8 int_switch_type; 1062 } __packed ant_sel_rsv; 1063 struct { 1064 u8 cmd; 1065 u8 data; 1066 } __packed bt_grant; 1067 }; 1068 }; 1069 1070 enum c2h_evt_8723b { 1071 C2H_8723B_DEBUG = 0, 1072 C2H_8723B_TSF = 1, 1073 C2H_8723B_AP_RPT_RSP = 2, 1074 C2H_8723B_CCX_TX_RPT = 3, 1075 C2H_8723B_BT_RSSI = 4, 1076 C2H_8723B_BT_OP_MODE = 5, 1077 C2H_8723B_EXT_RA_RPT = 6, 1078 C2H_8723B_BT_INFO = 9, 1079 C2H_8723B_HW_INFO_EXCH = 0x0a, 1080 C2H_8723B_BT_MP_INFO = 0x0b, 1081 C2H_8723B_RA_REPORT = 0x0c, 1082 C2H_8723B_FW_DEBUG = 0xff, 1083 }; 1084 1085 enum bt_info_src_8723b { 1086 BT_INFO_SRC_8723B_WIFI_FW = 0x0, 1087 BT_INFO_SRC_8723B_BT_RSP = 0x1, 1088 BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2, 1089 }; 1090 1091 enum bt_mp_oper_opcode_8723b { 1092 BT_MP_OP_GET_BT_VERSION = 0x00, 1093 BT_MP_OP_RESET = 0x01, 1094 BT_MP_OP_TEST_CTRL = 0x02, 1095 BT_MP_OP_SET_BT_MODE = 0x03, 1096 BT_MP_OP_SET_CHNL_TX_GAIN = 0x04, 1097 BT_MP_OP_SET_PKT_TYPE_LEN = 0x05, 1098 BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06, 1099 BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07, 1100 BT_MP_OP_SET_PKT_HEADER = 0x08, 1101 BT_MP_OP_SET_WHITENCOEFF = 0x09, 1102 BT_MP_OP_SET_BD_ADDR_L = 0x0a, 1103 BT_MP_OP_SET_BD_ADDR_H = 0x0b, 1104 BT_MP_OP_WRITE_REG_ADDR = 0x0c, 1105 BT_MP_OP_WRITE_REG_VALUE = 0x0d, 1106 BT_MP_OP_GET_BT_STATUS = 0x0e, 1107 BT_MP_OP_GET_BD_ADDR_L = 0x0f, 1108 BT_MP_OP_GET_BD_ADDR_H = 0x10, 1109 BT_MP_OP_READ_REG = 0x11, 1110 BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12, 1111 BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13, 1112 BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14, 1113 BT_MP_OP_GET_RX_PKT_CNT_L = 0x15, 1114 BT_MP_OP_GET_RX_PKT_CNT_H = 0x16, 1115 BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17, 1116 BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18, 1117 BT_MP_OP_GET_RSSI = 0x19, 1118 BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a, 1119 BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b, 1120 BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c, 1121 BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d, 1122 BT_MP_OP_GET_AFH_MAP_L = 0x1e, 1123 BT_MP_OP_GET_AFH_MAP_M = 0x1f, 1124 BT_MP_OP_GET_AFH_MAP_H = 0x20, 1125 BT_MP_OP_GET_AFH_STATUS = 0x21, 1126 BT_MP_OP_SET_TRACKING_INTERVAL = 0x22, 1127 BT_MP_OP_SET_THERMAL_METER = 0x23, 1128 BT_MP_OP_ENABLE_CFO_TRACKING = 0x24, 1129 }; 1130 1131 enum rtl8xxxu_bw_mode { 1132 RTL8XXXU_CHANNEL_WIDTH_20 = 0, 1133 RTL8XXXU_CHANNEL_WIDTH_40 = 1, 1134 RTL8XXXU_CHANNEL_WIDTH_80 = 2, 1135 RTL8XXXU_CHANNEL_WIDTH_160 = 3, 1136 RTL8XXXU_CHANNEL_WIDTH_80_80 = 4, 1137 RTL8XXXU_CHANNEL_WIDTH_MAX = 5, 1138 }; 1139 1140 struct rtl8723bu_c2h { 1141 u8 id; 1142 u8 seq; 1143 union { 1144 struct { 1145 u8 payload[0]; 1146 } __packed raw; 1147 struct { 1148 u8 ext_id; 1149 u8 status:4; 1150 u8 retlen:4; 1151 u8 opcode_ver:4; 1152 u8 req_num:4; 1153 u8 payload[2]; 1154 } __packed bt_mp_info; 1155 struct { 1156 u8 response_source:4; 1157 u8 dummy0_0:4; 1158 1159 u8 bt_info; 1160 1161 u8 retry_count:4; 1162 u8 dummy2_0:1; 1163 u8 bt_page:1; 1164 u8 tx_rx_mask:1; 1165 u8 dummy2_2:1; 1166 1167 u8 rssi; 1168 1169 u8 basic_rate:1; 1170 u8 bt_has_reset:1; 1171 u8 dummy4_1:1; 1172 u8 ignore_wlan:1; 1173 u8 auto_report:1; 1174 u8 dummy4_2:3; 1175 1176 u8 a4; 1177 u8 a5; 1178 } __packed bt_info; 1179 struct { 1180 u8 rate:7; 1181 u8 sgi:1; 1182 u8 macid; 1183 u8 ldpc:1; 1184 u8 txbf:1; 1185 u8 noisy_state:1; 1186 u8 dummy2_0:5; 1187 u8 dummy3_0; 1188 u8 dummy4_0; 1189 u8 dummy5_0; 1190 u8 bw; 1191 } __packed ra_report; 1192 }; 1193 }; 1194 1195 struct rtl8xxxu_fileops; 1196 1197 /*mlme related.*/ 1198 enum wireless_mode { 1199 WIRELESS_MODE_UNKNOWN = 0, 1200 /* Sub-Element */ 1201 WIRELESS_MODE_B = BIT(0), 1202 WIRELESS_MODE_G = BIT(1), 1203 WIRELESS_MODE_A = BIT(2), 1204 WIRELESS_MODE_N_24G = BIT(3), 1205 WIRELESS_MODE_N_5G = BIT(4), 1206 WIRELESS_AUTO = BIT(5), 1207 WIRELESS_MODE_AC = BIT(6), 1208 WIRELESS_MODE_MAX = 0x7F, 1209 }; 1210 1211 /* from rtlwifi/wifi.h */ 1212 enum ratr_table_mode_new { 1213 RATEID_IDX_BGN_40M_2SS = 0, 1214 RATEID_IDX_BGN_40M_1SS = 1, 1215 RATEID_IDX_BGN_20M_2SS_BN = 2, 1216 RATEID_IDX_BGN_20M_1SS_BN = 3, 1217 RATEID_IDX_GN_N2SS = 4, 1218 RATEID_IDX_GN_N1SS = 5, 1219 RATEID_IDX_BG = 6, 1220 RATEID_IDX_G = 7, 1221 RATEID_IDX_B = 8, 1222 RATEID_IDX_VHT_2SS = 9, 1223 RATEID_IDX_VHT_1SS = 10, 1224 RATEID_IDX_MIX1 = 11, 1225 RATEID_IDX_MIX2 = 12, 1226 RATEID_IDX_VHT_3SS = 13, 1227 RATEID_IDX_BGN_3SS = 14, 1228 }; 1229 1230 #define BT_INFO_8723B_1ANT_B_FTP BIT(7) 1231 #define BT_INFO_8723B_1ANT_B_A2DP BIT(6) 1232 #define BT_INFO_8723B_1ANT_B_HID BIT(5) 1233 #define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT(4) 1234 #define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT(3) 1235 #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT(2) 1236 #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT(1) 1237 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT(0) 1238 1239 enum _BT_8723B_1ANT_STATUS { 1240 BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE = 0x0, 1241 BT_8723B_1ANT_STATUS_CONNECTED_IDLE = 0x1, 1242 BT_8723B_1ANT_STATUS_INQ_PAGE = 0x2, 1243 BT_8723B_1ANT_STATUS_ACL_BUSY = 0x3, 1244 BT_8723B_1ANT_STATUS_SCO_BUSY = 0x4, 1245 BT_8723B_1ANT_STATUS_ACL_SCO_BUSY = 0x5, 1246 BT_8723B_1ANT_STATUS_MAX 1247 }; 1248 1249 struct rtl8xxxu_btcoex { 1250 u8 bt_status; 1251 bool bt_busy; 1252 bool has_sco; 1253 bool has_a2dp; 1254 bool has_hid; 1255 bool has_pan; 1256 bool hid_only; 1257 bool a2dp_only; 1258 bool c2h_bt_inquiry; 1259 }; 1260 1261 #define RTL8XXXU_RATR_STA_INIT 0 1262 #define RTL8XXXU_RATR_STA_HIGH 1 1263 #define RTL8XXXU_RATR_STA_MID 2 1264 #define RTL8XXXU_RATR_STA_LOW 3 1265 1266 #define RTL8XXXU_NOISE_FLOOR_MIN -100 1267 #define RTL8XXXU_SNR_THRESH_HIGH 50 1268 #define RTL8XXXU_SNR_THRESH_LOW 20 1269 1270 struct rtl8xxxu_ra_report { 1271 struct rate_info txrate; 1272 u32 bit_rate; 1273 u8 desc_rate; 1274 }; 1275 1276 struct rtl8xxxu_priv { 1277 struct ieee80211_hw *hw; 1278 struct usb_device *udev; 1279 struct rtl8xxxu_fileops *fops; 1280 1281 spinlock_t tx_urb_lock; 1282 struct list_head tx_urb_free_list; 1283 int tx_urb_free_count; 1284 bool tx_stopped; 1285 1286 spinlock_t rx_urb_lock; 1287 struct list_head rx_urb_pending_list; 1288 int rx_urb_pending_count; 1289 bool shutdown; 1290 struct work_struct rx_urb_wq; 1291 1292 u8 mac_addr[ETH_ALEN]; 1293 char chip_name[8]; 1294 char chip_vendor[8]; 1295 u8 cck_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1296 u8 cck_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1297 u8 ht40_1s_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1298 u8 ht40_1s_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1299 /* 1300 * The following entries are half-bytes split as: 1301 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 1302 */ 1303 struct rtl8723au_idx ht40_2s_tx_power_index_diff[ 1304 RTL8723A_CHANNEL_GROUPS]; 1305 struct rtl8723au_idx ht20_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1306 struct rtl8723au_idx ofdm_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1307 struct rtl8723au_idx ht40_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1308 struct rtl8723au_idx ht20_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1309 /* 1310 * Newer generation chips only keep power diffs per TX count, 1311 * not per channel group. 1312 */ 1313 struct rtl8723au_idx ofdm_tx_power_diff[RTL8723B_TX_COUNT]; 1314 struct rtl8723au_idx ht20_tx_power_diff[RTL8723B_TX_COUNT]; 1315 struct rtl8723au_idx ht40_tx_power_diff[RTL8723B_TX_COUNT]; 1316 struct rtl8xxxu_power_base *power_base; 1317 u32 chip_cut:4; 1318 u32 rom_rev:4; 1319 u32 is_multi_func:1; 1320 u32 has_wifi:1; 1321 u32 has_bluetooth:1; 1322 u32 enable_bluetooth:1; 1323 u32 has_gps:1; 1324 u32 hi_pa:1; 1325 u32 vendor_umc:1; 1326 u32 vendor_smic:1; 1327 u32 has_polarity_ctrl:1; 1328 u32 has_eeprom:1; 1329 u32 boot_eeprom:1; 1330 u32 usb_interrupts:1; 1331 u32 ep_tx_high_queue:1; 1332 u32 ep_tx_normal_queue:1; 1333 u32 ep_tx_low_queue:1; 1334 u32 has_xtalk:1; 1335 u32 rx_buf_aggregation:1; 1336 u8 xtalk; 1337 unsigned int pipe_interrupt; 1338 unsigned int pipe_in; 1339 unsigned int pipe_out[TXDESC_QUEUE_MAX]; 1340 u8 out_ep[RTL8XXXU_OUT_ENDPOINTS]; 1341 u8 ep_tx_count; 1342 u8 rf_paths; 1343 u8 rx_paths; 1344 u8 tx_paths; 1345 u32 rege94; 1346 u32 rege9c; 1347 u32 regeb4; 1348 u32 regebc; 1349 int next_mbox; 1350 int nr_out_eps; 1351 1352 struct mutex h2c_mutex; 1353 1354 struct usb_anchor rx_anchor; 1355 struct usb_anchor tx_anchor; 1356 struct usb_anchor int_anchor; 1357 struct rtl8xxxu_firmware_header *fw_data; 1358 size_t fw_size; 1359 struct mutex usb_buf_mutex; 1360 union { 1361 __le32 val32; 1362 __le16 val16; 1363 u8 val8; 1364 } usb_buf; 1365 union { 1366 u8 raw[EFUSE_MAP_LEN]; 1367 struct rtl8723au_efuse efuse8723; 1368 struct rtl8723bu_efuse efuse8723bu; 1369 struct rtl8192cu_efuse efuse8192; 1370 struct rtl8192eu_efuse efuse8192eu; 1371 } efuse_wifi; 1372 u32 adda_backup[RTL8XXXU_ADDA_REGS]; 1373 u32 mac_backup[RTL8XXXU_MAC_REGS]; 1374 u32 bb_backup[RTL8XXXU_BB_REGS]; 1375 u32 bb_recovery_backup[RTL8XXXU_BB_REGS]; 1376 enum rtl8xxxu_rtl_chip rtl_chip; 1377 u8 pi_enabled:1; 1378 u8 no_pape:1; 1379 u8 int_buf[USB_INTR_CONTENT_LENGTH]; 1380 u8 rssi_level; 1381 /* 1382 * Only one virtual interface permitted because only STA mode 1383 * is supported and no iface_combinations are provided. 1384 */ 1385 struct ieee80211_vif *vif; 1386 struct delayed_work ra_watchdog; 1387 struct work_struct c2hcmd_work; 1388 struct sk_buff_head c2hcmd_queue; 1389 struct rtl8xxxu_btcoex bt_coex; 1390 struct rtl8xxxu_ra_report ra_report; 1391 }; 1392 1393 struct rtl8xxxu_rx_urb { 1394 struct urb urb; 1395 struct ieee80211_hw *hw; 1396 struct list_head list; 1397 }; 1398 1399 struct rtl8xxxu_tx_urb { 1400 struct urb urb; 1401 struct ieee80211_hw *hw; 1402 struct list_head list; 1403 }; 1404 1405 struct rtl8xxxu_fileops { 1406 int (*parse_efuse) (struct rtl8xxxu_priv *priv); 1407 int (*load_firmware) (struct rtl8xxxu_priv *priv); 1408 int (*power_on) (struct rtl8xxxu_priv *priv); 1409 void (*power_off) (struct rtl8xxxu_priv *priv); 1410 void (*reset_8051) (struct rtl8xxxu_priv *priv); 1411 int (*llt_init) (struct rtl8xxxu_priv *priv); 1412 void (*init_phy_bb) (struct rtl8xxxu_priv *priv); 1413 int (*init_phy_rf) (struct rtl8xxxu_priv *priv); 1414 void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv); 1415 void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv); 1416 void (*config_channel) (struct ieee80211_hw *hw); 1417 int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb); 1418 void (*init_aggregation) (struct rtl8xxxu_priv *priv); 1419 void (*init_statistics) (struct rtl8xxxu_priv *priv); 1420 void (*enable_rf) (struct rtl8xxxu_priv *priv); 1421 void (*disable_rf) (struct rtl8xxxu_priv *priv); 1422 void (*usb_quirks) (struct rtl8xxxu_priv *priv); 1423 void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel, 1424 bool ht40); 1425 void (*update_rate_mask) (struct rtl8xxxu_priv *priv, 1426 u32 ramask, u8 rateid, int sgi); 1427 void (*report_connect) (struct rtl8xxxu_priv *priv, 1428 u8 macid, bool connect); 1429 void (*fill_txdesc) (struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 1430 struct ieee80211_tx_info *tx_info, 1431 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 1432 bool short_preamble, bool ampdu_enable, 1433 u32 rts_rate); 1434 int writeN_block_size; 1435 int rx_agg_buf_size; 1436 char tx_desc_size; 1437 char rx_desc_size; 1438 u8 has_s0s1:1; 1439 u8 has_tx_report:1; 1440 u8 gen2_thermal_meter:1; 1441 u8 needs_full_init:1; 1442 u32 adda_1t_init; 1443 u32 adda_1t_path_on; 1444 u32 adda_2t_path_on_a; 1445 u32 adda_2t_path_on_b; 1446 u16 trxff_boundary; 1447 u8 pbp_rx; 1448 u8 pbp_tx; 1449 struct rtl8xxxu_reg8val *mactable; 1450 u8 total_page_num; 1451 u8 page_num_hi; 1452 u8 page_num_lo; 1453 u8 page_num_norm; 1454 }; 1455 1456 extern int rtl8xxxu_debug; 1457 1458 extern struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[]; 1459 extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[]; 1460 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr); 1461 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr); 1462 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr); 1463 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val); 1464 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val); 1465 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val); 1466 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, 1467 enum rtl8xxxu_rfpath path, u8 reg); 1468 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, 1469 enum rtl8xxxu_rfpath path, u8 reg, u32 data); 1470 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 1471 u32 *backup, int count); 1472 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 1473 u32 *backup, int count); 1474 void rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, 1475 const u32 *reg, u32 *backup); 1476 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, 1477 const u32 *reg, u32 *backup); 1478 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, 1479 bool path_a_on); 1480 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, 1481 const u32 *regs, u32 *backup); 1482 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, 1483 int result[][8], int candidate, bool tx_only); 1484 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, 1485 int result[][8], int candidate, bool tx_only); 1486 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, 1487 struct rtl8xxxu_rfregval *table, 1488 enum rtl8xxxu_rfpath path); 1489 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, 1490 struct rtl8xxxu_reg32val *array); 1491 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name); 1492 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv); 1493 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv); 1494 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv); 1495 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv); 1496 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start); 1497 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv); 1498 int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, 1499 struct h2c_cmd *h2c, int len); 1500 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv); 1501 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv); 1502 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv); 1503 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv); 1504 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv); 1505 void rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, 1506 int channel, bool ht40); 1507 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw); 1508 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw); 1509 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv); 1510 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv); 1511 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, 1512 u32 ramask, u8 rateid, int sgi); 1513 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, 1514 u32 ramask, u8 rateid, int sgi); 1515 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, 1516 u8 macid, bool connect); 1517 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, 1518 u8 macid, bool connect); 1519 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv); 1520 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv); 1521 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv); 1522 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv); 1523 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 1524 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 1525 int rtl8xxxu_gen2_channel_to_group(int channel); 1526 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, 1527 int result[][8], int c1, int c2); 1528 void rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 1529 struct ieee80211_tx_info *tx_info, 1530 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 1531 bool short_preamble, bool ampdu_enable, 1532 u32 rts_rate); 1533 void rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 1534 struct ieee80211_tx_info *tx_info, 1535 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 1536 bool short_preamble, bool ampdu_enable, 1537 u32 rts_rate); 1538 void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, 1539 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5); 1540 1541 extern struct rtl8xxxu_fileops rtl8192cu_fops; 1542 extern struct rtl8xxxu_fileops rtl8192eu_fops; 1543 extern struct rtl8xxxu_fileops rtl8723au_fops; 1544 extern struct rtl8xxxu_fileops rtl8723bu_fops; 1545