1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 4 * 5 * Register definitions taken from original Realtek rtl8723au driver 6 */ 7 8 #include <asm/byteorder.h> 9 10 #define RTL8XXXU_DEBUG_REG_WRITE 0x01 11 #define RTL8XXXU_DEBUG_REG_READ 0x02 12 #define RTL8XXXU_DEBUG_RFREG_WRITE 0x04 13 #define RTL8XXXU_DEBUG_RFREG_READ 0x08 14 #define RTL8XXXU_DEBUG_CHANNEL 0x10 15 #define RTL8XXXU_DEBUG_TX 0x20 16 #define RTL8XXXU_DEBUG_TX_DUMP 0x40 17 #define RTL8XXXU_DEBUG_RX 0x80 18 #define RTL8XXXU_DEBUG_RX_DUMP 0x100 19 #define RTL8XXXU_DEBUG_USB 0x200 20 #define RTL8XXXU_DEBUG_KEY 0x400 21 #define RTL8XXXU_DEBUG_H2C 0x800 22 #define RTL8XXXU_DEBUG_ACTION 0x1000 23 #define RTL8XXXU_DEBUG_EFUSE 0x2000 24 #define RTL8XXXU_DEBUG_INTERRUPT 0x4000 25 26 #define RTW_USB_CONTROL_MSG_TIMEOUT 500 27 #define RTL8XXXU_MAX_REG_POLL 500 28 #define USB_INTR_CONTENT_LENGTH 56 29 30 #define RTL8XXXU_OUT_ENDPOINTS 6 31 32 #define REALTEK_USB_READ 0xc0 33 #define REALTEK_USB_WRITE 0x40 34 #define REALTEK_USB_CMD_REQ 0x05 35 #define REALTEK_USB_CMD_IDX 0x00 36 37 #define TX_TOTAL_PAGE_NUM 0xf8 38 #define TX_TOTAL_PAGE_NUM_8188F 0xf7 39 #define TX_TOTAL_PAGE_NUM_8188E 0xa9 40 #define TX_TOTAL_PAGE_NUM_8192E 0xf3 41 #define TX_TOTAL_PAGE_NUM_8723B 0xf7 42 /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */ 43 #define TX_PAGE_NUM_PUBQ 0xe7 44 #define TX_PAGE_NUM_HI_PQ 0x0c 45 #define TX_PAGE_NUM_LO_PQ 0x02 46 #define TX_PAGE_NUM_NORM_PQ 0x02 47 48 #define TX_PAGE_NUM_PUBQ_8188F 0xe5 49 #define TX_PAGE_NUM_HI_PQ_8188F 0x0c 50 #define TX_PAGE_NUM_LO_PQ_8188F 0x02 51 #define TX_PAGE_NUM_NORM_PQ_8188F 0x02 52 53 #define TX_PAGE_NUM_PUBQ_8188E 0x47 54 #define TX_PAGE_NUM_HI_PQ_8188E 0x29 55 #define TX_PAGE_NUM_LO_PQ_8188E 0x1c 56 #define TX_PAGE_NUM_NORM_PQ_8188E 0x1c 57 58 #define TX_PAGE_NUM_PUBQ_8192E 0xe7 59 #define TX_PAGE_NUM_HI_PQ_8192E 0x08 60 #define TX_PAGE_NUM_LO_PQ_8192E 0x0c 61 #define TX_PAGE_NUM_NORM_PQ_8192E 0x00 62 63 #define TX_PAGE_NUM_PUBQ_8723B 0xe7 64 #define TX_PAGE_NUM_HI_PQ_8723B 0x0c 65 #define TX_PAGE_NUM_LO_PQ_8723B 0x02 66 #define TX_PAGE_NUM_NORM_PQ_8723B 0x02 67 68 #define RTL_FW_PAGE_SIZE 4096 69 #define RTL8XXXU_FIRMWARE_POLL_MAX 1000 70 71 #define RTL8723A_CHANNEL_GROUPS 3 72 #define RTL8723A_MAX_RF_PATHS 2 73 #define RTL8723B_CHANNEL_GROUPS 6 74 #define RTL8723B_TX_COUNT 4 75 #define RTL8723B_MAX_RF_PATHS 4 76 #define RTL8XXXU_MAX_CHANNEL_GROUPS 6 77 #define RF6052_MAX_TX_PWR 0x3f 78 79 #define EFUSE_MAP_LEN 512 80 #define EFUSE_MAX_SECTION_8723A 64 81 #define EFUSE_REAL_CONTENT_LEN_8723A 512 82 #define EFUSE_BT_MAP_LEN_8723A 1024 83 #define EFUSE_MAX_WORD_UNIT 4 84 85 enum rtl8xxxu_rtl_chip { 86 RTL8192S = 0x81920, 87 RTL8191S = 0x81910, 88 RTL8192C = 0x8192c, 89 RTL8191C = 0x8191c, 90 RTL8188C = 0x8188c, 91 RTL8188R = 0x81889, 92 RTL8192D = 0x8192d, 93 RTL8723A = 0x8723a, 94 RTL8188E = 0x8188e, 95 RTL8812 = 0x88120, 96 RTL8821 = 0x88210, 97 RTL8192E = 0x8192e, 98 RTL8191E = 0x8191e, 99 RTL8723B = 0x8723b, 100 RTL8814A = 0x8814a, 101 RTL8881A = 0x8881a, 102 RTL8821B = 0x8821b, 103 RTL8822B = 0x8822b, 104 RTL8703B = 0x8703b, 105 RTL8195A = 0x8195a, 106 RTL8188F = 0x8188f, 107 RTL8710B = 0x8710b, 108 }; 109 110 enum rtl8xxxu_rx_type { 111 RX_TYPE_DATA_PKT = 0, 112 RX_TYPE_C2H = 1, 113 RX_TYPE_ERROR = -1 114 }; 115 116 struct rtl8xxxu_rxdesc16 { 117 #ifdef __LITTLE_ENDIAN 118 u32 pktlen:14; 119 u32 crc32:1; 120 u32 icverr:1; 121 u32 drvinfo_sz:4; 122 u32 security:3; 123 u32 qos:1; 124 u32 shift:2; 125 u32 phy_stats:1; 126 u32 swdec:1; 127 u32 ls:1; 128 u32 fs:1; 129 u32 eor:1; 130 u32 own:1; 131 132 u32 macid:5; 133 u32 tid:4; 134 u32 hwrsvd:4; 135 u32 amsdu:1; 136 u32 paggr:1; 137 u32 faggr:1; 138 u32 a1fit:4; 139 u32 a2fit:4; 140 u32 pam:1; 141 u32 pwr:1; 142 u32 md:1; 143 u32 mf:1; 144 u32 type:2; 145 u32 mc:1; 146 u32 bc:1; 147 148 u32 seq:12; 149 u32 frag:4; 150 u32 pkt_cnt:8; 151 u32 reserved:6; 152 u32 nextind:1; 153 u32 reserved0:1; 154 155 u32 rxmcs:6; 156 u32 rxht:1; 157 u32 gf:1; 158 u32 splcp:1; 159 u32 bw:1; 160 u32 htc:1; 161 u32 eosp:1; 162 u32 bssidfit:2; 163 u32 rpt_sel:2; /* 8188e */ 164 u32 reserved1:14; 165 u32 unicastwake:1; 166 u32 magicwake:1; 167 168 u32 pattern0match:1; 169 u32 pattern1match:1; 170 u32 pattern2match:1; 171 u32 pattern3match:1; 172 u32 pattern4match:1; 173 u32 pattern5match:1; 174 u32 pattern6match:1; 175 u32 pattern7match:1; 176 u32 pattern8match:1; 177 u32 pattern9match:1; 178 u32 patternamatch:1; 179 u32 patternbmatch:1; 180 u32 patterncmatch:1; 181 u32 reserved2:19; 182 #else 183 u32 own:1; 184 u32 eor:1; 185 u32 fs:1; 186 u32 ls:1; 187 u32 swdec:1; 188 u32 phy_stats:1; 189 u32 shift:2; 190 u32 qos:1; 191 u32 security:3; 192 u32 drvinfo_sz:4; 193 u32 icverr:1; 194 u32 crc32:1; 195 u32 pktlen:14; 196 197 u32 bc:1; 198 u32 mc:1; 199 u32 type:2; 200 u32 mf:1; 201 u32 md:1; 202 u32 pwr:1; 203 u32 pam:1; 204 u32 a2fit:4; 205 u32 a1fit:4; 206 u32 faggr:1; 207 u32 paggr:1; 208 u32 amsdu:1; 209 u32 hwrsvd:4; 210 u32 tid:4; 211 u32 macid:5; 212 213 u32 reserved0:1; 214 u32 nextind:1; 215 u32 reserved:6; 216 u32 pkt_cnt:8; 217 u32 frag:4; 218 u32 seq:12; 219 220 u32 magicwake:1; 221 u32 unicastwake:1; 222 u32 reserved1:14; 223 u32 rpt_sel:2; /* 8188e */ 224 u32 bssidfit:2; 225 u32 eosp:1; 226 u32 htc:1; 227 u32 bw:1; 228 u32 splcp:1; 229 u32 gf:1; 230 u32 rxht:1; 231 u32 rxmcs:6; 232 233 u32 reserved2:19; 234 u32 patterncmatch:1; 235 u32 patternbmatch:1; 236 u32 patternamatch:1; 237 u32 pattern9match:1; 238 u32 pattern8match:1; 239 u32 pattern7match:1; 240 u32 pattern6match:1; 241 u32 pattern5match:1; 242 u32 pattern4match:1; 243 u32 pattern3match:1; 244 u32 pattern2match:1; 245 u32 pattern1match:1; 246 u32 pattern0match:1; 247 #endif 248 u32 tsfl; 249 #if 0 250 u32 bassn:12; 251 u32 bavld:1; 252 u32 reserved3:19; 253 #endif 254 }; 255 256 struct rtl8xxxu_rxdesc24 { 257 #ifdef __LITTLE_ENDIAN 258 u32 pktlen:14; 259 u32 crc32:1; 260 u32 icverr:1; 261 u32 drvinfo_sz:4; 262 u32 security:3; 263 u32 qos:1; 264 u32 shift:2; 265 u32 phy_stats:1; 266 u32 swdec:1; 267 u32 ls:1; 268 u32 fs:1; 269 u32 eor:1; 270 u32 own:1; 271 272 u32 macid:7; 273 u32 dummy1_0:1; 274 u32 tid:4; 275 u32 dummy1_1:1; 276 u32 amsdu:1; 277 u32 rxid_match:1; 278 u32 paggr:1; 279 u32 a1fit:4; /* 16 */ 280 u32 chkerr:1; 281 u32 ipver:1; 282 u32 tcpudp:1; 283 u32 chkvld:1; 284 u32 pam:1; 285 u32 pwr:1; 286 u32 more_data:1; 287 u32 more_frag:1; 288 u32 type:2; 289 u32 mc:1; 290 u32 bc:1; 291 292 u32 seq:12; 293 u32 frag:4; 294 u32 rx_is_qos:1; /* 16 */ 295 u32 dummy2_0:1; 296 u32 wlanhd_iv_len:6; 297 u32 dummy2_1:4; 298 u32 rpt_sel:1; 299 u32 dummy2_2:3; 300 301 u32 rxmcs:7; 302 u32 dummy3_0:3; 303 u32 htc:1; 304 u32 eosp:1; 305 u32 bssidfit:2; 306 u32 dummy3_1:2; 307 u32 usb_agg_pktnum:8; /* 16 */ 308 u32 dummy3_2:5; 309 u32 pattern_match:1; 310 u32 unicast_match:1; 311 u32 magic_match:1; 312 313 u32 splcp:1; 314 u32 ldcp:1; 315 u32 stbc:1; 316 u32 dummy4_0:1; 317 u32 bw:2; 318 u32 dummy4_1:26; 319 #else 320 u32 own:1; 321 u32 eor:1; 322 u32 fs:1; 323 u32 ls:1; 324 u32 swdec:1; 325 u32 phy_stats:1; 326 u32 shift:2; 327 u32 qos:1; 328 u32 security:3; 329 u32 drvinfo_sz:4; 330 u32 icverr:1; 331 u32 crc32:1; 332 u32 pktlen:14; 333 334 u32 bc:1; 335 u32 mc:1; 336 u32 type:2; 337 u32 mf:1; 338 u32 md:1; 339 u32 pwr:1; 340 u32 pam:1; 341 u32 a2fit:4; 342 u32 a1fit:4; 343 u32 faggr:1; 344 u32 paggr:1; 345 u32 amsdu:1; 346 u32 hwrsvd:4; 347 u32 tid:4; 348 u32 macid:5; 349 350 u32 dummy2_2:3; 351 u32 rpt_sel:1; 352 u32 dummy2_1:4; 353 u32 wlanhd_iv_len:6; 354 u32 dummy2_0:1; 355 u32 rx_is_qos:1; 356 u32 frag:4; /* 16 */ 357 u32 seq:12; 358 359 u32 magic_match:1; 360 u32 unicast_match:1; 361 u32 pattern_match:1; 362 u32 dummy3_2:5; 363 u32 usb_agg_pktnum:8; 364 u32 dummy3_1:2; /* 16 */ 365 u32 bssidfit:2; 366 u32 eosp:1; 367 u32 htc:1; 368 u32 dummy3_0:3; 369 u32 rxmcs:7; 370 371 u32 dumm4_1:26; 372 u32 bw:2; 373 u32 dummy4_0:1; 374 u32 stbc:1; 375 u32 ldcp:1; 376 u32 splcp:1; 377 #endif 378 u32 tsfl; 379 }; 380 381 struct rtl8xxxu_txdesc32 { 382 __le16 pkt_size; 383 u8 pkt_offset; 384 u8 txdw0; 385 __le32 txdw1; 386 __le32 txdw2; 387 __le32 txdw3; 388 __le32 txdw4; 389 __le32 txdw5; 390 __le32 txdw6; 391 __le16 csum; 392 __le16 txdw7; 393 }; 394 395 struct rtl8xxxu_txdesc40 { 396 __le16 pkt_size; 397 u8 pkt_offset; 398 u8 txdw0; 399 __le32 txdw1; 400 __le32 txdw2; 401 __le32 txdw3; 402 __le32 txdw4; 403 __le32 txdw5; 404 __le32 txdw6; 405 __le16 csum; 406 __le16 txdw7; 407 __le32 txdw8; 408 __le32 txdw9; 409 }; 410 411 /* CCK Rates, TxHT = 0 */ 412 #define DESC_RATE_1M 0x00 413 #define DESC_RATE_2M 0x01 414 #define DESC_RATE_5_5M 0x02 415 #define DESC_RATE_11M 0x03 416 417 /* OFDM Rates, TxHT = 0 */ 418 #define DESC_RATE_6M 0x04 419 #define DESC_RATE_9M 0x05 420 #define DESC_RATE_12M 0x06 421 #define DESC_RATE_18M 0x07 422 #define DESC_RATE_24M 0x08 423 #define DESC_RATE_36M 0x09 424 #define DESC_RATE_48M 0x0a 425 #define DESC_RATE_54M 0x0b 426 427 /* MCS Rates, TxHT = 1 */ 428 #define DESC_RATE_MCS0 0x0c 429 #define DESC_RATE_MCS1 0x0d 430 #define DESC_RATE_MCS2 0x0e 431 #define DESC_RATE_MCS3 0x0f 432 #define DESC_RATE_MCS4 0x10 433 #define DESC_RATE_MCS5 0x11 434 #define DESC_RATE_MCS6 0x12 435 #define DESC_RATE_MCS7 0x13 436 #define DESC_RATE_MCS8 0x14 437 #define DESC_RATE_MCS9 0x15 438 #define DESC_RATE_MCS10 0x16 439 #define DESC_RATE_MCS11 0x17 440 #define DESC_RATE_MCS12 0x18 441 #define DESC_RATE_MCS13 0x19 442 #define DESC_RATE_MCS14 0x1a 443 #define DESC_RATE_MCS15 0x1b 444 #define DESC_RATE_MCS15_SG 0x1c 445 #define DESC_RATE_MCS32 0x20 446 447 #define TXDESC_OFFSET_SZ 0 448 #define TXDESC_OFFSET_SHT 16 449 #if 0 450 #define TXDESC_BMC BIT(24) 451 #define TXDESC_LSG BIT(26) 452 #define TXDESC_FSG BIT(27) 453 #define TXDESC_OWN BIT(31) 454 #else 455 #define TXDESC_BROADMULTICAST BIT(0) 456 #define TXDESC_HTC BIT(1) 457 #define TXDESC_LAST_SEGMENT BIT(2) 458 #define TXDESC_FIRST_SEGMENT BIT(3) 459 #define TXDESC_LINIP BIT(4) 460 #define TXDESC_NO_ACM BIT(5) 461 #define TXDESC_GF BIT(6) 462 #define TXDESC_OWN BIT(7) 463 #endif 464 465 /* Word 1 */ 466 /* 467 * Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are 468 * aggregation enable and break respectively. For 8723bu, bits 0-7 are macid. 469 */ 470 #define TXDESC_PKT_OFFSET_SZ 0 471 #define TXDESC32_AGG_ENABLE BIT(5) 472 #define TXDESC32_AGG_BREAK BIT(6) 473 #define TXDESC40_MACID_SHIFT 0 474 #define TXDESC40_MACID_MASK 0x00f0 475 #define TXDESC_QUEUE_SHIFT 8 476 #define TXDESC_QUEUE_MASK 0x1f00 477 #define TXDESC_QUEUE_BK 0x2 478 #define TXDESC_QUEUE_BE 0x0 479 #define TXDESC_QUEUE_VI 0x5 480 #define TXDESC_QUEUE_VO 0x7 481 #define TXDESC_QUEUE_BEACON 0x10 482 #define TXDESC_QUEUE_HIGH 0x11 483 #define TXDESC_QUEUE_MGNT 0x12 484 #define TXDESC_QUEUE_CMD 0x13 485 #define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1) 486 #define TXDESC40_RDG_NAV_EXT BIT(13) 487 #define TXDESC40_LSIG_TXOP_ENABLE BIT(14) 488 #define TXDESC40_PIFS BIT(15) 489 490 #define DESC_RATE_ID_SHIFT 16 491 #define DESC_RATE_ID_MASK 0xf 492 #define TXDESC_NAVUSEHDR BIT(20) 493 #define TXDESC_SEC_RC4 0x00400000 494 #define TXDESC_SEC_AES 0x00c00000 495 #define TXDESC_PKT_OFFSET_SHIFT 26 496 #define TXDESC_AGG_EN BIT(29) 497 #define TXDESC_HWPC BIT(31) 498 499 /* Word 2 */ 500 #define TXDESC40_PAID_SHIFT 0 501 #define TXDESC40_PAID_MASK 0x1ff 502 #define TXDESC40_CCA_RTS_SHIFT 10 503 #define TXDESC40_CCA_RTS_MASK 0xc00 504 #define TXDESC40_AGG_ENABLE BIT(12) 505 #define TXDESC40_RDG_ENABLE BIT(13) 506 #define TXDESC40_AGG_BREAK BIT(16) 507 #define TXDESC40_MORE_FRAG BIT(17) 508 #define TXDESC40_RAW BIT(18) 509 #define TXDESC32_ACK_REPORT BIT(19) 510 #define TXDESC40_SPE_RPT BIT(19) 511 #define TXDESC_AMPDU_DENSITY_SHIFT 20 512 #define TXDESC40_BT_INT BIT(23) 513 #define TXDESC40_GID_SHIFT 24 514 #define TXDESC_ANTENNA_SELECT_A BIT(24) 515 #define TXDESC_ANTENNA_SELECT_B BIT(25) 516 517 /* Word 3 */ 518 #define TXDESC40_USE_DRIVER_RATE BIT(8) 519 #define TXDESC40_CTS_SELF_ENABLE BIT(11) 520 #define TXDESC40_RTS_CTS_ENABLE BIT(12) 521 #define TXDESC40_HW_RTS_ENABLE BIT(13) 522 #define TXDESC32_SEQ_SHIFT 16 523 #define TXDESC32_SEQ_MASK 0x0fff0000 524 525 /* Word 4 */ 526 #define TXDESC32_RTS_RATE_SHIFT 0 527 #define TXDESC32_RTS_RATE_MASK 0x3f 528 #define TXDESC32_QOS BIT(6) 529 #define TXDESC32_HW_SEQ_ENABLE BIT(7) 530 #define TXDESC32_USE_DRIVER_RATE BIT(8) 531 #define TXDESC_DISABLE_DATA_FB BIT(10) 532 #define TXDESC32_CTS_SELF_ENABLE BIT(11) 533 #define TXDESC32_RTS_CTS_ENABLE BIT(12) 534 #define TXDESC32_HW_RTS_ENABLE BIT(13) 535 #define TXDESC32_PT_STAGE_MASK GENMASK(17, 15) 536 #define TXDESC_PRIME_CH_OFF_LOWER BIT(20) 537 #define TXDESC_PRIME_CH_OFF_UPPER BIT(21) 538 #define TXDESC32_SHORT_PREAMBLE BIT(24) 539 #define TXDESC_DATA_BW BIT(25) 540 #define TXDESC_RTS_DATA_BW BIT(27) 541 #define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28) 542 #define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29) 543 #define TXDESC40_DATA_RATE_FB_SHIFT 8 544 #define TXDESC40_DATA_RATE_FB_MASK 0x00001f00 545 #define TXDESC40_RETRY_LIMIT_ENABLE BIT(17) 546 #define TXDESC40_RETRY_LIMIT_SHIFT 18 547 #define TXDESC40_RETRY_LIMIT_MASK 0x00fc0000 548 #define TXDESC40_RTS_RATE_SHIFT 24 549 #define TXDESC40_RTS_RATE_MASK 0x3f000000 550 551 /* Word 5 */ 552 #define TXDESC40_SHORT_PREAMBLE BIT(4) 553 #define TXDESC32_SHORT_GI BIT(6) 554 #define TXDESC_CCX_TAG BIT(7) 555 #define TXDESC32_RETRY_LIMIT_ENABLE BIT(17) 556 #define TXDESC32_RETRY_LIMIT_SHIFT 18 557 #define TXDESC32_RETRY_LIMIT_MASK 0x00fc0000 558 559 /* Word 6 */ 560 #define TXDESC_MAX_AGG_SHIFT 11 561 #define TXDESC_USB_TX_AGG_SHIT 24 562 563 /* Word 7 */ 564 #define TXDESC_ANTENNA_SELECT_C BIT(29) 565 566 /* Word 8 */ 567 #define TXDESC40_HW_SEQ_ENABLE BIT(15) 568 569 /* Word 9 */ 570 #define TXDESC40_SEQ_SHIFT 12 571 #define TXDESC40_SEQ_MASK 0x00fff000 572 573 struct phy_rx_agc_info { 574 #ifdef __LITTLE_ENDIAN 575 u8 gain:7, trsw:1; 576 #else 577 u8 trsw:1, gain:7; 578 #endif 579 }; 580 581 #define CCK_AGC_RPT_LNA_IDX_MASK GENMASK(7, 5) 582 #define CCK_AGC_RPT_VGA_IDX_MASK GENMASK(4, 0) 583 584 struct rtl8723au_phy_stats { 585 struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS]; 586 u8 ch_corr[RTL8723A_MAX_RF_PATHS]; 587 u8 cck_sig_qual_ofdm_pwdb_all; 588 u8 cck_agc_rpt_ofdm_cfosho_a; 589 u8 cck_rpt_b_ofdm_cfosho_b; 590 u8 reserved_1; 591 u8 noise_power_db_msb; 592 s8 path_cfotail[RTL8723A_MAX_RF_PATHS]; 593 u8 pcts_mask[RTL8723A_MAX_RF_PATHS]; 594 s8 stream_rxevm[RTL8723A_MAX_RF_PATHS]; 595 u8 path_rxsnr[RTL8723A_MAX_RF_PATHS]; 596 u8 noise_power_db_lsb; 597 u8 reserved_2[3]; 598 u8 stream_csi[RTL8723A_MAX_RF_PATHS]; 599 u8 stream_target_csi[RTL8723A_MAX_RF_PATHS]; 600 s8 sig_evm; 601 u8 reserved_3; 602 603 #ifdef __LITTLE_ENDIAN 604 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 605 u8 sgi_en:1; 606 u8 rxsc:2; 607 u8 idle_long:1; 608 u8 r_ant_train_en:1; 609 u8 antenna_select_b:1; 610 u8 antenna_select:1; 611 #else /* _BIG_ENDIAN_ */ 612 u8 antenna_select:1; 613 u8 antenna_select_b:1; 614 u8 r_ant_train_en:1; 615 u8 idle_long:1; 616 u8 rxsc:2; 617 u8 sgi_en:1; 618 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 619 #endif 620 }; 621 622 struct jaguar2_phy_stats_type0 { 623 /* DW0 */ 624 u8 page_num; 625 u8 pwdb; 626 #ifdef __LITTLE_ENDIAN 627 u8 gain: 6; 628 u8 rsvd_0: 1; 629 u8 trsw: 1; 630 #else 631 u8 trsw: 1; 632 u8 rsvd_0: 1; 633 u8 gain: 6; 634 #endif 635 u8 rsvd_1; 636 637 /* DW1 */ 638 u8 rsvd_2; 639 #ifdef __LITTLE_ENDIAN 640 u8 rxsc: 4; 641 u8 agc_table: 4; 642 #else 643 u8 agc_table: 4; 644 u8 rxsc: 4; 645 #endif 646 u8 channel; 647 u8 band; 648 649 /* DW2 */ 650 u16 length; 651 #ifdef __LITTLE_ENDIAN 652 u8 antidx_a: 3; 653 u8 antidx_b: 3; 654 u8 rsvd_3: 2; 655 u8 antidx_c: 3; 656 u8 antidx_d: 3; 657 u8 rsvd_4:2; 658 #else 659 u8 rsvd_3: 2; 660 u8 antidx_b: 3; 661 u8 antidx_a: 3; 662 u8 rsvd_4:2; 663 u8 antidx_d: 3; 664 u8 antidx_c: 3; 665 #endif 666 667 /* DW3 */ 668 u8 signal_quality; 669 #ifdef __LITTLE_ENDIAN 670 u8 vga:5; 671 u8 lna_l:3; 672 u8 bb_power:6; 673 u8 rsvd_9:1; 674 u8 lna_h:1; 675 #else 676 u8 lna_l:3; 677 u8 vga:5; 678 u8 lna_h:1; 679 u8 rsvd_9:1; 680 u8 bb_power:6; 681 #endif 682 u8 rsvd_5; 683 684 /* DW4 */ 685 u32 rsvd_6; 686 687 /* DW5 */ 688 u32 rsvd_7; 689 690 /* DW6 */ 691 u32 rsvd_8; 692 } __packed; 693 694 struct jaguar2_phy_stats_type1 { 695 /* DW0 and DW1 */ 696 u8 page_num; 697 u8 pwdb[4]; 698 #ifdef __LITTLE_ENDIAN 699 u8 l_rxsc: 4; 700 u8 ht_rxsc: 4; 701 #else 702 u8 ht_rxsc: 4; 703 u8 l_rxsc: 4; 704 #endif 705 u8 channel; 706 #ifdef __LITTLE_ENDIAN 707 u8 band: 2; 708 u8 rsvd_0: 1; 709 u8 hw_antsw_occu: 1; 710 u8 gnt_bt: 1; 711 u8 ldpc: 1; 712 u8 stbc: 1; 713 u8 beamformed: 1; 714 #else 715 u8 beamformed: 1; 716 u8 stbc: 1; 717 u8 ldpc: 1; 718 u8 gnt_bt: 1; 719 u8 hw_antsw_occu: 1; 720 u8 rsvd_0: 1; 721 u8 band: 2; 722 #endif 723 724 /* DW2 */ 725 u16 lsig_length; 726 #ifdef __LITTLE_ENDIAN 727 u8 antidx_a: 3; 728 u8 antidx_b: 3; 729 u8 rsvd_1: 2; 730 u8 antidx_c: 3; 731 u8 antidx_d: 3; 732 u8 rsvd_2: 2; 733 #else 734 u8 rsvd_1: 2; 735 u8 antidx_b: 3; 736 u8 antidx_a: 3; 737 u8 rsvd_2: 2; 738 u8 antidx_d: 3; 739 u8 antidx_c: 3; 740 #endif 741 742 /* DW3 */ 743 u8 paid; 744 #ifdef __LITTLE_ENDIAN 745 u8 paid_msb: 1; 746 u8 gid: 6; 747 u8 rsvd_3: 1; 748 #else 749 u8 rsvd_3: 1; 750 u8 gid: 6; 751 u8 paid_msb: 1; 752 #endif 753 u8 intf_pos; 754 #ifdef __LITTLE_ENDIAN 755 u8 intf_pos_msb: 1; 756 u8 rsvd_4: 2; 757 u8 nb_intf_flag: 1; 758 u8 rf_mode: 2; 759 u8 rsvd_5: 2; 760 #else 761 u8 rsvd_5: 2; 762 u8 rf_mode: 2; 763 u8 nb_intf_flag: 1; 764 u8 rsvd_4: 2; 765 u8 intf_pos_msb: 1; 766 #endif 767 768 /* DW4 */ 769 s8 rxevm[4]; /* s(8,1) */ 770 771 /* DW5 */ 772 s8 cfo_tail[4]; /* s(8,7) */ 773 774 /* DW6 */ 775 s8 rxsnr[4]; /* s(8,1) */ 776 } __packed; 777 778 struct jaguar2_phy_stats_type2 { 779 /* DW0 ane DW1 */ 780 u8 page_num; 781 u8 pwdb[4]; 782 #ifdef __LITTLE_ENDIAN 783 u8 l_rxsc: 4; 784 u8 ht_rxsc: 4; 785 #else 786 u8 ht_rxsc: 4; 787 u8 l_rxsc: 4; 788 #endif 789 u8 channel; 790 #ifdef __LITTLE_ENDIAN 791 u8 band: 2; 792 u8 rsvd_0: 1; 793 u8 hw_antsw_occu: 1; 794 u8 gnt_bt: 1; 795 u8 ldpc: 1; 796 u8 stbc: 1; 797 u8 beamformed: 1; 798 #else 799 u8 beamformed: 1; 800 u8 stbc: 1; 801 u8 ldpc: 1; 802 u8 gnt_bt: 1; 803 u8 hw_antsw_occu: 1; 804 u8 rsvd_0: 1; 805 u8 band: 2; 806 #endif 807 808 /* DW2 */ 809 #ifdef __LITTLE_ENDIAN 810 u8 shift_l_map: 6; 811 u8 rsvd_1: 2; 812 #else 813 u8 rsvd_1: 2; 814 u8 shift_l_map: 6; 815 #endif 816 u8 cnt_pw2cca; 817 #ifdef __LITTLE_ENDIAN 818 u8 agc_table_a: 4; 819 u8 agc_table_b: 4; 820 u8 agc_table_c: 4; 821 u8 agc_table_d: 4; 822 #else 823 u8 agc_table_b: 4; 824 u8 agc_table_a: 4; 825 u8 agc_table_d: 4; 826 u8 agc_table_c: 4; 827 #endif 828 829 /* DW3 ~ DW6*/ 830 u8 cnt_cca2agc_rdy; 831 #ifdef __LITTLE_ENDIAN 832 u8 gain_a: 6; 833 u8 rsvd_2: 1; 834 u8 trsw_a: 1; 835 u8 gain_b: 6; 836 u8 rsvd_3: 1; 837 u8 trsw_b: 1; 838 u8 gain_c: 6; 839 u8 rsvd_4: 1; 840 u8 trsw_c: 1; 841 u8 gain_d: 6; 842 u8 rsvd_5: 1; 843 u8 trsw_d: 1; 844 u8 aagc_step_a: 2; 845 u8 aagc_step_b: 2; 846 u8 aagc_step_c: 2; 847 u8 aagc_step_d: 2; 848 #else 849 u8 trsw_a: 1; 850 u8 rsvd_2: 1; 851 u8 gain_a: 6; 852 u8 trsw_b: 1; 853 u8 rsvd_3: 1; 854 u8 gain_b: 6; 855 u8 trsw_c: 1; 856 u8 rsvd_4: 1; 857 u8 gain_c: 6; 858 u8 trsw_d: 1; 859 u8 rsvd_5: 1; 860 u8 gain_d: 6; 861 u8 aagc_step_d: 2; 862 u8 aagc_step_c: 2; 863 u8 aagc_step_b: 2; 864 u8 aagc_step_a: 2; 865 #endif 866 u8 ht_aagc_gain[4]; 867 u8 dagc_gain[4]; 868 #ifdef __LITTLE_ENDIAN 869 u8 counter: 6; 870 u8 rsvd_6: 2; 871 u8 syn_count: 5; 872 u8 rsvd_7:3; 873 #else 874 u8 rsvd_6: 2; 875 u8 counter: 6; 876 u8 rsvd_7:3; 877 u8 syn_count: 5; 878 #endif 879 } __packed; 880 881 /* 882 * Regs to backup 883 */ 884 #define RTL8XXXU_ADDA_REGS 16 885 #define RTL8XXXU_MAC_REGS 4 886 #define RTL8XXXU_BB_REGS 9 887 888 struct rtl8xxxu_firmware_header { 889 __le16 signature; /* 92C0: test chip; 92C, 890 88C0: test chip; 891 88C1: MP A-cut; 892 92C1: MP A-cut */ 893 u8 category; /* AP/NIC and USB/PCI */ 894 u8 function; 895 896 __le16 major_version; /* FW Version */ 897 u8 minor_version; /* FW Subversion, default 0x00 */ 898 u8 reserved1; 899 900 u8 month; /* Release time Month field */ 901 u8 date; /* Release time Date field */ 902 u8 hour; /* Release time Hour field */ 903 u8 minute; /* Release time Minute field */ 904 905 __le16 ramcodesize; /* Size of RAM code */ 906 u16 reserved2; 907 908 __le32 svn_idx; /* SVN entry index */ 909 u32 reserved3; 910 911 u32 reserved4; 912 u32 reserved5; 913 914 u8 data[]; 915 }; 916 917 /* 918 * 8723au/8192cu/8188ru required base power index offset tables. 919 */ 920 struct rtl8xxxu_power_base { 921 u32 reg_0e00; 922 u32 reg_0e04; 923 u32 reg_0e08; 924 u32 reg_086c; 925 926 u32 reg_0e10; 927 u32 reg_0e14; 928 u32 reg_0e18; 929 u32 reg_0e1c; 930 931 u32 reg_0830; 932 u32 reg_0834; 933 u32 reg_0838; 934 u32 reg_086c_2; 935 936 u32 reg_083c; 937 u32 reg_0848; 938 u32 reg_084c; 939 u32 reg_0868; 940 }; 941 942 /* 943 * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14 944 */ 945 struct rtl8723au_idx { 946 #ifdef __LITTLE_ENDIAN 947 int a:4; 948 int b:4; 949 #else 950 int b:4; 951 int a:4; 952 #endif 953 } __attribute__((packed)); 954 955 struct rtl8723au_efuse { 956 __le16 rtl_id; 957 u8 res0[0xe]; 958 u8 cck_tx_power_index_A[3]; /* 0x10 */ 959 u8 cck_tx_power_index_B[3]; 960 u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */ 961 u8 ht40_1s_tx_power_index_B[3]; 962 /* 963 * The following entries are half-bytes split as: 964 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 965 */ 966 struct rtl8723au_idx ht20_tx_power_index_diff[3]; 967 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 968 struct rtl8723au_idx ht40_max_power_offset[3]; 969 struct rtl8723au_idx ht20_max_power_offset[3]; 970 u8 channel_plan; /* 0x28 */ 971 u8 tssi_a; 972 u8 thermal_meter; 973 u8 rf_regulatory; 974 u8 rf_option_2; 975 u8 rf_option_3; 976 u8 rf_option_4; 977 u8 res7; 978 u8 version /* 0x30 */; 979 u8 customer_id_major; 980 u8 customer_id_minor; 981 u8 xtal_k; 982 u8 chipset; /* 0x34 */ 983 u8 res8[0x82]; 984 u8 vid; /* 0xb7 */ 985 u8 res9; 986 u8 pid; /* 0xb9 */ 987 u8 res10[0x0c]; 988 u8 mac_addr[ETH_ALEN]; /* 0xc6 */ 989 u8 res11[2]; 990 u8 vendor_name[7]; 991 u8 res12[2]; 992 u8 device_name[0x29]; /* 0xd7 */ 993 }; 994 995 struct rtl8192cu_efuse { 996 __le16 rtl_id; 997 __le16 hpon; 998 u8 res0[2]; 999 __le16 clk; 1000 __le16 testr; 1001 __le16 vid; 1002 __le16 did; 1003 __le16 svid; 1004 __le16 smid; /* 0x10 */ 1005 u8 res1[4]; 1006 u8 mac_addr[ETH_ALEN]; /* 0x16 */ 1007 u8 res2[2]; 1008 u8 vendor_name[7]; 1009 u8 res3[3]; 1010 u8 device_name[0x14]; /* 0x28 */ 1011 u8 res4[0x1e]; /* 0x3c */ 1012 u8 cck_tx_power_index_A[3]; /* 0x5a */ 1013 u8 cck_tx_power_index_B[3]; 1014 u8 ht40_1s_tx_power_index_A[3]; /* 0x60 */ 1015 u8 ht40_1s_tx_power_index_B[3]; 1016 /* 1017 * The following entries are half-bytes split as: 1018 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 1019 */ 1020 struct rtl8723au_idx ht40_2s_tx_power_index_diff[3]; 1021 struct rtl8723au_idx ht20_tx_power_index_diff[3]; /* 0x69 */ 1022 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 1023 struct rtl8723au_idx ht40_max_power_offset[3]; /* 0x6f */ 1024 struct rtl8723au_idx ht20_max_power_offset[3]; 1025 u8 channel_plan; /* 0x75 */ 1026 u8 tssi_a; 1027 u8 tssi_b; 1028 u8 thermal_meter; /* xtal_k */ /* 0x78 */ 1029 u8 rf_regulatory; 1030 u8 rf_option_2; 1031 u8 rf_option_3; 1032 u8 rf_option_4; 1033 u8 res5[1]; /* 0x7d */ 1034 u8 version; 1035 u8 customer_id; 1036 }; 1037 1038 struct rtl8723bu_pwr_idx { 1039 #ifdef __LITTLE_ENDIAN 1040 int ht20:4; 1041 int ht40:4; 1042 int ofdm:4; 1043 int cck:4; 1044 #else 1045 int cck:4; 1046 int ofdm:4; 1047 int ht40:4; 1048 int ht20:4; 1049 #endif 1050 } __attribute__((packed)); 1051 1052 struct rtl8723bu_efuse_tx_power { 1053 u8 cck_base[6]; 1054 u8 ht40_base[5]; 1055 struct rtl8723au_idx ht20_ofdm_1s_diff; 1056 struct rtl8723bu_pwr_idx pwr_diff[3]; 1057 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ 1058 }; 1059 1060 struct rtl8723bu_efuse { 1061 __le16 rtl_id; 1062 u8 res0[0x0e]; 1063 struct rtl8723bu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1064 struct rtl8723bu_efuse_tx_power tx_power_index_B; /* 0x3a */ 1065 struct rtl8723bu_efuse_tx_power tx_power_index_C; /* 0x64 */ 1066 struct rtl8723bu_efuse_tx_power tx_power_index_D; /* 0x8e */ 1067 u8 channel_plan; /* 0xb8 */ 1068 u8 xtal_k; 1069 u8 thermal_meter; 1070 u8 iqk_lck; 1071 u8 pa_type; /* 0xbc */ 1072 u8 lna_type_2g; /* 0xbd */ 1073 u8 res2[3]; 1074 u8 rf_board_option; 1075 u8 rf_feature_option; 1076 u8 rf_bt_setting; 1077 u8 eeprom_version; 1078 u8 eeprom_customer_id; 1079 u8 res3[2]; 1080 u8 tx_pwr_calibrate_rate; 1081 u8 rf_antenna_option; /* 0xc9 */ 1082 u8 rfe_option; 1083 u8 res4[9]; 1084 u8 usb_optional_function; 1085 u8 res5[0x1e]; 1086 u8 res6[2]; 1087 u8 serial[0x0b]; /* 0xf5 */ 1088 u8 vid; /* 0x100 */ 1089 u8 res7; 1090 u8 pid; 1091 u8 res8[4]; 1092 u8 mac_addr[ETH_ALEN]; /* 0x107 */ 1093 u8 res9[2]; 1094 u8 vendor_name[0x07]; 1095 u8 res10[2]; 1096 u8 device_name[0x14]; 1097 u8 res11[0xcf]; 1098 u8 package_type; /* 0x1fb */ 1099 u8 res12[0x4]; 1100 }; 1101 1102 struct rtl8192eu_efuse_tx_power { 1103 u8 cck_base[6]; 1104 u8 ht40_base[5]; 1105 struct rtl8723au_idx ht20_ofdm_1s_diff; 1106 struct rtl8723bu_pwr_idx pwr_diff[3]; 1107 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ 1108 }; 1109 1110 struct rtl8192eu_efuse { 1111 __le16 rtl_id; 1112 u8 res0[0x0e]; 1113 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1114 struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x3a */ 1115 u8 res2[0x54]; 1116 u8 channel_plan; /* 0xb8 */ 1117 u8 xtal_k; 1118 u8 thermal_meter; 1119 u8 iqk_lck; 1120 u8 pa_type; /* 0xbc */ 1121 u8 lna_type_2g; /* 0xbd */ 1122 u8 res3[1]; 1123 u8 lna_type_5g; /* 0xbf */ 1124 u8 res4[1]; 1125 u8 rf_board_option; 1126 u8 rf_feature_option; 1127 u8 rf_bt_setting; 1128 u8 eeprom_version; 1129 u8 eeprom_customer_id; 1130 u8 res5[3]; 1131 u8 rf_antenna_option; /* 0xc9 */ 1132 u8 res6[6]; 1133 u8 vid; /* 0xd0 */ 1134 u8 res7[1]; 1135 u8 pid; /* 0xd2 */ 1136 u8 res8[1]; 1137 u8 usb_optional_function; 1138 u8 res9[2]; 1139 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 1140 u8 device_info[80]; 1141 u8 res11[3]; 1142 u8 unknown[0x0d]; /* 0x130 */ 1143 u8 res12[0xc3]; 1144 }; 1145 1146 struct rtl8188fu_efuse_tx_power { 1147 u8 cck_base[6]; 1148 u8 ht40_base[5]; 1149 /* a: ofdm; b: ht20 */ 1150 struct rtl8723au_idx ht20_ofdm_1s_diff; 1151 }; 1152 1153 struct rtl8188fu_efuse { 1154 __le16 rtl_id; 1155 u8 res0[0x0e]; 1156 struct rtl8188fu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1157 u8 res1[0x9c]; /* 0x1c */ 1158 u8 channel_plan; /* 0xb8 */ 1159 u8 xtal_k; 1160 u8 thermal_meter; 1161 u8 iqk_lck; 1162 u8 res2[5]; 1163 u8 rf_board_option; 1164 u8 rf_feature_option; 1165 u8 rf_bt_setting; 1166 u8 eeprom_version; 1167 u8 eeprom_customer_id; 1168 u8 res3[2]; 1169 u8 kfree_thermal_k_on; 1170 u8 rf_antenna_option; /* 0xc9 */ 1171 u8 rfe_option; 1172 u8 country_code; 1173 u8 res4[4]; 1174 u8 vid; /* 0xd0 */ 1175 u8 res5[1]; 1176 u8 pid; /* 0xd2 */ 1177 u8 res6[1]; 1178 u8 usb_optional_function; 1179 u8 res7[2]; 1180 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 1181 u8 res8[2]; 1182 u8 vendor_name[7]; 1183 u8 res9[2]; 1184 u8 device_name[7]; /* 0xe8 */ 1185 u8 res10[0x41]; 1186 u8 unknown[0x0d]; /* 0x130 */ 1187 u8 res11[0xc3]; 1188 }; 1189 1190 struct rtl8188eu_efuse { 1191 __le16 rtl_id; 1192 u8 res0[0x0e]; 1193 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1194 u8 res1[0x7e]; /* 0x3a */ 1195 u8 channel_plan; /* 0xb8 */ 1196 u8 xtal_k; 1197 u8 thermal_meter; 1198 u8 iqk_lck; 1199 u8 res2[5]; 1200 u8 rf_board_option; 1201 u8 rf_feature_option; 1202 u8 rf_bt_setting; 1203 u8 eeprom_version; 1204 u8 eeprom_customer_id; 1205 u8 res3[3]; 1206 u8 rf_antenna_option; /* 0xc9 */ 1207 u8 res4[6]; 1208 u8 vid; /* 0xd0 */ 1209 u8 res5[1]; 1210 u8 pid; /* 0xd2 */ 1211 u8 res6[1]; 1212 u8 usb_optional_function; 1213 u8 res7[2]; 1214 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 1215 u8 res8[2]; 1216 u8 vendor_name[7]; 1217 u8 res9[2]; 1218 u8 device_name[0x0b]; /* 0xe8 */ 1219 u8 res10[2]; 1220 u8 serial[0x0b]; /* 0xf5 */ 1221 u8 res11[0x30]; 1222 u8 unknown[0x0d]; /* 0x130 */ 1223 u8 res12[0xc3]; 1224 } __packed; 1225 1226 struct rtl8710bu_efuse { 1227 __le16 rtl_id; 1228 u8 res0[0x1e]; 1229 struct rtl8188fu_efuse_tx_power tx_power_index_A; /* 0x20 */ 1230 u8 res1[0x9c]; /* 0x2c */ 1231 u8 channel_plan; /* 0xc8 */ 1232 u8 xtal_k; /* 0xc9 */ 1233 u8 thermal_meter; /* 0xca */ 1234 u8 res2[0x4f]; 1235 u8 mac_addr[ETH_ALEN]; /* 0x11a */ 1236 u8 res3[0x11]; 1237 u8 rf_board_option; /* 0x131 */ 1238 u8 res4[2]; 1239 u8 eeprom_version; /* 0x134 */ 1240 u8 eeprom_customer_id; /* 0x135 */ 1241 u8 res5[5]; 1242 u8 country_code; /* 0x13b */ 1243 u8 res6[0x84]; 1244 u8 vid[2]; /* 0x1c0 */ 1245 u8 pid[2]; /* 0x1c2 */ 1246 u8 res7[0x3c]; 1247 } __packed; 1248 1249 struct rtl8xxxu_reg8val { 1250 u16 reg; 1251 u8 val; 1252 }; 1253 1254 struct rtl8xxxu_reg32val { 1255 u16 reg; 1256 u32 val; 1257 }; 1258 1259 struct rtl8xxxu_rfregval { 1260 u8 reg; 1261 u32 val; 1262 }; 1263 1264 enum rtl8xxxu_rfpath { 1265 RF_A = 0, 1266 RF_B = 1, 1267 }; 1268 1269 struct rtl8xxxu_rfregs { 1270 u16 hssiparm1; 1271 u16 hssiparm2; 1272 u16 lssiparm; 1273 u16 hspiread; 1274 u16 lssiread; 1275 u16 rf_sw_ctrl; 1276 }; 1277 1278 #define H2C_MAX_MBOX 4 1279 #define H2C_EXT BIT(7) 1280 #define H2C_JOIN_BSS_DISCONNECT 0 1281 #define H2C_JOIN_BSS_CONNECT 1 1282 1283 /* 1284 * H2C (firmware) commands differ between the older generation chips 1285 * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu, 1286 * 8192[de]u, 8192eu, and 8812. 1287 */ 1288 enum h2c_cmd_8723a { 1289 H2C_SET_POWER_MODE = 1, 1290 H2C_JOIN_BSS_REPORT = 2, 1291 H2C_SET_RSSI = 5, 1292 H2C_SET_RATE_MASK = (6 | H2C_EXT), 1293 }; 1294 1295 enum h2c_cmd_8723b { 1296 /* 1297 * Common Class: 000 1298 */ 1299 H2C_8723B_RSVD_PAGE = 0x00, 1300 H2C_8723B_MEDIA_STATUS_RPT = 0x01, 1301 H2C_8723B_SCAN_ENABLE = 0x02, 1302 H2C_8723B_KEEP_ALIVE = 0x03, 1303 H2C_8723B_DISCON_DECISION = 0x04, 1304 H2C_8723B_PSD_OFFLOAD = 0x05, 1305 H2C_8723B_AP_OFFLOAD = 0x08, 1306 H2C_8723B_BCN_RSVDPAGE = 0x09, 1307 H2C_8723B_PROBERSP_RSVDPAGE = 0x0A, 1308 H2C_8723B_FCS_RSVDPAGE = 0x10, 1309 H2C_8723B_FCS_INFO = 0x11, 1310 H2C_8723B_AP_WOW_GPIO_CTRL = 0x13, 1311 1312 /* 1313 * PoweSave Class: 001 1314 */ 1315 H2C_8723B_SET_PWR_MODE = 0x20, 1316 H2C_8723B_PS_TUNING_PARA = 0x21, 1317 H2C_8723B_PS_TUNING_PARA2 = 0x22, 1318 H2C_8723B_P2P_LPS_PARAM = 0x23, 1319 H2C_8723B_P2P_PS_OFFLOAD = 0x24, 1320 H2C_8723B_PS_SCAN_ENABLE = 0x25, 1321 H2C_8723B_SAP_PS_ = 0x26, 1322 H2C_8723B_INACTIVE_PS_ = 0x27, 1323 H2C_8723B_FWLPS_IN_IPS_ = 0x28, 1324 1325 /* 1326 * Dynamic Mechanism Class: 010 1327 */ 1328 H2C_8723B_MACID_CFG_RAID = 0x40, 1329 H2C_8723B_TXBF = 0x41, 1330 H2C_8723B_RSSI_SETTING = 0x42, 1331 H2C_8723B_AP_REQ_TXRPT = 0x43, 1332 H2C_8723B_INIT_RATE_COLLECT = 0x44, 1333 1334 /* 1335 * BT Class: 011 1336 */ 1337 H2C_8723B_B_TYPE_TDMA = 0x60, 1338 H2C_8723B_BT_INFO = 0x61, 1339 H2C_8723B_FORCE_BT_TXPWR = 0x62, 1340 H2C_8723B_BT_IGNORE_WLANACT = 0x63, 1341 H2C_8723B_DAC_SWING_VALUE = 0x64, 1342 H2C_8723B_ANT_SEL_RSV = 0x65, 1343 H2C_8723B_WL_OPMODE = 0x66, 1344 H2C_8723B_BT_MP_OPER = 0x67, 1345 H2C_8723B_BT_CONTROL = 0x68, 1346 H2C_8723B_BT_WIFI_CTRL = 0x69, 1347 H2C_8723B_BT_FW_PATCH = 0x6a, 1348 H2C_8723B_BT_WLAN_CALIBRATION = 0x6d, 1349 H2C_8723B_BT_GRANT = 0x6e, 1350 1351 /* 1352 * WOWLAN Class: 100 1353 */ 1354 H2C_8723B_WOWLAN = 0x80, 1355 H2C_8723B_REMOTE_WAKE_CTRL = 0x81, 1356 H2C_8723B_AOAC_GLOBAL_INFO = 0x82, 1357 H2C_8723B_AOAC_RSVD_PAGE = 0x83, 1358 H2C_8723B_AOAC_RSVD_PAGE2 = 0x84, 1359 H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85, 1360 H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86, 1361 H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87, 1362 1363 H2C_8723B_RESET_TSF = 0xC0, 1364 }; 1365 1366 1367 struct h2c_cmd { 1368 union { 1369 struct { 1370 u8 cmd; 1371 u8 data[7]; 1372 } __packed cmd; 1373 struct { 1374 __le32 data; 1375 __le16 ext; 1376 } __packed raw; 1377 struct { 1378 __le32 data; 1379 __le32 ext; 1380 } __packed raw_wide; 1381 struct { 1382 u8 cmd; 1383 u8 data; 1384 } __packed joinbss; 1385 struct { 1386 u8 cmd; 1387 __le16 mask_hi; 1388 u8 arg; 1389 __le16 mask_lo; 1390 } __packed ramask; 1391 struct { 1392 u8 cmd; 1393 u8 parm; 1394 u8 macid; 1395 u8 macid_end; 1396 } __packed media_status_rpt; 1397 struct { 1398 u8 cmd; 1399 u8 macid; 1400 /* 1401 * [0:4] - RAID 1402 * [7] - SGI 1403 */ 1404 u8 data1; 1405 /* 1406 * [0:1] - Bandwidth 1407 * [3] - No Update 1408 * [4:5] - VHT enable 1409 * [6] - DISPT 1410 * [7] - DISRA 1411 */ 1412 u8 data2; 1413 u8 ramask0; 1414 u8 ramask1; 1415 u8 ramask2; 1416 u8 ramask3; 1417 } __packed b_macid_cfg; 1418 struct { 1419 u8 cmd; 1420 u8 data1; 1421 u8 data2; 1422 u8 data3; 1423 u8 data4; 1424 u8 data5; 1425 } __packed b_type_dma; 1426 struct { 1427 u8 cmd; 1428 u8 data; 1429 } __packed bt_info; 1430 struct { 1431 u8 cmd; 1432 u8 operreq; 1433 u8 opcode; 1434 u8 data; 1435 u8 addr; 1436 } __packed bt_mp_oper; 1437 struct { 1438 u8 cmd; 1439 u8 data; 1440 } __packed bt_wlan_calibration; 1441 struct { 1442 u8 cmd; 1443 u8 data; 1444 } __packed ignore_wlan; 1445 struct { 1446 u8 cmd; 1447 u8 ant_inverse; 1448 u8 int_switch_type; 1449 } __packed ant_sel_rsv; 1450 struct { 1451 u8 cmd; 1452 u8 data; 1453 } __packed bt_grant; 1454 struct { 1455 u8 cmd; 1456 u8 macid; 1457 u8 unknown0; 1458 u8 rssi; 1459 /* 1460 * [0] - is_rx 1461 * [1] - stbc_en 1462 * [2] - noisy_decision 1463 * [6] - bf_en 1464 */ 1465 u8 data; 1466 /* 1467 * [0:6] - ra_th_offset 1468 * [7] - ra_offset_direction 1469 */ 1470 u8 ra_th_offset; 1471 u8 unknown1; 1472 u8 unknown2; 1473 } __packed rssi_report; 1474 }; 1475 }; 1476 1477 enum c2h_evt_8723b { 1478 C2H_8723B_DEBUG = 0, 1479 C2H_8723B_TSF = 1, 1480 C2H_8723B_AP_RPT_RSP = 2, 1481 C2H_8723B_CCX_TX_RPT = 3, 1482 C2H_8723B_BT_RSSI = 4, 1483 C2H_8723B_BT_OP_MODE = 5, 1484 C2H_8723B_EXT_RA_RPT = 6, 1485 C2H_8723B_BT_INFO = 9, 1486 C2H_8723B_HW_INFO_EXCH = 0x0a, 1487 C2H_8723B_BT_MP_INFO = 0x0b, 1488 C2H_8723B_RA_REPORT = 0x0c, 1489 C2H_8723B_FW_DEBUG = 0xff, 1490 }; 1491 1492 enum bt_info_src_8723b { 1493 BT_INFO_SRC_8723B_WIFI_FW = 0x0, 1494 BT_INFO_SRC_8723B_BT_RSP = 0x1, 1495 BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2, 1496 }; 1497 1498 enum bt_mp_oper_opcode_8723b { 1499 BT_MP_OP_GET_BT_VERSION = 0x00, 1500 BT_MP_OP_RESET = 0x01, 1501 BT_MP_OP_TEST_CTRL = 0x02, 1502 BT_MP_OP_SET_BT_MODE = 0x03, 1503 BT_MP_OP_SET_CHNL_TX_GAIN = 0x04, 1504 BT_MP_OP_SET_PKT_TYPE_LEN = 0x05, 1505 BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06, 1506 BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07, 1507 BT_MP_OP_SET_PKT_HEADER = 0x08, 1508 BT_MP_OP_SET_WHITENCOEFF = 0x09, 1509 BT_MP_OP_SET_BD_ADDR_L = 0x0a, 1510 BT_MP_OP_SET_BD_ADDR_H = 0x0b, 1511 BT_MP_OP_WRITE_REG_ADDR = 0x0c, 1512 BT_MP_OP_WRITE_REG_VALUE = 0x0d, 1513 BT_MP_OP_GET_BT_STATUS = 0x0e, 1514 BT_MP_OP_GET_BD_ADDR_L = 0x0f, 1515 BT_MP_OP_GET_BD_ADDR_H = 0x10, 1516 BT_MP_OP_READ_REG = 0x11, 1517 BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12, 1518 BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13, 1519 BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14, 1520 BT_MP_OP_GET_RX_PKT_CNT_L = 0x15, 1521 BT_MP_OP_GET_RX_PKT_CNT_H = 0x16, 1522 BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17, 1523 BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18, 1524 BT_MP_OP_GET_RSSI = 0x19, 1525 BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a, 1526 BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b, 1527 BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c, 1528 BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d, 1529 BT_MP_OP_GET_AFH_MAP_L = 0x1e, 1530 BT_MP_OP_GET_AFH_MAP_M = 0x1f, 1531 BT_MP_OP_GET_AFH_MAP_H = 0x20, 1532 BT_MP_OP_GET_AFH_STATUS = 0x21, 1533 BT_MP_OP_SET_TRACKING_INTERVAL = 0x22, 1534 BT_MP_OP_SET_THERMAL_METER = 0x23, 1535 BT_MP_OP_ENABLE_CFO_TRACKING = 0x24, 1536 }; 1537 1538 enum rtl8xxxu_bw_mode { 1539 RTL8XXXU_CHANNEL_WIDTH_20 = 0, 1540 RTL8XXXU_CHANNEL_WIDTH_40 = 1, 1541 RTL8XXXU_CHANNEL_WIDTH_80 = 2, 1542 RTL8XXXU_CHANNEL_WIDTH_160 = 3, 1543 RTL8XXXU_CHANNEL_WIDTH_80_80 = 4, 1544 RTL8XXXU_CHANNEL_WIDTH_MAX = 5, 1545 }; 1546 1547 struct rtl8723bu_c2h { 1548 u8 id; 1549 u8 seq; 1550 union { 1551 struct { 1552 u8 payload[0]; 1553 } __packed raw; 1554 struct { 1555 u8 ext_id; 1556 u8 status:4; 1557 u8 retlen:4; 1558 u8 opcode_ver:4; 1559 u8 req_num:4; 1560 u8 payload[2]; 1561 } __packed bt_mp_info; 1562 struct { 1563 u8 response_source:4; 1564 u8 dummy0_0:4; 1565 1566 u8 bt_info; 1567 1568 u8 retry_count:4; 1569 u8 dummy2_0:1; 1570 u8 bt_page:1; 1571 u8 tx_rx_mask:1; 1572 u8 dummy2_2:1; 1573 1574 u8 rssi; 1575 1576 u8 basic_rate:1; 1577 u8 bt_has_reset:1; 1578 u8 dummy4_1:1; 1579 u8 ignore_wlan:1; 1580 u8 auto_report:1; 1581 u8 dummy4_2:3; 1582 1583 u8 a4; 1584 u8 a5; 1585 } __packed bt_info; 1586 struct { 1587 u8 rate:7; 1588 u8 sgi:1; 1589 u8 macid; 1590 u8 ldpc:1; 1591 u8 txbf:1; 1592 u8 noisy_state:1; 1593 u8 dummy2_0:5; 1594 u8 dummy3_0; 1595 u8 dummy4_0; 1596 u8 dummy5_0; 1597 u8 bw; 1598 } __packed ra_report; 1599 }; 1600 } __packed; 1601 1602 struct rtl8xxxu_fileops; 1603 1604 /*mlme related.*/ 1605 enum wireless_mode { 1606 WIRELESS_MODE_UNKNOWN = 0, 1607 /* Sub-Element */ 1608 WIRELESS_MODE_B = BIT(0), 1609 WIRELESS_MODE_G = BIT(1), 1610 WIRELESS_MODE_A = BIT(2), 1611 WIRELESS_MODE_N_24G = BIT(3), 1612 WIRELESS_MODE_N_5G = BIT(4), 1613 WIRELESS_AUTO = BIT(5), 1614 WIRELESS_MODE_AC = BIT(6), 1615 WIRELESS_MODE_MAX = 0x7F, 1616 }; 1617 1618 /* from rtlwifi/wifi.h */ 1619 enum ratr_table_mode_new { 1620 RATEID_IDX_BGN_40M_2SS = 0, 1621 RATEID_IDX_BGN_40M_1SS = 1, 1622 RATEID_IDX_BGN_20M_2SS_BN = 2, 1623 RATEID_IDX_BGN_20M_1SS_BN = 3, 1624 RATEID_IDX_GN_N2SS = 4, 1625 RATEID_IDX_GN_N1SS = 5, 1626 RATEID_IDX_BG = 6, 1627 RATEID_IDX_G = 7, 1628 RATEID_IDX_B = 8, 1629 RATEID_IDX_VHT_2SS = 9, 1630 RATEID_IDX_VHT_1SS = 10, 1631 RATEID_IDX_MIX1 = 11, 1632 RATEID_IDX_MIX2 = 12, 1633 RATEID_IDX_VHT_3SS = 13, 1634 RATEID_IDX_BGN_3SS = 14, 1635 }; 1636 1637 #define BT_INFO_8723B_1ANT_B_FTP BIT(7) 1638 #define BT_INFO_8723B_1ANT_B_A2DP BIT(6) 1639 #define BT_INFO_8723B_1ANT_B_HID BIT(5) 1640 #define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT(4) 1641 #define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT(3) 1642 #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT(2) 1643 #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT(1) 1644 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT(0) 1645 1646 enum _BT_8723B_1ANT_STATUS { 1647 BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE = 0x0, 1648 BT_8723B_1ANT_STATUS_CONNECTED_IDLE = 0x1, 1649 BT_8723B_1ANT_STATUS_INQ_PAGE = 0x2, 1650 BT_8723B_1ANT_STATUS_ACL_BUSY = 0x3, 1651 BT_8723B_1ANT_STATUS_SCO_BUSY = 0x4, 1652 BT_8723B_1ANT_STATUS_ACL_SCO_BUSY = 0x5, 1653 BT_8723B_1ANT_STATUS_MAX 1654 }; 1655 1656 struct rtl8xxxu_btcoex { 1657 u8 bt_status; 1658 bool bt_busy; 1659 bool has_sco; 1660 bool has_a2dp; 1661 bool has_hid; 1662 bool has_pan; 1663 bool hid_only; 1664 bool a2dp_only; 1665 bool c2h_bt_inquiry; 1666 }; 1667 1668 #define RTL8XXXU_RATR_STA_INIT 0 1669 #define RTL8XXXU_RATR_STA_HIGH 1 1670 #define RTL8XXXU_RATR_STA_MID 2 1671 #define RTL8XXXU_RATR_STA_LOW 3 1672 1673 #define RTL8XXXU_NOISE_FLOOR_MIN -100 1674 #define RTL8XXXU_SNR_THRESH_HIGH 50 1675 #define RTL8XXXU_SNR_THRESH_LOW 20 1676 1677 struct rtl8xxxu_ra_report { 1678 struct rate_info txrate; 1679 u32 bit_rate; 1680 u8 desc_rate; 1681 }; 1682 1683 struct rtl8xxxu_ra_info { 1684 u8 rate_id; 1685 u32 rate_mask; 1686 u32 ra_use_rate; 1687 u8 rate_sgi; 1688 u8 rssi_sta_ra; /* Percentage */ 1689 u8 pre_rssi_sta_ra; 1690 u8 sgi_enable; 1691 u8 decision_rate; 1692 u8 pre_rate; 1693 u8 highest_rate; 1694 u8 lowest_rate; 1695 u32 nsc_up; 1696 u32 nsc_down; 1697 u32 total; 1698 u16 retry[5]; 1699 u16 drop; 1700 u16 rpt_time; 1701 u16 pre_min_rpt_time; 1702 u8 dynamic_tx_rpt_timing_counter; 1703 u8 ra_waiting_counter; 1704 u8 ra_pending_counter; 1705 u8 ra_drop_after_down; 1706 u8 pt_try_state; /* 0 trying state, 1 for decision state */ 1707 u8 pt_stage; /* 0~6 */ 1708 u8 pt_stop_count; /* Stop PT counter */ 1709 u8 pt_pre_rate; /* if rate change do PT */ 1710 u8 pt_pre_rssi; /* if RSSI change 5% do PT */ 1711 u8 pt_mode_ss; /* decide which rate should do PT */ 1712 u8 ra_stage; /* StageRA, decide how many times RA will be done between PT */ 1713 u8 pt_smooth_factor; 1714 }; 1715 1716 #define CFO_TH_XTAL_HIGH 20 /* kHz */ 1717 #define CFO_TH_XTAL_LOW 10 /* kHz */ 1718 #define CFO_TH_ATC 80 /* kHz */ 1719 1720 struct rtl8xxxu_cfo_tracking { 1721 bool adjust; 1722 bool atc_status; 1723 int cfo_tail[2]; 1724 u8 crystal_cap; 1725 u32 packet_count; 1726 u32 packet_count_pre; 1727 }; 1728 1729 #define RTL8XXXU_HW_LED_CONTROL 2 1730 1731 struct rtl8xxxu_priv { 1732 struct ieee80211_hw *hw; 1733 struct usb_device *udev; 1734 struct rtl8xxxu_fileops *fops; 1735 1736 spinlock_t tx_urb_lock; 1737 struct list_head tx_urb_free_list; 1738 int tx_urb_free_count; 1739 bool tx_stopped; 1740 1741 spinlock_t rx_urb_lock; 1742 struct list_head rx_urb_pending_list; 1743 int rx_urb_pending_count; 1744 bool shutdown; 1745 struct work_struct rx_urb_wq; 1746 1747 u8 mac_addr[ETH_ALEN]; 1748 char chip_name[8]; 1749 char chip_vendor[8]; 1750 u8 cck_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1751 u8 cck_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1752 u8 ht40_1s_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1753 u8 ht40_1s_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1754 /* 1755 * The following entries are half-bytes split as: 1756 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 1757 */ 1758 struct rtl8723au_idx ht40_2s_tx_power_index_diff[ 1759 RTL8723A_CHANNEL_GROUPS]; 1760 struct rtl8723au_idx ht20_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1761 struct rtl8723au_idx ofdm_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1762 struct rtl8723au_idx ht40_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1763 struct rtl8723au_idx ht20_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1764 /* 1765 * Newer generation chips only keep power diffs per TX count, 1766 * not per channel group. 1767 */ 1768 struct rtl8723au_idx ofdm_tx_power_diff[RTL8723B_TX_COUNT]; 1769 struct rtl8723au_idx ht20_tx_power_diff[RTL8723B_TX_COUNT]; 1770 struct rtl8723au_idx ht40_tx_power_diff[RTL8723B_TX_COUNT]; 1771 struct rtl8xxxu_power_base *power_base; 1772 u8 package_type; 1773 u32 chip_cut:4; 1774 u32 rom_rev:4; 1775 u32 is_multi_func:1; 1776 u32 has_wifi:1; 1777 u32 has_bluetooth:1; 1778 u32 enable_bluetooth:1; 1779 u32 has_gps:1; 1780 u32 hi_pa:1; 1781 u32 vendor_umc:1; 1782 u32 vendor_smic:1; 1783 u32 has_polarity_ctrl:1; 1784 u32 has_eeprom:1; 1785 u32 boot_eeprom:1; 1786 u32 usb_interrupts:1; 1787 u32 ep_tx_high_queue:1; 1788 u32 ep_tx_normal_queue:1; 1789 u32 ep_tx_low_queue:1; 1790 u32 rx_buf_aggregation:1; 1791 u32 cck_agc_report_type:1; 1792 u32 cck_new_agc:1; 1793 u8 default_crystal_cap; 1794 unsigned int pipe_interrupt; 1795 unsigned int pipe_in; 1796 unsigned int pipe_out[TXDESC_QUEUE_MAX]; 1797 u8 out_ep[RTL8XXXU_OUT_ENDPOINTS]; 1798 u8 ep_tx_count; 1799 u8 rf_paths; 1800 u8 rx_paths; 1801 u8 tx_paths; 1802 u32 rege94; 1803 u32 rege9c; 1804 u32 regeb4; 1805 u32 regebc; 1806 int next_mbox; 1807 int nr_out_eps; 1808 1809 struct mutex h2c_mutex; 1810 /* Protect the indirect register accesses of RTL8710BU. */ 1811 struct mutex syson_indirect_access_mutex; 1812 1813 struct usb_anchor rx_anchor; 1814 struct usb_anchor tx_anchor; 1815 struct usb_anchor int_anchor; 1816 struct rtl8xxxu_firmware_header *fw_data; 1817 size_t fw_size; 1818 struct mutex usb_buf_mutex; 1819 union { 1820 __le32 val32; 1821 __le16 val16; 1822 u8 val8; 1823 } usb_buf; 1824 union { 1825 u8 raw[EFUSE_MAP_LEN]; 1826 struct rtl8723au_efuse efuse8723; 1827 struct rtl8723bu_efuse efuse8723bu; 1828 struct rtl8192cu_efuse efuse8192; 1829 struct rtl8192eu_efuse efuse8192eu; 1830 struct rtl8188fu_efuse efuse8188fu; 1831 struct rtl8188eu_efuse efuse8188eu; 1832 struct rtl8710bu_efuse efuse8710bu; 1833 } efuse_wifi; 1834 u32 adda_backup[RTL8XXXU_ADDA_REGS]; 1835 u32 mac_backup[RTL8XXXU_MAC_REGS]; 1836 u32 bb_backup[RTL8XXXU_BB_REGS]; 1837 u32 bb_recovery_backup[RTL8XXXU_BB_REGS]; 1838 enum rtl8xxxu_rtl_chip rtl_chip; 1839 u8 pi_enabled:1; 1840 u8 no_pape:1; 1841 u8 int_buf[USB_INTR_CONTENT_LENGTH]; 1842 u8 rssi_level; 1843 DECLARE_BITMAP(tx_aggr_started, IEEE80211_NUM_TIDS); 1844 DECLARE_BITMAP(tid_tx_operational, IEEE80211_NUM_TIDS); 1845 /* 1846 * Only one virtual interface permitted because only STA mode 1847 * is supported and no iface_combinations are provided. 1848 */ 1849 struct ieee80211_vif *vif; 1850 struct delayed_work ra_watchdog; 1851 struct work_struct c2hcmd_work; 1852 struct sk_buff_head c2hcmd_queue; 1853 struct rtl8xxxu_btcoex bt_coex; 1854 struct rtl8xxxu_ra_report ra_report; 1855 struct rtl8xxxu_cfo_tracking cfo_tracking; 1856 struct rtl8xxxu_ra_info ra_info; 1857 1858 bool led_registered; 1859 char led_name[32]; 1860 struct led_classdev led_cdev; 1861 }; 1862 1863 struct rtl8xxxu_rx_urb { 1864 struct urb urb; 1865 struct ieee80211_hw *hw; 1866 struct list_head list; 1867 }; 1868 1869 struct rtl8xxxu_tx_urb { 1870 struct urb urb; 1871 struct ieee80211_hw *hw; 1872 struct list_head list; 1873 }; 1874 1875 struct rtl8xxxu_fileops { 1876 int (*identify_chip) (struct rtl8xxxu_priv *priv); 1877 int (*read_efuse) (struct rtl8xxxu_priv *priv); 1878 int (*parse_efuse) (struct rtl8xxxu_priv *priv); 1879 int (*load_firmware) (struct rtl8xxxu_priv *priv); 1880 int (*power_on) (struct rtl8xxxu_priv *priv); 1881 void (*power_off) (struct rtl8xxxu_priv *priv); 1882 void (*reset_8051) (struct rtl8xxxu_priv *priv); 1883 int (*llt_init) (struct rtl8xxxu_priv *priv); 1884 void (*init_phy_bb) (struct rtl8xxxu_priv *priv); 1885 int (*init_phy_rf) (struct rtl8xxxu_priv *priv); 1886 void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv); 1887 void (*phy_lc_calibrate) (struct rtl8xxxu_priv *priv); 1888 void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv); 1889 void (*config_channel) (struct ieee80211_hw *hw); 1890 int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb); 1891 void (*parse_phystats) (struct rtl8xxxu_priv *priv, 1892 struct ieee80211_rx_status *rx_status, 1893 struct rtl8723au_phy_stats *phy_stats, 1894 u32 rxmcs, struct ieee80211_hdr *hdr, 1895 bool crc_icv_err); 1896 void (*init_aggregation) (struct rtl8xxxu_priv *priv); 1897 void (*init_statistics) (struct rtl8xxxu_priv *priv); 1898 void (*init_burst) (struct rtl8xxxu_priv *priv); 1899 void (*enable_rf) (struct rtl8xxxu_priv *priv); 1900 void (*disable_rf) (struct rtl8xxxu_priv *priv); 1901 void (*usb_quirks) (struct rtl8xxxu_priv *priv); 1902 void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel, 1903 bool ht40); 1904 void (*update_rate_mask) (struct rtl8xxxu_priv *priv, 1905 u32 ramask, u8 rateid, int sgi, int txbw_40mhz); 1906 void (*report_connect) (struct rtl8xxxu_priv *priv, 1907 u8 macid, bool connect); 1908 void (*report_rssi) (struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 1909 void (*fill_txdesc) (struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 1910 struct ieee80211_tx_info *tx_info, 1911 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 1912 bool short_preamble, bool ampdu_enable, 1913 u32 rts_rate); 1914 void (*set_crystal_cap) (struct rtl8xxxu_priv *priv, u8 crystal_cap); 1915 s8 (*cck_rssi) (struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats); 1916 int (*led_classdev_brightness_set) (struct led_classdev *led_cdev, 1917 enum led_brightness brightness); 1918 int writeN_block_size; 1919 int rx_agg_buf_size; 1920 char tx_desc_size; 1921 char rx_desc_size; 1922 u8 has_s0s1:1; 1923 u8 has_tx_report:1; 1924 u8 gen2_thermal_meter:1; 1925 u8 needs_full_init:1; 1926 u8 init_reg_rxfltmap:1; 1927 u8 init_reg_pkt_life_time:1; 1928 u8 init_reg_hmtfr:1; 1929 u8 ampdu_max_time; 1930 u8 ustime_tsf_edca; 1931 u32 adda_1t_init; 1932 u32 adda_1t_path_on; 1933 u32 adda_2t_path_on_a; 1934 u32 adda_2t_path_on_b; 1935 u16 trxff_boundary; 1936 u8 pbp_rx; 1937 u8 pbp_tx; 1938 const struct rtl8xxxu_reg8val *mactable; 1939 u8 total_page_num; 1940 u8 page_num_hi; 1941 u8 page_num_lo; 1942 u8 page_num_norm; 1943 u8 last_llt_entry; 1944 }; 1945 1946 extern int rtl8xxxu_debug; 1947 1948 extern const struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[]; 1949 extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[]; 1950 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr); 1951 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr); 1952 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr); 1953 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val); 1954 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val); 1955 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val); 1956 int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits); 1957 int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits); 1958 int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits); 1959 int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits); 1960 int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits); 1961 int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits); 1962 int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr, 1963 u32 mask, u32 val); 1964 1965 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, 1966 enum rtl8xxxu_rfpath path, u8 reg); 1967 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, 1968 enum rtl8xxxu_rfpath path, u8 reg, u32 data); 1969 int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv, 1970 enum rtl8xxxu_rfpath path, u8 reg, 1971 u32 mask, u32 val); 1972 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 1973 u32 *backup, int count); 1974 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 1975 u32 *backup, int count); 1976 void rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, 1977 const u32 *reg, u32 *backup); 1978 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, 1979 const u32 *reg, u32 *backup); 1980 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, 1981 bool path_a_on); 1982 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, 1983 const u32 *regs, u32 *backup); 1984 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, 1985 int result[][8], int candidate, bool tx_only); 1986 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, 1987 int result[][8], int candidate, bool tx_only); 1988 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, 1989 const struct rtl8xxxu_rfregval *table, 1990 enum rtl8xxxu_rfpath path); 1991 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, 1992 const struct rtl8xxxu_reg32val *array); 1993 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name); 1994 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv); 1995 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv); 1996 void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor); 1997 void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor); 1998 void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv); 1999 int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv); 2000 int rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data); 2001 int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv); 2002 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv); 2003 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv); 2004 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start); 2005 void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv); 2006 void rtl8188f_phy_lc_calibrate(struct rtl8xxxu_priv *priv); 2007 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv); 2008 int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, 2009 struct h2c_cmd *h2c, int len); 2010 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv); 2011 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv); 2012 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv); 2013 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv); 2014 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv); 2015 void rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, 2016 int channel, bool ht40); 2017 void rtl8188f_set_tx_power(struct rtl8xxxu_priv *priv, 2018 int channel, bool ht40); 2019 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw); 2020 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw); 2021 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv); 2022 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv); 2023 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, 2024 u32 ramask, u8 rateid, int sgi, int txbw_40mhz); 2025 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, 2026 u32 ramask, u8 rateid, int sgi, int txbw_40mhz); 2027 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, 2028 u8 macid, bool connect); 2029 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, 2030 u8 macid, bool connect); 2031 void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 2032 void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 2033 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv); 2034 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv); 2035 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv); 2036 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv); 2037 void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv); 2038 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 2039 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 2040 void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv, 2041 struct ieee80211_rx_status *rx_status, 2042 struct rtl8723au_phy_stats *phy_stats, 2043 u32 rxmcs, struct ieee80211_hdr *hdr, 2044 bool crc_icv_err); 2045 void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv, 2046 struct ieee80211_rx_status *rx_status, 2047 struct rtl8723au_phy_stats *phy_stats, 2048 u32 rxmcs, struct ieee80211_hdr *hdr, 2049 bool crc_icv_err); 2050 int rtl8xxxu_gen2_channel_to_group(int channel); 2051 bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, 2052 int result[][8], int c1, int c2); 2053 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, 2054 int result[][8], int c1, int c2); 2055 void rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 2056 struct ieee80211_tx_info *tx_info, 2057 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 2058 bool short_preamble, bool ampdu_enable, 2059 u32 rts_rate); 2060 void rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 2061 struct ieee80211_tx_info *tx_info, 2062 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 2063 bool short_preamble, bool ampdu_enable, 2064 u32 rts_rate); 2065 void rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 2066 struct ieee80211_tx_info *tx_info, 2067 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 2068 bool short_preamble, bool ampdu_enable, 2069 u32 rts_rate); 2070 void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, 2071 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5); 2072 void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv); 2073 void rtl8723a_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap); 2074 void rtl8188f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap); 2075 s8 rtl8723a_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats); 2076 void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt, 2077 u8 rate, u8 sgi, u8 bw); 2078 void rtl8188e_ra_info_init_all(struct rtl8xxxu_ra_info *ra); 2079 void rtl8188e_handle_ra_tx_report2(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 2080 2081 extern struct rtl8xxxu_fileops rtl8710bu_fops; 2082 extern struct rtl8xxxu_fileops rtl8188fu_fops; 2083 extern struct rtl8xxxu_fileops rtl8188eu_fops; 2084 extern struct rtl8xxxu_fileops rtl8192cu_fops; 2085 extern struct rtl8xxxu_fileops rtl8192eu_fops; 2086 extern struct rtl8xxxu_fileops rtl8723au_fops; 2087 extern struct rtl8xxxu_fileops rtl8723bu_fops; 2088