1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 4 * 5 * Register definitions taken from original Realtek rtl8723au driver 6 */ 7 8 #include <asm/byteorder.h> 9 10 #define RTL8XXXU_DEBUG_REG_WRITE 0x01 11 #define RTL8XXXU_DEBUG_REG_READ 0x02 12 #define RTL8XXXU_DEBUG_RFREG_WRITE 0x04 13 #define RTL8XXXU_DEBUG_RFREG_READ 0x08 14 #define RTL8XXXU_DEBUG_CHANNEL 0x10 15 #define RTL8XXXU_DEBUG_TX 0x20 16 #define RTL8XXXU_DEBUG_TX_DUMP 0x40 17 #define RTL8XXXU_DEBUG_RX 0x80 18 #define RTL8XXXU_DEBUG_RX_DUMP 0x100 19 #define RTL8XXXU_DEBUG_USB 0x200 20 #define RTL8XXXU_DEBUG_KEY 0x400 21 #define RTL8XXXU_DEBUG_H2C 0x800 22 #define RTL8XXXU_DEBUG_ACTION 0x1000 23 #define RTL8XXXU_DEBUG_EFUSE 0x2000 24 #define RTL8XXXU_DEBUG_INTERRUPT 0x4000 25 26 #define RTW_USB_CONTROL_MSG_TIMEOUT 500 27 #define RTL8XXXU_MAX_REG_POLL 500 28 #define USB_INTR_CONTENT_LENGTH 56 29 30 #define RTL8XXXU_OUT_ENDPOINTS 4 31 32 #define REALTEK_USB_READ 0xc0 33 #define REALTEK_USB_WRITE 0x40 34 #define REALTEK_USB_CMD_REQ 0x05 35 #define REALTEK_USB_CMD_IDX 0x00 36 37 #define TX_TOTAL_PAGE_NUM 0xf8 38 #define TX_TOTAL_PAGE_NUM_8188F 0xf7 39 #define TX_TOTAL_PAGE_NUM_8188E 0xa9 40 #define TX_TOTAL_PAGE_NUM_8192E 0xf3 41 #define TX_TOTAL_PAGE_NUM_8723B 0xf7 42 /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */ 43 #define TX_PAGE_NUM_PUBQ 0xe7 44 #define TX_PAGE_NUM_HI_PQ 0x0c 45 #define TX_PAGE_NUM_LO_PQ 0x02 46 #define TX_PAGE_NUM_NORM_PQ 0x02 47 48 #define TX_PAGE_NUM_PUBQ_8188F 0xe5 49 #define TX_PAGE_NUM_HI_PQ_8188F 0x0c 50 #define TX_PAGE_NUM_LO_PQ_8188F 0x02 51 #define TX_PAGE_NUM_NORM_PQ_8188F 0x02 52 53 #define TX_PAGE_NUM_PUBQ_8188E 0x47 54 #define TX_PAGE_NUM_HI_PQ_8188E 0x29 55 #define TX_PAGE_NUM_LO_PQ_8188E 0x1c 56 #define TX_PAGE_NUM_NORM_PQ_8188E 0x1c 57 58 #define TX_PAGE_NUM_PUBQ_8192E 0xe7 59 #define TX_PAGE_NUM_HI_PQ_8192E 0x08 60 #define TX_PAGE_NUM_LO_PQ_8192E 0x0c 61 #define TX_PAGE_NUM_NORM_PQ_8192E 0x00 62 63 #define TX_PAGE_NUM_PUBQ_8723B 0xe7 64 #define TX_PAGE_NUM_HI_PQ_8723B 0x0c 65 #define TX_PAGE_NUM_LO_PQ_8723B 0x02 66 #define TX_PAGE_NUM_NORM_PQ_8723B 0x02 67 68 #define RTL_FW_PAGE_SIZE 4096 69 #define RTL8XXXU_FIRMWARE_POLL_MAX 1000 70 71 #define RTL8723A_CHANNEL_GROUPS 3 72 #define RTL8723A_MAX_RF_PATHS 2 73 #define RTL8723B_CHANNEL_GROUPS 6 74 #define RTL8723B_TX_COUNT 4 75 #define RTL8723B_MAX_RF_PATHS 4 76 #define RTL8XXXU_MAX_CHANNEL_GROUPS 6 77 #define RF6052_MAX_TX_PWR 0x3f 78 79 #define EFUSE_MAP_LEN 512 80 #define EFUSE_MAX_SECTION_8723A 64 81 #define EFUSE_REAL_CONTENT_LEN_8723A 512 82 #define EFUSE_BT_MAP_LEN_8723A 1024 83 #define EFUSE_MAX_WORD_UNIT 4 84 85 enum rtl8xxxu_rtl_chip { 86 RTL8192S = 0x81920, 87 RTL8191S = 0x81910, 88 RTL8192C = 0x8192c, 89 RTL8191C = 0x8191c, 90 RTL8188C = 0x8188c, 91 RTL8188R = 0x81889, 92 RTL8192D = 0x8192d, 93 RTL8723A = 0x8723a, 94 RTL8188E = 0x8188e, 95 RTL8812 = 0x88120, 96 RTL8821 = 0x88210, 97 RTL8192E = 0x8192e, 98 RTL8191E = 0x8191e, 99 RTL8723B = 0x8723b, 100 RTL8814A = 0x8814a, 101 RTL8881A = 0x8881a, 102 RTL8821B = 0x8821b, 103 RTL8822B = 0x8822b, 104 RTL8703B = 0x8703b, 105 RTL8195A = 0x8195a, 106 RTL8188F = 0x8188f 107 }; 108 109 enum rtl8xxxu_rx_type { 110 RX_TYPE_DATA_PKT = 0, 111 RX_TYPE_C2H = 1, 112 RX_TYPE_ERROR = -1 113 }; 114 115 struct rtl8xxxu_rxdesc16 { 116 #ifdef __LITTLE_ENDIAN 117 u32 pktlen:14; 118 u32 crc32:1; 119 u32 icverr:1; 120 u32 drvinfo_sz:4; 121 u32 security:3; 122 u32 qos:1; 123 u32 shift:2; 124 u32 phy_stats:1; 125 u32 swdec:1; 126 u32 ls:1; 127 u32 fs:1; 128 u32 eor:1; 129 u32 own:1; 130 131 u32 macid:5; 132 u32 tid:4; 133 u32 hwrsvd:4; 134 u32 amsdu:1; 135 u32 paggr:1; 136 u32 faggr:1; 137 u32 a1fit:4; 138 u32 a2fit:4; 139 u32 pam:1; 140 u32 pwr:1; 141 u32 md:1; 142 u32 mf:1; 143 u32 type:2; 144 u32 mc:1; 145 u32 bc:1; 146 147 u32 seq:12; 148 u32 frag:4; 149 u32 pkt_cnt:8; 150 u32 reserved:6; 151 u32 nextind:1; 152 u32 reserved0:1; 153 154 u32 rxmcs:6; 155 u32 rxht:1; 156 u32 gf:1; 157 u32 splcp:1; 158 u32 bw:1; 159 u32 htc:1; 160 u32 eosp:1; 161 u32 bssidfit:2; 162 u32 rpt_sel:2; /* 8188e */ 163 u32 reserved1:14; 164 u32 unicastwake:1; 165 u32 magicwake:1; 166 167 u32 pattern0match:1; 168 u32 pattern1match:1; 169 u32 pattern2match:1; 170 u32 pattern3match:1; 171 u32 pattern4match:1; 172 u32 pattern5match:1; 173 u32 pattern6match:1; 174 u32 pattern7match:1; 175 u32 pattern8match:1; 176 u32 pattern9match:1; 177 u32 patternamatch:1; 178 u32 patternbmatch:1; 179 u32 patterncmatch:1; 180 u32 reserved2:19; 181 #else 182 u32 own:1; 183 u32 eor:1; 184 u32 fs:1; 185 u32 ls:1; 186 u32 swdec:1; 187 u32 phy_stats:1; 188 u32 shift:2; 189 u32 qos:1; 190 u32 security:3; 191 u32 drvinfo_sz:4; 192 u32 icverr:1; 193 u32 crc32:1; 194 u32 pktlen:14; 195 196 u32 bc:1; 197 u32 mc:1; 198 u32 type:2; 199 u32 mf:1; 200 u32 md:1; 201 u32 pwr:1; 202 u32 pam:1; 203 u32 a2fit:4; 204 u32 a1fit:4; 205 u32 faggr:1; 206 u32 paggr:1; 207 u32 amsdu:1; 208 u32 hwrsvd:4; 209 u32 tid:4; 210 u32 macid:5; 211 212 u32 reserved0:1; 213 u32 nextind:1; 214 u32 reserved:6; 215 u32 pkt_cnt:8; 216 u32 frag:4; 217 u32 seq:12; 218 219 u32 magicwake:1; 220 u32 unicastwake:1; 221 u32 reserved1:14; 222 u32 rpt_sel:2; /* 8188e */ 223 u32 bssidfit:2; 224 u32 eosp:1; 225 u32 htc:1; 226 u32 bw:1; 227 u32 splcp:1; 228 u32 gf:1; 229 u32 rxht:1; 230 u32 rxmcs:6; 231 232 u32 reserved2:19; 233 u32 patterncmatch:1; 234 u32 patternbmatch:1; 235 u32 patternamatch:1; 236 u32 pattern9match:1; 237 u32 pattern8match:1; 238 u32 pattern7match:1; 239 u32 pattern6match:1; 240 u32 pattern5match:1; 241 u32 pattern4match:1; 242 u32 pattern3match:1; 243 u32 pattern2match:1; 244 u32 pattern1match:1; 245 u32 pattern0match:1; 246 #endif 247 u32 tsfl; 248 #if 0 249 u32 bassn:12; 250 u32 bavld:1; 251 u32 reserved3:19; 252 #endif 253 }; 254 255 struct rtl8xxxu_rxdesc24 { 256 #ifdef __LITTLE_ENDIAN 257 u32 pktlen:14; 258 u32 crc32:1; 259 u32 icverr:1; 260 u32 drvinfo_sz:4; 261 u32 security:3; 262 u32 qos:1; 263 u32 shift:2; 264 u32 phy_stats:1; 265 u32 swdec:1; 266 u32 ls:1; 267 u32 fs:1; 268 u32 eor:1; 269 u32 own:1; 270 271 u32 macid:7; 272 u32 dummy1_0:1; 273 u32 tid:4; 274 u32 dummy1_1:1; 275 u32 amsdu:1; 276 u32 rxid_match:1; 277 u32 paggr:1; 278 u32 a1fit:4; /* 16 */ 279 u32 chkerr:1; 280 u32 ipver:1; 281 u32 tcpudp:1; 282 u32 chkvld:1; 283 u32 pam:1; 284 u32 pwr:1; 285 u32 more_data:1; 286 u32 more_frag:1; 287 u32 type:2; 288 u32 mc:1; 289 u32 bc:1; 290 291 u32 seq:12; 292 u32 frag:4; 293 u32 rx_is_qos:1; /* 16 */ 294 u32 dummy2_0:1; 295 u32 wlanhd_iv_len:6; 296 u32 dummy2_1:4; 297 u32 rpt_sel:1; 298 u32 dummy2_2:3; 299 300 u32 rxmcs:7; 301 u32 dummy3_0:3; 302 u32 htc:1; 303 u32 eosp:1; 304 u32 bssidfit:2; 305 u32 dummy3_1:2; 306 u32 usb_agg_pktnum:8; /* 16 */ 307 u32 dummy3_2:5; 308 u32 pattern_match:1; 309 u32 unicast_match:1; 310 u32 magic_match:1; 311 312 u32 splcp:1; 313 u32 ldcp:1; 314 u32 stbc:1; 315 u32 dummy4_0:1; 316 u32 bw:2; 317 u32 dummy4_1:26; 318 #else 319 u32 own:1; 320 u32 eor:1; 321 u32 fs:1; 322 u32 ls:1; 323 u32 swdec:1; 324 u32 phy_stats:1; 325 u32 shift:2; 326 u32 qos:1; 327 u32 security:3; 328 u32 drvinfo_sz:4; 329 u32 icverr:1; 330 u32 crc32:1; 331 u32 pktlen:14; 332 333 u32 bc:1; 334 u32 mc:1; 335 u32 type:2; 336 u32 mf:1; 337 u32 md:1; 338 u32 pwr:1; 339 u32 pam:1; 340 u32 a2fit:4; 341 u32 a1fit:4; 342 u32 faggr:1; 343 u32 paggr:1; 344 u32 amsdu:1; 345 u32 hwrsvd:4; 346 u32 tid:4; 347 u32 macid:5; 348 349 u32 dummy2_2:3; 350 u32 rpt_sel:1; 351 u32 dummy2_1:4; 352 u32 wlanhd_iv_len:6; 353 u32 dummy2_0:1; 354 u32 rx_is_qos:1; 355 u32 frag:4; /* 16 */ 356 u32 seq:12; 357 358 u32 magic_match:1; 359 u32 unicast_match:1; 360 u32 pattern_match:1; 361 u32 dummy3_2:5; 362 u32 usb_agg_pktnum:8; 363 u32 dummy3_1:2; /* 16 */ 364 u32 bssidfit:2; 365 u32 eosp:1; 366 u32 htc:1; 367 u32 dummy3_0:3; 368 u32 rxmcs:7; 369 370 u32 dumm4_1:26; 371 u32 bw:2; 372 u32 dummy4_0:1; 373 u32 stbc:1; 374 u32 ldcp:1; 375 u32 splcp:1; 376 #endif 377 u32 tsfl; 378 }; 379 380 struct rtl8xxxu_txdesc32 { 381 __le16 pkt_size; 382 u8 pkt_offset; 383 u8 txdw0; 384 __le32 txdw1; 385 __le32 txdw2; 386 __le32 txdw3; 387 __le32 txdw4; 388 __le32 txdw5; 389 __le32 txdw6; 390 __le16 csum; 391 __le16 txdw7; 392 }; 393 394 struct rtl8xxxu_txdesc40 { 395 __le16 pkt_size; 396 u8 pkt_offset; 397 u8 txdw0; 398 __le32 txdw1; 399 __le32 txdw2; 400 __le32 txdw3; 401 __le32 txdw4; 402 __le32 txdw5; 403 __le32 txdw6; 404 __le16 csum; 405 __le16 txdw7; 406 __le32 txdw8; 407 __le32 txdw9; 408 }; 409 410 /* CCK Rates, TxHT = 0 */ 411 #define DESC_RATE_1M 0x00 412 #define DESC_RATE_2M 0x01 413 #define DESC_RATE_5_5M 0x02 414 #define DESC_RATE_11M 0x03 415 416 /* OFDM Rates, TxHT = 0 */ 417 #define DESC_RATE_6M 0x04 418 #define DESC_RATE_9M 0x05 419 #define DESC_RATE_12M 0x06 420 #define DESC_RATE_18M 0x07 421 #define DESC_RATE_24M 0x08 422 #define DESC_RATE_36M 0x09 423 #define DESC_RATE_48M 0x0a 424 #define DESC_RATE_54M 0x0b 425 426 /* MCS Rates, TxHT = 1 */ 427 #define DESC_RATE_MCS0 0x0c 428 #define DESC_RATE_MCS1 0x0d 429 #define DESC_RATE_MCS2 0x0e 430 #define DESC_RATE_MCS3 0x0f 431 #define DESC_RATE_MCS4 0x10 432 #define DESC_RATE_MCS5 0x11 433 #define DESC_RATE_MCS6 0x12 434 #define DESC_RATE_MCS7 0x13 435 #define DESC_RATE_MCS8 0x14 436 #define DESC_RATE_MCS9 0x15 437 #define DESC_RATE_MCS10 0x16 438 #define DESC_RATE_MCS11 0x17 439 #define DESC_RATE_MCS12 0x18 440 #define DESC_RATE_MCS13 0x19 441 #define DESC_RATE_MCS14 0x1a 442 #define DESC_RATE_MCS15 0x1b 443 #define DESC_RATE_MCS15_SG 0x1c 444 #define DESC_RATE_MCS32 0x20 445 446 #define TXDESC_OFFSET_SZ 0 447 #define TXDESC_OFFSET_SHT 16 448 #if 0 449 #define TXDESC_BMC BIT(24) 450 #define TXDESC_LSG BIT(26) 451 #define TXDESC_FSG BIT(27) 452 #define TXDESC_OWN BIT(31) 453 #else 454 #define TXDESC_BROADMULTICAST BIT(0) 455 #define TXDESC_HTC BIT(1) 456 #define TXDESC_LAST_SEGMENT BIT(2) 457 #define TXDESC_FIRST_SEGMENT BIT(3) 458 #define TXDESC_LINIP BIT(4) 459 #define TXDESC_NO_ACM BIT(5) 460 #define TXDESC_GF BIT(6) 461 #define TXDESC_OWN BIT(7) 462 #endif 463 464 /* Word 1 */ 465 /* 466 * Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are 467 * aggregation enable and break respectively. For 8723bu, bits 0-7 are macid. 468 */ 469 #define TXDESC_PKT_OFFSET_SZ 0 470 #define TXDESC32_AGG_ENABLE BIT(5) 471 #define TXDESC32_AGG_BREAK BIT(6) 472 #define TXDESC40_MACID_SHIFT 0 473 #define TXDESC40_MACID_MASK 0x00f0 474 #define TXDESC_QUEUE_SHIFT 8 475 #define TXDESC_QUEUE_MASK 0x1f00 476 #define TXDESC_QUEUE_BK 0x2 477 #define TXDESC_QUEUE_BE 0x0 478 #define TXDESC_QUEUE_VI 0x5 479 #define TXDESC_QUEUE_VO 0x7 480 #define TXDESC_QUEUE_BEACON 0x10 481 #define TXDESC_QUEUE_HIGH 0x11 482 #define TXDESC_QUEUE_MGNT 0x12 483 #define TXDESC_QUEUE_CMD 0x13 484 #define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1) 485 #define TXDESC40_RDG_NAV_EXT BIT(13) 486 #define TXDESC40_LSIG_TXOP_ENABLE BIT(14) 487 #define TXDESC40_PIFS BIT(15) 488 489 #define DESC_RATE_ID_SHIFT 16 490 #define DESC_RATE_ID_MASK 0xf 491 #define TXDESC_NAVUSEHDR BIT(20) 492 #define TXDESC_SEC_RC4 0x00400000 493 #define TXDESC_SEC_AES 0x00c00000 494 #define TXDESC_PKT_OFFSET_SHIFT 26 495 #define TXDESC_AGG_EN BIT(29) 496 #define TXDESC_HWPC BIT(31) 497 498 /* Word 2 */ 499 #define TXDESC40_PAID_SHIFT 0 500 #define TXDESC40_PAID_MASK 0x1ff 501 #define TXDESC40_CCA_RTS_SHIFT 10 502 #define TXDESC40_CCA_RTS_MASK 0xc00 503 #define TXDESC40_AGG_ENABLE BIT(12) 504 #define TXDESC40_RDG_ENABLE BIT(13) 505 #define TXDESC40_AGG_BREAK BIT(16) 506 #define TXDESC40_MORE_FRAG BIT(17) 507 #define TXDESC40_RAW BIT(18) 508 #define TXDESC32_ACK_REPORT BIT(19) 509 #define TXDESC40_SPE_RPT BIT(19) 510 #define TXDESC_AMPDU_DENSITY_SHIFT 20 511 #define TXDESC40_BT_INT BIT(23) 512 #define TXDESC40_GID_SHIFT 24 513 #define TXDESC_ANTENNA_SELECT_A BIT(24) 514 #define TXDESC_ANTENNA_SELECT_B BIT(25) 515 516 /* Word 3 */ 517 #define TXDESC40_USE_DRIVER_RATE BIT(8) 518 #define TXDESC40_CTS_SELF_ENABLE BIT(11) 519 #define TXDESC40_RTS_CTS_ENABLE BIT(12) 520 #define TXDESC40_HW_RTS_ENABLE BIT(13) 521 #define TXDESC32_SEQ_SHIFT 16 522 #define TXDESC32_SEQ_MASK 0x0fff0000 523 524 /* Word 4 */ 525 #define TXDESC32_RTS_RATE_SHIFT 0 526 #define TXDESC32_RTS_RATE_MASK 0x3f 527 #define TXDESC32_QOS BIT(6) 528 #define TXDESC32_HW_SEQ_ENABLE BIT(7) 529 #define TXDESC32_USE_DRIVER_RATE BIT(8) 530 #define TXDESC_DISABLE_DATA_FB BIT(10) 531 #define TXDESC32_CTS_SELF_ENABLE BIT(11) 532 #define TXDESC32_RTS_CTS_ENABLE BIT(12) 533 #define TXDESC32_HW_RTS_ENABLE BIT(13) 534 #define TXDESC32_PT_STAGE_MASK GENMASK(17, 15) 535 #define TXDESC_PRIME_CH_OFF_LOWER BIT(20) 536 #define TXDESC_PRIME_CH_OFF_UPPER BIT(21) 537 #define TXDESC32_SHORT_PREAMBLE BIT(24) 538 #define TXDESC_DATA_BW BIT(25) 539 #define TXDESC_RTS_DATA_BW BIT(27) 540 #define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28) 541 #define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29) 542 #define TXDESC40_DATA_RATE_FB_SHIFT 8 543 #define TXDESC40_DATA_RATE_FB_MASK 0x00001f00 544 #define TXDESC40_RETRY_LIMIT_ENABLE BIT(17) 545 #define TXDESC40_RETRY_LIMIT_SHIFT 18 546 #define TXDESC40_RETRY_LIMIT_MASK 0x00fc0000 547 #define TXDESC40_RTS_RATE_SHIFT 24 548 #define TXDESC40_RTS_RATE_MASK 0x3f000000 549 550 /* Word 5 */ 551 #define TXDESC40_SHORT_PREAMBLE BIT(4) 552 #define TXDESC32_SHORT_GI BIT(6) 553 #define TXDESC_CCX_TAG BIT(7) 554 #define TXDESC32_RETRY_LIMIT_ENABLE BIT(17) 555 #define TXDESC32_RETRY_LIMIT_SHIFT 18 556 #define TXDESC32_RETRY_LIMIT_MASK 0x00fc0000 557 558 /* Word 6 */ 559 #define TXDESC_MAX_AGG_SHIFT 11 560 #define TXDESC_USB_TX_AGG_SHIT 24 561 562 /* Word 7 */ 563 #define TXDESC_ANTENNA_SELECT_C BIT(29) 564 565 /* Word 8 */ 566 #define TXDESC40_HW_SEQ_ENABLE BIT(15) 567 568 /* Word 9 */ 569 #define TXDESC40_SEQ_SHIFT 12 570 #define TXDESC40_SEQ_MASK 0x00fff000 571 572 struct phy_rx_agc_info { 573 #ifdef __LITTLE_ENDIAN 574 u8 gain:7, trsw:1; 575 #else 576 u8 trsw:1, gain:7; 577 #endif 578 }; 579 580 #define CCK_AGC_RPT_LNA_IDX_MASK GENMASK(7, 5) 581 #define CCK_AGC_RPT_VGA_IDX_MASK GENMASK(4, 0) 582 583 struct rtl8723au_phy_stats { 584 struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS]; 585 u8 ch_corr[RTL8723A_MAX_RF_PATHS]; 586 u8 cck_sig_qual_ofdm_pwdb_all; 587 u8 cck_agc_rpt_ofdm_cfosho_a; 588 u8 cck_rpt_b_ofdm_cfosho_b; 589 u8 reserved_1; 590 u8 noise_power_db_msb; 591 s8 path_cfotail[RTL8723A_MAX_RF_PATHS]; 592 u8 pcts_mask[RTL8723A_MAX_RF_PATHS]; 593 s8 stream_rxevm[RTL8723A_MAX_RF_PATHS]; 594 u8 path_rxsnr[RTL8723A_MAX_RF_PATHS]; 595 u8 noise_power_db_lsb; 596 u8 reserved_2[3]; 597 u8 stream_csi[RTL8723A_MAX_RF_PATHS]; 598 u8 stream_target_csi[RTL8723A_MAX_RF_PATHS]; 599 s8 sig_evm; 600 u8 reserved_3; 601 602 #ifdef __LITTLE_ENDIAN 603 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 604 u8 sgi_en:1; 605 u8 rxsc:2; 606 u8 idle_long:1; 607 u8 r_ant_train_en:1; 608 u8 antenna_select_b:1; 609 u8 antenna_select:1; 610 #else /* _BIG_ENDIAN_ */ 611 u8 antenna_select:1; 612 u8 antenna_select_b:1; 613 u8 r_ant_train_en:1; 614 u8 idle_long:1; 615 u8 rxsc:2; 616 u8 sgi_en:1; 617 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 618 #endif 619 }; 620 621 /* 622 * Regs to backup 623 */ 624 #define RTL8XXXU_ADDA_REGS 16 625 #define RTL8XXXU_MAC_REGS 4 626 #define RTL8XXXU_BB_REGS 9 627 628 struct rtl8xxxu_firmware_header { 629 __le16 signature; /* 92C0: test chip; 92C, 630 88C0: test chip; 631 88C1: MP A-cut; 632 92C1: MP A-cut */ 633 u8 category; /* AP/NIC and USB/PCI */ 634 u8 function; 635 636 __le16 major_version; /* FW Version */ 637 u8 minor_version; /* FW Subversion, default 0x00 */ 638 u8 reserved1; 639 640 u8 month; /* Release time Month field */ 641 u8 date; /* Release time Date field */ 642 u8 hour; /* Release time Hour field */ 643 u8 minute; /* Release time Minute field */ 644 645 __le16 ramcodesize; /* Size of RAM code */ 646 u16 reserved2; 647 648 __le32 svn_idx; /* SVN entry index */ 649 u32 reserved3; 650 651 u32 reserved4; 652 u32 reserved5; 653 654 u8 data[]; 655 }; 656 657 /* 658 * 8723au/8192cu/8188ru required base power index offset tables. 659 */ 660 struct rtl8xxxu_power_base { 661 u32 reg_0e00; 662 u32 reg_0e04; 663 u32 reg_0e08; 664 u32 reg_086c; 665 666 u32 reg_0e10; 667 u32 reg_0e14; 668 u32 reg_0e18; 669 u32 reg_0e1c; 670 671 u32 reg_0830; 672 u32 reg_0834; 673 u32 reg_0838; 674 u32 reg_086c_2; 675 676 u32 reg_083c; 677 u32 reg_0848; 678 u32 reg_084c; 679 u32 reg_0868; 680 }; 681 682 /* 683 * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14 684 */ 685 struct rtl8723au_idx { 686 #ifdef __LITTLE_ENDIAN 687 int a:4; 688 int b:4; 689 #else 690 int b:4; 691 int a:4; 692 #endif 693 } __attribute__((packed)); 694 695 struct rtl8723au_efuse { 696 __le16 rtl_id; 697 u8 res0[0xe]; 698 u8 cck_tx_power_index_A[3]; /* 0x10 */ 699 u8 cck_tx_power_index_B[3]; 700 u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */ 701 u8 ht40_1s_tx_power_index_B[3]; 702 /* 703 * The following entries are half-bytes split as: 704 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 705 */ 706 struct rtl8723au_idx ht20_tx_power_index_diff[3]; 707 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 708 struct rtl8723au_idx ht40_max_power_offset[3]; 709 struct rtl8723au_idx ht20_max_power_offset[3]; 710 u8 channel_plan; /* 0x28 */ 711 u8 tssi_a; 712 u8 thermal_meter; 713 u8 rf_regulatory; 714 u8 rf_option_2; 715 u8 rf_option_3; 716 u8 rf_option_4; 717 u8 res7; 718 u8 version /* 0x30 */; 719 u8 customer_id_major; 720 u8 customer_id_minor; 721 u8 xtal_k; 722 u8 chipset; /* 0x34 */ 723 u8 res8[0x82]; 724 u8 vid; /* 0xb7 */ 725 u8 res9; 726 u8 pid; /* 0xb9 */ 727 u8 res10[0x0c]; 728 u8 mac_addr[ETH_ALEN]; /* 0xc6 */ 729 u8 res11[2]; 730 u8 vendor_name[7]; 731 u8 res12[2]; 732 u8 device_name[0x29]; /* 0xd7 */ 733 }; 734 735 struct rtl8192cu_efuse { 736 __le16 rtl_id; 737 __le16 hpon; 738 u8 res0[2]; 739 __le16 clk; 740 __le16 testr; 741 __le16 vid; 742 __le16 did; 743 __le16 svid; 744 __le16 smid; /* 0x10 */ 745 u8 res1[4]; 746 u8 mac_addr[ETH_ALEN]; /* 0x16 */ 747 u8 res2[2]; 748 u8 vendor_name[7]; 749 u8 res3[3]; 750 u8 device_name[0x14]; /* 0x28 */ 751 u8 res4[0x1e]; /* 0x3c */ 752 u8 cck_tx_power_index_A[3]; /* 0x5a */ 753 u8 cck_tx_power_index_B[3]; 754 u8 ht40_1s_tx_power_index_A[3]; /* 0x60 */ 755 u8 ht40_1s_tx_power_index_B[3]; 756 /* 757 * The following entries are half-bytes split as: 758 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 759 */ 760 struct rtl8723au_idx ht40_2s_tx_power_index_diff[3]; 761 struct rtl8723au_idx ht20_tx_power_index_diff[3]; /* 0x69 */ 762 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 763 struct rtl8723au_idx ht40_max_power_offset[3]; /* 0x6f */ 764 struct rtl8723au_idx ht20_max_power_offset[3]; 765 u8 channel_plan; /* 0x75 */ 766 u8 tssi_a; 767 u8 tssi_b; 768 u8 thermal_meter; /* xtal_k */ /* 0x78 */ 769 u8 rf_regulatory; 770 u8 rf_option_2; 771 u8 rf_option_3; 772 u8 rf_option_4; 773 u8 res5[1]; /* 0x7d */ 774 u8 version; 775 u8 customer_id; 776 }; 777 778 struct rtl8723bu_pwr_idx { 779 #ifdef __LITTLE_ENDIAN 780 int ht20:4; 781 int ht40:4; 782 int ofdm:4; 783 int cck:4; 784 #else 785 int cck:4; 786 int ofdm:4; 787 int ht40:4; 788 int ht20:4; 789 #endif 790 } __attribute__((packed)); 791 792 struct rtl8723bu_efuse_tx_power { 793 u8 cck_base[6]; 794 u8 ht40_base[5]; 795 struct rtl8723au_idx ht20_ofdm_1s_diff; 796 struct rtl8723bu_pwr_idx pwr_diff[3]; 797 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ 798 }; 799 800 struct rtl8723bu_efuse { 801 __le16 rtl_id; 802 u8 res0[0x0e]; 803 struct rtl8723bu_efuse_tx_power tx_power_index_A; /* 0x10 */ 804 struct rtl8723bu_efuse_tx_power tx_power_index_B; /* 0x3a */ 805 struct rtl8723bu_efuse_tx_power tx_power_index_C; /* 0x64 */ 806 struct rtl8723bu_efuse_tx_power tx_power_index_D; /* 0x8e */ 807 u8 channel_plan; /* 0xb8 */ 808 u8 xtal_k; 809 u8 thermal_meter; 810 u8 iqk_lck; 811 u8 pa_type; /* 0xbc */ 812 u8 lna_type_2g; /* 0xbd */ 813 u8 res2[3]; 814 u8 rf_board_option; 815 u8 rf_feature_option; 816 u8 rf_bt_setting; 817 u8 eeprom_version; 818 u8 eeprom_customer_id; 819 u8 res3[2]; 820 u8 tx_pwr_calibrate_rate; 821 u8 rf_antenna_option; /* 0xc9 */ 822 u8 rfe_option; 823 u8 res4[9]; 824 u8 usb_optional_function; 825 u8 res5[0x1e]; 826 u8 res6[2]; 827 u8 serial[0x0b]; /* 0xf5 */ 828 u8 vid; /* 0x100 */ 829 u8 res7; 830 u8 pid; 831 u8 res8[4]; 832 u8 mac_addr[ETH_ALEN]; /* 0x107 */ 833 u8 res9[2]; 834 u8 vendor_name[0x07]; 835 u8 res10[2]; 836 u8 device_name[0x14]; 837 u8 res11[0xcf]; 838 u8 package_type; /* 0x1fb */ 839 u8 res12[0x4]; 840 }; 841 842 struct rtl8192eu_efuse_tx_power { 843 u8 cck_base[6]; 844 u8 ht40_base[5]; 845 struct rtl8723au_idx ht20_ofdm_1s_diff; 846 struct rtl8723bu_pwr_idx pwr_diff[3]; 847 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ 848 }; 849 850 struct rtl8192eu_efuse { 851 __le16 rtl_id; 852 u8 res0[0x0e]; 853 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 854 struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x3a */ 855 u8 res2[0x54]; 856 u8 channel_plan; /* 0xb8 */ 857 u8 xtal_k; 858 u8 thermal_meter; 859 u8 iqk_lck; 860 u8 pa_type; /* 0xbc */ 861 u8 lna_type_2g; /* 0xbd */ 862 u8 res3[1]; 863 u8 lna_type_5g; /* 0xbf */ 864 u8 res4[1]; 865 u8 rf_board_option; 866 u8 rf_feature_option; 867 u8 rf_bt_setting; 868 u8 eeprom_version; 869 u8 eeprom_customer_id; 870 u8 res5[3]; 871 u8 rf_antenna_option; /* 0xc9 */ 872 u8 res6[6]; 873 u8 vid; /* 0xd0 */ 874 u8 res7[1]; 875 u8 pid; /* 0xd2 */ 876 u8 res8[1]; 877 u8 usb_optional_function; 878 u8 res9[2]; 879 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 880 u8 device_info[80]; 881 u8 res11[3]; 882 u8 unknown[0x0d]; /* 0x130 */ 883 u8 res12[0xc3]; 884 }; 885 886 struct rtl8188fu_efuse_tx_power { 887 u8 cck_base[6]; 888 u8 ht40_base[5]; 889 /* a: ofdm; b: ht20 */ 890 struct rtl8723au_idx ht20_ofdm_1s_diff; 891 }; 892 893 struct rtl8188fu_efuse { 894 __le16 rtl_id; 895 u8 res0[0x0e]; 896 struct rtl8188fu_efuse_tx_power tx_power_index_A; /* 0x10 */ 897 u8 res1[0x9c]; /* 0x1c */ 898 u8 channel_plan; /* 0xb8 */ 899 u8 xtal_k; 900 u8 thermal_meter; 901 u8 iqk_lck; 902 u8 res2[5]; 903 u8 rf_board_option; 904 u8 rf_feature_option; 905 u8 rf_bt_setting; 906 u8 eeprom_version; 907 u8 eeprom_customer_id; 908 u8 res3[2]; 909 u8 kfree_thermal_k_on; 910 u8 rf_antenna_option; /* 0xc9 */ 911 u8 rfe_option; 912 u8 country_code; 913 u8 res4[4]; 914 u8 vid; /* 0xd0 */ 915 u8 res5[1]; 916 u8 pid; /* 0xd2 */ 917 u8 res6[1]; 918 u8 usb_optional_function; 919 u8 res7[2]; 920 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 921 u8 res8[2]; 922 u8 vendor_name[7]; 923 u8 res9[2]; 924 u8 device_name[7]; /* 0xe8 */ 925 u8 res10[0x41]; 926 u8 unknown[0x0d]; /* 0x130 */ 927 u8 res11[0xc3]; 928 }; 929 930 struct rtl8188eu_efuse { 931 __le16 rtl_id; 932 u8 res0[0x0e]; 933 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 934 u8 res1[0x7e]; /* 0x3a */ 935 u8 channel_plan; /* 0xb8 */ 936 u8 xtal_k; 937 u8 thermal_meter; 938 u8 iqk_lck; 939 u8 res2[5]; 940 u8 rf_board_option; 941 u8 rf_feature_option; 942 u8 rf_bt_setting; 943 u8 eeprom_version; 944 u8 eeprom_customer_id; 945 u8 res3[3]; 946 u8 rf_antenna_option; /* 0xc9 */ 947 u8 res4[6]; 948 u8 vid; /* 0xd0 */ 949 u8 res5[1]; 950 u8 pid; /* 0xd2 */ 951 u8 res6[1]; 952 u8 usb_optional_function; 953 u8 res7[2]; 954 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 955 u8 res8[2]; 956 u8 vendor_name[7]; 957 u8 res9[2]; 958 u8 device_name[0x0b]; /* 0xe8 */ 959 u8 res10[2]; 960 u8 serial[0x0b]; /* 0xf5 */ 961 u8 res11[0x30]; 962 u8 unknown[0x0d]; /* 0x130 */ 963 u8 res12[0xc3]; 964 } __packed; 965 966 struct rtl8xxxu_reg8val { 967 u16 reg; 968 u8 val; 969 }; 970 971 struct rtl8xxxu_reg32val { 972 u16 reg; 973 u32 val; 974 }; 975 976 struct rtl8xxxu_rfregval { 977 u8 reg; 978 u32 val; 979 }; 980 981 enum rtl8xxxu_rfpath { 982 RF_A = 0, 983 RF_B = 1, 984 }; 985 986 struct rtl8xxxu_rfregs { 987 u16 hssiparm1; 988 u16 hssiparm2; 989 u16 lssiparm; 990 u16 hspiread; 991 u16 lssiread; 992 u16 rf_sw_ctrl; 993 }; 994 995 #define H2C_MAX_MBOX 4 996 #define H2C_EXT BIT(7) 997 #define H2C_JOIN_BSS_DISCONNECT 0 998 #define H2C_JOIN_BSS_CONNECT 1 999 1000 /* 1001 * H2C (firmware) commands differ between the older generation chips 1002 * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu, 1003 * 8192[de]u, 8192eu, and 8812. 1004 */ 1005 enum h2c_cmd_8723a { 1006 H2C_SET_POWER_MODE = 1, 1007 H2C_JOIN_BSS_REPORT = 2, 1008 H2C_SET_RSSI = 5, 1009 H2C_SET_RATE_MASK = (6 | H2C_EXT), 1010 }; 1011 1012 enum h2c_cmd_8723b { 1013 /* 1014 * Common Class: 000 1015 */ 1016 H2C_8723B_RSVD_PAGE = 0x00, 1017 H2C_8723B_MEDIA_STATUS_RPT = 0x01, 1018 H2C_8723B_SCAN_ENABLE = 0x02, 1019 H2C_8723B_KEEP_ALIVE = 0x03, 1020 H2C_8723B_DISCON_DECISION = 0x04, 1021 H2C_8723B_PSD_OFFLOAD = 0x05, 1022 H2C_8723B_AP_OFFLOAD = 0x08, 1023 H2C_8723B_BCN_RSVDPAGE = 0x09, 1024 H2C_8723B_PROBERSP_RSVDPAGE = 0x0A, 1025 H2C_8723B_FCS_RSVDPAGE = 0x10, 1026 H2C_8723B_FCS_INFO = 0x11, 1027 H2C_8723B_AP_WOW_GPIO_CTRL = 0x13, 1028 1029 /* 1030 * PoweSave Class: 001 1031 */ 1032 H2C_8723B_SET_PWR_MODE = 0x20, 1033 H2C_8723B_PS_TUNING_PARA = 0x21, 1034 H2C_8723B_PS_TUNING_PARA2 = 0x22, 1035 H2C_8723B_P2P_LPS_PARAM = 0x23, 1036 H2C_8723B_P2P_PS_OFFLOAD = 0x24, 1037 H2C_8723B_PS_SCAN_ENABLE = 0x25, 1038 H2C_8723B_SAP_PS_ = 0x26, 1039 H2C_8723B_INACTIVE_PS_ = 0x27, 1040 H2C_8723B_FWLPS_IN_IPS_ = 0x28, 1041 1042 /* 1043 * Dynamic Mechanism Class: 010 1044 */ 1045 H2C_8723B_MACID_CFG_RAID = 0x40, 1046 H2C_8723B_TXBF = 0x41, 1047 H2C_8723B_RSSI_SETTING = 0x42, 1048 H2C_8723B_AP_REQ_TXRPT = 0x43, 1049 H2C_8723B_INIT_RATE_COLLECT = 0x44, 1050 1051 /* 1052 * BT Class: 011 1053 */ 1054 H2C_8723B_B_TYPE_TDMA = 0x60, 1055 H2C_8723B_BT_INFO = 0x61, 1056 H2C_8723B_FORCE_BT_TXPWR = 0x62, 1057 H2C_8723B_BT_IGNORE_WLANACT = 0x63, 1058 H2C_8723B_DAC_SWING_VALUE = 0x64, 1059 H2C_8723B_ANT_SEL_RSV = 0x65, 1060 H2C_8723B_WL_OPMODE = 0x66, 1061 H2C_8723B_BT_MP_OPER = 0x67, 1062 H2C_8723B_BT_CONTROL = 0x68, 1063 H2C_8723B_BT_WIFI_CTRL = 0x69, 1064 H2C_8723B_BT_FW_PATCH = 0x6a, 1065 H2C_8723B_BT_WLAN_CALIBRATION = 0x6d, 1066 H2C_8723B_BT_GRANT = 0x6e, 1067 1068 /* 1069 * WOWLAN Class: 100 1070 */ 1071 H2C_8723B_WOWLAN = 0x80, 1072 H2C_8723B_REMOTE_WAKE_CTRL = 0x81, 1073 H2C_8723B_AOAC_GLOBAL_INFO = 0x82, 1074 H2C_8723B_AOAC_RSVD_PAGE = 0x83, 1075 H2C_8723B_AOAC_RSVD_PAGE2 = 0x84, 1076 H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85, 1077 H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86, 1078 H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87, 1079 1080 H2C_8723B_RESET_TSF = 0xC0, 1081 }; 1082 1083 1084 struct h2c_cmd { 1085 union { 1086 struct { 1087 u8 cmd; 1088 u8 data[7]; 1089 } __packed cmd; 1090 struct { 1091 __le32 data; 1092 __le16 ext; 1093 } __packed raw; 1094 struct { 1095 __le32 data; 1096 __le32 ext; 1097 } __packed raw_wide; 1098 struct { 1099 u8 cmd; 1100 u8 data; 1101 } __packed joinbss; 1102 struct { 1103 u8 cmd; 1104 __le16 mask_hi; 1105 u8 arg; 1106 __le16 mask_lo; 1107 } __packed ramask; 1108 struct { 1109 u8 cmd; 1110 u8 parm; 1111 u8 macid; 1112 u8 macid_end; 1113 } __packed media_status_rpt; 1114 struct { 1115 u8 cmd; 1116 u8 macid; 1117 /* 1118 * [0:4] - RAID 1119 * [7] - SGI 1120 */ 1121 u8 data1; 1122 /* 1123 * [0:1] - Bandwidth 1124 * [3] - No Update 1125 * [4:5] - VHT enable 1126 * [6] - DISPT 1127 * [7] - DISRA 1128 */ 1129 u8 data2; 1130 u8 ramask0; 1131 u8 ramask1; 1132 u8 ramask2; 1133 u8 ramask3; 1134 } __packed b_macid_cfg; 1135 struct { 1136 u8 cmd; 1137 u8 data1; 1138 u8 data2; 1139 u8 data3; 1140 u8 data4; 1141 u8 data5; 1142 } __packed b_type_dma; 1143 struct { 1144 u8 cmd; 1145 u8 data; 1146 } __packed bt_info; 1147 struct { 1148 u8 cmd; 1149 u8 operreq; 1150 u8 opcode; 1151 u8 data; 1152 u8 addr; 1153 } __packed bt_mp_oper; 1154 struct { 1155 u8 cmd; 1156 u8 data; 1157 } __packed bt_wlan_calibration; 1158 struct { 1159 u8 cmd; 1160 u8 data; 1161 } __packed ignore_wlan; 1162 struct { 1163 u8 cmd; 1164 u8 ant_inverse; 1165 u8 int_switch_type; 1166 } __packed ant_sel_rsv; 1167 struct { 1168 u8 cmd; 1169 u8 data; 1170 } __packed bt_grant; 1171 struct { 1172 u8 cmd; 1173 u8 macid; 1174 u8 unknown0; 1175 u8 rssi; 1176 /* 1177 * [0] - is_rx 1178 * [1] - stbc_en 1179 * [2] - noisy_decision 1180 * [6] - bf_en 1181 */ 1182 u8 data; 1183 /* 1184 * [0:6] - ra_th_offset 1185 * [7] - ra_offset_direction 1186 */ 1187 u8 ra_th_offset; 1188 u8 unknown1; 1189 u8 unknown2; 1190 } __packed rssi_report; 1191 }; 1192 }; 1193 1194 enum c2h_evt_8723b { 1195 C2H_8723B_DEBUG = 0, 1196 C2H_8723B_TSF = 1, 1197 C2H_8723B_AP_RPT_RSP = 2, 1198 C2H_8723B_CCX_TX_RPT = 3, 1199 C2H_8723B_BT_RSSI = 4, 1200 C2H_8723B_BT_OP_MODE = 5, 1201 C2H_8723B_EXT_RA_RPT = 6, 1202 C2H_8723B_BT_INFO = 9, 1203 C2H_8723B_HW_INFO_EXCH = 0x0a, 1204 C2H_8723B_BT_MP_INFO = 0x0b, 1205 C2H_8723B_RA_REPORT = 0x0c, 1206 C2H_8723B_FW_DEBUG = 0xff, 1207 }; 1208 1209 enum bt_info_src_8723b { 1210 BT_INFO_SRC_8723B_WIFI_FW = 0x0, 1211 BT_INFO_SRC_8723B_BT_RSP = 0x1, 1212 BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2, 1213 }; 1214 1215 enum bt_mp_oper_opcode_8723b { 1216 BT_MP_OP_GET_BT_VERSION = 0x00, 1217 BT_MP_OP_RESET = 0x01, 1218 BT_MP_OP_TEST_CTRL = 0x02, 1219 BT_MP_OP_SET_BT_MODE = 0x03, 1220 BT_MP_OP_SET_CHNL_TX_GAIN = 0x04, 1221 BT_MP_OP_SET_PKT_TYPE_LEN = 0x05, 1222 BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06, 1223 BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07, 1224 BT_MP_OP_SET_PKT_HEADER = 0x08, 1225 BT_MP_OP_SET_WHITENCOEFF = 0x09, 1226 BT_MP_OP_SET_BD_ADDR_L = 0x0a, 1227 BT_MP_OP_SET_BD_ADDR_H = 0x0b, 1228 BT_MP_OP_WRITE_REG_ADDR = 0x0c, 1229 BT_MP_OP_WRITE_REG_VALUE = 0x0d, 1230 BT_MP_OP_GET_BT_STATUS = 0x0e, 1231 BT_MP_OP_GET_BD_ADDR_L = 0x0f, 1232 BT_MP_OP_GET_BD_ADDR_H = 0x10, 1233 BT_MP_OP_READ_REG = 0x11, 1234 BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12, 1235 BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13, 1236 BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14, 1237 BT_MP_OP_GET_RX_PKT_CNT_L = 0x15, 1238 BT_MP_OP_GET_RX_PKT_CNT_H = 0x16, 1239 BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17, 1240 BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18, 1241 BT_MP_OP_GET_RSSI = 0x19, 1242 BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a, 1243 BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b, 1244 BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c, 1245 BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d, 1246 BT_MP_OP_GET_AFH_MAP_L = 0x1e, 1247 BT_MP_OP_GET_AFH_MAP_M = 0x1f, 1248 BT_MP_OP_GET_AFH_MAP_H = 0x20, 1249 BT_MP_OP_GET_AFH_STATUS = 0x21, 1250 BT_MP_OP_SET_TRACKING_INTERVAL = 0x22, 1251 BT_MP_OP_SET_THERMAL_METER = 0x23, 1252 BT_MP_OP_ENABLE_CFO_TRACKING = 0x24, 1253 }; 1254 1255 enum rtl8xxxu_bw_mode { 1256 RTL8XXXU_CHANNEL_WIDTH_20 = 0, 1257 RTL8XXXU_CHANNEL_WIDTH_40 = 1, 1258 RTL8XXXU_CHANNEL_WIDTH_80 = 2, 1259 RTL8XXXU_CHANNEL_WIDTH_160 = 3, 1260 RTL8XXXU_CHANNEL_WIDTH_80_80 = 4, 1261 RTL8XXXU_CHANNEL_WIDTH_MAX = 5, 1262 }; 1263 1264 struct rtl8723bu_c2h { 1265 u8 id; 1266 u8 seq; 1267 union { 1268 struct { 1269 u8 payload[0]; 1270 } __packed raw; 1271 struct { 1272 u8 ext_id; 1273 u8 status:4; 1274 u8 retlen:4; 1275 u8 opcode_ver:4; 1276 u8 req_num:4; 1277 u8 payload[2]; 1278 } __packed bt_mp_info; 1279 struct { 1280 u8 response_source:4; 1281 u8 dummy0_0:4; 1282 1283 u8 bt_info; 1284 1285 u8 retry_count:4; 1286 u8 dummy2_0:1; 1287 u8 bt_page:1; 1288 u8 tx_rx_mask:1; 1289 u8 dummy2_2:1; 1290 1291 u8 rssi; 1292 1293 u8 basic_rate:1; 1294 u8 bt_has_reset:1; 1295 u8 dummy4_1:1; 1296 u8 ignore_wlan:1; 1297 u8 auto_report:1; 1298 u8 dummy4_2:3; 1299 1300 u8 a4; 1301 u8 a5; 1302 } __packed bt_info; 1303 struct { 1304 u8 rate:7; 1305 u8 sgi:1; 1306 u8 macid; 1307 u8 ldpc:1; 1308 u8 txbf:1; 1309 u8 noisy_state:1; 1310 u8 dummy2_0:5; 1311 u8 dummy3_0; 1312 u8 dummy4_0; 1313 u8 dummy5_0; 1314 u8 bw; 1315 } __packed ra_report; 1316 }; 1317 } __packed; 1318 1319 struct rtl8xxxu_fileops; 1320 1321 /*mlme related.*/ 1322 enum wireless_mode { 1323 WIRELESS_MODE_UNKNOWN = 0, 1324 /* Sub-Element */ 1325 WIRELESS_MODE_B = BIT(0), 1326 WIRELESS_MODE_G = BIT(1), 1327 WIRELESS_MODE_A = BIT(2), 1328 WIRELESS_MODE_N_24G = BIT(3), 1329 WIRELESS_MODE_N_5G = BIT(4), 1330 WIRELESS_AUTO = BIT(5), 1331 WIRELESS_MODE_AC = BIT(6), 1332 WIRELESS_MODE_MAX = 0x7F, 1333 }; 1334 1335 /* from rtlwifi/wifi.h */ 1336 enum ratr_table_mode_new { 1337 RATEID_IDX_BGN_40M_2SS = 0, 1338 RATEID_IDX_BGN_40M_1SS = 1, 1339 RATEID_IDX_BGN_20M_2SS_BN = 2, 1340 RATEID_IDX_BGN_20M_1SS_BN = 3, 1341 RATEID_IDX_GN_N2SS = 4, 1342 RATEID_IDX_GN_N1SS = 5, 1343 RATEID_IDX_BG = 6, 1344 RATEID_IDX_G = 7, 1345 RATEID_IDX_B = 8, 1346 RATEID_IDX_VHT_2SS = 9, 1347 RATEID_IDX_VHT_1SS = 10, 1348 RATEID_IDX_MIX1 = 11, 1349 RATEID_IDX_MIX2 = 12, 1350 RATEID_IDX_VHT_3SS = 13, 1351 RATEID_IDX_BGN_3SS = 14, 1352 }; 1353 1354 #define BT_INFO_8723B_1ANT_B_FTP BIT(7) 1355 #define BT_INFO_8723B_1ANT_B_A2DP BIT(6) 1356 #define BT_INFO_8723B_1ANT_B_HID BIT(5) 1357 #define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT(4) 1358 #define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT(3) 1359 #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT(2) 1360 #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT(1) 1361 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT(0) 1362 1363 enum _BT_8723B_1ANT_STATUS { 1364 BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE = 0x0, 1365 BT_8723B_1ANT_STATUS_CONNECTED_IDLE = 0x1, 1366 BT_8723B_1ANT_STATUS_INQ_PAGE = 0x2, 1367 BT_8723B_1ANT_STATUS_ACL_BUSY = 0x3, 1368 BT_8723B_1ANT_STATUS_SCO_BUSY = 0x4, 1369 BT_8723B_1ANT_STATUS_ACL_SCO_BUSY = 0x5, 1370 BT_8723B_1ANT_STATUS_MAX 1371 }; 1372 1373 struct rtl8xxxu_btcoex { 1374 u8 bt_status; 1375 bool bt_busy; 1376 bool has_sco; 1377 bool has_a2dp; 1378 bool has_hid; 1379 bool has_pan; 1380 bool hid_only; 1381 bool a2dp_only; 1382 bool c2h_bt_inquiry; 1383 }; 1384 1385 #define RTL8XXXU_RATR_STA_INIT 0 1386 #define RTL8XXXU_RATR_STA_HIGH 1 1387 #define RTL8XXXU_RATR_STA_MID 2 1388 #define RTL8XXXU_RATR_STA_LOW 3 1389 1390 #define RTL8XXXU_NOISE_FLOOR_MIN -100 1391 #define RTL8XXXU_SNR_THRESH_HIGH 50 1392 #define RTL8XXXU_SNR_THRESH_LOW 20 1393 1394 struct rtl8xxxu_ra_report { 1395 struct rate_info txrate; 1396 u32 bit_rate; 1397 u8 desc_rate; 1398 }; 1399 1400 struct rtl8xxxu_ra_info { 1401 u8 rate_id; 1402 u32 rate_mask; 1403 u32 ra_use_rate; 1404 u8 rate_sgi; 1405 u8 rssi_sta_ra; /* Percentage */ 1406 u8 pre_rssi_sta_ra; 1407 u8 sgi_enable; 1408 u8 decision_rate; 1409 u8 pre_rate; 1410 u8 highest_rate; 1411 u8 lowest_rate; 1412 u32 nsc_up; 1413 u32 nsc_down; 1414 u32 total; 1415 u16 retry[5]; 1416 u16 drop; 1417 u16 rpt_time; 1418 u16 pre_min_rpt_time; 1419 u8 dynamic_tx_rpt_timing_counter; 1420 u8 ra_waiting_counter; 1421 u8 ra_pending_counter; 1422 u8 ra_drop_after_down; 1423 u8 pt_try_state; /* 0 trying state, 1 for decision state */ 1424 u8 pt_stage; /* 0~6 */ 1425 u8 pt_stop_count; /* Stop PT counter */ 1426 u8 pt_pre_rate; /* if rate change do PT */ 1427 u8 pt_pre_rssi; /* if RSSI change 5% do PT */ 1428 u8 pt_mode_ss; /* decide which rate should do PT */ 1429 u8 ra_stage; /* StageRA, decide how many times RA will be done between PT */ 1430 u8 pt_smooth_factor; 1431 }; 1432 1433 #define CFO_TH_XTAL_HIGH 20 /* kHz */ 1434 #define CFO_TH_XTAL_LOW 10 /* kHz */ 1435 #define CFO_TH_ATC 80 /* kHz */ 1436 1437 struct rtl8xxxu_cfo_tracking { 1438 bool adjust; 1439 bool atc_status; 1440 int cfo_tail[2]; 1441 u8 crystal_cap; 1442 u32 packet_count; 1443 u32 packet_count_pre; 1444 }; 1445 1446 #define RTL8XXXU_HW_LED_CONTROL 2 1447 1448 struct rtl8xxxu_priv { 1449 struct ieee80211_hw *hw; 1450 struct usb_device *udev; 1451 struct rtl8xxxu_fileops *fops; 1452 1453 spinlock_t tx_urb_lock; 1454 struct list_head tx_urb_free_list; 1455 int tx_urb_free_count; 1456 bool tx_stopped; 1457 1458 spinlock_t rx_urb_lock; 1459 struct list_head rx_urb_pending_list; 1460 int rx_urb_pending_count; 1461 bool shutdown; 1462 struct work_struct rx_urb_wq; 1463 1464 u8 mac_addr[ETH_ALEN]; 1465 char chip_name[8]; 1466 char chip_vendor[8]; 1467 u8 cck_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1468 u8 cck_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1469 u8 ht40_1s_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1470 u8 ht40_1s_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1471 /* 1472 * The following entries are half-bytes split as: 1473 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 1474 */ 1475 struct rtl8723au_idx ht40_2s_tx_power_index_diff[ 1476 RTL8723A_CHANNEL_GROUPS]; 1477 struct rtl8723au_idx ht20_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1478 struct rtl8723au_idx ofdm_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1479 struct rtl8723au_idx ht40_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1480 struct rtl8723au_idx ht20_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1481 /* 1482 * Newer generation chips only keep power diffs per TX count, 1483 * not per channel group. 1484 */ 1485 struct rtl8723au_idx ofdm_tx_power_diff[RTL8723B_TX_COUNT]; 1486 struct rtl8723au_idx ht20_tx_power_diff[RTL8723B_TX_COUNT]; 1487 struct rtl8723au_idx ht40_tx_power_diff[RTL8723B_TX_COUNT]; 1488 struct rtl8xxxu_power_base *power_base; 1489 u32 chip_cut:4; 1490 u32 rom_rev:4; 1491 u32 is_multi_func:1; 1492 u32 has_wifi:1; 1493 u32 has_bluetooth:1; 1494 u32 enable_bluetooth:1; 1495 u32 has_gps:1; 1496 u32 hi_pa:1; 1497 u32 vendor_umc:1; 1498 u32 vendor_smic:1; 1499 u32 has_polarity_ctrl:1; 1500 u32 has_eeprom:1; 1501 u32 boot_eeprom:1; 1502 u32 usb_interrupts:1; 1503 u32 ep_tx_high_queue:1; 1504 u32 ep_tx_normal_queue:1; 1505 u32 ep_tx_low_queue:1; 1506 u32 rx_buf_aggregation:1; 1507 u32 cck_agc_report_type:1; 1508 u8 default_crystal_cap; 1509 unsigned int pipe_interrupt; 1510 unsigned int pipe_in; 1511 unsigned int pipe_out[TXDESC_QUEUE_MAX]; 1512 u8 out_ep[RTL8XXXU_OUT_ENDPOINTS]; 1513 u8 ep_tx_count; 1514 u8 rf_paths; 1515 u8 rx_paths; 1516 u8 tx_paths; 1517 u32 rege94; 1518 u32 rege9c; 1519 u32 regeb4; 1520 u32 regebc; 1521 int next_mbox; 1522 int nr_out_eps; 1523 1524 struct mutex h2c_mutex; 1525 1526 struct usb_anchor rx_anchor; 1527 struct usb_anchor tx_anchor; 1528 struct usb_anchor int_anchor; 1529 struct rtl8xxxu_firmware_header *fw_data; 1530 size_t fw_size; 1531 struct mutex usb_buf_mutex; 1532 union { 1533 __le32 val32; 1534 __le16 val16; 1535 u8 val8; 1536 } usb_buf; 1537 union { 1538 u8 raw[EFUSE_MAP_LEN]; 1539 struct rtl8723au_efuse efuse8723; 1540 struct rtl8723bu_efuse efuse8723bu; 1541 struct rtl8192cu_efuse efuse8192; 1542 struct rtl8192eu_efuse efuse8192eu; 1543 struct rtl8188fu_efuse efuse8188fu; 1544 struct rtl8188eu_efuse efuse8188eu; 1545 } efuse_wifi; 1546 u32 adda_backup[RTL8XXXU_ADDA_REGS]; 1547 u32 mac_backup[RTL8XXXU_MAC_REGS]; 1548 u32 bb_backup[RTL8XXXU_BB_REGS]; 1549 u32 bb_recovery_backup[RTL8XXXU_BB_REGS]; 1550 enum rtl8xxxu_rtl_chip rtl_chip; 1551 u8 pi_enabled:1; 1552 u8 no_pape:1; 1553 u8 int_buf[USB_INTR_CONTENT_LENGTH]; 1554 u8 rssi_level; 1555 DECLARE_BITMAP(tx_aggr_started, IEEE80211_NUM_TIDS); 1556 DECLARE_BITMAP(tid_tx_operational, IEEE80211_NUM_TIDS); 1557 /* 1558 * Only one virtual interface permitted because only STA mode 1559 * is supported and no iface_combinations are provided. 1560 */ 1561 struct ieee80211_vif *vif; 1562 struct delayed_work ra_watchdog; 1563 struct work_struct c2hcmd_work; 1564 struct sk_buff_head c2hcmd_queue; 1565 struct rtl8xxxu_btcoex bt_coex; 1566 struct rtl8xxxu_ra_report ra_report; 1567 struct rtl8xxxu_cfo_tracking cfo_tracking; 1568 struct rtl8xxxu_ra_info ra_info; 1569 1570 bool led_registered; 1571 char led_name[32]; 1572 struct led_classdev led_cdev; 1573 }; 1574 1575 struct rtl8xxxu_rx_urb { 1576 struct urb urb; 1577 struct ieee80211_hw *hw; 1578 struct list_head list; 1579 }; 1580 1581 struct rtl8xxxu_tx_urb { 1582 struct urb urb; 1583 struct ieee80211_hw *hw; 1584 struct list_head list; 1585 }; 1586 1587 struct rtl8xxxu_fileops { 1588 int (*identify_chip) (struct rtl8xxxu_priv *priv); 1589 int (*parse_efuse) (struct rtl8xxxu_priv *priv); 1590 int (*load_firmware) (struct rtl8xxxu_priv *priv); 1591 int (*power_on) (struct rtl8xxxu_priv *priv); 1592 void (*power_off) (struct rtl8xxxu_priv *priv); 1593 void (*reset_8051) (struct rtl8xxxu_priv *priv); 1594 int (*llt_init) (struct rtl8xxxu_priv *priv); 1595 void (*init_phy_bb) (struct rtl8xxxu_priv *priv); 1596 int (*init_phy_rf) (struct rtl8xxxu_priv *priv); 1597 void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv); 1598 void (*phy_lc_calibrate) (struct rtl8xxxu_priv *priv); 1599 void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv); 1600 void (*config_channel) (struct ieee80211_hw *hw); 1601 int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb); 1602 void (*init_aggregation) (struct rtl8xxxu_priv *priv); 1603 void (*init_statistics) (struct rtl8xxxu_priv *priv); 1604 void (*init_burst) (struct rtl8xxxu_priv *priv); 1605 void (*enable_rf) (struct rtl8xxxu_priv *priv); 1606 void (*disable_rf) (struct rtl8xxxu_priv *priv); 1607 void (*usb_quirks) (struct rtl8xxxu_priv *priv); 1608 void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel, 1609 bool ht40); 1610 void (*update_rate_mask) (struct rtl8xxxu_priv *priv, 1611 u32 ramask, u8 rateid, int sgi, int txbw_40mhz); 1612 void (*report_connect) (struct rtl8xxxu_priv *priv, 1613 u8 macid, bool connect); 1614 void (*report_rssi) (struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 1615 void (*fill_txdesc) (struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 1616 struct ieee80211_tx_info *tx_info, 1617 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 1618 bool short_preamble, bool ampdu_enable, 1619 u32 rts_rate); 1620 void (*set_crystal_cap) (struct rtl8xxxu_priv *priv, u8 crystal_cap); 1621 s8 (*cck_rssi) (struct rtl8xxxu_priv *priv, u8 cck_agc_rpt); 1622 int (*led_classdev_brightness_set) (struct led_classdev *led_cdev, 1623 enum led_brightness brightness); 1624 int writeN_block_size; 1625 int rx_agg_buf_size; 1626 char tx_desc_size; 1627 char rx_desc_size; 1628 u8 has_s0s1:1; 1629 u8 has_tx_report:1; 1630 u8 gen2_thermal_meter:1; 1631 u8 needs_full_init:1; 1632 u32 adda_1t_init; 1633 u32 adda_1t_path_on; 1634 u32 adda_2t_path_on_a; 1635 u32 adda_2t_path_on_b; 1636 u16 trxff_boundary; 1637 u8 pbp_rx; 1638 u8 pbp_tx; 1639 const struct rtl8xxxu_reg8val *mactable; 1640 u8 total_page_num; 1641 u8 page_num_hi; 1642 u8 page_num_lo; 1643 u8 page_num_norm; 1644 u8 last_llt_entry; 1645 }; 1646 1647 extern int rtl8xxxu_debug; 1648 1649 extern const struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[]; 1650 extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[]; 1651 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr); 1652 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr); 1653 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr); 1654 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val); 1655 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val); 1656 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val); 1657 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, 1658 enum rtl8xxxu_rfpath path, u8 reg); 1659 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, 1660 enum rtl8xxxu_rfpath path, u8 reg, u32 data); 1661 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 1662 u32 *backup, int count); 1663 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 1664 u32 *backup, int count); 1665 void rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, 1666 const u32 *reg, u32 *backup); 1667 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, 1668 const u32 *reg, u32 *backup); 1669 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, 1670 bool path_a_on); 1671 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, 1672 const u32 *regs, u32 *backup); 1673 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, 1674 int result[][8], int candidate, bool tx_only); 1675 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, 1676 int result[][8], int candidate, bool tx_only); 1677 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, 1678 const struct rtl8xxxu_rfregval *table, 1679 enum rtl8xxxu_rfpath path); 1680 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, 1681 const struct rtl8xxxu_reg32val *array); 1682 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name); 1683 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv); 1684 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv); 1685 void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor); 1686 void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor); 1687 void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv); 1688 int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv); 1689 int rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data); 1690 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv); 1691 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv); 1692 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start); 1693 void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv); 1694 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv); 1695 int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, 1696 struct h2c_cmd *h2c, int len); 1697 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv); 1698 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv); 1699 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv); 1700 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv); 1701 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv); 1702 void rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, 1703 int channel, bool ht40); 1704 void rtl8188f_set_tx_power(struct rtl8xxxu_priv *priv, 1705 int channel, bool ht40); 1706 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw); 1707 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw); 1708 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv); 1709 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv); 1710 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, 1711 u32 ramask, u8 rateid, int sgi, int txbw_40mhz); 1712 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, 1713 u32 ramask, u8 rateid, int sgi, int txbw_40mhz); 1714 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, 1715 u8 macid, bool connect); 1716 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, 1717 u8 macid, bool connect); 1718 void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 1719 void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 1720 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv); 1721 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv); 1722 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv); 1723 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv); 1724 void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv); 1725 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 1726 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 1727 int rtl8xxxu_gen2_channel_to_group(int channel); 1728 bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, 1729 int result[][8], int c1, int c2); 1730 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, 1731 int result[][8], int c1, int c2); 1732 void rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 1733 struct ieee80211_tx_info *tx_info, 1734 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 1735 bool short_preamble, bool ampdu_enable, 1736 u32 rts_rate); 1737 void rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 1738 struct ieee80211_tx_info *tx_info, 1739 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 1740 bool short_preamble, bool ampdu_enable, 1741 u32 rts_rate); 1742 void rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 1743 struct ieee80211_tx_info *tx_info, 1744 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 1745 bool short_preamble, bool ampdu_enable, 1746 u32 rts_rate); 1747 void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, 1748 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5); 1749 void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv); 1750 void rtl8723a_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap); 1751 void rtl8188f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap); 1752 s8 rtl8723a_cck_rssi(struct rtl8xxxu_priv *priv, u8 cck_agc_rpt); 1753 void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt, 1754 u8 rate, u8 sgi, u8 bw); 1755 void rtl8188e_ra_info_init_all(struct rtl8xxxu_ra_info *ra); 1756 void rtl8188e_handle_ra_tx_report2(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 1757 1758 extern struct rtl8xxxu_fileops rtl8188fu_fops; 1759 extern struct rtl8xxxu_fileops rtl8188eu_fops; 1760 extern struct rtl8xxxu_fileops rtl8192cu_fops; 1761 extern struct rtl8xxxu_fileops rtl8192eu_fops; 1762 extern struct rtl8xxxu_fileops rtl8723au_fops; 1763 extern struct rtl8xxxu_fileops rtl8723bu_fops; 1764