1 /* 2 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com> 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * Register definitions taken from original Realtek rtl8723au driver 14 */ 15 16 #include <asm/byteorder.h> 17 18 #define RTL8XXXU_DEBUG_REG_WRITE 0x01 19 #define RTL8XXXU_DEBUG_REG_READ 0x02 20 #define RTL8XXXU_DEBUG_RFREG_WRITE 0x04 21 #define RTL8XXXU_DEBUG_RFREG_READ 0x08 22 #define RTL8XXXU_DEBUG_CHANNEL 0x10 23 #define RTL8XXXU_DEBUG_TX 0x20 24 #define RTL8XXXU_DEBUG_TX_DUMP 0x40 25 #define RTL8XXXU_DEBUG_RX 0x80 26 #define RTL8XXXU_DEBUG_RX_DUMP 0x100 27 #define RTL8XXXU_DEBUG_USB 0x200 28 #define RTL8XXXU_DEBUG_KEY 0x400 29 #define RTL8XXXU_DEBUG_H2C 0x800 30 #define RTL8XXXU_DEBUG_ACTION 0x1000 31 #define RTL8XXXU_DEBUG_EFUSE 0x2000 32 33 #define RTW_USB_CONTROL_MSG_TIMEOUT 500 34 #define RTL8XXXU_MAX_REG_POLL 500 35 #define USB_INTR_CONTENT_LENGTH 56 36 37 #define RTL8XXXU_OUT_ENDPOINTS 4 38 39 #define REALTEK_USB_READ 0xc0 40 #define REALTEK_USB_WRITE 0x40 41 #define REALTEK_USB_CMD_REQ 0x05 42 #define REALTEK_USB_CMD_IDX 0x00 43 44 #define TX_TOTAL_PAGE_NUM 0xf8 45 /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */ 46 #define TX_PAGE_NUM_PUBQ 0xe7 47 #define TX_PAGE_NUM_HI_PQ 0x0c 48 #define TX_PAGE_NUM_LO_PQ 0x02 49 #define TX_PAGE_NUM_NORM_PQ 0x02 50 51 #define RTL_FW_PAGE_SIZE 4096 52 #define RTL8XXXU_FIRMWARE_POLL_MAX 1000 53 54 #define RTL8723A_CHANNEL_GROUPS 3 55 #define RTL8723A_MAX_RF_PATHS 2 56 #define RTL8723B_CHANNEL_GROUPS 6 57 #define RTL8723B_TX_COUNT 4 58 #define RTL8723B_MAX_RF_PATHS 4 59 #define RTL8XXXU_MAX_CHANNEL_GROUPS 6 60 #define RF6052_MAX_TX_PWR 0x3f 61 62 #define EFUSE_MAP_LEN 512 63 #define EFUSE_MAX_SECTION_8723A 64 64 #define EFUSE_REAL_CONTENT_LEN_8723A 512 65 #define EFUSE_BT_MAP_LEN_8723A 1024 66 #define EFUSE_MAX_WORD_UNIT 4 67 68 enum rtl8xxxu_rx_type { 69 RX_TYPE_DATA_PKT = 0, 70 RX_TYPE_C2H = 1, 71 RX_TYPE_ERROR = -1 72 }; 73 74 struct rtl8xxxu_rx_desc { 75 #ifdef __LITTLE_ENDIAN 76 u32 pktlen:14; 77 u32 crc32:1; 78 u32 icverr:1; 79 u32 drvinfo_sz:4; 80 u32 security:3; 81 u32 qos:1; 82 u32 shift:2; 83 u32 phy_stats:1; 84 u32 swdec:1; 85 u32 ls:1; 86 u32 fs:1; 87 u32 eor:1; 88 u32 own:1; 89 90 u32 macid:5; 91 u32 tid:4; 92 u32 hwrsvd:4; 93 u32 amsdu:1; 94 u32 paggr:1; 95 u32 faggr:1; 96 u32 a1fit:4; 97 u32 a2fit:4; 98 u32 pam:1; 99 u32 pwr:1; 100 u32 md:1; 101 u32 mf:1; 102 u32 type:2; 103 u32 mc:1; 104 u32 bc:1; 105 106 u32 seq:12; 107 u32 frag:4; 108 u32 nextpktlen:14; 109 u32 nextind:1; 110 u32 reserved0:1; 111 112 u32 rxmcs:6; 113 u32 rxht:1; 114 u32 gf:1; 115 u32 splcp:1; 116 u32 bw:1; 117 u32 htc:1; 118 u32 eosp:1; 119 u32 bssidfit:2; 120 u32 reserved1:16; 121 u32 unicastwake:1; 122 u32 magicwake:1; 123 124 u32 pattern0match:1; 125 u32 pattern1match:1; 126 u32 pattern2match:1; 127 u32 pattern3match:1; 128 u32 pattern4match:1; 129 u32 pattern5match:1; 130 u32 pattern6match:1; 131 u32 pattern7match:1; 132 u32 pattern8match:1; 133 u32 pattern9match:1; 134 u32 patternamatch:1; 135 u32 patternbmatch:1; 136 u32 patterncmatch:1; 137 u32 reserved2:19; 138 #else 139 u32 own:1; 140 u32 eor:1; 141 u32 fs:1; 142 u32 ls:1; 143 u32 swdec:1; 144 u32 phy_stats:1; 145 u32 shift:2; 146 u32 qos:1; 147 u32 security:3; 148 u32 drvinfo_sz:4; 149 u32 icverr:1; 150 u32 crc32:1; 151 u32 pktlen:14; 152 153 u32 bc:1; 154 u32 mc:1; 155 u32 type:2; 156 u32 mf:1; 157 u32 md:1; 158 u32 pwr:1; 159 u32 pam:1; 160 u32 a2fit:4; 161 u32 a1fit:4; 162 u32 faggr:1; 163 u32 paggr:1; 164 u32 amsdu:1; 165 u32 hwrsvd:4; 166 u32 tid:4; 167 u32 macid:5; 168 169 u32 reserved0:1; 170 u32 nextind:1; 171 u32 nextpktlen:14; 172 u32 frag:4; 173 u32 seq:12; 174 175 u32 magicwake:1; 176 u32 unicastwake:1; 177 u32 reserved1:16; 178 u32 bssidfit:2; 179 u32 eosp:1; 180 u32 htc:1; 181 u32 bw:1; 182 u32 splcp:1; 183 u32 gf:1; 184 u32 rxht:1; 185 u32 rxmcs:6; 186 187 u32 reserved2:19; 188 u32 patterncmatch:1; 189 u32 patternbmatch:1; 190 u32 patternamatch:1; 191 u32 pattern9match:1; 192 u32 pattern8match:1; 193 u32 pattern7match:1; 194 u32 pattern6match:1; 195 u32 pattern5match:1; 196 u32 pattern4match:1; 197 u32 pattern3match:1; 198 u32 pattern2match:1; 199 u32 pattern1match:1; 200 u32 pattern0match:1; 201 #endif 202 __le32 tsfl; 203 #if 0 204 u32 bassn:12; 205 u32 bavld:1; 206 u32 reserved3:19; 207 #endif 208 }; 209 210 struct rtl8723bu_rx_desc { 211 #ifdef __LITTLE_ENDIAN 212 u32 pktlen:14; 213 u32 crc32:1; 214 u32 icverr:1; 215 u32 drvinfo_sz:4; 216 u32 security:3; 217 u32 qos:1; 218 u32 shift:2; 219 u32 phy_stats:1; 220 u32 swdec:1; 221 u32 ls:1; 222 u32 fs:1; 223 u32 eor:1; 224 u32 own:1; 225 226 u32 macid:7; 227 u32 dummy1_0:1; 228 u32 tid:4; 229 u32 dummy1_1:1; 230 u32 amsdu:1; 231 u32 rxid_match:1; 232 u32 paggr:1; 233 u32 a1fit:4; /* 16 */ 234 u32 chkerr:1; 235 u32 ipver:1; 236 u32 tcpudp:1; 237 u32 chkvld:1; 238 u32 pam:1; 239 u32 pwr:1; 240 u32 more_data:1; 241 u32 more_frag:1; 242 u32 type:2; 243 u32 mc:1; 244 u32 bc:1; 245 246 u32 seq:12; 247 u32 frag:4; 248 u32 rx_is_qos:1; /* 16 */ 249 u32 dummy2_0:1; 250 u32 wlanhd_iv_len:6; 251 u32 dummy2_1:4; 252 u32 rpt_sel:1; 253 u32 dummy2_2:3; 254 255 u32 rxmcs:7; 256 u32 dummy3_0:3; 257 u32 htc:1; 258 u32 eosp:1; 259 u32 bssidfit:2; 260 u32 dummy3_1:2; 261 u32 usb_agg_pktnum:8; /* 16 */ 262 u32 dummy3_2:5; 263 u32 pattern_match:1; 264 u32 unicast_match:1; 265 u32 magic_match:1; 266 267 u32 splcp:1; 268 u32 ldcp:1; 269 u32 stbc:1; 270 u32 dummy4_0:1; 271 u32 bw:2; 272 u32 dummy4_1:26; 273 #else 274 u32 own:1; 275 u32 eor:1; 276 u32 fs:1; 277 u32 ls:1; 278 u32 swdec:1; 279 u32 phy_stats:1; 280 u32 shift:2; 281 u32 qos:1; 282 u32 security:3; 283 u32 drvinfo_sz:4; 284 u32 icverr:1; 285 u32 crc32:1; 286 u32 pktlen:14; 287 288 u32 bc:1; 289 u32 mc:1; 290 u32 type:2; 291 u32 mf:1; 292 u32 md:1; 293 u32 pwr:1; 294 u32 pam:1; 295 u32 a2fit:4; 296 u32 a1fit:4; 297 u32 faggr:1; 298 u32 paggr:1; 299 u32 amsdu:1; 300 u32 hwrsvd:4; 301 u32 tid:4; 302 u32 macid:5; 303 304 u32 dummy2_2:3; 305 u32 rpt_sel:1; 306 u32 dummy2_1:4; 307 u32 wlanhd_iv_len:6; 308 u32 dummy2_0:1; 309 u32 rx_is_qos:1; 310 u32 frag:4; /* 16 */ 311 u32 seq:12; 312 313 u32 magic_match:1; 314 u32 unicast_match:1; 315 u32 pattern_match:1; 316 u32 dummy3_2:5; 317 u32 usb_agg_pktnum:8; 318 u32 dummy3_1:2; /* 16 */ 319 u32 bssidfit:2; 320 u32 eosp:1; 321 u32 htc:1; 322 u32 dummy3_0:3; 323 u32 rxmcs:7; 324 325 u32 dumm4_1:26; 326 u32 bw:2; 327 u32 dummy4_0:1; 328 u32 stbc:1; 329 u32 ldcp:1; 330 u32 splcp:1; 331 #endif 332 __le32 tsfl; 333 }; 334 335 struct rtl8723au_tx_desc { 336 __le16 pkt_size; 337 u8 pkt_offset; 338 u8 txdw0; 339 __le32 txdw1; 340 __le32 txdw2; 341 __le32 txdw3; 342 __le32 txdw4; 343 __le32 txdw5; 344 __le32 txdw6; 345 __le16 csum; 346 __le16 txdw7; 347 }; 348 349 struct rtl8723bu_tx_desc { 350 __le16 pkt_size; 351 u8 pkt_offset; 352 u8 txdw0; 353 __le32 txdw1; 354 __le32 txdw2; 355 __le32 txdw3; 356 __le32 txdw4; 357 __le32 txdw5; 358 __le32 txdw6; 359 __le16 csum; 360 __le16 txdw7; 361 __le32 txdw8; 362 __le32 txdw9; 363 }; 364 365 /* CCK Rates, TxHT = 0 */ 366 #define DESC_RATE_1M 0x00 367 #define DESC_RATE_2M 0x01 368 #define DESC_RATE_5_5M 0x02 369 #define DESC_RATE_11M 0x03 370 371 /* OFDM Rates, TxHT = 0 */ 372 #define DESC_RATE_6M 0x04 373 #define DESC_RATE_9M 0x05 374 #define DESC_RATE_12M 0x06 375 #define DESC_RATE_18M 0x07 376 #define DESC_RATE_24M 0x08 377 #define DESC_RATE_36M 0x09 378 #define DESC_RATE_48M 0x0a 379 #define DESC_RATE_54M 0x0b 380 381 /* MCS Rates, TxHT = 1 */ 382 #define DESC_RATE_MCS0 0x0c 383 #define DESC_RATE_MCS1 0x0d 384 #define DESC_RATE_MCS2 0x0e 385 #define DESC_RATE_MCS3 0x0f 386 #define DESC_RATE_MCS4 0x10 387 #define DESC_RATE_MCS5 0x11 388 #define DESC_RATE_MCS6 0x12 389 #define DESC_RATE_MCS7 0x13 390 #define DESC_RATE_MCS8 0x14 391 #define DESC_RATE_MCS9 0x15 392 #define DESC_RATE_MCS10 0x16 393 #define DESC_RATE_MCS11 0x17 394 #define DESC_RATE_MCS12 0x18 395 #define DESC_RATE_MCS13 0x19 396 #define DESC_RATE_MCS14 0x1a 397 #define DESC_RATE_MCS15 0x1b 398 #define DESC_RATE_MCS15_SG 0x1c 399 #define DESC_RATE_MCS32 0x20 400 401 #define TXDESC_OFFSET_SZ 0 402 #define TXDESC_OFFSET_SHT 16 403 #if 0 404 #define TXDESC_BMC BIT(24) 405 #define TXDESC_LSG BIT(26) 406 #define TXDESC_FSG BIT(27) 407 #define TXDESC_OWN BIT(31) 408 #else 409 #define TXDESC_BROADMULTICAST BIT(0) 410 #define TXDESC_HTC BIT(1) 411 #define TXDESC_LAST_SEGMENT BIT(2) 412 #define TXDESC_FIRST_SEGMENT BIT(3) 413 #define TXDESC_LINIP BIT(4) 414 #define TXDESC_NO_ACM BIT(5) 415 #define TXDESC_GF BIT(6) 416 #define TXDESC_OWN BIT(7) 417 #endif 418 419 /* Word 1 */ 420 /* 421 * Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are 422 * aggregation enable and break respectively. For 8723bu, bits 0-7 are macid. 423 */ 424 #define TXDESC_PKT_OFFSET_SZ 0 425 #define TXDESC_AGG_ENABLE_8723A BIT(5) 426 #define TXDESC_AGG_BREAK_8723A BIT(6) 427 #define TXDESC_MACID_SHIFT_8723B 0 428 #define TXDESC_MACID_MASK_8723B 0x00f0 429 #define TXDESC_QUEUE_SHIFT 8 430 #define TXDESC_QUEUE_MASK 0x1f00 431 #define TXDESC_QUEUE_BK 0x2 432 #define TXDESC_QUEUE_BE 0x0 433 #define TXDESC_QUEUE_VI 0x5 434 #define TXDESC_QUEUE_VO 0x7 435 #define TXDESC_QUEUE_BEACON 0x10 436 #define TXDESC_QUEUE_HIGH 0x11 437 #define TXDESC_QUEUE_MGNT 0x12 438 #define TXDESC_QUEUE_CMD 0x13 439 #define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1) 440 #define TXDESC_RDG_NAV_EXT_8723B BIT(13) 441 #define TXDESC_LSIG_TXOP_ENABLE_8723B BIT(14) 442 #define TXDESC_PIFS_8723B BIT(15) 443 444 #define DESC_RATE_ID_SHIFT 16 445 #define DESC_RATE_ID_MASK 0xf 446 #define TXDESC_NAVUSEHDR BIT(20) 447 #define TXDESC_SEC_RC4 0x00400000 448 #define TXDESC_SEC_AES 0x00c00000 449 #define TXDESC_PKT_OFFSET_SHIFT 26 450 #define TXDESC_AGG_EN BIT(29) 451 #define TXDESC_HWPC BIT(31) 452 453 /* Word 2 */ 454 #define TXDESC_PAID_SHIFT_8723B 0 455 #define TXDESC_PAID_MASK_8723B 0x1ff 456 #define TXDESC_CCA_RTS_SHIFT_8723B 10 457 #define TXDESC_CCA_RTS_MASK_8723B 0xc00 458 #define TXDESC_AGG_ENABLE_8723B BIT(12) 459 #define TXDESC_RDG_ENABLE_8723B BIT(13) 460 #define TXDESC_AGG_BREAK_8723B BIT(16) 461 #define TXDESC_MORE_FRAG_8723B BIT(17) 462 #define TXDESC_RAW_8723B BIT(18) 463 #define TXDESC_ACK_REPORT_8723A BIT(19) 464 #define TXDESC_SPE_RPT_8723B BIT(19) 465 #define TXDESC_AMPDU_DENSITY_SHIFT 20 466 #define TXDESC_BT_INT_8723B BIT(23) 467 #define TXDESC_GID_8723B BIT(24) 468 469 /* Word 3 */ 470 #define TXDESC_USE_DRIVER_RATE_8723B BIT(8) 471 #define TXDESC_CTS_SELF_ENABLE_8723B BIT(11) 472 #define TXDESC_RTS_CTS_ENABLE_8723B BIT(12) 473 #define TXDESC_HW_RTS_ENABLE_8723B BIT(13) 474 #define TXDESC_SEQ_SHIFT_8723A 16 475 #define TXDESC_SEQ_MASK_8723A 0x0fff0000 476 477 /* Word 4 */ 478 #define TXDESC_RTS_RATE_SHIFT_8723A 0 479 #define TXDESC_RTS_RATE_MASK_8723A 0x3f 480 #define TXDESC_QOS_8723A BIT(6) 481 #define TXDESC_HW_SEQ_ENABLE_8723A BIT(7) 482 #define TXDESC_USE_DRIVER_RATE_8723A BIT(8) 483 #define TXDESC_DISABLE_DATA_FB BIT(10) 484 #define TXDESC_CTS_SELF_ENABLE_8723A BIT(11) 485 #define TXDESC_RTS_CTS_ENABLE_8723A BIT(12) 486 #define TXDESC_HW_RTS_ENABLE_8723A BIT(13) 487 #define TXDESC_PRIME_CH_OFF_LOWER BIT(20) 488 #define TXDESC_PRIME_CH_OFF_UPPER BIT(21) 489 #define TXDESC_SHORT_PREAMBLE_8723A BIT(24) 490 #define TXDESC_DATA_BW BIT(25) 491 #define TXDESC_RTS_DATA_BW BIT(27) 492 #define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28) 493 #define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29) 494 #define TXDESC_DATA_RATE_FB_SHIFT_8723B 8 495 #define TXDESC_DATA_RATE_FB_MASK_8723B 0x00001f00 496 #define TXDESC_RETRY_LIMIT_ENABLE_8723B BIT(17) 497 #define TXDESC_RETRY_LIMIT_SHIFT_8723B 18 498 #define TXDESC_RETRY_LIMIT_MASK_8723B 0x00fc0000 499 #define TXDESC_RTS_RATE_SHIFT_8723B 24 500 #define TXDESC_RTS_RATE_MASK_8723B 0x3f000000 501 502 /* Word 5 */ 503 #define TXDESC_SHORT_PREAMBLE_8723B BIT(4) 504 #define TXDESC_SHORT_GI BIT(6) 505 #define TXDESC_CCX_TAG BIT(7) 506 #define TXDESC_RETRY_LIMIT_ENABLE_8723A BIT(17) 507 #define TXDESC_RETRY_LIMIT_SHIFT_8723A 18 508 #define TXDESC_RETRY_LIMIT_MASK_8723A 0x00fc0000 509 510 /* Word 6 */ 511 #define TXDESC_MAX_AGG_SHIFT 11 512 513 /* Word 8 */ 514 #define TXDESC_HW_SEQ_ENABLE_8723B BIT(15) 515 516 /* Word 9 */ 517 #define TXDESC_SEQ_SHIFT_8723B 12 518 #define TXDESC_SEQ_MASK_8723B 0x00fff000 519 520 struct phy_rx_agc_info { 521 #ifdef __LITTLE_ENDIAN 522 u8 gain:7, trsw:1; 523 #else 524 u8 trsw:1, gain:7; 525 #endif 526 }; 527 528 struct rtl8723au_phy_stats { 529 struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS]; 530 u8 ch_corr[RTL8723A_MAX_RF_PATHS]; 531 u8 cck_sig_qual_ofdm_pwdb_all; 532 u8 cck_agc_rpt_ofdm_cfosho_a; 533 u8 cck_rpt_b_ofdm_cfosho_b; 534 u8 reserved_1; 535 u8 noise_power_db_msb; 536 u8 path_cfotail[RTL8723A_MAX_RF_PATHS]; 537 u8 pcts_mask[RTL8723A_MAX_RF_PATHS]; 538 s8 stream_rxevm[RTL8723A_MAX_RF_PATHS]; 539 u8 path_rxsnr[RTL8723A_MAX_RF_PATHS]; 540 u8 noise_power_db_lsb; 541 u8 reserved_2[3]; 542 u8 stream_csi[RTL8723A_MAX_RF_PATHS]; 543 u8 stream_target_csi[RTL8723A_MAX_RF_PATHS]; 544 s8 sig_evm; 545 u8 reserved_3; 546 547 #ifdef __LITTLE_ENDIAN 548 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 549 u8 sgi_en:1; 550 u8 rxsc:2; 551 u8 idle_long:1; 552 u8 r_ant_train_en:1; 553 u8 antenna_select_b:1; 554 u8 antenna_select:1; 555 #else /* _BIG_ENDIAN_ */ 556 u8 antenna_select:1; 557 u8 antenna_select_b:1; 558 u8 r_ant_train_en:1; 559 u8 idle_long:1; 560 u8 rxsc:2; 561 u8 sgi_en:1; 562 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 563 #endif 564 }; 565 566 /* 567 * Regs to backup 568 */ 569 #define RTL8XXXU_ADDA_REGS 16 570 #define RTL8XXXU_MAC_REGS 4 571 #define RTL8XXXU_BB_REGS 9 572 573 struct rtl8xxxu_firmware_header { 574 __le16 signature; /* 92C0: test chip; 92C, 575 88C0: test chip; 576 88C1: MP A-cut; 577 92C1: MP A-cut */ 578 u8 category; /* AP/NIC and USB/PCI */ 579 u8 function; 580 581 __le16 major_version; /* FW Version */ 582 u8 minor_version; /* FW Subversion, default 0x00 */ 583 u8 reserved1; 584 585 u8 month; /* Release time Month field */ 586 u8 date; /* Release time Date field */ 587 u8 hour; /* Release time Hour field */ 588 u8 minute; /* Release time Minute field */ 589 590 __le16 ramcodesize; /* Size of RAM code */ 591 u16 reserved2; 592 593 __le32 svn_idx; /* SVN entry index */ 594 u32 reserved3; 595 596 u32 reserved4; 597 u32 reserved5; 598 599 u8 data[0]; 600 }; 601 602 /* 603 * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14 604 */ 605 struct rtl8723au_idx { 606 #ifdef __LITTLE_ENDIAN 607 int a:4; 608 int b:4; 609 #else 610 int b:4; 611 int a:4; 612 #endif 613 } __attribute__((packed)); 614 615 struct rtl8723au_efuse { 616 __le16 rtl_id; 617 u8 res0[0xe]; 618 u8 cck_tx_power_index_A[3]; /* 0x10 */ 619 u8 cck_tx_power_index_B[3]; 620 u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */ 621 u8 ht40_1s_tx_power_index_B[3]; 622 /* 623 * The following entries are half-bytes split as: 624 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 625 */ 626 struct rtl8723au_idx ht20_tx_power_index_diff[3]; 627 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 628 struct rtl8723au_idx ht40_max_power_offset[3]; 629 struct rtl8723au_idx ht20_max_power_offset[3]; 630 u8 channel_plan; /* 0x28 */ 631 u8 tssi_a; 632 u8 thermal_meter; 633 u8 rf_regulatory; 634 u8 rf_option_2; 635 u8 rf_option_3; 636 u8 rf_option_4; 637 u8 res7; 638 u8 version /* 0x30 */; 639 u8 customer_id_major; 640 u8 customer_id_minor; 641 u8 xtal_k; 642 u8 chipset; /* 0x34 */ 643 u8 res8[0x82]; 644 u8 vid; /* 0xb7 */ 645 u8 res9; 646 u8 pid; /* 0xb9 */ 647 u8 res10[0x0c]; 648 u8 mac_addr[ETH_ALEN]; /* 0xc6 */ 649 u8 res11[2]; 650 u8 vendor_name[7]; 651 u8 res12[2]; 652 u8 device_name[0x29]; /* 0xd7 */ 653 }; 654 655 struct rtl8192cu_efuse { 656 __le16 rtl_id; 657 __le16 hpon; 658 u8 res0[2]; 659 __le16 clk; 660 __le16 testr; 661 __le16 vid; 662 __le16 did; 663 __le16 svid; 664 __le16 smid; /* 0x10 */ 665 u8 res1[4]; 666 u8 mac_addr[ETH_ALEN]; /* 0x16 */ 667 u8 res2[2]; 668 u8 vendor_name[7]; 669 u8 res3[3]; 670 u8 device_name[0x14]; /* 0x28 */ 671 u8 res4[0x1e]; /* 0x3c */ 672 u8 cck_tx_power_index_A[3]; /* 0x5a */ 673 u8 cck_tx_power_index_B[3]; 674 u8 ht40_1s_tx_power_index_A[3]; /* 0x60 */ 675 u8 ht40_1s_tx_power_index_B[3]; 676 /* 677 * The following entries are half-bytes split as: 678 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 679 */ 680 struct rtl8723au_idx ht40_2s_tx_power_index_diff[3]; 681 struct rtl8723au_idx ht20_tx_power_index_diff[3]; /* 0x69 */ 682 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 683 struct rtl8723au_idx ht40_max_power_offset[3]; /* 0x6f */ 684 struct rtl8723au_idx ht20_max_power_offset[3]; 685 u8 channel_plan; /* 0x75 */ 686 u8 tssi_a; 687 u8 tssi_b; 688 u8 thermal_meter; /* xtal_k */ /* 0x78 */ 689 u8 rf_regulatory; 690 u8 rf_option_2; 691 u8 rf_option_3; 692 u8 rf_option_4; 693 u8 res5[1]; /* 0x7d */ 694 u8 version; 695 u8 customer_id; 696 }; 697 698 struct rtl8723bu_pwr_idx { 699 #ifdef __LITTLE_ENDIAN 700 int ht20:4; 701 int ht40:4; 702 int ofdm:4; 703 int cck:4; 704 #else 705 int cck:4; 706 int ofdm:4; 707 int ht40:4; 708 int ht20:4; 709 #endif 710 } __attribute__((packed)); 711 712 struct rtl8723bu_efuse_tx_power { 713 u8 cck_base[6]; 714 u8 ht40_base[5]; 715 struct rtl8723au_idx ht20_ofdm_1s_diff; 716 struct rtl8723bu_pwr_idx pwr_diff[3]; 717 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ 718 }; 719 720 struct rtl8723bu_efuse { 721 __le16 rtl_id; 722 u8 res0[0x0e]; 723 struct rtl8723bu_efuse_tx_power tx_power_index_A; /* 0x10 */ 724 struct rtl8723bu_efuse_tx_power tx_power_index_B; /* 0x3a */ 725 struct rtl8723bu_efuse_tx_power tx_power_index_C; /* 0x64 */ 726 struct rtl8723bu_efuse_tx_power tx_power_index_D; /* 0x8e */ 727 u8 channel_plan; /* 0xb8 */ 728 u8 xtal_k; 729 u8 thermal_meter; 730 u8 iqk_lck; 731 u8 pa_type; /* 0xbc */ 732 u8 lna_type_2g; /* 0xbd */ 733 u8 res2[3]; 734 u8 rf_board_option; 735 u8 rf_feature_option; 736 u8 rf_bt_setting; 737 u8 eeprom_version; 738 u8 eeprom_customer_id; 739 u8 res3[2]; 740 u8 tx_pwr_calibrate_rate; 741 u8 rf_antenna_option; /* 0xc9 */ 742 u8 rfe_option; 743 u8 res4[9]; 744 u8 usb_optional_function; 745 u8 res5[0x1e]; 746 u8 res6[2]; 747 u8 serial[0x0b]; /* 0xf5 */ 748 u8 vid; /* 0x100 */ 749 u8 res7; 750 u8 pid; 751 u8 res8[4]; 752 u8 mac_addr[ETH_ALEN]; /* 0x107 */ 753 u8 res9[2]; 754 u8 vendor_name[0x07]; 755 u8 res10[2]; 756 u8 device_name[0x14]; 757 u8 res11[0xcf]; 758 u8 package_type; /* 0x1fb */ 759 u8 res12[0x4]; 760 }; 761 762 struct rtl8192eu_efuse_tx_power { 763 u8 cck_base[6]; 764 u8 ht40_base[5]; 765 struct rtl8723au_idx ht20_ofdm_1s_diff; 766 struct rtl8723au_idx ht40_ht20_2s_diff; 767 struct rtl8723au_idx ofdm_cck_2s_diff; /* not used */ 768 struct rtl8723au_idx ht40_ht20_3s_diff; 769 struct rtl8723au_idx ofdm_cck_3s_diff; /* not used */ 770 struct rtl8723au_idx ht40_ht20_4s_diff; 771 struct rtl8723au_idx ofdm_cck_4s_diff; /* not used */ 772 }; 773 774 struct rtl8192eu_efuse { 775 __le16 rtl_id; 776 u8 res0[0x0e]; 777 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 778 struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x22 */ 779 struct rtl8192eu_efuse_tx_power tx_power_index_C; /* 0x34 */ 780 struct rtl8192eu_efuse_tx_power tx_power_index_D; /* 0x46 */ 781 u8 res1[0x60]; 782 u8 channel_plan; /* 0xb8 */ 783 u8 xtal_k; 784 u8 thermal_meter; 785 u8 iqk_lck; 786 u8 pa_type; /* 0xbc */ 787 u8 lna_type_2g; /* 0xbd */ 788 u8 res2[1]; 789 u8 lna_type_5g; /* 0xbf */ 790 u8 res13[1]; 791 u8 rf_board_option; 792 u8 rf_feature_option; 793 u8 rf_bt_setting; 794 u8 eeprom_version; 795 u8 eeprom_customer_id; 796 u8 res3[3]; 797 u8 rf_antenna_option; /* 0xc9 */ 798 u8 res4[6]; 799 u8 vid; /* 0xd0 */ 800 u8 res5[1]; 801 u8 pid; /* 0xd2 */ 802 u8 res6[1]; 803 u8 usb_optional_function; 804 u8 res7[2]; 805 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 806 u8 res8[2]; 807 u8 vendor_name[7]; 808 u8 res9[2]; 809 u8 device_name[0x0b]; /* 0xe8 */ 810 u8 res10[2]; 811 u8 serial[0x0b]; /* 0xf5 */ 812 u8 res11[0x30]; 813 u8 unknown[0x0d]; /* 0x130 */ 814 u8 res12[0xc3]; 815 }; 816 817 struct rtl8xxxu_reg8val { 818 u16 reg; 819 u8 val; 820 }; 821 822 struct rtl8xxxu_reg32val { 823 u16 reg; 824 u32 val; 825 }; 826 827 struct rtl8xxxu_rfregval { 828 u8 reg; 829 u32 val; 830 }; 831 832 enum rtl8xxxu_rfpath { 833 RF_A = 0, 834 RF_B = 1, 835 }; 836 837 struct rtl8xxxu_rfregs { 838 u16 hssiparm1; 839 u16 hssiparm2; 840 u16 lssiparm; 841 u16 hspiread; 842 u16 lssiread; 843 u16 rf_sw_ctrl; 844 }; 845 846 #define H2C_MAX_MBOX 4 847 #define H2C_EXT BIT(7) 848 #define H2C_JOIN_BSS_DISCONNECT 0 849 #define H2C_JOIN_BSS_CONNECT 1 850 851 /* 852 * H2C (firmware) commands differ between the older generation chips 853 * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu, 854 * 8192[de]u, 8192eu, and 8812. 855 */ 856 enum h2c_cmd_8723a { 857 H2C_SET_POWER_MODE = 1, 858 H2C_JOIN_BSS_REPORT = 2, 859 H2C_SET_RSSI = 5, 860 H2C_SET_RATE_MASK = (6 | H2C_EXT), 861 }; 862 863 enum h2c_cmd_8723b { 864 /* 865 * Common Class: 000 866 */ 867 H2C_8723B_RSVD_PAGE = 0x00, 868 H2C_8723B_MEDIA_STATUS_RPT = 0x01, 869 H2C_8723B_SCAN_ENABLE = 0x02, 870 H2C_8723B_KEEP_ALIVE = 0x03, 871 H2C_8723B_DISCON_DECISION = 0x04, 872 H2C_8723B_PSD_OFFLOAD = 0x05, 873 H2C_8723B_AP_OFFLOAD = 0x08, 874 H2C_8723B_BCN_RSVDPAGE = 0x09, 875 H2C_8723B_PROBERSP_RSVDPAGE = 0x0A, 876 H2C_8723B_FCS_RSVDPAGE = 0x10, 877 H2C_8723B_FCS_INFO = 0x11, 878 H2C_8723B_AP_WOW_GPIO_CTRL = 0x13, 879 880 /* 881 * PoweSave Class: 001 882 */ 883 H2C_8723B_SET_PWR_MODE = 0x20, 884 H2C_8723B_PS_TUNING_PARA = 0x21, 885 H2C_8723B_PS_TUNING_PARA2 = 0x22, 886 H2C_8723B_P2P_LPS_PARAM = 0x23, 887 H2C_8723B_P2P_PS_OFFLOAD = 0x24, 888 H2C_8723B_PS_SCAN_ENABLE = 0x25, 889 H2C_8723B_SAP_PS_ = 0x26, 890 H2C_8723B_INACTIVE_PS_ = 0x27, 891 H2C_8723B_FWLPS_IN_IPS_ = 0x28, 892 893 /* 894 * Dynamic Mechanism Class: 010 895 */ 896 H2C_8723B_MACID_CFG_RAID = 0x40, 897 H2C_8723B_TXBF = 0x41, 898 H2C_8723B_RSSI_SETTING = 0x42, 899 H2C_8723B_AP_REQ_TXRPT = 0x43, 900 H2C_8723B_INIT_RATE_COLLECT = 0x44, 901 902 /* 903 * BT Class: 011 904 */ 905 H2C_8723B_B_TYPE_TDMA = 0x60, 906 H2C_8723B_BT_INFO = 0x61, 907 H2C_8723B_FORCE_BT_TXPWR = 0x62, 908 H2C_8723B_BT_IGNORE_WLANACT = 0x63, 909 H2C_8723B_DAC_SWING_VALUE = 0x64, 910 H2C_8723B_ANT_SEL_RSV = 0x65, 911 H2C_8723B_WL_OPMODE = 0x66, 912 H2C_8723B_BT_MP_OPER = 0x67, 913 H2C_8723B_BT_CONTROL = 0x68, 914 H2C_8723B_BT_WIFI_CTRL = 0x69, 915 H2C_8723B_BT_FW_PATCH = 0x6a, 916 H2C_8723B_BT_WLAN_CALIBRATION = 0x6d, 917 H2C_8723B_BT_GRANT = 0x6e, 918 919 /* 920 * WOWLAN Class: 100 921 */ 922 H2C_8723B_WOWLAN = 0x80, 923 H2C_8723B_REMOTE_WAKE_CTRL = 0x81, 924 H2C_8723B_AOAC_GLOBAL_INFO = 0x82, 925 H2C_8723B_AOAC_RSVD_PAGE = 0x83, 926 H2C_8723B_AOAC_RSVD_PAGE2 = 0x84, 927 H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85, 928 H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86, 929 H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87, 930 931 H2C_8723B_RESET_TSF = 0xC0, 932 }; 933 934 935 struct h2c_cmd { 936 union { 937 struct { 938 u8 cmd; 939 u8 data[7]; 940 } __packed cmd; 941 struct { 942 __le32 data; 943 __le16 ext; 944 } __packed raw; 945 struct { 946 __le32 data; 947 __le32 ext; 948 } __packed raw_wide; 949 struct { 950 u8 cmd; 951 u8 data; 952 } __packed joinbss; 953 struct { 954 u8 cmd; 955 __le16 mask_hi; 956 u8 arg; 957 __le16 mask_lo; 958 } __packed ramask; 959 struct { 960 u8 cmd; 961 u8 parm; 962 u8 macid; 963 u8 macid_end; 964 } __packed media_status_rpt; 965 struct { 966 u8 cmd; 967 u8 macid; 968 /* 969 * [0:4] - RAID 970 * [7] - SGI 971 */ 972 u8 data1; 973 /* 974 * [0:1] - Bandwidth 975 * [3] - No Update 976 * [4:5] - VHT enable 977 * [6] - DISPT 978 * [7] - DISRA 979 */ 980 u8 data2; 981 u8 ramask0; 982 u8 ramask1; 983 u8 ramask2; 984 u8 ramask3; 985 } __packed b_macid_cfg; 986 struct { 987 u8 cmd; 988 u8 data1; 989 u8 data2; 990 u8 data3; 991 u8 data4; 992 u8 data5; 993 } __packed b_type_dma; 994 struct { 995 u8 cmd; 996 u8 data; 997 } __packed bt_info; 998 struct { 999 u8 cmd; 1000 u8 operreq; 1001 u8 opcode; 1002 u8 data; 1003 u8 addr; 1004 } __packed bt_mp_oper; 1005 struct { 1006 u8 cmd; 1007 u8 data; 1008 } __packed bt_wlan_calibration; 1009 struct { 1010 u8 cmd; 1011 u8 data; 1012 } __packed ignore_wlan; 1013 struct { 1014 u8 cmd; 1015 u8 ant_inverse; 1016 u8 int_switch_type; 1017 } __packed ant_sel_rsv; 1018 struct { 1019 u8 cmd; 1020 u8 data; 1021 } __packed bt_grant; 1022 }; 1023 }; 1024 1025 enum c2h_evt_8723b { 1026 C2H_8723B_DEBUG = 0, 1027 C2H_8723B_TSF = 1, 1028 C2H_8723B_AP_RPT_RSP = 2, 1029 C2H_8723B_CCX_TX_RPT = 3, 1030 C2H_8723B_BT_RSSI = 4, 1031 C2H_8723B_BT_OP_MODE = 5, 1032 C2H_8723B_EXT_RA_RPT = 6, 1033 C2H_8723B_BT_INFO = 9, 1034 C2H_8723B_HW_INFO_EXCH = 0x0a, 1035 C2H_8723B_BT_MP_INFO = 0x0b, 1036 C2H_8723B_RA_REPORT = 0x0c, 1037 C2H_8723B_FW_DEBUG = 0xff, 1038 }; 1039 1040 enum bt_info_src_8723b { 1041 BT_INFO_SRC_8723B_WIFI_FW = 0x0, 1042 BT_INFO_SRC_8723B_BT_RSP = 0x1, 1043 BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2, 1044 }; 1045 1046 enum bt_mp_oper_opcode_8723b { 1047 BT_MP_OP_GET_BT_VERSION = 0x00, 1048 BT_MP_OP_RESET = 0x01, 1049 BT_MP_OP_TEST_CTRL = 0x02, 1050 BT_MP_OP_SET_BT_MODE = 0x03, 1051 BT_MP_OP_SET_CHNL_TX_GAIN = 0x04, 1052 BT_MP_OP_SET_PKT_TYPE_LEN = 0x05, 1053 BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06, 1054 BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07, 1055 BT_MP_OP_SET_PKT_HEADER = 0x08, 1056 BT_MP_OP_SET_WHITENCOEFF = 0x09, 1057 BT_MP_OP_SET_BD_ADDR_L = 0x0a, 1058 BT_MP_OP_SET_BD_ADDR_H = 0x0b, 1059 BT_MP_OP_WRITE_REG_ADDR = 0x0c, 1060 BT_MP_OP_WRITE_REG_VALUE = 0x0d, 1061 BT_MP_OP_GET_BT_STATUS = 0x0e, 1062 BT_MP_OP_GET_BD_ADDR_L = 0x0f, 1063 BT_MP_OP_GET_BD_ADDR_H = 0x10, 1064 BT_MP_OP_READ_REG = 0x11, 1065 BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12, 1066 BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13, 1067 BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14, 1068 BT_MP_OP_GET_RX_PKT_CNT_L = 0x15, 1069 BT_MP_OP_GET_RX_PKT_CNT_H = 0x16, 1070 BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17, 1071 BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18, 1072 BT_MP_OP_GET_RSSI = 0x19, 1073 BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a, 1074 BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b, 1075 BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c, 1076 BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d, 1077 BT_MP_OP_GET_AFH_MAP_L = 0x1e, 1078 BT_MP_OP_GET_AFH_MAP_M = 0x1f, 1079 BT_MP_OP_GET_AFH_MAP_H = 0x20, 1080 BT_MP_OP_GET_AFH_STATUS = 0x21, 1081 BT_MP_OP_SET_TRACKING_INTERVAL = 0x22, 1082 BT_MP_OP_SET_THERMAL_METER = 0x23, 1083 BT_MP_OP_ENABLE_CFO_TRACKING = 0x24, 1084 }; 1085 1086 struct rtl8723bu_c2h { 1087 u8 id; 1088 u8 seq; 1089 union { 1090 struct { 1091 u8 payload[0]; 1092 } __packed raw; 1093 struct { 1094 u8 ext_id; 1095 u8 status:4; 1096 u8 retlen:4; 1097 u8 opcode_ver:4; 1098 u8 req_num:4; 1099 u8 payload[2]; 1100 } __packed bt_mp_info; 1101 struct { 1102 u8 response_source:4; 1103 u8 dummy0_0:4; 1104 1105 u8 bt_info; 1106 1107 u8 retry_count:4; 1108 u8 dummy2_0:1; 1109 u8 bt_page:1; 1110 u8 tx_rx_mask:1; 1111 u8 dummy2_2:1; 1112 1113 u8 rssi; 1114 1115 u8 basic_rate:1; 1116 u8 bt_has_reset:1; 1117 u8 dummy4_1:1;; 1118 u8 ignore_wlan:1; 1119 u8 auto_report:1; 1120 u8 dummy4_2:3; 1121 1122 u8 a4; 1123 u8 a5; 1124 } __packed bt_info; 1125 struct { 1126 u8 rate:7; 1127 u8 dummy0_0:1; 1128 u8 macid; 1129 u8 ldpc:1; 1130 u8 txbf:1; 1131 u8 noisy_state:1; 1132 u8 dummy2_0:5; 1133 u8 dummy3_0; 1134 } __packed ra_report; 1135 }; 1136 }; 1137 1138 struct rtl8xxxu_fileops; 1139 1140 struct rtl8xxxu_priv { 1141 struct ieee80211_hw *hw; 1142 struct usb_device *udev; 1143 struct rtl8xxxu_fileops *fops; 1144 1145 spinlock_t tx_urb_lock; 1146 struct list_head tx_urb_free_list; 1147 int tx_urb_free_count; 1148 bool tx_stopped; 1149 1150 spinlock_t rx_urb_lock; 1151 struct list_head rx_urb_pending_list; 1152 int rx_urb_pending_count; 1153 bool shutdown; 1154 struct work_struct rx_urb_wq; 1155 1156 u8 mac_addr[ETH_ALEN]; 1157 char chip_name[8]; 1158 char chip_vendor[8]; 1159 u8 cck_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1160 u8 cck_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1161 u8 ht40_1s_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1162 u8 ht40_1s_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1163 /* 1164 * The following entries are half-bytes split as: 1165 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 1166 */ 1167 struct rtl8723au_idx ht40_2s_tx_power_index_diff[ 1168 RTL8723A_CHANNEL_GROUPS]; 1169 struct rtl8723au_idx ht20_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1170 struct rtl8723au_idx ofdm_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1171 struct rtl8723au_idx ht40_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1172 struct rtl8723au_idx ht20_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1173 /* 1174 * Newer generation chips only keep power diffs per TX count, 1175 * not per channel group. 1176 */ 1177 struct rtl8723au_idx ofdm_tx_power_diff[RTL8723B_TX_COUNT]; 1178 struct rtl8723au_idx ht20_tx_power_diff[RTL8723B_TX_COUNT]; 1179 struct rtl8723au_idx ht40_tx_power_diff[RTL8723B_TX_COUNT]; 1180 u32 chip_cut:4; 1181 u32 rom_rev:4; 1182 u32 is_multi_func:1; 1183 u32 has_wifi:1; 1184 u32 has_bluetooth:1; 1185 u32 enable_bluetooth:1; 1186 u32 has_gps:1; 1187 u32 hi_pa:1; 1188 u32 vendor_umc:1; 1189 u32 vendor_smic:1; 1190 u32 has_polarity_ctrl:1; 1191 u32 has_eeprom:1; 1192 u32 boot_eeprom:1; 1193 u32 usb_interrupts:1; 1194 u32 ep_tx_high_queue:1; 1195 u32 ep_tx_normal_queue:1; 1196 u32 ep_tx_low_queue:1; 1197 u32 has_xtalk:1; 1198 u8 xtalk; 1199 unsigned int pipe_interrupt; 1200 unsigned int pipe_in; 1201 unsigned int pipe_out[TXDESC_QUEUE_MAX]; 1202 u8 out_ep[RTL8XXXU_OUT_ENDPOINTS]; 1203 u8 ep_tx_count; 1204 u8 rf_paths; 1205 u8 rx_paths; 1206 u8 tx_paths; 1207 u32 rf_mode_ag[2]; 1208 u32 rege94; 1209 u32 rege9c; 1210 u32 regeb4; 1211 u32 regebc; 1212 int next_mbox; 1213 int nr_out_eps; 1214 1215 struct mutex h2c_mutex; 1216 1217 struct usb_anchor rx_anchor; 1218 struct usb_anchor tx_anchor; 1219 struct usb_anchor int_anchor; 1220 struct rtl8xxxu_firmware_header *fw_data; 1221 size_t fw_size; 1222 struct mutex usb_buf_mutex; 1223 union { 1224 __le32 val32; 1225 __le16 val16; 1226 u8 val8; 1227 } usb_buf; 1228 union { 1229 u8 raw[EFUSE_MAP_LEN]; 1230 struct rtl8723au_efuse efuse8723; 1231 struct rtl8723bu_efuse efuse8723bu; 1232 struct rtl8192cu_efuse efuse8192; 1233 struct rtl8192eu_efuse efuse8192eu; 1234 } efuse_wifi; 1235 u32 adda_backup[RTL8XXXU_ADDA_REGS]; 1236 u32 mac_backup[RTL8XXXU_MAC_REGS]; 1237 u32 bb_backup[RTL8XXXU_BB_REGS]; 1238 u32 bb_recovery_backup[RTL8XXXU_BB_REGS]; 1239 u32 rtlchip; 1240 u8 pi_enabled:1; 1241 u8 int_buf[USB_INTR_CONTENT_LENGTH]; 1242 }; 1243 1244 struct rtl8xxxu_rx_urb { 1245 struct urb urb; 1246 struct ieee80211_hw *hw; 1247 struct list_head list; 1248 }; 1249 1250 struct rtl8xxxu_tx_urb { 1251 struct urb urb; 1252 struct ieee80211_hw *hw; 1253 struct list_head list; 1254 }; 1255 1256 struct rtl8xxxu_fileops { 1257 int (*parse_efuse) (struct rtl8xxxu_priv *priv); 1258 int (*load_firmware) (struct rtl8xxxu_priv *priv); 1259 int (*power_on) (struct rtl8xxxu_priv *priv); 1260 void (*power_off) (struct rtl8xxxu_priv *priv); 1261 void (*reset_8051) (struct rtl8xxxu_priv *priv); 1262 int (*llt_init) (struct rtl8xxxu_priv *priv, u8 last_tx_page); 1263 void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv); 1264 void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv); 1265 void (*config_channel) (struct ieee80211_hw *hw); 1266 int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb, 1267 struct ieee80211_rx_status *rx_status); 1268 void (*init_aggregation) (struct rtl8xxxu_priv *priv); 1269 void (*init_statistics) (struct rtl8xxxu_priv *priv); 1270 void (*enable_rf) (struct rtl8xxxu_priv *priv); 1271 void (*disable_rf) (struct rtl8xxxu_priv *priv); 1272 void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel, 1273 bool ht40); 1274 void (*update_rate_mask) (struct rtl8xxxu_priv *priv, 1275 u32 ramask, int sgi); 1276 void (*report_connect) (struct rtl8xxxu_priv *priv, 1277 u8 macid, bool connect); 1278 int writeN_block_size; 1279 u16 mbox_ext_reg; 1280 char mbox_ext_width; 1281 char tx_desc_size; 1282 char has_s0s1; 1283 u32 adda_1t_init; 1284 u32 adda_1t_path_on; 1285 u32 adda_2t_path_on_a; 1286 u32 adda_2t_path_on_b; 1287 }; 1288