1 /*
2 	Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 	<http://rt2x00.serialmonkey.com>
4 
5 	This program is free software; you can redistribute it and/or modify
6 	it under the terms of the GNU General Public License as published by
7 	the Free Software Foundation; either version 2 of the License, or
8 	(at your option) any later version.
9 
10 	This program is distributed in the hope that it will be useful,
11 	but WITHOUT ANY WARRANTY; without even the implied warranty of
12 	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 	GNU General Public License for more details.
14 
15 	You should have received a copy of the GNU General Public License
16 	along with this program; if not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 /*
20 	Module: rt73usb
21 	Abstract: Data structures and registers for the rt73usb module.
22 	Supported chipsets: rt2571W & rt2671.
23  */
24 
25 #ifndef RT73USB_H
26 #define RT73USB_H
27 
28 /*
29  * RF chip defines.
30  */
31 #define RF5226				0x0001
32 #define RF2528				0x0002
33 #define RF5225				0x0003
34 #define RF2527				0x0004
35 
36 /*
37  * Signal information.
38  * Default offset is required for RSSI <-> dBm conversion.
39  */
40 #define DEFAULT_RSSI_OFFSET		120
41 
42 /*
43  * Register layout information.
44  */
45 #define CSR_REG_BASE			0x3000
46 #define CSR_REG_SIZE			0x04b0
47 #define EEPROM_BASE			0x0000
48 #define EEPROM_SIZE			0x0100
49 #define BBP_BASE			0x0000
50 #define BBP_SIZE			0x0080
51 #define RF_BASE				0x0004
52 #define RF_SIZE				0x0010
53 
54 /*
55  * Number of TX queues.
56  */
57 #define NUM_TX_QUEUES			4
58 
59 /*
60  * USB registers.
61  */
62 
63 /*
64  * MCU_LEDCS: LED control for MCU Mailbox.
65  */
66 #define MCU_LEDCS_LED_MODE		FIELD16(0x001f)
67 #define MCU_LEDCS_RADIO_STATUS		FIELD16(0x0020)
68 #define MCU_LEDCS_LINK_BG_STATUS	FIELD16(0x0040)
69 #define MCU_LEDCS_LINK_A_STATUS		FIELD16(0x0080)
70 #define MCU_LEDCS_POLARITY_GPIO_0	FIELD16(0x0100)
71 #define MCU_LEDCS_POLARITY_GPIO_1	FIELD16(0x0200)
72 #define MCU_LEDCS_POLARITY_GPIO_2	FIELD16(0x0400)
73 #define MCU_LEDCS_POLARITY_GPIO_3	FIELD16(0x0800)
74 #define MCU_LEDCS_POLARITY_GPIO_4	FIELD16(0x1000)
75 #define MCU_LEDCS_POLARITY_ACT		FIELD16(0x2000)
76 #define MCU_LEDCS_POLARITY_READY_BG	FIELD16(0x4000)
77 #define MCU_LEDCS_POLARITY_READY_A	FIELD16(0x8000)
78 
79 /*
80  * 8051 firmware image.
81  */
82 #define FIRMWARE_RT2571			"rt73.bin"
83 #define FIRMWARE_IMAGE_BASE		0x0800
84 
85 /*
86  * Security key table memory.
87  * 16 entries 32-byte for shared key table
88  * 64 entries 32-byte for pairwise key table
89  * 64 entries 8-byte for pairwise ta key table
90  */
91 #define SHARED_KEY_TABLE_BASE		0x1000
92 #define PAIRWISE_KEY_TABLE_BASE		0x1200
93 #define PAIRWISE_TA_TABLE_BASE		0x1a00
94 
95 #define SHARED_KEY_ENTRY(__idx) \
96 	( SHARED_KEY_TABLE_BASE + \
97 		((__idx) * sizeof(struct hw_key_entry)) )
98 #define PAIRWISE_KEY_ENTRY(__idx) \
99 	( PAIRWISE_KEY_TABLE_BASE + \
100 		((__idx) * sizeof(struct hw_key_entry)) )
101 #define PAIRWISE_TA_ENTRY(__idx) \
102 	( PAIRWISE_TA_TABLE_BASE + \
103 		((__idx) * sizeof(struct hw_pairwise_ta_entry)) )
104 
105 struct hw_key_entry {
106 	u8 key[16];
107 	u8 tx_mic[8];
108 	u8 rx_mic[8];
109 } __packed;
110 
111 struct hw_pairwise_ta_entry {
112 	u8 address[6];
113 	u8 cipher;
114 	u8 reserved;
115 } __packed;
116 
117 /*
118  * Since NULL frame won't be that long (256 byte),
119  * We steal 16 tail bytes to save debugging settings.
120  */
121 #define HW_DEBUG_SETTING_BASE		0x2bf0
122 
123 /*
124  * On-chip BEACON frame space.
125  */
126 #define HW_BEACON_BASE0			0x2400
127 #define HW_BEACON_BASE1			0x2500
128 #define HW_BEACON_BASE2			0x2600
129 #define HW_BEACON_BASE3			0x2700
130 
131 #define HW_BEACON_OFFSET(__index) \
132 	( HW_BEACON_BASE0 + (__index * 0x0100) )
133 
134 /*
135  * MAC Control/Status Registers(CSR).
136  * Some values are set in TU, whereas 1 TU == 1024 us.
137  */
138 
139 /*
140  * MAC_CSR0: ASIC revision number.
141  */
142 #define MAC_CSR0			0x3000
143 #define MAC_CSR0_REVISION		FIELD32(0x0000000f)
144 #define MAC_CSR0_CHIPSET		FIELD32(0x000ffff0)
145 
146 /*
147  * MAC_CSR1: System control register.
148  * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
149  * BBP_RESET: Hardware reset BBP.
150  * HOST_READY: Host is ready after initialization, 1: ready.
151  */
152 #define MAC_CSR1			0x3004
153 #define MAC_CSR1_SOFT_RESET		FIELD32(0x00000001)
154 #define MAC_CSR1_BBP_RESET		FIELD32(0x00000002)
155 #define MAC_CSR1_HOST_READY		FIELD32(0x00000004)
156 
157 /*
158  * MAC_CSR2: STA MAC register 0.
159  */
160 #define MAC_CSR2			0x3008
161 #define MAC_CSR2_BYTE0			FIELD32(0x000000ff)
162 #define MAC_CSR2_BYTE1			FIELD32(0x0000ff00)
163 #define MAC_CSR2_BYTE2			FIELD32(0x00ff0000)
164 #define MAC_CSR2_BYTE3			FIELD32(0xff000000)
165 
166 /*
167  * MAC_CSR3: STA MAC register 1.
168  * UNICAST_TO_ME_MASK:
169  *	Used to mask off bits from byte 5 of the MAC address
170  *	to determine the UNICAST_TO_ME bit for RX frames.
171  *	The full mask is complemented by BSS_ID_MASK:
172  *		MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
173  */
174 #define MAC_CSR3			0x300c
175 #define MAC_CSR3_BYTE4			FIELD32(0x000000ff)
176 #define MAC_CSR3_BYTE5			FIELD32(0x0000ff00)
177 #define MAC_CSR3_UNICAST_TO_ME_MASK	FIELD32(0x00ff0000)
178 
179 /*
180  * MAC_CSR4: BSSID register 0.
181  */
182 #define MAC_CSR4			0x3010
183 #define MAC_CSR4_BYTE0			FIELD32(0x000000ff)
184 #define MAC_CSR4_BYTE1			FIELD32(0x0000ff00)
185 #define MAC_CSR4_BYTE2			FIELD32(0x00ff0000)
186 #define MAC_CSR4_BYTE3			FIELD32(0xff000000)
187 
188 /*
189  * MAC_CSR5: BSSID register 1.
190  * BSS_ID_MASK:
191  *	This mask is used to mask off bits 0 and 1 of byte 5 of the
192  *	BSSID. This will make sure that those bits will be ignored
193  *	when determining the MY_BSS of RX frames.
194  *		0: 1-BSSID mode (BSS index = 0)
195  *		1: 2-BSSID mode (BSS index: Byte5, bit 0)
196  *		2: 2-BSSID mode (BSS index: byte5, bit 1)
197  *		3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
198  */
199 #define MAC_CSR5			0x3014
200 #define MAC_CSR5_BYTE4			FIELD32(0x000000ff)
201 #define MAC_CSR5_BYTE5			FIELD32(0x0000ff00)
202 #define MAC_CSR5_BSS_ID_MASK		FIELD32(0x00ff0000)
203 
204 /*
205  * MAC_CSR6: Maximum frame length register.
206  */
207 #define MAC_CSR6			0x3018
208 #define MAC_CSR6_MAX_FRAME_UNIT		FIELD32(0x00000fff)
209 
210 /*
211  * MAC_CSR7: Reserved
212  */
213 #define MAC_CSR7			0x301c
214 
215 /*
216  * MAC_CSR8: SIFS/EIFS register.
217  * All units are in US.
218  */
219 #define MAC_CSR8			0x3020
220 #define MAC_CSR8_SIFS			FIELD32(0x000000ff)
221 #define MAC_CSR8_SIFS_AFTER_RX_OFDM	FIELD32(0x0000ff00)
222 #define MAC_CSR8_EIFS			FIELD32(0xffff0000)
223 
224 /*
225  * MAC_CSR9: Back-Off control register.
226  * SLOT_TIME: Slot time, default is 20us for 802.11BG.
227  * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
228  * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
229  * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
230  */
231 #define MAC_CSR9			0x3024
232 #define MAC_CSR9_SLOT_TIME		FIELD32(0x000000ff)
233 #define MAC_CSR9_CWMIN			FIELD32(0x00000f00)
234 #define MAC_CSR9_CWMAX			FIELD32(0x0000f000)
235 #define MAC_CSR9_CW_SELECT		FIELD32(0x00010000)
236 
237 /*
238  * MAC_CSR10: Power state configuration.
239  */
240 #define MAC_CSR10			0x3028
241 
242 /*
243  * MAC_CSR11: Power saving transition time register.
244  * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
245  * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
246  * WAKEUP_LATENCY: In unit of TU.
247  */
248 #define MAC_CSR11			0x302c
249 #define MAC_CSR11_DELAY_AFTER_TBCN	FIELD32(0x000000ff)
250 #define MAC_CSR11_TBCN_BEFORE_WAKEUP	FIELD32(0x00007f00)
251 #define MAC_CSR11_AUTOWAKE		FIELD32(0x00008000)
252 #define MAC_CSR11_WAKEUP_LATENCY	FIELD32(0x000f0000)
253 
254 /*
255  * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
256  * CURRENT_STATE: 0:sleep, 1:awake.
257  * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
258  * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
259  */
260 #define MAC_CSR12			0x3030
261 #define MAC_CSR12_CURRENT_STATE		FIELD32(0x00000001)
262 #define MAC_CSR12_PUT_TO_SLEEP		FIELD32(0x00000002)
263 #define MAC_CSR12_FORCE_WAKEUP		FIELD32(0x00000004)
264 #define MAC_CSR12_BBP_CURRENT_STATE	FIELD32(0x00000008)
265 
266 /*
267  * MAC_CSR13: GPIO.
268  *	MAC_CSR13_VALx: GPIO value
269  *	MAC_CSR13_DIRx: GPIO direction: 0 = input; 1 = output
270  */
271 #define MAC_CSR13			0x3034
272 #define MAC_CSR13_VAL0			FIELD32(0x00000001)
273 #define MAC_CSR13_VAL1			FIELD32(0x00000002)
274 #define MAC_CSR13_VAL2			FIELD32(0x00000004)
275 #define MAC_CSR13_VAL3			FIELD32(0x00000008)
276 #define MAC_CSR13_VAL4			FIELD32(0x00000010)
277 #define MAC_CSR13_VAL5			FIELD32(0x00000020)
278 #define MAC_CSR13_VAL6			FIELD32(0x00000040)
279 #define MAC_CSR13_VAL7			FIELD32(0x00000080)
280 #define MAC_CSR13_DIR0			FIELD32(0x00000100)
281 #define MAC_CSR13_DIR1			FIELD32(0x00000200)
282 #define MAC_CSR13_DIR2			FIELD32(0x00000400)
283 #define MAC_CSR13_DIR3			FIELD32(0x00000800)
284 #define MAC_CSR13_DIR4			FIELD32(0x00001000)
285 #define MAC_CSR13_DIR5			FIELD32(0x00002000)
286 #define MAC_CSR13_DIR6			FIELD32(0x00004000)
287 #define MAC_CSR13_DIR7			FIELD32(0x00008000)
288 
289 /*
290  * MAC_CSR14: LED control register.
291  * ON_PERIOD: On period, default 70ms.
292  * OFF_PERIOD: Off period, default 30ms.
293  * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
294  * SW_LED: s/w LED, 1: ON, 0: OFF.
295  * HW_LED_POLARITY: 0: active low, 1: active high.
296  */
297 #define MAC_CSR14			0x3038
298 #define MAC_CSR14_ON_PERIOD		FIELD32(0x000000ff)
299 #define MAC_CSR14_OFF_PERIOD		FIELD32(0x0000ff00)
300 #define MAC_CSR14_HW_LED		FIELD32(0x00010000)
301 #define MAC_CSR14_SW_LED		FIELD32(0x00020000)
302 #define MAC_CSR14_HW_LED_POLARITY	FIELD32(0x00040000)
303 #define MAC_CSR14_SW_LED2		FIELD32(0x00080000)
304 
305 /*
306  * MAC_CSR15: NAV control.
307  */
308 #define MAC_CSR15			0x303c
309 
310 /*
311  * TXRX control registers.
312  * Some values are set in TU, whereas 1 TU == 1024 us.
313  */
314 
315 /*
316  * TXRX_CSR0: TX/RX configuration register.
317  * TSF_OFFSET: Default is 24.
318  * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
319  * DISABLE_RX: Disable Rx engine.
320  * DROP_CRC: Drop CRC error.
321  * DROP_PHYSICAL: Drop physical error.
322  * DROP_CONTROL: Drop control frame.
323  * DROP_NOT_TO_ME: Drop not to me unicast frame.
324  * DROP_TO_DS: Drop fram ToDs bit is true.
325  * DROP_VERSION_ERROR: Drop version error frame.
326  * DROP_MULTICAST: Drop multicast frames.
327  * DROP_BORADCAST: Drop broadcast frames.
328  * DROP_ACK_CTS: Drop received ACK and CTS.
329  */
330 #define TXRX_CSR0			0x3040
331 #define TXRX_CSR0_RX_ACK_TIMEOUT	FIELD32(0x000001ff)
332 #define TXRX_CSR0_TSF_OFFSET		FIELD32(0x00007e00)
333 #define TXRX_CSR0_AUTO_TX_SEQ		FIELD32(0x00008000)
334 #define TXRX_CSR0_DISABLE_RX		FIELD32(0x00010000)
335 #define TXRX_CSR0_DROP_CRC		FIELD32(0x00020000)
336 #define TXRX_CSR0_DROP_PHYSICAL		FIELD32(0x00040000)
337 #define TXRX_CSR0_DROP_CONTROL		FIELD32(0x00080000)
338 #define TXRX_CSR0_DROP_NOT_TO_ME	FIELD32(0x00100000)
339 #define TXRX_CSR0_DROP_TO_DS		FIELD32(0x00200000)
340 #define TXRX_CSR0_DROP_VERSION_ERROR	FIELD32(0x00400000)
341 #define TXRX_CSR0_DROP_MULTICAST	FIELD32(0x00800000)
342 #define TXRX_CSR0_DROP_BROADCAST	FIELD32(0x01000000)
343 #define TXRX_CSR0_DROP_ACK_CTS		FIELD32(0x02000000)
344 #define TXRX_CSR0_TX_WITHOUT_WAITING	FIELD32(0x04000000)
345 
346 /*
347  * TXRX_CSR1
348  */
349 #define TXRX_CSR1			0x3044
350 #define TXRX_CSR1_BBP_ID0		FIELD32(0x0000007f)
351 #define TXRX_CSR1_BBP_ID0_VALID		FIELD32(0x00000080)
352 #define TXRX_CSR1_BBP_ID1		FIELD32(0x00007f00)
353 #define TXRX_CSR1_BBP_ID1_VALID		FIELD32(0x00008000)
354 #define TXRX_CSR1_BBP_ID2		FIELD32(0x007f0000)
355 #define TXRX_CSR1_BBP_ID2_VALID		FIELD32(0x00800000)
356 #define TXRX_CSR1_BBP_ID3		FIELD32(0x7f000000)
357 #define TXRX_CSR1_BBP_ID3_VALID		FIELD32(0x80000000)
358 
359 /*
360  * TXRX_CSR2
361  */
362 #define TXRX_CSR2			0x3048
363 #define TXRX_CSR2_BBP_ID0		FIELD32(0x0000007f)
364 #define TXRX_CSR2_BBP_ID0_VALID		FIELD32(0x00000080)
365 #define TXRX_CSR2_BBP_ID1		FIELD32(0x00007f00)
366 #define TXRX_CSR2_BBP_ID1_VALID		FIELD32(0x00008000)
367 #define TXRX_CSR2_BBP_ID2		FIELD32(0x007f0000)
368 #define TXRX_CSR2_BBP_ID2_VALID		FIELD32(0x00800000)
369 #define TXRX_CSR2_BBP_ID3		FIELD32(0x7f000000)
370 #define TXRX_CSR2_BBP_ID3_VALID		FIELD32(0x80000000)
371 
372 /*
373  * TXRX_CSR3
374  */
375 #define TXRX_CSR3			0x304c
376 #define TXRX_CSR3_BBP_ID0		FIELD32(0x0000007f)
377 #define TXRX_CSR3_BBP_ID0_VALID		FIELD32(0x00000080)
378 #define TXRX_CSR3_BBP_ID1		FIELD32(0x00007f00)
379 #define TXRX_CSR3_BBP_ID1_VALID		FIELD32(0x00008000)
380 #define TXRX_CSR3_BBP_ID2		FIELD32(0x007f0000)
381 #define TXRX_CSR3_BBP_ID2_VALID		FIELD32(0x00800000)
382 #define TXRX_CSR3_BBP_ID3		FIELD32(0x7f000000)
383 #define TXRX_CSR3_BBP_ID3_VALID		FIELD32(0x80000000)
384 
385 /*
386  * TXRX_CSR4: Auto-Responder/Tx-retry register.
387  * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
388  * OFDM_TX_RATE_DOWN: 1:enable.
389  * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
390  * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
391  */
392 #define TXRX_CSR4			0x3050
393 #define TXRX_CSR4_TX_ACK_TIMEOUT	FIELD32(0x000000ff)
394 #define TXRX_CSR4_CNTL_ACK_POLICY	FIELD32(0x00000700)
395 #define TXRX_CSR4_ACK_CTS_PSM		FIELD32(0x00010000)
396 #define TXRX_CSR4_AUTORESPOND_ENABLE	FIELD32(0x00020000)
397 #define TXRX_CSR4_AUTORESPOND_PREAMBLE	FIELD32(0x00040000)
398 #define TXRX_CSR4_OFDM_TX_RATE_DOWN	FIELD32(0x00080000)
399 #define TXRX_CSR4_OFDM_TX_RATE_STEP	FIELD32(0x00300000)
400 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK	FIELD32(0x00400000)
401 #define TXRX_CSR4_LONG_RETRY_LIMIT	FIELD32(0x0f000000)
402 #define TXRX_CSR4_SHORT_RETRY_LIMIT	FIELD32(0xf0000000)
403 
404 /*
405  * TXRX_CSR5
406  */
407 #define TXRX_CSR5			0x3054
408 
409 /*
410  * TXRX_CSR6: ACK/CTS payload consumed time
411  */
412 #define TXRX_CSR6			0x3058
413 
414 /*
415  * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
416  */
417 #define TXRX_CSR7			0x305c
418 #define TXRX_CSR7_ACK_CTS_6MBS		FIELD32(0x000000ff)
419 #define TXRX_CSR7_ACK_CTS_9MBS		FIELD32(0x0000ff00)
420 #define TXRX_CSR7_ACK_CTS_12MBS		FIELD32(0x00ff0000)
421 #define TXRX_CSR7_ACK_CTS_18MBS		FIELD32(0xff000000)
422 
423 /*
424  * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
425  */
426 #define TXRX_CSR8			0x3060
427 #define TXRX_CSR8_ACK_CTS_24MBS		FIELD32(0x000000ff)
428 #define TXRX_CSR8_ACK_CTS_36MBS		FIELD32(0x0000ff00)
429 #define TXRX_CSR8_ACK_CTS_48MBS		FIELD32(0x00ff0000)
430 #define TXRX_CSR8_ACK_CTS_54MBS		FIELD32(0xff000000)
431 
432 /*
433  * TXRX_CSR9: Synchronization control register.
434  * BEACON_INTERVAL: In unit of 1/16 TU.
435  * TSF_TICKING: Enable TSF auto counting.
436  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
437  * BEACON_GEN: Enable beacon generator.
438  */
439 #define TXRX_CSR9			0x3064
440 #define TXRX_CSR9_BEACON_INTERVAL	FIELD32(0x0000ffff)
441 #define TXRX_CSR9_TSF_TICKING		FIELD32(0x00010000)
442 #define TXRX_CSR9_TSF_SYNC		FIELD32(0x00060000)
443 #define TXRX_CSR9_TBTT_ENABLE		FIELD32(0x00080000)
444 #define TXRX_CSR9_BEACON_GEN		FIELD32(0x00100000)
445 #define TXRX_CSR9_TIMESTAMP_COMPENSATE	FIELD32(0xff000000)
446 
447 /*
448  * TXRX_CSR10: BEACON alignment.
449  */
450 #define TXRX_CSR10			0x3068
451 
452 /*
453  * TXRX_CSR11: AES mask.
454  */
455 #define TXRX_CSR11			0x306c
456 
457 /*
458  * TXRX_CSR12: TSF low 32.
459  */
460 #define TXRX_CSR12			0x3070
461 #define TXRX_CSR12_LOW_TSFTIMER		FIELD32(0xffffffff)
462 
463 /*
464  * TXRX_CSR13: TSF high 32.
465  */
466 #define TXRX_CSR13			0x3074
467 #define TXRX_CSR13_HIGH_TSFTIMER	FIELD32(0xffffffff)
468 
469 /*
470  * TXRX_CSR14: TBTT timer.
471  */
472 #define TXRX_CSR14			0x3078
473 
474 /*
475  * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
476  */
477 #define TXRX_CSR15			0x307c
478 
479 /*
480  * PHY control registers.
481  * Some values are set in TU, whereas 1 TU == 1024 us.
482  */
483 
484 /*
485  * PHY_CSR0: RF/PS control.
486  */
487 #define PHY_CSR0			0x3080
488 #define PHY_CSR0_PA_PE_BG		FIELD32(0x00010000)
489 #define PHY_CSR0_PA_PE_A		FIELD32(0x00020000)
490 
491 /*
492  * PHY_CSR1
493  */
494 #define PHY_CSR1			0x3084
495 #define PHY_CSR1_RF_RPI			FIELD32(0x00010000)
496 
497 /*
498  * PHY_CSR2: Pre-TX BBP control.
499  */
500 #define PHY_CSR2			0x3088
501 
502 /*
503  * PHY_CSR3: BBP serial control register.
504  * VALUE: Register value to program into BBP.
505  * REG_NUM: Selected BBP register.
506  * READ_CONTROL: 0: Write BBP, 1: Read BBP.
507  * BUSY: 1: ASIC is busy execute BBP programming.
508  */
509 #define PHY_CSR3			0x308c
510 #define PHY_CSR3_VALUE			FIELD32(0x000000ff)
511 #define PHY_CSR3_REGNUM			FIELD32(0x00007f00)
512 #define PHY_CSR3_READ_CONTROL		FIELD32(0x00008000)
513 #define PHY_CSR3_BUSY			FIELD32(0x00010000)
514 
515 /*
516  * PHY_CSR4: RF serial control register
517  * VALUE: Register value (include register id) serial out to RF/IF chip.
518  * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
519  * IF_SELECT: 1: select IF to program, 0: select RF to program.
520  * PLL_LD: RF PLL_LD status.
521  * BUSY: 1: ASIC is busy execute RF programming.
522  */
523 #define PHY_CSR4			0x3090
524 #define PHY_CSR4_VALUE			FIELD32(0x00ffffff)
525 #define PHY_CSR4_NUMBER_OF_BITS		FIELD32(0x1f000000)
526 #define PHY_CSR4_IF_SELECT		FIELD32(0x20000000)
527 #define PHY_CSR4_PLL_LD			FIELD32(0x40000000)
528 #define PHY_CSR4_BUSY			FIELD32(0x80000000)
529 
530 /*
531  * PHY_CSR5: RX to TX signal switch timing control.
532  */
533 #define PHY_CSR5			0x3094
534 #define PHY_CSR5_IQ_FLIP		FIELD32(0x00000004)
535 
536 /*
537  * PHY_CSR6: TX to RX signal timing control.
538  */
539 #define PHY_CSR6			0x3098
540 #define PHY_CSR6_IQ_FLIP		FIELD32(0x00000004)
541 
542 /*
543  * PHY_CSR7: TX DAC switching timing control.
544  */
545 #define PHY_CSR7			0x309c
546 
547 /*
548  * Security control register.
549  */
550 
551 /*
552  * SEC_CSR0: Shared key table control.
553  */
554 #define SEC_CSR0			0x30a0
555 #define SEC_CSR0_BSS0_KEY0_VALID	FIELD32(0x00000001)
556 #define SEC_CSR0_BSS0_KEY1_VALID	FIELD32(0x00000002)
557 #define SEC_CSR0_BSS0_KEY2_VALID	FIELD32(0x00000004)
558 #define SEC_CSR0_BSS0_KEY3_VALID	FIELD32(0x00000008)
559 #define SEC_CSR0_BSS1_KEY0_VALID	FIELD32(0x00000010)
560 #define SEC_CSR0_BSS1_KEY1_VALID	FIELD32(0x00000020)
561 #define SEC_CSR0_BSS1_KEY2_VALID	FIELD32(0x00000040)
562 #define SEC_CSR0_BSS1_KEY3_VALID	FIELD32(0x00000080)
563 #define SEC_CSR0_BSS2_KEY0_VALID	FIELD32(0x00000100)
564 #define SEC_CSR0_BSS2_KEY1_VALID	FIELD32(0x00000200)
565 #define SEC_CSR0_BSS2_KEY2_VALID	FIELD32(0x00000400)
566 #define SEC_CSR0_BSS2_KEY3_VALID	FIELD32(0x00000800)
567 #define SEC_CSR0_BSS3_KEY0_VALID	FIELD32(0x00001000)
568 #define SEC_CSR0_BSS3_KEY1_VALID	FIELD32(0x00002000)
569 #define SEC_CSR0_BSS3_KEY2_VALID	FIELD32(0x00004000)
570 #define SEC_CSR0_BSS3_KEY3_VALID	FIELD32(0x00008000)
571 
572 /*
573  * SEC_CSR1: Shared key table security mode register.
574  */
575 #define SEC_CSR1			0x30a4
576 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG	FIELD32(0x00000007)
577 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG	FIELD32(0x00000070)
578 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG	FIELD32(0x00000700)
579 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG	FIELD32(0x00007000)
580 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG	FIELD32(0x00070000)
581 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG	FIELD32(0x00700000)
582 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG	FIELD32(0x07000000)
583 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG	FIELD32(0x70000000)
584 
585 /*
586  * Pairwise key table valid bitmap registers.
587  * SEC_CSR2: pairwise key table valid bitmap 0.
588  * SEC_CSR3: pairwise key table valid bitmap 1.
589  */
590 #define SEC_CSR2			0x30a8
591 #define SEC_CSR3			0x30ac
592 
593 /*
594  * SEC_CSR4: Pairwise key table lookup control.
595  */
596 #define SEC_CSR4			0x30b0
597 #define SEC_CSR4_ENABLE_BSS0		FIELD32(0x00000001)
598 #define SEC_CSR4_ENABLE_BSS1		FIELD32(0x00000002)
599 #define SEC_CSR4_ENABLE_BSS2		FIELD32(0x00000004)
600 #define SEC_CSR4_ENABLE_BSS3		FIELD32(0x00000008)
601 
602 /*
603  * SEC_CSR5: shared key table security mode register.
604  */
605 #define SEC_CSR5			0x30b4
606 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG	FIELD32(0x00000007)
607 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG	FIELD32(0x00000070)
608 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG	FIELD32(0x00000700)
609 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG	FIELD32(0x00007000)
610 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG	FIELD32(0x00070000)
611 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG	FIELD32(0x00700000)
612 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG	FIELD32(0x07000000)
613 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG	FIELD32(0x70000000)
614 
615 /*
616  * STA control registers.
617  */
618 
619 /*
620  * STA_CSR0: RX PLCP error count & RX FCS error count.
621  */
622 #define STA_CSR0			0x30c0
623 #define STA_CSR0_FCS_ERROR		FIELD32(0x0000ffff)
624 #define STA_CSR0_PLCP_ERROR		FIELD32(0xffff0000)
625 
626 /*
627  * STA_CSR1: RX False CCA count & RX LONG frame count.
628  */
629 #define STA_CSR1			0x30c4
630 #define STA_CSR1_PHYSICAL_ERROR		FIELD32(0x0000ffff)
631 #define STA_CSR1_FALSE_CCA_ERROR	FIELD32(0xffff0000)
632 
633 /*
634  * STA_CSR2: TX Beacon count and RX FIFO overflow count.
635  */
636 #define STA_CSR2			0x30c8
637 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT	FIELD32(0x0000ffff)
638 #define STA_CSR2_RX_OVERFLOW_COUNT	FIELD32(0xffff0000)
639 
640 /*
641  * STA_CSR3: TX Beacon count.
642  */
643 #define STA_CSR3			0x30cc
644 #define STA_CSR3_TX_BEACON_COUNT	FIELD32(0x0000ffff)
645 
646 /*
647  * STA_CSR4: TX Retry count.
648  */
649 #define STA_CSR4			0x30d0
650 #define STA_CSR4_TX_NO_RETRY_COUNT	FIELD32(0x0000ffff)
651 #define STA_CSR4_TX_ONE_RETRY_COUNT	FIELD32(0xffff0000)
652 
653 /*
654  * STA_CSR5: TX Retry count.
655  */
656 #define STA_CSR5			0x30d4
657 #define STA_CSR4_TX_MULTI_RETRY_COUNT	FIELD32(0x0000ffff)
658 #define STA_CSR4_TX_RETRY_FAIL_COUNT	FIELD32(0xffff0000)
659 
660 /*
661  * QOS control registers.
662  */
663 
664 /*
665  * QOS_CSR1: TXOP holder MAC address register.
666  */
667 #define QOS_CSR1			0x30e4
668 #define QOS_CSR1_BYTE4			FIELD32(0x000000ff)
669 #define QOS_CSR1_BYTE5			FIELD32(0x0000ff00)
670 
671 /*
672  * QOS_CSR2: TXOP holder timeout register.
673  */
674 #define QOS_CSR2			0x30e8
675 
676 /*
677  * RX QOS-CFPOLL MAC address register.
678  * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
679  * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
680  */
681 #define QOS_CSR3			0x30ec
682 #define QOS_CSR4			0x30f0
683 
684 /*
685  * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
686  */
687 #define QOS_CSR5			0x30f4
688 
689 /*
690  * WMM Scheduler Register
691  */
692 
693 /*
694  * AIFSN_CSR: AIFSN for each EDCA AC.
695  * AIFSN0: For AC_VO.
696  * AIFSN1: For AC_VI.
697  * AIFSN2: For AC_BE.
698  * AIFSN3: For AC_BK.
699  */
700 #define AIFSN_CSR			0x0400
701 #define AIFSN_CSR_AIFSN0		FIELD32(0x0000000f)
702 #define AIFSN_CSR_AIFSN1		FIELD32(0x000000f0)
703 #define AIFSN_CSR_AIFSN2		FIELD32(0x00000f00)
704 #define AIFSN_CSR_AIFSN3		FIELD32(0x0000f000)
705 
706 /*
707  * CWMIN_CSR: CWmin for each EDCA AC.
708  * CWMIN0: For AC_VO.
709  * CWMIN1: For AC_VI.
710  * CWMIN2: For AC_BE.
711  * CWMIN3: For AC_BK.
712  */
713 #define CWMIN_CSR			0x0404
714 #define CWMIN_CSR_CWMIN0		FIELD32(0x0000000f)
715 #define CWMIN_CSR_CWMIN1		FIELD32(0x000000f0)
716 #define CWMIN_CSR_CWMIN2		FIELD32(0x00000f00)
717 #define CWMIN_CSR_CWMIN3		FIELD32(0x0000f000)
718 
719 /*
720  * CWMAX_CSR: CWmax for each EDCA AC.
721  * CWMAX0: For AC_VO.
722  * CWMAX1: For AC_VI.
723  * CWMAX2: For AC_BE.
724  * CWMAX3: For AC_BK.
725  */
726 #define CWMAX_CSR			0x0408
727 #define CWMAX_CSR_CWMAX0		FIELD32(0x0000000f)
728 #define CWMAX_CSR_CWMAX1		FIELD32(0x000000f0)
729 #define CWMAX_CSR_CWMAX2		FIELD32(0x00000f00)
730 #define CWMAX_CSR_CWMAX3		FIELD32(0x0000f000)
731 
732 /*
733  * AC_TXOP_CSR0: AC_VO/AC_VI TXOP register.
734  * AC0_TX_OP: For AC_VO, in unit of 32us.
735  * AC1_TX_OP: For AC_VI, in unit of 32us.
736  */
737 #define AC_TXOP_CSR0			0x040c
738 #define AC_TXOP_CSR0_AC0_TX_OP		FIELD32(0x0000ffff)
739 #define AC_TXOP_CSR0_AC1_TX_OP		FIELD32(0xffff0000)
740 
741 /*
742  * AC_TXOP_CSR1: AC_BE/AC_BK TXOP register.
743  * AC2_TX_OP: For AC_BE, in unit of 32us.
744  * AC3_TX_OP: For AC_BK, in unit of 32us.
745  */
746 #define AC_TXOP_CSR1			0x0410
747 #define AC_TXOP_CSR1_AC2_TX_OP		FIELD32(0x0000ffff)
748 #define AC_TXOP_CSR1_AC3_TX_OP		FIELD32(0xffff0000)
749 
750 /*
751  * BBP registers.
752  * The wordsize of the BBP is 8 bits.
753  */
754 
755 /*
756  * R2
757  */
758 #define BBP_R2_BG_MODE			FIELD8(0x20)
759 
760 /*
761  * R3
762  */
763 #define BBP_R3_SMART_MODE		FIELD8(0x01)
764 
765 /*
766  * R4: RX antenna control
767  * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
768  */
769 
770 /*
771  * ANTENNA_CONTROL semantics (guessed):
772  * 0x1: Software controlled antenna switching (fixed or SW diversity)
773  * 0x2: Hardware diversity.
774  */
775 #define BBP_R4_RX_ANTENNA_CONTROL	FIELD8(0x03)
776 #define BBP_R4_RX_FRAME_END		FIELD8(0x20)
777 
778 /*
779  * R77
780  */
781 #define BBP_R77_RX_ANTENNA		FIELD8(0x03)
782 
783 /*
784  * RF registers
785  */
786 
787 /*
788  * RF 3
789  */
790 #define RF3_TXPOWER			FIELD32(0x00003e00)
791 
792 /*
793  * RF 4
794  */
795 #define RF4_FREQ_OFFSET			FIELD32(0x0003f000)
796 
797 /*
798  * EEPROM content.
799  * The wordsize of the EEPROM is 16 bits.
800  */
801 
802 /*
803  * HW MAC address.
804  */
805 #define EEPROM_MAC_ADDR_0		0x0002
806 #define EEPROM_MAC_ADDR_BYTE0		FIELD16(0x00ff)
807 #define EEPROM_MAC_ADDR_BYTE1		FIELD16(0xff00)
808 #define EEPROM_MAC_ADDR1		0x0003
809 #define EEPROM_MAC_ADDR_BYTE2		FIELD16(0x00ff)
810 #define EEPROM_MAC_ADDR_BYTE3		FIELD16(0xff00)
811 #define EEPROM_MAC_ADDR_2		0x0004
812 #define EEPROM_MAC_ADDR_BYTE4		FIELD16(0x00ff)
813 #define EEPROM_MAC_ADDR_BYTE5		FIELD16(0xff00)
814 
815 /*
816  * EEPROM antenna.
817  * ANTENNA_NUM: Number of antennas.
818  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
819  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
820  * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
821  * DYN_TXAGC: Dynamic TX AGC control.
822  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
823  * RF_TYPE: Rf_type of this adapter.
824  */
825 #define EEPROM_ANTENNA			0x0010
826 #define EEPROM_ANTENNA_NUM		FIELD16(0x0003)
827 #define EEPROM_ANTENNA_TX_DEFAULT	FIELD16(0x000c)
828 #define EEPROM_ANTENNA_RX_DEFAULT	FIELD16(0x0030)
829 #define EEPROM_ANTENNA_FRAME_TYPE	FIELD16(0x0040)
830 #define EEPROM_ANTENNA_DYN_TXAGC	FIELD16(0x0200)
831 #define EEPROM_ANTENNA_HARDWARE_RADIO	FIELD16(0x0400)
832 #define EEPROM_ANTENNA_RF_TYPE		FIELD16(0xf800)
833 
834 /*
835  * EEPROM NIC config.
836  * EXTERNAL_LNA: External LNA.
837  */
838 #define EEPROM_NIC			0x0011
839 #define EEPROM_NIC_EXTERNAL_LNA		FIELD16(0x0010)
840 
841 /*
842  * EEPROM geography.
843  * GEO_A: Default geographical setting for 5GHz band
844  * GEO: Default geographical setting.
845  */
846 #define EEPROM_GEOGRAPHY		0x0012
847 #define EEPROM_GEOGRAPHY_GEO_A		FIELD16(0x00ff)
848 #define EEPROM_GEOGRAPHY_GEO		FIELD16(0xff00)
849 
850 /*
851  * EEPROM BBP.
852  */
853 #define EEPROM_BBP_START		0x0013
854 #define EEPROM_BBP_SIZE			16
855 #define EEPROM_BBP_VALUE		FIELD16(0x00ff)
856 #define EEPROM_BBP_REG_ID		FIELD16(0xff00)
857 
858 /*
859  * EEPROM TXPOWER 802.11G
860  */
861 #define EEPROM_TXPOWER_G_START		0x0023
862 #define EEPROM_TXPOWER_G_SIZE		7
863 #define EEPROM_TXPOWER_G_1		FIELD16(0x00ff)
864 #define EEPROM_TXPOWER_G_2		FIELD16(0xff00)
865 
866 /*
867  * EEPROM Frequency
868  */
869 #define EEPROM_FREQ			0x002f
870 #define EEPROM_FREQ_OFFSET		FIELD16(0x00ff)
871 #define EEPROM_FREQ_SEQ_MASK		FIELD16(0xff00)
872 #define EEPROM_FREQ_SEQ			FIELD16(0x0300)
873 
874 /*
875  * EEPROM LED.
876  * POLARITY_RDY_G: Polarity RDY_G setting.
877  * POLARITY_RDY_A: Polarity RDY_A setting.
878  * POLARITY_ACT: Polarity ACT setting.
879  * POLARITY_GPIO_0: Polarity GPIO0 setting.
880  * POLARITY_GPIO_1: Polarity GPIO1 setting.
881  * POLARITY_GPIO_2: Polarity GPIO2 setting.
882  * POLARITY_GPIO_3: Polarity GPIO3 setting.
883  * POLARITY_GPIO_4: Polarity GPIO4 setting.
884  * LED_MODE: Led mode.
885  */
886 #define EEPROM_LED			0x0030
887 #define EEPROM_LED_POLARITY_RDY_G	FIELD16(0x0001)
888 #define EEPROM_LED_POLARITY_RDY_A	FIELD16(0x0002)
889 #define EEPROM_LED_POLARITY_ACT		FIELD16(0x0004)
890 #define EEPROM_LED_POLARITY_GPIO_0	FIELD16(0x0008)
891 #define EEPROM_LED_POLARITY_GPIO_1	FIELD16(0x0010)
892 #define EEPROM_LED_POLARITY_GPIO_2	FIELD16(0x0020)
893 #define EEPROM_LED_POLARITY_GPIO_3	FIELD16(0x0040)
894 #define EEPROM_LED_POLARITY_GPIO_4	FIELD16(0x0080)
895 #define EEPROM_LED_LED_MODE		FIELD16(0x1f00)
896 
897 /*
898  * EEPROM TXPOWER 802.11A
899  */
900 #define EEPROM_TXPOWER_A_START		0x0031
901 #define EEPROM_TXPOWER_A_SIZE		12
902 #define EEPROM_TXPOWER_A_1		FIELD16(0x00ff)
903 #define EEPROM_TXPOWER_A_2		FIELD16(0xff00)
904 
905 /*
906  * EEPROM RSSI offset 802.11BG
907  */
908 #define EEPROM_RSSI_OFFSET_BG		0x004d
909 #define EEPROM_RSSI_OFFSET_BG_1		FIELD16(0x00ff)
910 #define EEPROM_RSSI_OFFSET_BG_2		FIELD16(0xff00)
911 
912 /*
913  * EEPROM RSSI offset 802.11A
914  */
915 #define EEPROM_RSSI_OFFSET_A		0x004e
916 #define EEPROM_RSSI_OFFSET_A_1		FIELD16(0x00ff)
917 #define EEPROM_RSSI_OFFSET_A_2		FIELD16(0xff00)
918 
919 /*
920  * DMA descriptor defines.
921  */
922 #define TXD_DESC_SIZE			( 6 * sizeof(__le32) )
923 #define TXINFO_SIZE			( 6 * sizeof(__le32) )
924 #define RXD_DESC_SIZE			( 6 * sizeof(__le32) )
925 
926 /*
927  * TX descriptor format for TX, PRIO and Beacon Ring.
928  */
929 
930 /*
931  * Word0
932  * BURST: Next frame belongs to same "burst" event.
933  * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
934  * KEY_TABLE: Use per-client pairwise KEY table.
935  * KEY_INDEX:
936  * Key index (0~31) to the pairwise KEY table.
937  * 0~3 to shared KEY table 0 (BSS0).
938  * 4~7 to shared KEY table 1 (BSS1).
939  * 8~11 to shared KEY table 2 (BSS2).
940  * 12~15 to shared KEY table 3 (BSS3).
941  * BURST2: For backward compatibility, set to same value as BURST.
942  */
943 #define TXD_W0_BURST			FIELD32(0x00000001)
944 #define TXD_W0_VALID			FIELD32(0x00000002)
945 #define TXD_W0_MORE_FRAG		FIELD32(0x00000004)
946 #define TXD_W0_ACK			FIELD32(0x00000008)
947 #define TXD_W0_TIMESTAMP		FIELD32(0x00000010)
948 #define TXD_W0_OFDM			FIELD32(0x00000020)
949 #define TXD_W0_IFS			FIELD32(0x00000040)
950 #define TXD_W0_RETRY_MODE		FIELD32(0x00000080)
951 #define TXD_W0_TKIP_MIC			FIELD32(0x00000100)
952 #define TXD_W0_KEY_TABLE		FIELD32(0x00000200)
953 #define TXD_W0_KEY_INDEX		FIELD32(0x0000fc00)
954 #define TXD_W0_DATABYTE_COUNT		FIELD32(0x0fff0000)
955 #define TXD_W0_BURST2			FIELD32(0x10000000)
956 #define TXD_W0_CIPHER_ALG		FIELD32(0xe0000000)
957 
958 /*
959  * Word1
960  * HOST_Q_ID: EDCA/HCCA queue ID.
961  * HW_SEQUENCE: MAC overwrites the frame sequence number.
962  * BUFFER_COUNT: Number of buffers in this TXD.
963  */
964 #define TXD_W1_HOST_Q_ID		FIELD32(0x0000000f)
965 #define TXD_W1_AIFSN			FIELD32(0x000000f0)
966 #define TXD_W1_CWMIN			FIELD32(0x00000f00)
967 #define TXD_W1_CWMAX			FIELD32(0x0000f000)
968 #define TXD_W1_IV_OFFSET		FIELD32(0x003f0000)
969 #define TXD_W1_HW_SEQUENCE		FIELD32(0x10000000)
970 #define TXD_W1_BUFFER_COUNT		FIELD32(0xe0000000)
971 
972 /*
973  * Word2: PLCP information
974  */
975 #define TXD_W2_PLCP_SIGNAL		FIELD32(0x000000ff)
976 #define TXD_W2_PLCP_SERVICE		FIELD32(0x0000ff00)
977 #define TXD_W2_PLCP_LENGTH_LOW		FIELD32(0x00ff0000)
978 #define TXD_W2_PLCP_LENGTH_HIGH		FIELD32(0xff000000)
979 
980 /*
981  * Word3
982  */
983 #define TXD_W3_IV			FIELD32(0xffffffff)
984 
985 /*
986  * Word4
987  */
988 #define TXD_W4_EIV			FIELD32(0xffffffff)
989 
990 /*
991  * Word5
992  * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
993  * PACKET_ID: Driver assigned packet ID to categorize TXResult in interrupt.
994  * WAITING_DMA_DONE_INT: TXD been filled with data
995  * and waiting for TxDoneISR housekeeping.
996  */
997 #define TXD_W5_FRAME_OFFSET		FIELD32(0x000000ff)
998 #define TXD_W5_PACKET_ID		FIELD32(0x0000ff00)
999 #define TXD_W5_TX_POWER			FIELD32(0x00ff0000)
1000 #define TXD_W5_WAITING_DMA_DONE_INT	FIELD32(0x01000000)
1001 
1002 /*
1003  * RX descriptor format for RX Ring.
1004  */
1005 
1006 /*
1007  * Word0
1008  * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
1009  * KEY_INDEX: Decryption key actually used.
1010  */
1011 #define RXD_W0_OWNER_NIC		FIELD32(0x00000001)
1012 #define RXD_W0_DROP			FIELD32(0x00000002)
1013 #define RXD_W0_UNICAST_TO_ME		FIELD32(0x00000004)
1014 #define RXD_W0_MULTICAST		FIELD32(0x00000008)
1015 #define RXD_W0_BROADCAST		FIELD32(0x00000010)
1016 #define RXD_W0_MY_BSS			FIELD32(0x00000020)
1017 #define RXD_W0_CRC_ERROR		FIELD32(0x00000040)
1018 #define RXD_W0_OFDM			FIELD32(0x00000080)
1019 #define RXD_W0_CIPHER_ERROR		FIELD32(0x00000300)
1020 #define RXD_W0_KEY_INDEX		FIELD32(0x0000fc00)
1021 #define RXD_W0_DATABYTE_COUNT		FIELD32(0x0fff0000)
1022 #define RXD_W0_CIPHER_ALG		FIELD32(0xe0000000)
1023 
1024 /*
1025  * WORD1
1026  * SIGNAL: RX raw data rate reported by BBP.
1027  * RSSI: RSSI reported by BBP.
1028  */
1029 #define RXD_W1_SIGNAL			FIELD32(0x000000ff)
1030 #define RXD_W1_RSSI_AGC			FIELD32(0x00001f00)
1031 #define RXD_W1_RSSI_LNA			FIELD32(0x00006000)
1032 #define RXD_W1_FRAME_OFFSET		FIELD32(0x7f000000)
1033 
1034 /*
1035  * Word2
1036  * IV: Received IV of originally encrypted.
1037  */
1038 #define RXD_W2_IV			FIELD32(0xffffffff)
1039 
1040 /*
1041  * Word3
1042  * EIV: Received EIV of originally encrypted.
1043  */
1044 #define RXD_W3_EIV			FIELD32(0xffffffff)
1045 
1046 /*
1047  * Word4
1048  * ICV: Received ICV of originally encrypted.
1049  * NOTE: This is a guess, the official definition is "reserved"
1050  */
1051 #define RXD_W4_ICV			FIELD32(0xffffffff)
1052 
1053 /*
1054  * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1055  * and passed to the HOST driver.
1056  * The following fields are for DMA block and HOST usage only.
1057  * Can't be touched by ASIC MAC block.
1058  */
1059 
1060 /*
1061  * Word5
1062  */
1063 #define RXD_W5_RESERVED			FIELD32(0xffffffff)
1064 
1065 /*
1066  * Macros for converting txpower from EEPROM to mac80211 value
1067  * and from mac80211 value to register value.
1068  */
1069 #define MIN_TXPOWER	0
1070 #define MAX_TXPOWER	31
1071 #define DEFAULT_TXPOWER	24
1072 
1073 #define TXPOWER_FROM_DEV(__txpower) \
1074 	(((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1075 
1076 #define TXPOWER_TO_DEV(__txpower) \
1077 	clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
1078 
1079 #endif /* RT73USB_H */
1080