1 /* 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 3 <http://rt2x00.serialmonkey.com> 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 /* 20 Module: rt73usb 21 Abstract: rt73usb device specific routines. 22 Supported chipsets: rt2571W & rt2671. 23 */ 24 25 #include <linux/crc-itu-t.h> 26 #include <linux/delay.h> 27 #include <linux/etherdevice.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/slab.h> 31 #include <linux/usb.h> 32 33 #include "rt2x00.h" 34 #include "rt2x00usb.h" 35 #include "rt73usb.h" 36 37 /* 38 * Allow hardware encryption to be disabled. 39 */ 40 static bool modparam_nohwcrypt; 41 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); 42 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 43 44 /* 45 * Register access. 46 * All access to the CSR registers will go through the methods 47 * rt2x00usb_register_read and rt2x00usb_register_write. 48 * BBP and RF register require indirect register access, 49 * and use the CSR registers BBPCSR and RFCSR to achieve this. 50 * These indirect registers work with busy bits, 51 * and we will try maximal REGISTER_BUSY_COUNT times to access 52 * the register while taking a REGISTER_BUSY_DELAY us delay 53 * between each attampt. When the busy bit is still set at that time, 54 * the access attempt is considered to have failed, 55 * and we will print an error. 56 * The _lock versions must be used if you already hold the csr_mutex 57 */ 58 #define WAIT_FOR_BBP(__dev, __reg) \ 59 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg)) 60 #define WAIT_FOR_RF(__dev, __reg) \ 61 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg)) 62 63 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev, 64 const unsigned int word, const u8 value) 65 { 66 u32 reg; 67 68 mutex_lock(&rt2x00dev->csr_mutex); 69 70 /* 71 * Wait until the BBP becomes available, afterwards we 72 * can safely write the new data into the register. 73 */ 74 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 75 reg = 0; 76 rt2x00_set_field32(®, PHY_CSR3_VALUE, value); 77 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); 78 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); 79 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); 80 81 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); 82 } 83 84 mutex_unlock(&rt2x00dev->csr_mutex); 85 } 86 87 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev, 88 const unsigned int word, u8 *value) 89 { 90 u32 reg; 91 92 mutex_lock(&rt2x00dev->csr_mutex); 93 94 /* 95 * Wait until the BBP becomes available, afterwards we 96 * can safely write the read request into the register. 97 * After the data has been written, we wait until hardware 98 * returns the correct value, if at any time the register 99 * doesn't become available in time, reg will be 0xffffffff 100 * which means we return 0xff to the caller. 101 */ 102 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 103 reg = 0; 104 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); 105 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); 106 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); 107 108 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); 109 110 WAIT_FOR_BBP(rt2x00dev, ®); 111 } 112 113 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); 114 115 mutex_unlock(&rt2x00dev->csr_mutex); 116 } 117 118 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev, 119 const unsigned int word, const u32 value) 120 { 121 u32 reg; 122 123 mutex_lock(&rt2x00dev->csr_mutex); 124 125 /* 126 * Wait until the RF becomes available, afterwards we 127 * can safely write the new data into the register. 128 */ 129 if (WAIT_FOR_RF(rt2x00dev, ®)) { 130 reg = 0; 131 rt2x00_set_field32(®, PHY_CSR4_VALUE, value); 132 /* 133 * RF5225 and RF2527 contain 21 bits per RF register value, 134 * all others contain 20 bits. 135 */ 136 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 137 20 + (rt2x00_rf(rt2x00dev, RF5225) || 138 rt2x00_rf(rt2x00dev, RF2527))); 139 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); 140 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); 141 142 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg); 143 rt2x00_rf_write(rt2x00dev, word, value); 144 } 145 146 mutex_unlock(&rt2x00dev->csr_mutex); 147 } 148 149 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 150 static const struct rt2x00debug rt73usb_rt2x00debug = { 151 .owner = THIS_MODULE, 152 .csr = { 153 .read = rt2x00usb_register_read, 154 .write = rt2x00usb_register_write, 155 .flags = RT2X00DEBUGFS_OFFSET, 156 .word_base = CSR_REG_BASE, 157 .word_size = sizeof(u32), 158 .word_count = CSR_REG_SIZE / sizeof(u32), 159 }, 160 .eeprom = { 161 .read = rt2x00_eeprom_read, 162 .write = rt2x00_eeprom_write, 163 .word_base = EEPROM_BASE, 164 .word_size = sizeof(u16), 165 .word_count = EEPROM_SIZE / sizeof(u16), 166 }, 167 .bbp = { 168 .read = rt73usb_bbp_read, 169 .write = rt73usb_bbp_write, 170 .word_base = BBP_BASE, 171 .word_size = sizeof(u8), 172 .word_count = BBP_SIZE / sizeof(u8), 173 }, 174 .rf = { 175 .read = rt2x00_rf_read, 176 .write = rt73usb_rf_write, 177 .word_base = RF_BASE, 178 .word_size = sizeof(u32), 179 .word_count = RF_SIZE / sizeof(u32), 180 }, 181 }; 182 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 183 184 static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev) 185 { 186 u32 reg; 187 188 rt2x00usb_register_read(rt2x00dev, MAC_CSR13, ®); 189 return rt2x00_get_field32(reg, MAC_CSR13_VAL7); 190 } 191 192 #ifdef CONFIG_RT2X00_LIB_LEDS 193 static void rt73usb_brightness_set(struct led_classdev *led_cdev, 194 enum led_brightness brightness) 195 { 196 struct rt2x00_led *led = 197 container_of(led_cdev, struct rt2x00_led, led_dev); 198 unsigned int enabled = brightness != LED_OFF; 199 unsigned int a_mode = 200 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); 201 unsigned int bg_mode = 202 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); 203 204 if (led->type == LED_TYPE_RADIO) { 205 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, 206 MCU_LEDCS_RADIO_STATUS, enabled); 207 208 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL, 209 0, led->rt2x00dev->led_mcu_reg, 210 REGISTER_TIMEOUT); 211 } else if (led->type == LED_TYPE_ASSOC) { 212 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, 213 MCU_LEDCS_LINK_BG_STATUS, bg_mode); 214 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, 215 MCU_LEDCS_LINK_A_STATUS, a_mode); 216 217 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL, 218 0, led->rt2x00dev->led_mcu_reg, 219 REGISTER_TIMEOUT); 220 } else if (led->type == LED_TYPE_QUALITY) { 221 /* 222 * The brightness is divided into 6 levels (0 - 5), 223 * this means we need to convert the brightness 224 * argument into the matching level within that range. 225 */ 226 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL, 227 brightness / (LED_FULL / 6), 228 led->rt2x00dev->led_mcu_reg, 229 REGISTER_TIMEOUT); 230 } 231 } 232 233 static int rt73usb_blink_set(struct led_classdev *led_cdev, 234 unsigned long *delay_on, 235 unsigned long *delay_off) 236 { 237 struct rt2x00_led *led = 238 container_of(led_cdev, struct rt2x00_led, led_dev); 239 u32 reg; 240 241 rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, ®); 242 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); 243 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); 244 rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg); 245 246 return 0; 247 } 248 249 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev, 250 struct rt2x00_led *led, 251 enum led_type type) 252 { 253 led->rt2x00dev = rt2x00dev; 254 led->type = type; 255 led->led_dev.brightness_set = rt73usb_brightness_set; 256 led->led_dev.blink_set = rt73usb_blink_set; 257 led->flags = LED_INITIALIZED; 258 } 259 #endif /* CONFIG_RT2X00_LIB_LEDS */ 260 261 /* 262 * Configuration handlers. 263 */ 264 static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev, 265 struct rt2x00lib_crypto *crypto, 266 struct ieee80211_key_conf *key) 267 { 268 struct hw_key_entry key_entry; 269 struct rt2x00_field32 field; 270 u32 mask; 271 u32 reg; 272 273 if (crypto->cmd == SET_KEY) { 274 /* 275 * rt2x00lib can't determine the correct free 276 * key_idx for shared keys. We have 1 register 277 * with key valid bits. The goal is simple, read 278 * the register, if that is full we have no slots 279 * left. 280 * Note that each BSS is allowed to have up to 4 281 * shared keys, so put a mask over the allowed 282 * entries. 283 */ 284 mask = (0xf << crypto->bssidx); 285 286 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, ®); 287 reg &= mask; 288 289 if (reg && reg == mask) 290 return -ENOSPC; 291 292 key->hw_key_idx += reg ? ffz(reg) : 0; 293 294 /* 295 * Upload key to hardware 296 */ 297 memcpy(key_entry.key, crypto->key, 298 sizeof(key_entry.key)); 299 memcpy(key_entry.tx_mic, crypto->tx_mic, 300 sizeof(key_entry.tx_mic)); 301 memcpy(key_entry.rx_mic, crypto->rx_mic, 302 sizeof(key_entry.rx_mic)); 303 304 reg = SHARED_KEY_ENTRY(key->hw_key_idx); 305 rt2x00usb_register_multiwrite(rt2x00dev, reg, 306 &key_entry, sizeof(key_entry)); 307 308 /* 309 * The cipher types are stored over 2 registers. 310 * bssidx 0 and 1 keys are stored in SEC_CSR1 and 311 * bssidx 1 and 2 keys are stored in SEC_CSR5. 312 * Using the correct defines correctly will cause overhead, 313 * so just calculate the correct offset. 314 */ 315 if (key->hw_key_idx < 8) { 316 field.bit_offset = (3 * key->hw_key_idx); 317 field.bit_mask = 0x7 << field.bit_offset; 318 319 rt2x00usb_register_read(rt2x00dev, SEC_CSR1, ®); 320 rt2x00_set_field32(®, field, crypto->cipher); 321 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg); 322 } else { 323 field.bit_offset = (3 * (key->hw_key_idx - 8)); 324 field.bit_mask = 0x7 << field.bit_offset; 325 326 rt2x00usb_register_read(rt2x00dev, SEC_CSR5, ®); 327 rt2x00_set_field32(®, field, crypto->cipher); 328 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg); 329 } 330 331 /* 332 * The driver does not support the IV/EIV generation 333 * in hardware. However it doesn't support the IV/EIV 334 * inside the ieee80211 frame either, but requires it 335 * to be provided separately for the descriptor. 336 * rt2x00lib will cut the IV/EIV data out of all frames 337 * given to us by mac80211, but we must tell mac80211 338 * to generate the IV/EIV data. 339 */ 340 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 341 } 342 343 /* 344 * SEC_CSR0 contains only single-bit fields to indicate 345 * a particular key is valid. Because using the FIELD32() 346 * defines directly will cause a lot of overhead we use 347 * a calculation to determine the correct bit directly. 348 */ 349 mask = 1 << key->hw_key_idx; 350 351 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, ®); 352 if (crypto->cmd == SET_KEY) 353 reg |= mask; 354 else if (crypto->cmd == DISABLE_KEY) 355 reg &= ~mask; 356 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg); 357 358 return 0; 359 } 360 361 static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 362 struct rt2x00lib_crypto *crypto, 363 struct ieee80211_key_conf *key) 364 { 365 struct hw_pairwise_ta_entry addr_entry; 366 struct hw_key_entry key_entry; 367 u32 mask; 368 u32 reg; 369 370 if (crypto->cmd == SET_KEY) { 371 /* 372 * rt2x00lib can't determine the correct free 373 * key_idx for pairwise keys. We have 2 registers 374 * with key valid bits. The goal is simple, read 375 * the first register, if that is full move to 376 * the next register. 377 * When both registers are full, we drop the key, 378 * otherwise we use the first invalid entry. 379 */ 380 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, ®); 381 if (reg && reg == ~0) { 382 key->hw_key_idx = 32; 383 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, ®); 384 if (reg && reg == ~0) 385 return -ENOSPC; 386 } 387 388 key->hw_key_idx += reg ? ffz(reg) : 0; 389 390 /* 391 * Upload key to hardware 392 */ 393 memcpy(key_entry.key, crypto->key, 394 sizeof(key_entry.key)); 395 memcpy(key_entry.tx_mic, crypto->tx_mic, 396 sizeof(key_entry.tx_mic)); 397 memcpy(key_entry.rx_mic, crypto->rx_mic, 398 sizeof(key_entry.rx_mic)); 399 400 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 401 rt2x00usb_register_multiwrite(rt2x00dev, reg, 402 &key_entry, sizeof(key_entry)); 403 404 /* 405 * Send the address and cipher type to the hardware register. 406 */ 407 memset(&addr_entry, 0, sizeof(addr_entry)); 408 memcpy(&addr_entry, crypto->address, ETH_ALEN); 409 addr_entry.cipher = crypto->cipher; 410 411 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); 412 rt2x00usb_register_multiwrite(rt2x00dev, reg, 413 &addr_entry, sizeof(addr_entry)); 414 415 /* 416 * Enable pairwise lookup table for given BSS idx, 417 * without this received frames will not be decrypted 418 * by the hardware. 419 */ 420 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, ®); 421 reg |= (1 << crypto->bssidx); 422 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg); 423 424 /* 425 * The driver does not support the IV/EIV generation 426 * in hardware. However it doesn't support the IV/EIV 427 * inside the ieee80211 frame either, but requires it 428 * to be provided separately for the descriptor. 429 * rt2x00lib will cut the IV/EIV data out of all frames 430 * given to us by mac80211, but we must tell mac80211 431 * to generate the IV/EIV data. 432 */ 433 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 434 } 435 436 /* 437 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate 438 * a particular key is valid. Because using the FIELD32() 439 * defines directly will cause a lot of overhead we use 440 * a calculation to determine the correct bit directly. 441 */ 442 if (key->hw_key_idx < 32) { 443 mask = 1 << key->hw_key_idx; 444 445 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, ®); 446 if (crypto->cmd == SET_KEY) 447 reg |= mask; 448 else if (crypto->cmd == DISABLE_KEY) 449 reg &= ~mask; 450 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg); 451 } else { 452 mask = 1 << (key->hw_key_idx - 32); 453 454 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, ®); 455 if (crypto->cmd == SET_KEY) 456 reg |= mask; 457 else if (crypto->cmd == DISABLE_KEY) 458 reg &= ~mask; 459 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg); 460 } 461 462 return 0; 463 } 464 465 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev, 466 const unsigned int filter_flags) 467 { 468 u32 reg; 469 470 /* 471 * Start configuration steps. 472 * Note that the version error will always be dropped 473 * and broadcast frames will always be accepted since 474 * there is no filter for it at this time. 475 */ 476 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); 477 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, 478 !(filter_flags & FIF_FCSFAIL)); 479 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, 480 !(filter_flags & FIF_PLCPFAIL)); 481 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, 482 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL))); 483 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, 1); 484 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, 485 !rt2x00dev->intf_ap_count); 486 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); 487 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, 488 !(filter_flags & FIF_ALLMULTI)); 489 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); 490 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, 491 !(filter_flags & FIF_CONTROL)); 492 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); 493 } 494 495 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev, 496 struct rt2x00_intf *intf, 497 struct rt2x00intf_conf *conf, 498 const unsigned int flags) 499 { 500 u32 reg; 501 502 if (flags & CONFIG_UPDATE_TYPE) { 503 /* 504 * Enable synchronisation. 505 */ 506 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); 507 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); 508 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); 509 } 510 511 if (flags & CONFIG_UPDATE_MAC) { 512 reg = le32_to_cpu(conf->mac[1]); 513 rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); 514 conf->mac[1] = cpu_to_le32(reg); 515 516 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2, 517 conf->mac, sizeof(conf->mac)); 518 } 519 520 if (flags & CONFIG_UPDATE_BSSID) { 521 reg = le32_to_cpu(conf->bssid[1]); 522 rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3); 523 conf->bssid[1] = cpu_to_le32(reg); 524 525 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4, 526 conf->bssid, sizeof(conf->bssid)); 527 } 528 } 529 530 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev, 531 struct rt2x00lib_erp *erp, 532 u32 changed) 533 { 534 u32 reg; 535 536 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); 537 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); 538 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); 539 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); 540 541 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 542 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, ®); 543 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); 544 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, 545 !!erp->short_preamble); 546 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); 547 } 548 549 if (changed & BSS_CHANGED_BASIC_RATES) 550 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, 551 erp->basic_rates); 552 553 if (changed & BSS_CHANGED_BEACON_INT) { 554 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); 555 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 556 erp->beacon_int * 16); 557 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); 558 } 559 560 if (changed & BSS_CHANGED_ERP_SLOT) { 561 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, ®); 562 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time); 563 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg); 564 565 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, ®); 566 rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs); 567 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); 568 rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs); 569 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg); 570 } 571 } 572 573 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev, 574 struct antenna_setup *ant) 575 { 576 u8 r3; 577 u8 r4; 578 u8 r77; 579 u8 temp; 580 581 rt73usb_bbp_read(rt2x00dev, 3, &r3); 582 rt73usb_bbp_read(rt2x00dev, 4, &r4); 583 rt73usb_bbp_read(rt2x00dev, 77, &r77); 584 585 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0); 586 587 /* 588 * Configure the RX antenna. 589 */ 590 switch (ant->rx) { 591 case ANTENNA_HW_DIVERSITY: 592 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); 593 temp = !rt2x00_has_cap_frame_type(rt2x00dev) && 594 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ); 595 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp); 596 break; 597 case ANTENNA_A: 598 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 599 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); 600 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) 601 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); 602 else 603 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); 604 break; 605 case ANTENNA_B: 606 default: 607 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 608 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); 609 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) 610 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); 611 else 612 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); 613 break; 614 } 615 616 rt73usb_bbp_write(rt2x00dev, 77, r77); 617 rt73usb_bbp_write(rt2x00dev, 3, r3); 618 rt73usb_bbp_write(rt2x00dev, 4, r4); 619 } 620 621 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev, 622 struct antenna_setup *ant) 623 { 624 u8 r3; 625 u8 r4; 626 u8 r77; 627 628 rt73usb_bbp_read(rt2x00dev, 3, &r3); 629 rt73usb_bbp_read(rt2x00dev, 4, &r4); 630 rt73usb_bbp_read(rt2x00dev, 77, &r77); 631 632 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0); 633 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 634 !rt2x00_has_cap_frame_type(rt2x00dev)); 635 636 /* 637 * Configure the RX antenna. 638 */ 639 switch (ant->rx) { 640 case ANTENNA_HW_DIVERSITY: 641 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); 642 break; 643 case ANTENNA_A: 644 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); 645 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 646 break; 647 case ANTENNA_B: 648 default: 649 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); 650 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 651 break; 652 } 653 654 rt73usb_bbp_write(rt2x00dev, 77, r77); 655 rt73usb_bbp_write(rt2x00dev, 3, r3); 656 rt73usb_bbp_write(rt2x00dev, 4, r4); 657 } 658 659 struct antenna_sel { 660 u8 word; 661 /* 662 * value[0] -> non-LNA 663 * value[1] -> LNA 664 */ 665 u8 value[2]; 666 }; 667 668 static const struct antenna_sel antenna_sel_a[] = { 669 { 96, { 0x58, 0x78 } }, 670 { 104, { 0x38, 0x48 } }, 671 { 75, { 0xfe, 0x80 } }, 672 { 86, { 0xfe, 0x80 } }, 673 { 88, { 0xfe, 0x80 } }, 674 { 35, { 0x60, 0x60 } }, 675 { 97, { 0x58, 0x58 } }, 676 { 98, { 0x58, 0x58 } }, 677 }; 678 679 static const struct antenna_sel antenna_sel_bg[] = { 680 { 96, { 0x48, 0x68 } }, 681 { 104, { 0x2c, 0x3c } }, 682 { 75, { 0xfe, 0x80 } }, 683 { 86, { 0xfe, 0x80 } }, 684 { 88, { 0xfe, 0x80 } }, 685 { 35, { 0x50, 0x50 } }, 686 { 97, { 0x48, 0x48 } }, 687 { 98, { 0x48, 0x48 } }, 688 }; 689 690 static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev, 691 struct antenna_setup *ant) 692 { 693 const struct antenna_sel *sel; 694 unsigned int lna; 695 unsigned int i; 696 u32 reg; 697 698 /* 699 * We should never come here because rt2x00lib is supposed 700 * to catch this and send us the correct antenna explicitely. 701 */ 702 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || 703 ant->tx == ANTENNA_SW_DIVERSITY); 704 705 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { 706 sel = antenna_sel_a; 707 lna = rt2x00_has_cap_external_lna_a(rt2x00dev); 708 } else { 709 sel = antenna_sel_bg; 710 lna = rt2x00_has_cap_external_lna_bg(rt2x00dev); 711 } 712 713 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) 714 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); 715 716 rt2x00usb_register_read(rt2x00dev, PHY_CSR0, ®); 717 718 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, 719 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)); 720 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, 721 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)); 722 723 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg); 724 725 if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225)) 726 rt73usb_config_antenna_5x(rt2x00dev, ant); 727 else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527)) 728 rt73usb_config_antenna_2x(rt2x00dev, ant); 729 } 730 731 static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev, 732 struct rt2x00lib_conf *libconf) 733 { 734 u16 eeprom; 735 short lna_gain = 0; 736 737 if (libconf->conf->chandef.chan->band == IEEE80211_BAND_2GHZ) { 738 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 739 lna_gain += 14; 740 741 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom); 742 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1); 743 } else { 744 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom); 745 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1); 746 } 747 748 rt2x00dev->lna_gain = lna_gain; 749 } 750 751 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev, 752 struct rf_channel *rf, const int txpower) 753 { 754 u8 r3; 755 u8 r94; 756 u8 smart; 757 758 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); 759 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 760 761 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527)); 762 763 rt73usb_bbp_read(rt2x00dev, 3, &r3); 764 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart); 765 rt73usb_bbp_write(rt2x00dev, 3, r3); 766 767 r94 = 6; 768 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94)) 769 r94 += txpower - MAX_TXPOWER; 770 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94)) 771 r94 += txpower; 772 rt73usb_bbp_write(rt2x00dev, 94, r94); 773 774 rt73usb_rf_write(rt2x00dev, 1, rf->rf1); 775 rt73usb_rf_write(rt2x00dev, 2, rf->rf2); 776 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 777 rt73usb_rf_write(rt2x00dev, 4, rf->rf4); 778 779 rt73usb_rf_write(rt2x00dev, 1, rf->rf1); 780 rt73usb_rf_write(rt2x00dev, 2, rf->rf2); 781 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 782 rt73usb_rf_write(rt2x00dev, 4, rf->rf4); 783 784 rt73usb_rf_write(rt2x00dev, 1, rf->rf1); 785 rt73usb_rf_write(rt2x00dev, 2, rf->rf2); 786 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 787 rt73usb_rf_write(rt2x00dev, 4, rf->rf4); 788 789 udelay(10); 790 } 791 792 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev, 793 const int txpower) 794 { 795 struct rf_channel rf; 796 797 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1); 798 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2); 799 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3); 800 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4); 801 802 rt73usb_config_channel(rt2x00dev, &rf, txpower); 803 } 804 805 static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev, 806 struct rt2x00lib_conf *libconf) 807 { 808 u32 reg; 809 810 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, ®); 811 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); 812 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); 813 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); 814 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, 815 libconf->conf->long_frame_max_tx_count); 816 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, 817 libconf->conf->short_frame_max_tx_count); 818 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); 819 } 820 821 static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev, 822 struct rt2x00lib_conf *libconf) 823 { 824 enum dev_state state = 825 (libconf->conf->flags & IEEE80211_CONF_PS) ? 826 STATE_SLEEP : STATE_AWAKE; 827 u32 reg; 828 829 if (state == STATE_SLEEP) { 830 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, ®); 831 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 832 rt2x00dev->beacon_int - 10); 833 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 834 libconf->conf->listen_interval - 1); 835 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5); 836 837 /* We must first disable autowake before it can be enabled */ 838 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); 839 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); 840 841 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1); 842 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); 843 844 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0, 845 USB_MODE_SLEEP, REGISTER_TIMEOUT); 846 } else { 847 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, ®); 848 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0); 849 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); 850 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); 851 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0); 852 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); 853 854 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0, 855 USB_MODE_WAKEUP, REGISTER_TIMEOUT); 856 } 857 } 858 859 static void rt73usb_config(struct rt2x00_dev *rt2x00dev, 860 struct rt2x00lib_conf *libconf, 861 const unsigned int flags) 862 { 863 /* Always recalculate LNA gain before changing configuration */ 864 rt73usb_config_lna_gain(rt2x00dev, libconf); 865 866 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) 867 rt73usb_config_channel(rt2x00dev, &libconf->rf, 868 libconf->conf->power_level); 869 if ((flags & IEEE80211_CONF_CHANGE_POWER) && 870 !(flags & IEEE80211_CONF_CHANGE_CHANNEL)) 871 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level); 872 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 873 rt73usb_config_retry_limit(rt2x00dev, libconf); 874 if (flags & IEEE80211_CONF_CHANGE_PS) 875 rt73usb_config_ps(rt2x00dev, libconf); 876 } 877 878 /* 879 * Link tuning 880 */ 881 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev, 882 struct link_qual *qual) 883 { 884 u32 reg; 885 886 /* 887 * Update FCS error count from register. 888 */ 889 rt2x00usb_register_read(rt2x00dev, STA_CSR0, ®); 890 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); 891 892 /* 893 * Update False CCA count from register. 894 */ 895 rt2x00usb_register_read(rt2x00dev, STA_CSR1, ®); 896 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); 897 } 898 899 static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev, 900 struct link_qual *qual, u8 vgc_level) 901 { 902 if (qual->vgc_level != vgc_level) { 903 rt73usb_bbp_write(rt2x00dev, 17, vgc_level); 904 qual->vgc_level = vgc_level; 905 qual->vgc_level_reg = vgc_level; 906 } 907 } 908 909 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev, 910 struct link_qual *qual) 911 { 912 rt73usb_set_vgc(rt2x00dev, qual, 0x20); 913 } 914 915 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev, 916 struct link_qual *qual, const u32 count) 917 { 918 u8 up_bound; 919 u8 low_bound; 920 921 /* 922 * Determine r17 bounds. 923 */ 924 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { 925 low_bound = 0x28; 926 up_bound = 0x48; 927 928 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) { 929 low_bound += 0x10; 930 up_bound += 0x10; 931 } 932 } else { 933 if (qual->rssi > -82) { 934 low_bound = 0x1c; 935 up_bound = 0x40; 936 } else if (qual->rssi > -84) { 937 low_bound = 0x1c; 938 up_bound = 0x20; 939 } else { 940 low_bound = 0x1c; 941 up_bound = 0x1c; 942 } 943 944 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 945 low_bound += 0x14; 946 up_bound += 0x10; 947 } 948 } 949 950 /* 951 * If we are not associated, we should go straight to the 952 * dynamic CCA tuning. 953 */ 954 if (!rt2x00dev->intf_associated) 955 goto dynamic_cca_tune; 956 957 /* 958 * Special big-R17 for very short distance 959 */ 960 if (qual->rssi > -35) { 961 rt73usb_set_vgc(rt2x00dev, qual, 0x60); 962 return; 963 } 964 965 /* 966 * Special big-R17 for short distance 967 */ 968 if (qual->rssi >= -58) { 969 rt73usb_set_vgc(rt2x00dev, qual, up_bound); 970 return; 971 } 972 973 /* 974 * Special big-R17 for middle-short distance 975 */ 976 if (qual->rssi >= -66) { 977 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10); 978 return; 979 } 980 981 /* 982 * Special mid-R17 for middle distance 983 */ 984 if (qual->rssi >= -74) { 985 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08); 986 return; 987 } 988 989 /* 990 * Special case: Change up_bound based on the rssi. 991 * Lower up_bound when rssi is weaker then -74 dBm. 992 */ 993 up_bound -= 2 * (-74 - qual->rssi); 994 if (low_bound > up_bound) 995 up_bound = low_bound; 996 997 if (qual->vgc_level > up_bound) { 998 rt73usb_set_vgc(rt2x00dev, qual, up_bound); 999 return; 1000 } 1001 1002 dynamic_cca_tune: 1003 1004 /* 1005 * r17 does not yet exceed upper limit, continue and base 1006 * the r17 tuning on the false CCA count. 1007 */ 1008 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound)) 1009 rt73usb_set_vgc(rt2x00dev, qual, 1010 min_t(u8, qual->vgc_level + 4, up_bound)); 1011 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound)) 1012 rt73usb_set_vgc(rt2x00dev, qual, 1013 max_t(u8, qual->vgc_level - 4, low_bound)); 1014 } 1015 1016 /* 1017 * Queue handlers. 1018 */ 1019 static void rt73usb_start_queue(struct data_queue *queue) 1020 { 1021 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; 1022 u32 reg; 1023 1024 switch (queue->qid) { 1025 case QID_RX: 1026 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); 1027 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); 1028 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); 1029 break; 1030 case QID_BEACON: 1031 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); 1032 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); 1033 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); 1034 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); 1035 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1036 break; 1037 default: 1038 break; 1039 } 1040 } 1041 1042 static void rt73usb_stop_queue(struct data_queue *queue) 1043 { 1044 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; 1045 u32 reg; 1046 1047 switch (queue->qid) { 1048 case QID_RX: 1049 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); 1050 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 1); 1051 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); 1052 break; 1053 case QID_BEACON: 1054 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); 1055 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); 1056 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); 1057 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); 1058 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1059 break; 1060 default: 1061 break; 1062 } 1063 } 1064 1065 /* 1066 * Firmware functions 1067 */ 1068 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev) 1069 { 1070 return FIRMWARE_RT2571; 1071 } 1072 1073 static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev, 1074 const u8 *data, const size_t len) 1075 { 1076 u16 fw_crc; 1077 u16 crc; 1078 1079 /* 1080 * Only support 2kb firmware files. 1081 */ 1082 if (len != 2048) 1083 return FW_BAD_LENGTH; 1084 1085 /* 1086 * The last 2 bytes in the firmware array are the crc checksum itself, 1087 * this means that we should never pass those 2 bytes to the crc 1088 * algorithm. 1089 */ 1090 fw_crc = (data[len - 2] << 8 | data[len - 1]); 1091 1092 /* 1093 * Use the crc itu-t algorithm. 1094 */ 1095 crc = crc_itu_t(0, data, len - 2); 1096 crc = crc_itu_t_byte(crc, 0); 1097 crc = crc_itu_t_byte(crc, 0); 1098 1099 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC; 1100 } 1101 1102 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, 1103 const u8 *data, const size_t len) 1104 { 1105 unsigned int i; 1106 int status; 1107 u32 reg; 1108 1109 /* 1110 * Wait for stable hardware. 1111 */ 1112 for (i = 0; i < 100; i++) { 1113 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, ®); 1114 if (reg) 1115 break; 1116 msleep(1); 1117 } 1118 1119 if (!reg) { 1120 rt2x00_err(rt2x00dev, "Unstable hardware\n"); 1121 return -EBUSY; 1122 } 1123 1124 /* 1125 * Write firmware to device. 1126 */ 1127 rt2x00usb_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, data, len); 1128 1129 /* 1130 * Send firmware request to device to load firmware, 1131 * we need to specify a long timeout time. 1132 */ 1133 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 1134 0, USB_MODE_FIRMWARE, 1135 REGISTER_TIMEOUT_FIRMWARE); 1136 if (status < 0) { 1137 rt2x00_err(rt2x00dev, "Failed to write Firmware to device\n"); 1138 return status; 1139 } 1140 1141 return 0; 1142 } 1143 1144 /* 1145 * Initialization functions. 1146 */ 1147 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev) 1148 { 1149 u32 reg; 1150 1151 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); 1152 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); 1153 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); 1154 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); 1155 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); 1156 1157 rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, ®); 1158 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ 1159 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); 1160 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ 1161 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); 1162 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ 1163 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); 1164 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ 1165 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); 1166 rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg); 1167 1168 /* 1169 * CCK TXD BBP registers 1170 */ 1171 rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, ®); 1172 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); 1173 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); 1174 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); 1175 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); 1176 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); 1177 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); 1178 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); 1179 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); 1180 rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg); 1181 1182 /* 1183 * OFDM TXD BBP registers 1184 */ 1185 rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, ®); 1186 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); 1187 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); 1188 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); 1189 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); 1190 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); 1191 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); 1192 rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg); 1193 1194 rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, ®); 1195 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); 1196 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); 1197 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); 1198 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); 1199 rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg); 1200 1201 rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, ®); 1202 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); 1203 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); 1204 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); 1205 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); 1206 rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg); 1207 1208 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); 1209 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0); 1210 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); 1211 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); 1212 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); 1213 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); 1214 rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); 1215 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1216 1217 rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); 1218 1219 rt2x00usb_register_read(rt2x00dev, MAC_CSR6, ®); 1220 rt2x00_set_field32(®, MAC_CSR6_MAX_FRAME_UNIT, 0xfff); 1221 rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg); 1222 1223 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718); 1224 1225 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) 1226 return -EBUSY; 1227 1228 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00); 1229 1230 /* 1231 * Invalidate all Shared Keys (SEC_CSR0), 1232 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) 1233 */ 1234 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000); 1235 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000); 1236 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000); 1237 1238 reg = 0x000023b0; 1239 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527)) 1240 rt2x00_set_field32(®, PHY_CSR1_RF_RPI, 1); 1241 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg); 1242 1243 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06); 1244 rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606); 1245 rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408); 1246 1247 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, ®); 1248 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); 1249 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg); 1250 1251 /* 1252 * Clear all beacons 1253 * For the Beacon base registers we only need to clear 1254 * the first byte since that byte contains the VALID and OWNER 1255 * bits which (when set to 0) will invalidate the entire beacon. 1256 */ 1257 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0); 1258 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0); 1259 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0); 1260 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0); 1261 1262 /* 1263 * We must clear the error counters. 1264 * These registers are cleared on read, 1265 * so we may pass a useless variable to store the value. 1266 */ 1267 rt2x00usb_register_read(rt2x00dev, STA_CSR0, ®); 1268 rt2x00usb_register_read(rt2x00dev, STA_CSR1, ®); 1269 rt2x00usb_register_read(rt2x00dev, STA_CSR2, ®); 1270 1271 /* 1272 * Reset MAC and BBP registers. 1273 */ 1274 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, ®); 1275 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); 1276 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); 1277 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); 1278 1279 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, ®); 1280 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); 1281 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); 1282 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); 1283 1284 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, ®); 1285 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); 1286 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); 1287 1288 return 0; 1289 } 1290 1291 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 1292 { 1293 unsigned int i; 1294 u8 value; 1295 1296 for (i = 0; i < REGISTER_USB_BUSY_COUNT; i++) { 1297 rt73usb_bbp_read(rt2x00dev, 0, &value); 1298 if ((value != 0xff) && (value != 0x00)) 1299 return 0; 1300 udelay(REGISTER_BUSY_DELAY); 1301 } 1302 1303 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 1304 return -EACCES; 1305 } 1306 1307 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev) 1308 { 1309 unsigned int i; 1310 u16 eeprom; 1311 u8 reg_id; 1312 u8 value; 1313 1314 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev))) 1315 return -EACCES; 1316 1317 rt73usb_bbp_write(rt2x00dev, 3, 0x80); 1318 rt73usb_bbp_write(rt2x00dev, 15, 0x30); 1319 rt73usb_bbp_write(rt2x00dev, 21, 0xc8); 1320 rt73usb_bbp_write(rt2x00dev, 22, 0x38); 1321 rt73usb_bbp_write(rt2x00dev, 23, 0x06); 1322 rt73usb_bbp_write(rt2x00dev, 24, 0xfe); 1323 rt73usb_bbp_write(rt2x00dev, 25, 0x0a); 1324 rt73usb_bbp_write(rt2x00dev, 26, 0x0d); 1325 rt73usb_bbp_write(rt2x00dev, 32, 0x0b); 1326 rt73usb_bbp_write(rt2x00dev, 34, 0x12); 1327 rt73usb_bbp_write(rt2x00dev, 37, 0x07); 1328 rt73usb_bbp_write(rt2x00dev, 39, 0xf8); 1329 rt73usb_bbp_write(rt2x00dev, 41, 0x60); 1330 rt73usb_bbp_write(rt2x00dev, 53, 0x10); 1331 rt73usb_bbp_write(rt2x00dev, 54, 0x18); 1332 rt73usb_bbp_write(rt2x00dev, 60, 0x10); 1333 rt73usb_bbp_write(rt2x00dev, 61, 0x04); 1334 rt73usb_bbp_write(rt2x00dev, 62, 0x04); 1335 rt73usb_bbp_write(rt2x00dev, 75, 0xfe); 1336 rt73usb_bbp_write(rt2x00dev, 86, 0xfe); 1337 rt73usb_bbp_write(rt2x00dev, 88, 0xfe); 1338 rt73usb_bbp_write(rt2x00dev, 90, 0x0f); 1339 rt73usb_bbp_write(rt2x00dev, 99, 0x00); 1340 rt73usb_bbp_write(rt2x00dev, 102, 0x16); 1341 rt73usb_bbp_write(rt2x00dev, 107, 0x04); 1342 1343 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 1344 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); 1345 1346 if (eeprom != 0xffff && eeprom != 0x0000) { 1347 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 1348 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 1349 rt73usb_bbp_write(rt2x00dev, reg_id, value); 1350 } 1351 } 1352 1353 return 0; 1354 } 1355 1356 /* 1357 * Device state switch handlers. 1358 */ 1359 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev) 1360 { 1361 /* 1362 * Initialize all registers. 1363 */ 1364 if (unlikely(rt73usb_init_registers(rt2x00dev) || 1365 rt73usb_init_bbp(rt2x00dev))) 1366 return -EIO; 1367 1368 return 0; 1369 } 1370 1371 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev) 1372 { 1373 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818); 1374 1375 /* 1376 * Disable synchronisation. 1377 */ 1378 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0); 1379 1380 rt2x00usb_disable_radio(rt2x00dev); 1381 } 1382 1383 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) 1384 { 1385 u32 reg, reg2; 1386 unsigned int i; 1387 char put_to_sleep; 1388 1389 put_to_sleep = (state != STATE_AWAKE); 1390 1391 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, ®); 1392 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); 1393 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); 1394 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg); 1395 1396 /* 1397 * Device is not guaranteed to be in the requested state yet. 1398 * We must wait until the register indicates that the 1399 * device has entered the correct state. 1400 */ 1401 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1402 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, ®2); 1403 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE); 1404 if (state == !put_to_sleep) 1405 return 0; 1406 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg); 1407 msleep(10); 1408 } 1409 1410 return -EBUSY; 1411 } 1412 1413 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev, 1414 enum dev_state state) 1415 { 1416 int retval = 0; 1417 1418 switch (state) { 1419 case STATE_RADIO_ON: 1420 retval = rt73usb_enable_radio(rt2x00dev); 1421 break; 1422 case STATE_RADIO_OFF: 1423 rt73usb_disable_radio(rt2x00dev); 1424 break; 1425 case STATE_RADIO_IRQ_ON: 1426 case STATE_RADIO_IRQ_OFF: 1427 /* No support, but no error either */ 1428 break; 1429 case STATE_DEEP_SLEEP: 1430 case STATE_SLEEP: 1431 case STATE_STANDBY: 1432 case STATE_AWAKE: 1433 retval = rt73usb_set_state(rt2x00dev, state); 1434 break; 1435 default: 1436 retval = -ENOTSUPP; 1437 break; 1438 } 1439 1440 if (unlikely(retval)) 1441 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n", 1442 state, retval); 1443 1444 return retval; 1445 } 1446 1447 /* 1448 * TX descriptor initialization 1449 */ 1450 static void rt73usb_write_tx_desc(struct queue_entry *entry, 1451 struct txentry_desc *txdesc) 1452 { 1453 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1454 __le32 *txd = (__le32 *) entry->skb->data; 1455 u32 word; 1456 1457 /* 1458 * Start writing the descriptor words. 1459 */ 1460 rt2x00_desc_read(txd, 0, &word); 1461 rt2x00_set_field32(&word, TXD_W0_BURST, 1462 test_bit(ENTRY_TXD_BURST, &txdesc->flags)); 1463 rt2x00_set_field32(&word, TXD_W0_VALID, 1); 1464 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, 1465 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 1466 rt2x00_set_field32(&word, TXD_W0_ACK, 1467 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 1468 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, 1469 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 1470 rt2x00_set_field32(&word, TXD_W0_OFDM, 1471 (txdesc->rate_mode == RATE_MODE_OFDM)); 1472 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs); 1473 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1474 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1475 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 1476 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags)); 1477 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE, 1478 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags)); 1479 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx); 1480 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); 1481 rt2x00_set_field32(&word, TXD_W0_BURST2, 1482 test_bit(ENTRY_TXD_BURST, &txdesc->flags)); 1483 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher); 1484 rt2x00_desc_write(txd, 0, word); 1485 1486 rt2x00_desc_read(txd, 1, &word); 1487 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid); 1488 rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs); 1489 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min); 1490 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max); 1491 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); 1492 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1493 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 1494 rt2x00_desc_write(txd, 1, word); 1495 1496 rt2x00_desc_read(txd, 2, &word); 1497 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal); 1498 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service); 1499 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, 1500 txdesc->u.plcp.length_low); 1501 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, 1502 txdesc->u.plcp.length_high); 1503 rt2x00_desc_write(txd, 2, word); 1504 1505 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { 1506 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]); 1507 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]); 1508 } 1509 1510 rt2x00_desc_read(txd, 5, &word); 1511 rt2x00_set_field32(&word, TXD_W5_TX_POWER, 1512 TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power)); 1513 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); 1514 rt2x00_desc_write(txd, 5, word); 1515 1516 /* 1517 * Register descriptor details in skb frame descriptor. 1518 */ 1519 skbdesc->flags |= SKBDESC_DESC_IN_SKB; 1520 skbdesc->desc = txd; 1521 skbdesc->desc_len = TXD_DESC_SIZE; 1522 } 1523 1524 /* 1525 * TX data initialization 1526 */ 1527 static void rt73usb_write_beacon(struct queue_entry *entry, 1528 struct txentry_desc *txdesc) 1529 { 1530 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1531 unsigned int beacon_base; 1532 unsigned int padding_len; 1533 u32 orig_reg, reg; 1534 1535 /* 1536 * Disable beaconing while we are reloading the beacon data, 1537 * otherwise we might be sending out invalid data. 1538 */ 1539 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); 1540 orig_reg = reg; 1541 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); 1542 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1543 1544 /* 1545 * Add space for the descriptor in front of the skb. 1546 */ 1547 skb_push(entry->skb, TXD_DESC_SIZE); 1548 memset(entry->skb->data, 0, TXD_DESC_SIZE); 1549 1550 /* 1551 * Write the TX descriptor for the beacon. 1552 */ 1553 rt73usb_write_tx_desc(entry, txdesc); 1554 1555 /* 1556 * Dump beacon to userspace through debugfs. 1557 */ 1558 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); 1559 1560 /* 1561 * Write entire beacon with descriptor and padding to register. 1562 */ 1563 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 1564 if (padding_len && skb_pad(entry->skb, padding_len)) { 1565 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); 1566 /* skb freed by skb_pad() on failure */ 1567 entry->skb = NULL; 1568 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, orig_reg); 1569 return; 1570 } 1571 1572 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 1573 rt2x00usb_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, 1574 entry->skb->len + padding_len); 1575 1576 /* 1577 * Enable beaconing again. 1578 * 1579 * For Wi-Fi faily generated beacons between participating stations. 1580 * Set TBTT phase adaptive adjustment step to 8us (default 16us) 1581 */ 1582 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); 1583 1584 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); 1585 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1586 1587 /* 1588 * Clean up the beacon skb. 1589 */ 1590 dev_kfree_skb(entry->skb); 1591 entry->skb = NULL; 1592 } 1593 1594 static void rt73usb_clear_beacon(struct queue_entry *entry) 1595 { 1596 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1597 unsigned int beacon_base; 1598 u32 orig_reg, reg; 1599 1600 /* 1601 * Disable beaconing while we are reloading the beacon data, 1602 * otherwise we might be sending out invalid data. 1603 */ 1604 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &orig_reg); 1605 reg = orig_reg; 1606 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); 1607 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1608 1609 /* 1610 * Clear beacon. 1611 */ 1612 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 1613 rt2x00usb_register_write(rt2x00dev, beacon_base, 0); 1614 1615 /* 1616 * Restore beaconing state. 1617 */ 1618 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, orig_reg); 1619 } 1620 1621 static int rt73usb_get_tx_data_len(struct queue_entry *entry) 1622 { 1623 int length; 1624 1625 /* 1626 * The length _must_ be a multiple of 4, 1627 * but it must _not_ be a multiple of the USB packet size. 1628 */ 1629 length = roundup(entry->skb->len, 4); 1630 length += (4 * !(length % entry->queue->usb_maxpacket)); 1631 1632 return length; 1633 } 1634 1635 /* 1636 * RX control handlers 1637 */ 1638 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1) 1639 { 1640 u8 offset = rt2x00dev->lna_gain; 1641 u8 lna; 1642 1643 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA); 1644 switch (lna) { 1645 case 3: 1646 offset += 90; 1647 break; 1648 case 2: 1649 offset += 74; 1650 break; 1651 case 1: 1652 offset += 64; 1653 break; 1654 default: 1655 return 0; 1656 } 1657 1658 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { 1659 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) { 1660 if (lna == 3 || lna == 2) 1661 offset += 10; 1662 } else { 1663 if (lna == 3) 1664 offset += 6; 1665 else if (lna == 2) 1666 offset += 8; 1667 } 1668 } 1669 1670 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset; 1671 } 1672 1673 static void rt73usb_fill_rxdone(struct queue_entry *entry, 1674 struct rxdone_entry_desc *rxdesc) 1675 { 1676 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1677 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1678 __le32 *rxd = (__le32 *)entry->skb->data; 1679 u32 word0; 1680 u32 word1; 1681 1682 /* 1683 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of 1684 * frame data in rt2x00usb. 1685 */ 1686 memcpy(skbdesc->desc, rxd, skbdesc->desc_len); 1687 rxd = (__le32 *)skbdesc->desc; 1688 1689 /* 1690 * It is now safe to read the descriptor on all architectures. 1691 */ 1692 rt2x00_desc_read(rxd, 0, &word0); 1693 rt2x00_desc_read(rxd, 1, &word1); 1694 1695 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1696 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 1697 1698 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG); 1699 rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR); 1700 1701 if (rxdesc->cipher != CIPHER_NONE) { 1702 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]); 1703 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]); 1704 rxdesc->dev_flags |= RXDONE_CRYPTO_IV; 1705 1706 _rt2x00_desc_read(rxd, 4, &rxdesc->icv); 1707 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV; 1708 1709 /* 1710 * Hardware has stripped IV/EIV data from 802.11 frame during 1711 * decryption. It has provided the data separately but rt2x00lib 1712 * should decide if it should be reinserted. 1713 */ 1714 rxdesc->flags |= RX_FLAG_IV_STRIPPED; 1715 1716 /* 1717 * The hardware has already checked the Michael Mic and has 1718 * stripped it from the frame. Signal this to mac80211. 1719 */ 1720 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED; 1721 1722 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS) 1723 rxdesc->flags |= RX_FLAG_DECRYPTED; 1724 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC) 1725 rxdesc->flags |= RX_FLAG_MMIC_ERROR; 1726 } 1727 1728 /* 1729 * Obtain the status about this packet. 1730 * When frame was received with an OFDM bitrate, 1731 * the signal is the PLCP value. If it was received with 1732 * a CCK bitrate the signal is the rate in 100kbit/s. 1733 */ 1734 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL); 1735 rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1); 1736 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); 1737 1738 if (rt2x00_get_field32(word0, RXD_W0_OFDM)) 1739 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; 1740 else 1741 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE; 1742 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) 1743 rxdesc->dev_flags |= RXDONE_MY_BSS; 1744 1745 /* 1746 * Set skb pointers, and update frame information. 1747 */ 1748 skb_pull(entry->skb, entry->queue->desc_size); 1749 skb_trim(entry->skb, rxdesc->size); 1750 } 1751 1752 /* 1753 * Device probe functions. 1754 */ 1755 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev) 1756 { 1757 u16 word; 1758 u8 *mac; 1759 s8 value; 1760 1761 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE); 1762 1763 /* 1764 * Start validation of the data that has been read. 1765 */ 1766 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 1767 if (!is_valid_ether_addr(mac)) { 1768 eth_random_addr(mac); 1769 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac); 1770 } 1771 1772 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); 1773 if (word == 0xffff) { 1774 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); 1775 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 1776 ANTENNA_B); 1777 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 1778 ANTENNA_B); 1779 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0); 1780 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); 1781 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); 1782 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226); 1783 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); 1784 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 1785 } 1786 1787 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); 1788 if (word == 0xffff) { 1789 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0); 1790 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); 1791 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 1792 } 1793 1794 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word); 1795 if (word == 0xffff) { 1796 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0); 1797 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0); 1798 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0); 1799 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0); 1800 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0); 1801 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0); 1802 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0); 1803 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0); 1804 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE, 1805 LED_MODE_DEFAULT); 1806 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word); 1807 rt2x00_eeprom_dbg(rt2x00dev, "Led: 0x%04x\n", word); 1808 } 1809 1810 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); 1811 if (word == 0xffff) { 1812 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 1813 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0); 1814 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 1815 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); 1816 } 1817 1818 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word); 1819 if (word == 0xffff) { 1820 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); 1821 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); 1822 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); 1823 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word); 1824 } else { 1825 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1); 1826 if (value < -10 || value > 10) 1827 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); 1828 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2); 1829 if (value < -10 || value > 10) 1830 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); 1831 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); 1832 } 1833 1834 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word); 1835 if (word == 0xffff) { 1836 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); 1837 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); 1838 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); 1839 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word); 1840 } else { 1841 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1); 1842 if (value < -10 || value > 10) 1843 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); 1844 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2); 1845 if (value < -10 || value > 10) 1846 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); 1847 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); 1848 } 1849 1850 return 0; 1851 } 1852 1853 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev) 1854 { 1855 u32 reg; 1856 u16 value; 1857 u16 eeprom; 1858 1859 /* 1860 * Read EEPROM word for configuration. 1861 */ 1862 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); 1863 1864 /* 1865 * Identify RF chipset. 1866 */ 1867 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 1868 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, ®); 1869 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), 1870 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); 1871 1872 if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) { 1873 rt2x00_err(rt2x00dev, "Invalid RT chipset detected\n"); 1874 return -ENODEV; 1875 } 1876 1877 if (!rt2x00_rf(rt2x00dev, RF5226) && 1878 !rt2x00_rf(rt2x00dev, RF2528) && 1879 !rt2x00_rf(rt2x00dev, RF5225) && 1880 !rt2x00_rf(rt2x00dev, RF2527)) { 1881 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n"); 1882 return -ENODEV; 1883 } 1884 1885 /* 1886 * Identify default antenna configuration. 1887 */ 1888 rt2x00dev->default_ant.tx = 1889 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); 1890 rt2x00dev->default_ant.rx = 1891 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); 1892 1893 /* 1894 * Read the Frame type. 1895 */ 1896 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE)) 1897 __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags); 1898 1899 /* 1900 * Detect if this device has an hardware controlled radio. 1901 */ 1902 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) 1903 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 1904 1905 /* 1906 * Read frequency offset. 1907 */ 1908 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); 1909 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 1910 1911 /* 1912 * Read external LNA informations. 1913 */ 1914 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 1915 1916 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) { 1917 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); 1918 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); 1919 } 1920 1921 /* 1922 * Store led settings, for correct led behaviour. 1923 */ 1924 #ifdef CONFIG_RT2X00_LIB_LEDS 1925 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom); 1926 1927 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 1928 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 1929 if (value == LED_MODE_SIGNAL_STRENGTH) 1930 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual, 1931 LED_TYPE_QUALITY); 1932 1933 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value); 1934 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0, 1935 rt2x00_get_field16(eeprom, 1936 EEPROM_LED_POLARITY_GPIO_0)); 1937 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1, 1938 rt2x00_get_field16(eeprom, 1939 EEPROM_LED_POLARITY_GPIO_1)); 1940 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2, 1941 rt2x00_get_field16(eeprom, 1942 EEPROM_LED_POLARITY_GPIO_2)); 1943 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3, 1944 rt2x00_get_field16(eeprom, 1945 EEPROM_LED_POLARITY_GPIO_3)); 1946 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4, 1947 rt2x00_get_field16(eeprom, 1948 EEPROM_LED_POLARITY_GPIO_4)); 1949 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT, 1950 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT)); 1951 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG, 1952 rt2x00_get_field16(eeprom, 1953 EEPROM_LED_POLARITY_RDY_G)); 1954 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A, 1955 rt2x00_get_field16(eeprom, 1956 EEPROM_LED_POLARITY_RDY_A)); 1957 #endif /* CONFIG_RT2X00_LIB_LEDS */ 1958 1959 return 0; 1960 } 1961 1962 /* 1963 * RF value list for RF2528 1964 * Supports: 2.4 GHz 1965 */ 1966 static const struct rf_channel rf_vals_bg_2528[] = { 1967 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b }, 1968 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f }, 1969 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b }, 1970 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f }, 1971 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b }, 1972 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f }, 1973 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b }, 1974 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f }, 1975 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b }, 1976 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f }, 1977 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b }, 1978 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f }, 1979 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b }, 1980 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 }, 1981 }; 1982 1983 /* 1984 * RF value list for RF5226 1985 * Supports: 2.4 GHz & 5.2 GHz 1986 */ 1987 static const struct rf_channel rf_vals_5226[] = { 1988 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b }, 1989 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f }, 1990 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b }, 1991 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f }, 1992 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b }, 1993 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f }, 1994 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b }, 1995 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f }, 1996 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b }, 1997 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f }, 1998 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b }, 1999 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f }, 2000 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b }, 2001 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 }, 2002 2003 /* 802.11 UNI / HyperLan 2 */ 2004 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 }, 2005 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 }, 2006 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b }, 2007 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 }, 2008 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b }, 2009 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 }, 2010 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 }, 2011 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b }, 2012 2013 /* 802.11 HyperLan 2 */ 2014 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 }, 2015 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b }, 2016 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 }, 2017 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b }, 2018 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 }, 2019 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 }, 2020 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b }, 2021 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 }, 2022 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b }, 2023 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 }, 2024 2025 /* 802.11 UNII */ 2026 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 }, 2027 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f }, 2028 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 }, 2029 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 }, 2030 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f }, 2031 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 }, 2032 2033 /* MMAC(Japan)J52 ch 34,38,42,46 */ 2034 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b }, 2035 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 }, 2036 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b }, 2037 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 }, 2038 }; 2039 2040 /* 2041 * RF value list for RF5225 & RF2527 2042 * Supports: 2.4 GHz & 5.2 GHz 2043 */ 2044 static const struct rf_channel rf_vals_5225_2527[] = { 2045 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, 2046 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, 2047 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, 2048 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, 2049 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, 2050 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, 2051 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, 2052 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, 2053 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, 2054 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, 2055 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, 2056 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, 2057 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, 2058 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, 2059 2060 /* 802.11 UNI / HyperLan 2 */ 2061 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 }, 2062 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 }, 2063 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b }, 2064 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 }, 2065 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b }, 2066 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 }, 2067 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 }, 2068 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b }, 2069 2070 /* 802.11 HyperLan 2 */ 2071 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 }, 2072 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b }, 2073 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 }, 2074 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b }, 2075 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 }, 2076 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 }, 2077 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b }, 2078 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 }, 2079 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b }, 2080 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 }, 2081 2082 /* 802.11 UNII */ 2083 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 }, 2084 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f }, 2085 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 }, 2086 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 }, 2087 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f }, 2088 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 }, 2089 2090 /* MMAC(Japan)J52 ch 34,38,42,46 */ 2091 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b }, 2092 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 }, 2093 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b }, 2094 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 }, 2095 }; 2096 2097 2098 static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 2099 { 2100 struct hw_mode_spec *spec = &rt2x00dev->spec; 2101 struct channel_info *info; 2102 char *tx_power; 2103 unsigned int i; 2104 2105 /* 2106 * Initialize all hw fields. 2107 * 2108 * Don't set IEEE80211_HOST_BROADCAST_PS_BUFFERING unless we are 2109 * capable of sending the buffered frames out after the DTIM 2110 * transmission using rt2x00lib_beacondone. This will send out 2111 * multicast and broadcast traffic immediately instead of buffering it 2112 * infinitly and thus dropping it after some time. 2113 */ 2114 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); 2115 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); 2116 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); 2117 2118 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 2119 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 2120 rt2x00_eeprom_addr(rt2x00dev, 2121 EEPROM_MAC_ADDR_0)); 2122 2123 /* 2124 * Initialize hw_mode information. 2125 */ 2126 spec->supported_bands = SUPPORT_BAND_2GHZ; 2127 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 2128 2129 if (rt2x00_rf(rt2x00dev, RF2528)) { 2130 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528); 2131 spec->channels = rf_vals_bg_2528; 2132 } else if (rt2x00_rf(rt2x00dev, RF5226)) { 2133 spec->supported_bands |= SUPPORT_BAND_5GHZ; 2134 spec->num_channels = ARRAY_SIZE(rf_vals_5226); 2135 spec->channels = rf_vals_5226; 2136 } else if (rt2x00_rf(rt2x00dev, RF2527)) { 2137 spec->num_channels = 14; 2138 spec->channels = rf_vals_5225_2527; 2139 } else if (rt2x00_rf(rt2x00dev, RF5225)) { 2140 spec->supported_bands |= SUPPORT_BAND_5GHZ; 2141 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527); 2142 spec->channels = rf_vals_5225_2527; 2143 } 2144 2145 /* 2146 * Create channel information array 2147 */ 2148 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 2149 if (!info) 2150 return -ENOMEM; 2151 2152 spec->channels_info = info; 2153 2154 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); 2155 for (i = 0; i < 14; i++) { 2156 info[i].max_power = MAX_TXPOWER; 2157 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); 2158 } 2159 2160 if (spec->num_channels > 14) { 2161 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); 2162 for (i = 14; i < spec->num_channels; i++) { 2163 info[i].max_power = MAX_TXPOWER; 2164 info[i].default_power1 = 2165 TXPOWER_FROM_DEV(tx_power[i - 14]); 2166 } 2167 } 2168 2169 return 0; 2170 } 2171 2172 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev) 2173 { 2174 int retval; 2175 u32 reg; 2176 2177 /* 2178 * Allocate eeprom data. 2179 */ 2180 retval = rt73usb_validate_eeprom(rt2x00dev); 2181 if (retval) 2182 return retval; 2183 2184 retval = rt73usb_init_eeprom(rt2x00dev); 2185 if (retval) 2186 return retval; 2187 2188 /* 2189 * Enable rfkill polling by setting GPIO direction of the 2190 * rfkill switch GPIO pin correctly. 2191 */ 2192 rt2x00usb_register_read(rt2x00dev, MAC_CSR13, ®); 2193 rt2x00_set_field32(®, MAC_CSR13_DIR7, 0); 2194 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, reg); 2195 2196 /* 2197 * Initialize hw specifications. 2198 */ 2199 retval = rt73usb_probe_hw_mode(rt2x00dev); 2200 if (retval) 2201 return retval; 2202 2203 /* 2204 * This device has multiple filters for control frames, 2205 * but has no a separate filter for PS Poll frames. 2206 */ 2207 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); 2208 2209 /* 2210 * This device requires firmware. 2211 */ 2212 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); 2213 if (!modparam_nohwcrypt) 2214 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); 2215 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 2216 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); 2217 2218 /* 2219 * Set the rssi offset. 2220 */ 2221 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 2222 2223 return 0; 2224 } 2225 2226 /* 2227 * IEEE80211 stack callback functions. 2228 */ 2229 static int rt73usb_conf_tx(struct ieee80211_hw *hw, 2230 struct ieee80211_vif *vif, u16 queue_idx, 2231 const struct ieee80211_tx_queue_params *params) 2232 { 2233 struct rt2x00_dev *rt2x00dev = hw->priv; 2234 struct data_queue *queue; 2235 struct rt2x00_field32 field; 2236 int retval; 2237 u32 reg; 2238 u32 offset; 2239 2240 /* 2241 * First pass the configuration through rt2x00lib, that will 2242 * update the queue settings and validate the input. After that 2243 * we are free to update the registers based on the value 2244 * in the queue parameter. 2245 */ 2246 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params); 2247 if (retval) 2248 return retval; 2249 2250 /* 2251 * We only need to perform additional register initialization 2252 * for WMM queues/ 2253 */ 2254 if (queue_idx >= 4) 2255 return 0; 2256 2257 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 2258 2259 /* Update WMM TXOP register */ 2260 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2))); 2261 field.bit_offset = (queue_idx & 1) * 16; 2262 field.bit_mask = 0xffff << field.bit_offset; 2263 2264 rt2x00usb_register_read(rt2x00dev, offset, ®); 2265 rt2x00_set_field32(®, field, queue->txop); 2266 rt2x00usb_register_write(rt2x00dev, offset, reg); 2267 2268 /* Update WMM registers */ 2269 field.bit_offset = queue_idx * 4; 2270 field.bit_mask = 0xf << field.bit_offset; 2271 2272 rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, ®); 2273 rt2x00_set_field32(®, field, queue->aifs); 2274 rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg); 2275 2276 rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, ®); 2277 rt2x00_set_field32(®, field, queue->cw_min); 2278 rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg); 2279 2280 rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, ®); 2281 rt2x00_set_field32(®, field, queue->cw_max); 2282 rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg); 2283 2284 return 0; 2285 } 2286 2287 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 2288 { 2289 struct rt2x00_dev *rt2x00dev = hw->priv; 2290 u64 tsf; 2291 u32 reg; 2292 2293 rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, ®); 2294 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; 2295 rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, ®); 2296 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); 2297 2298 return tsf; 2299 } 2300 2301 static const struct ieee80211_ops rt73usb_mac80211_ops = { 2302 .tx = rt2x00mac_tx, 2303 .start = rt2x00mac_start, 2304 .stop = rt2x00mac_stop, 2305 .add_interface = rt2x00mac_add_interface, 2306 .remove_interface = rt2x00mac_remove_interface, 2307 .config = rt2x00mac_config, 2308 .configure_filter = rt2x00mac_configure_filter, 2309 .set_tim = rt2x00mac_set_tim, 2310 .set_key = rt2x00mac_set_key, 2311 .sw_scan_start = rt2x00mac_sw_scan_start, 2312 .sw_scan_complete = rt2x00mac_sw_scan_complete, 2313 .get_stats = rt2x00mac_get_stats, 2314 .bss_info_changed = rt2x00mac_bss_info_changed, 2315 .conf_tx = rt73usb_conf_tx, 2316 .get_tsf = rt73usb_get_tsf, 2317 .rfkill_poll = rt2x00mac_rfkill_poll, 2318 .flush = rt2x00mac_flush, 2319 .set_antenna = rt2x00mac_set_antenna, 2320 .get_antenna = rt2x00mac_get_antenna, 2321 .get_ringparam = rt2x00mac_get_ringparam, 2322 .tx_frames_pending = rt2x00mac_tx_frames_pending, 2323 }; 2324 2325 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = { 2326 .probe_hw = rt73usb_probe_hw, 2327 .get_firmware_name = rt73usb_get_firmware_name, 2328 .check_firmware = rt73usb_check_firmware, 2329 .load_firmware = rt73usb_load_firmware, 2330 .initialize = rt2x00usb_initialize, 2331 .uninitialize = rt2x00usb_uninitialize, 2332 .clear_entry = rt2x00usb_clear_entry, 2333 .set_device_state = rt73usb_set_device_state, 2334 .rfkill_poll = rt73usb_rfkill_poll, 2335 .link_stats = rt73usb_link_stats, 2336 .reset_tuner = rt73usb_reset_tuner, 2337 .link_tuner = rt73usb_link_tuner, 2338 .watchdog = rt2x00usb_watchdog, 2339 .start_queue = rt73usb_start_queue, 2340 .kick_queue = rt2x00usb_kick_queue, 2341 .stop_queue = rt73usb_stop_queue, 2342 .flush_queue = rt2x00usb_flush_queue, 2343 .write_tx_desc = rt73usb_write_tx_desc, 2344 .write_beacon = rt73usb_write_beacon, 2345 .clear_beacon = rt73usb_clear_beacon, 2346 .get_tx_data_len = rt73usb_get_tx_data_len, 2347 .fill_rxdone = rt73usb_fill_rxdone, 2348 .config_shared_key = rt73usb_config_shared_key, 2349 .config_pairwise_key = rt73usb_config_pairwise_key, 2350 .config_filter = rt73usb_config_filter, 2351 .config_intf = rt73usb_config_intf, 2352 .config_erp = rt73usb_config_erp, 2353 .config_ant = rt73usb_config_ant, 2354 .config = rt73usb_config, 2355 }; 2356 2357 static void rt73usb_queue_init(struct data_queue *queue) 2358 { 2359 switch (queue->qid) { 2360 case QID_RX: 2361 queue->limit = 32; 2362 queue->data_size = DATA_FRAME_SIZE; 2363 queue->desc_size = RXD_DESC_SIZE; 2364 queue->priv_size = sizeof(struct queue_entry_priv_usb); 2365 break; 2366 2367 case QID_AC_VO: 2368 case QID_AC_VI: 2369 case QID_AC_BE: 2370 case QID_AC_BK: 2371 queue->limit = 32; 2372 queue->data_size = DATA_FRAME_SIZE; 2373 queue->desc_size = TXD_DESC_SIZE; 2374 queue->priv_size = sizeof(struct queue_entry_priv_usb); 2375 break; 2376 2377 case QID_BEACON: 2378 queue->limit = 4; 2379 queue->data_size = MGMT_FRAME_SIZE; 2380 queue->desc_size = TXINFO_SIZE; 2381 queue->priv_size = sizeof(struct queue_entry_priv_usb); 2382 break; 2383 2384 case QID_ATIM: 2385 /* fallthrough */ 2386 default: 2387 BUG(); 2388 break; 2389 } 2390 } 2391 2392 static const struct rt2x00_ops rt73usb_ops = { 2393 .name = KBUILD_MODNAME, 2394 .max_ap_intf = 4, 2395 .eeprom_size = EEPROM_SIZE, 2396 .rf_size = RF_SIZE, 2397 .tx_queues = NUM_TX_QUEUES, 2398 .queue_init = rt73usb_queue_init, 2399 .lib = &rt73usb_rt2x00_ops, 2400 .hw = &rt73usb_mac80211_ops, 2401 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 2402 .debugfs = &rt73usb_rt2x00debug, 2403 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 2404 }; 2405 2406 /* 2407 * rt73usb module information. 2408 */ 2409 static struct usb_device_id rt73usb_device_table[] = { 2410 /* AboCom */ 2411 { USB_DEVICE(0x07b8, 0xb21b) }, 2412 { USB_DEVICE(0x07b8, 0xb21c) }, 2413 { USB_DEVICE(0x07b8, 0xb21d) }, 2414 { USB_DEVICE(0x07b8, 0xb21e) }, 2415 { USB_DEVICE(0x07b8, 0xb21f) }, 2416 /* AL */ 2417 { USB_DEVICE(0x14b2, 0x3c10) }, 2418 /* Amigo */ 2419 { USB_DEVICE(0x148f, 0x9021) }, 2420 { USB_DEVICE(0x0eb0, 0x9021) }, 2421 /* AMIT */ 2422 { USB_DEVICE(0x18c5, 0x0002) }, 2423 /* Askey */ 2424 { USB_DEVICE(0x1690, 0x0722) }, 2425 /* ASUS */ 2426 { USB_DEVICE(0x0b05, 0x1723) }, 2427 { USB_DEVICE(0x0b05, 0x1724) }, 2428 /* Belkin */ 2429 { USB_DEVICE(0x050d, 0x7050) }, /* FCC ID: K7SF5D7050B ver. 3.x */ 2430 { USB_DEVICE(0x050d, 0x705a) }, 2431 { USB_DEVICE(0x050d, 0x905b) }, 2432 { USB_DEVICE(0x050d, 0x905c) }, 2433 /* Billionton */ 2434 { USB_DEVICE(0x1631, 0xc019) }, 2435 { USB_DEVICE(0x08dd, 0x0120) }, 2436 /* Buffalo */ 2437 { USB_DEVICE(0x0411, 0x00d8) }, 2438 { USB_DEVICE(0x0411, 0x00d9) }, 2439 { USB_DEVICE(0x0411, 0x00e6) }, 2440 { USB_DEVICE(0x0411, 0x00f4) }, 2441 { USB_DEVICE(0x0411, 0x0116) }, 2442 { USB_DEVICE(0x0411, 0x0119) }, 2443 { USB_DEVICE(0x0411, 0x0137) }, 2444 /* CEIVA */ 2445 { USB_DEVICE(0x178d, 0x02be) }, 2446 /* CNet */ 2447 { USB_DEVICE(0x1371, 0x9022) }, 2448 { USB_DEVICE(0x1371, 0x9032) }, 2449 /* Conceptronic */ 2450 { USB_DEVICE(0x14b2, 0x3c22) }, 2451 /* Corega */ 2452 { USB_DEVICE(0x07aa, 0x002e) }, 2453 /* D-Link */ 2454 { USB_DEVICE(0x07d1, 0x3c03) }, 2455 { USB_DEVICE(0x07d1, 0x3c04) }, 2456 { USB_DEVICE(0x07d1, 0x3c06) }, 2457 { USB_DEVICE(0x07d1, 0x3c07) }, 2458 /* Edimax */ 2459 { USB_DEVICE(0x7392, 0x7318) }, 2460 { USB_DEVICE(0x7392, 0x7618) }, 2461 /* EnGenius */ 2462 { USB_DEVICE(0x1740, 0x3701) }, 2463 /* Gemtek */ 2464 { USB_DEVICE(0x15a9, 0x0004) }, 2465 /* Gigabyte */ 2466 { USB_DEVICE(0x1044, 0x8008) }, 2467 { USB_DEVICE(0x1044, 0x800a) }, 2468 /* Huawei-3Com */ 2469 { USB_DEVICE(0x1472, 0x0009) }, 2470 /* Hercules */ 2471 { USB_DEVICE(0x06f8, 0xe002) }, 2472 { USB_DEVICE(0x06f8, 0xe010) }, 2473 { USB_DEVICE(0x06f8, 0xe020) }, 2474 /* Linksys */ 2475 { USB_DEVICE(0x13b1, 0x0020) }, 2476 { USB_DEVICE(0x13b1, 0x0023) }, 2477 { USB_DEVICE(0x13b1, 0x0028) }, 2478 /* MSI */ 2479 { USB_DEVICE(0x0db0, 0x4600) }, 2480 { USB_DEVICE(0x0db0, 0x6877) }, 2481 { USB_DEVICE(0x0db0, 0x6874) }, 2482 { USB_DEVICE(0x0db0, 0xa861) }, 2483 { USB_DEVICE(0x0db0, 0xa874) }, 2484 /* Ovislink */ 2485 { USB_DEVICE(0x1b75, 0x7318) }, 2486 /* Ralink */ 2487 { USB_DEVICE(0x04bb, 0x093d) }, 2488 { USB_DEVICE(0x148f, 0x2573) }, 2489 { USB_DEVICE(0x148f, 0x2671) }, 2490 { USB_DEVICE(0x0812, 0x3101) }, 2491 /* Qcom */ 2492 { USB_DEVICE(0x18e8, 0x6196) }, 2493 { USB_DEVICE(0x18e8, 0x6229) }, 2494 { USB_DEVICE(0x18e8, 0x6238) }, 2495 /* Samsung */ 2496 { USB_DEVICE(0x04e8, 0x4471) }, 2497 /* Senao */ 2498 { USB_DEVICE(0x1740, 0x7100) }, 2499 /* Sitecom */ 2500 { USB_DEVICE(0x0df6, 0x0024) }, 2501 { USB_DEVICE(0x0df6, 0x0027) }, 2502 { USB_DEVICE(0x0df6, 0x002f) }, 2503 { USB_DEVICE(0x0df6, 0x90ac) }, 2504 { USB_DEVICE(0x0df6, 0x9712) }, 2505 /* Surecom */ 2506 { USB_DEVICE(0x0769, 0x31f3) }, 2507 /* Tilgin */ 2508 { USB_DEVICE(0x6933, 0x5001) }, 2509 /* Philips */ 2510 { USB_DEVICE(0x0471, 0x200a) }, 2511 /* Planex */ 2512 { USB_DEVICE(0x2019, 0xab01) }, 2513 { USB_DEVICE(0x2019, 0xab50) }, 2514 /* WideTell */ 2515 { USB_DEVICE(0x7167, 0x3840) }, 2516 /* Zcom */ 2517 { USB_DEVICE(0x0cde, 0x001c) }, 2518 /* ZyXEL */ 2519 { USB_DEVICE(0x0586, 0x3415) }, 2520 { 0, } 2521 }; 2522 2523 MODULE_AUTHOR(DRV_PROJECT); 2524 MODULE_VERSION(DRV_VERSION); 2525 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver."); 2526 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards"); 2527 MODULE_DEVICE_TABLE(usb, rt73usb_device_table); 2528 MODULE_FIRMWARE(FIRMWARE_RT2571); 2529 MODULE_LICENSE("GPL"); 2530 2531 static int rt73usb_probe(struct usb_interface *usb_intf, 2532 const struct usb_device_id *id) 2533 { 2534 return rt2x00usb_probe(usb_intf, &rt73usb_ops); 2535 } 2536 2537 static struct usb_driver rt73usb_driver = { 2538 .name = KBUILD_MODNAME, 2539 .id_table = rt73usb_device_table, 2540 .probe = rt73usb_probe, 2541 .disconnect = rt2x00usb_disconnect, 2542 .suspend = rt2x00usb_suspend, 2543 .resume = rt2x00usb_resume, 2544 .reset_resume = rt2x00usb_resume, 2545 .disable_hub_initiated_lpm = 1, 2546 }; 2547 2548 module_usb_driver(rt73usb_driver); 2549