1 /*
2 	Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 	<http://rt2x00.serialmonkey.com>
4 
5 	This program is free software; you can redistribute it and/or modify
6 	it under the terms of the GNU General Public License as published by
7 	the Free Software Foundation; either version 2 of the License, or
8 	(at your option) any later version.
9 
10 	This program is distributed in the hope that it will be useful,
11 	but WITHOUT ANY WARRANTY; without even the implied warranty of
12 	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 	GNU General Public License for more details.
14 
15 	You should have received a copy of the GNU General Public License
16 	along with this program; if not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 /*
20 	Module: rt73usb
21 	Abstract: rt73usb device specific routines.
22 	Supported chipsets: rt2571W & rt2671.
23  */
24 
25 #include <linux/crc-itu-t.h>
26 #include <linux/delay.h>
27 #include <linux/etherdevice.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/slab.h>
31 #include <linux/usb.h>
32 
33 #include "rt2x00.h"
34 #include "rt2x00usb.h"
35 #include "rt73usb.h"
36 
37 /*
38  * Allow hardware encryption to be disabled.
39  */
40 static bool modparam_nohwcrypt;
41 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, 0444);
42 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
43 
44 /*
45  * Register access.
46  * All access to the CSR registers will go through the methods
47  * rt2x00usb_register_read and rt2x00usb_register_write.
48  * BBP and RF register require indirect register access,
49  * and use the CSR registers BBPCSR and RFCSR to achieve this.
50  * These indirect registers work with busy bits,
51  * and we will try maximal REGISTER_BUSY_COUNT times to access
52  * the register while taking a REGISTER_BUSY_DELAY us delay
53  * between each attampt. When the busy bit is still set at that time,
54  * the access attempt is considered to have failed,
55  * and we will print an error.
56  * The _lock versions must be used if you already hold the csr_mutex
57  */
58 #define WAIT_FOR_BBP(__dev, __reg) \
59 	rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
60 #define WAIT_FOR_RF(__dev, __reg) \
61 	rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
62 
63 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
64 			      const unsigned int word, const u8 value)
65 {
66 	u32 reg;
67 
68 	mutex_lock(&rt2x00dev->csr_mutex);
69 
70 	/*
71 	 * Wait until the BBP becomes available, afterwards we
72 	 * can safely write the new data into the register.
73 	 */
74 	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
75 		reg = 0;
76 		rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
77 		rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
78 		rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
79 		rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
80 
81 		rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
82 	}
83 
84 	mutex_unlock(&rt2x00dev->csr_mutex);
85 }
86 
87 static u8 rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
88 			   const unsigned int word)
89 {
90 	u32 reg;
91 	u8 value;
92 
93 	mutex_lock(&rt2x00dev->csr_mutex);
94 
95 	/*
96 	 * Wait until the BBP becomes available, afterwards we
97 	 * can safely write the read request into the register.
98 	 * After the data has been written, we wait until hardware
99 	 * returns the correct value, if at any time the register
100 	 * doesn't become available in time, reg will be 0xffffffff
101 	 * which means we return 0xff to the caller.
102 	 */
103 	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
104 		reg = 0;
105 		rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
106 		rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
107 		rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
108 
109 		rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
110 
111 		WAIT_FOR_BBP(rt2x00dev, &reg);
112 	}
113 
114 	value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
115 
116 	mutex_unlock(&rt2x00dev->csr_mutex);
117 
118 	return value;
119 }
120 
121 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
122 			     const unsigned int word, const u32 value)
123 {
124 	u32 reg;
125 
126 	mutex_lock(&rt2x00dev->csr_mutex);
127 
128 	/*
129 	 * Wait until the RF becomes available, afterwards we
130 	 * can safely write the new data into the register.
131 	 */
132 	if (WAIT_FOR_RF(rt2x00dev, &reg)) {
133 		reg = 0;
134 		rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
135 		/*
136 		 * RF5225 and RF2527 contain 21 bits per RF register value,
137 		 * all others contain 20 bits.
138 		 */
139 		rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
140 				   20 + (rt2x00_rf(rt2x00dev, RF5225) ||
141 					 rt2x00_rf(rt2x00dev, RF2527)));
142 		rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
143 		rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
144 
145 		rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
146 		rt2x00_rf_write(rt2x00dev, word, value);
147 	}
148 
149 	mutex_unlock(&rt2x00dev->csr_mutex);
150 }
151 
152 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
153 static const struct rt2x00debug rt73usb_rt2x00debug = {
154 	.owner	= THIS_MODULE,
155 	.csr	= {
156 		.read		= rt2x00usb_register_read,
157 		.write		= rt2x00usb_register_write,
158 		.flags		= RT2X00DEBUGFS_OFFSET,
159 		.word_base	= CSR_REG_BASE,
160 		.word_size	= sizeof(u32),
161 		.word_count	= CSR_REG_SIZE / sizeof(u32),
162 	},
163 	.eeprom	= {
164 		.read		= rt2x00_eeprom_read,
165 		.write		= rt2x00_eeprom_write,
166 		.word_base	= EEPROM_BASE,
167 		.word_size	= sizeof(u16),
168 		.word_count	= EEPROM_SIZE / sizeof(u16),
169 	},
170 	.bbp	= {
171 		.read		= rt73usb_bbp_read,
172 		.write		= rt73usb_bbp_write,
173 		.word_base	= BBP_BASE,
174 		.word_size	= sizeof(u8),
175 		.word_count	= BBP_SIZE / sizeof(u8),
176 	},
177 	.rf	= {
178 		.read		= rt2x00_rf_read,
179 		.write		= rt73usb_rf_write,
180 		.word_base	= RF_BASE,
181 		.word_size	= sizeof(u32),
182 		.word_count	= RF_SIZE / sizeof(u32),
183 	},
184 };
185 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
186 
187 static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
188 {
189 	u32 reg;
190 
191 	reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR13);
192 	return rt2x00_get_field32(reg, MAC_CSR13_VAL7);
193 }
194 
195 #ifdef CONFIG_RT2X00_LIB_LEDS
196 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
197 				   enum led_brightness brightness)
198 {
199 	struct rt2x00_led *led =
200 	   container_of(led_cdev, struct rt2x00_led, led_dev);
201 	unsigned int enabled = brightness != LED_OFF;
202 	unsigned int a_mode =
203 	    (enabled && led->rt2x00dev->curr_band == NL80211_BAND_5GHZ);
204 	unsigned int bg_mode =
205 	    (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
206 
207 	if (led->type == LED_TYPE_RADIO) {
208 		rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
209 				   MCU_LEDCS_RADIO_STATUS, enabled);
210 
211 		rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
212 					    0, led->rt2x00dev->led_mcu_reg,
213 					    REGISTER_TIMEOUT);
214 	} else if (led->type == LED_TYPE_ASSOC) {
215 		rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
216 				   MCU_LEDCS_LINK_BG_STATUS, bg_mode);
217 		rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
218 				   MCU_LEDCS_LINK_A_STATUS, a_mode);
219 
220 		rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
221 					    0, led->rt2x00dev->led_mcu_reg,
222 					    REGISTER_TIMEOUT);
223 	} else if (led->type == LED_TYPE_QUALITY) {
224 		/*
225 		 * The brightness is divided into 6 levels (0 - 5),
226 		 * this means we need to convert the brightness
227 		 * argument into the matching level within that range.
228 		 */
229 		rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
230 					    brightness / (LED_FULL / 6),
231 					    led->rt2x00dev->led_mcu_reg,
232 					    REGISTER_TIMEOUT);
233 	}
234 }
235 
236 static int rt73usb_blink_set(struct led_classdev *led_cdev,
237 			     unsigned long *delay_on,
238 			     unsigned long *delay_off)
239 {
240 	struct rt2x00_led *led =
241 	    container_of(led_cdev, struct rt2x00_led, led_dev);
242 	u32 reg;
243 
244 	reg = rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14);
245 	rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
246 	rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
247 	rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
248 
249 	return 0;
250 }
251 
252 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
253 			     struct rt2x00_led *led,
254 			     enum led_type type)
255 {
256 	led->rt2x00dev = rt2x00dev;
257 	led->type = type;
258 	led->led_dev.brightness_set = rt73usb_brightness_set;
259 	led->led_dev.blink_set = rt73usb_blink_set;
260 	led->flags = LED_INITIALIZED;
261 }
262 #endif /* CONFIG_RT2X00_LIB_LEDS */
263 
264 /*
265  * Configuration handlers.
266  */
267 static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
268 				     struct rt2x00lib_crypto *crypto,
269 				     struct ieee80211_key_conf *key)
270 {
271 	struct hw_key_entry key_entry;
272 	struct rt2x00_field32 field;
273 	u32 mask;
274 	u32 reg;
275 
276 	if (crypto->cmd == SET_KEY) {
277 		/*
278 		 * rt2x00lib can't determine the correct free
279 		 * key_idx for shared keys. We have 1 register
280 		 * with key valid bits. The goal is simple, read
281 		 * the register, if that is full we have no slots
282 		 * left.
283 		 * Note that each BSS is allowed to have up to 4
284 		 * shared keys, so put a mask over the allowed
285 		 * entries.
286 		 */
287 		mask = (0xf << crypto->bssidx);
288 
289 		reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR0);
290 		reg &= mask;
291 
292 		if (reg && reg == mask)
293 			return -ENOSPC;
294 
295 		key->hw_key_idx += reg ? ffz(reg) : 0;
296 
297 		/*
298 		 * Upload key to hardware
299 		 */
300 		memcpy(key_entry.key, crypto->key,
301 		       sizeof(key_entry.key));
302 		memcpy(key_entry.tx_mic, crypto->tx_mic,
303 		       sizeof(key_entry.tx_mic));
304 		memcpy(key_entry.rx_mic, crypto->rx_mic,
305 		       sizeof(key_entry.rx_mic));
306 
307 		reg = SHARED_KEY_ENTRY(key->hw_key_idx);
308 		rt2x00usb_register_multiwrite(rt2x00dev, reg,
309 					      &key_entry, sizeof(key_entry));
310 
311 		/*
312 		 * The cipher types are stored over 2 registers.
313 		 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
314 		 * bssidx 1 and 2 keys are stored in SEC_CSR5.
315 		 * Using the correct defines correctly will cause overhead,
316 		 * so just calculate the correct offset.
317 		 */
318 		if (key->hw_key_idx < 8) {
319 			field.bit_offset = (3 * key->hw_key_idx);
320 			field.bit_mask = 0x7 << field.bit_offset;
321 
322 			reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR1);
323 			rt2x00_set_field32(&reg, field, crypto->cipher);
324 			rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
325 		} else {
326 			field.bit_offset = (3 * (key->hw_key_idx - 8));
327 			field.bit_mask = 0x7 << field.bit_offset;
328 
329 			reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR5);
330 			rt2x00_set_field32(&reg, field, crypto->cipher);
331 			rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
332 		}
333 
334 		/*
335 		 * The driver does not support the IV/EIV generation
336 		 * in hardware. However it doesn't support the IV/EIV
337 		 * inside the ieee80211 frame either, but requires it
338 		 * to be provided separately for the descriptor.
339 		 * rt2x00lib will cut the IV/EIV data out of all frames
340 		 * given to us by mac80211, but we must tell mac80211
341 		 * to generate the IV/EIV data.
342 		 */
343 		key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
344 	}
345 
346 	/*
347 	 * SEC_CSR0 contains only single-bit fields to indicate
348 	 * a particular key is valid. Because using the FIELD32()
349 	 * defines directly will cause a lot of overhead we use
350 	 * a calculation to determine the correct bit directly.
351 	 */
352 	mask = 1 << key->hw_key_idx;
353 
354 	reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR0);
355 	if (crypto->cmd == SET_KEY)
356 		reg |= mask;
357 	else if (crypto->cmd == DISABLE_KEY)
358 		reg &= ~mask;
359 	rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
360 
361 	return 0;
362 }
363 
364 static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
365 				       struct rt2x00lib_crypto *crypto,
366 				       struct ieee80211_key_conf *key)
367 {
368 	struct hw_pairwise_ta_entry addr_entry;
369 	struct hw_key_entry key_entry;
370 	u32 mask;
371 	u32 reg;
372 
373 	if (crypto->cmd == SET_KEY) {
374 		/*
375 		 * rt2x00lib can't determine the correct free
376 		 * key_idx for pairwise keys. We have 2 registers
377 		 * with key valid bits. The goal is simple, read
378 		 * the first register, if that is full move to
379 		 * the next register.
380 		 * When both registers are full, we drop the key,
381 		 * otherwise we use the first invalid entry.
382 		 */
383 		reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR2);
384 		if (reg && reg == ~0) {
385 			key->hw_key_idx = 32;
386 			reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR3);
387 			if (reg && reg == ~0)
388 				return -ENOSPC;
389 		}
390 
391 		key->hw_key_idx += reg ? ffz(reg) : 0;
392 
393 		/*
394 		 * Upload key to hardware
395 		 */
396 		memcpy(key_entry.key, crypto->key,
397 		       sizeof(key_entry.key));
398 		memcpy(key_entry.tx_mic, crypto->tx_mic,
399 		       sizeof(key_entry.tx_mic));
400 		memcpy(key_entry.rx_mic, crypto->rx_mic,
401 		       sizeof(key_entry.rx_mic));
402 
403 		reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
404 		rt2x00usb_register_multiwrite(rt2x00dev, reg,
405 					      &key_entry, sizeof(key_entry));
406 
407 		/*
408 		 * Send the address and cipher type to the hardware register.
409 		 */
410 		memset(&addr_entry, 0, sizeof(addr_entry));
411 		memcpy(&addr_entry, crypto->address, ETH_ALEN);
412 		addr_entry.cipher = crypto->cipher;
413 
414 		reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
415 		rt2x00usb_register_multiwrite(rt2x00dev, reg,
416 					    &addr_entry, sizeof(addr_entry));
417 
418 		/*
419 		 * Enable pairwise lookup table for given BSS idx,
420 		 * without this received frames will not be decrypted
421 		 * by the hardware.
422 		 */
423 		reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR4);
424 		reg |= (1 << crypto->bssidx);
425 		rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
426 
427 		/*
428 		 * The driver does not support the IV/EIV generation
429 		 * in hardware. However it doesn't support the IV/EIV
430 		 * inside the ieee80211 frame either, but requires it
431 		 * to be provided separately for the descriptor.
432 		 * rt2x00lib will cut the IV/EIV data out of all frames
433 		 * given to us by mac80211, but we must tell mac80211
434 		 * to generate the IV/EIV data.
435 		 */
436 		key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
437 	}
438 
439 	/*
440 	 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
441 	 * a particular key is valid. Because using the FIELD32()
442 	 * defines directly will cause a lot of overhead we use
443 	 * a calculation to determine the correct bit directly.
444 	 */
445 	if (key->hw_key_idx < 32) {
446 		mask = 1 << key->hw_key_idx;
447 
448 		reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR2);
449 		if (crypto->cmd == SET_KEY)
450 			reg |= mask;
451 		else if (crypto->cmd == DISABLE_KEY)
452 			reg &= ~mask;
453 		rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
454 	} else {
455 		mask = 1 << (key->hw_key_idx - 32);
456 
457 		reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR3);
458 		if (crypto->cmd == SET_KEY)
459 			reg |= mask;
460 		else if (crypto->cmd == DISABLE_KEY)
461 			reg &= ~mask;
462 		rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
463 	}
464 
465 	return 0;
466 }
467 
468 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
469 				  const unsigned int filter_flags)
470 {
471 	u32 reg;
472 
473 	/*
474 	 * Start configuration steps.
475 	 * Note that the version error will always be dropped
476 	 * and broadcast frames will always be accepted since
477 	 * there is no filter for it at this time.
478 	 */
479 	reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR0);
480 	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
481 			   !(filter_flags & FIF_FCSFAIL));
482 	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
483 			   !(filter_flags & FIF_PLCPFAIL));
484 	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
485 			   !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
486 	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
487 			   !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
488 	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
489 			   !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) &&
490 			   !rt2x00dev->intf_ap_count);
491 	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
492 	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
493 			   !(filter_flags & FIF_ALLMULTI));
494 	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
495 	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
496 			   !(filter_flags & FIF_CONTROL));
497 	rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
498 }
499 
500 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
501 				struct rt2x00_intf *intf,
502 				struct rt2x00intf_conf *conf,
503 				const unsigned int flags)
504 {
505 	u32 reg;
506 
507 	if (flags & CONFIG_UPDATE_TYPE) {
508 		/*
509 		 * Enable synchronisation.
510 		 */
511 		reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9);
512 		rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
513 		rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
514 	}
515 
516 	if (flags & CONFIG_UPDATE_MAC) {
517 		reg = le32_to_cpu(conf->mac[1]);
518 		rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
519 		conf->mac[1] = cpu_to_le32(reg);
520 
521 		rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
522 					    conf->mac, sizeof(conf->mac));
523 	}
524 
525 	if (flags & CONFIG_UPDATE_BSSID) {
526 		reg = le32_to_cpu(conf->bssid[1]);
527 		rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
528 		conf->bssid[1] = cpu_to_le32(reg);
529 
530 		rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
531 					    conf->bssid, sizeof(conf->bssid));
532 	}
533 }
534 
535 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
536 			       struct rt2x00lib_erp *erp,
537 			       u32 changed)
538 {
539 	u32 reg;
540 
541 	reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR0);
542 	rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
543 	rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
544 	rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
545 
546 	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
547 		reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR4);
548 		rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
549 		rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
550 				   !!erp->short_preamble);
551 		rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
552 	}
553 
554 	if (changed & BSS_CHANGED_BASIC_RATES)
555 		rt2x00usb_register_write(rt2x00dev, TXRX_CSR5,
556 					 erp->basic_rates);
557 
558 	if (changed & BSS_CHANGED_BEACON_INT) {
559 		reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9);
560 		rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
561 				   erp->beacon_int * 16);
562 		rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
563 	}
564 
565 	if (changed & BSS_CHANGED_ERP_SLOT) {
566 		reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR9);
567 		rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
568 		rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
569 
570 		reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR8);
571 		rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
572 		rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
573 		rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
574 		rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
575 	}
576 }
577 
578 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
579 				      struct antenna_setup *ant)
580 {
581 	u8 r3;
582 	u8 r4;
583 	u8 r77;
584 	u8 temp;
585 
586 	r3 = rt73usb_bbp_read(rt2x00dev, 3);
587 	r4 = rt73usb_bbp_read(rt2x00dev, 4);
588 	r77 = rt73usb_bbp_read(rt2x00dev, 77);
589 
590 	rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
591 
592 	/*
593 	 * Configure the RX antenna.
594 	 */
595 	switch (ant->rx) {
596 	case ANTENNA_HW_DIVERSITY:
597 		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
598 		temp = !rt2x00_has_cap_frame_type(rt2x00dev) &&
599 		       (rt2x00dev->curr_band != NL80211_BAND_5GHZ);
600 		rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
601 		break;
602 	case ANTENNA_A:
603 		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
604 		rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
605 		if (rt2x00dev->curr_band == NL80211_BAND_5GHZ)
606 			rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
607 		else
608 			rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
609 		break;
610 	case ANTENNA_B:
611 	default:
612 		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
613 		rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
614 		if (rt2x00dev->curr_band == NL80211_BAND_5GHZ)
615 			rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
616 		else
617 			rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
618 		break;
619 	}
620 
621 	rt73usb_bbp_write(rt2x00dev, 77, r77);
622 	rt73usb_bbp_write(rt2x00dev, 3, r3);
623 	rt73usb_bbp_write(rt2x00dev, 4, r4);
624 }
625 
626 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
627 				      struct antenna_setup *ant)
628 {
629 	u8 r3;
630 	u8 r4;
631 	u8 r77;
632 
633 	r3 = rt73usb_bbp_read(rt2x00dev, 3);
634 	r4 = rt73usb_bbp_read(rt2x00dev, 4);
635 	r77 = rt73usb_bbp_read(rt2x00dev, 77);
636 
637 	rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
638 	rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
639 			  !rt2x00_has_cap_frame_type(rt2x00dev));
640 
641 	/*
642 	 * Configure the RX antenna.
643 	 */
644 	switch (ant->rx) {
645 	case ANTENNA_HW_DIVERSITY:
646 		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
647 		break;
648 	case ANTENNA_A:
649 		rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
650 		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
651 		break;
652 	case ANTENNA_B:
653 	default:
654 		rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
655 		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
656 		break;
657 	}
658 
659 	rt73usb_bbp_write(rt2x00dev, 77, r77);
660 	rt73usb_bbp_write(rt2x00dev, 3, r3);
661 	rt73usb_bbp_write(rt2x00dev, 4, r4);
662 }
663 
664 struct antenna_sel {
665 	u8 word;
666 	/*
667 	 * value[0] -> non-LNA
668 	 * value[1] -> LNA
669 	 */
670 	u8 value[2];
671 };
672 
673 static const struct antenna_sel antenna_sel_a[] = {
674 	{ 96,  { 0x58, 0x78 } },
675 	{ 104, { 0x38, 0x48 } },
676 	{ 75,  { 0xfe, 0x80 } },
677 	{ 86,  { 0xfe, 0x80 } },
678 	{ 88,  { 0xfe, 0x80 } },
679 	{ 35,  { 0x60, 0x60 } },
680 	{ 97,  { 0x58, 0x58 } },
681 	{ 98,  { 0x58, 0x58 } },
682 };
683 
684 static const struct antenna_sel antenna_sel_bg[] = {
685 	{ 96,  { 0x48, 0x68 } },
686 	{ 104, { 0x2c, 0x3c } },
687 	{ 75,  { 0xfe, 0x80 } },
688 	{ 86,  { 0xfe, 0x80 } },
689 	{ 88,  { 0xfe, 0x80 } },
690 	{ 35,  { 0x50, 0x50 } },
691 	{ 97,  { 0x48, 0x48 } },
692 	{ 98,  { 0x48, 0x48 } },
693 };
694 
695 static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
696 			       struct antenna_setup *ant)
697 {
698 	const struct antenna_sel *sel;
699 	unsigned int lna;
700 	unsigned int i;
701 	u32 reg;
702 
703 	/*
704 	 * We should never come here because rt2x00lib is supposed
705 	 * to catch this and send us the correct antenna explicitely.
706 	 */
707 	BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
708 	       ant->tx == ANTENNA_SW_DIVERSITY);
709 
710 	if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
711 		sel = antenna_sel_a;
712 		lna = rt2x00_has_cap_external_lna_a(rt2x00dev);
713 	} else {
714 		sel = antenna_sel_bg;
715 		lna = rt2x00_has_cap_external_lna_bg(rt2x00dev);
716 	}
717 
718 	for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
719 		rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
720 
721 	reg = rt2x00usb_register_read(rt2x00dev, PHY_CSR0);
722 
723 	rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
724 			   (rt2x00dev->curr_band == NL80211_BAND_2GHZ));
725 	rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
726 			   (rt2x00dev->curr_band == NL80211_BAND_5GHZ));
727 
728 	rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
729 
730 	if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225))
731 		rt73usb_config_antenna_5x(rt2x00dev, ant);
732 	else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527))
733 		rt73usb_config_antenna_2x(rt2x00dev, ant);
734 }
735 
736 static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
737 				    struct rt2x00lib_conf *libconf)
738 {
739 	u16 eeprom;
740 	short lna_gain = 0;
741 
742 	if (libconf->conf->chandef.chan->band == NL80211_BAND_2GHZ) {
743 		if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
744 			lna_gain += 14;
745 
746 		eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG);
747 		lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
748 	} else {
749 		eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A);
750 		lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
751 	}
752 
753 	rt2x00dev->lna_gain = lna_gain;
754 }
755 
756 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
757 				   struct rf_channel *rf, const int txpower)
758 {
759 	u8 r3;
760 	u8 r94;
761 	u8 smart;
762 
763 	rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
764 	rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
765 
766 	smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
767 
768 	r3 = rt73usb_bbp_read(rt2x00dev, 3);
769 	rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
770 	rt73usb_bbp_write(rt2x00dev, 3, r3);
771 
772 	r94 = 6;
773 	if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
774 		r94 += txpower - MAX_TXPOWER;
775 	else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
776 		r94 += txpower;
777 	rt73usb_bbp_write(rt2x00dev, 94, r94);
778 
779 	rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
780 	rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
781 	rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
782 	rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
783 
784 	rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
785 	rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
786 	rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
787 	rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
788 
789 	rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
790 	rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
791 	rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
792 	rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
793 
794 	udelay(10);
795 }
796 
797 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
798 				   const int txpower)
799 {
800 	struct rf_channel rf;
801 
802 	rf.rf1 = rt2x00_rf_read(rt2x00dev, 1);
803 	rf.rf2 = rt2x00_rf_read(rt2x00dev, 2);
804 	rf.rf3 = rt2x00_rf_read(rt2x00dev, 3);
805 	rf.rf4 = rt2x00_rf_read(rt2x00dev, 4);
806 
807 	rt73usb_config_channel(rt2x00dev, &rf, txpower);
808 }
809 
810 static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
811 				       struct rt2x00lib_conf *libconf)
812 {
813 	u32 reg;
814 
815 	reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR4);
816 	rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
817 	rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
818 	rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
819 	rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
820 			   libconf->conf->long_frame_max_tx_count);
821 	rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
822 			   libconf->conf->short_frame_max_tx_count);
823 	rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
824 }
825 
826 static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
827 				struct rt2x00lib_conf *libconf)
828 {
829 	enum dev_state state =
830 	    (libconf->conf->flags & IEEE80211_CONF_PS) ?
831 		STATE_SLEEP : STATE_AWAKE;
832 	u32 reg;
833 
834 	if (state == STATE_SLEEP) {
835 		reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR11);
836 		rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
837 				   rt2x00dev->beacon_int - 10);
838 		rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
839 				   libconf->conf->listen_interval - 1);
840 		rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
841 
842 		/* We must first disable autowake before it can be enabled */
843 		rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
844 		rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
845 
846 		rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
847 		rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
848 
849 		rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
850 					    USB_MODE_SLEEP, REGISTER_TIMEOUT);
851 	} else {
852 		reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR11);
853 		rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
854 		rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
855 		rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
856 		rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
857 		rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
858 
859 		rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
860 					    USB_MODE_WAKEUP, REGISTER_TIMEOUT);
861 	}
862 }
863 
864 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
865 			   struct rt2x00lib_conf *libconf,
866 			   const unsigned int flags)
867 {
868 	/* Always recalculate LNA gain before changing configuration */
869 	rt73usb_config_lna_gain(rt2x00dev, libconf);
870 
871 	if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
872 		rt73usb_config_channel(rt2x00dev, &libconf->rf,
873 				       libconf->conf->power_level);
874 	if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
875 	    !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
876 		rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
877 	if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
878 		rt73usb_config_retry_limit(rt2x00dev, libconf);
879 	if (flags & IEEE80211_CONF_CHANGE_PS)
880 		rt73usb_config_ps(rt2x00dev, libconf);
881 }
882 
883 /*
884  * Link tuning
885  */
886 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
887 			       struct link_qual *qual)
888 {
889 	u32 reg;
890 
891 	/*
892 	 * Update FCS error count from register.
893 	 */
894 	reg = rt2x00usb_register_read(rt2x00dev, STA_CSR0);
895 	qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
896 
897 	/*
898 	 * Update False CCA count from register.
899 	 */
900 	reg = rt2x00usb_register_read(rt2x00dev, STA_CSR1);
901 	qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
902 }
903 
904 static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
905 				   struct link_qual *qual, u8 vgc_level)
906 {
907 	if (qual->vgc_level != vgc_level) {
908 		rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
909 		qual->vgc_level = vgc_level;
910 		qual->vgc_level_reg = vgc_level;
911 	}
912 }
913 
914 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
915 				struct link_qual *qual)
916 {
917 	rt73usb_set_vgc(rt2x00dev, qual, 0x20);
918 }
919 
920 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
921 			       struct link_qual *qual, const u32 count)
922 {
923 	u8 up_bound;
924 	u8 low_bound;
925 
926 	/*
927 	 * Determine r17 bounds.
928 	 */
929 	if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
930 		low_bound = 0x28;
931 		up_bound = 0x48;
932 
933 		if (rt2x00_has_cap_external_lna_a(rt2x00dev)) {
934 			low_bound += 0x10;
935 			up_bound += 0x10;
936 		}
937 	} else {
938 		if (qual->rssi > -82) {
939 			low_bound = 0x1c;
940 			up_bound = 0x40;
941 		} else if (qual->rssi > -84) {
942 			low_bound = 0x1c;
943 			up_bound = 0x20;
944 		} else {
945 			low_bound = 0x1c;
946 			up_bound = 0x1c;
947 		}
948 
949 		if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
950 			low_bound += 0x14;
951 			up_bound += 0x10;
952 		}
953 	}
954 
955 	/*
956 	 * If we are not associated, we should go straight to the
957 	 * dynamic CCA tuning.
958 	 */
959 	if (!rt2x00dev->intf_associated)
960 		goto dynamic_cca_tune;
961 
962 	/*
963 	 * Special big-R17 for very short distance
964 	 */
965 	if (qual->rssi > -35) {
966 		rt73usb_set_vgc(rt2x00dev, qual, 0x60);
967 		return;
968 	}
969 
970 	/*
971 	 * Special big-R17 for short distance
972 	 */
973 	if (qual->rssi >= -58) {
974 		rt73usb_set_vgc(rt2x00dev, qual, up_bound);
975 		return;
976 	}
977 
978 	/*
979 	 * Special big-R17 for middle-short distance
980 	 */
981 	if (qual->rssi >= -66) {
982 		rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
983 		return;
984 	}
985 
986 	/*
987 	 * Special mid-R17 for middle distance
988 	 */
989 	if (qual->rssi >= -74) {
990 		rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
991 		return;
992 	}
993 
994 	/*
995 	 * Special case: Change up_bound based on the rssi.
996 	 * Lower up_bound when rssi is weaker then -74 dBm.
997 	 */
998 	up_bound -= 2 * (-74 - qual->rssi);
999 	if (low_bound > up_bound)
1000 		up_bound = low_bound;
1001 
1002 	if (qual->vgc_level > up_bound) {
1003 		rt73usb_set_vgc(rt2x00dev, qual, up_bound);
1004 		return;
1005 	}
1006 
1007 dynamic_cca_tune:
1008 
1009 	/*
1010 	 * r17 does not yet exceed upper limit, continue and base
1011 	 * the r17 tuning on the false CCA count.
1012 	 */
1013 	if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1014 		rt73usb_set_vgc(rt2x00dev, qual,
1015 				min_t(u8, qual->vgc_level + 4, up_bound));
1016 	else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1017 		rt73usb_set_vgc(rt2x00dev, qual,
1018 				max_t(u8, qual->vgc_level - 4, low_bound));
1019 }
1020 
1021 /*
1022  * Queue handlers.
1023  */
1024 static void rt73usb_start_queue(struct data_queue *queue)
1025 {
1026 	struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1027 	u32 reg;
1028 
1029 	switch (queue->qid) {
1030 	case QID_RX:
1031 		reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR0);
1032 		rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1033 		rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1034 		break;
1035 	case QID_BEACON:
1036 		reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9);
1037 		rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1038 		rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1039 		rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1040 		rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1041 		break;
1042 	default:
1043 		break;
1044 	}
1045 }
1046 
1047 static void rt73usb_stop_queue(struct data_queue *queue)
1048 {
1049 	struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1050 	u32 reg;
1051 
1052 	switch (queue->qid) {
1053 	case QID_RX:
1054 		reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR0);
1055 		rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1056 		rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1057 		break;
1058 	case QID_BEACON:
1059 		reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9);
1060 		rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1061 		rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1062 		rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1063 		rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1064 		break;
1065 	default:
1066 		break;
1067 	}
1068 }
1069 
1070 /*
1071  * Firmware functions
1072  */
1073 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1074 {
1075 	return FIRMWARE_RT2571;
1076 }
1077 
1078 static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1079 				  const u8 *data, const size_t len)
1080 {
1081 	u16 fw_crc;
1082 	u16 crc;
1083 
1084 	/*
1085 	 * Only support 2kb firmware files.
1086 	 */
1087 	if (len != 2048)
1088 		return FW_BAD_LENGTH;
1089 
1090 	/*
1091 	 * The last 2 bytes in the firmware array are the crc checksum itself,
1092 	 * this means that we should never pass those 2 bytes to the crc
1093 	 * algorithm.
1094 	 */
1095 	fw_crc = (data[len - 2] << 8 | data[len - 1]);
1096 
1097 	/*
1098 	 * Use the crc itu-t algorithm.
1099 	 */
1100 	crc = crc_itu_t(0, data, len - 2);
1101 	crc = crc_itu_t_byte(crc, 0);
1102 	crc = crc_itu_t_byte(crc, 0);
1103 
1104 	return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1105 }
1106 
1107 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1108 				 const u8 *data, const size_t len)
1109 {
1110 	unsigned int i;
1111 	int status;
1112 	u32 reg;
1113 
1114 	/*
1115 	 * Wait for stable hardware.
1116 	 */
1117 	for (i = 0; i < 100; i++) {
1118 		reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR0);
1119 		if (reg)
1120 			break;
1121 		msleep(1);
1122 	}
1123 
1124 	if (!reg) {
1125 		rt2x00_err(rt2x00dev, "Unstable hardware\n");
1126 		return -EBUSY;
1127 	}
1128 
1129 	/*
1130 	 * Write firmware to device.
1131 	 */
1132 	rt2x00usb_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, data, len);
1133 
1134 	/*
1135 	 * Send firmware request to device to load firmware,
1136 	 * we need to specify a long timeout time.
1137 	 */
1138 	status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1139 					     0, USB_MODE_FIRMWARE,
1140 					     REGISTER_TIMEOUT_FIRMWARE);
1141 	if (status < 0) {
1142 		rt2x00_err(rt2x00dev, "Failed to write Firmware to device\n");
1143 		return status;
1144 	}
1145 
1146 	return 0;
1147 }
1148 
1149 /*
1150  * Initialization functions.
1151  */
1152 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1153 {
1154 	u32 reg;
1155 
1156 	reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR0);
1157 	rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1158 	rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1159 	rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1160 	rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1161 
1162 	reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR1);
1163 	rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1164 	rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1165 	rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1166 	rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1167 	rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1168 	rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1169 	rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1170 	rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1171 	rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1172 
1173 	/*
1174 	 * CCK TXD BBP registers
1175 	 */
1176 	reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR2);
1177 	rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1178 	rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1179 	rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1180 	rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1181 	rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1182 	rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1183 	rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1184 	rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1185 	rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1186 
1187 	/*
1188 	 * OFDM TXD BBP registers
1189 	 */
1190 	reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR3);
1191 	rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1192 	rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1193 	rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1194 	rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1195 	rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1196 	rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1197 	rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1198 
1199 	reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR7);
1200 	rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1201 	rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1202 	rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1203 	rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1204 	rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1205 
1206 	reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR8);
1207 	rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1208 	rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1209 	rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1210 	rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1211 	rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1212 
1213 	reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9);
1214 	rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1215 	rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1216 	rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1217 	rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1218 	rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1219 	rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1220 	rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1221 
1222 	rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1223 
1224 	reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR6);
1225 	rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1226 	rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
1227 
1228 	rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1229 
1230 	if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1231 		return -EBUSY;
1232 
1233 	rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1234 
1235 	/*
1236 	 * Invalidate all Shared Keys (SEC_CSR0),
1237 	 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1238 	 */
1239 	rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1240 	rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1241 	rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1242 
1243 	reg = 0x000023b0;
1244 	if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527))
1245 		rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1246 	rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
1247 
1248 	rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1249 	rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1250 	rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1251 
1252 	reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR9);
1253 	rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1254 	rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
1255 
1256 	/*
1257 	 * Clear all beacons
1258 	 * For the Beacon base registers we only need to clear
1259 	 * the first byte since that byte contains the VALID and OWNER
1260 	 * bits which (when set to 0) will invalidate the entire beacon.
1261 	 */
1262 	rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1263 	rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1264 	rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1265 	rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1266 
1267 	/*
1268 	 * We must clear the error counters.
1269 	 * These registers are cleared on read,
1270 	 * so we may pass a useless variable to store the value.
1271 	 */
1272 	reg = rt2x00usb_register_read(rt2x00dev, STA_CSR0);
1273 	reg = rt2x00usb_register_read(rt2x00dev, STA_CSR1);
1274 	reg = rt2x00usb_register_read(rt2x00dev, STA_CSR2);
1275 
1276 	/*
1277 	 * Reset MAC and BBP registers.
1278 	 */
1279 	reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR1);
1280 	rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1281 	rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1282 	rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1283 
1284 	reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR1);
1285 	rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1286 	rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1287 	rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1288 
1289 	reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR1);
1290 	rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1291 	rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1292 
1293 	return 0;
1294 }
1295 
1296 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1297 {
1298 	unsigned int i;
1299 	u8 value;
1300 
1301 	for (i = 0; i < REGISTER_USB_BUSY_COUNT; i++) {
1302 		value = rt73usb_bbp_read(rt2x00dev, 0);
1303 		if ((value != 0xff) && (value != 0x00))
1304 			return 0;
1305 		udelay(REGISTER_BUSY_DELAY);
1306 	}
1307 
1308 	rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
1309 	return -EACCES;
1310 }
1311 
1312 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1313 {
1314 	unsigned int i;
1315 	u16 eeprom;
1316 	u8 reg_id;
1317 	u8 value;
1318 
1319 	if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1320 		return -EACCES;
1321 
1322 	rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1323 	rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1324 	rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1325 	rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1326 	rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1327 	rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1328 	rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1329 	rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1330 	rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1331 	rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1332 	rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1333 	rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1334 	rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1335 	rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1336 	rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1337 	rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1338 	rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1339 	rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1340 	rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1341 	rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1342 	rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1343 	rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1344 	rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1345 	rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1346 	rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1347 
1348 	for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1349 		eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i);
1350 
1351 		if (eeprom != 0xffff && eeprom != 0x0000) {
1352 			reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1353 			value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1354 			rt73usb_bbp_write(rt2x00dev, reg_id, value);
1355 		}
1356 	}
1357 
1358 	return 0;
1359 }
1360 
1361 /*
1362  * Device state switch handlers.
1363  */
1364 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1365 {
1366 	/*
1367 	 * Initialize all registers.
1368 	 */
1369 	if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1370 		     rt73usb_init_bbp(rt2x00dev)))
1371 		return -EIO;
1372 
1373 	return 0;
1374 }
1375 
1376 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1377 {
1378 	rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1379 
1380 	/*
1381 	 * Disable synchronisation.
1382 	 */
1383 	rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1384 
1385 	rt2x00usb_disable_radio(rt2x00dev);
1386 }
1387 
1388 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1389 {
1390 	u32 reg, reg2;
1391 	unsigned int i;
1392 	char put_to_sleep;
1393 
1394 	put_to_sleep = (state != STATE_AWAKE);
1395 
1396 	reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR12);
1397 	rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1398 	rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1399 	rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1400 
1401 	/*
1402 	 * Device is not guaranteed to be in the requested state yet.
1403 	 * We must wait until the register indicates that the
1404 	 * device has entered the correct state.
1405 	 */
1406 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1407 		reg2 = rt2x00usb_register_read(rt2x00dev, MAC_CSR12);
1408 		state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
1409 		if (state == !put_to_sleep)
1410 			return 0;
1411 		rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1412 		msleep(10);
1413 	}
1414 
1415 	return -EBUSY;
1416 }
1417 
1418 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1419 				    enum dev_state state)
1420 {
1421 	int retval = 0;
1422 
1423 	switch (state) {
1424 	case STATE_RADIO_ON:
1425 		retval = rt73usb_enable_radio(rt2x00dev);
1426 		break;
1427 	case STATE_RADIO_OFF:
1428 		rt73usb_disable_radio(rt2x00dev);
1429 		break;
1430 	case STATE_RADIO_IRQ_ON:
1431 	case STATE_RADIO_IRQ_OFF:
1432 		/* No support, but no error either */
1433 		break;
1434 	case STATE_DEEP_SLEEP:
1435 	case STATE_SLEEP:
1436 	case STATE_STANDBY:
1437 	case STATE_AWAKE:
1438 		retval = rt73usb_set_state(rt2x00dev, state);
1439 		break;
1440 	default:
1441 		retval = -ENOTSUPP;
1442 		break;
1443 	}
1444 
1445 	if (unlikely(retval))
1446 		rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1447 			   state, retval);
1448 
1449 	return retval;
1450 }
1451 
1452 /*
1453  * TX descriptor initialization
1454  */
1455 static void rt73usb_write_tx_desc(struct queue_entry *entry,
1456 				  struct txentry_desc *txdesc)
1457 {
1458 	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1459 	__le32 *txd = (__le32 *) entry->skb->data;
1460 	u32 word;
1461 
1462 	/*
1463 	 * Start writing the descriptor words.
1464 	 */
1465 	word = rt2x00_desc_read(txd, 0);
1466 	rt2x00_set_field32(&word, TXD_W0_BURST,
1467 			   test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1468 	rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1469 	rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1470 			   test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1471 	rt2x00_set_field32(&word, TXD_W0_ACK,
1472 			   test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1473 	rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1474 			   test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1475 	rt2x00_set_field32(&word, TXD_W0_OFDM,
1476 			   (txdesc->rate_mode == RATE_MODE_OFDM));
1477 	rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1478 	rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1479 			   test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1480 	rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1481 			   test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1482 	rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1483 			   test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1484 	rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1485 	rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1486 	rt2x00_set_field32(&word, TXD_W0_BURST2,
1487 			   test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1488 	rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1489 	rt2x00_desc_write(txd, 0, word);
1490 
1491 	word = rt2x00_desc_read(txd, 1);
1492 	rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1493 	rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1494 	rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1495 	rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
1496 	rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1497 	rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1498 			   test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1499 	rt2x00_desc_write(txd, 1, word);
1500 
1501 	word = rt2x00_desc_read(txd, 2);
1502 	rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
1503 	rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
1504 	rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
1505 			   txdesc->u.plcp.length_low);
1506 	rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
1507 			   txdesc->u.plcp.length_high);
1508 	rt2x00_desc_write(txd, 2, word);
1509 
1510 	if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1511 		_rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1512 		_rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1513 	}
1514 
1515 	word = rt2x00_desc_read(txd, 5);
1516 	rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1517 			   TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1518 	rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1519 	rt2x00_desc_write(txd, 5, word);
1520 
1521 	/*
1522 	 * Register descriptor details in skb frame descriptor.
1523 	 */
1524 	skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1525 	skbdesc->desc = txd;
1526 	skbdesc->desc_len = TXD_DESC_SIZE;
1527 }
1528 
1529 /*
1530  * TX data initialization
1531  */
1532 static void rt73usb_write_beacon(struct queue_entry *entry,
1533 				 struct txentry_desc *txdesc)
1534 {
1535 	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1536 	unsigned int beacon_base;
1537 	unsigned int padding_len;
1538 	u32 orig_reg, reg;
1539 
1540 	/*
1541 	 * Disable beaconing while we are reloading the beacon data,
1542 	 * otherwise we might be sending out invalid data.
1543 	 */
1544 	reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9);
1545 	orig_reg = reg;
1546 	rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1547 	rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1548 
1549 	/*
1550 	 * Add space for the descriptor in front of the skb.
1551 	 */
1552 	skb_push(entry->skb, TXD_DESC_SIZE);
1553 	memset(entry->skb->data, 0, TXD_DESC_SIZE);
1554 
1555 	/*
1556 	 * Write the TX descriptor for the beacon.
1557 	 */
1558 	rt73usb_write_tx_desc(entry, txdesc);
1559 
1560 	/*
1561 	 * Dump beacon to userspace through debugfs.
1562 	 */
1563 	rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1564 
1565 	/*
1566 	 * Write entire beacon with descriptor and padding to register.
1567 	 */
1568 	padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1569 	if (padding_len && skb_pad(entry->skb, padding_len)) {
1570 		rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1571 		/* skb freed by skb_pad() on failure */
1572 		entry->skb = NULL;
1573 		rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
1574 		return;
1575 	}
1576 
1577 	beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1578 	rt2x00usb_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1579 				      entry->skb->len + padding_len);
1580 
1581 	/*
1582 	 * Enable beaconing again.
1583 	 *
1584 	 * For Wi-Fi faily generated beacons between participating stations.
1585 	 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1586 	 */
1587 	rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1588 
1589 	rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1590 	rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1591 
1592 	/*
1593 	 * Clean up the beacon skb.
1594 	 */
1595 	dev_kfree_skb(entry->skb);
1596 	entry->skb = NULL;
1597 }
1598 
1599 static void rt73usb_clear_beacon(struct queue_entry *entry)
1600 {
1601 	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1602 	unsigned int beacon_base;
1603 	u32 orig_reg, reg;
1604 
1605 	/*
1606 	 * Disable beaconing while we are reloading the beacon data,
1607 	 * otherwise we might be sending out invalid data.
1608 	 */
1609 	orig_reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9);
1610 	reg = orig_reg;
1611 	rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1612 	rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1613 
1614 	/*
1615 	 * Clear beacon.
1616 	 */
1617 	beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1618 	rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
1619 
1620 	/*
1621 	 * Restore beaconing state.
1622 	 */
1623 	rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
1624 }
1625 
1626 static int rt73usb_get_tx_data_len(struct queue_entry *entry)
1627 {
1628 	int length;
1629 
1630 	/*
1631 	 * The length _must_ be a multiple of 4,
1632 	 * but it must _not_ be a multiple of the USB packet size.
1633 	 */
1634 	length = roundup(entry->skb->len, 4);
1635 	length += (4 * !(length % entry->queue->usb_maxpacket));
1636 
1637 	return length;
1638 }
1639 
1640 /*
1641  * RX control handlers
1642  */
1643 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1644 {
1645 	u8 offset = rt2x00dev->lna_gain;
1646 	u8 lna;
1647 
1648 	lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1649 	switch (lna) {
1650 	case 3:
1651 		offset += 90;
1652 		break;
1653 	case 2:
1654 		offset += 74;
1655 		break;
1656 	case 1:
1657 		offset += 64;
1658 		break;
1659 	default:
1660 		return 0;
1661 	}
1662 
1663 	if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
1664 		if (rt2x00_has_cap_external_lna_a(rt2x00dev)) {
1665 			if (lna == 3 || lna == 2)
1666 				offset += 10;
1667 		} else {
1668 			if (lna == 3)
1669 				offset += 6;
1670 			else if (lna == 2)
1671 				offset += 8;
1672 		}
1673 	}
1674 
1675 	return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1676 }
1677 
1678 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1679 				struct rxdone_entry_desc *rxdesc)
1680 {
1681 	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1682 	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1683 	__le32 *rxd = (__le32 *)entry->skb->data;
1684 	u32 word0;
1685 	u32 word1;
1686 
1687 	/*
1688 	 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1689 	 * frame data in rt2x00usb.
1690 	 */
1691 	memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1692 	rxd = (__le32 *)skbdesc->desc;
1693 
1694 	/*
1695 	 * It is now safe to read the descriptor on all architectures.
1696 	 */
1697 	word0 = rt2x00_desc_read(rxd, 0);
1698 	word1 = rt2x00_desc_read(rxd, 1);
1699 
1700 	if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1701 		rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1702 
1703 	rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1704 	rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1705 
1706 	if (rxdesc->cipher != CIPHER_NONE) {
1707 		rxdesc->iv[0] = _rt2x00_desc_read(rxd, 2);
1708 		rxdesc->iv[1] = _rt2x00_desc_read(rxd, 3);
1709 		rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1710 
1711 		rxdesc->icv = _rt2x00_desc_read(rxd, 4);
1712 		rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
1713 
1714 		/*
1715 		 * Hardware has stripped IV/EIV data from 802.11 frame during
1716 		 * decryption. It has provided the data separately but rt2x00lib
1717 		 * should decide if it should be reinserted.
1718 		 */
1719 		rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1720 
1721 		/*
1722 		 * The hardware has already checked the Michael Mic and has
1723 		 * stripped it from the frame. Signal this to mac80211.
1724 		 */
1725 		rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1726 
1727 		if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1728 			rxdesc->flags |= RX_FLAG_DECRYPTED;
1729 		else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1730 			rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1731 	}
1732 
1733 	/*
1734 	 * Obtain the status about this packet.
1735 	 * When frame was received with an OFDM bitrate,
1736 	 * the signal is the PLCP value. If it was received with
1737 	 * a CCK bitrate the signal is the rate in 100kbit/s.
1738 	 */
1739 	rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1740 	rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
1741 	rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1742 
1743 	if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1744 		rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1745 	else
1746 		rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1747 	if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1748 		rxdesc->dev_flags |= RXDONE_MY_BSS;
1749 
1750 	/*
1751 	 * Set skb pointers, and update frame information.
1752 	 */
1753 	skb_pull(entry->skb, entry->queue->desc_size);
1754 	skb_trim(entry->skb, rxdesc->size);
1755 }
1756 
1757 /*
1758  * Device probe functions.
1759  */
1760 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1761 {
1762 	u16 word;
1763 	u8 *mac;
1764 	s8 value;
1765 
1766 	rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1767 
1768 	/*
1769 	 * Start validation of the data that has been read.
1770 	 */
1771 	mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1772 	rt2x00lib_set_mac_address(rt2x00dev, mac);
1773 
1774 	word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1775 	if (word == 0xffff) {
1776 		rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1777 		rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1778 				   ANTENNA_B);
1779 		rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1780 				   ANTENNA_B);
1781 		rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1782 		rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1783 		rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1784 		rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1785 		rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1786 		rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
1787 	}
1788 
1789 	word = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC);
1790 	if (word == 0xffff) {
1791 		rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1792 		rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1793 		rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
1794 	}
1795 
1796 	word = rt2x00_eeprom_read(rt2x00dev, EEPROM_LED);
1797 	if (word == 0xffff) {
1798 		rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1799 		rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1800 		rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1801 		rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1802 		rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1803 		rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1804 		rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1805 		rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1806 		rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1807 				   LED_MODE_DEFAULT);
1808 		rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1809 		rt2x00_eeprom_dbg(rt2x00dev, "Led: 0x%04x\n", word);
1810 	}
1811 
1812 	word = rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ);
1813 	if (word == 0xffff) {
1814 		rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1815 		rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1816 		rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1817 		rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
1818 	}
1819 
1820 	word = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG);
1821 	if (word == 0xffff) {
1822 		rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1823 		rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1824 		rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1825 		rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1826 	} else {
1827 		value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1828 		if (value < -10 || value > 10)
1829 			rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1830 		value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1831 		if (value < -10 || value > 10)
1832 			rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1833 		rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1834 	}
1835 
1836 	word = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A);
1837 	if (word == 0xffff) {
1838 		rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1839 		rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1840 		rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1841 		rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1842 	} else {
1843 		value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1844 		if (value < -10 || value > 10)
1845 			rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1846 		value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1847 		if (value < -10 || value > 10)
1848 			rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1849 		rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1850 	}
1851 
1852 	return 0;
1853 }
1854 
1855 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1856 {
1857 	u32 reg;
1858 	u16 value;
1859 	u16 eeprom;
1860 
1861 	/*
1862 	 * Read EEPROM word for configuration.
1863 	 */
1864 	eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1865 
1866 	/*
1867 	 * Identify RF chipset.
1868 	 */
1869 	value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1870 	reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR0);
1871 	rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1872 			value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
1873 
1874 	if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) {
1875 		rt2x00_err(rt2x00dev, "Invalid RT chipset detected\n");
1876 		return -ENODEV;
1877 	}
1878 
1879 	if (!rt2x00_rf(rt2x00dev, RF5226) &&
1880 	    !rt2x00_rf(rt2x00dev, RF2528) &&
1881 	    !rt2x00_rf(rt2x00dev, RF5225) &&
1882 	    !rt2x00_rf(rt2x00dev, RF2527)) {
1883 		rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
1884 		return -ENODEV;
1885 	}
1886 
1887 	/*
1888 	 * Identify default antenna configuration.
1889 	 */
1890 	rt2x00dev->default_ant.tx =
1891 	    rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1892 	rt2x00dev->default_ant.rx =
1893 	    rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1894 
1895 	/*
1896 	 * Read the Frame type.
1897 	 */
1898 	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1899 		__set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags);
1900 
1901 	/*
1902 	 * Detect if this device has an hardware controlled radio.
1903 	 */
1904 	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1905 		__set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1906 
1907 	/*
1908 	 * Read frequency offset.
1909 	 */
1910 	eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ);
1911 	rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1912 
1913 	/*
1914 	 * Read external LNA informations.
1915 	 */
1916 	eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC);
1917 
1918 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1919 		__set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
1920 		__set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
1921 	}
1922 
1923 	/*
1924 	 * Store led settings, for correct led behaviour.
1925 	 */
1926 #ifdef CONFIG_RT2X00_LIB_LEDS
1927 	eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_LED);
1928 
1929 	rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1930 	rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1931 	if (value == LED_MODE_SIGNAL_STRENGTH)
1932 		rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1933 				 LED_TYPE_QUALITY);
1934 
1935 	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1936 	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1937 			   rt2x00_get_field16(eeprom,
1938 					      EEPROM_LED_POLARITY_GPIO_0));
1939 	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1940 			   rt2x00_get_field16(eeprom,
1941 					      EEPROM_LED_POLARITY_GPIO_1));
1942 	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1943 			   rt2x00_get_field16(eeprom,
1944 					      EEPROM_LED_POLARITY_GPIO_2));
1945 	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1946 			   rt2x00_get_field16(eeprom,
1947 					      EEPROM_LED_POLARITY_GPIO_3));
1948 	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1949 			   rt2x00_get_field16(eeprom,
1950 					      EEPROM_LED_POLARITY_GPIO_4));
1951 	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1952 			   rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1953 	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1954 			   rt2x00_get_field16(eeprom,
1955 					      EEPROM_LED_POLARITY_RDY_G));
1956 	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1957 			   rt2x00_get_field16(eeprom,
1958 					      EEPROM_LED_POLARITY_RDY_A));
1959 #endif /* CONFIG_RT2X00_LIB_LEDS */
1960 
1961 	return 0;
1962 }
1963 
1964 /*
1965  * RF value list for RF2528
1966  * Supports: 2.4 GHz
1967  */
1968 static const struct rf_channel rf_vals_bg_2528[] = {
1969 	{ 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1970 	{ 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1971 	{ 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1972 	{ 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1973 	{ 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1974 	{ 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1975 	{ 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1976 	{ 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1977 	{ 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1978 	{ 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1979 	{ 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1980 	{ 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1981 	{ 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1982 	{ 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1983 };
1984 
1985 /*
1986  * RF value list for RF5226
1987  * Supports: 2.4 GHz & 5.2 GHz
1988  */
1989 static const struct rf_channel rf_vals_5226[] = {
1990 	{ 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1991 	{ 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1992 	{ 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1993 	{ 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1994 	{ 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1995 	{ 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1996 	{ 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1997 	{ 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1998 	{ 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1999 	{ 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
2000 	{ 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
2001 	{ 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
2002 	{ 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
2003 	{ 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
2004 
2005 	/* 802.11 UNI / HyperLan 2 */
2006 	{ 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
2007 	{ 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
2008 	{ 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
2009 	{ 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
2010 	{ 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
2011 	{ 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
2012 	{ 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
2013 	{ 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
2014 
2015 	/* 802.11 HyperLan 2 */
2016 	{ 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
2017 	{ 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
2018 	{ 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
2019 	{ 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
2020 	{ 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
2021 	{ 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
2022 	{ 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
2023 	{ 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
2024 	{ 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
2025 	{ 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
2026 
2027 	/* 802.11 UNII */
2028 	{ 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
2029 	{ 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
2030 	{ 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
2031 	{ 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
2032 	{ 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
2033 	{ 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
2034 
2035 	/* MMAC(Japan)J52 ch 34,38,42,46 */
2036 	{ 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
2037 	{ 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
2038 	{ 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
2039 	{ 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
2040 };
2041 
2042 /*
2043  * RF value list for RF5225 & RF2527
2044  * Supports: 2.4 GHz & 5.2 GHz
2045  */
2046 static const struct rf_channel rf_vals_5225_2527[] = {
2047 	{ 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2048 	{ 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2049 	{ 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2050 	{ 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2051 	{ 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2052 	{ 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2053 	{ 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2054 	{ 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2055 	{ 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2056 	{ 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2057 	{ 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2058 	{ 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2059 	{ 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2060 	{ 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2061 
2062 	/* 802.11 UNI / HyperLan 2 */
2063 	{ 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2064 	{ 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2065 	{ 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2066 	{ 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2067 	{ 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2068 	{ 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2069 	{ 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2070 	{ 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2071 
2072 	/* 802.11 HyperLan 2 */
2073 	{ 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2074 	{ 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2075 	{ 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2076 	{ 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2077 	{ 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2078 	{ 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2079 	{ 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2080 	{ 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2081 	{ 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2082 	{ 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2083 
2084 	/* 802.11 UNII */
2085 	{ 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2086 	{ 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2087 	{ 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2088 	{ 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2089 	{ 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2090 	{ 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2091 
2092 	/* MMAC(Japan)J52 ch 34,38,42,46 */
2093 	{ 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2094 	{ 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2095 	{ 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2096 	{ 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2097 };
2098 
2099 
2100 static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2101 {
2102 	struct hw_mode_spec *spec = &rt2x00dev->spec;
2103 	struct channel_info *info;
2104 	char *tx_power;
2105 	unsigned int i;
2106 
2107 	/*
2108 	 * Initialize all hw fields.
2109 	 *
2110 	 * Don't set IEEE80211_HOST_BROADCAST_PS_BUFFERING unless we are
2111 	 * capable of sending the buffered frames out after the DTIM
2112 	 * transmission using rt2x00lib_beacondone. This will send out
2113 	 * multicast and broadcast traffic immediately instead of buffering it
2114 	 * infinitly and thus dropping it after some time.
2115 	 */
2116 	ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
2117 	ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
2118 	ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
2119 
2120 	SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2121 	SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2122 				rt2x00_eeprom_addr(rt2x00dev,
2123 						   EEPROM_MAC_ADDR_0));
2124 
2125 	/*
2126 	 * Initialize hw_mode information.
2127 	 */
2128 	spec->supported_bands = SUPPORT_BAND_2GHZ;
2129 	spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2130 
2131 	if (rt2x00_rf(rt2x00dev, RF2528)) {
2132 		spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2133 		spec->channels = rf_vals_bg_2528;
2134 	} else if (rt2x00_rf(rt2x00dev, RF5226)) {
2135 		spec->supported_bands |= SUPPORT_BAND_5GHZ;
2136 		spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2137 		spec->channels = rf_vals_5226;
2138 	} else if (rt2x00_rf(rt2x00dev, RF2527)) {
2139 		spec->num_channels = 14;
2140 		spec->channels = rf_vals_5225_2527;
2141 	} else if (rt2x00_rf(rt2x00dev, RF5225)) {
2142 		spec->supported_bands |= SUPPORT_BAND_5GHZ;
2143 		spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2144 		spec->channels = rf_vals_5225_2527;
2145 	}
2146 
2147 	/*
2148 	 * Create channel information array
2149 	 */
2150 	info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2151 	if (!info)
2152 		return -ENOMEM;
2153 
2154 	spec->channels_info = info;
2155 
2156 	tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2157 	for (i = 0; i < 14; i++) {
2158 		info[i].max_power = MAX_TXPOWER;
2159 		info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2160 	}
2161 
2162 	if (spec->num_channels > 14) {
2163 		tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2164 		for (i = 14; i < spec->num_channels; i++) {
2165 			info[i].max_power = MAX_TXPOWER;
2166 			info[i].default_power1 =
2167 					TXPOWER_FROM_DEV(tx_power[i - 14]);
2168 		}
2169 	}
2170 
2171 	return 0;
2172 }
2173 
2174 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2175 {
2176 	int retval;
2177 	u32 reg;
2178 
2179 	/*
2180 	 * Allocate eeprom data.
2181 	 */
2182 	retval = rt73usb_validate_eeprom(rt2x00dev);
2183 	if (retval)
2184 		return retval;
2185 
2186 	retval = rt73usb_init_eeprom(rt2x00dev);
2187 	if (retval)
2188 		return retval;
2189 
2190 	/*
2191 	 * Enable rfkill polling by setting GPIO direction of the
2192 	 * rfkill switch GPIO pin correctly.
2193 	 */
2194 	reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR13);
2195 	rt2x00_set_field32(&reg, MAC_CSR13_DIR7, 0);
2196 	rt2x00usb_register_write(rt2x00dev, MAC_CSR13, reg);
2197 
2198 	/*
2199 	 * Initialize hw specifications.
2200 	 */
2201 	retval = rt73usb_probe_hw_mode(rt2x00dev);
2202 	if (retval)
2203 		return retval;
2204 
2205 	/*
2206 	 * This device has multiple filters for control frames,
2207 	 * but has no a separate filter for PS Poll frames.
2208 	 */
2209 	__set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
2210 
2211 	/*
2212 	 * This device requires firmware.
2213 	 */
2214 	__set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
2215 	if (!modparam_nohwcrypt)
2216 		__set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
2217 	__set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
2218 	__set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
2219 
2220 	/*
2221 	 * Set the rssi offset.
2222 	 */
2223 	rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2224 
2225 	return 0;
2226 }
2227 
2228 /*
2229  * IEEE80211 stack callback functions.
2230  */
2231 static int rt73usb_conf_tx(struct ieee80211_hw *hw,
2232 			   struct ieee80211_vif *vif, u16 queue_idx,
2233 			   const struct ieee80211_tx_queue_params *params)
2234 {
2235 	struct rt2x00_dev *rt2x00dev = hw->priv;
2236 	struct data_queue *queue;
2237 	struct rt2x00_field32 field;
2238 	int retval;
2239 	u32 reg;
2240 	u32 offset;
2241 
2242 	/*
2243 	 * First pass the configuration through rt2x00lib, that will
2244 	 * update the queue settings and validate the input. After that
2245 	 * we are free to update the registers based on the value
2246 	 * in the queue parameter.
2247 	 */
2248 	retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2249 	if (retval)
2250 		return retval;
2251 
2252 	/*
2253 	 * We only need to perform additional register initialization
2254 	 * for WMM queues/
2255 	 */
2256 	if (queue_idx >= 4)
2257 		return 0;
2258 
2259 	queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2260 
2261 	/* Update WMM TXOP register */
2262 	offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2263 	field.bit_offset = (queue_idx & 1) * 16;
2264 	field.bit_mask = 0xffff << field.bit_offset;
2265 
2266 	reg = rt2x00usb_register_read(rt2x00dev, offset);
2267 	rt2x00_set_field32(&reg, field, queue->txop);
2268 	rt2x00usb_register_write(rt2x00dev, offset, reg);
2269 
2270 	/* Update WMM registers */
2271 	field.bit_offset = queue_idx * 4;
2272 	field.bit_mask = 0xf << field.bit_offset;
2273 
2274 	reg = rt2x00usb_register_read(rt2x00dev, AIFSN_CSR);
2275 	rt2x00_set_field32(&reg, field, queue->aifs);
2276 	rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2277 
2278 	reg = rt2x00usb_register_read(rt2x00dev, CWMIN_CSR);
2279 	rt2x00_set_field32(&reg, field, queue->cw_min);
2280 	rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2281 
2282 	reg = rt2x00usb_register_read(rt2x00dev, CWMAX_CSR);
2283 	rt2x00_set_field32(&reg, field, queue->cw_max);
2284 	rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2285 
2286 	return 0;
2287 }
2288 
2289 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2290 {
2291 	struct rt2x00_dev *rt2x00dev = hw->priv;
2292 	u64 tsf;
2293 	u32 reg;
2294 
2295 	reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR13);
2296 	tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2297 	reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR12);
2298 	tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2299 
2300 	return tsf;
2301 }
2302 
2303 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2304 	.tx			= rt2x00mac_tx,
2305 	.start			= rt2x00mac_start,
2306 	.stop			= rt2x00mac_stop,
2307 	.add_interface		= rt2x00mac_add_interface,
2308 	.remove_interface	= rt2x00mac_remove_interface,
2309 	.config			= rt2x00mac_config,
2310 	.configure_filter	= rt2x00mac_configure_filter,
2311 	.set_tim		= rt2x00mac_set_tim,
2312 	.set_key		= rt2x00mac_set_key,
2313 	.sw_scan_start		= rt2x00mac_sw_scan_start,
2314 	.sw_scan_complete	= rt2x00mac_sw_scan_complete,
2315 	.get_stats		= rt2x00mac_get_stats,
2316 	.bss_info_changed	= rt2x00mac_bss_info_changed,
2317 	.conf_tx		= rt73usb_conf_tx,
2318 	.get_tsf		= rt73usb_get_tsf,
2319 	.rfkill_poll		= rt2x00mac_rfkill_poll,
2320 	.flush			= rt2x00mac_flush,
2321 	.set_antenna		= rt2x00mac_set_antenna,
2322 	.get_antenna		= rt2x00mac_get_antenna,
2323 	.get_ringparam		= rt2x00mac_get_ringparam,
2324 	.tx_frames_pending	= rt2x00mac_tx_frames_pending,
2325 };
2326 
2327 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2328 	.probe_hw		= rt73usb_probe_hw,
2329 	.get_firmware_name	= rt73usb_get_firmware_name,
2330 	.check_firmware		= rt73usb_check_firmware,
2331 	.load_firmware		= rt73usb_load_firmware,
2332 	.initialize		= rt2x00usb_initialize,
2333 	.uninitialize		= rt2x00usb_uninitialize,
2334 	.clear_entry		= rt2x00usb_clear_entry,
2335 	.set_device_state	= rt73usb_set_device_state,
2336 	.rfkill_poll		= rt73usb_rfkill_poll,
2337 	.link_stats		= rt73usb_link_stats,
2338 	.reset_tuner		= rt73usb_reset_tuner,
2339 	.link_tuner		= rt73usb_link_tuner,
2340 	.watchdog		= rt2x00usb_watchdog,
2341 	.start_queue		= rt73usb_start_queue,
2342 	.kick_queue		= rt2x00usb_kick_queue,
2343 	.stop_queue		= rt73usb_stop_queue,
2344 	.flush_queue		= rt2x00usb_flush_queue,
2345 	.write_tx_desc		= rt73usb_write_tx_desc,
2346 	.write_beacon		= rt73usb_write_beacon,
2347 	.clear_beacon		= rt73usb_clear_beacon,
2348 	.get_tx_data_len	= rt73usb_get_tx_data_len,
2349 	.fill_rxdone		= rt73usb_fill_rxdone,
2350 	.config_shared_key	= rt73usb_config_shared_key,
2351 	.config_pairwise_key	= rt73usb_config_pairwise_key,
2352 	.config_filter		= rt73usb_config_filter,
2353 	.config_intf		= rt73usb_config_intf,
2354 	.config_erp		= rt73usb_config_erp,
2355 	.config_ant		= rt73usb_config_ant,
2356 	.config			= rt73usb_config,
2357 };
2358 
2359 static void rt73usb_queue_init(struct data_queue *queue)
2360 {
2361 	switch (queue->qid) {
2362 	case QID_RX:
2363 		queue->limit = 32;
2364 		queue->data_size = DATA_FRAME_SIZE;
2365 		queue->desc_size = RXD_DESC_SIZE;
2366 		queue->priv_size = sizeof(struct queue_entry_priv_usb);
2367 		break;
2368 
2369 	case QID_AC_VO:
2370 	case QID_AC_VI:
2371 	case QID_AC_BE:
2372 	case QID_AC_BK:
2373 		queue->limit = 32;
2374 		queue->data_size = DATA_FRAME_SIZE;
2375 		queue->desc_size = TXD_DESC_SIZE;
2376 		queue->priv_size = sizeof(struct queue_entry_priv_usb);
2377 		break;
2378 
2379 	case QID_BEACON:
2380 		queue->limit = 4;
2381 		queue->data_size = MGMT_FRAME_SIZE;
2382 		queue->desc_size = TXINFO_SIZE;
2383 		queue->priv_size = sizeof(struct queue_entry_priv_usb);
2384 		break;
2385 
2386 	case QID_ATIM:
2387 		/* fallthrough */
2388 	default:
2389 		BUG();
2390 		break;
2391 	}
2392 }
2393 
2394 static const struct rt2x00_ops rt73usb_ops = {
2395 	.name			= KBUILD_MODNAME,
2396 	.max_ap_intf		= 4,
2397 	.eeprom_size		= EEPROM_SIZE,
2398 	.rf_size		= RF_SIZE,
2399 	.tx_queues		= NUM_TX_QUEUES,
2400 	.queue_init		= rt73usb_queue_init,
2401 	.lib			= &rt73usb_rt2x00_ops,
2402 	.hw			= &rt73usb_mac80211_ops,
2403 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2404 	.debugfs		= &rt73usb_rt2x00debug,
2405 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2406 };
2407 
2408 /*
2409  * rt73usb module information.
2410  */
2411 static const struct usb_device_id rt73usb_device_table[] = {
2412 	/* AboCom */
2413 	{ USB_DEVICE(0x07b8, 0xb21b) },
2414 	{ USB_DEVICE(0x07b8, 0xb21c) },
2415 	{ USB_DEVICE(0x07b8, 0xb21d) },
2416 	{ USB_DEVICE(0x07b8, 0xb21e) },
2417 	{ USB_DEVICE(0x07b8, 0xb21f) },
2418 	/* AL */
2419 	{ USB_DEVICE(0x14b2, 0x3c10) },
2420 	/* Amigo */
2421 	{ USB_DEVICE(0x148f, 0x9021) },
2422 	{ USB_DEVICE(0x0eb0, 0x9021) },
2423 	/* AMIT  */
2424 	{ USB_DEVICE(0x18c5, 0x0002) },
2425 	/* Askey */
2426 	{ USB_DEVICE(0x1690, 0x0722) },
2427 	/* ASUS */
2428 	{ USB_DEVICE(0x0b05, 0x1723) },
2429 	{ USB_DEVICE(0x0b05, 0x1724) },
2430 	/* Belkin */
2431 	{ USB_DEVICE(0x050d, 0x7050) },	/* FCC ID: K7SF5D7050B ver. 3.x */
2432 	{ USB_DEVICE(0x050d, 0x705a) },
2433 	{ USB_DEVICE(0x050d, 0x905b) },
2434 	{ USB_DEVICE(0x050d, 0x905c) },
2435 	/* Billionton */
2436 	{ USB_DEVICE(0x1631, 0xc019) },
2437 	{ USB_DEVICE(0x08dd, 0x0120) },
2438 	/* Buffalo */
2439 	{ USB_DEVICE(0x0411, 0x00d8) },
2440 	{ USB_DEVICE(0x0411, 0x00d9) },
2441 	{ USB_DEVICE(0x0411, 0x00e6) },
2442 	{ USB_DEVICE(0x0411, 0x00f4) },
2443 	{ USB_DEVICE(0x0411, 0x0116) },
2444 	{ USB_DEVICE(0x0411, 0x0119) },
2445 	{ USB_DEVICE(0x0411, 0x0137) },
2446 	/* CEIVA */
2447 	{ USB_DEVICE(0x178d, 0x02be) },
2448 	/* CNet */
2449 	{ USB_DEVICE(0x1371, 0x9022) },
2450 	{ USB_DEVICE(0x1371, 0x9032) },
2451 	/* Conceptronic */
2452 	{ USB_DEVICE(0x14b2, 0x3c22) },
2453 	/* Corega */
2454 	{ USB_DEVICE(0x07aa, 0x002e) },
2455 	/* D-Link */
2456 	{ USB_DEVICE(0x07d1, 0x3c03) },
2457 	{ USB_DEVICE(0x07d1, 0x3c04) },
2458 	{ USB_DEVICE(0x07d1, 0x3c06) },
2459 	{ USB_DEVICE(0x07d1, 0x3c07) },
2460 	/* Edimax */
2461 	{ USB_DEVICE(0x7392, 0x7318) },
2462 	{ USB_DEVICE(0x7392, 0x7618) },
2463 	/* EnGenius */
2464 	{ USB_DEVICE(0x1740, 0x3701) },
2465 	/* Gemtek */
2466 	{ USB_DEVICE(0x15a9, 0x0004) },
2467 	/* Gigabyte */
2468 	{ USB_DEVICE(0x1044, 0x8008) },
2469 	{ USB_DEVICE(0x1044, 0x800a) },
2470 	/* Huawei-3Com */
2471 	{ USB_DEVICE(0x1472, 0x0009) },
2472 	/* Hercules */
2473 	{ USB_DEVICE(0x06f8, 0xe002) },
2474 	{ USB_DEVICE(0x06f8, 0xe010) },
2475 	{ USB_DEVICE(0x06f8, 0xe020) },
2476 	/* Linksys */
2477 	{ USB_DEVICE(0x13b1, 0x0020) },
2478 	{ USB_DEVICE(0x13b1, 0x0023) },
2479 	{ USB_DEVICE(0x13b1, 0x0028) },
2480 	/* MSI */
2481 	{ USB_DEVICE(0x0db0, 0x4600) },
2482 	{ USB_DEVICE(0x0db0, 0x6877) },
2483 	{ USB_DEVICE(0x0db0, 0x6874) },
2484 	{ USB_DEVICE(0x0db0, 0xa861) },
2485 	{ USB_DEVICE(0x0db0, 0xa874) },
2486 	/* Ovislink */
2487 	{ USB_DEVICE(0x1b75, 0x7318) },
2488 	/* Ralink */
2489 	{ USB_DEVICE(0x04bb, 0x093d) },
2490 	{ USB_DEVICE(0x148f, 0x2573) },
2491 	{ USB_DEVICE(0x148f, 0x2671) },
2492 	{ USB_DEVICE(0x0812, 0x3101) },
2493 	/* Qcom */
2494 	{ USB_DEVICE(0x18e8, 0x6196) },
2495 	{ USB_DEVICE(0x18e8, 0x6229) },
2496 	{ USB_DEVICE(0x18e8, 0x6238) },
2497 	/* Samsung */
2498 	{ USB_DEVICE(0x04e8, 0x4471) },
2499 	/* Senao */
2500 	{ USB_DEVICE(0x1740, 0x7100) },
2501 	/* Sitecom */
2502 	{ USB_DEVICE(0x0df6, 0x0024) },
2503 	{ USB_DEVICE(0x0df6, 0x0027) },
2504 	{ USB_DEVICE(0x0df6, 0x002f) },
2505 	{ USB_DEVICE(0x0df6, 0x90ac) },
2506 	{ USB_DEVICE(0x0df6, 0x9712) },
2507 	/* Surecom */
2508 	{ USB_DEVICE(0x0769, 0x31f3) },
2509 	/* Tilgin */
2510 	{ USB_DEVICE(0x6933, 0x5001) },
2511 	/* Philips */
2512 	{ USB_DEVICE(0x0471, 0x200a) },
2513 	/* Planex */
2514 	{ USB_DEVICE(0x2019, 0xab01) },
2515 	{ USB_DEVICE(0x2019, 0xab50) },
2516 	/* WideTell */
2517 	{ USB_DEVICE(0x7167, 0x3840) },
2518 	/* Zcom */
2519 	{ USB_DEVICE(0x0cde, 0x001c) },
2520 	/* ZyXEL */
2521 	{ USB_DEVICE(0x0586, 0x3415) },
2522 	{ 0, }
2523 };
2524 
2525 MODULE_AUTHOR(DRV_PROJECT);
2526 MODULE_VERSION(DRV_VERSION);
2527 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2528 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2529 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2530 MODULE_FIRMWARE(FIRMWARE_RT2571);
2531 MODULE_LICENSE("GPL");
2532 
2533 static int rt73usb_probe(struct usb_interface *usb_intf,
2534 			 const struct usb_device_id *id)
2535 {
2536 	return rt2x00usb_probe(usb_intf, &rt73usb_ops);
2537 }
2538 
2539 static struct usb_driver rt73usb_driver = {
2540 	.name		= KBUILD_MODNAME,
2541 	.id_table	= rt73usb_device_table,
2542 	.probe		= rt73usb_probe,
2543 	.disconnect	= rt2x00usb_disconnect,
2544 	.suspend	= rt2x00usb_suspend,
2545 	.resume		= rt2x00usb_resume,
2546 	.reset_resume	= rt2x00usb_resume,
2547 	.disable_hub_initiated_lpm = 1,
2548 };
2549 
2550 module_usb_driver(rt73usb_driver);
2551