1 /*
2 	Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 	<http://rt2x00.serialmonkey.com>
4 
5 	This program is free software; you can redistribute it and/or modify
6 	it under the terms of the GNU General Public License as published by
7 	the Free Software Foundation; either version 2 of the License, or
8 	(at your option) any later version.
9 
10 	This program is distributed in the hope that it will be useful,
11 	but WITHOUT ANY WARRANTY; without even the implied warranty of
12 	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 	GNU General Public License for more details.
14 
15 	You should have received a copy of the GNU General Public License
16 	along with this program; if not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 /*
20 	Module: rt61pci
21 	Abstract: Data structures and registers for the rt61pci module.
22 	Supported chipsets: RT2561, RT2561s, RT2661.
23  */
24 
25 #ifndef RT61PCI_H
26 #define RT61PCI_H
27 
28 /*
29  * RT chip PCI IDs.
30  */
31 #define RT2561s_PCI_ID			0x0301
32 #define RT2561_PCI_ID			0x0302
33 #define RT2661_PCI_ID			0x0401
34 
35 /*
36  * RF chip defines.
37  */
38 #define RF5225				0x0001
39 #define RF5325				0x0002
40 #define RF2527				0x0003
41 #define RF2529				0x0004
42 
43 /*
44  * Signal information.
45  * Default offset is required for RSSI <-> dBm conversion.
46  */
47 #define DEFAULT_RSSI_OFFSET		120
48 
49 /*
50  * Register layout information.
51  */
52 #define CSR_REG_BASE			0x3000
53 #define CSR_REG_SIZE			0x04b0
54 #define EEPROM_BASE			0x0000
55 #define EEPROM_SIZE			0x0100
56 #define BBP_BASE			0x0000
57 #define BBP_SIZE			0x0080
58 #define RF_BASE				0x0004
59 #define RF_SIZE				0x0010
60 
61 /*
62  * Number of TX queues.
63  */
64 #define NUM_TX_QUEUES			4
65 
66 /*
67  * PCI registers.
68  */
69 
70 /*
71  * HOST_CMD_CSR: For HOST to interrupt embedded processor
72  */
73 #define HOST_CMD_CSR			0x0008
74 #define HOST_CMD_CSR_HOST_COMMAND	FIELD32(0x0000007f)
75 #define HOST_CMD_CSR_INTERRUPT_MCU	FIELD32(0x00000080)
76 
77 /*
78  * MCU_CNTL_CSR
79  * SELECT_BANK: Select 8051 program bank.
80  * RESET: Enable 8051 reset state.
81  * READY: Ready state for 8051.
82  */
83 #define MCU_CNTL_CSR			0x000c
84 #define MCU_CNTL_CSR_SELECT_BANK	FIELD32(0x00000001)
85 #define MCU_CNTL_CSR_RESET		FIELD32(0x00000002)
86 #define MCU_CNTL_CSR_READY		FIELD32(0x00000004)
87 
88 /*
89  * SOFT_RESET_CSR
90  * FORCE_CLOCK_ON: Host force MAC clock ON
91  */
92 #define SOFT_RESET_CSR			0x0010
93 #define SOFT_RESET_CSR_FORCE_CLOCK_ON	FIELD32(0x00000002)
94 
95 /*
96  * MCU_INT_SOURCE_CSR: MCU interrupt source/mask register.
97  */
98 #define MCU_INT_SOURCE_CSR		0x0014
99 #define MCU_INT_SOURCE_CSR_0		FIELD32(0x00000001)
100 #define MCU_INT_SOURCE_CSR_1		FIELD32(0x00000002)
101 #define MCU_INT_SOURCE_CSR_2		FIELD32(0x00000004)
102 #define MCU_INT_SOURCE_CSR_3		FIELD32(0x00000008)
103 #define MCU_INT_SOURCE_CSR_4		FIELD32(0x00000010)
104 #define MCU_INT_SOURCE_CSR_5		FIELD32(0x00000020)
105 #define MCU_INT_SOURCE_CSR_6		FIELD32(0x00000040)
106 #define MCU_INT_SOURCE_CSR_7		FIELD32(0x00000080)
107 #define MCU_INT_SOURCE_CSR_TWAKEUP	FIELD32(0x00000100)
108 #define MCU_INT_SOURCE_CSR_TBTT_EXPIRE	FIELD32(0x00000200)
109 
110 /*
111  * MCU_INT_MASK_CSR: MCU interrupt source/mask register.
112  */
113 #define MCU_INT_MASK_CSR		0x0018
114 #define MCU_INT_MASK_CSR_0		FIELD32(0x00000001)
115 #define MCU_INT_MASK_CSR_1		FIELD32(0x00000002)
116 #define MCU_INT_MASK_CSR_2		FIELD32(0x00000004)
117 #define MCU_INT_MASK_CSR_3		FIELD32(0x00000008)
118 #define MCU_INT_MASK_CSR_4		FIELD32(0x00000010)
119 #define MCU_INT_MASK_CSR_5		FIELD32(0x00000020)
120 #define MCU_INT_MASK_CSR_6		FIELD32(0x00000040)
121 #define MCU_INT_MASK_CSR_7		FIELD32(0x00000080)
122 #define MCU_INT_MASK_CSR_TWAKEUP	FIELD32(0x00000100)
123 #define MCU_INT_MASK_CSR_TBTT_EXPIRE	FIELD32(0x00000200)
124 
125 /*
126  * PCI_USEC_CSR
127  */
128 #define PCI_USEC_CSR			0x001c
129 
130 /*
131  * Security key table memory.
132  * 16 entries 32-byte for shared key table
133  * 64 entries 32-byte for pairwise key table
134  * 64 entries 8-byte for pairwise ta key table
135  */
136 #define SHARED_KEY_TABLE_BASE		0x1000
137 #define PAIRWISE_KEY_TABLE_BASE		0x1200
138 #define PAIRWISE_TA_TABLE_BASE		0x1a00
139 
140 #define SHARED_KEY_ENTRY(__idx) \
141 	(SHARED_KEY_TABLE_BASE + \
142 		((__idx) * sizeof(struct hw_key_entry)))
143 #define PAIRWISE_KEY_ENTRY(__idx) \
144 	(PAIRWISE_KEY_TABLE_BASE + \
145 		((__idx) * sizeof(struct hw_key_entry)))
146 #define PAIRWISE_TA_ENTRY(__idx) \
147 	(PAIRWISE_TA_TABLE_BASE + \
148 		((__idx) * sizeof(struct hw_pairwise_ta_entry)))
149 
150 struct hw_key_entry {
151 	u8 key[16];
152 	u8 tx_mic[8];
153 	u8 rx_mic[8];
154 } __packed;
155 
156 struct hw_pairwise_ta_entry {
157 	u8 address[6];
158 	u8 cipher;
159 	u8 reserved;
160 } __packed;
161 
162 /*
163  * Other on-chip shared memory space.
164  */
165 #define HW_CIS_BASE			0x2000
166 #define HW_NULL_BASE			0x2b00
167 
168 /*
169  * Since NULL frame won't be that long (256 byte),
170  * We steal 16 tail bytes to save debugging settings.
171  */
172 #define HW_DEBUG_SETTING_BASE		0x2bf0
173 
174 /*
175  * On-chip BEACON frame space.
176  */
177 #define HW_BEACON_BASE0			0x2c00
178 #define HW_BEACON_BASE1			0x2d00
179 #define HW_BEACON_BASE2			0x2e00
180 #define HW_BEACON_BASE3			0x2f00
181 
182 #define HW_BEACON_OFFSET(__index) \
183 	(HW_BEACON_BASE0 + (__index * 0x0100))
184 
185 /*
186  * HOST-MCU shared memory.
187  */
188 
189 /*
190  * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
191  */
192 #define H2M_MAILBOX_CSR			0x2100
193 #define H2M_MAILBOX_CSR_ARG0		FIELD32(0x000000ff)
194 #define H2M_MAILBOX_CSR_ARG1		FIELD32(0x0000ff00)
195 #define H2M_MAILBOX_CSR_CMD_TOKEN	FIELD32(0x00ff0000)
196 #define H2M_MAILBOX_CSR_OWNER		FIELD32(0xff000000)
197 
198 /*
199  * MCU_LEDCS: LED control for MCU Mailbox.
200  */
201 #define MCU_LEDCS_LED_MODE		FIELD16(0x001f)
202 #define MCU_LEDCS_RADIO_STATUS		FIELD16(0x0020)
203 #define MCU_LEDCS_LINK_BG_STATUS	FIELD16(0x0040)
204 #define MCU_LEDCS_LINK_A_STATUS		FIELD16(0x0080)
205 #define MCU_LEDCS_POLARITY_GPIO_0	FIELD16(0x0100)
206 #define MCU_LEDCS_POLARITY_GPIO_1	FIELD16(0x0200)
207 #define MCU_LEDCS_POLARITY_GPIO_2	FIELD16(0x0400)
208 #define MCU_LEDCS_POLARITY_GPIO_3	FIELD16(0x0800)
209 #define MCU_LEDCS_POLARITY_GPIO_4	FIELD16(0x1000)
210 #define MCU_LEDCS_POLARITY_ACT		FIELD16(0x2000)
211 #define MCU_LEDCS_POLARITY_READY_BG	FIELD16(0x4000)
212 #define MCU_LEDCS_POLARITY_READY_A	FIELD16(0x8000)
213 
214 /*
215  * M2H_CMD_DONE_CSR.
216  */
217 #define M2H_CMD_DONE_CSR		0x2104
218 
219 /*
220  * MCU_TXOP_ARRAY_BASE.
221  */
222 #define MCU_TXOP_ARRAY_BASE		0x2110
223 
224 /*
225  * MAC Control/Status Registers(CSR).
226  * Some values are set in TU, whereas 1 TU == 1024 us.
227  */
228 
229 /*
230  * MAC_CSR0: ASIC revision number.
231  */
232 #define MAC_CSR0			0x3000
233 #define MAC_CSR0_REVISION		FIELD32(0x0000000f)
234 #define MAC_CSR0_CHIPSET		FIELD32(0x000ffff0)
235 
236 /*
237  * MAC_CSR1: System control register.
238  * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
239  * BBP_RESET: Hardware reset BBP.
240  * HOST_READY: Host is ready after initialization, 1: ready.
241  */
242 #define MAC_CSR1			0x3004
243 #define MAC_CSR1_SOFT_RESET		FIELD32(0x00000001)
244 #define MAC_CSR1_BBP_RESET		FIELD32(0x00000002)
245 #define MAC_CSR1_HOST_READY		FIELD32(0x00000004)
246 
247 /*
248  * MAC_CSR2: STA MAC register 0.
249  */
250 #define MAC_CSR2			0x3008
251 #define MAC_CSR2_BYTE0			FIELD32(0x000000ff)
252 #define MAC_CSR2_BYTE1			FIELD32(0x0000ff00)
253 #define MAC_CSR2_BYTE2			FIELD32(0x00ff0000)
254 #define MAC_CSR2_BYTE3			FIELD32(0xff000000)
255 
256 /*
257  * MAC_CSR3: STA MAC register 1.
258  * UNICAST_TO_ME_MASK:
259  *	Used to mask off bits from byte 5 of the MAC address
260  *	to determine the UNICAST_TO_ME bit for RX frames.
261  *	The full mask is complemented by BSS_ID_MASK:
262  *		MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
263  */
264 #define MAC_CSR3			0x300c
265 #define MAC_CSR3_BYTE4			FIELD32(0x000000ff)
266 #define MAC_CSR3_BYTE5			FIELD32(0x0000ff00)
267 #define MAC_CSR3_UNICAST_TO_ME_MASK	FIELD32(0x00ff0000)
268 
269 /*
270  * MAC_CSR4: BSSID register 0.
271  */
272 #define MAC_CSR4			0x3010
273 #define MAC_CSR4_BYTE0			FIELD32(0x000000ff)
274 #define MAC_CSR4_BYTE1			FIELD32(0x0000ff00)
275 #define MAC_CSR4_BYTE2			FIELD32(0x00ff0000)
276 #define MAC_CSR4_BYTE3			FIELD32(0xff000000)
277 
278 /*
279  * MAC_CSR5: BSSID register 1.
280  * BSS_ID_MASK:
281  *	This mask is used to mask off bits 0 and 1 of byte 5 of the
282  *	BSSID. This will make sure that those bits will be ignored
283  *	when determining the MY_BSS of RX frames.
284  *		0: 1-BSSID mode (BSS index = 0)
285  *		1: 2-BSSID mode (BSS index: Byte5, bit 0)
286  *		2: 2-BSSID mode (BSS index: byte5, bit 1)
287  *		3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
288  */
289 #define MAC_CSR5			0x3014
290 #define MAC_CSR5_BYTE4			FIELD32(0x000000ff)
291 #define MAC_CSR5_BYTE5			FIELD32(0x0000ff00)
292 #define MAC_CSR5_BSS_ID_MASK		FIELD32(0x00ff0000)
293 
294 /*
295  * MAC_CSR6: Maximum frame length register.
296  */
297 #define MAC_CSR6			0x3018
298 #define MAC_CSR6_MAX_FRAME_UNIT		FIELD32(0x00000fff)
299 
300 /*
301  * MAC_CSR7: Reserved
302  */
303 #define MAC_CSR7			0x301c
304 
305 /*
306  * MAC_CSR8: SIFS/EIFS register.
307  * All units are in US.
308  */
309 #define MAC_CSR8			0x3020
310 #define MAC_CSR8_SIFS			FIELD32(0x000000ff)
311 #define MAC_CSR8_SIFS_AFTER_RX_OFDM	FIELD32(0x0000ff00)
312 #define MAC_CSR8_EIFS			FIELD32(0xffff0000)
313 
314 /*
315  * MAC_CSR9: Back-Off control register.
316  * SLOT_TIME: Slot time, default is 20us for 802.11BG.
317  * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
318  * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
319  * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
320  */
321 #define MAC_CSR9			0x3024
322 #define MAC_CSR9_SLOT_TIME		FIELD32(0x000000ff)
323 #define MAC_CSR9_CWMIN			FIELD32(0x00000f00)
324 #define MAC_CSR9_CWMAX			FIELD32(0x0000f000)
325 #define MAC_CSR9_CW_SELECT		FIELD32(0x00010000)
326 
327 /*
328  * MAC_CSR10: Power state configuration.
329  */
330 #define MAC_CSR10			0x3028
331 
332 /*
333  * MAC_CSR11: Power saving transition time register.
334  * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
335  * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
336  * WAKEUP_LATENCY: In unit of TU.
337  */
338 #define MAC_CSR11			0x302c
339 #define MAC_CSR11_DELAY_AFTER_TBCN	FIELD32(0x000000ff)
340 #define MAC_CSR11_TBCN_BEFORE_WAKEUP	FIELD32(0x00007f00)
341 #define MAC_CSR11_AUTOWAKE		FIELD32(0x00008000)
342 #define MAC_CSR11_WAKEUP_LATENCY	FIELD32(0x000f0000)
343 
344 /*
345  * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
346  * CURRENT_STATE: 0:sleep, 1:awake.
347  * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
348  * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
349  */
350 #define MAC_CSR12			0x3030
351 #define MAC_CSR12_CURRENT_STATE		FIELD32(0x00000001)
352 #define MAC_CSR12_PUT_TO_SLEEP		FIELD32(0x00000002)
353 #define MAC_CSR12_FORCE_WAKEUP		FIELD32(0x00000004)
354 #define MAC_CSR12_BBP_CURRENT_STATE	FIELD32(0x00000008)
355 
356 /*
357  * MAC_CSR13: GPIO.
358  *	MAC_CSR13_VALx: GPIO value
359  *	MAC_CSR13_DIRx: GPIO direction: 0 = output; 1 = input
360  */
361 #define MAC_CSR13			0x3034
362 #define MAC_CSR13_VAL0			FIELD32(0x00000001)
363 #define MAC_CSR13_VAL1			FIELD32(0x00000002)
364 #define MAC_CSR13_VAL2			FIELD32(0x00000004)
365 #define MAC_CSR13_VAL3			FIELD32(0x00000008)
366 #define MAC_CSR13_VAL4			FIELD32(0x00000010)
367 #define MAC_CSR13_VAL5			FIELD32(0x00000020)
368 #define MAC_CSR13_DIR0			FIELD32(0x00000100)
369 #define MAC_CSR13_DIR1			FIELD32(0x00000200)
370 #define MAC_CSR13_DIR2			FIELD32(0x00000400)
371 #define MAC_CSR13_DIR3			FIELD32(0x00000800)
372 #define MAC_CSR13_DIR4			FIELD32(0x00001000)
373 #define MAC_CSR13_DIR5			FIELD32(0x00002000)
374 
375 /*
376  * MAC_CSR14: LED control register.
377  * ON_PERIOD: On period, default 70ms.
378  * OFF_PERIOD: Off period, default 30ms.
379  * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
380  * SW_LED: s/w LED, 1: ON, 0: OFF.
381  * HW_LED_POLARITY: 0: active low, 1: active high.
382  */
383 #define MAC_CSR14			0x3038
384 #define MAC_CSR14_ON_PERIOD		FIELD32(0x000000ff)
385 #define MAC_CSR14_OFF_PERIOD		FIELD32(0x0000ff00)
386 #define MAC_CSR14_HW_LED		FIELD32(0x00010000)
387 #define MAC_CSR14_SW_LED		FIELD32(0x00020000)
388 #define MAC_CSR14_HW_LED_POLARITY	FIELD32(0x00040000)
389 #define MAC_CSR14_SW_LED2		FIELD32(0x00080000)
390 
391 /*
392  * MAC_CSR15: NAV control.
393  */
394 #define MAC_CSR15			0x303c
395 
396 /*
397  * TXRX control registers.
398  * Some values are set in TU, whereas 1 TU == 1024 us.
399  */
400 
401 /*
402  * TXRX_CSR0: TX/RX configuration register.
403  * TSF_OFFSET: Default is 24.
404  * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
405  * DISABLE_RX: Disable Rx engine.
406  * DROP_CRC: Drop CRC error.
407  * DROP_PHYSICAL: Drop physical error.
408  * DROP_CONTROL: Drop control frame.
409  * DROP_NOT_TO_ME: Drop not to me unicast frame.
410  * DROP_TO_DS: Drop fram ToDs bit is true.
411  * DROP_VERSION_ERROR: Drop version error frame.
412  * DROP_MULTICAST: Drop multicast frames.
413  * DROP_BORADCAST: Drop broadcast frames.
414  * DROP_ACK_CTS: Drop received ACK and CTS.
415  */
416 #define TXRX_CSR0			0x3040
417 #define TXRX_CSR0_RX_ACK_TIMEOUT	FIELD32(0x000001ff)
418 #define TXRX_CSR0_TSF_OFFSET		FIELD32(0x00007e00)
419 #define TXRX_CSR0_AUTO_TX_SEQ		FIELD32(0x00008000)
420 #define TXRX_CSR0_DISABLE_RX		FIELD32(0x00010000)
421 #define TXRX_CSR0_DROP_CRC		FIELD32(0x00020000)
422 #define TXRX_CSR0_DROP_PHYSICAL		FIELD32(0x00040000)
423 #define TXRX_CSR0_DROP_CONTROL		FIELD32(0x00080000)
424 #define TXRX_CSR0_DROP_NOT_TO_ME	FIELD32(0x00100000)
425 #define TXRX_CSR0_DROP_TO_DS		FIELD32(0x00200000)
426 #define TXRX_CSR0_DROP_VERSION_ERROR	FIELD32(0x00400000)
427 #define TXRX_CSR0_DROP_MULTICAST	FIELD32(0x00800000)
428 #define TXRX_CSR0_DROP_BROADCAST	FIELD32(0x01000000)
429 #define TXRX_CSR0_DROP_ACK_CTS		FIELD32(0x02000000)
430 #define TXRX_CSR0_TX_WITHOUT_WAITING	FIELD32(0x04000000)
431 
432 /*
433  * TXRX_CSR1
434  */
435 #define TXRX_CSR1			0x3044
436 #define TXRX_CSR1_BBP_ID0		FIELD32(0x0000007f)
437 #define TXRX_CSR1_BBP_ID0_VALID		FIELD32(0x00000080)
438 #define TXRX_CSR1_BBP_ID1		FIELD32(0x00007f00)
439 #define TXRX_CSR1_BBP_ID1_VALID		FIELD32(0x00008000)
440 #define TXRX_CSR1_BBP_ID2		FIELD32(0x007f0000)
441 #define TXRX_CSR1_BBP_ID2_VALID		FIELD32(0x00800000)
442 #define TXRX_CSR1_BBP_ID3		FIELD32(0x7f000000)
443 #define TXRX_CSR1_BBP_ID3_VALID		FIELD32(0x80000000)
444 
445 /*
446  * TXRX_CSR2
447  */
448 #define TXRX_CSR2			0x3048
449 #define TXRX_CSR2_BBP_ID0		FIELD32(0x0000007f)
450 #define TXRX_CSR2_BBP_ID0_VALID		FIELD32(0x00000080)
451 #define TXRX_CSR2_BBP_ID1		FIELD32(0x00007f00)
452 #define TXRX_CSR2_BBP_ID1_VALID		FIELD32(0x00008000)
453 #define TXRX_CSR2_BBP_ID2		FIELD32(0x007f0000)
454 #define TXRX_CSR2_BBP_ID2_VALID		FIELD32(0x00800000)
455 #define TXRX_CSR2_BBP_ID3		FIELD32(0x7f000000)
456 #define TXRX_CSR2_BBP_ID3_VALID		FIELD32(0x80000000)
457 
458 /*
459  * TXRX_CSR3
460  */
461 #define TXRX_CSR3			0x304c
462 #define TXRX_CSR3_BBP_ID0		FIELD32(0x0000007f)
463 #define TXRX_CSR3_BBP_ID0_VALID		FIELD32(0x00000080)
464 #define TXRX_CSR3_BBP_ID1		FIELD32(0x00007f00)
465 #define TXRX_CSR3_BBP_ID1_VALID		FIELD32(0x00008000)
466 #define TXRX_CSR3_BBP_ID2		FIELD32(0x007f0000)
467 #define TXRX_CSR3_BBP_ID2_VALID		FIELD32(0x00800000)
468 #define TXRX_CSR3_BBP_ID3		FIELD32(0x7f000000)
469 #define TXRX_CSR3_BBP_ID3_VALID		FIELD32(0x80000000)
470 
471 /*
472  * TXRX_CSR4: Auto-Responder/Tx-retry register.
473  * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
474  * OFDM_TX_RATE_DOWN: 1:enable.
475  * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
476  * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
477  */
478 #define TXRX_CSR4			0x3050
479 #define TXRX_CSR4_TX_ACK_TIMEOUT	FIELD32(0x000000ff)
480 #define TXRX_CSR4_CNTL_ACK_POLICY	FIELD32(0x00000700)
481 #define TXRX_CSR4_ACK_CTS_PSM		FIELD32(0x00010000)
482 #define TXRX_CSR4_AUTORESPOND_ENABLE	FIELD32(0x00020000)
483 #define TXRX_CSR4_AUTORESPOND_PREAMBLE	FIELD32(0x00040000)
484 #define TXRX_CSR4_OFDM_TX_RATE_DOWN	FIELD32(0x00080000)
485 #define TXRX_CSR4_OFDM_TX_RATE_STEP	FIELD32(0x00300000)
486 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK	FIELD32(0x00400000)
487 #define TXRX_CSR4_LONG_RETRY_LIMIT	FIELD32(0x0f000000)
488 #define TXRX_CSR4_SHORT_RETRY_LIMIT	FIELD32(0xf0000000)
489 
490 /*
491  * TXRX_CSR5
492  */
493 #define TXRX_CSR5			0x3054
494 
495 /*
496  * TXRX_CSR6: ACK/CTS payload consumed time
497  */
498 #define TXRX_CSR6			0x3058
499 
500 /*
501  * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
502  */
503 #define TXRX_CSR7			0x305c
504 #define TXRX_CSR7_ACK_CTS_6MBS		FIELD32(0x000000ff)
505 #define TXRX_CSR7_ACK_CTS_9MBS		FIELD32(0x0000ff00)
506 #define TXRX_CSR7_ACK_CTS_12MBS		FIELD32(0x00ff0000)
507 #define TXRX_CSR7_ACK_CTS_18MBS		FIELD32(0xff000000)
508 
509 /*
510  * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
511  */
512 #define TXRX_CSR8			0x3060
513 #define TXRX_CSR8_ACK_CTS_24MBS		FIELD32(0x000000ff)
514 #define TXRX_CSR8_ACK_CTS_36MBS		FIELD32(0x0000ff00)
515 #define TXRX_CSR8_ACK_CTS_48MBS		FIELD32(0x00ff0000)
516 #define TXRX_CSR8_ACK_CTS_54MBS		FIELD32(0xff000000)
517 
518 /*
519  * TXRX_CSR9: Synchronization control register.
520  * BEACON_INTERVAL: In unit of 1/16 TU.
521  * TSF_TICKING: Enable TSF auto counting.
522  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
523  * BEACON_GEN: Enable beacon generator.
524  */
525 #define TXRX_CSR9			0x3064
526 #define TXRX_CSR9_BEACON_INTERVAL	FIELD32(0x0000ffff)
527 #define TXRX_CSR9_TSF_TICKING		FIELD32(0x00010000)
528 #define TXRX_CSR9_TSF_SYNC		FIELD32(0x00060000)
529 #define TXRX_CSR9_TBTT_ENABLE		FIELD32(0x00080000)
530 #define TXRX_CSR9_BEACON_GEN		FIELD32(0x00100000)
531 #define TXRX_CSR9_TIMESTAMP_COMPENSATE	FIELD32(0xff000000)
532 
533 /*
534  * TXRX_CSR10: BEACON alignment.
535  */
536 #define TXRX_CSR10			0x3068
537 
538 /*
539  * TXRX_CSR11: AES mask.
540  */
541 #define TXRX_CSR11			0x306c
542 
543 /*
544  * TXRX_CSR12: TSF low 32.
545  */
546 #define TXRX_CSR12			0x3070
547 #define TXRX_CSR12_LOW_TSFTIMER		FIELD32(0xffffffff)
548 
549 /*
550  * TXRX_CSR13: TSF high 32.
551  */
552 #define TXRX_CSR13			0x3074
553 #define TXRX_CSR13_HIGH_TSFTIMER	FIELD32(0xffffffff)
554 
555 /*
556  * TXRX_CSR14: TBTT timer.
557  */
558 #define TXRX_CSR14			0x3078
559 
560 /*
561  * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
562  */
563 #define TXRX_CSR15			0x307c
564 
565 /*
566  * PHY control registers.
567  * Some values are set in TU, whereas 1 TU == 1024 us.
568  */
569 
570 /*
571  * PHY_CSR0: RF/PS control.
572  */
573 #define PHY_CSR0			0x3080
574 #define PHY_CSR0_PA_PE_BG		FIELD32(0x00010000)
575 #define PHY_CSR0_PA_PE_A		FIELD32(0x00020000)
576 
577 /*
578  * PHY_CSR1
579  */
580 #define PHY_CSR1			0x3084
581 
582 /*
583  * PHY_CSR2: Pre-TX BBP control.
584  */
585 #define PHY_CSR2			0x3088
586 
587 /*
588  * PHY_CSR3: BBP serial control register.
589  * VALUE: Register value to program into BBP.
590  * REG_NUM: Selected BBP register.
591  * READ_CONTROL: 0: Write BBP, 1: Read BBP.
592  * BUSY: 1: ASIC is busy execute BBP programming.
593  */
594 #define PHY_CSR3			0x308c
595 #define PHY_CSR3_VALUE			FIELD32(0x000000ff)
596 #define PHY_CSR3_REGNUM			FIELD32(0x00007f00)
597 #define PHY_CSR3_READ_CONTROL		FIELD32(0x00008000)
598 #define PHY_CSR3_BUSY			FIELD32(0x00010000)
599 
600 /*
601  * PHY_CSR4: RF serial control register
602  * VALUE: Register value (include register id) serial out to RF/IF chip.
603  * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
604  * IF_SELECT: 1: select IF to program, 0: select RF to program.
605  * PLL_LD: RF PLL_LD status.
606  * BUSY: 1: ASIC is busy execute RF programming.
607  */
608 #define PHY_CSR4			0x3090
609 #define PHY_CSR4_VALUE			FIELD32(0x00ffffff)
610 #define PHY_CSR4_NUMBER_OF_BITS		FIELD32(0x1f000000)
611 #define PHY_CSR4_IF_SELECT		FIELD32(0x20000000)
612 #define PHY_CSR4_PLL_LD			FIELD32(0x40000000)
613 #define PHY_CSR4_BUSY			FIELD32(0x80000000)
614 
615 /*
616  * PHY_CSR5: RX to TX signal switch timing control.
617  */
618 #define PHY_CSR5			0x3094
619 #define PHY_CSR5_IQ_FLIP		FIELD32(0x00000004)
620 
621 /*
622  * PHY_CSR6: TX to RX signal timing control.
623  */
624 #define PHY_CSR6			0x3098
625 #define PHY_CSR6_IQ_FLIP		FIELD32(0x00000004)
626 
627 /*
628  * PHY_CSR7: TX DAC switching timing control.
629  */
630 #define PHY_CSR7			0x309c
631 
632 /*
633  * Security control register.
634  */
635 
636 /*
637  * SEC_CSR0: Shared key table control.
638  */
639 #define SEC_CSR0			0x30a0
640 #define SEC_CSR0_BSS0_KEY0_VALID	FIELD32(0x00000001)
641 #define SEC_CSR0_BSS0_KEY1_VALID	FIELD32(0x00000002)
642 #define SEC_CSR0_BSS0_KEY2_VALID	FIELD32(0x00000004)
643 #define SEC_CSR0_BSS0_KEY3_VALID	FIELD32(0x00000008)
644 #define SEC_CSR0_BSS1_KEY0_VALID	FIELD32(0x00000010)
645 #define SEC_CSR0_BSS1_KEY1_VALID	FIELD32(0x00000020)
646 #define SEC_CSR0_BSS1_KEY2_VALID	FIELD32(0x00000040)
647 #define SEC_CSR0_BSS1_KEY3_VALID	FIELD32(0x00000080)
648 #define SEC_CSR0_BSS2_KEY0_VALID	FIELD32(0x00000100)
649 #define SEC_CSR0_BSS2_KEY1_VALID	FIELD32(0x00000200)
650 #define SEC_CSR0_BSS2_KEY2_VALID	FIELD32(0x00000400)
651 #define SEC_CSR0_BSS2_KEY3_VALID	FIELD32(0x00000800)
652 #define SEC_CSR0_BSS3_KEY0_VALID	FIELD32(0x00001000)
653 #define SEC_CSR0_BSS3_KEY1_VALID	FIELD32(0x00002000)
654 #define SEC_CSR0_BSS3_KEY2_VALID	FIELD32(0x00004000)
655 #define SEC_CSR0_BSS3_KEY3_VALID	FIELD32(0x00008000)
656 
657 /*
658  * SEC_CSR1: Shared key table security mode register.
659  */
660 #define SEC_CSR1			0x30a4
661 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG	FIELD32(0x00000007)
662 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG	FIELD32(0x00000070)
663 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG	FIELD32(0x00000700)
664 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG	FIELD32(0x00007000)
665 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG	FIELD32(0x00070000)
666 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG	FIELD32(0x00700000)
667 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG	FIELD32(0x07000000)
668 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG	FIELD32(0x70000000)
669 
670 /*
671  * Pairwise key table valid bitmap registers.
672  * SEC_CSR2: pairwise key table valid bitmap 0.
673  * SEC_CSR3: pairwise key table valid bitmap 1.
674  */
675 #define SEC_CSR2			0x30a8
676 #define SEC_CSR3			0x30ac
677 
678 /*
679  * SEC_CSR4: Pairwise key table lookup control.
680  */
681 #define SEC_CSR4			0x30b0
682 #define SEC_CSR4_ENABLE_BSS0		FIELD32(0x00000001)
683 #define SEC_CSR4_ENABLE_BSS1		FIELD32(0x00000002)
684 #define SEC_CSR4_ENABLE_BSS2		FIELD32(0x00000004)
685 #define SEC_CSR4_ENABLE_BSS3		FIELD32(0x00000008)
686 
687 /*
688  * SEC_CSR5: shared key table security mode register.
689  */
690 #define SEC_CSR5			0x30b4
691 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG	FIELD32(0x00000007)
692 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG	FIELD32(0x00000070)
693 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG	FIELD32(0x00000700)
694 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG	FIELD32(0x00007000)
695 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG	FIELD32(0x00070000)
696 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG	FIELD32(0x00700000)
697 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG	FIELD32(0x07000000)
698 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG	FIELD32(0x70000000)
699 
700 /*
701  * STA control registers.
702  */
703 
704 /*
705  * STA_CSR0: RX PLCP error count & RX FCS error count.
706  */
707 #define STA_CSR0			0x30c0
708 #define STA_CSR0_FCS_ERROR		FIELD32(0x0000ffff)
709 #define STA_CSR0_PLCP_ERROR		FIELD32(0xffff0000)
710 
711 /*
712  * STA_CSR1: RX False CCA count & RX LONG frame count.
713  */
714 #define STA_CSR1			0x30c4
715 #define STA_CSR1_PHYSICAL_ERROR		FIELD32(0x0000ffff)
716 #define STA_CSR1_FALSE_CCA_ERROR	FIELD32(0xffff0000)
717 
718 /*
719  * STA_CSR2: TX Beacon count and RX FIFO overflow count.
720  */
721 #define STA_CSR2			0x30c8
722 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT	FIELD32(0x0000ffff)
723 #define STA_CSR2_RX_OVERFLOW_COUNT	FIELD32(0xffff0000)
724 
725 /*
726  * STA_CSR3: TX Beacon count.
727  */
728 #define STA_CSR3			0x30cc
729 #define STA_CSR3_TX_BEACON_COUNT	FIELD32(0x0000ffff)
730 
731 /*
732  * STA_CSR4: TX Result status register.
733  * VALID: 1:This register contains a valid TX result.
734  */
735 #define STA_CSR4			0x30d0
736 #define STA_CSR4_VALID			FIELD32(0x00000001)
737 #define STA_CSR4_TX_RESULT		FIELD32(0x0000000e)
738 #define STA_CSR4_RETRY_COUNT		FIELD32(0x000000f0)
739 #define STA_CSR4_PID_SUBTYPE		FIELD32(0x00001f00)
740 #define STA_CSR4_PID_TYPE		FIELD32(0x0000e000)
741 #define STA_CSR4_TXRATE			FIELD32(0x000f0000)
742 
743 /*
744  * QOS control registers.
745  */
746 
747 /*
748  * QOS_CSR0: TXOP holder MAC address register.
749  */
750 #define QOS_CSR0			0x30e0
751 #define QOS_CSR0_BYTE0			FIELD32(0x000000ff)
752 #define QOS_CSR0_BYTE1			FIELD32(0x0000ff00)
753 #define QOS_CSR0_BYTE2			FIELD32(0x00ff0000)
754 #define QOS_CSR0_BYTE3			FIELD32(0xff000000)
755 
756 /*
757  * QOS_CSR1: TXOP holder MAC address register.
758  */
759 #define QOS_CSR1			0x30e4
760 #define QOS_CSR1_BYTE4			FIELD32(0x000000ff)
761 #define QOS_CSR1_BYTE5			FIELD32(0x0000ff00)
762 
763 /*
764  * QOS_CSR2: TXOP holder timeout register.
765  */
766 #define QOS_CSR2			0x30e8
767 
768 /*
769  * RX QOS-CFPOLL MAC address register.
770  * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
771  * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
772  */
773 #define QOS_CSR3			0x30ec
774 #define QOS_CSR4			0x30f0
775 
776 /*
777  * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
778  */
779 #define QOS_CSR5			0x30f4
780 
781 /*
782  * Host DMA registers.
783  */
784 
785 /*
786  * AC0_BASE_CSR: AC_VO base address.
787  */
788 #define AC0_BASE_CSR			0x3400
789 #define AC0_BASE_CSR_RING_REGISTER	FIELD32(0xffffffff)
790 
791 /*
792  * AC1_BASE_CSR: AC_VI base address.
793  */
794 #define AC1_BASE_CSR			0x3404
795 #define AC1_BASE_CSR_RING_REGISTER	FIELD32(0xffffffff)
796 
797 /*
798  * AC2_BASE_CSR: AC_BE base address.
799  */
800 #define AC2_BASE_CSR			0x3408
801 #define AC2_BASE_CSR_RING_REGISTER	FIELD32(0xffffffff)
802 
803 /*
804  * AC3_BASE_CSR: AC_BK base address.
805  */
806 #define AC3_BASE_CSR			0x340c
807 #define AC3_BASE_CSR_RING_REGISTER	FIELD32(0xffffffff)
808 
809 /*
810  * MGMT_BASE_CSR: MGMT ring base address.
811  */
812 #define MGMT_BASE_CSR			0x3410
813 #define MGMT_BASE_CSR_RING_REGISTER	FIELD32(0xffffffff)
814 
815 /*
816  * TX_RING_CSR0: TX Ring size for AC_VO, AC_VI, AC_BE, AC_BK.
817  */
818 #define TX_RING_CSR0			0x3418
819 #define TX_RING_CSR0_AC0_RING_SIZE	FIELD32(0x000000ff)
820 #define TX_RING_CSR0_AC1_RING_SIZE	FIELD32(0x0000ff00)
821 #define TX_RING_CSR0_AC2_RING_SIZE	FIELD32(0x00ff0000)
822 #define TX_RING_CSR0_AC3_RING_SIZE	FIELD32(0xff000000)
823 
824 /*
825  * TX_RING_CSR1: TX Ring size for MGMT Ring, HCCA Ring
826  * TXD_SIZE: In unit of 32-bit.
827  */
828 #define TX_RING_CSR1			0x341c
829 #define TX_RING_CSR1_MGMT_RING_SIZE	FIELD32(0x000000ff)
830 #define TX_RING_CSR1_HCCA_RING_SIZE	FIELD32(0x0000ff00)
831 #define TX_RING_CSR1_TXD_SIZE		FIELD32(0x003f0000)
832 
833 /*
834  * AIFSN_CSR: AIFSN for each EDCA AC.
835  * AIFSN0: For AC_VO.
836  * AIFSN1: For AC_VI.
837  * AIFSN2: For AC_BE.
838  * AIFSN3: For AC_BK.
839  */
840 #define AIFSN_CSR			0x3420
841 #define AIFSN_CSR_AIFSN0		FIELD32(0x0000000f)
842 #define AIFSN_CSR_AIFSN1		FIELD32(0x000000f0)
843 #define AIFSN_CSR_AIFSN2		FIELD32(0x00000f00)
844 #define AIFSN_CSR_AIFSN3		FIELD32(0x0000f000)
845 
846 /*
847  * CWMIN_CSR: CWmin for each EDCA AC.
848  * CWMIN0: For AC_VO.
849  * CWMIN1: For AC_VI.
850  * CWMIN2: For AC_BE.
851  * CWMIN3: For AC_BK.
852  */
853 #define CWMIN_CSR			0x3424
854 #define CWMIN_CSR_CWMIN0		FIELD32(0x0000000f)
855 #define CWMIN_CSR_CWMIN1		FIELD32(0x000000f0)
856 #define CWMIN_CSR_CWMIN2		FIELD32(0x00000f00)
857 #define CWMIN_CSR_CWMIN3		FIELD32(0x0000f000)
858 
859 /*
860  * CWMAX_CSR: CWmax for each EDCA AC.
861  * CWMAX0: For AC_VO.
862  * CWMAX1: For AC_VI.
863  * CWMAX2: For AC_BE.
864  * CWMAX3: For AC_BK.
865  */
866 #define CWMAX_CSR			0x3428
867 #define CWMAX_CSR_CWMAX0		FIELD32(0x0000000f)
868 #define CWMAX_CSR_CWMAX1		FIELD32(0x000000f0)
869 #define CWMAX_CSR_CWMAX2		FIELD32(0x00000f00)
870 #define CWMAX_CSR_CWMAX3		FIELD32(0x0000f000)
871 
872 /*
873  * TX_DMA_DST_CSR: TX DMA destination
874  * 0: TX ring0, 1: TX ring1, 2: TX ring2 3: invalid
875  */
876 #define TX_DMA_DST_CSR			0x342c
877 #define TX_DMA_DST_CSR_DEST_AC0		FIELD32(0x00000003)
878 #define TX_DMA_DST_CSR_DEST_AC1		FIELD32(0x0000000c)
879 #define TX_DMA_DST_CSR_DEST_AC2		FIELD32(0x00000030)
880 #define TX_DMA_DST_CSR_DEST_AC3		FIELD32(0x000000c0)
881 #define TX_DMA_DST_CSR_DEST_MGMT	FIELD32(0x00000300)
882 
883 /*
884  * TX_CNTL_CSR: KICK/Abort TX.
885  * KICK_TX_AC0: For AC_VO.
886  * KICK_TX_AC1: For AC_VI.
887  * KICK_TX_AC2: For AC_BE.
888  * KICK_TX_AC3: For AC_BK.
889  * ABORT_TX_AC0: For AC_VO.
890  * ABORT_TX_AC1: For AC_VI.
891  * ABORT_TX_AC2: For AC_BE.
892  * ABORT_TX_AC3: For AC_BK.
893  */
894 #define TX_CNTL_CSR			0x3430
895 #define TX_CNTL_CSR_KICK_TX_AC0		FIELD32(0x00000001)
896 #define TX_CNTL_CSR_KICK_TX_AC1		FIELD32(0x00000002)
897 #define TX_CNTL_CSR_KICK_TX_AC2		FIELD32(0x00000004)
898 #define TX_CNTL_CSR_KICK_TX_AC3		FIELD32(0x00000008)
899 #define TX_CNTL_CSR_KICK_TX_MGMT	FIELD32(0x00000010)
900 #define TX_CNTL_CSR_ABORT_TX_AC0	FIELD32(0x00010000)
901 #define TX_CNTL_CSR_ABORT_TX_AC1	FIELD32(0x00020000)
902 #define TX_CNTL_CSR_ABORT_TX_AC2	FIELD32(0x00040000)
903 #define TX_CNTL_CSR_ABORT_TX_AC3	FIELD32(0x00080000)
904 #define TX_CNTL_CSR_ABORT_TX_MGMT	FIELD32(0x00100000)
905 
906 /*
907  * LOAD_TX_RING_CSR: Load RX desriptor
908  */
909 #define LOAD_TX_RING_CSR		0x3434
910 #define LOAD_TX_RING_CSR_LOAD_TXD_AC0	FIELD32(0x00000001)
911 #define LOAD_TX_RING_CSR_LOAD_TXD_AC1	FIELD32(0x00000002)
912 #define LOAD_TX_RING_CSR_LOAD_TXD_AC2	FIELD32(0x00000004)
913 #define LOAD_TX_RING_CSR_LOAD_TXD_AC3	FIELD32(0x00000008)
914 #define LOAD_TX_RING_CSR_LOAD_TXD_MGMT	FIELD32(0x00000010)
915 
916 /*
917  * Several read-only registers, for debugging.
918  */
919 #define AC0_TXPTR_CSR			0x3438
920 #define AC1_TXPTR_CSR			0x343c
921 #define AC2_TXPTR_CSR			0x3440
922 #define AC3_TXPTR_CSR			0x3444
923 #define MGMT_TXPTR_CSR			0x3448
924 
925 /*
926  * RX_BASE_CSR
927  */
928 #define RX_BASE_CSR			0x3450
929 #define RX_BASE_CSR_RING_REGISTER	FIELD32(0xffffffff)
930 
931 /*
932  * RX_RING_CSR.
933  * RXD_SIZE: In unit of 32-bit.
934  */
935 #define RX_RING_CSR			0x3454
936 #define RX_RING_CSR_RING_SIZE		FIELD32(0x000000ff)
937 #define RX_RING_CSR_RXD_SIZE		FIELD32(0x00003f00)
938 #define RX_RING_CSR_RXD_WRITEBACK_SIZE	FIELD32(0x00070000)
939 
940 /*
941  * RX_CNTL_CSR
942  */
943 #define RX_CNTL_CSR			0x3458
944 #define RX_CNTL_CSR_ENABLE_RX_DMA	FIELD32(0x00000001)
945 #define RX_CNTL_CSR_LOAD_RXD		FIELD32(0x00000002)
946 
947 /*
948  * RXPTR_CSR: Read-only, for debugging.
949  */
950 #define RXPTR_CSR			0x345c
951 
952 /*
953  * PCI_CFG_CSR
954  */
955 #define PCI_CFG_CSR			0x3460
956 
957 /*
958  * BUF_FORMAT_CSR
959  */
960 #define BUF_FORMAT_CSR			0x3464
961 
962 /*
963  * INT_SOURCE_CSR: Interrupt source register.
964  * Write one to clear corresponding bit.
965  */
966 #define INT_SOURCE_CSR			0x3468
967 #define INT_SOURCE_CSR_TXDONE		FIELD32(0x00000001)
968 #define INT_SOURCE_CSR_RXDONE		FIELD32(0x00000002)
969 #define INT_SOURCE_CSR_BEACON_DONE	FIELD32(0x00000004)
970 #define INT_SOURCE_CSR_TX_ABORT_DONE	FIELD32(0x00000010)
971 #define INT_SOURCE_CSR_AC0_DMA_DONE	FIELD32(0x00010000)
972 #define INT_SOURCE_CSR_AC1_DMA_DONE	FIELD32(0x00020000)
973 #define INT_SOURCE_CSR_AC2_DMA_DONE	FIELD32(0x00040000)
974 #define INT_SOURCE_CSR_AC3_DMA_DONE	FIELD32(0x00080000)
975 #define INT_SOURCE_CSR_MGMT_DMA_DONE	FIELD32(0x00100000)
976 #define INT_SOURCE_CSR_HCCA_DMA_DONE	FIELD32(0x00200000)
977 
978 /*
979  * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
980  * MITIGATION_PERIOD: Interrupt mitigation in unit of 32 PCI clock.
981  */
982 #define INT_MASK_CSR			0x346c
983 #define INT_MASK_CSR_TXDONE		FIELD32(0x00000001)
984 #define INT_MASK_CSR_RXDONE		FIELD32(0x00000002)
985 #define INT_MASK_CSR_BEACON_DONE	FIELD32(0x00000004)
986 #define INT_MASK_CSR_TX_ABORT_DONE	FIELD32(0x00000010)
987 #define INT_MASK_CSR_ENABLE_MITIGATION	FIELD32(0x00000080)
988 #define INT_MASK_CSR_MITIGATION_PERIOD	FIELD32(0x0000ff00)
989 #define INT_MASK_CSR_AC0_DMA_DONE	FIELD32(0x00010000)
990 #define INT_MASK_CSR_AC1_DMA_DONE	FIELD32(0x00020000)
991 #define INT_MASK_CSR_AC2_DMA_DONE	FIELD32(0x00040000)
992 #define INT_MASK_CSR_AC3_DMA_DONE	FIELD32(0x00080000)
993 #define INT_MASK_CSR_MGMT_DMA_DONE	FIELD32(0x00100000)
994 #define INT_MASK_CSR_HCCA_DMA_DONE	FIELD32(0x00200000)
995 
996 /*
997  * E2PROM_CSR: EEPROM control register.
998  * RELOAD: Write 1 to reload eeprom content.
999  * TYPE_93C46: 1: 93c46, 0:93c66.
1000  * LOAD_STATUS: 1:loading, 0:done.
1001  */
1002 #define E2PROM_CSR			0x3470
1003 #define E2PROM_CSR_RELOAD		FIELD32(0x00000001)
1004 #define E2PROM_CSR_DATA_CLOCK		FIELD32(0x00000002)
1005 #define E2PROM_CSR_CHIP_SELECT		FIELD32(0x00000004)
1006 #define E2PROM_CSR_DATA_IN		FIELD32(0x00000008)
1007 #define E2PROM_CSR_DATA_OUT		FIELD32(0x00000010)
1008 #define E2PROM_CSR_TYPE_93C46		FIELD32(0x00000020)
1009 #define E2PROM_CSR_LOAD_STATUS		FIELD32(0x00000040)
1010 
1011 /*
1012  * AC_TXOP_CSR0: AC_VO/AC_VI TXOP register.
1013  * AC0_TX_OP: For AC_VO, in unit of 32us.
1014  * AC1_TX_OP: For AC_VI, in unit of 32us.
1015  */
1016 #define AC_TXOP_CSR0			0x3474
1017 #define AC_TXOP_CSR0_AC0_TX_OP		FIELD32(0x0000ffff)
1018 #define AC_TXOP_CSR0_AC1_TX_OP		FIELD32(0xffff0000)
1019 
1020 /*
1021  * AC_TXOP_CSR1: AC_BE/AC_BK TXOP register.
1022  * AC2_TX_OP: For AC_BE, in unit of 32us.
1023  * AC3_TX_OP: For AC_BK, in unit of 32us.
1024  */
1025 #define AC_TXOP_CSR1			0x3478
1026 #define AC_TXOP_CSR1_AC2_TX_OP		FIELD32(0x0000ffff)
1027 #define AC_TXOP_CSR1_AC3_TX_OP		FIELD32(0xffff0000)
1028 
1029 /*
1030  * DMA_STATUS_CSR
1031  */
1032 #define DMA_STATUS_CSR			0x3480
1033 
1034 /*
1035  * TEST_MODE_CSR
1036  */
1037 #define TEST_MODE_CSR			0x3484
1038 
1039 /*
1040  * UART0_TX_CSR
1041  */
1042 #define UART0_TX_CSR			0x3488
1043 
1044 /*
1045  * UART0_RX_CSR
1046  */
1047 #define UART0_RX_CSR			0x348c
1048 
1049 /*
1050  * UART0_FRAME_CSR
1051  */
1052 #define UART0_FRAME_CSR			0x3490
1053 
1054 /*
1055  * UART0_BUFFER_CSR
1056  */
1057 #define UART0_BUFFER_CSR		0x3494
1058 
1059 /*
1060  * IO_CNTL_CSR
1061  * RF_PS: Set RF interface value to power save
1062  */
1063 #define IO_CNTL_CSR			0x3498
1064 #define IO_CNTL_CSR_RF_PS		FIELD32(0x00000004)
1065 
1066 /*
1067  * UART_INT_SOURCE_CSR
1068  */
1069 #define UART_INT_SOURCE_CSR		0x34a8
1070 
1071 /*
1072  * UART_INT_MASK_CSR
1073  */
1074 #define UART_INT_MASK_CSR		0x34ac
1075 
1076 /*
1077  * PBF_QUEUE_CSR
1078  */
1079 #define PBF_QUEUE_CSR			0x34b0
1080 
1081 /*
1082  * Firmware DMA registers.
1083  * Firmware DMA registers are dedicated for MCU usage
1084  * and should not be touched by host driver.
1085  * Therefore we skip the definition of these registers.
1086  */
1087 #define FW_TX_BASE_CSR			0x34c0
1088 #define FW_TX_START_CSR			0x34c4
1089 #define FW_TX_LAST_CSR			0x34c8
1090 #define FW_MODE_CNTL_CSR		0x34cc
1091 #define FW_TXPTR_CSR			0x34d0
1092 
1093 /*
1094  * 8051 firmware image.
1095  */
1096 #define FIRMWARE_RT2561			"rt2561.bin"
1097 #define FIRMWARE_RT2561s		"rt2561s.bin"
1098 #define FIRMWARE_RT2661			"rt2661.bin"
1099 #define FIRMWARE_IMAGE_BASE		0x4000
1100 
1101 /*
1102  * BBP registers.
1103  * The wordsize of the BBP is 8 bits.
1104  */
1105 
1106 /*
1107  * R2
1108  */
1109 #define BBP_R2_BG_MODE			FIELD8(0x20)
1110 
1111 /*
1112  * R3
1113  */
1114 #define BBP_R3_SMART_MODE		FIELD8(0x01)
1115 
1116 /*
1117  * R4: RX antenna control
1118  * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
1119  */
1120 
1121 /*
1122  * ANTENNA_CONTROL semantics (guessed):
1123  * 0x1: Software controlled antenna switching (fixed or SW diversity)
1124  * 0x2: Hardware diversity.
1125  */
1126 #define BBP_R4_RX_ANTENNA_CONTROL	FIELD8(0x03)
1127 #define BBP_R4_RX_FRAME_END		FIELD8(0x20)
1128 
1129 /*
1130  * R77
1131  */
1132 #define BBP_R77_RX_ANTENNA		FIELD8(0x03)
1133 
1134 /*
1135  * RF registers
1136  */
1137 
1138 /*
1139  * RF 3
1140  */
1141 #define RF3_TXPOWER			FIELD32(0x00003e00)
1142 
1143 /*
1144  * RF 4
1145  */
1146 #define RF4_FREQ_OFFSET			FIELD32(0x0003f000)
1147 
1148 /*
1149  * EEPROM content.
1150  * The wordsize of the EEPROM is 16 bits.
1151  */
1152 
1153 /*
1154  * HW MAC address.
1155  */
1156 #define EEPROM_MAC_ADDR_0		0x0002
1157 #define EEPROM_MAC_ADDR_BYTE0		FIELD16(0x00ff)
1158 #define EEPROM_MAC_ADDR_BYTE1		FIELD16(0xff00)
1159 #define EEPROM_MAC_ADDR1		0x0003
1160 #define EEPROM_MAC_ADDR_BYTE2		FIELD16(0x00ff)
1161 #define EEPROM_MAC_ADDR_BYTE3		FIELD16(0xff00)
1162 #define EEPROM_MAC_ADDR_2		0x0004
1163 #define EEPROM_MAC_ADDR_BYTE4		FIELD16(0x00ff)
1164 #define EEPROM_MAC_ADDR_BYTE5		FIELD16(0xff00)
1165 
1166 /*
1167  * EEPROM antenna.
1168  * ANTENNA_NUM: Number of antenna's.
1169  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1170  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1171  * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
1172  * DYN_TXAGC: Dynamic TX AGC control.
1173  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
1174  * RF_TYPE: Rf_type of this adapter.
1175  */
1176 #define EEPROM_ANTENNA			0x0010
1177 #define EEPROM_ANTENNA_NUM		FIELD16(0x0003)
1178 #define EEPROM_ANTENNA_TX_DEFAULT	FIELD16(0x000c)
1179 #define EEPROM_ANTENNA_RX_DEFAULT	FIELD16(0x0030)
1180 #define EEPROM_ANTENNA_FRAME_TYPE	FIELD16(0x0040)
1181 #define EEPROM_ANTENNA_DYN_TXAGC	FIELD16(0x0200)
1182 #define EEPROM_ANTENNA_HARDWARE_RADIO	FIELD16(0x0400)
1183 #define EEPROM_ANTENNA_RF_TYPE		FIELD16(0xf800)
1184 
1185 /*
1186  * EEPROM NIC config.
1187  * ENABLE_DIVERSITY: 1:enable, 0:disable.
1188  * EXTERNAL_LNA_BG: External LNA enable for 2.4G.
1189  * CARDBUS_ACCEL: 0:enable, 1:disable.
1190  * EXTERNAL_LNA_A: External LNA enable for 5G.
1191  */
1192 #define EEPROM_NIC			0x0011
1193 #define EEPROM_NIC_ENABLE_DIVERSITY	FIELD16(0x0001)
1194 #define EEPROM_NIC_TX_DIVERSITY		FIELD16(0x0002)
1195 #define EEPROM_NIC_RX_FIXED		FIELD16(0x0004)
1196 #define EEPROM_NIC_TX_FIXED		FIELD16(0x0008)
1197 #define EEPROM_NIC_EXTERNAL_LNA_BG	FIELD16(0x0010)
1198 #define EEPROM_NIC_CARDBUS_ACCEL	FIELD16(0x0020)
1199 #define EEPROM_NIC_EXTERNAL_LNA_A	FIELD16(0x0040)
1200 
1201 /*
1202  * EEPROM geography.
1203  * GEO_A: Default geographical setting for 5GHz band
1204  * GEO: Default geographical setting.
1205  */
1206 #define EEPROM_GEOGRAPHY		0x0012
1207 #define EEPROM_GEOGRAPHY_GEO_A		FIELD16(0x00ff)
1208 #define EEPROM_GEOGRAPHY_GEO		FIELD16(0xff00)
1209 
1210 /*
1211  * EEPROM BBP.
1212  */
1213 #define EEPROM_BBP_START		0x0013
1214 #define EEPROM_BBP_SIZE			16
1215 #define EEPROM_BBP_VALUE		FIELD16(0x00ff)
1216 #define EEPROM_BBP_REG_ID		FIELD16(0xff00)
1217 
1218 /*
1219  * EEPROM TXPOWER 802.11G
1220  */
1221 #define EEPROM_TXPOWER_G_START		0x0023
1222 #define EEPROM_TXPOWER_G_SIZE		7
1223 #define EEPROM_TXPOWER_G_1		FIELD16(0x00ff)
1224 #define EEPROM_TXPOWER_G_2		FIELD16(0xff00)
1225 
1226 /*
1227  * EEPROM Frequency
1228  */
1229 #define EEPROM_FREQ			0x002f
1230 #define EEPROM_FREQ_OFFSET		FIELD16(0x00ff)
1231 #define EEPROM_FREQ_SEQ_MASK		FIELD16(0xff00)
1232 #define EEPROM_FREQ_SEQ			FIELD16(0x0300)
1233 
1234 /*
1235  * EEPROM LED.
1236  * POLARITY_RDY_G: Polarity RDY_G setting.
1237  * POLARITY_RDY_A: Polarity RDY_A setting.
1238  * POLARITY_ACT: Polarity ACT setting.
1239  * POLARITY_GPIO_0: Polarity GPIO0 setting.
1240  * POLARITY_GPIO_1: Polarity GPIO1 setting.
1241  * POLARITY_GPIO_2: Polarity GPIO2 setting.
1242  * POLARITY_GPIO_3: Polarity GPIO3 setting.
1243  * POLARITY_GPIO_4: Polarity GPIO4 setting.
1244  * LED_MODE: Led mode.
1245  */
1246 #define EEPROM_LED			0x0030
1247 #define EEPROM_LED_POLARITY_RDY_G	FIELD16(0x0001)
1248 #define EEPROM_LED_POLARITY_RDY_A	FIELD16(0x0002)
1249 #define EEPROM_LED_POLARITY_ACT		FIELD16(0x0004)
1250 #define EEPROM_LED_POLARITY_GPIO_0	FIELD16(0x0008)
1251 #define EEPROM_LED_POLARITY_GPIO_1	FIELD16(0x0010)
1252 #define EEPROM_LED_POLARITY_GPIO_2	FIELD16(0x0020)
1253 #define EEPROM_LED_POLARITY_GPIO_3	FIELD16(0x0040)
1254 #define EEPROM_LED_POLARITY_GPIO_4	FIELD16(0x0080)
1255 #define EEPROM_LED_LED_MODE		FIELD16(0x1f00)
1256 
1257 /*
1258  * EEPROM TXPOWER 802.11A
1259  */
1260 #define EEPROM_TXPOWER_A_START		0x0031
1261 #define EEPROM_TXPOWER_A_SIZE		12
1262 #define EEPROM_TXPOWER_A_1		FIELD16(0x00ff)
1263 #define EEPROM_TXPOWER_A_2		FIELD16(0xff00)
1264 
1265 /*
1266  * EEPROM RSSI offset 802.11BG
1267  */
1268 #define EEPROM_RSSI_OFFSET_BG		0x004d
1269 #define EEPROM_RSSI_OFFSET_BG_1		FIELD16(0x00ff)
1270 #define EEPROM_RSSI_OFFSET_BG_2		FIELD16(0xff00)
1271 
1272 /*
1273  * EEPROM RSSI offset 802.11A
1274  */
1275 #define EEPROM_RSSI_OFFSET_A		0x004e
1276 #define EEPROM_RSSI_OFFSET_A_1		FIELD16(0x00ff)
1277 #define EEPROM_RSSI_OFFSET_A_2		FIELD16(0xff00)
1278 
1279 /*
1280  * MCU mailbox commands.
1281  */
1282 #define MCU_SLEEP			0x30
1283 #define MCU_WAKEUP			0x31
1284 #define MCU_LED				0x50
1285 #define MCU_LED_STRENGTH		0x52
1286 
1287 /*
1288  * DMA descriptor defines.
1289  */
1290 #define TXD_DESC_SIZE			(16 * sizeof(__le32))
1291 #define TXINFO_SIZE			(6 * sizeof(__le32))
1292 #define RXD_DESC_SIZE			(16 * sizeof(__le32))
1293 
1294 /*
1295  * TX descriptor format for TX, PRIO and Beacon Ring.
1296  */
1297 
1298 /*
1299  * Word0
1300  * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
1301  * KEY_TABLE: Use per-client pairwise KEY table.
1302  * KEY_INDEX:
1303  * Key index (0~31) to the pairwise KEY table.
1304  * 0~3 to shared KEY table 0 (BSS0).
1305  * 4~7 to shared KEY table 1 (BSS1).
1306  * 8~11 to shared KEY table 2 (BSS2).
1307  * 12~15 to shared KEY table 3 (BSS3).
1308  * BURST: Next frame belongs to same "burst" event.
1309  */
1310 #define TXD_W0_OWNER_NIC		FIELD32(0x00000001)
1311 #define TXD_W0_VALID			FIELD32(0x00000002)
1312 #define TXD_W0_MORE_FRAG		FIELD32(0x00000004)
1313 #define TXD_W0_ACK			FIELD32(0x00000008)
1314 #define TXD_W0_TIMESTAMP		FIELD32(0x00000010)
1315 #define TXD_W0_OFDM			FIELD32(0x00000020)
1316 #define TXD_W0_IFS			FIELD32(0x00000040)
1317 #define TXD_W0_RETRY_MODE		FIELD32(0x00000080)
1318 #define TXD_W0_TKIP_MIC			FIELD32(0x00000100)
1319 #define TXD_W0_KEY_TABLE		FIELD32(0x00000200)
1320 #define TXD_W0_KEY_INDEX		FIELD32(0x0000fc00)
1321 #define TXD_W0_DATABYTE_COUNT		FIELD32(0x0fff0000)
1322 #define TXD_W0_BURST			FIELD32(0x10000000)
1323 #define TXD_W0_CIPHER_ALG		FIELD32(0xe0000000)
1324 
1325 /*
1326  * Word1
1327  * HOST_Q_ID: EDCA/HCCA queue ID.
1328  * HW_SEQUENCE: MAC overwrites the frame sequence number.
1329  * BUFFER_COUNT: Number of buffers in this TXD.
1330  */
1331 #define TXD_W1_HOST_Q_ID		FIELD32(0x0000000f)
1332 #define TXD_W1_AIFSN			FIELD32(0x000000f0)
1333 #define TXD_W1_CWMIN			FIELD32(0x00000f00)
1334 #define TXD_W1_CWMAX			FIELD32(0x0000f000)
1335 #define TXD_W1_IV_OFFSET		FIELD32(0x003f0000)
1336 #define TXD_W1_PIGGY_BACK		FIELD32(0x01000000)
1337 #define TXD_W1_HW_SEQUENCE		FIELD32(0x10000000)
1338 #define TXD_W1_BUFFER_COUNT		FIELD32(0xe0000000)
1339 
1340 /*
1341  * Word2: PLCP information
1342  */
1343 #define TXD_W2_PLCP_SIGNAL		FIELD32(0x000000ff)
1344 #define TXD_W2_PLCP_SERVICE		FIELD32(0x0000ff00)
1345 #define TXD_W2_PLCP_LENGTH_LOW		FIELD32(0x00ff0000)
1346 #define TXD_W2_PLCP_LENGTH_HIGH		FIELD32(0xff000000)
1347 
1348 /*
1349  * Word3
1350  */
1351 #define TXD_W3_IV			FIELD32(0xffffffff)
1352 
1353 /*
1354  * Word4
1355  */
1356 #define TXD_W4_EIV			FIELD32(0xffffffff)
1357 
1358 /*
1359  * Word5
1360  * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
1361  * TXD_W5_PID_SUBTYPE: Driver assigned packet ID index for txdone handler.
1362  * TXD_W5_PID_TYPE: Driver assigned packet ID type for txdone handler.
1363  * WAITING_DMA_DONE_INT: TXD been filled with data
1364  * and waiting for TxDoneISR housekeeping.
1365  */
1366 #define TXD_W5_FRAME_OFFSET		FIELD32(0x000000ff)
1367 #define TXD_W5_PID_SUBTYPE		FIELD32(0x00001f00)
1368 #define TXD_W5_PID_TYPE			FIELD32(0x0000e000)
1369 #define TXD_W5_TX_POWER			FIELD32(0x00ff0000)
1370 #define TXD_W5_WAITING_DMA_DONE_INT	FIELD32(0x01000000)
1371 
1372 /*
1373  * the above 24-byte is called TXINFO and will be DMAed to MAC block
1374  * through TXFIFO. MAC block use this TXINFO to control the transmission
1375  * behavior of this frame.
1376  * The following fields are not used by MAC block.
1377  * They are used by DMA block and HOST driver only.
1378  * Once a frame has been DMA to ASIC, all the following fields are useless
1379  * to ASIC.
1380  */
1381 
1382 /*
1383  * Word6-10: Buffer physical address
1384  */
1385 #define TXD_W6_BUFFER_PHYSICAL_ADDRESS	FIELD32(0xffffffff)
1386 #define TXD_W7_BUFFER_PHYSICAL_ADDRESS	FIELD32(0xffffffff)
1387 #define TXD_W8_BUFFER_PHYSICAL_ADDRESS	FIELD32(0xffffffff)
1388 #define TXD_W9_BUFFER_PHYSICAL_ADDRESS	FIELD32(0xffffffff)
1389 #define TXD_W10_BUFFER_PHYSICAL_ADDRESS	FIELD32(0xffffffff)
1390 
1391 /*
1392  * Word11-13: Buffer length
1393  */
1394 #define TXD_W11_BUFFER_LENGTH0		FIELD32(0x00000fff)
1395 #define TXD_W11_BUFFER_LENGTH1		FIELD32(0x0fff0000)
1396 #define TXD_W12_BUFFER_LENGTH2		FIELD32(0x00000fff)
1397 #define TXD_W12_BUFFER_LENGTH3		FIELD32(0x0fff0000)
1398 #define TXD_W13_BUFFER_LENGTH4		FIELD32(0x00000fff)
1399 
1400 /*
1401  * Word14
1402  */
1403 #define TXD_W14_SK_BUFFER		FIELD32(0xffffffff)
1404 
1405 /*
1406  * Word15
1407  */
1408 #define TXD_W15_NEXT_SK_BUFFER		FIELD32(0xffffffff)
1409 
1410 /*
1411  * RX descriptor format for RX Ring.
1412  */
1413 
1414 /*
1415  * Word0
1416  * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
1417  * KEY_INDEX: Decryption key actually used.
1418  */
1419 #define RXD_W0_OWNER_NIC		FIELD32(0x00000001)
1420 #define RXD_W0_DROP			FIELD32(0x00000002)
1421 #define RXD_W0_UNICAST_TO_ME		FIELD32(0x00000004)
1422 #define RXD_W0_MULTICAST		FIELD32(0x00000008)
1423 #define RXD_W0_BROADCAST		FIELD32(0x00000010)
1424 #define RXD_W0_MY_BSS			FIELD32(0x00000020)
1425 #define RXD_W0_CRC_ERROR		FIELD32(0x00000040)
1426 #define RXD_W0_OFDM			FIELD32(0x00000080)
1427 #define RXD_W0_CIPHER_ERROR		FIELD32(0x00000300)
1428 #define RXD_W0_KEY_INDEX		FIELD32(0x0000fc00)
1429 #define RXD_W0_DATABYTE_COUNT		FIELD32(0x0fff0000)
1430 #define RXD_W0_CIPHER_ALG		FIELD32(0xe0000000)
1431 
1432 /*
1433  * Word1
1434  * SIGNAL: RX raw data rate reported by BBP.
1435  */
1436 #define RXD_W1_SIGNAL			FIELD32(0x000000ff)
1437 #define RXD_W1_RSSI_AGC			FIELD32(0x00001f00)
1438 #define RXD_W1_RSSI_LNA			FIELD32(0x00006000)
1439 #define RXD_W1_FRAME_OFFSET		FIELD32(0x7f000000)
1440 
1441 /*
1442  * Word2
1443  * IV: Received IV of originally encrypted.
1444  */
1445 #define RXD_W2_IV			FIELD32(0xffffffff)
1446 
1447 /*
1448  * Word3
1449  * EIV: Received EIV of originally encrypted.
1450  */
1451 #define RXD_W3_EIV			FIELD32(0xffffffff)
1452 
1453 /*
1454  * Word4
1455  * ICV: Received ICV of originally encrypted.
1456  * NOTE: This is a guess, the official definition is "reserved"
1457  */
1458 #define RXD_W4_ICV			FIELD32(0xffffffff)
1459 
1460 /*
1461  * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1462  * and passed to the HOST driver.
1463  * The following fields are for DMA block and HOST usage only.
1464  * Can't be touched by ASIC MAC block.
1465  */
1466 
1467 /*
1468  * Word5
1469  */
1470 #define RXD_W5_BUFFER_PHYSICAL_ADDRESS	FIELD32(0xffffffff)
1471 
1472 /*
1473  * Word6-15: Reserved
1474  */
1475 #define RXD_W6_RESERVED			FIELD32(0xffffffff)
1476 #define RXD_W7_RESERVED			FIELD32(0xffffffff)
1477 #define RXD_W8_RESERVED			FIELD32(0xffffffff)
1478 #define RXD_W9_RESERVED			FIELD32(0xffffffff)
1479 #define RXD_W10_RESERVED		FIELD32(0xffffffff)
1480 #define RXD_W11_RESERVED		FIELD32(0xffffffff)
1481 #define RXD_W12_RESERVED		FIELD32(0xffffffff)
1482 #define RXD_W13_RESERVED		FIELD32(0xffffffff)
1483 #define RXD_W14_RESERVED		FIELD32(0xffffffff)
1484 #define RXD_W15_RESERVED		FIELD32(0xffffffff)
1485 
1486 /*
1487  * Macros for converting txpower from EEPROM to mac80211 value
1488  * and from mac80211 value to register value.
1489  */
1490 #define MIN_TXPOWER	0
1491 #define MAX_TXPOWER	31
1492 #define DEFAULT_TXPOWER	24
1493 
1494 #define TXPOWER_FROM_DEV(__txpower) \
1495 	(((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1496 
1497 #define TXPOWER_TO_DEV(__txpower) \
1498 	clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
1499 
1500 #endif /* RT61PCI_H */
1501