1 /* 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 3 <http://rt2x00.serialmonkey.com> 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 /* 20 Module: rt61pci 21 Abstract: rt61pci device specific routines. 22 Supported chipsets: RT2561, RT2561s, RT2661. 23 */ 24 25 #include <linux/crc-itu-t.h> 26 #include <linux/delay.h> 27 #include <linux/etherdevice.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/eeprom_93cx6.h> 33 34 #include "rt2x00.h" 35 #include "rt2x00mmio.h" 36 #include "rt2x00pci.h" 37 #include "rt61pci.h" 38 39 /* 40 * Allow hardware encryption to be disabled. 41 */ 42 static bool modparam_nohwcrypt = false; 43 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, 0444); 44 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 45 46 /* 47 * Register access. 48 * BBP and RF register require indirect register access, 49 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this. 50 * These indirect registers work with busy bits, 51 * and we will try maximal REGISTER_BUSY_COUNT times to access 52 * the register while taking a REGISTER_BUSY_DELAY us delay 53 * between each attempt. When the busy bit is still set at that time, 54 * the access attempt is considered to have failed, 55 * and we will print an error. 56 */ 57 #define WAIT_FOR_BBP(__dev, __reg) \ 58 rt2x00mmio_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg)) 59 #define WAIT_FOR_RF(__dev, __reg) \ 60 rt2x00mmio_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg)) 61 #define WAIT_FOR_MCU(__dev, __reg) \ 62 rt2x00mmio_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 63 H2M_MAILBOX_CSR_OWNER, (__reg)) 64 65 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev, 66 const unsigned int word, const u8 value) 67 { 68 u32 reg; 69 70 mutex_lock(&rt2x00dev->csr_mutex); 71 72 /* 73 * Wait until the BBP becomes available, afterwards we 74 * can safely write the new data into the register. 75 */ 76 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 77 reg = 0; 78 rt2x00_set_field32(®, PHY_CSR3_VALUE, value); 79 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); 80 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); 81 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); 82 83 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); 84 } 85 86 mutex_unlock(&rt2x00dev->csr_mutex); 87 } 88 89 static u8 rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev, 90 const unsigned int word) 91 { 92 u32 reg; 93 u8 value; 94 95 mutex_lock(&rt2x00dev->csr_mutex); 96 97 /* 98 * Wait until the BBP becomes available, afterwards we 99 * can safely write the read request into the register. 100 * After the data has been written, we wait until hardware 101 * returns the correct value, if at any time the register 102 * doesn't become available in time, reg will be 0xffffffff 103 * which means we return 0xff to the caller. 104 */ 105 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 106 reg = 0; 107 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); 108 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); 109 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); 110 111 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); 112 113 WAIT_FOR_BBP(rt2x00dev, ®); 114 } 115 116 value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); 117 118 mutex_unlock(&rt2x00dev->csr_mutex); 119 120 return value; 121 } 122 123 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev, 124 const unsigned int word, const u32 value) 125 { 126 u32 reg; 127 128 mutex_lock(&rt2x00dev->csr_mutex); 129 130 /* 131 * Wait until the RF becomes available, afterwards we 132 * can safely write the new data into the register. 133 */ 134 if (WAIT_FOR_RF(rt2x00dev, ®)) { 135 reg = 0; 136 rt2x00_set_field32(®, PHY_CSR4_VALUE, value); 137 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21); 138 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); 139 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); 140 141 rt2x00mmio_register_write(rt2x00dev, PHY_CSR4, reg); 142 rt2x00_rf_write(rt2x00dev, word, value); 143 } 144 145 mutex_unlock(&rt2x00dev->csr_mutex); 146 } 147 148 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev, 149 const u8 command, const u8 token, 150 const u8 arg0, const u8 arg1) 151 { 152 u32 reg; 153 154 mutex_lock(&rt2x00dev->csr_mutex); 155 156 /* 157 * Wait until the MCU becomes available, afterwards we 158 * can safely write the new data into the register. 159 */ 160 if (WAIT_FOR_MCU(rt2x00dev, ®)) { 161 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); 162 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); 163 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); 164 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); 165 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); 166 167 reg = rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR); 168 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); 169 rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1); 170 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg); 171 } 172 173 mutex_unlock(&rt2x00dev->csr_mutex); 174 175 } 176 177 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom) 178 { 179 struct rt2x00_dev *rt2x00dev = eeprom->data; 180 u32 reg; 181 182 reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR); 183 184 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); 185 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); 186 eeprom->reg_data_clock = 187 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK); 188 eeprom->reg_chip_select = 189 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT); 190 } 191 192 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom) 193 { 194 struct rt2x00_dev *rt2x00dev = eeprom->data; 195 u32 reg = 0; 196 197 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); 198 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); 199 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, 200 !!eeprom->reg_data_clock); 201 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT, 202 !!eeprom->reg_chip_select); 203 204 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg); 205 } 206 207 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 208 static const struct rt2x00debug rt61pci_rt2x00debug = { 209 .owner = THIS_MODULE, 210 .csr = { 211 .read = rt2x00mmio_register_read, 212 .write = rt2x00mmio_register_write, 213 .flags = RT2X00DEBUGFS_OFFSET, 214 .word_base = CSR_REG_BASE, 215 .word_size = sizeof(u32), 216 .word_count = CSR_REG_SIZE / sizeof(u32), 217 }, 218 .eeprom = { 219 .read = rt2x00_eeprom_read, 220 .write = rt2x00_eeprom_write, 221 .word_base = EEPROM_BASE, 222 .word_size = sizeof(u16), 223 .word_count = EEPROM_SIZE / sizeof(u16), 224 }, 225 .bbp = { 226 .read = rt61pci_bbp_read, 227 .write = rt61pci_bbp_write, 228 .word_base = BBP_BASE, 229 .word_size = sizeof(u8), 230 .word_count = BBP_SIZE / sizeof(u8), 231 }, 232 .rf = { 233 .read = rt2x00_rf_read, 234 .write = rt61pci_rf_write, 235 .word_base = RF_BASE, 236 .word_size = sizeof(u32), 237 .word_count = RF_SIZE / sizeof(u32), 238 }, 239 }; 240 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 241 242 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) 243 { 244 u32 reg; 245 246 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); 247 return rt2x00_get_field32(reg, MAC_CSR13_VAL5); 248 } 249 250 #ifdef CONFIG_RT2X00_LIB_LEDS 251 static void rt61pci_brightness_set(struct led_classdev *led_cdev, 252 enum led_brightness brightness) 253 { 254 struct rt2x00_led *led = 255 container_of(led_cdev, struct rt2x00_led, led_dev); 256 unsigned int enabled = brightness != LED_OFF; 257 unsigned int a_mode = 258 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_5GHZ); 259 unsigned int bg_mode = 260 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); 261 262 if (led->type == LED_TYPE_RADIO) { 263 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, 264 MCU_LEDCS_RADIO_STATUS, enabled); 265 266 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, 267 (led->rt2x00dev->led_mcu_reg & 0xff), 268 ((led->rt2x00dev->led_mcu_reg >> 8))); 269 } else if (led->type == LED_TYPE_ASSOC) { 270 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, 271 MCU_LEDCS_LINK_BG_STATUS, bg_mode); 272 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, 273 MCU_LEDCS_LINK_A_STATUS, a_mode); 274 275 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, 276 (led->rt2x00dev->led_mcu_reg & 0xff), 277 ((led->rt2x00dev->led_mcu_reg >> 8))); 278 } else if (led->type == LED_TYPE_QUALITY) { 279 /* 280 * The brightness is divided into 6 levels (0 - 5), 281 * this means we need to convert the brightness 282 * argument into the matching level within that range. 283 */ 284 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 285 brightness / (LED_FULL / 6), 0); 286 } 287 } 288 289 static int rt61pci_blink_set(struct led_classdev *led_cdev, 290 unsigned long *delay_on, 291 unsigned long *delay_off) 292 { 293 struct rt2x00_led *led = 294 container_of(led_cdev, struct rt2x00_led, led_dev); 295 u32 reg; 296 297 reg = rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14); 298 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); 299 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); 300 rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg); 301 302 return 0; 303 } 304 305 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev, 306 struct rt2x00_led *led, 307 enum led_type type) 308 { 309 led->rt2x00dev = rt2x00dev; 310 led->type = type; 311 led->led_dev.brightness_set = rt61pci_brightness_set; 312 led->led_dev.blink_set = rt61pci_blink_set; 313 led->flags = LED_INITIALIZED; 314 } 315 #endif /* CONFIG_RT2X00_LIB_LEDS */ 316 317 /* 318 * Configuration handlers. 319 */ 320 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev, 321 struct rt2x00lib_crypto *crypto, 322 struct ieee80211_key_conf *key) 323 { 324 struct hw_key_entry key_entry; 325 struct rt2x00_field32 field; 326 u32 mask; 327 u32 reg; 328 329 if (crypto->cmd == SET_KEY) { 330 /* 331 * rt2x00lib can't determine the correct free 332 * key_idx for shared keys. We have 1 register 333 * with key valid bits. The goal is simple, read 334 * the register, if that is full we have no slots 335 * left. 336 * Note that each BSS is allowed to have up to 4 337 * shared keys, so put a mask over the allowed 338 * entries. 339 */ 340 mask = (0xf << crypto->bssidx); 341 342 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR0); 343 reg &= mask; 344 345 if (reg && reg == mask) 346 return -ENOSPC; 347 348 key->hw_key_idx += reg ? ffz(reg) : 0; 349 350 /* 351 * Upload key to hardware 352 */ 353 memcpy(key_entry.key, crypto->key, 354 sizeof(key_entry.key)); 355 memcpy(key_entry.tx_mic, crypto->tx_mic, 356 sizeof(key_entry.tx_mic)); 357 memcpy(key_entry.rx_mic, crypto->rx_mic, 358 sizeof(key_entry.rx_mic)); 359 360 reg = SHARED_KEY_ENTRY(key->hw_key_idx); 361 rt2x00mmio_register_multiwrite(rt2x00dev, reg, 362 &key_entry, sizeof(key_entry)); 363 364 /* 365 * The cipher types are stored over 2 registers. 366 * bssidx 0 and 1 keys are stored in SEC_CSR1 and 367 * bssidx 1 and 2 keys are stored in SEC_CSR5. 368 * Using the correct defines correctly will cause overhead, 369 * so just calculate the correct offset. 370 */ 371 if (key->hw_key_idx < 8) { 372 field.bit_offset = (3 * key->hw_key_idx); 373 field.bit_mask = 0x7 << field.bit_offset; 374 375 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR1); 376 rt2x00_set_field32(®, field, crypto->cipher); 377 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, reg); 378 } else { 379 field.bit_offset = (3 * (key->hw_key_idx - 8)); 380 field.bit_mask = 0x7 << field.bit_offset; 381 382 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR5); 383 rt2x00_set_field32(®, field, crypto->cipher); 384 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, reg); 385 } 386 387 /* 388 * The driver does not support the IV/EIV generation 389 * in hardware. However it doesn't support the IV/EIV 390 * inside the ieee80211 frame either, but requires it 391 * to be provided separately for the descriptor. 392 * rt2x00lib will cut the IV/EIV data out of all frames 393 * given to us by mac80211, but we must tell mac80211 394 * to generate the IV/EIV data. 395 */ 396 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 397 } 398 399 /* 400 * SEC_CSR0 contains only single-bit fields to indicate 401 * a particular key is valid. Because using the FIELD32() 402 * defines directly will cause a lot of overhead, we use 403 * a calculation to determine the correct bit directly. 404 */ 405 mask = 1 << key->hw_key_idx; 406 407 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR0); 408 if (crypto->cmd == SET_KEY) 409 reg |= mask; 410 else if (crypto->cmd == DISABLE_KEY) 411 reg &= ~mask; 412 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, reg); 413 414 return 0; 415 } 416 417 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 418 struct rt2x00lib_crypto *crypto, 419 struct ieee80211_key_conf *key) 420 { 421 struct hw_pairwise_ta_entry addr_entry; 422 struct hw_key_entry key_entry; 423 u32 mask; 424 u32 reg; 425 426 if (crypto->cmd == SET_KEY) { 427 /* 428 * rt2x00lib can't determine the correct free 429 * key_idx for pairwise keys. We have 2 registers 430 * with key valid bits. The goal is simple: read 431 * the first register. If that is full, move to 432 * the next register. 433 * When both registers are full, we drop the key. 434 * Otherwise, we use the first invalid entry. 435 */ 436 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR2); 437 if (reg && reg == ~0) { 438 key->hw_key_idx = 32; 439 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR3); 440 if (reg && reg == ~0) 441 return -ENOSPC; 442 } 443 444 key->hw_key_idx += reg ? ffz(reg) : 0; 445 446 /* 447 * Upload key to hardware 448 */ 449 memcpy(key_entry.key, crypto->key, 450 sizeof(key_entry.key)); 451 memcpy(key_entry.tx_mic, crypto->tx_mic, 452 sizeof(key_entry.tx_mic)); 453 memcpy(key_entry.rx_mic, crypto->rx_mic, 454 sizeof(key_entry.rx_mic)); 455 456 memset(&addr_entry, 0, sizeof(addr_entry)); 457 memcpy(&addr_entry, crypto->address, ETH_ALEN); 458 addr_entry.cipher = crypto->cipher; 459 460 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 461 rt2x00mmio_register_multiwrite(rt2x00dev, reg, 462 &key_entry, sizeof(key_entry)); 463 464 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); 465 rt2x00mmio_register_multiwrite(rt2x00dev, reg, 466 &addr_entry, sizeof(addr_entry)); 467 468 /* 469 * Enable pairwise lookup table for given BSS idx. 470 * Without this, received frames will not be decrypted 471 * by the hardware. 472 */ 473 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR4); 474 reg |= (1 << crypto->bssidx); 475 rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg); 476 477 /* 478 * The driver does not support the IV/EIV generation 479 * in hardware. However it doesn't support the IV/EIV 480 * inside the ieee80211 frame either, but requires it 481 * to be provided separately for the descriptor. 482 * rt2x00lib will cut the IV/EIV data out of all frames 483 * given to us by mac80211, but we must tell mac80211 484 * to generate the IV/EIV data. 485 */ 486 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 487 } 488 489 /* 490 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate 491 * a particular key is valid. Because using the FIELD32() 492 * defines directly will cause a lot of overhead, we use 493 * a calculation to determine the correct bit directly. 494 */ 495 if (key->hw_key_idx < 32) { 496 mask = 1 << key->hw_key_idx; 497 498 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR2); 499 if (crypto->cmd == SET_KEY) 500 reg |= mask; 501 else if (crypto->cmd == DISABLE_KEY) 502 reg &= ~mask; 503 rt2x00mmio_register_write(rt2x00dev, SEC_CSR2, reg); 504 } else { 505 mask = 1 << (key->hw_key_idx - 32); 506 507 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR3); 508 if (crypto->cmd == SET_KEY) 509 reg |= mask; 510 else if (crypto->cmd == DISABLE_KEY) 511 reg &= ~mask; 512 rt2x00mmio_register_write(rt2x00dev, SEC_CSR3, reg); 513 } 514 515 return 0; 516 } 517 518 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev, 519 const unsigned int filter_flags) 520 { 521 u32 reg; 522 523 /* 524 * Start configuration steps. 525 * Note that the version error will always be dropped 526 * and broadcast frames will always be accepted since 527 * there is no filter for it at this time. 528 */ 529 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); 530 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, 531 !(filter_flags & FIF_FCSFAIL)); 532 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, 533 !(filter_flags & FIF_PLCPFAIL)); 534 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, 535 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL))); 536 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, 537 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); 538 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, 539 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) && 540 !rt2x00dev->intf_ap_count); 541 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); 542 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, 543 !(filter_flags & FIF_ALLMULTI)); 544 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); 545 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, 546 !(filter_flags & FIF_CONTROL)); 547 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); 548 } 549 550 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev, 551 struct rt2x00_intf *intf, 552 struct rt2x00intf_conf *conf, 553 const unsigned int flags) 554 { 555 u32 reg; 556 557 if (flags & CONFIG_UPDATE_TYPE) { 558 /* 559 * Enable synchronisation. 560 */ 561 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); 562 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); 563 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); 564 } 565 566 if (flags & CONFIG_UPDATE_MAC) { 567 reg = le32_to_cpu(conf->mac[1]); 568 rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); 569 conf->mac[1] = cpu_to_le32(reg); 570 571 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR2, 572 conf->mac, sizeof(conf->mac)); 573 } 574 575 if (flags & CONFIG_UPDATE_BSSID) { 576 reg = le32_to_cpu(conf->bssid[1]); 577 rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3); 578 conf->bssid[1] = cpu_to_le32(reg); 579 580 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR4, 581 conf->bssid, 582 sizeof(conf->bssid)); 583 } 584 } 585 586 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev, 587 struct rt2x00lib_erp *erp, 588 u32 changed) 589 { 590 u32 reg; 591 592 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); 593 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); 594 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); 595 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); 596 597 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 598 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4); 599 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); 600 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, 601 !!erp->short_preamble); 602 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); 603 } 604 605 if (changed & BSS_CHANGED_BASIC_RATES) 606 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR5, 607 erp->basic_rates); 608 609 if (changed & BSS_CHANGED_BEACON_INT) { 610 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); 611 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 612 erp->beacon_int * 16); 613 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); 614 } 615 616 if (changed & BSS_CHANGED_ERP_SLOT) { 617 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR9); 618 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time); 619 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); 620 621 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR8); 622 rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs); 623 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); 624 rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs); 625 rt2x00mmio_register_write(rt2x00dev, MAC_CSR8, reg); 626 } 627 } 628 629 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev, 630 struct antenna_setup *ant) 631 { 632 u8 r3; 633 u8 r4; 634 u8 r77; 635 636 r3 = rt61pci_bbp_read(rt2x00dev, 3); 637 r4 = rt61pci_bbp_read(rt2x00dev, 4); 638 r77 = rt61pci_bbp_read(rt2x00dev, 77); 639 640 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325)); 641 642 /* 643 * Configure the RX antenna. 644 */ 645 switch (ant->rx) { 646 case ANTENNA_HW_DIVERSITY: 647 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); 648 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 649 (rt2x00dev->curr_band != NL80211_BAND_5GHZ)); 650 break; 651 case ANTENNA_A: 652 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 653 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); 654 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) 655 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); 656 else 657 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); 658 break; 659 case ANTENNA_B: 660 default: 661 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 662 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); 663 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) 664 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); 665 else 666 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); 667 break; 668 } 669 670 rt61pci_bbp_write(rt2x00dev, 77, r77); 671 rt61pci_bbp_write(rt2x00dev, 3, r3); 672 rt61pci_bbp_write(rt2x00dev, 4, r4); 673 } 674 675 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev, 676 struct antenna_setup *ant) 677 { 678 u8 r3; 679 u8 r4; 680 u8 r77; 681 682 r3 = rt61pci_bbp_read(rt2x00dev, 3); 683 r4 = rt61pci_bbp_read(rt2x00dev, 4); 684 r77 = rt61pci_bbp_read(rt2x00dev, 77); 685 686 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529)); 687 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 688 !rt2x00_has_cap_frame_type(rt2x00dev)); 689 690 /* 691 * Configure the RX antenna. 692 */ 693 switch (ant->rx) { 694 case ANTENNA_HW_DIVERSITY: 695 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); 696 break; 697 case ANTENNA_A: 698 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 699 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); 700 break; 701 case ANTENNA_B: 702 default: 703 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 704 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); 705 break; 706 } 707 708 rt61pci_bbp_write(rt2x00dev, 77, r77); 709 rt61pci_bbp_write(rt2x00dev, 3, r3); 710 rt61pci_bbp_write(rt2x00dev, 4, r4); 711 } 712 713 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev, 714 const int p1, const int p2) 715 { 716 u32 reg; 717 718 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); 719 720 rt2x00_set_field32(®, MAC_CSR13_DIR4, 0); 721 rt2x00_set_field32(®, MAC_CSR13_VAL4, p1); 722 723 rt2x00_set_field32(®, MAC_CSR13_DIR3, 0); 724 rt2x00_set_field32(®, MAC_CSR13_VAL3, !p2); 725 726 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); 727 } 728 729 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev, 730 struct antenna_setup *ant) 731 { 732 u8 r3; 733 u8 r4; 734 u8 r77; 735 736 r3 = rt61pci_bbp_read(rt2x00dev, 3); 737 r4 = rt61pci_bbp_read(rt2x00dev, 4); 738 r77 = rt61pci_bbp_read(rt2x00dev, 77); 739 740 /* 741 * Configure the RX antenna. 742 */ 743 switch (ant->rx) { 744 case ANTENNA_A: 745 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 746 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); 747 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0); 748 break; 749 case ANTENNA_HW_DIVERSITY: 750 /* 751 * FIXME: Antenna selection for the rf 2529 is very confusing 752 * in the legacy driver. Just default to antenna B until the 753 * legacy code can be properly translated into rt2x00 code. 754 */ 755 case ANTENNA_B: 756 default: 757 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 758 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); 759 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1); 760 break; 761 } 762 763 rt61pci_bbp_write(rt2x00dev, 77, r77); 764 rt61pci_bbp_write(rt2x00dev, 3, r3); 765 rt61pci_bbp_write(rt2x00dev, 4, r4); 766 } 767 768 struct antenna_sel { 769 u8 word; 770 /* 771 * value[0] -> non-LNA 772 * value[1] -> LNA 773 */ 774 u8 value[2]; 775 }; 776 777 static const struct antenna_sel antenna_sel_a[] = { 778 { 96, { 0x58, 0x78 } }, 779 { 104, { 0x38, 0x48 } }, 780 { 75, { 0xfe, 0x80 } }, 781 { 86, { 0xfe, 0x80 } }, 782 { 88, { 0xfe, 0x80 } }, 783 { 35, { 0x60, 0x60 } }, 784 { 97, { 0x58, 0x58 } }, 785 { 98, { 0x58, 0x58 } }, 786 }; 787 788 static const struct antenna_sel antenna_sel_bg[] = { 789 { 96, { 0x48, 0x68 } }, 790 { 104, { 0x2c, 0x3c } }, 791 { 75, { 0xfe, 0x80 } }, 792 { 86, { 0xfe, 0x80 } }, 793 { 88, { 0xfe, 0x80 } }, 794 { 35, { 0x50, 0x50 } }, 795 { 97, { 0x48, 0x48 } }, 796 { 98, { 0x48, 0x48 } }, 797 }; 798 799 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev, 800 struct antenna_setup *ant) 801 { 802 const struct antenna_sel *sel; 803 unsigned int lna; 804 unsigned int i; 805 u32 reg; 806 807 /* 808 * We should never come here because rt2x00lib is supposed 809 * to catch this and send us the correct antenna explicitely. 810 */ 811 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || 812 ant->tx == ANTENNA_SW_DIVERSITY); 813 814 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { 815 sel = antenna_sel_a; 816 lna = rt2x00_has_cap_external_lna_a(rt2x00dev); 817 } else { 818 sel = antenna_sel_bg; 819 lna = rt2x00_has_cap_external_lna_bg(rt2x00dev); 820 } 821 822 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) 823 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); 824 825 reg = rt2x00mmio_register_read(rt2x00dev, PHY_CSR0); 826 827 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, 828 rt2x00dev->curr_band == NL80211_BAND_2GHZ); 829 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, 830 rt2x00dev->curr_band == NL80211_BAND_5GHZ); 831 832 rt2x00mmio_register_write(rt2x00dev, PHY_CSR0, reg); 833 834 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) 835 rt61pci_config_antenna_5x(rt2x00dev, ant); 836 else if (rt2x00_rf(rt2x00dev, RF2527)) 837 rt61pci_config_antenna_2x(rt2x00dev, ant); 838 else if (rt2x00_rf(rt2x00dev, RF2529)) { 839 if (rt2x00_has_cap_double_antenna(rt2x00dev)) 840 rt61pci_config_antenna_2x(rt2x00dev, ant); 841 else 842 rt61pci_config_antenna_2529(rt2x00dev, ant); 843 } 844 } 845 846 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev, 847 struct rt2x00lib_conf *libconf) 848 { 849 u16 eeprom; 850 short lna_gain = 0; 851 852 if (libconf->conf->chandef.chan->band == NL80211_BAND_2GHZ) { 853 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 854 lna_gain += 14; 855 856 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG); 857 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1); 858 } else { 859 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) 860 lna_gain += 14; 861 862 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A); 863 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1); 864 } 865 866 rt2x00dev->lna_gain = lna_gain; 867 } 868 869 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev, 870 struct rf_channel *rf, const int txpower) 871 { 872 u8 r3; 873 u8 r94; 874 u8 smart; 875 876 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); 877 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 878 879 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527)); 880 881 r3 = rt61pci_bbp_read(rt2x00dev, 3); 882 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart); 883 rt61pci_bbp_write(rt2x00dev, 3, r3); 884 885 r94 = 6; 886 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94)) 887 r94 += txpower - MAX_TXPOWER; 888 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94)) 889 r94 += txpower; 890 rt61pci_bbp_write(rt2x00dev, 94, r94); 891 892 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); 893 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); 894 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 895 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); 896 897 udelay(200); 898 899 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); 900 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); 901 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 902 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); 903 904 udelay(200); 905 906 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); 907 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); 908 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 909 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); 910 911 msleep(1); 912 } 913 914 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev, 915 const int txpower) 916 { 917 struct rf_channel rf; 918 919 rf.rf1 = rt2x00_rf_read(rt2x00dev, 1); 920 rf.rf2 = rt2x00_rf_read(rt2x00dev, 2); 921 rf.rf3 = rt2x00_rf_read(rt2x00dev, 3); 922 rf.rf4 = rt2x00_rf_read(rt2x00dev, 4); 923 924 rt61pci_config_channel(rt2x00dev, &rf, txpower); 925 } 926 927 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, 928 struct rt2x00lib_conf *libconf) 929 { 930 u32 reg; 931 932 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4); 933 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); 934 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); 935 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); 936 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, 937 libconf->conf->long_frame_max_tx_count); 938 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, 939 libconf->conf->short_frame_max_tx_count); 940 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); 941 } 942 943 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev, 944 struct rt2x00lib_conf *libconf) 945 { 946 enum dev_state state = 947 (libconf->conf->flags & IEEE80211_CONF_PS) ? 948 STATE_SLEEP : STATE_AWAKE; 949 u32 reg; 950 951 if (state == STATE_SLEEP) { 952 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR11); 953 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 954 rt2x00dev->beacon_int - 10); 955 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 956 libconf->conf->listen_interval - 1); 957 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5); 958 959 /* We must first disable autowake before it can be enabled */ 960 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); 961 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); 962 963 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1); 964 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); 965 966 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, 967 0x00000005); 968 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c); 969 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060); 970 971 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0); 972 } else { 973 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR11); 974 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0); 975 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); 976 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); 977 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0); 978 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); 979 980 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, 981 0x00000007); 982 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018); 983 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020); 984 985 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0); 986 } 987 } 988 989 static void rt61pci_config(struct rt2x00_dev *rt2x00dev, 990 struct rt2x00lib_conf *libconf, 991 const unsigned int flags) 992 { 993 /* Always recalculate LNA gain before changing configuration */ 994 rt61pci_config_lna_gain(rt2x00dev, libconf); 995 996 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) 997 rt61pci_config_channel(rt2x00dev, &libconf->rf, 998 libconf->conf->power_level); 999 if ((flags & IEEE80211_CONF_CHANGE_POWER) && 1000 !(flags & IEEE80211_CONF_CHANGE_CHANNEL)) 1001 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level); 1002 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 1003 rt61pci_config_retry_limit(rt2x00dev, libconf); 1004 if (flags & IEEE80211_CONF_CHANGE_PS) 1005 rt61pci_config_ps(rt2x00dev, libconf); 1006 } 1007 1008 /* 1009 * Link tuning 1010 */ 1011 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev, 1012 struct link_qual *qual) 1013 { 1014 u32 reg; 1015 1016 /* 1017 * Update FCS error count from register. 1018 */ 1019 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR0); 1020 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); 1021 1022 /* 1023 * Update False CCA count from register. 1024 */ 1025 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR1); 1026 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); 1027 } 1028 1029 static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev, 1030 struct link_qual *qual, u8 vgc_level) 1031 { 1032 if (qual->vgc_level != vgc_level) { 1033 rt61pci_bbp_write(rt2x00dev, 17, vgc_level); 1034 qual->vgc_level = vgc_level; 1035 qual->vgc_level_reg = vgc_level; 1036 } 1037 } 1038 1039 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev, 1040 struct link_qual *qual) 1041 { 1042 rt61pci_set_vgc(rt2x00dev, qual, 0x20); 1043 } 1044 1045 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev, 1046 struct link_qual *qual, const u32 count) 1047 { 1048 u8 up_bound; 1049 u8 low_bound; 1050 1051 /* 1052 * Determine r17 bounds. 1053 */ 1054 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { 1055 low_bound = 0x28; 1056 up_bound = 0x48; 1057 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) { 1058 low_bound += 0x10; 1059 up_bound += 0x10; 1060 } 1061 } else { 1062 low_bound = 0x20; 1063 up_bound = 0x40; 1064 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 1065 low_bound += 0x10; 1066 up_bound += 0x10; 1067 } 1068 } 1069 1070 /* 1071 * If we are not associated, we should go straight to the 1072 * dynamic CCA tuning. 1073 */ 1074 if (!rt2x00dev->intf_associated) 1075 goto dynamic_cca_tune; 1076 1077 /* 1078 * Special big-R17 for very short distance 1079 */ 1080 if (qual->rssi >= -35) { 1081 rt61pci_set_vgc(rt2x00dev, qual, 0x60); 1082 return; 1083 } 1084 1085 /* 1086 * Special big-R17 for short distance 1087 */ 1088 if (qual->rssi >= -58) { 1089 rt61pci_set_vgc(rt2x00dev, qual, up_bound); 1090 return; 1091 } 1092 1093 /* 1094 * Special big-R17 for middle-short distance 1095 */ 1096 if (qual->rssi >= -66) { 1097 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10); 1098 return; 1099 } 1100 1101 /* 1102 * Special mid-R17 for middle distance 1103 */ 1104 if (qual->rssi >= -74) { 1105 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08); 1106 return; 1107 } 1108 1109 /* 1110 * Special case: Change up_bound based on the rssi. 1111 * Lower up_bound when rssi is weaker then -74 dBm. 1112 */ 1113 up_bound -= 2 * (-74 - qual->rssi); 1114 if (low_bound > up_bound) 1115 up_bound = low_bound; 1116 1117 if (qual->vgc_level > up_bound) { 1118 rt61pci_set_vgc(rt2x00dev, qual, up_bound); 1119 return; 1120 } 1121 1122 dynamic_cca_tune: 1123 1124 /* 1125 * r17 does not yet exceed upper limit, continue and base 1126 * the r17 tuning on the false CCA count. 1127 */ 1128 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound)) 1129 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level); 1130 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound)) 1131 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level); 1132 } 1133 1134 /* 1135 * Queue handlers. 1136 */ 1137 static void rt61pci_start_queue(struct data_queue *queue) 1138 { 1139 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; 1140 u32 reg; 1141 1142 switch (queue->qid) { 1143 case QID_RX: 1144 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); 1145 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); 1146 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); 1147 break; 1148 case QID_BEACON: 1149 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); 1150 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); 1151 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); 1152 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); 1153 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); 1154 break; 1155 default: 1156 break; 1157 } 1158 } 1159 1160 static void rt61pci_kick_queue(struct data_queue *queue) 1161 { 1162 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; 1163 u32 reg; 1164 1165 switch (queue->qid) { 1166 case QID_AC_VO: 1167 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); 1168 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, 1); 1169 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1170 break; 1171 case QID_AC_VI: 1172 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); 1173 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, 1); 1174 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1175 break; 1176 case QID_AC_BE: 1177 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); 1178 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, 1); 1179 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1180 break; 1181 case QID_AC_BK: 1182 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); 1183 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, 1); 1184 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1185 break; 1186 default: 1187 break; 1188 } 1189 } 1190 1191 static void rt61pci_stop_queue(struct data_queue *queue) 1192 { 1193 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; 1194 u32 reg; 1195 1196 switch (queue->qid) { 1197 case QID_AC_VO: 1198 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); 1199 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1); 1200 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1201 break; 1202 case QID_AC_VI: 1203 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); 1204 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1); 1205 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1206 break; 1207 case QID_AC_BE: 1208 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); 1209 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1); 1210 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1211 break; 1212 case QID_AC_BK: 1213 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); 1214 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1); 1215 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1216 break; 1217 case QID_RX: 1218 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); 1219 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 1); 1220 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); 1221 break; 1222 case QID_BEACON: 1223 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); 1224 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); 1225 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); 1226 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); 1227 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); 1228 1229 /* 1230 * Wait for possibly running tbtt tasklets. 1231 */ 1232 tasklet_kill(&rt2x00dev->tbtt_tasklet); 1233 break; 1234 default: 1235 break; 1236 } 1237 } 1238 1239 /* 1240 * Firmware functions 1241 */ 1242 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) 1243 { 1244 u16 chip; 1245 char *fw_name; 1246 1247 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip); 1248 switch (chip) { 1249 case RT2561_PCI_ID: 1250 fw_name = FIRMWARE_RT2561; 1251 break; 1252 case RT2561s_PCI_ID: 1253 fw_name = FIRMWARE_RT2561s; 1254 break; 1255 case RT2661_PCI_ID: 1256 fw_name = FIRMWARE_RT2661; 1257 break; 1258 default: 1259 fw_name = NULL; 1260 break; 1261 } 1262 1263 return fw_name; 1264 } 1265 1266 static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev, 1267 const u8 *data, const size_t len) 1268 { 1269 u16 fw_crc; 1270 u16 crc; 1271 1272 /* 1273 * Only support 8kb firmware files. 1274 */ 1275 if (len != 8192) 1276 return FW_BAD_LENGTH; 1277 1278 /* 1279 * The last 2 bytes in the firmware array are the crc checksum itself. 1280 * This means that we should never pass those 2 bytes to the crc 1281 * algorithm. 1282 */ 1283 fw_crc = (data[len - 2] << 8 | data[len - 1]); 1284 1285 /* 1286 * Use the crc itu-t algorithm. 1287 */ 1288 crc = crc_itu_t(0, data, len - 2); 1289 crc = crc_itu_t_byte(crc, 0); 1290 crc = crc_itu_t_byte(crc, 0); 1291 1292 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC; 1293 } 1294 1295 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, 1296 const u8 *data, const size_t len) 1297 { 1298 int i; 1299 u32 reg; 1300 1301 /* 1302 * Wait for stable hardware. 1303 */ 1304 for (i = 0; i < 100; i++) { 1305 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR0); 1306 if (reg) 1307 break; 1308 msleep(1); 1309 } 1310 1311 if (!reg) { 1312 rt2x00_err(rt2x00dev, "Unstable hardware\n"); 1313 return -EBUSY; 1314 } 1315 1316 /* 1317 * Prepare MCU and mailbox for firmware loading. 1318 */ 1319 reg = 0; 1320 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); 1321 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); 1322 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); 1323 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 1324 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, 0); 1325 1326 /* 1327 * Write firmware to device. 1328 */ 1329 reg = 0; 1330 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); 1331 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1); 1332 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); 1333 1334 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, 1335 data, len); 1336 1337 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0); 1338 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); 1339 1340 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0); 1341 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); 1342 1343 for (i = 0; i < 100; i++) { 1344 reg = rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR); 1345 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY)) 1346 break; 1347 msleep(1); 1348 } 1349 1350 if (i == 100) { 1351 rt2x00_err(rt2x00dev, "MCU Control register not ready\n"); 1352 return -EBUSY; 1353 } 1354 1355 /* 1356 * Hardware needs another millisecond before it is ready. 1357 */ 1358 msleep(1); 1359 1360 /* 1361 * Reset MAC and BBP registers. 1362 */ 1363 reg = 0; 1364 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); 1365 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); 1366 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); 1367 1368 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); 1369 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); 1370 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); 1371 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); 1372 1373 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); 1374 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); 1375 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); 1376 1377 return 0; 1378 } 1379 1380 /* 1381 * Initialization functions. 1382 */ 1383 static bool rt61pci_get_entry_state(struct queue_entry *entry) 1384 { 1385 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; 1386 u32 word; 1387 1388 if (entry->queue->qid == QID_RX) { 1389 word = rt2x00_desc_read(entry_priv->desc, 0); 1390 1391 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC); 1392 } else { 1393 word = rt2x00_desc_read(entry_priv->desc, 0); 1394 1395 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 1396 rt2x00_get_field32(word, TXD_W0_VALID)); 1397 } 1398 } 1399 1400 static void rt61pci_clear_entry(struct queue_entry *entry) 1401 { 1402 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; 1403 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1404 u32 word; 1405 1406 if (entry->queue->qid == QID_RX) { 1407 word = rt2x00_desc_read(entry_priv->desc, 5); 1408 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, 1409 skbdesc->skb_dma); 1410 rt2x00_desc_write(entry_priv->desc, 5, word); 1411 1412 word = rt2x00_desc_read(entry_priv->desc, 0); 1413 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); 1414 rt2x00_desc_write(entry_priv->desc, 0, word); 1415 } else { 1416 word = rt2x00_desc_read(entry_priv->desc, 0); 1417 rt2x00_set_field32(&word, TXD_W0_VALID, 0); 1418 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); 1419 rt2x00_desc_write(entry_priv->desc, 0, word); 1420 } 1421 } 1422 1423 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev) 1424 { 1425 struct queue_entry_priv_mmio *entry_priv; 1426 u32 reg; 1427 1428 /* 1429 * Initialize registers. 1430 */ 1431 reg = rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0); 1432 rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE, 1433 rt2x00dev->tx[0].limit); 1434 rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE, 1435 rt2x00dev->tx[1].limit); 1436 rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE, 1437 rt2x00dev->tx[2].limit); 1438 rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE, 1439 rt2x00dev->tx[3].limit); 1440 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg); 1441 1442 reg = rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1); 1443 rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE, 1444 rt2x00dev->tx[0].desc_size / 4); 1445 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg); 1446 1447 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; 1448 reg = rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR); 1449 rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER, 1450 entry_priv->desc_dma); 1451 rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg); 1452 1453 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; 1454 reg = rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR); 1455 rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER, 1456 entry_priv->desc_dma); 1457 rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg); 1458 1459 entry_priv = rt2x00dev->tx[2].entries[0].priv_data; 1460 reg = rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR); 1461 rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER, 1462 entry_priv->desc_dma); 1463 rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg); 1464 1465 entry_priv = rt2x00dev->tx[3].entries[0].priv_data; 1466 reg = rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR); 1467 rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER, 1468 entry_priv->desc_dma); 1469 rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg); 1470 1471 reg = rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR); 1472 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); 1473 rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE, 1474 rt2x00dev->rx->desc_size / 4); 1475 rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4); 1476 rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg); 1477 1478 entry_priv = rt2x00dev->rx->entries[0].priv_data; 1479 reg = rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR); 1480 rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER, 1481 entry_priv->desc_dma); 1482 rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg); 1483 1484 reg = rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR); 1485 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2); 1486 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2); 1487 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2); 1488 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2); 1489 rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); 1490 1491 reg = rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR); 1492 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1); 1493 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1); 1494 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1); 1495 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1); 1496 rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); 1497 1498 reg = rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR); 1499 rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1); 1500 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); 1501 1502 return 0; 1503 } 1504 1505 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev) 1506 { 1507 u32 reg; 1508 1509 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); 1510 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); 1511 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); 1512 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); 1513 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); 1514 1515 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1); 1516 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ 1517 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); 1518 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ 1519 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); 1520 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ 1521 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); 1522 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ 1523 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); 1524 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR1, reg); 1525 1526 /* 1527 * CCK TXD BBP registers 1528 */ 1529 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2); 1530 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); 1531 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); 1532 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); 1533 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); 1534 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); 1535 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); 1536 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); 1537 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); 1538 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR2, reg); 1539 1540 /* 1541 * OFDM TXD BBP registers 1542 */ 1543 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3); 1544 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); 1545 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); 1546 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); 1547 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); 1548 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); 1549 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); 1550 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg); 1551 1552 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7); 1553 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); 1554 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); 1555 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); 1556 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); 1557 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg); 1558 1559 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8); 1560 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); 1561 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); 1562 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); 1563 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); 1564 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg); 1565 1566 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); 1567 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0); 1568 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); 1569 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); 1570 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); 1571 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); 1572 rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); 1573 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); 1574 1575 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); 1576 1577 rt2x00mmio_register_write(rt2x00dev, MAC_CSR6, 0x00000fff); 1578 1579 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR9); 1580 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); 1581 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); 1582 1583 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x0000071c); 1584 1585 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) 1586 return -EBUSY; 1587 1588 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, 0x0000e000); 1589 1590 /* 1591 * Invalidate all Shared Keys (SEC_CSR0), 1592 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) 1593 */ 1594 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, 0x00000000); 1595 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, 0x00000000); 1596 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, 0x00000000); 1597 1598 rt2x00mmio_register_write(rt2x00dev, PHY_CSR1, 0x000023b0); 1599 rt2x00mmio_register_write(rt2x00dev, PHY_CSR5, 0x060a100c); 1600 rt2x00mmio_register_write(rt2x00dev, PHY_CSR6, 0x00080606); 1601 rt2x00mmio_register_write(rt2x00dev, PHY_CSR7, 0x00000a08); 1602 1603 rt2x00mmio_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404); 1604 1605 rt2x00mmio_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200); 1606 1607 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); 1608 1609 /* 1610 * Clear all beacons 1611 * For the Beacon base registers we only need to clear 1612 * the first byte since that byte contains the VALID and OWNER 1613 * bits which (when set to 0) will invalidate the entire beacon. 1614 */ 1615 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE0, 0); 1616 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE1, 0); 1617 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE2, 0); 1618 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE3, 0); 1619 1620 /* 1621 * We must clear the error counters. 1622 * These registers are cleared on read, 1623 * so we may pass a useless variable to store the value. 1624 */ 1625 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR0); 1626 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR1); 1627 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR2); 1628 1629 /* 1630 * Reset MAC and BBP registers. 1631 */ 1632 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); 1633 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); 1634 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); 1635 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); 1636 1637 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); 1638 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); 1639 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); 1640 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); 1641 1642 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); 1643 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); 1644 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); 1645 1646 return 0; 1647 } 1648 1649 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 1650 { 1651 unsigned int i; 1652 u8 value; 1653 1654 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1655 value = rt61pci_bbp_read(rt2x00dev, 0); 1656 if ((value != 0xff) && (value != 0x00)) 1657 return 0; 1658 udelay(REGISTER_BUSY_DELAY); 1659 } 1660 1661 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 1662 return -EACCES; 1663 } 1664 1665 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev) 1666 { 1667 unsigned int i; 1668 u16 eeprom; 1669 u8 reg_id; 1670 u8 value; 1671 1672 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev))) 1673 return -EACCES; 1674 1675 rt61pci_bbp_write(rt2x00dev, 3, 0x00); 1676 rt61pci_bbp_write(rt2x00dev, 15, 0x30); 1677 rt61pci_bbp_write(rt2x00dev, 21, 0xc8); 1678 rt61pci_bbp_write(rt2x00dev, 22, 0x38); 1679 rt61pci_bbp_write(rt2x00dev, 23, 0x06); 1680 rt61pci_bbp_write(rt2x00dev, 24, 0xfe); 1681 rt61pci_bbp_write(rt2x00dev, 25, 0x0a); 1682 rt61pci_bbp_write(rt2x00dev, 26, 0x0d); 1683 rt61pci_bbp_write(rt2x00dev, 34, 0x12); 1684 rt61pci_bbp_write(rt2x00dev, 37, 0x07); 1685 rt61pci_bbp_write(rt2x00dev, 39, 0xf8); 1686 rt61pci_bbp_write(rt2x00dev, 41, 0x60); 1687 rt61pci_bbp_write(rt2x00dev, 53, 0x10); 1688 rt61pci_bbp_write(rt2x00dev, 54, 0x18); 1689 rt61pci_bbp_write(rt2x00dev, 60, 0x10); 1690 rt61pci_bbp_write(rt2x00dev, 61, 0x04); 1691 rt61pci_bbp_write(rt2x00dev, 62, 0x04); 1692 rt61pci_bbp_write(rt2x00dev, 75, 0xfe); 1693 rt61pci_bbp_write(rt2x00dev, 86, 0xfe); 1694 rt61pci_bbp_write(rt2x00dev, 88, 0xfe); 1695 rt61pci_bbp_write(rt2x00dev, 90, 0x0f); 1696 rt61pci_bbp_write(rt2x00dev, 99, 0x00); 1697 rt61pci_bbp_write(rt2x00dev, 102, 0x16); 1698 rt61pci_bbp_write(rt2x00dev, 107, 0x04); 1699 1700 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 1701 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i); 1702 1703 if (eeprom != 0xffff && eeprom != 0x0000) { 1704 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 1705 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 1706 rt61pci_bbp_write(rt2x00dev, reg_id, value); 1707 } 1708 } 1709 1710 return 0; 1711 } 1712 1713 /* 1714 * Device state switch handlers. 1715 */ 1716 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 1717 enum dev_state state) 1718 { 1719 int mask = (state == STATE_RADIO_IRQ_OFF); 1720 u32 reg; 1721 unsigned long flags; 1722 1723 /* 1724 * When interrupts are being enabled, the interrupt registers 1725 * should clear the register to assure a clean state. 1726 */ 1727 if (state == STATE_RADIO_IRQ_ON) { 1728 reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR); 1729 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 1730 1731 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR); 1732 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); 1733 } 1734 1735 /* 1736 * Only toggle the interrupts bits we are going to use. 1737 * Non-checked interrupt bits are disabled by default. 1738 */ 1739 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); 1740 1741 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); 1742 rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask); 1743 rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask); 1744 rt2x00_set_field32(®, INT_MASK_CSR_BEACON_DONE, mask); 1745 rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask); 1746 rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff); 1747 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); 1748 1749 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); 1750 rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask); 1751 rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask); 1752 rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask); 1753 rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask); 1754 rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask); 1755 rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask); 1756 rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask); 1757 rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask); 1758 rt2x00_set_field32(®, MCU_INT_MASK_CSR_TWAKEUP, mask); 1759 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); 1760 1761 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); 1762 1763 if (state == STATE_RADIO_IRQ_OFF) { 1764 /* 1765 * Ensure that all tasklets are finished. 1766 */ 1767 tasklet_kill(&rt2x00dev->txstatus_tasklet); 1768 tasklet_kill(&rt2x00dev->rxdone_tasklet); 1769 tasklet_kill(&rt2x00dev->autowake_tasklet); 1770 tasklet_kill(&rt2x00dev->tbtt_tasklet); 1771 } 1772 } 1773 1774 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev) 1775 { 1776 u32 reg; 1777 1778 /* 1779 * Initialize all registers. 1780 */ 1781 if (unlikely(rt61pci_init_queues(rt2x00dev) || 1782 rt61pci_init_registers(rt2x00dev) || 1783 rt61pci_init_bbp(rt2x00dev))) 1784 return -EIO; 1785 1786 /* 1787 * Enable RX. 1788 */ 1789 reg = rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR); 1790 rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1); 1791 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); 1792 1793 return 0; 1794 } 1795 1796 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev) 1797 { 1798 /* 1799 * Disable power 1800 */ 1801 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x00001818); 1802 } 1803 1804 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) 1805 { 1806 u32 reg, reg2; 1807 unsigned int i; 1808 char put_to_sleep; 1809 1810 put_to_sleep = (state != STATE_AWAKE); 1811 1812 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR12); 1813 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); 1814 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); 1815 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); 1816 1817 /* 1818 * Device is not guaranteed to be in the requested state yet. 1819 * We must wait until the register indicates that the 1820 * device has entered the correct state. 1821 */ 1822 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1823 reg2 = rt2x00mmio_register_read(rt2x00dev, MAC_CSR12); 1824 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE); 1825 if (state == !put_to_sleep) 1826 return 0; 1827 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); 1828 msleep(10); 1829 } 1830 1831 return -EBUSY; 1832 } 1833 1834 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev, 1835 enum dev_state state) 1836 { 1837 int retval = 0; 1838 1839 switch (state) { 1840 case STATE_RADIO_ON: 1841 retval = rt61pci_enable_radio(rt2x00dev); 1842 break; 1843 case STATE_RADIO_OFF: 1844 rt61pci_disable_radio(rt2x00dev); 1845 break; 1846 case STATE_RADIO_IRQ_ON: 1847 case STATE_RADIO_IRQ_OFF: 1848 rt61pci_toggle_irq(rt2x00dev, state); 1849 break; 1850 case STATE_DEEP_SLEEP: 1851 case STATE_SLEEP: 1852 case STATE_STANDBY: 1853 case STATE_AWAKE: 1854 retval = rt61pci_set_state(rt2x00dev, state); 1855 break; 1856 default: 1857 retval = -ENOTSUPP; 1858 break; 1859 } 1860 1861 if (unlikely(retval)) 1862 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n", 1863 state, retval); 1864 1865 return retval; 1866 } 1867 1868 /* 1869 * TX descriptor initialization 1870 */ 1871 static void rt61pci_write_tx_desc(struct queue_entry *entry, 1872 struct txentry_desc *txdesc) 1873 { 1874 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1875 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; 1876 __le32 *txd = entry_priv->desc; 1877 u32 word; 1878 1879 /* 1880 * Start writing the descriptor words. 1881 */ 1882 word = rt2x00_desc_read(txd, 1); 1883 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid); 1884 rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs); 1885 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min); 1886 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max); 1887 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); 1888 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1889 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 1890 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1); 1891 rt2x00_desc_write(txd, 1, word); 1892 1893 word = rt2x00_desc_read(txd, 2); 1894 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal); 1895 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service); 1896 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, 1897 txdesc->u.plcp.length_low); 1898 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, 1899 txdesc->u.plcp.length_high); 1900 rt2x00_desc_write(txd, 2, word); 1901 1902 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { 1903 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]); 1904 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]); 1905 } 1906 1907 word = rt2x00_desc_read(txd, 5); 1908 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid); 1909 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx); 1910 rt2x00_set_field32(&word, TXD_W5_TX_POWER, 1911 TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power)); 1912 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); 1913 rt2x00_desc_write(txd, 5, word); 1914 1915 if (entry->queue->qid != QID_BEACON) { 1916 word = rt2x00_desc_read(txd, 6); 1917 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, 1918 skbdesc->skb_dma); 1919 rt2x00_desc_write(txd, 6, word); 1920 1921 word = rt2x00_desc_read(txd, 11); 1922 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, 1923 txdesc->length); 1924 rt2x00_desc_write(txd, 11, word); 1925 } 1926 1927 /* 1928 * Writing TXD word 0 must the last to prevent a race condition with 1929 * the device, whereby the device may take hold of the TXD before we 1930 * finished updating it. 1931 */ 1932 word = rt2x00_desc_read(txd, 0); 1933 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); 1934 rt2x00_set_field32(&word, TXD_W0_VALID, 1); 1935 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, 1936 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 1937 rt2x00_set_field32(&word, TXD_W0_ACK, 1938 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 1939 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, 1940 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 1941 rt2x00_set_field32(&word, TXD_W0_OFDM, 1942 (txdesc->rate_mode == RATE_MODE_OFDM)); 1943 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs); 1944 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1945 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1946 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 1947 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags)); 1948 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE, 1949 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags)); 1950 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx); 1951 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); 1952 rt2x00_set_field32(&word, TXD_W0_BURST, 1953 test_bit(ENTRY_TXD_BURST, &txdesc->flags)); 1954 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher); 1955 rt2x00_desc_write(txd, 0, word); 1956 1957 /* 1958 * Register descriptor details in skb frame descriptor. 1959 */ 1960 skbdesc->desc = txd; 1961 skbdesc->desc_len = (entry->queue->qid == QID_BEACON) ? TXINFO_SIZE : 1962 TXD_DESC_SIZE; 1963 } 1964 1965 /* 1966 * TX data initialization 1967 */ 1968 static void rt61pci_write_beacon(struct queue_entry *entry, 1969 struct txentry_desc *txdesc) 1970 { 1971 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1972 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; 1973 unsigned int beacon_base; 1974 unsigned int padding_len; 1975 u32 orig_reg, reg; 1976 1977 /* 1978 * Disable beaconing while we are reloading the beacon data, 1979 * otherwise we might be sending out invalid data. 1980 */ 1981 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); 1982 orig_reg = reg; 1983 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); 1984 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); 1985 1986 /* 1987 * Write the TX descriptor for the beacon. 1988 */ 1989 rt61pci_write_tx_desc(entry, txdesc); 1990 1991 /* 1992 * Dump beacon to userspace through debugfs. 1993 */ 1994 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); 1995 1996 /* 1997 * Write entire beacon with descriptor and padding to register. 1998 */ 1999 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 2000 if (padding_len && skb_pad(entry->skb, padding_len)) { 2001 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); 2002 /* skb freed by skb_pad() on failure */ 2003 entry->skb = NULL; 2004 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg); 2005 return; 2006 } 2007 2008 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 2009 rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base, 2010 entry_priv->desc, TXINFO_SIZE); 2011 rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE, 2012 entry->skb->data, 2013 entry->skb->len + padding_len); 2014 2015 /* 2016 * Enable beaconing again. 2017 * 2018 * For Wi-Fi faily generated beacons between participating 2019 * stations. Set TBTT phase adaptive adjustment step to 8us. 2020 */ 2021 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); 2022 2023 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); 2024 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); 2025 2026 /* 2027 * Clean up beacon skb. 2028 */ 2029 dev_kfree_skb_any(entry->skb); 2030 entry->skb = NULL; 2031 } 2032 2033 static void rt61pci_clear_beacon(struct queue_entry *entry) 2034 { 2035 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 2036 u32 orig_reg, reg; 2037 2038 /* 2039 * Disable beaconing while we are reloading the beacon data, 2040 * otherwise we might be sending out invalid data. 2041 */ 2042 orig_reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); 2043 reg = orig_reg; 2044 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); 2045 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); 2046 2047 /* 2048 * Clear beacon. 2049 */ 2050 rt2x00mmio_register_write(rt2x00dev, 2051 HW_BEACON_OFFSET(entry->entry_idx), 0); 2052 2053 /* 2054 * Restore global beaconing state. 2055 */ 2056 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg); 2057 } 2058 2059 /* 2060 * RX control handlers 2061 */ 2062 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1) 2063 { 2064 u8 offset = rt2x00dev->lna_gain; 2065 u8 lna; 2066 2067 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA); 2068 switch (lna) { 2069 case 3: 2070 offset += 90; 2071 break; 2072 case 2: 2073 offset += 74; 2074 break; 2075 case 1: 2076 offset += 64; 2077 break; 2078 default: 2079 return 0; 2080 } 2081 2082 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { 2083 if (lna == 3 || lna == 2) 2084 offset += 10; 2085 } 2086 2087 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset; 2088 } 2089 2090 static void rt61pci_fill_rxdone(struct queue_entry *entry, 2091 struct rxdone_entry_desc *rxdesc) 2092 { 2093 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 2094 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; 2095 u32 word0; 2096 u32 word1; 2097 2098 word0 = rt2x00_desc_read(entry_priv->desc, 0); 2099 word1 = rt2x00_desc_read(entry_priv->desc, 1); 2100 2101 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 2102 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 2103 2104 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG); 2105 rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR); 2106 2107 if (rxdesc->cipher != CIPHER_NONE) { 2108 rxdesc->iv[0] = _rt2x00_desc_read(entry_priv->desc, 2); 2109 rxdesc->iv[1] = _rt2x00_desc_read(entry_priv->desc, 3); 2110 rxdesc->dev_flags |= RXDONE_CRYPTO_IV; 2111 2112 rxdesc->icv = _rt2x00_desc_read(entry_priv->desc, 4); 2113 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV; 2114 2115 /* 2116 * Hardware has stripped IV/EIV data from 802.11 frame during 2117 * decryption. It has provided the data separately but rt2x00lib 2118 * should decide if it should be reinserted. 2119 */ 2120 rxdesc->flags |= RX_FLAG_IV_STRIPPED; 2121 2122 /* 2123 * The hardware has already checked the Michael Mic and has 2124 * stripped it from the frame. Signal this to mac80211. 2125 */ 2126 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED; 2127 2128 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS) 2129 rxdesc->flags |= RX_FLAG_DECRYPTED; 2130 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC) 2131 rxdesc->flags |= RX_FLAG_MMIC_ERROR; 2132 } 2133 2134 /* 2135 * Obtain the status about this packet. 2136 * When frame was received with an OFDM bitrate, 2137 * the signal is the PLCP value. If it was received with 2138 * a CCK bitrate the signal is the rate in 100kbit/s. 2139 */ 2140 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL); 2141 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1); 2142 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); 2143 2144 if (rt2x00_get_field32(word0, RXD_W0_OFDM)) 2145 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; 2146 else 2147 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE; 2148 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) 2149 rxdesc->dev_flags |= RXDONE_MY_BSS; 2150 } 2151 2152 /* 2153 * Interrupt functions. 2154 */ 2155 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev) 2156 { 2157 struct data_queue *queue; 2158 struct queue_entry *entry; 2159 struct queue_entry *entry_done; 2160 struct queue_entry_priv_mmio *entry_priv; 2161 struct txdone_entry_desc txdesc; 2162 u32 word; 2163 u32 reg; 2164 int type; 2165 int index; 2166 int i; 2167 2168 /* 2169 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO 2170 * at most X times and also stop processing once the TX_STA_FIFO_VALID 2171 * flag is not set anymore. 2172 * 2173 * The legacy drivers use X=TX_RING_SIZE but state in a comment 2174 * that the TX_STA_FIFO stack has a size of 16. We stick to our 2175 * tx ring size for now. 2176 */ 2177 for (i = 0; i < rt2x00dev->tx->limit; i++) { 2178 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR4); 2179 if (!rt2x00_get_field32(reg, STA_CSR4_VALID)) 2180 break; 2181 2182 /* 2183 * Skip this entry when it contains an invalid 2184 * queue identication number. 2185 */ 2186 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE); 2187 queue = rt2x00queue_get_tx_queue(rt2x00dev, type); 2188 if (unlikely(!queue)) 2189 continue; 2190 2191 /* 2192 * Skip this entry when it contains an invalid 2193 * index number. 2194 */ 2195 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE); 2196 if (unlikely(index >= queue->limit)) 2197 continue; 2198 2199 entry = &queue->entries[index]; 2200 entry_priv = entry->priv_data; 2201 word = rt2x00_desc_read(entry_priv->desc, 0); 2202 2203 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 2204 !rt2x00_get_field32(word, TXD_W0_VALID)) 2205 return; 2206 2207 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 2208 while (entry != entry_done) { 2209 /* Catch up. 2210 * Just report any entries we missed as failed. 2211 */ 2212 rt2x00_warn(rt2x00dev, "TX status report missed for entry %d\n", 2213 entry_done->entry_idx); 2214 2215 rt2x00lib_txdone_noinfo(entry_done, TXDONE_UNKNOWN); 2216 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 2217 } 2218 2219 /* 2220 * Obtain the status about this packet. 2221 */ 2222 txdesc.flags = 0; 2223 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) { 2224 case 0: /* Success, maybe with retry */ 2225 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 2226 break; 2227 case 6: /* Failure, excessive retries */ 2228 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags); 2229 /* Fall through - this is a failed frame! */ 2230 default: /* Failure */ 2231 __set_bit(TXDONE_FAILURE, &txdesc.flags); 2232 } 2233 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT); 2234 2235 /* 2236 * the frame was retried at least once 2237 * -> hw used fallback rates 2238 */ 2239 if (txdesc.retry) 2240 __set_bit(TXDONE_FALLBACK, &txdesc.flags); 2241 2242 rt2x00lib_txdone(entry, &txdesc); 2243 } 2244 } 2245 2246 static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev) 2247 { 2248 struct rt2x00lib_conf libconf = { .conf = &rt2x00dev->hw->conf }; 2249 2250 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS); 2251 } 2252 2253 static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, 2254 struct rt2x00_field32 irq_field) 2255 { 2256 u32 reg; 2257 2258 /* 2259 * Enable a single interrupt. The interrupt mask register 2260 * access needs locking. 2261 */ 2262 spin_lock_irq(&rt2x00dev->irqmask_lock); 2263 2264 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); 2265 rt2x00_set_field32(®, irq_field, 0); 2266 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); 2267 2268 spin_unlock_irq(&rt2x00dev->irqmask_lock); 2269 } 2270 2271 static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev, 2272 struct rt2x00_field32 irq_field) 2273 { 2274 u32 reg; 2275 2276 /* 2277 * Enable a single MCU interrupt. The interrupt mask register 2278 * access needs locking. 2279 */ 2280 spin_lock_irq(&rt2x00dev->irqmask_lock); 2281 2282 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); 2283 rt2x00_set_field32(®, irq_field, 0); 2284 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); 2285 2286 spin_unlock_irq(&rt2x00dev->irqmask_lock); 2287 } 2288 2289 static void rt61pci_txstatus_tasklet(unsigned long data) 2290 { 2291 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; 2292 rt61pci_txdone(rt2x00dev); 2293 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 2294 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TXDONE); 2295 } 2296 2297 static void rt61pci_tbtt_tasklet(unsigned long data) 2298 { 2299 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; 2300 rt2x00lib_beacondone(rt2x00dev); 2301 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 2302 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_BEACON_DONE); 2303 } 2304 2305 static void rt61pci_rxdone_tasklet(unsigned long data) 2306 { 2307 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; 2308 if (rt2x00mmio_rxdone(rt2x00dev)) 2309 tasklet_schedule(&rt2x00dev->rxdone_tasklet); 2310 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 2311 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE); 2312 } 2313 2314 static void rt61pci_autowake_tasklet(unsigned long data) 2315 { 2316 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; 2317 rt61pci_wakeup(rt2x00dev); 2318 rt2x00mmio_register_write(rt2x00dev, 2319 M2H_CMD_DONE_CSR, 0xffffffff); 2320 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 2321 rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP); 2322 } 2323 2324 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance) 2325 { 2326 struct rt2x00_dev *rt2x00dev = dev_instance; 2327 u32 reg_mcu, mask_mcu; 2328 u32 reg, mask; 2329 2330 /* 2331 * Get the interrupt sources & saved to local variable. 2332 * Write register value back to clear pending interrupts. 2333 */ 2334 reg_mcu = rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR); 2335 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu); 2336 2337 reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR); 2338 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 2339 2340 if (!reg && !reg_mcu) 2341 return IRQ_NONE; 2342 2343 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 2344 return IRQ_HANDLED; 2345 2346 /* 2347 * Schedule tasklets for interrupt handling. 2348 */ 2349 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE)) 2350 tasklet_schedule(&rt2x00dev->rxdone_tasklet); 2351 2352 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE)) 2353 tasklet_schedule(&rt2x00dev->txstatus_tasklet); 2354 2355 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE)) 2356 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet); 2357 2358 if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP)) 2359 tasklet_schedule(&rt2x00dev->autowake_tasklet); 2360 2361 /* 2362 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits 2363 * for interrupts and interrupt masks we can just use the value of 2364 * INT_SOURCE_CSR to create the interrupt mask. 2365 */ 2366 mask = reg; 2367 mask_mcu = reg_mcu; 2368 2369 /* 2370 * Disable all interrupts for which a tasklet was scheduled right now, 2371 * the tasklet will reenable the appropriate interrupts. 2372 */ 2373 spin_lock(&rt2x00dev->irqmask_lock); 2374 2375 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); 2376 reg |= mask; 2377 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); 2378 2379 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); 2380 reg |= mask_mcu; 2381 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); 2382 2383 spin_unlock(&rt2x00dev->irqmask_lock); 2384 2385 return IRQ_HANDLED; 2386 } 2387 2388 /* 2389 * Device probe functions. 2390 */ 2391 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) 2392 { 2393 struct eeprom_93cx6 eeprom; 2394 u32 reg; 2395 u16 word; 2396 u8 *mac; 2397 s8 value; 2398 2399 reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR); 2400 2401 eeprom.data = rt2x00dev; 2402 eeprom.register_read = rt61pci_eepromregister_read; 2403 eeprom.register_write = rt61pci_eepromregister_write; 2404 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ? 2405 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66; 2406 eeprom.reg_data_in = 0; 2407 eeprom.reg_data_out = 0; 2408 eeprom.reg_data_clock = 0; 2409 eeprom.reg_chip_select = 0; 2410 2411 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, 2412 EEPROM_SIZE / sizeof(u16)); 2413 2414 /* 2415 * Start validation of the data that has been read. 2416 */ 2417 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 2418 rt2x00lib_set_mac_address(rt2x00dev, mac); 2419 2420 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA); 2421 if (word == 0xffff) { 2422 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); 2423 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 2424 ANTENNA_B); 2425 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 2426 ANTENNA_B); 2427 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0); 2428 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); 2429 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); 2430 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225); 2431 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); 2432 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 2433 } 2434 2435 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC); 2436 if (word == 0xffff) { 2437 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0); 2438 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0); 2439 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0); 2440 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0); 2441 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0); 2442 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0); 2443 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0); 2444 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); 2445 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 2446 } 2447 2448 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_LED); 2449 if (word == 0xffff) { 2450 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE, 2451 LED_MODE_DEFAULT); 2452 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word); 2453 rt2x00_eeprom_dbg(rt2x00dev, "Led: 0x%04x\n", word); 2454 } 2455 2456 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ); 2457 if (word == 0xffff) { 2458 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 2459 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0); 2460 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 2461 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); 2462 } 2463 2464 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG); 2465 if (word == 0xffff) { 2466 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); 2467 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); 2468 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); 2469 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word); 2470 } else { 2471 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1); 2472 if (value < -10 || value > 10) 2473 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); 2474 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2); 2475 if (value < -10 || value > 10) 2476 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); 2477 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); 2478 } 2479 2480 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A); 2481 if (word == 0xffff) { 2482 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); 2483 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); 2484 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); 2485 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word); 2486 } else { 2487 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1); 2488 if (value < -10 || value > 10) 2489 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); 2490 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2); 2491 if (value < -10 || value > 10) 2492 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); 2493 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); 2494 } 2495 2496 return 0; 2497 } 2498 2499 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev) 2500 { 2501 u32 reg; 2502 u16 value; 2503 u16 eeprom; 2504 2505 /* 2506 * Read EEPROM word for configuration. 2507 */ 2508 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA); 2509 2510 /* 2511 * Identify RF chipset. 2512 */ 2513 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 2514 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR0); 2515 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), 2516 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); 2517 2518 if (!rt2x00_rf(rt2x00dev, RF5225) && 2519 !rt2x00_rf(rt2x00dev, RF5325) && 2520 !rt2x00_rf(rt2x00dev, RF2527) && 2521 !rt2x00_rf(rt2x00dev, RF2529)) { 2522 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n"); 2523 return -ENODEV; 2524 } 2525 2526 /* 2527 * Determine number of antennas. 2528 */ 2529 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2) 2530 __set_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags); 2531 2532 /* 2533 * Identify default antenna configuration. 2534 */ 2535 rt2x00dev->default_ant.tx = 2536 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); 2537 rt2x00dev->default_ant.rx = 2538 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); 2539 2540 /* 2541 * Read the Frame type. 2542 */ 2543 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE)) 2544 __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags); 2545 2546 /* 2547 * Detect if this device has a hardware controlled radio. 2548 */ 2549 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) 2550 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 2551 2552 /* 2553 * Read frequency offset and RF programming sequence. 2554 */ 2555 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ); 2556 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ)) 2557 __set_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags); 2558 2559 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 2560 2561 /* 2562 * Read external LNA informations. 2563 */ 2564 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC); 2565 2566 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A)) 2567 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); 2568 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG)) 2569 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); 2570 2571 /* 2572 * When working with a RF2529 chip without double antenna, 2573 * the antenna settings should be gathered from the NIC 2574 * eeprom word. 2575 */ 2576 if (rt2x00_rf(rt2x00dev, RF2529) && 2577 !rt2x00_has_cap_double_antenna(rt2x00dev)) { 2578 rt2x00dev->default_ant.rx = 2579 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED); 2580 rt2x00dev->default_ant.tx = 2581 ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED); 2582 2583 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) 2584 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY; 2585 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY)) 2586 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY; 2587 } 2588 2589 /* 2590 * Store led settings, for correct led behaviour. 2591 * If the eeprom value is invalid, 2592 * switch to default led mode. 2593 */ 2594 #ifdef CONFIG_RT2X00_LIB_LEDS 2595 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_LED); 2596 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE); 2597 2598 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 2599 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 2600 if (value == LED_MODE_SIGNAL_STRENGTH) 2601 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual, 2602 LED_TYPE_QUALITY); 2603 2604 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value); 2605 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0, 2606 rt2x00_get_field16(eeprom, 2607 EEPROM_LED_POLARITY_GPIO_0)); 2608 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1, 2609 rt2x00_get_field16(eeprom, 2610 EEPROM_LED_POLARITY_GPIO_1)); 2611 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2, 2612 rt2x00_get_field16(eeprom, 2613 EEPROM_LED_POLARITY_GPIO_2)); 2614 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3, 2615 rt2x00_get_field16(eeprom, 2616 EEPROM_LED_POLARITY_GPIO_3)); 2617 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4, 2618 rt2x00_get_field16(eeprom, 2619 EEPROM_LED_POLARITY_GPIO_4)); 2620 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT, 2621 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT)); 2622 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG, 2623 rt2x00_get_field16(eeprom, 2624 EEPROM_LED_POLARITY_RDY_G)); 2625 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A, 2626 rt2x00_get_field16(eeprom, 2627 EEPROM_LED_POLARITY_RDY_A)); 2628 #endif /* CONFIG_RT2X00_LIB_LEDS */ 2629 2630 return 0; 2631 } 2632 2633 /* 2634 * RF value list for RF5225 & RF5325 2635 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled 2636 */ 2637 static const struct rf_channel rf_vals_noseq[] = { 2638 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, 2639 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, 2640 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, 2641 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, 2642 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, 2643 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, 2644 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, 2645 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, 2646 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, 2647 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, 2648 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, 2649 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, 2650 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, 2651 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, 2652 2653 /* 802.11 UNI / HyperLan 2 */ 2654 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 }, 2655 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 }, 2656 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b }, 2657 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 }, 2658 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b }, 2659 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 }, 2660 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 }, 2661 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b }, 2662 2663 /* 802.11 HyperLan 2 */ 2664 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 }, 2665 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b }, 2666 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 }, 2667 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b }, 2668 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 }, 2669 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 }, 2670 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b }, 2671 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 }, 2672 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b }, 2673 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 }, 2674 2675 /* 802.11 UNII */ 2676 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 }, 2677 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f }, 2678 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 }, 2679 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 }, 2680 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f }, 2681 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 }, 2682 2683 /* MMAC(Japan)J52 ch 34,38,42,46 */ 2684 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b }, 2685 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 }, 2686 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b }, 2687 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 }, 2688 }; 2689 2690 /* 2691 * RF value list for RF5225 & RF5325 2692 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled 2693 */ 2694 static const struct rf_channel rf_vals_seq[] = { 2695 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, 2696 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, 2697 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, 2698 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, 2699 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, 2700 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, 2701 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, 2702 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, 2703 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, 2704 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, 2705 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, 2706 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, 2707 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, 2708 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, 2709 2710 /* 802.11 UNI / HyperLan 2 */ 2711 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 }, 2712 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 }, 2713 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b }, 2714 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b }, 2715 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 }, 2716 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 }, 2717 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 }, 2718 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b }, 2719 2720 /* 802.11 HyperLan 2 */ 2721 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 }, 2722 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 }, 2723 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 }, 2724 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 }, 2725 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 }, 2726 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 }, 2727 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b }, 2728 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b }, 2729 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 }, 2730 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 }, 2731 2732 /* 802.11 UNII */ 2733 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 }, 2734 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b }, 2735 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b }, 2736 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 }, 2737 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 }, 2738 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 }, 2739 2740 /* MMAC(Japan)J52 ch 34,38,42,46 */ 2741 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b }, 2742 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 }, 2743 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b }, 2744 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 }, 2745 }; 2746 2747 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 2748 { 2749 struct hw_mode_spec *spec = &rt2x00dev->spec; 2750 struct channel_info *info; 2751 char *tx_power; 2752 unsigned int i; 2753 2754 /* 2755 * Disable powersaving as default. 2756 */ 2757 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 2758 2759 /* 2760 * Initialize all hw fields. 2761 */ 2762 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); 2763 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); 2764 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); 2765 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); 2766 2767 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 2768 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 2769 rt2x00_eeprom_addr(rt2x00dev, 2770 EEPROM_MAC_ADDR_0)); 2771 2772 /* 2773 * As rt61 has a global fallback table we cannot specify 2774 * more then one tx rate per frame but since the hw will 2775 * try several rates (based on the fallback table) we should 2776 * initialize max_report_rates to the maximum number of rates 2777 * we are going to try. Otherwise mac80211 will truncate our 2778 * reported tx rates and the rc algortihm will end up with 2779 * incorrect data. 2780 */ 2781 rt2x00dev->hw->max_rates = 1; 2782 rt2x00dev->hw->max_report_rates = 7; 2783 rt2x00dev->hw->max_rate_tries = 1; 2784 2785 /* 2786 * Initialize hw_mode information. 2787 */ 2788 spec->supported_bands = SUPPORT_BAND_2GHZ; 2789 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 2790 2791 if (!rt2x00_has_cap_rf_sequence(rt2x00dev)) { 2792 spec->num_channels = 14; 2793 spec->channels = rf_vals_noseq; 2794 } else { 2795 spec->num_channels = 14; 2796 spec->channels = rf_vals_seq; 2797 } 2798 2799 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) { 2800 spec->supported_bands |= SUPPORT_BAND_5GHZ; 2801 spec->num_channels = ARRAY_SIZE(rf_vals_seq); 2802 } 2803 2804 /* 2805 * Create channel information array 2806 */ 2807 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 2808 if (!info) 2809 return -ENOMEM; 2810 2811 spec->channels_info = info; 2812 2813 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); 2814 for (i = 0; i < 14; i++) { 2815 info[i].max_power = MAX_TXPOWER; 2816 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); 2817 } 2818 2819 if (spec->num_channels > 14) { 2820 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); 2821 for (i = 14; i < spec->num_channels; i++) { 2822 info[i].max_power = MAX_TXPOWER; 2823 info[i].default_power1 = 2824 TXPOWER_FROM_DEV(tx_power[i - 14]); 2825 } 2826 } 2827 2828 return 0; 2829 } 2830 2831 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev) 2832 { 2833 int retval; 2834 u32 reg; 2835 2836 /* 2837 * Disable power saving. 2838 */ 2839 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007); 2840 2841 /* 2842 * Allocate eeprom data. 2843 */ 2844 retval = rt61pci_validate_eeprom(rt2x00dev); 2845 if (retval) 2846 return retval; 2847 2848 retval = rt61pci_init_eeprom(rt2x00dev); 2849 if (retval) 2850 return retval; 2851 2852 /* 2853 * Enable rfkill polling by setting GPIO direction of the 2854 * rfkill switch GPIO pin correctly. 2855 */ 2856 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); 2857 rt2x00_set_field32(®, MAC_CSR13_DIR5, 1); 2858 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); 2859 2860 /* 2861 * Initialize hw specifications. 2862 */ 2863 retval = rt61pci_probe_hw_mode(rt2x00dev); 2864 if (retval) 2865 return retval; 2866 2867 /* 2868 * This device has multiple filters for control frames, 2869 * but has no a separate filter for PS Poll frames. 2870 */ 2871 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); 2872 2873 /* 2874 * This device requires firmware and DMA mapped skbs. 2875 */ 2876 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); 2877 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); 2878 if (!modparam_nohwcrypt) 2879 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); 2880 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 2881 2882 /* 2883 * Set the rssi offset. 2884 */ 2885 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 2886 2887 return 0; 2888 } 2889 2890 /* 2891 * IEEE80211 stack callback functions. 2892 */ 2893 static int rt61pci_conf_tx(struct ieee80211_hw *hw, 2894 struct ieee80211_vif *vif, u16 queue_idx, 2895 const struct ieee80211_tx_queue_params *params) 2896 { 2897 struct rt2x00_dev *rt2x00dev = hw->priv; 2898 struct data_queue *queue; 2899 struct rt2x00_field32 field; 2900 int retval; 2901 u32 reg; 2902 u32 offset; 2903 2904 /* 2905 * First pass the configuration through rt2x00lib, that will 2906 * update the queue settings and validate the input. After that 2907 * we are free to update the registers based on the value 2908 * in the queue parameter. 2909 */ 2910 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params); 2911 if (retval) 2912 return retval; 2913 2914 /* 2915 * We only need to perform additional register initialization 2916 * for WMM queues. 2917 */ 2918 if (queue_idx >= 4) 2919 return 0; 2920 2921 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 2922 2923 /* Update WMM TXOP register */ 2924 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2))); 2925 field.bit_offset = (queue_idx & 1) * 16; 2926 field.bit_mask = 0xffff << field.bit_offset; 2927 2928 reg = rt2x00mmio_register_read(rt2x00dev, offset); 2929 rt2x00_set_field32(®, field, queue->txop); 2930 rt2x00mmio_register_write(rt2x00dev, offset, reg); 2931 2932 /* Update WMM registers */ 2933 field.bit_offset = queue_idx * 4; 2934 field.bit_mask = 0xf << field.bit_offset; 2935 2936 reg = rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR); 2937 rt2x00_set_field32(®, field, queue->aifs); 2938 rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg); 2939 2940 reg = rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR); 2941 rt2x00_set_field32(®, field, queue->cw_min); 2942 rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg); 2943 2944 reg = rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR); 2945 rt2x00_set_field32(®, field, queue->cw_max); 2946 rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg); 2947 2948 return 0; 2949 } 2950 2951 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 2952 { 2953 struct rt2x00_dev *rt2x00dev = hw->priv; 2954 u64 tsf; 2955 u32 reg; 2956 2957 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13); 2958 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; 2959 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12); 2960 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); 2961 2962 return tsf; 2963 } 2964 2965 static const struct ieee80211_ops rt61pci_mac80211_ops = { 2966 .tx = rt2x00mac_tx, 2967 .start = rt2x00mac_start, 2968 .stop = rt2x00mac_stop, 2969 .add_interface = rt2x00mac_add_interface, 2970 .remove_interface = rt2x00mac_remove_interface, 2971 .config = rt2x00mac_config, 2972 .configure_filter = rt2x00mac_configure_filter, 2973 .set_key = rt2x00mac_set_key, 2974 .sw_scan_start = rt2x00mac_sw_scan_start, 2975 .sw_scan_complete = rt2x00mac_sw_scan_complete, 2976 .get_stats = rt2x00mac_get_stats, 2977 .bss_info_changed = rt2x00mac_bss_info_changed, 2978 .conf_tx = rt61pci_conf_tx, 2979 .get_tsf = rt61pci_get_tsf, 2980 .rfkill_poll = rt2x00mac_rfkill_poll, 2981 .flush = rt2x00mac_flush, 2982 .set_antenna = rt2x00mac_set_antenna, 2983 .get_antenna = rt2x00mac_get_antenna, 2984 .get_ringparam = rt2x00mac_get_ringparam, 2985 .tx_frames_pending = rt2x00mac_tx_frames_pending, 2986 }; 2987 2988 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = { 2989 .irq_handler = rt61pci_interrupt, 2990 .txstatus_tasklet = rt61pci_txstatus_tasklet, 2991 .tbtt_tasklet = rt61pci_tbtt_tasklet, 2992 .rxdone_tasklet = rt61pci_rxdone_tasklet, 2993 .autowake_tasklet = rt61pci_autowake_tasklet, 2994 .probe_hw = rt61pci_probe_hw, 2995 .get_firmware_name = rt61pci_get_firmware_name, 2996 .check_firmware = rt61pci_check_firmware, 2997 .load_firmware = rt61pci_load_firmware, 2998 .initialize = rt2x00mmio_initialize, 2999 .uninitialize = rt2x00mmio_uninitialize, 3000 .get_entry_state = rt61pci_get_entry_state, 3001 .clear_entry = rt61pci_clear_entry, 3002 .set_device_state = rt61pci_set_device_state, 3003 .rfkill_poll = rt61pci_rfkill_poll, 3004 .link_stats = rt61pci_link_stats, 3005 .reset_tuner = rt61pci_reset_tuner, 3006 .link_tuner = rt61pci_link_tuner, 3007 .start_queue = rt61pci_start_queue, 3008 .kick_queue = rt61pci_kick_queue, 3009 .stop_queue = rt61pci_stop_queue, 3010 .flush_queue = rt2x00mmio_flush_queue, 3011 .write_tx_desc = rt61pci_write_tx_desc, 3012 .write_beacon = rt61pci_write_beacon, 3013 .clear_beacon = rt61pci_clear_beacon, 3014 .fill_rxdone = rt61pci_fill_rxdone, 3015 .config_shared_key = rt61pci_config_shared_key, 3016 .config_pairwise_key = rt61pci_config_pairwise_key, 3017 .config_filter = rt61pci_config_filter, 3018 .config_intf = rt61pci_config_intf, 3019 .config_erp = rt61pci_config_erp, 3020 .config_ant = rt61pci_config_ant, 3021 .config = rt61pci_config, 3022 }; 3023 3024 static void rt61pci_queue_init(struct data_queue *queue) 3025 { 3026 switch (queue->qid) { 3027 case QID_RX: 3028 queue->limit = 32; 3029 queue->data_size = DATA_FRAME_SIZE; 3030 queue->desc_size = RXD_DESC_SIZE; 3031 queue->priv_size = sizeof(struct queue_entry_priv_mmio); 3032 break; 3033 3034 case QID_AC_VO: 3035 case QID_AC_VI: 3036 case QID_AC_BE: 3037 case QID_AC_BK: 3038 queue->limit = 32; 3039 queue->data_size = DATA_FRAME_SIZE; 3040 queue->desc_size = TXD_DESC_SIZE; 3041 queue->priv_size = sizeof(struct queue_entry_priv_mmio); 3042 break; 3043 3044 case QID_BEACON: 3045 queue->limit = 4; 3046 queue->data_size = 0; /* No DMA required for beacons */ 3047 queue->desc_size = TXINFO_SIZE; 3048 queue->priv_size = sizeof(struct queue_entry_priv_mmio); 3049 break; 3050 3051 case QID_ATIM: 3052 /* fallthrough */ 3053 default: 3054 BUG(); 3055 break; 3056 } 3057 } 3058 3059 static const struct rt2x00_ops rt61pci_ops = { 3060 .name = KBUILD_MODNAME, 3061 .max_ap_intf = 4, 3062 .eeprom_size = EEPROM_SIZE, 3063 .rf_size = RF_SIZE, 3064 .tx_queues = NUM_TX_QUEUES, 3065 .queue_init = rt61pci_queue_init, 3066 .lib = &rt61pci_rt2x00_ops, 3067 .hw = &rt61pci_mac80211_ops, 3068 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 3069 .debugfs = &rt61pci_rt2x00debug, 3070 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 3071 }; 3072 3073 /* 3074 * RT61pci module information. 3075 */ 3076 static const struct pci_device_id rt61pci_device_table[] = { 3077 /* RT2561s */ 3078 { PCI_DEVICE(0x1814, 0x0301) }, 3079 /* RT2561 v2 */ 3080 { PCI_DEVICE(0x1814, 0x0302) }, 3081 /* RT2661 */ 3082 { PCI_DEVICE(0x1814, 0x0401) }, 3083 { 0, } 3084 }; 3085 3086 MODULE_AUTHOR(DRV_PROJECT); 3087 MODULE_VERSION(DRV_VERSION); 3088 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver."); 3089 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 " 3090 "PCI & PCMCIA chipset based cards"); 3091 MODULE_DEVICE_TABLE(pci, rt61pci_device_table); 3092 MODULE_FIRMWARE(FIRMWARE_RT2561); 3093 MODULE_FIRMWARE(FIRMWARE_RT2561s); 3094 MODULE_FIRMWARE(FIRMWARE_RT2661); 3095 MODULE_LICENSE("GPL"); 3096 3097 static int rt61pci_probe(struct pci_dev *pci_dev, 3098 const struct pci_device_id *id) 3099 { 3100 return rt2x00pci_probe(pci_dev, &rt61pci_ops); 3101 } 3102 3103 static struct pci_driver rt61pci_driver = { 3104 .name = KBUILD_MODNAME, 3105 .id_table = rt61pci_device_table, 3106 .probe = rt61pci_probe, 3107 .remove = rt2x00pci_remove, 3108 .suspend = rt2x00pci_suspend, 3109 .resume = rt2x00pci_resume, 3110 }; 3111 3112 module_pci_driver(rt61pci_driver); 3113