1 /* 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> 6 7 Based on the original rt2800pci.c and rt2800usb.c. 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 14 <http://rt2x00.serialmonkey.com> 15 16 This program is free software; you can redistribute it and/or modify 17 it under the terms of the GNU General Public License as published by 18 the Free Software Foundation; either version 2 of the License, or 19 (at your option) any later version. 20 21 This program is distributed in the hope that it will be useful, 22 but WITHOUT ANY WARRANTY; without even the implied warranty of 23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 GNU General Public License for more details. 25 26 You should have received a copy of the GNU General Public License 27 along with this program; if not, see <http://www.gnu.org/licenses/>. 28 */ 29 30 /* 31 Module: rt2800lib 32 Abstract: rt2800 generic device routines. 33 */ 34 35 #include <linux/crc-ccitt.h> 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/slab.h> 39 40 #include "rt2x00.h" 41 #include "rt2800lib.h" 42 #include "rt2800.h" 43 44 /* 45 * Register access. 46 * All access to the CSR registers will go through the methods 47 * rt2800_register_read and rt2800_register_write. 48 * BBP and RF register require indirect register access, 49 * and use the CSR registers BBPCSR and RFCSR to achieve this. 50 * These indirect registers work with busy bits, 51 * and we will try maximal REGISTER_BUSY_COUNT times to access 52 * the register while taking a REGISTER_BUSY_DELAY us delay 53 * between each attampt. When the busy bit is still set at that time, 54 * the access attempt is considered to have failed, 55 * and we will print an error. 56 * The _lock versions must be used if you already hold the csr_mutex 57 */ 58 #define WAIT_FOR_BBP(__dev, __reg) \ 59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) 60 #define WAIT_FOR_RFCSR(__dev, __reg) \ 61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) 62 #define WAIT_FOR_RF(__dev, __reg) \ 63 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) 64 #define WAIT_FOR_MCU(__dev, __reg) \ 65 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 66 H2M_MAILBOX_CSR_OWNER, (__reg)) 67 68 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) 69 { 70 /* check for rt2872 on SoC */ 71 if (!rt2x00_is_soc(rt2x00dev) || 72 !rt2x00_rt(rt2x00dev, RT2872)) 73 return false; 74 75 /* we know for sure that these rf chipsets are used on rt305x boards */ 76 if (rt2x00_rf(rt2x00dev, RF3020) || 77 rt2x00_rf(rt2x00dev, RF3021) || 78 rt2x00_rf(rt2x00dev, RF3022)) 79 return true; 80 81 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n"); 82 return false; 83 } 84 85 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, 86 const unsigned int word, const u8 value) 87 { 88 u32 reg; 89 90 mutex_lock(&rt2x00dev->csr_mutex); 91 92 /* 93 * Wait until the BBP becomes available, afterwards we 94 * can safely write the new data into the register. 95 */ 96 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 97 reg = 0; 98 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); 99 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 100 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 101 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); 102 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 103 104 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 105 } 106 107 mutex_unlock(&rt2x00dev->csr_mutex); 108 } 109 110 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, 111 const unsigned int word, u8 *value) 112 { 113 u32 reg; 114 115 mutex_lock(&rt2x00dev->csr_mutex); 116 117 /* 118 * Wait until the BBP becomes available, afterwards we 119 * can safely write the read request into the register. 120 * After the data has been written, we wait until hardware 121 * returns the correct value, if at any time the register 122 * doesn't become available in time, reg will be 0xffffffff 123 * which means we return 0xff to the caller. 124 */ 125 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 126 reg = 0; 127 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 128 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 129 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); 130 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 131 132 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 133 134 WAIT_FOR_BBP(rt2x00dev, ®); 135 } 136 137 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); 138 139 mutex_unlock(&rt2x00dev->csr_mutex); 140 } 141 142 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, 143 const unsigned int word, const u8 value) 144 { 145 u32 reg; 146 147 mutex_lock(&rt2x00dev->csr_mutex); 148 149 /* 150 * Wait until the RFCSR becomes available, afterwards we 151 * can safely write the new data into the register. 152 */ 153 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 154 reg = 0; 155 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); 156 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 157 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); 158 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 159 160 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 161 } 162 163 mutex_unlock(&rt2x00dev->csr_mutex); 164 } 165 166 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, 167 const unsigned int word, u8 *value) 168 { 169 u32 reg; 170 171 mutex_lock(&rt2x00dev->csr_mutex); 172 173 /* 174 * Wait until the RFCSR becomes available, afterwards we 175 * can safely write the read request into the register. 176 * After the data has been written, we wait until hardware 177 * returns the correct value, if at any time the register 178 * doesn't become available in time, reg will be 0xffffffff 179 * which means we return 0xff to the caller. 180 */ 181 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 182 reg = 0; 183 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 184 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); 185 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 186 187 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 188 189 WAIT_FOR_RFCSR(rt2x00dev, ®); 190 } 191 192 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); 193 194 mutex_unlock(&rt2x00dev->csr_mutex); 195 } 196 197 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, 198 const unsigned int word, const u32 value) 199 { 200 u32 reg; 201 202 mutex_lock(&rt2x00dev->csr_mutex); 203 204 /* 205 * Wait until the RF becomes available, afterwards we 206 * can safely write the new data into the register. 207 */ 208 if (WAIT_FOR_RF(rt2x00dev, ®)) { 209 reg = 0; 210 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); 211 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); 212 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); 213 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); 214 215 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); 216 rt2x00_rf_write(rt2x00dev, word, value); 217 } 218 219 mutex_unlock(&rt2x00dev->csr_mutex); 220 } 221 222 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { 223 [EEPROM_CHIP_ID] = 0x0000, 224 [EEPROM_VERSION] = 0x0001, 225 [EEPROM_MAC_ADDR_0] = 0x0002, 226 [EEPROM_MAC_ADDR_1] = 0x0003, 227 [EEPROM_MAC_ADDR_2] = 0x0004, 228 [EEPROM_NIC_CONF0] = 0x001a, 229 [EEPROM_NIC_CONF1] = 0x001b, 230 [EEPROM_FREQ] = 0x001d, 231 [EEPROM_LED_AG_CONF] = 0x001e, 232 [EEPROM_LED_ACT_CONF] = 0x001f, 233 [EEPROM_LED_POLARITY] = 0x0020, 234 [EEPROM_NIC_CONF2] = 0x0021, 235 [EEPROM_LNA] = 0x0022, 236 [EEPROM_RSSI_BG] = 0x0023, 237 [EEPROM_RSSI_BG2] = 0x0024, 238 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */ 239 [EEPROM_RSSI_A] = 0x0025, 240 [EEPROM_RSSI_A2] = 0x0026, 241 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */ 242 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027, 243 [EEPROM_TXPOWER_DELTA] = 0x0028, 244 [EEPROM_TXPOWER_BG1] = 0x0029, 245 [EEPROM_TXPOWER_BG2] = 0x0030, 246 [EEPROM_TSSI_BOUND_BG1] = 0x0037, 247 [EEPROM_TSSI_BOUND_BG2] = 0x0038, 248 [EEPROM_TSSI_BOUND_BG3] = 0x0039, 249 [EEPROM_TSSI_BOUND_BG4] = 0x003a, 250 [EEPROM_TSSI_BOUND_BG5] = 0x003b, 251 [EEPROM_TXPOWER_A1] = 0x003c, 252 [EEPROM_TXPOWER_A2] = 0x0053, 253 [EEPROM_TSSI_BOUND_A1] = 0x006a, 254 [EEPROM_TSSI_BOUND_A2] = 0x006b, 255 [EEPROM_TSSI_BOUND_A3] = 0x006c, 256 [EEPROM_TSSI_BOUND_A4] = 0x006d, 257 [EEPROM_TSSI_BOUND_A5] = 0x006e, 258 [EEPROM_TXPOWER_BYRATE] = 0x006f, 259 [EEPROM_BBP_START] = 0x0078, 260 }; 261 262 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = { 263 [EEPROM_CHIP_ID] = 0x0000, 264 [EEPROM_VERSION] = 0x0001, 265 [EEPROM_MAC_ADDR_0] = 0x0002, 266 [EEPROM_MAC_ADDR_1] = 0x0003, 267 [EEPROM_MAC_ADDR_2] = 0x0004, 268 [EEPROM_NIC_CONF0] = 0x001a, 269 [EEPROM_NIC_CONF1] = 0x001b, 270 [EEPROM_NIC_CONF2] = 0x001c, 271 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020, 272 [EEPROM_FREQ] = 0x0022, 273 [EEPROM_LED_AG_CONF] = 0x0023, 274 [EEPROM_LED_ACT_CONF] = 0x0024, 275 [EEPROM_LED_POLARITY] = 0x0025, 276 [EEPROM_LNA] = 0x0026, 277 [EEPROM_EXT_LNA2] = 0x0027, 278 [EEPROM_RSSI_BG] = 0x0028, 279 [EEPROM_RSSI_BG2] = 0x0029, 280 [EEPROM_RSSI_A] = 0x002a, 281 [EEPROM_RSSI_A2] = 0x002b, 282 [EEPROM_TXPOWER_BG1] = 0x0030, 283 [EEPROM_TXPOWER_BG2] = 0x0037, 284 [EEPROM_EXT_TXPOWER_BG3] = 0x003e, 285 [EEPROM_TSSI_BOUND_BG1] = 0x0045, 286 [EEPROM_TSSI_BOUND_BG2] = 0x0046, 287 [EEPROM_TSSI_BOUND_BG3] = 0x0047, 288 [EEPROM_TSSI_BOUND_BG4] = 0x0048, 289 [EEPROM_TSSI_BOUND_BG5] = 0x0049, 290 [EEPROM_TXPOWER_A1] = 0x004b, 291 [EEPROM_TXPOWER_A2] = 0x0065, 292 [EEPROM_EXT_TXPOWER_A3] = 0x007f, 293 [EEPROM_TSSI_BOUND_A1] = 0x009a, 294 [EEPROM_TSSI_BOUND_A2] = 0x009b, 295 [EEPROM_TSSI_BOUND_A3] = 0x009c, 296 [EEPROM_TSSI_BOUND_A4] = 0x009d, 297 [EEPROM_TSSI_BOUND_A5] = 0x009e, 298 [EEPROM_TXPOWER_BYRATE] = 0x00a0, 299 }; 300 301 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev, 302 const enum rt2800_eeprom_word word) 303 { 304 const unsigned int *map; 305 unsigned int index; 306 307 if (WARN_ONCE(word >= EEPROM_WORD_COUNT, 308 "%s: invalid EEPROM word %d\n", 309 wiphy_name(rt2x00dev->hw->wiphy), word)) 310 return 0; 311 312 if (rt2x00_rt(rt2x00dev, RT3593)) 313 map = rt2800_eeprom_map_ext; 314 else 315 map = rt2800_eeprom_map; 316 317 index = map[word]; 318 319 /* Index 0 is valid only for EEPROM_CHIP_ID. 320 * Otherwise it means that the offset of the 321 * given word is not initialized in the map, 322 * or that the field is not usable on the 323 * actual chipset. 324 */ 325 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0, 326 "%s: invalid access of EEPROM word %d\n", 327 wiphy_name(rt2x00dev->hw->wiphy), word); 328 329 return index; 330 } 331 332 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev, 333 const enum rt2800_eeprom_word word) 334 { 335 unsigned int index; 336 337 index = rt2800_eeprom_word_index(rt2x00dev, word); 338 return rt2x00_eeprom_addr(rt2x00dev, index); 339 } 340 341 static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, 342 const enum rt2800_eeprom_word word, u16 *data) 343 { 344 unsigned int index; 345 346 index = rt2800_eeprom_word_index(rt2x00dev, word); 347 rt2x00_eeprom_read(rt2x00dev, index, data); 348 } 349 350 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, 351 const enum rt2800_eeprom_word word, u16 data) 352 { 353 unsigned int index; 354 355 index = rt2800_eeprom_word_index(rt2x00dev, word); 356 rt2x00_eeprom_write(rt2x00dev, index, data); 357 } 358 359 static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, 360 const enum rt2800_eeprom_word array, 361 unsigned int offset, 362 u16 *data) 363 { 364 unsigned int index; 365 366 index = rt2800_eeprom_word_index(rt2x00dev, array); 367 rt2x00_eeprom_read(rt2x00dev, index + offset, data); 368 } 369 370 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) 371 { 372 u32 reg; 373 int i, count; 374 375 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); 376 if (rt2x00_get_field32(reg, WLAN_EN)) 377 return 0; 378 379 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); 380 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); 381 rt2x00_set_field32(®, WLAN_CLK_EN, 0); 382 rt2x00_set_field32(®, WLAN_EN, 1); 383 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 384 385 udelay(REGISTER_BUSY_DELAY); 386 387 count = 0; 388 do { 389 /* 390 * Check PLL_LD & XTAL_RDY. 391 */ 392 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 393 rt2800_register_read(rt2x00dev, CMB_CTRL, ®); 394 if (rt2x00_get_field32(reg, PLL_LD) && 395 rt2x00_get_field32(reg, XTAL_RDY)) 396 break; 397 udelay(REGISTER_BUSY_DELAY); 398 } 399 400 if (i >= REGISTER_BUSY_COUNT) { 401 402 if (count >= 10) 403 return -EIO; 404 405 rt2800_register_write(rt2x00dev, 0x58, 0x018); 406 udelay(REGISTER_BUSY_DELAY); 407 rt2800_register_write(rt2x00dev, 0x58, 0x418); 408 udelay(REGISTER_BUSY_DELAY); 409 rt2800_register_write(rt2x00dev, 0x58, 0x618); 410 udelay(REGISTER_BUSY_DELAY); 411 count++; 412 } else { 413 count = 0; 414 } 415 416 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); 417 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); 418 rt2x00_set_field32(®, WLAN_CLK_EN, 1); 419 rt2x00_set_field32(®, WLAN_RESET, 1); 420 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 421 udelay(10); 422 rt2x00_set_field32(®, WLAN_RESET, 0); 423 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 424 udelay(10); 425 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff); 426 } while (count != 0); 427 428 return 0; 429 } 430 431 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 432 const u8 command, const u8 token, 433 const u8 arg0, const u8 arg1) 434 { 435 u32 reg; 436 437 /* 438 * SOC devices don't support MCU requests. 439 */ 440 if (rt2x00_is_soc(rt2x00dev)) 441 return; 442 443 mutex_lock(&rt2x00dev->csr_mutex); 444 445 /* 446 * Wait until the MCU becomes available, afterwards we 447 * can safely write the new data into the register. 448 */ 449 if (WAIT_FOR_MCU(rt2x00dev, ®)) { 450 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); 451 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); 452 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); 453 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); 454 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); 455 456 reg = 0; 457 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); 458 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); 459 } 460 461 mutex_unlock(&rt2x00dev->csr_mutex); 462 } 463 EXPORT_SYMBOL_GPL(rt2800_mcu_request); 464 465 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) 466 { 467 unsigned int i = 0; 468 u32 reg; 469 470 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 471 rt2800_register_read(rt2x00dev, MAC_CSR0, ®); 472 if (reg && reg != ~0) 473 return 0; 474 msleep(1); 475 } 476 477 rt2x00_err(rt2x00dev, "Unstable hardware\n"); 478 return -EBUSY; 479 } 480 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); 481 482 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 483 { 484 unsigned int i; 485 u32 reg; 486 487 /* 488 * Some devices are really slow to respond here. Wait a whole second 489 * before timing out. 490 */ 491 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 492 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); 493 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 494 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 495 return 0; 496 497 msleep(10); 498 } 499 500 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); 501 return -EACCES; 502 } 503 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); 504 505 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) 506 { 507 u32 reg; 508 509 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); 510 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 511 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 512 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 513 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 514 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 515 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 516 } 517 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma); 518 519 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev, 520 unsigned short *txwi_size, 521 unsigned short *rxwi_size) 522 { 523 switch (rt2x00dev->chip.rt) { 524 case RT3593: 525 *txwi_size = TXWI_DESC_SIZE_4WORDS; 526 *rxwi_size = RXWI_DESC_SIZE_5WORDS; 527 break; 528 529 case RT5592: 530 *txwi_size = TXWI_DESC_SIZE_5WORDS; 531 *rxwi_size = RXWI_DESC_SIZE_6WORDS; 532 break; 533 534 default: 535 *txwi_size = TXWI_DESC_SIZE_4WORDS; 536 *rxwi_size = RXWI_DESC_SIZE_4WORDS; 537 break; 538 } 539 } 540 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size); 541 542 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) 543 { 544 u16 fw_crc; 545 u16 crc; 546 547 /* 548 * The last 2 bytes in the firmware array are the crc checksum itself, 549 * this means that we should never pass those 2 bytes to the crc 550 * algorithm. 551 */ 552 fw_crc = (data[len - 2] << 8 | data[len - 1]); 553 554 /* 555 * Use the crc ccitt algorithm. 556 * This will return the same value as the legacy driver which 557 * used bit ordering reversion on the both the firmware bytes 558 * before input input as well as on the final output. 559 * Obviously using crc ccitt directly is much more efficient. 560 */ 561 crc = crc_ccitt(~0, data, len - 2); 562 563 /* 564 * There is a small difference between the crc-itu-t + bitrev and 565 * the crc-ccitt crc calculation. In the latter method the 2 bytes 566 * will be swapped, use swab16 to convert the crc to the correct 567 * value. 568 */ 569 crc = swab16(crc); 570 571 return fw_crc == crc; 572 } 573 574 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, 575 const u8 *data, const size_t len) 576 { 577 size_t offset = 0; 578 size_t fw_len; 579 bool multiple; 580 581 /* 582 * PCI(e) & SOC devices require firmware with a length 583 * of 8kb. USB devices require firmware files with a length 584 * of 4kb. Certain USB chipsets however require different firmware, 585 * which Ralink only provides attached to the original firmware 586 * file. Thus for USB devices, firmware files have a length 587 * which is a multiple of 4kb. The firmware for rt3290 chip also 588 * have a length which is a multiple of 4kb. 589 */ 590 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290)) 591 fw_len = 4096; 592 else 593 fw_len = 8192; 594 595 multiple = true; 596 /* 597 * Validate the firmware length 598 */ 599 if (len != fw_len && (!multiple || (len % fw_len) != 0)) 600 return FW_BAD_LENGTH; 601 602 /* 603 * Check if the chipset requires one of the upper parts 604 * of the firmware. 605 */ 606 if (rt2x00_is_usb(rt2x00dev) && 607 !rt2x00_rt(rt2x00dev, RT2860) && 608 !rt2x00_rt(rt2x00dev, RT2872) && 609 !rt2x00_rt(rt2x00dev, RT3070) && 610 ((len / fw_len) == 1)) 611 return FW_BAD_VERSION; 612 613 /* 614 * 8kb firmware files must be checked as if it were 615 * 2 separate firmware files. 616 */ 617 while (offset < len) { 618 if (!rt2800_check_firmware_crc(data + offset, fw_len)) 619 return FW_BAD_CRC; 620 621 offset += fw_len; 622 } 623 624 return FW_OK; 625 } 626 EXPORT_SYMBOL_GPL(rt2800_check_firmware); 627 628 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, 629 const u8 *data, const size_t len) 630 { 631 unsigned int i; 632 u32 reg; 633 int retval; 634 635 if (rt2x00_rt(rt2x00dev, RT3290)) { 636 retval = rt2800_enable_wlan_rt3290(rt2x00dev); 637 if (retval) 638 return -EBUSY; 639 } 640 641 /* 642 * If driver doesn't wake up firmware here, 643 * rt2800_load_firmware will hang forever when interface is up again. 644 */ 645 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 646 647 /* 648 * Wait for stable hardware. 649 */ 650 if (rt2800_wait_csr_ready(rt2x00dev)) 651 return -EBUSY; 652 653 if (rt2x00_is_pci(rt2x00dev)) { 654 if (rt2x00_rt(rt2x00dev, RT3290) || 655 rt2x00_rt(rt2x00dev, RT3572) || 656 rt2x00_rt(rt2x00dev, RT5390) || 657 rt2x00_rt(rt2x00dev, RT5392)) { 658 rt2800_register_read(rt2x00dev, AUX_CTRL, ®); 659 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); 660 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); 661 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); 662 } 663 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 664 } 665 666 rt2800_disable_wpdma(rt2x00dev); 667 668 /* 669 * Write firmware to the device. 670 */ 671 rt2800_drv_write_firmware(rt2x00dev, data, len); 672 673 /* 674 * Wait for device to stabilize. 675 */ 676 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 677 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®); 678 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 679 break; 680 msleep(1); 681 } 682 683 if (i == REGISTER_BUSY_COUNT) { 684 rt2x00_err(rt2x00dev, "PBF system register not ready\n"); 685 return -EBUSY; 686 } 687 688 /* 689 * Disable DMA, will be reenabled later when enabling 690 * the radio. 691 */ 692 rt2800_disable_wpdma(rt2x00dev); 693 694 /* 695 * Initialize firmware. 696 */ 697 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 698 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 699 if (rt2x00_is_usb(rt2x00dev)) { 700 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 701 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 702 } 703 msleep(1); 704 705 return 0; 706 } 707 EXPORT_SYMBOL_GPL(rt2800_load_firmware); 708 709 void rt2800_write_tx_data(struct queue_entry *entry, 710 struct txentry_desc *txdesc) 711 { 712 __le32 *txwi = rt2800_drv_get_txwi(entry); 713 u32 word; 714 int i; 715 716 /* 717 * Initialize TX Info descriptor 718 */ 719 rt2x00_desc_read(txwi, 0, &word); 720 rt2x00_set_field32(&word, TXWI_W0_FRAG, 721 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 722 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 723 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); 724 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); 725 rt2x00_set_field32(&word, TXWI_W0_TS, 726 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 727 rt2x00_set_field32(&word, TXWI_W0_AMPDU, 728 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); 729 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, 730 txdesc->u.ht.mpdu_density); 731 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); 732 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); 733 rt2x00_set_field32(&word, TXWI_W0_BW, 734 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); 735 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, 736 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); 737 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); 738 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); 739 rt2x00_desc_write(txwi, 0, word); 740 741 rt2x00_desc_read(txwi, 1, &word); 742 rt2x00_set_field32(&word, TXWI_W1_ACK, 743 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 744 rt2x00_set_field32(&word, TXWI_W1_NSEQ, 745 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 746 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); 747 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 748 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 749 txdesc->key_idx : txdesc->u.ht.wcid); 750 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 751 txdesc->length); 752 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); 753 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); 754 rt2x00_desc_write(txwi, 1, word); 755 756 /* 757 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert 758 * the IV from the IVEIV register when TXD_W3_WIV is set to 0. 759 * When TXD_W3_WIV is set to 1 it will use the IV data 760 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 761 * crypto entry in the registers should be used to encrypt the frame. 762 * 763 * Nulify all remaining words as well, we don't know how to program them. 764 */ 765 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++) 766 _rt2x00_desc_write(txwi, i, 0); 767 } 768 EXPORT_SYMBOL_GPL(rt2800_write_tx_data); 769 770 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) 771 { 772 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); 773 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); 774 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); 775 u16 eeprom; 776 u8 offset0; 777 u8 offset1; 778 u8 offset2; 779 780 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 781 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom); 782 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); 783 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); 784 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); 785 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); 786 } else { 787 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom); 788 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); 789 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); 790 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); 791 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); 792 } 793 794 /* 795 * Convert the value from the descriptor into the RSSI value 796 * If the value in the descriptor is 0, it is considered invalid 797 * and the default (extremely low) rssi value is assumed 798 */ 799 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128; 800 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128; 801 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128; 802 803 /* 804 * mac80211 only accepts a single RSSI value. Calculating the 805 * average doesn't deliver a fair answer either since -60:-60 would 806 * be considered equally good as -50:-70 while the second is the one 807 * which gives less energy... 808 */ 809 rssi0 = max(rssi0, rssi1); 810 return (int)max(rssi0, rssi2); 811 } 812 813 void rt2800_process_rxwi(struct queue_entry *entry, 814 struct rxdone_entry_desc *rxdesc) 815 { 816 __le32 *rxwi = (__le32 *) entry->skb->data; 817 u32 word; 818 819 rt2x00_desc_read(rxwi, 0, &word); 820 821 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); 822 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); 823 824 rt2x00_desc_read(rxwi, 1, &word); 825 826 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) 827 rxdesc->flags |= RX_FLAG_SHORT_GI; 828 829 if (rt2x00_get_field32(word, RXWI_W1_BW)) 830 rxdesc->flags |= RX_FLAG_40MHZ; 831 832 /* 833 * Detect RX rate, always use MCS as signal type. 834 */ 835 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; 836 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); 837 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); 838 839 /* 840 * Mask of 0x8 bit to remove the short preamble flag. 841 */ 842 if (rxdesc->rate_mode == RATE_MODE_CCK) 843 rxdesc->signal &= ~0x8; 844 845 rt2x00_desc_read(rxwi, 2, &word); 846 847 /* 848 * Convert descriptor AGC value to RSSI value. 849 */ 850 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); 851 /* 852 * Remove RXWI descriptor from start of the buffer. 853 */ 854 skb_pull(entry->skb, entry->queue->winfo_size); 855 } 856 EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 857 858 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi) 859 { 860 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 861 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 862 struct txdone_entry_desc txdesc; 863 u32 word; 864 u16 mcs, real_mcs; 865 int aggr, ampdu; 866 867 /* 868 * Obtain the status about this packet. 869 */ 870 txdesc.flags = 0; 871 rt2x00_desc_read(txwi, 0, &word); 872 873 mcs = rt2x00_get_field32(word, TXWI_W0_MCS); 874 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); 875 876 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 877 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); 878 879 /* 880 * If a frame was meant to be sent as a single non-aggregated MPDU 881 * but ended up in an aggregate the used tx rate doesn't correlate 882 * with the one specified in the TXWI as the whole aggregate is sent 883 * with the same rate. 884 * 885 * For example: two frames are sent to rt2x00, the first one sets 886 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 887 * and requests MCS15. If the hw aggregates both frames into one 888 * AMDPU the tx status for both frames will contain MCS7 although 889 * the frame was sent successfully. 890 * 891 * Hence, replace the requested rate with the real tx rate to not 892 * confuse the rate control algortihm by providing clearly wrong 893 * data. 894 */ 895 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) { 896 skbdesc->tx_rate_idx = real_mcs; 897 mcs = real_mcs; 898 } 899 900 if (aggr == 1 || ampdu == 1) 901 __set_bit(TXDONE_AMPDU, &txdesc.flags); 902 903 /* 904 * Ralink has a retry mechanism using a global fallback 905 * table. We setup this fallback table to try the immediate 906 * lower rate for all rates. In the TX_STA_FIFO, the MCS field 907 * always contains the MCS used for the last transmission, be 908 * it successful or not. 909 */ 910 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { 911 /* 912 * Transmission succeeded. The number of retries is 913 * mcs - real_mcs 914 */ 915 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 916 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); 917 } else { 918 /* 919 * Transmission failed. The number of retries is 920 * always 7 in this case (for a total number of 8 921 * frames sent). 922 */ 923 __set_bit(TXDONE_FAILURE, &txdesc.flags); 924 txdesc.retry = rt2x00dev->long_retry; 925 } 926 927 /* 928 * the frame was retried at least once 929 * -> hw used fallback rates 930 */ 931 if (txdesc.retry) 932 __set_bit(TXDONE_FALLBACK, &txdesc.flags); 933 934 rt2x00lib_txdone(entry, &txdesc); 935 } 936 EXPORT_SYMBOL_GPL(rt2800_txdone_entry); 937 938 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev, 939 unsigned int index) 940 { 941 return HW_BEACON_BASE(index); 942 } 943 944 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev, 945 unsigned int index) 946 { 947 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index)); 948 } 949 950 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev) 951 { 952 struct data_queue *queue = rt2x00dev->bcn; 953 struct queue_entry *entry; 954 int i, bcn_num = 0; 955 u64 off, reg = 0; 956 u32 bssid_dw1; 957 958 /* 959 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers. 960 */ 961 for (i = 0; i < queue->limit; i++) { 962 entry = &queue->entries[i]; 963 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags)) 964 continue; 965 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx); 966 reg |= off << (8 * bcn_num); 967 bcn_num++; 968 } 969 970 WARN_ON_ONCE(bcn_num != rt2x00dev->intf_beaconing); 971 972 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); 973 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); 974 975 /* 976 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons. 977 */ 978 rt2800_register_read(rt2x00dev, MAC_BSSID_DW1, &bssid_dw1); 979 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, 980 bcn_num > 0 ? bcn_num - 1 : 0); 981 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1); 982 } 983 984 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) 985 { 986 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 987 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 988 unsigned int beacon_base; 989 unsigned int padding_len; 990 u32 orig_reg, reg; 991 const int txwi_desc_size = entry->queue->winfo_size; 992 993 /* 994 * Disable beaconing while we are reloading the beacon data, 995 * otherwise we might be sending out invalid data. 996 */ 997 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); 998 orig_reg = reg; 999 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1000 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1001 1002 /* 1003 * Add space for the TXWI in front of the skb. 1004 */ 1005 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size); 1006 1007 /* 1008 * Register descriptor details in skb frame descriptor. 1009 */ 1010 skbdesc->flags |= SKBDESC_DESC_IN_SKB; 1011 skbdesc->desc = entry->skb->data; 1012 skbdesc->desc_len = txwi_desc_size; 1013 1014 /* 1015 * Add the TXWI for the beacon to the skb. 1016 */ 1017 rt2800_write_tx_data(entry, txdesc); 1018 1019 /* 1020 * Dump beacon to userspace through debugfs. 1021 */ 1022 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); 1023 1024 /* 1025 * Write entire beacon with TXWI and padding to register. 1026 */ 1027 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 1028 if (padding_len && skb_pad(entry->skb, padding_len)) { 1029 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); 1030 /* skb freed by skb_pad() on failure */ 1031 entry->skb = NULL; 1032 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1033 return; 1034 } 1035 1036 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx); 1037 1038 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, 1039 entry->skb->len + padding_len); 1040 __set_bit(ENTRY_BCN_ENABLED, &entry->flags); 1041 1042 /* 1043 * Change global beacons settings. 1044 */ 1045 rt2800_update_beacons_setup(rt2x00dev); 1046 1047 /* 1048 * Restore beaconing state. 1049 */ 1050 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1051 1052 /* 1053 * Clean up beacon skb. 1054 */ 1055 dev_kfree_skb_any(entry->skb); 1056 entry->skb = NULL; 1057 } 1058 EXPORT_SYMBOL_GPL(rt2800_write_beacon); 1059 1060 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, 1061 unsigned int index) 1062 { 1063 int i; 1064 const int txwi_desc_size = rt2x00dev->bcn->winfo_size; 1065 unsigned int beacon_base; 1066 1067 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index); 1068 1069 /* 1070 * For the Beacon base registers we only need to clear 1071 * the whole TXWI which (when set to 0) will invalidate 1072 * the entire beacon. 1073 */ 1074 for (i = 0; i < txwi_desc_size; i += sizeof(__le32)) 1075 rt2800_register_write(rt2x00dev, beacon_base + i, 0); 1076 } 1077 1078 void rt2800_clear_beacon(struct queue_entry *entry) 1079 { 1080 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1081 u32 orig_reg, reg; 1082 1083 /* 1084 * Disable beaconing while we are reloading the beacon data, 1085 * otherwise we might be sending out invalid data. 1086 */ 1087 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &orig_reg); 1088 reg = orig_reg; 1089 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1090 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1091 1092 /* 1093 * Clear beacon. 1094 */ 1095 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx); 1096 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags); 1097 1098 /* 1099 * Change global beacons settings. 1100 */ 1101 rt2800_update_beacons_setup(rt2x00dev); 1102 /* 1103 * Restore beaconing state. 1104 */ 1105 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1106 } 1107 EXPORT_SYMBOL_GPL(rt2800_clear_beacon); 1108 1109 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 1110 const struct rt2x00debug rt2800_rt2x00debug = { 1111 .owner = THIS_MODULE, 1112 .csr = { 1113 .read = rt2800_register_read, 1114 .write = rt2800_register_write, 1115 .flags = RT2X00DEBUGFS_OFFSET, 1116 .word_base = CSR_REG_BASE, 1117 .word_size = sizeof(u32), 1118 .word_count = CSR_REG_SIZE / sizeof(u32), 1119 }, 1120 .eeprom = { 1121 /* NOTE: The local EEPROM access functions can't 1122 * be used here, use the generic versions instead. 1123 */ 1124 .read = rt2x00_eeprom_read, 1125 .write = rt2x00_eeprom_write, 1126 .word_base = EEPROM_BASE, 1127 .word_size = sizeof(u16), 1128 .word_count = EEPROM_SIZE / sizeof(u16), 1129 }, 1130 .bbp = { 1131 .read = rt2800_bbp_read, 1132 .write = rt2800_bbp_write, 1133 .word_base = BBP_BASE, 1134 .word_size = sizeof(u8), 1135 .word_count = BBP_SIZE / sizeof(u8), 1136 }, 1137 .rf = { 1138 .read = rt2x00_rf_read, 1139 .write = rt2800_rf_write, 1140 .word_base = RF_BASE, 1141 .word_size = sizeof(u32), 1142 .word_count = RF_SIZE / sizeof(u32), 1143 }, 1144 .rfcsr = { 1145 .read = rt2800_rfcsr_read, 1146 .write = rt2800_rfcsr_write, 1147 .word_base = RFCSR_BASE, 1148 .word_size = sizeof(u8), 1149 .word_count = RFCSR_SIZE / sizeof(u8), 1150 }, 1151 }; 1152 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); 1153 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1154 1155 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) 1156 { 1157 u32 reg; 1158 1159 if (rt2x00_rt(rt2x00dev, RT3290)) { 1160 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); 1161 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); 1162 } else { 1163 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 1164 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); 1165 } 1166 } 1167 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 1168 1169 #ifdef CONFIG_RT2X00_LIB_LEDS 1170 static void rt2800_brightness_set(struct led_classdev *led_cdev, 1171 enum led_brightness brightness) 1172 { 1173 struct rt2x00_led *led = 1174 container_of(led_cdev, struct rt2x00_led, led_dev); 1175 unsigned int enabled = brightness != LED_OFF; 1176 unsigned int bg_mode = 1177 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); 1178 unsigned int polarity = 1179 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1180 EEPROM_FREQ_LED_POLARITY); 1181 unsigned int ledmode = 1182 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1183 EEPROM_FREQ_LED_MODE); 1184 u32 reg; 1185 1186 /* Check for SoC (SOC devices don't support MCU requests) */ 1187 if (rt2x00_is_soc(led->rt2x00dev)) { 1188 rt2800_register_read(led->rt2x00dev, LED_CFG, ®); 1189 1190 /* Set LED Polarity */ 1191 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); 1192 1193 /* Set LED Mode */ 1194 if (led->type == LED_TYPE_RADIO) { 1195 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 1196 enabled ? 3 : 0); 1197 } else if (led->type == LED_TYPE_ASSOC) { 1198 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 1199 enabled ? 3 : 0); 1200 } else if (led->type == LED_TYPE_QUALITY) { 1201 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 1202 enabled ? 3 : 0); 1203 } 1204 1205 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 1206 1207 } else { 1208 if (led->type == LED_TYPE_RADIO) { 1209 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1210 enabled ? 0x20 : 0); 1211 } else if (led->type == LED_TYPE_ASSOC) { 1212 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1213 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); 1214 } else if (led->type == LED_TYPE_QUALITY) { 1215 /* 1216 * The brightness is divided into 6 levels (0 - 5), 1217 * The specs tell us the following levels: 1218 * 0, 1 ,3, 7, 15, 31 1219 * to determine the level in a simple way we can simply 1220 * work with bitshifting: 1221 * (1 << level) - 1 1222 */ 1223 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 1224 (1 << brightness / (LED_FULL / 6)) - 1, 1225 polarity); 1226 } 1227 } 1228 } 1229 1230 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, 1231 struct rt2x00_led *led, enum led_type type) 1232 { 1233 led->rt2x00dev = rt2x00dev; 1234 led->type = type; 1235 led->led_dev.brightness_set = rt2800_brightness_set; 1236 led->flags = LED_INITIALIZED; 1237 } 1238 #endif /* CONFIG_RT2X00_LIB_LEDS */ 1239 1240 /* 1241 * Configuration handlers. 1242 */ 1243 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, 1244 const u8 *address, 1245 int wcid) 1246 { 1247 struct mac_wcid_entry wcid_entry; 1248 u32 offset; 1249 1250 offset = MAC_WCID_ENTRY(wcid); 1251 1252 memset(&wcid_entry, 0xff, sizeof(wcid_entry)); 1253 if (address) 1254 memcpy(wcid_entry.mac, address, ETH_ALEN); 1255 1256 rt2800_register_multiwrite(rt2x00dev, offset, 1257 &wcid_entry, sizeof(wcid_entry)); 1258 } 1259 1260 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) 1261 { 1262 u32 offset; 1263 offset = MAC_WCID_ATTR_ENTRY(wcid); 1264 rt2800_register_write(rt2x00dev, offset, 0); 1265 } 1266 1267 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, 1268 int wcid, u32 bssidx) 1269 { 1270 u32 offset = MAC_WCID_ATTR_ENTRY(wcid); 1271 u32 reg; 1272 1273 /* 1274 * The BSS Idx numbers is split in a main value of 3 bits, 1275 * and a extended field for adding one additional bit to the value. 1276 */ 1277 rt2800_register_read(rt2x00dev, offset, ®); 1278 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); 1279 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, 1280 (bssidx & 0x8) >> 3); 1281 rt2800_register_write(rt2x00dev, offset, reg); 1282 } 1283 1284 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, 1285 struct rt2x00lib_crypto *crypto, 1286 struct ieee80211_key_conf *key) 1287 { 1288 struct mac_iveiv_entry iveiv_entry; 1289 u32 offset; 1290 u32 reg; 1291 1292 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); 1293 1294 if (crypto->cmd == SET_KEY) { 1295 rt2800_register_read(rt2x00dev, offset, ®); 1296 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 1297 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 1298 /* 1299 * Both the cipher as the BSS Idx numbers are split in a main 1300 * value of 3 bits, and a extended field for adding one additional 1301 * bit to the value. 1302 */ 1303 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 1304 (crypto->cipher & 0x7)); 1305 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 1306 (crypto->cipher & 0x8) >> 3); 1307 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); 1308 rt2800_register_write(rt2x00dev, offset, reg); 1309 } else { 1310 /* Delete the cipher without touching the bssidx */ 1311 rt2800_register_read(rt2x00dev, offset, ®); 1312 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); 1313 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); 1314 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); 1315 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); 1316 rt2800_register_write(rt2x00dev, offset, reg); 1317 } 1318 1319 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 1320 1321 memset(&iveiv_entry, 0, sizeof(iveiv_entry)); 1322 if ((crypto->cipher == CIPHER_TKIP) || 1323 (crypto->cipher == CIPHER_TKIP_NO_MIC) || 1324 (crypto->cipher == CIPHER_AES)) 1325 iveiv_entry.iv[3] |= 0x20; 1326 iveiv_entry.iv[3] |= key->keyidx << 6; 1327 rt2800_register_multiwrite(rt2x00dev, offset, 1328 &iveiv_entry, sizeof(iveiv_entry)); 1329 } 1330 1331 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, 1332 struct rt2x00lib_crypto *crypto, 1333 struct ieee80211_key_conf *key) 1334 { 1335 struct hw_key_entry key_entry; 1336 struct rt2x00_field32 field; 1337 u32 offset; 1338 u32 reg; 1339 1340 if (crypto->cmd == SET_KEY) { 1341 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; 1342 1343 memcpy(key_entry.key, crypto->key, 1344 sizeof(key_entry.key)); 1345 memcpy(key_entry.tx_mic, crypto->tx_mic, 1346 sizeof(key_entry.tx_mic)); 1347 memcpy(key_entry.rx_mic, crypto->rx_mic, 1348 sizeof(key_entry.rx_mic)); 1349 1350 offset = SHARED_KEY_ENTRY(key->hw_key_idx); 1351 rt2800_register_multiwrite(rt2x00dev, offset, 1352 &key_entry, sizeof(key_entry)); 1353 } 1354 1355 /* 1356 * The cipher types are stored over multiple registers 1357 * starting with SHARED_KEY_MODE_BASE each word will have 1358 * 32 bits and contains the cipher types for 2 bssidx each. 1359 * Using the correct defines correctly will cause overhead, 1360 * so just calculate the correct offset. 1361 */ 1362 field.bit_offset = 4 * (key->hw_key_idx % 8); 1363 field.bit_mask = 0x7 << field.bit_offset; 1364 1365 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); 1366 1367 rt2800_register_read(rt2x00dev, offset, ®); 1368 rt2x00_set_field32(®, field, 1369 (crypto->cmd == SET_KEY) * crypto->cipher); 1370 rt2800_register_write(rt2x00dev, offset, reg); 1371 1372 /* 1373 * Update WCID information 1374 */ 1375 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); 1376 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, 1377 crypto->bssidx); 1378 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1379 1380 return 0; 1381 } 1382 EXPORT_SYMBOL_GPL(rt2800_config_shared_key); 1383 1384 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 1385 struct rt2x00lib_crypto *crypto, 1386 struct ieee80211_key_conf *key) 1387 { 1388 struct hw_key_entry key_entry; 1389 u32 offset; 1390 1391 if (crypto->cmd == SET_KEY) { 1392 /* 1393 * Allow key configuration only for STAs that are 1394 * known by the hw. 1395 */ 1396 if (crypto->wcid > WCID_END) 1397 return -ENOSPC; 1398 key->hw_key_idx = crypto->wcid; 1399 1400 memcpy(key_entry.key, crypto->key, 1401 sizeof(key_entry.key)); 1402 memcpy(key_entry.tx_mic, crypto->tx_mic, 1403 sizeof(key_entry.tx_mic)); 1404 memcpy(key_entry.rx_mic, crypto->rx_mic, 1405 sizeof(key_entry.rx_mic)); 1406 1407 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 1408 rt2800_register_multiwrite(rt2x00dev, offset, 1409 &key_entry, sizeof(key_entry)); 1410 } 1411 1412 /* 1413 * Update WCID information 1414 */ 1415 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1416 1417 return 0; 1418 } 1419 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); 1420 1421 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev) 1422 { 1423 u8 i, max_psdu; 1424 u32 reg; 1425 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1426 1427 for (i = 0; i < 3; i++) 1428 if (drv_data->ampdu_factor_cnt[i] > 0) 1429 break; 1430 1431 max_psdu = min(drv_data->max_psdu, i); 1432 1433 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®); 1434 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); 1435 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1436 } 1437 1438 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif, 1439 struct ieee80211_sta *sta) 1440 { 1441 int wcid; 1442 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1443 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1444 1445 /* 1446 * Limit global maximum TX AMPDU length to smallest value of all 1447 * connected stations. In AP mode this can be suboptimal, but we 1448 * do not have a choice if some connected STA is not capable to 1449 * receive the same amount of data like the others. 1450 */ 1451 if (sta->ht_cap.ht_supported) { 1452 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++; 1453 rt2800_set_max_psdu_len(rt2x00dev); 1454 } 1455 1456 /* 1457 * Search for the first free WCID entry and return the corresponding 1458 * index. 1459 */ 1460 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START; 1461 1462 /* 1463 * Store selected wcid even if it is invalid so that we can 1464 * later decide if the STA is uploaded into the hw. 1465 */ 1466 sta_priv->wcid = wcid; 1467 1468 /* 1469 * No space left in the device, however, we can still communicate 1470 * with the STA -> No error. 1471 */ 1472 if (wcid > WCID_END) 1473 return 0; 1474 1475 __set_bit(wcid - WCID_START, drv_data->sta_ids); 1476 1477 /* 1478 * Clean up WCID attributes and write STA address to the device. 1479 */ 1480 rt2800_delete_wcid_attr(rt2x00dev, wcid); 1481 rt2800_config_wcid(rt2x00dev, sta->addr, wcid); 1482 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, 1483 rt2x00lib_get_bssidx(rt2x00dev, vif)); 1484 return 0; 1485 } 1486 EXPORT_SYMBOL_GPL(rt2800_sta_add); 1487 1488 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, struct ieee80211_sta *sta) 1489 { 1490 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1491 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1492 int wcid = sta_priv->wcid; 1493 1494 if (sta->ht_cap.ht_supported) { 1495 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--; 1496 rt2800_set_max_psdu_len(rt2x00dev); 1497 } 1498 1499 if (wcid > WCID_END) 1500 return 0; 1501 /* 1502 * Remove WCID entry, no need to clean the attributes as they will 1503 * get renewed when the WCID is reused. 1504 */ 1505 rt2800_config_wcid(rt2x00dev, NULL, wcid); 1506 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1507 1508 return 0; 1509 } 1510 EXPORT_SYMBOL_GPL(rt2800_sta_remove); 1511 1512 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, 1513 const unsigned int filter_flags) 1514 { 1515 u32 reg; 1516 1517 /* 1518 * Start configuration steps. 1519 * Note that the version error will always be dropped 1520 * and broadcast frames will always be accepted since 1521 * there is no filter for it at this time. 1522 */ 1523 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®); 1524 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, 1525 !(filter_flags & FIF_FCSFAIL)); 1526 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, 1527 !(filter_flags & FIF_PLCPFAIL)); 1528 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, 1529 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); 1530 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); 1531 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); 1532 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, 1533 !(filter_flags & FIF_ALLMULTI)); 1534 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); 1535 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); 1536 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, 1537 !(filter_flags & FIF_CONTROL)); 1538 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, 1539 !(filter_flags & FIF_CONTROL)); 1540 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, 1541 !(filter_flags & FIF_CONTROL)); 1542 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, 1543 !(filter_flags & FIF_CONTROL)); 1544 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, 1545 !(filter_flags & FIF_CONTROL)); 1546 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, 1547 !(filter_flags & FIF_PSPOLL)); 1548 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); 1549 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 1550 !(filter_flags & FIF_CONTROL)); 1551 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, 1552 !(filter_flags & FIF_CONTROL)); 1553 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); 1554 } 1555 EXPORT_SYMBOL_GPL(rt2800_config_filter); 1556 1557 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, 1558 struct rt2x00intf_conf *conf, const unsigned int flags) 1559 { 1560 u32 reg; 1561 bool update_bssid = false; 1562 1563 if (flags & CONFIG_UPDATE_TYPE) { 1564 /* 1565 * Enable synchronisation. 1566 */ 1567 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); 1568 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); 1569 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1570 1571 if (conf->sync == TSF_SYNC_AP_NONE) { 1572 /* 1573 * Tune beacon queue transmit parameters for AP mode 1574 */ 1575 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); 1576 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); 1577 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); 1578 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1579 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); 1580 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1581 } else { 1582 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); 1583 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); 1584 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); 1585 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1586 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); 1587 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1588 } 1589 } 1590 1591 if (flags & CONFIG_UPDATE_MAC) { 1592 if (flags & CONFIG_UPDATE_TYPE && 1593 conf->sync == TSF_SYNC_AP_NONE) { 1594 /* 1595 * The BSSID register has to be set to our own mac 1596 * address in AP mode. 1597 */ 1598 memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); 1599 update_bssid = true; 1600 } 1601 1602 if (!is_zero_ether_addr((const u8 *)conf->mac)) { 1603 reg = le32_to_cpu(conf->mac[1]); 1604 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); 1605 conf->mac[1] = cpu_to_le32(reg); 1606 } 1607 1608 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, 1609 conf->mac, sizeof(conf->mac)); 1610 } 1611 1612 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { 1613 if (!is_zero_ether_addr((const u8 *)conf->bssid)) { 1614 reg = le32_to_cpu(conf->bssid[1]); 1615 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); 1616 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); 1617 conf->bssid[1] = cpu_to_le32(reg); 1618 } 1619 1620 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, 1621 conf->bssid, sizeof(conf->bssid)); 1622 } 1623 } 1624 EXPORT_SYMBOL_GPL(rt2800_config_intf); 1625 1626 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, 1627 struct rt2x00lib_erp *erp) 1628 { 1629 bool any_sta_nongf = !!(erp->ht_opmode & 1630 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 1631 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; 1632 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; 1633 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; 1634 u32 reg; 1635 1636 /* default protection rate for HT20: OFDM 24M */ 1637 mm20_rate = gf20_rate = 0x4004; 1638 1639 /* default protection rate for HT40: duplicate OFDM 24M */ 1640 mm40_rate = gf40_rate = 0x4084; 1641 1642 switch (protection) { 1643 case IEEE80211_HT_OP_MODE_PROTECTION_NONE: 1644 /* 1645 * All STAs in this BSS are HT20/40 but there might be 1646 * STAs not supporting greenfield mode. 1647 * => Disable protection for HT transmissions. 1648 */ 1649 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; 1650 1651 break; 1652 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 1653 /* 1654 * All STAs in this BSS are HT20 or HT20/40 but there 1655 * might be STAs not supporting greenfield mode. 1656 * => Protect all HT40 transmissions. 1657 */ 1658 mm20_mode = gf20_mode = 0; 1659 mm40_mode = gf40_mode = 1; 1660 1661 break; 1662 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 1663 /* 1664 * Nonmember protection: 1665 * According to 802.11n we _should_ protect all 1666 * HT transmissions (but we don't have to). 1667 * 1668 * But if cts_protection is enabled we _shall_ protect 1669 * all HT transmissions using a CCK rate. 1670 * 1671 * And if any station is non GF we _shall_ protect 1672 * GF transmissions. 1673 * 1674 * We decide to protect everything 1675 * -> fall through to mixed mode. 1676 */ 1677 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 1678 /* 1679 * Legacy STAs are present 1680 * => Protect all HT transmissions. 1681 */ 1682 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1; 1683 1684 /* 1685 * If erp protection is needed we have to protect HT 1686 * transmissions with CCK 11M long preamble. 1687 */ 1688 if (erp->cts_protection) { 1689 /* don't duplicate RTS/CTS in CCK mode */ 1690 mm20_rate = mm40_rate = 0x0003; 1691 gf20_rate = gf40_rate = 0x0003; 1692 } 1693 break; 1694 } 1695 1696 /* check for STAs not supporting greenfield mode */ 1697 if (any_sta_nongf) 1698 gf20_mode = gf40_mode = 1; 1699 1700 /* Update HT protection config */ 1701 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); 1702 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); 1703 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); 1704 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 1705 1706 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); 1707 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); 1708 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); 1709 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 1710 1711 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); 1712 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); 1713 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); 1714 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 1715 1716 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); 1717 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); 1718 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); 1719 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 1720 } 1721 1722 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, 1723 u32 changed) 1724 { 1725 u32 reg; 1726 1727 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 1728 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); 1729 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 1730 !!erp->short_preamble); 1731 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 1732 } 1733 1734 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 1735 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); 1736 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 1737 erp->cts_protection ? 2 : 0); 1738 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 1739 } 1740 1741 if (changed & BSS_CHANGED_BASIC_RATES) { 1742 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 1743 0xff0 | erp->basic_rates); 1744 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 1745 } 1746 1747 if (changed & BSS_CHANGED_ERP_SLOT) { 1748 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); 1749 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 1750 erp->slot_time); 1751 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 1752 1753 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); 1754 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); 1755 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 1756 } 1757 1758 if (changed & BSS_CHANGED_BEACON_INT) { 1759 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); 1760 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1761 erp->beacon_int * 16); 1762 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1763 } 1764 1765 if (changed & BSS_CHANGED_HT) 1766 rt2800_config_ht_opmode(rt2x00dev, erp); 1767 } 1768 EXPORT_SYMBOL_GPL(rt2800_config_erp); 1769 1770 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) 1771 { 1772 u32 reg; 1773 u16 eeprom; 1774 u8 led_ctrl, led_g_mode, led_r_mode; 1775 1776 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); 1777 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { 1778 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); 1779 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); 1780 } else { 1781 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); 1782 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); 1783 } 1784 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 1785 1786 rt2800_register_read(rt2x00dev, LED_CFG, ®); 1787 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; 1788 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; 1789 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || 1790 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { 1791 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); 1792 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); 1793 if (led_ctrl == 0 || led_ctrl > 0x40) { 1794 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); 1795 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); 1796 rt2800_register_write(rt2x00dev, LED_CFG, reg); 1797 } else { 1798 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, 1799 (led_g_mode << 2) | led_r_mode, 1); 1800 } 1801 } 1802 } 1803 1804 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, 1805 enum antenna ant) 1806 { 1807 u32 reg; 1808 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; 1809 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; 1810 1811 if (rt2x00_is_pci(rt2x00dev)) { 1812 rt2800_register_read(rt2x00dev, E2PROM_CSR, ®); 1813 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); 1814 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); 1815 } else if (rt2x00_is_usb(rt2x00dev)) 1816 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, 1817 eesk_pin, 0); 1818 1819 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 1820 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 1821 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); 1822 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 1823 } 1824 1825 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 1826 { 1827 u8 r1; 1828 u8 r3; 1829 u16 eeprom; 1830 1831 rt2800_bbp_read(rt2x00dev, 1, &r1); 1832 rt2800_bbp_read(rt2x00dev, 3, &r3); 1833 1834 if (rt2x00_rt(rt2x00dev, RT3572) && 1835 rt2x00_has_cap_bt_coexist(rt2x00dev)) 1836 rt2800_config_3572bt_ant(rt2x00dev); 1837 1838 /* 1839 * Configure the TX antenna. 1840 */ 1841 switch (ant->tx_chain_num) { 1842 case 1: 1843 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 1844 break; 1845 case 2: 1846 if (rt2x00_rt(rt2x00dev, RT3572) && 1847 rt2x00_has_cap_bt_coexist(rt2x00dev)) 1848 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); 1849 else 1850 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 1851 break; 1852 case 3: 1853 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 1854 break; 1855 } 1856 1857 /* 1858 * Configure the RX antenna. 1859 */ 1860 switch (ant->rx_chain_num) { 1861 case 1: 1862 if (rt2x00_rt(rt2x00dev, RT3070) || 1863 rt2x00_rt(rt2x00dev, RT3090) || 1864 rt2x00_rt(rt2x00dev, RT3352) || 1865 rt2x00_rt(rt2x00dev, RT3390)) { 1866 rt2800_eeprom_read(rt2x00dev, 1867 EEPROM_NIC_CONF1, &eeprom); 1868 if (rt2x00_get_field16(eeprom, 1869 EEPROM_NIC_CONF1_ANT_DIVERSITY)) 1870 rt2800_set_ant_diversity(rt2x00dev, 1871 rt2x00dev->default_ant.rx); 1872 } 1873 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 1874 break; 1875 case 2: 1876 if (rt2x00_rt(rt2x00dev, RT3572) && 1877 rt2x00_has_cap_bt_coexist(rt2x00dev)) { 1878 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); 1879 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1880 rt2x00dev->curr_band == NL80211_BAND_5GHZ); 1881 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); 1882 } else { 1883 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); 1884 } 1885 break; 1886 case 3: 1887 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); 1888 break; 1889 } 1890 1891 rt2800_bbp_write(rt2x00dev, 3, r3); 1892 rt2800_bbp_write(rt2x00dev, 1, r1); 1893 1894 if (rt2x00_rt(rt2x00dev, RT3593)) { 1895 if (ant->rx_chain_num == 1) 1896 rt2800_bbp_write(rt2x00dev, 86, 0x00); 1897 else 1898 rt2800_bbp_write(rt2x00dev, 86, 0x46); 1899 } 1900 } 1901 EXPORT_SYMBOL_GPL(rt2800_config_ant); 1902 1903 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, 1904 struct rt2x00lib_conf *libconf) 1905 { 1906 u16 eeprom; 1907 short lna_gain; 1908 1909 if (libconf->rf.channel <= 14) { 1910 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); 1911 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); 1912 } else if (libconf->rf.channel <= 64) { 1913 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); 1914 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); 1915 } else if (libconf->rf.channel <= 128) { 1916 if (rt2x00_rt(rt2x00dev, RT3593)) { 1917 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom); 1918 lna_gain = rt2x00_get_field16(eeprom, 1919 EEPROM_EXT_LNA2_A1); 1920 } else { 1921 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); 1922 lna_gain = rt2x00_get_field16(eeprom, 1923 EEPROM_RSSI_BG2_LNA_A1); 1924 } 1925 } else { 1926 if (rt2x00_rt(rt2x00dev, RT3593)) { 1927 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom); 1928 lna_gain = rt2x00_get_field16(eeprom, 1929 EEPROM_EXT_LNA2_A2); 1930 } else { 1931 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); 1932 lna_gain = rt2x00_get_field16(eeprom, 1933 EEPROM_RSSI_A2_LNA_A2); 1934 } 1935 } 1936 1937 rt2x00dev->lna_gain = lna_gain; 1938 } 1939 1940 #define FREQ_OFFSET_BOUND 0x5f 1941 1942 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev) 1943 { 1944 u8 freq_offset, prev_freq_offset; 1945 u8 rfcsr, prev_rfcsr; 1946 1947 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE); 1948 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND); 1949 1950 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); 1951 prev_rfcsr = rfcsr; 1952 1953 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset); 1954 if (rfcsr == prev_rfcsr) 1955 return; 1956 1957 if (rt2x00_is_usb(rt2x00dev)) { 1958 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff, 1959 freq_offset, prev_rfcsr); 1960 return; 1961 } 1962 1963 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE); 1964 while (prev_freq_offset != freq_offset) { 1965 if (prev_freq_offset < freq_offset) 1966 prev_freq_offset++; 1967 else 1968 prev_freq_offset--; 1969 1970 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset); 1971 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 1972 1973 usleep_range(1000, 1500); 1974 } 1975 } 1976 1977 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, 1978 struct ieee80211_conf *conf, 1979 struct rf_channel *rf, 1980 struct channel_info *info) 1981 { 1982 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 1983 1984 if (rt2x00dev->default_ant.tx_chain_num == 1) 1985 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); 1986 1987 if (rt2x00dev->default_ant.rx_chain_num == 1) { 1988 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); 1989 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 1990 } else if (rt2x00dev->default_ant.rx_chain_num == 2) 1991 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 1992 1993 if (rf->channel > 14) { 1994 /* 1995 * When TX power is below 0, we should increase it by 7 to 1996 * make it a positive value (Minimum value is -7). 1997 * However this means that values between 0 and 7 have 1998 * double meaning, and we should set a 7DBm boost flag. 1999 */ 2000 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, 2001 (info->default_power1 >= 0)); 2002 2003 if (info->default_power1 < 0) 2004 info->default_power1 += 7; 2005 2006 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); 2007 2008 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, 2009 (info->default_power2 >= 0)); 2010 2011 if (info->default_power2 < 0) 2012 info->default_power2 += 7; 2013 2014 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); 2015 } else { 2016 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); 2017 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); 2018 } 2019 2020 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); 2021 2022 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2023 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2024 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2025 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2026 2027 udelay(200); 2028 2029 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2030 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2031 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 2032 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2033 2034 udelay(200); 2035 2036 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2037 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2038 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2039 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2040 } 2041 2042 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, 2043 struct ieee80211_conf *conf, 2044 struct rf_channel *rf, 2045 struct channel_info *info) 2046 { 2047 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2048 u8 rfcsr, calib_tx, calib_rx; 2049 2050 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2051 2052 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); 2053 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3); 2054 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2055 2056 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 2057 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2058 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2059 2060 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); 2061 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); 2062 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2063 2064 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); 2065 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); 2066 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2067 2068 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2069 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2070 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 2071 rt2x00dev->default_ant.rx_chain_num <= 1); 2072 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 2073 rt2x00dev->default_ant.rx_chain_num <= 2); 2074 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2075 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 2076 rt2x00dev->default_ant.tx_chain_num <= 1); 2077 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 2078 rt2x00dev->default_ant.tx_chain_num <= 2); 2079 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2080 2081 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); 2082 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2083 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2084 2085 if (rt2x00_rt(rt2x00dev, RT3390)) { 2086 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f; 2087 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f; 2088 } else { 2089 if (conf_is_ht40(conf)) { 2090 calib_tx = drv_data->calibration_bw40; 2091 calib_rx = drv_data->calibration_bw40; 2092 } else { 2093 calib_tx = drv_data->calibration_bw20; 2094 calib_rx = drv_data->calibration_bw20; 2095 } 2096 } 2097 2098 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr); 2099 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx); 2100 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr); 2101 2102 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr); 2103 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx); 2104 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2105 2106 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); 2107 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2108 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2109 2110 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 2111 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 2112 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2113 2114 usleep_range(1000, 1500); 2115 2116 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 2117 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2118 } 2119 2120 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, 2121 struct ieee80211_conf *conf, 2122 struct rf_channel *rf, 2123 struct channel_info *info) 2124 { 2125 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2126 u8 rfcsr; 2127 u32 reg; 2128 2129 if (rf->channel <= 14) { 2130 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2131 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2132 } else { 2133 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2134 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2135 } 2136 2137 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2138 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 2139 2140 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 2141 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2142 if (rf->channel <= 14) 2143 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); 2144 else 2145 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); 2146 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2147 2148 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr); 2149 if (rf->channel <= 14) 2150 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); 2151 else 2152 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); 2153 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); 2154 2155 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); 2156 if (rf->channel <= 14) { 2157 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); 2158 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2159 info->default_power1); 2160 } else { 2161 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); 2162 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2163 (info->default_power1 & 0x3) | 2164 ((info->default_power1 & 0xC) << 1)); 2165 } 2166 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2167 2168 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); 2169 if (rf->channel <= 14) { 2170 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); 2171 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2172 info->default_power2); 2173 } else { 2174 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); 2175 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2176 (info->default_power2 & 0x3) | 2177 ((info->default_power2 & 0xC) << 1)); 2178 } 2179 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2180 2181 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2182 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2183 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2184 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2185 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2186 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2187 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2188 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2189 if (rf->channel <= 14) { 2190 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2191 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2192 } 2193 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2194 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2195 } else { 2196 switch (rt2x00dev->default_ant.tx_chain_num) { 2197 case 1: 2198 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2199 case 2: 2200 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2201 break; 2202 } 2203 2204 switch (rt2x00dev->default_ant.rx_chain_num) { 2205 case 1: 2206 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2207 case 2: 2208 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2209 break; 2210 } 2211 } 2212 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2213 2214 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); 2215 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2216 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2217 2218 if (conf_is_ht40(conf)) { 2219 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40); 2220 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40); 2221 } else { 2222 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20); 2223 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20); 2224 } 2225 2226 if (rf->channel <= 14) { 2227 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 2228 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 2229 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2230 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 2231 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 2232 rfcsr = 0x4c; 2233 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2234 drv_data->txmixer_gain_24g); 2235 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2236 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2237 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 2238 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 2239 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 2240 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 2241 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 2242 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 2243 } else { 2244 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); 2245 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1); 2246 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0); 2247 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1); 2248 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0); 2249 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2250 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 2251 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2252 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 2253 rt2800_rfcsr_write(rt2x00dev, 15, 0x43); 2254 rfcsr = 0x7a; 2255 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2256 drv_data->txmixer_gain_5g); 2257 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2258 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2259 if (rf->channel <= 64) { 2260 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7); 2261 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6); 2262 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 2263 } else if (rf->channel <= 128) { 2264 rt2800_rfcsr_write(rt2x00dev, 19, 0x74); 2265 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4); 2266 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2267 } else { 2268 rt2800_rfcsr_write(rt2x00dev, 19, 0x72); 2269 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3); 2270 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2271 } 2272 rt2800_rfcsr_write(rt2x00dev, 26, 0x87); 2273 rt2800_rfcsr_write(rt2x00dev, 27, 0x01); 2274 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); 2275 } 2276 2277 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 2278 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 2279 if (rf->channel <= 14) 2280 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 2281 else 2282 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); 2283 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2284 2285 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); 2286 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2287 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2288 } 2289 2290 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, 2291 struct ieee80211_conf *conf, 2292 struct rf_channel *rf, 2293 struct channel_info *info) 2294 { 2295 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2296 u8 txrx_agc_fc; 2297 u8 txrx_h20m; 2298 u8 rfcsr; 2299 u8 bbp; 2300 const bool txbf_enabled = false; /* TODO */ 2301 2302 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */ 2303 rt2800_bbp_read(rt2x00dev, 109, &bbp); 2304 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0); 2305 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0); 2306 rt2800_bbp_write(rt2x00dev, 109, bbp); 2307 2308 rt2800_bbp_read(rt2x00dev, 110, &bbp); 2309 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0); 2310 rt2800_bbp_write(rt2x00dev, 110, bbp); 2311 2312 if (rf->channel <= 14) { 2313 /* Restore BBP 25 & 26 for 2.4 GHz */ 2314 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2315 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2316 } else { 2317 /* Hard code BBP 25 & 26 for 5GHz */ 2318 2319 /* Enable IQ Phase correction */ 2320 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2321 /* Setup IQ Phase correction value */ 2322 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2323 } 2324 2325 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2326 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf); 2327 2328 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); 2329 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3)); 2330 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2331 2332 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); 2333 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1); 2334 if (rf->channel <= 14) 2335 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1); 2336 else 2337 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2); 2338 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2339 2340 rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr); 2341 if (rf->channel <= 14) { 2342 rfcsr = 0; 2343 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2344 info->default_power1 & 0x1f); 2345 } else { 2346 if (rt2x00_is_usb(rt2x00dev)) 2347 rfcsr = 0x40; 2348 2349 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2350 ((info->default_power1 & 0x18) << 1) | 2351 (info->default_power1 & 7)); 2352 } 2353 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr); 2354 2355 rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr); 2356 if (rf->channel <= 14) { 2357 rfcsr = 0; 2358 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2359 info->default_power2 & 0x1f); 2360 } else { 2361 if (rt2x00_is_usb(rt2x00dev)) 2362 rfcsr = 0x40; 2363 2364 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2365 ((info->default_power2 & 0x18) << 1) | 2366 (info->default_power2 & 7)); 2367 } 2368 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr); 2369 2370 rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr); 2371 if (rf->channel <= 14) { 2372 rfcsr = 0; 2373 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2374 info->default_power3 & 0x1f); 2375 } else { 2376 if (rt2x00_is_usb(rt2x00dev)) 2377 rfcsr = 0x40; 2378 2379 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2380 ((info->default_power3 & 0x18) << 1) | 2381 (info->default_power3 & 7)); 2382 } 2383 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr); 2384 2385 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2386 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2387 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2388 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2389 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2390 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2391 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2392 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2393 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2394 2395 switch (rt2x00dev->default_ant.tx_chain_num) { 2396 case 3: 2397 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2398 /* fallthrough */ 2399 case 2: 2400 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2401 /* fallthrough */ 2402 case 1: 2403 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2404 break; 2405 } 2406 2407 switch (rt2x00dev->default_ant.rx_chain_num) { 2408 case 3: 2409 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2410 /* fallthrough */ 2411 case 2: 2412 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2413 /* fallthrough */ 2414 case 1: 2415 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2416 break; 2417 } 2418 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2419 2420 rt2800_freq_cal_mode1(rt2x00dev); 2421 2422 if (conf_is_ht40(conf)) { 2423 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40, 2424 RFCSR24_TX_AGC_FC); 2425 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40, 2426 RFCSR24_TX_H20M); 2427 } else { 2428 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20, 2429 RFCSR24_TX_AGC_FC); 2430 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20, 2431 RFCSR24_TX_H20M); 2432 } 2433 2434 /* NOTE: the reference driver does not writes the new value 2435 * back to RFCSR 32 2436 */ 2437 rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr); 2438 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc); 2439 2440 if (rf->channel <= 14) 2441 rfcsr = 0xa0; 2442 else 2443 rfcsr = 0x80; 2444 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2445 2446 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 2447 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m); 2448 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m); 2449 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2450 2451 /* Band selection */ 2452 rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr); 2453 if (rf->channel <= 14) 2454 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 2455 else 2456 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 2457 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 2458 2459 rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr); 2460 if (rf->channel <= 14) 2461 rfcsr = 0x3c; 2462 else 2463 rfcsr = 0x20; 2464 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 2465 2466 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); 2467 if (rf->channel <= 14) 2468 rfcsr = 0x1a; 2469 else 2470 rfcsr = 0x12; 2471 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2472 2473 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 2474 if (rf->channel >= 1 && rf->channel <= 14) 2475 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2476 else if (rf->channel >= 36 && rf->channel <= 64) 2477 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2478 else if (rf->channel >= 100 && rf->channel <= 128) 2479 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2480 else 2481 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2482 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2483 2484 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 2485 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 2486 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2487 2488 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 2489 2490 if (rf->channel <= 14) { 2491 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 2492 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 2493 } else { 2494 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8); 2495 rt2800_rfcsr_write(rt2x00dev, 13, 0x23); 2496 } 2497 2498 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr); 2499 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1); 2500 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2501 2502 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr); 2503 if (rf->channel <= 14) { 2504 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5); 2505 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3); 2506 } else { 2507 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4); 2508 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2); 2509 } 2510 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2511 2512 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); 2513 if (rf->channel <= 14) 2514 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3); 2515 else 2516 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2); 2517 2518 if (txbf_enabled) 2519 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1); 2520 2521 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2522 2523 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); 2524 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0); 2525 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2526 2527 rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr); 2528 if (rf->channel <= 14) 2529 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b); 2530 else 2531 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f); 2532 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr); 2533 2534 if (rf->channel <= 14) { 2535 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 2536 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 2537 } else { 2538 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 2539 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 2540 } 2541 2542 /* Initiate VCO calibration */ 2543 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); 2544 if (rf->channel <= 14) { 2545 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2546 } else { 2547 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1); 2548 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1); 2549 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1); 2550 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1); 2551 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1); 2552 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2553 } 2554 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2555 2556 if (rf->channel >= 1 && rf->channel <= 14) { 2557 rfcsr = 0x23; 2558 if (txbf_enabled) 2559 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2560 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2561 2562 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 2563 } else if (rf->channel >= 36 && rf->channel <= 64) { 2564 rfcsr = 0x36; 2565 if (txbf_enabled) 2566 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2567 rt2800_rfcsr_write(rt2x00dev, 39, 0x36); 2568 2569 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb); 2570 } else if (rf->channel >= 100 && rf->channel <= 128) { 2571 rfcsr = 0x32; 2572 if (txbf_enabled) 2573 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2574 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2575 2576 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3); 2577 } else { 2578 rfcsr = 0x30; 2579 if (txbf_enabled) 2580 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2581 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2582 2583 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b); 2584 } 2585 } 2586 2587 #define POWER_BOUND 0x27 2588 #define POWER_BOUND_5G 0x2b 2589 2590 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev, 2591 struct ieee80211_conf *conf, 2592 struct rf_channel *rf, 2593 struct channel_info *info) 2594 { 2595 u8 rfcsr; 2596 2597 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2598 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2599 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); 2600 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 2601 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2602 2603 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); 2604 if (info->default_power1 > POWER_BOUND) 2605 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 2606 else 2607 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2608 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2609 2610 rt2800_freq_cal_mode1(rt2x00dev); 2611 2612 if (rf->channel <= 14) { 2613 if (rf->channel == 6) 2614 rt2800_bbp_write(rt2x00dev, 68, 0x0c); 2615 else 2616 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 2617 2618 if (rf->channel >= 1 && rf->channel <= 6) 2619 rt2800_bbp_write(rt2x00dev, 59, 0x0f); 2620 else if (rf->channel >= 7 && rf->channel <= 11) 2621 rt2800_bbp_write(rt2x00dev, 59, 0x0e); 2622 else if (rf->channel >= 12 && rf->channel <= 14) 2623 rt2800_bbp_write(rt2x00dev, 59, 0x0d); 2624 } 2625 } 2626 2627 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev, 2628 struct ieee80211_conf *conf, 2629 struct rf_channel *rf, 2630 struct channel_info *info) 2631 { 2632 u8 rfcsr; 2633 2634 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2635 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2636 2637 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 2638 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 2639 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 2640 2641 if (info->default_power1 > POWER_BOUND) 2642 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND); 2643 else 2644 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1); 2645 2646 if (info->default_power2 > POWER_BOUND) 2647 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND); 2648 else 2649 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2); 2650 2651 rt2800_freq_cal_mode1(rt2x00dev); 2652 2653 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2654 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2655 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2656 2657 if ( rt2x00dev->default_ant.tx_chain_num == 2 ) 2658 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2659 else 2660 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2661 2662 if ( rt2x00dev->default_ant.rx_chain_num == 2 ) 2663 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2664 else 2665 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2666 2667 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2668 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2669 2670 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2671 2672 rt2800_rfcsr_write(rt2x00dev, 31, 80); 2673 } 2674 2675 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 2676 struct ieee80211_conf *conf, 2677 struct rf_channel *rf, 2678 struct channel_info *info) 2679 { 2680 u8 rfcsr; 2681 2682 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2683 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2684 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); 2685 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 2686 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2687 2688 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); 2689 if (info->default_power1 > POWER_BOUND) 2690 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 2691 else 2692 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2693 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2694 2695 if (rt2x00_rt(rt2x00dev, RT5392)) { 2696 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); 2697 if (info->default_power2 > POWER_BOUND) 2698 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND); 2699 else 2700 rt2x00_set_field8(&rfcsr, RFCSR50_TX, 2701 info->default_power2); 2702 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2703 } 2704 2705 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2706 if (rt2x00_rt(rt2x00dev, RT5392)) { 2707 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2708 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2709 } 2710 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2711 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2712 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2713 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2714 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2715 2716 rt2800_freq_cal_mode1(rt2x00dev); 2717 2718 if (rf->channel <= 14) { 2719 int idx = rf->channel-1; 2720 2721 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2722 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 2723 /* r55/r59 value array of channel 1~14 */ 2724 static const char r55_bt_rev[] = {0x83, 0x83, 2725 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, 2726 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; 2727 static const char r59_bt_rev[] = {0x0e, 0x0e, 2728 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, 2729 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; 2730 2731 rt2800_rfcsr_write(rt2x00dev, 55, 2732 r55_bt_rev[idx]); 2733 rt2800_rfcsr_write(rt2x00dev, 59, 2734 r59_bt_rev[idx]); 2735 } else { 2736 static const char r59_bt[] = {0x8b, 0x8b, 0x8b, 2737 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, 2738 0x88, 0x88, 0x86, 0x85, 0x84}; 2739 2740 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); 2741 } 2742 } else { 2743 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 2744 static const char r55_nonbt_rev[] = {0x23, 0x23, 2745 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, 2746 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; 2747 static const char r59_nonbt_rev[] = {0x07, 0x07, 2748 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 2749 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; 2750 2751 rt2800_rfcsr_write(rt2x00dev, 55, 2752 r55_nonbt_rev[idx]); 2753 rt2800_rfcsr_write(rt2x00dev, 59, 2754 r59_nonbt_rev[idx]); 2755 } else if (rt2x00_rt(rt2x00dev, RT5390) || 2756 rt2x00_rt(rt2x00dev, RT5392)) { 2757 static const char r59_non_bt[] = {0x8f, 0x8f, 2758 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, 2759 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; 2760 2761 rt2800_rfcsr_write(rt2x00dev, 59, 2762 r59_non_bt[idx]); 2763 } 2764 } 2765 } 2766 } 2767 2768 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, 2769 struct ieee80211_conf *conf, 2770 struct rf_channel *rf, 2771 struct channel_info *info) 2772 { 2773 u8 rfcsr, ep_reg; 2774 u32 reg; 2775 int power_bound; 2776 2777 /* TODO */ 2778 const bool is_11b = false; 2779 const bool is_type_ep = false; 2780 2781 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 2782 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 2783 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0); 2784 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 2785 2786 /* Order of values on rf_channel entry: N, K, mod, R */ 2787 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff); 2788 2789 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr); 2790 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf); 2791 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8); 2792 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2); 2793 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr); 2794 2795 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); 2796 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1); 2797 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3); 2798 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2799 2800 if (rf->channel <= 14) { 2801 rt2800_rfcsr_write(rt2x00dev, 10, 0x90); 2802 /* FIXME: RF11 owerwrite ? */ 2803 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A); 2804 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 2805 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 2806 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 2807 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A); 2808 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 2809 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 2810 rt2800_rfcsr_write(rt2x00dev, 36, 0x80); 2811 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 2812 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 2813 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B); 2814 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D); 2815 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B); 2816 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5); 2817 rt2800_rfcsr_write(rt2x00dev, 43, 0x72); 2818 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E); 2819 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2); 2820 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B); 2821 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 2822 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E); 2823 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 2824 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 2825 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1); 2826 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 2827 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 2828 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 2829 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 2830 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 2831 2832 /* TODO RF27 <- tssi */ 2833 2834 rfcsr = rf->channel <= 10 ? 0x07 : 0x06; 2835 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2836 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr); 2837 2838 if (is_11b) { 2839 /* CCK */ 2840 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8); 2841 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0); 2842 if (is_type_ep) 2843 rt2800_rfcsr_write(rt2x00dev, 55, 0x06); 2844 else 2845 rt2800_rfcsr_write(rt2x00dev, 55, 0x47); 2846 } else { 2847 /* OFDM */ 2848 if (is_type_ep) 2849 rt2800_rfcsr_write(rt2x00dev, 55, 0x03); 2850 else 2851 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 2852 } 2853 2854 power_bound = POWER_BOUND; 2855 ep_reg = 0x2; 2856 } else { 2857 rt2800_rfcsr_write(rt2x00dev, 10, 0x97); 2858 /* FIMXE: RF11 overwrite */ 2859 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 2860 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF); 2861 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 2862 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 2863 rt2800_rfcsr_write(rt2x00dev, 37, 0x04); 2864 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 2865 rt2800_rfcsr_write(rt2x00dev, 40, 0x42); 2866 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB); 2867 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7); 2868 rt2800_rfcsr_write(rt2x00dev, 45, 0x41); 2869 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 2870 rt2800_rfcsr_write(rt2x00dev, 57, 0x77); 2871 rt2800_rfcsr_write(rt2x00dev, 60, 0x05); 2872 rt2800_rfcsr_write(rt2x00dev, 61, 0x01); 2873 2874 /* TODO RF27 <- tssi */ 2875 2876 if (rf->channel >= 36 && rf->channel <= 64) { 2877 2878 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E); 2879 rt2800_rfcsr_write(rt2x00dev, 13, 0x22); 2880 rt2800_rfcsr_write(rt2x00dev, 22, 0x60); 2881 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F); 2882 if (rf->channel <= 50) 2883 rt2800_rfcsr_write(rt2x00dev, 24, 0x09); 2884 else if (rf->channel >= 52) 2885 rt2800_rfcsr_write(rt2x00dev, 24, 0x07); 2886 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C); 2887 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B); 2888 rt2800_rfcsr_write(rt2x00dev, 44, 0X40); 2889 rt2800_rfcsr_write(rt2x00dev, 46, 0X00); 2890 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE); 2891 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C); 2892 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8); 2893 if (rf->channel <= 50) { 2894 rt2800_rfcsr_write(rt2x00dev, 55, 0x06), 2895 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3); 2896 } else if (rf->channel >= 52) { 2897 rt2800_rfcsr_write(rt2x00dev, 55, 0x04); 2898 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 2899 } 2900 2901 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 2902 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F); 2903 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 2904 2905 } else if (rf->channel >= 100 && rf->channel <= 165) { 2906 2907 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E); 2908 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 2909 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 2910 if (rf->channel <= 153) { 2911 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C); 2912 rt2800_rfcsr_write(rt2x00dev, 24, 0x06); 2913 } else if (rf->channel >= 155) { 2914 rt2800_rfcsr_write(rt2x00dev, 23, 0x38); 2915 rt2800_rfcsr_write(rt2x00dev, 24, 0x05); 2916 } 2917 if (rf->channel <= 138) { 2918 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A); 2919 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B); 2920 rt2800_rfcsr_write(rt2x00dev, 44, 0x20); 2921 rt2800_rfcsr_write(rt2x00dev, 46, 0x18); 2922 } else if (rf->channel >= 140) { 2923 rt2800_rfcsr_write(rt2x00dev, 39, 0x18); 2924 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B); 2925 rt2800_rfcsr_write(rt2x00dev, 44, 0x10); 2926 rt2800_rfcsr_write(rt2x00dev, 46, 0X08); 2927 } 2928 if (rf->channel <= 124) 2929 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC); 2930 else if (rf->channel >= 126) 2931 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC); 2932 if (rf->channel <= 138) 2933 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 2934 else if (rf->channel >= 140) 2935 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 2936 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB); 2937 if (rf->channel <= 138) 2938 rt2800_rfcsr_write(rt2x00dev, 55, 0x01); 2939 else if (rf->channel >= 140) 2940 rt2800_rfcsr_write(rt2x00dev, 55, 0x00); 2941 if (rf->channel <= 128) 2942 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 2943 else if (rf->channel >= 130) 2944 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB); 2945 if (rf->channel <= 116) 2946 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D); 2947 else if (rf->channel >= 118) 2948 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 2949 if (rf->channel <= 138) 2950 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F); 2951 else if (rf->channel >= 140) 2952 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C); 2953 if (rf->channel <= 116) 2954 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D); 2955 else if (rf->channel >= 118) 2956 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 2957 } 2958 2959 power_bound = POWER_BOUND_5G; 2960 ep_reg = 0x3; 2961 } 2962 2963 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); 2964 if (info->default_power1 > power_bound) 2965 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound); 2966 else 2967 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2968 if (is_type_ep) 2969 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg); 2970 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2971 2972 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); 2973 if (info->default_power2 > power_bound) 2974 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound); 2975 else 2976 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2); 2977 if (is_type_ep) 2978 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg); 2979 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2980 2981 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2982 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2983 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2984 2985 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 2986 rt2x00dev->default_ant.tx_chain_num >= 1); 2987 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 2988 rt2x00dev->default_ant.tx_chain_num == 2); 2989 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2990 2991 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 2992 rt2x00dev->default_ant.rx_chain_num >= 1); 2993 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 2994 rt2x00dev->default_ant.rx_chain_num == 2); 2995 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2996 2997 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2998 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4); 2999 3000 if (conf_is_ht40(conf)) 3001 rt2800_rfcsr_write(rt2x00dev, 30, 0x16); 3002 else 3003 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 3004 3005 if (!is_11b) { 3006 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3007 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3008 } 3009 3010 /* TODO proper frequency adjustment */ 3011 rt2800_freq_cal_mode1(rt2x00dev); 3012 3013 /* TODO merge with others */ 3014 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); 3015 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3016 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3017 3018 /* BBP settings */ 3019 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3020 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3021 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3022 3023 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18); 3024 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08); 3025 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38); 3026 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92); 3027 3028 /* GLRT band configuration */ 3029 rt2800_bbp_write(rt2x00dev, 195, 128); 3030 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0); 3031 rt2800_bbp_write(rt2x00dev, 195, 129); 3032 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E); 3033 rt2800_bbp_write(rt2x00dev, 195, 130); 3034 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28); 3035 rt2800_bbp_write(rt2x00dev, 195, 131); 3036 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20); 3037 rt2800_bbp_write(rt2x00dev, 195, 133); 3038 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F); 3039 rt2800_bbp_write(rt2x00dev, 195, 124); 3040 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F); 3041 } 3042 3043 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, 3044 const unsigned int word, 3045 const u8 value) 3046 { 3047 u8 chain, reg; 3048 3049 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) { 3050 rt2800_bbp_read(rt2x00dev, 27, ®); 3051 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); 3052 rt2800_bbp_write(rt2x00dev, 27, reg); 3053 3054 rt2800_bbp_write(rt2x00dev, word, value); 3055 } 3056 } 3057 3058 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel) 3059 { 3060 u8 cal; 3061 3062 /* TX0 IQ Gain */ 3063 rt2800_bbp_write(rt2x00dev, 158, 0x2c); 3064 if (channel <= 14) 3065 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G); 3066 else if (channel >= 36 && channel <= 64) 3067 cal = rt2x00_eeprom_byte(rt2x00dev, 3068 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G); 3069 else if (channel >= 100 && channel <= 138) 3070 cal = rt2x00_eeprom_byte(rt2x00dev, 3071 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G); 3072 else if (channel >= 140 && channel <= 165) 3073 cal = rt2x00_eeprom_byte(rt2x00dev, 3074 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G); 3075 else 3076 cal = 0; 3077 rt2800_bbp_write(rt2x00dev, 159, cal); 3078 3079 /* TX0 IQ Phase */ 3080 rt2800_bbp_write(rt2x00dev, 158, 0x2d); 3081 if (channel <= 14) 3082 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G); 3083 else if (channel >= 36 && channel <= 64) 3084 cal = rt2x00_eeprom_byte(rt2x00dev, 3085 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G); 3086 else if (channel >= 100 && channel <= 138) 3087 cal = rt2x00_eeprom_byte(rt2x00dev, 3088 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G); 3089 else if (channel >= 140 && channel <= 165) 3090 cal = rt2x00_eeprom_byte(rt2x00dev, 3091 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G); 3092 else 3093 cal = 0; 3094 rt2800_bbp_write(rt2x00dev, 159, cal); 3095 3096 /* TX1 IQ Gain */ 3097 rt2800_bbp_write(rt2x00dev, 158, 0x4a); 3098 if (channel <= 14) 3099 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G); 3100 else if (channel >= 36 && channel <= 64) 3101 cal = rt2x00_eeprom_byte(rt2x00dev, 3102 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G); 3103 else if (channel >= 100 && channel <= 138) 3104 cal = rt2x00_eeprom_byte(rt2x00dev, 3105 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G); 3106 else if (channel >= 140 && channel <= 165) 3107 cal = rt2x00_eeprom_byte(rt2x00dev, 3108 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G); 3109 else 3110 cal = 0; 3111 rt2800_bbp_write(rt2x00dev, 159, cal); 3112 3113 /* TX1 IQ Phase */ 3114 rt2800_bbp_write(rt2x00dev, 158, 0x4b); 3115 if (channel <= 14) 3116 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G); 3117 else if (channel >= 36 && channel <= 64) 3118 cal = rt2x00_eeprom_byte(rt2x00dev, 3119 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G); 3120 else if (channel >= 100 && channel <= 138) 3121 cal = rt2x00_eeprom_byte(rt2x00dev, 3122 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G); 3123 else if (channel >= 140 && channel <= 165) 3124 cal = rt2x00_eeprom_byte(rt2x00dev, 3125 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G); 3126 else 3127 cal = 0; 3128 rt2800_bbp_write(rt2x00dev, 159, cal); 3129 3130 /* FIXME: possible RX0, RX1 callibration ? */ 3131 3132 /* RF IQ compensation control */ 3133 rt2800_bbp_write(rt2x00dev, 158, 0x04); 3134 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL); 3135 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3136 3137 /* RF IQ imbalance compensation control */ 3138 rt2800_bbp_write(rt2x00dev, 158, 0x03); 3139 cal = rt2x00_eeprom_byte(rt2x00dev, 3140 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL); 3141 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3142 } 3143 3144 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev, 3145 unsigned int channel, 3146 char txpower) 3147 { 3148 if (rt2x00_rt(rt2x00dev, RT3593)) 3149 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC); 3150 3151 if (channel <= 14) 3152 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER); 3153 3154 if (rt2x00_rt(rt2x00dev, RT3593)) 3155 return clamp_t(char, txpower, MIN_A_TXPOWER_3593, 3156 MAX_A_TXPOWER_3593); 3157 else 3158 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER); 3159 } 3160 3161 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 3162 struct ieee80211_conf *conf, 3163 struct rf_channel *rf, 3164 struct channel_info *info) 3165 { 3166 u32 reg; 3167 unsigned int tx_pin; 3168 u8 bbp, rfcsr; 3169 3170 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3171 info->default_power1); 3172 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3173 info->default_power2); 3174 if (rt2x00dev->default_ant.tx_chain_num > 2) 3175 info->default_power3 = 3176 rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3177 info->default_power3); 3178 3179 switch (rt2x00dev->chip.rf) { 3180 case RF2020: 3181 case RF3020: 3182 case RF3021: 3183 case RF3022: 3184 case RF3320: 3185 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 3186 break; 3187 case RF3052: 3188 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); 3189 break; 3190 case RF3053: 3191 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info); 3192 break; 3193 case RF3290: 3194 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info); 3195 break; 3196 case RF3322: 3197 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); 3198 break; 3199 case RF3070: 3200 case RF5360: 3201 case RF5362: 3202 case RF5370: 3203 case RF5372: 3204 case RF5390: 3205 case RF5392: 3206 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); 3207 break; 3208 case RF5592: 3209 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info); 3210 break; 3211 default: 3212 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 3213 } 3214 3215 if (rt2x00_rf(rt2x00dev, RF3070) || 3216 rt2x00_rf(rt2x00dev, RF3290) || 3217 rt2x00_rf(rt2x00dev, RF3322) || 3218 rt2x00_rf(rt2x00dev, RF5360) || 3219 rt2x00_rf(rt2x00dev, RF5362) || 3220 rt2x00_rf(rt2x00dev, RF5370) || 3221 rt2x00_rf(rt2x00dev, RF5372) || 3222 rt2x00_rf(rt2x00dev, RF5390) || 3223 rt2x00_rf(rt2x00dev, RF5392)) { 3224 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 3225 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0); 3226 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0); 3227 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 3228 3229 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); 3230 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3231 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3232 } 3233 3234 /* 3235 * Change BBP settings 3236 */ 3237 if (rt2x00_rt(rt2x00dev, RT3352)) { 3238 rt2800_bbp_write(rt2x00dev, 27, 0x0); 3239 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 3240 rt2800_bbp_write(rt2x00dev, 27, 0x20); 3241 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 3242 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 3243 if (rf->channel > 14) { 3244 /* Disable CCK Packet detection on 5GHz */ 3245 rt2800_bbp_write(rt2x00dev, 70, 0x00); 3246 } else { 3247 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 3248 } 3249 3250 if (conf_is_ht40(conf)) 3251 rt2800_bbp_write(rt2x00dev, 105, 0x04); 3252 else 3253 rt2800_bbp_write(rt2x00dev, 105, 0x34); 3254 3255 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3256 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3257 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3258 rt2800_bbp_write(rt2x00dev, 77, 0x98); 3259 } else { 3260 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3261 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3262 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3263 rt2800_bbp_write(rt2x00dev, 86, 0); 3264 } 3265 3266 if (rf->channel <= 14) { 3267 if (!rt2x00_rt(rt2x00dev, RT5390) && 3268 !rt2x00_rt(rt2x00dev, RT5392)) { 3269 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 3270 rt2800_bbp_write(rt2x00dev, 82, 0x62); 3271 rt2800_bbp_write(rt2x00dev, 75, 0x46); 3272 } else { 3273 if (rt2x00_rt(rt2x00dev, RT3593)) 3274 rt2800_bbp_write(rt2x00dev, 82, 0x62); 3275 else 3276 rt2800_bbp_write(rt2x00dev, 82, 0x84); 3277 rt2800_bbp_write(rt2x00dev, 75, 0x50); 3278 } 3279 if (rt2x00_rt(rt2x00dev, RT3593)) 3280 rt2800_bbp_write(rt2x00dev, 83, 0x8a); 3281 } 3282 3283 } else { 3284 if (rt2x00_rt(rt2x00dev, RT3572)) 3285 rt2800_bbp_write(rt2x00dev, 82, 0x94); 3286 else if (rt2x00_rt(rt2x00dev, RT3593)) 3287 rt2800_bbp_write(rt2x00dev, 82, 0x82); 3288 else 3289 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 3290 3291 if (rt2x00_rt(rt2x00dev, RT3593)) 3292 rt2800_bbp_write(rt2x00dev, 83, 0x9a); 3293 3294 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) 3295 rt2800_bbp_write(rt2x00dev, 75, 0x46); 3296 else 3297 rt2800_bbp_write(rt2x00dev, 75, 0x50); 3298 } 3299 3300 rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®); 3301 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); 3302 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); 3303 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); 3304 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); 3305 3306 if (rt2x00_rt(rt2x00dev, RT3572)) 3307 rt2800_rfcsr_write(rt2x00dev, 8, 0); 3308 3309 tx_pin = 0; 3310 3311 switch (rt2x00dev->default_ant.tx_chain_num) { 3312 case 3: 3313 /* Turn on tertiary PAs */ 3314 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 3315 rf->channel > 14); 3316 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 3317 rf->channel <= 14); 3318 /* fall-through */ 3319 case 2: 3320 /* Turn on secondary PAs */ 3321 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 3322 rf->channel > 14); 3323 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 3324 rf->channel <= 14); 3325 /* fall-through */ 3326 case 1: 3327 /* Turn on primary PAs */ 3328 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 3329 rf->channel > 14); 3330 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) 3331 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 3332 else 3333 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 3334 rf->channel <= 14); 3335 break; 3336 } 3337 3338 switch (rt2x00dev->default_ant.rx_chain_num) { 3339 case 3: 3340 /* Turn on tertiary LNAs */ 3341 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1); 3342 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1); 3343 /* fall-through */ 3344 case 2: 3345 /* Turn on secondary LNAs */ 3346 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); 3347 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); 3348 /* fall-through */ 3349 case 1: 3350 /* Turn on primary LNAs */ 3351 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); 3352 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); 3353 break; 3354 } 3355 3356 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); 3357 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); 3358 3359 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 3360 3361 if (rt2x00_rt(rt2x00dev, RT3572)) { 3362 rt2800_rfcsr_write(rt2x00dev, 8, 0x80); 3363 3364 /* AGC init */ 3365 if (rf->channel <= 14) 3366 reg = 0x1c + (2 * rt2x00dev->lna_gain); 3367 else 3368 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 3369 3370 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3371 } 3372 3373 if (rt2x00_rt(rt2x00dev, RT3593)) { 3374 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 3375 3376 /* Band selection */ 3377 if (rt2x00_is_usb(rt2x00dev) || 3378 rt2x00_is_pcie(rt2x00dev)) { 3379 /* GPIO #8 controls all paths */ 3380 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); 3381 if (rf->channel <= 14) 3382 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); 3383 else 3384 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); 3385 } 3386 3387 /* LNA PE control. */ 3388 if (rt2x00_is_usb(rt2x00dev)) { 3389 /* GPIO #4 controls PE0 and PE1, 3390 * GPIO #7 controls PE2 3391 */ 3392 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 3393 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 3394 3395 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 3396 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 3397 } else if (rt2x00_is_pcie(rt2x00dev)) { 3398 /* GPIO #4 controls PE0, PE1 and PE2 */ 3399 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 3400 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 3401 } 3402 3403 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 3404 3405 /* AGC init */ 3406 if (rf->channel <= 14) 3407 reg = 0x1c + 2 * rt2x00dev->lna_gain; 3408 else 3409 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 3410 3411 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3412 3413 usleep_range(1000, 1500); 3414 } 3415 3416 if (rt2x00_rt(rt2x00dev, RT5592)) { 3417 rt2800_bbp_write(rt2x00dev, 195, 141); 3418 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a); 3419 3420 /* AGC init */ 3421 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain; 3422 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3423 3424 rt2800_iq_calibrate(rt2x00dev, rf->channel); 3425 } 3426 3427 rt2800_bbp_read(rt2x00dev, 4, &bbp); 3428 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 3429 rt2800_bbp_write(rt2x00dev, 4, bbp); 3430 3431 rt2800_bbp_read(rt2x00dev, 3, &bbp); 3432 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); 3433 rt2800_bbp_write(rt2x00dev, 3, bbp); 3434 3435 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 3436 if (conf_is_ht40(conf)) { 3437 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 3438 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 3439 rt2800_bbp_write(rt2x00dev, 73, 0x16); 3440 } else { 3441 rt2800_bbp_write(rt2x00dev, 69, 0x16); 3442 rt2800_bbp_write(rt2x00dev, 70, 0x08); 3443 rt2800_bbp_write(rt2x00dev, 73, 0x11); 3444 } 3445 } 3446 3447 usleep_range(1000, 1500); 3448 3449 /* 3450 * Clear channel statistic counters 3451 */ 3452 rt2800_register_read(rt2x00dev, CH_IDLE_STA, ®); 3453 rt2800_register_read(rt2x00dev, CH_BUSY_STA, ®); 3454 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, ®); 3455 3456 /* 3457 * Clear update flag 3458 */ 3459 if (rt2x00_rt(rt2x00dev, RT3352)) { 3460 rt2800_bbp_read(rt2x00dev, 49, &bbp); 3461 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0); 3462 rt2800_bbp_write(rt2x00dev, 49, bbp); 3463 } 3464 } 3465 3466 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) 3467 { 3468 u8 tssi_bounds[9]; 3469 u8 current_tssi; 3470 u16 eeprom; 3471 u8 step; 3472 int i; 3473 3474 /* 3475 * First check if temperature compensation is supported. 3476 */ 3477 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); 3478 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC)) 3479 return 0; 3480 3481 /* 3482 * Read TSSI boundaries for temperature compensation from 3483 * the EEPROM. 3484 * 3485 * Array idx 0 1 2 3 4 5 6 7 8 3486 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4 3487 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 3488 */ 3489 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 3490 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom); 3491 tssi_bounds[0] = rt2x00_get_field16(eeprom, 3492 EEPROM_TSSI_BOUND_BG1_MINUS4); 3493 tssi_bounds[1] = rt2x00_get_field16(eeprom, 3494 EEPROM_TSSI_BOUND_BG1_MINUS3); 3495 3496 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom); 3497 tssi_bounds[2] = rt2x00_get_field16(eeprom, 3498 EEPROM_TSSI_BOUND_BG2_MINUS2); 3499 tssi_bounds[3] = rt2x00_get_field16(eeprom, 3500 EEPROM_TSSI_BOUND_BG2_MINUS1); 3501 3502 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom); 3503 tssi_bounds[4] = rt2x00_get_field16(eeprom, 3504 EEPROM_TSSI_BOUND_BG3_REF); 3505 tssi_bounds[5] = rt2x00_get_field16(eeprom, 3506 EEPROM_TSSI_BOUND_BG3_PLUS1); 3507 3508 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom); 3509 tssi_bounds[6] = rt2x00_get_field16(eeprom, 3510 EEPROM_TSSI_BOUND_BG4_PLUS2); 3511 tssi_bounds[7] = rt2x00_get_field16(eeprom, 3512 EEPROM_TSSI_BOUND_BG4_PLUS3); 3513 3514 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom); 3515 tssi_bounds[8] = rt2x00_get_field16(eeprom, 3516 EEPROM_TSSI_BOUND_BG5_PLUS4); 3517 3518 step = rt2x00_get_field16(eeprom, 3519 EEPROM_TSSI_BOUND_BG5_AGC_STEP); 3520 } else { 3521 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom); 3522 tssi_bounds[0] = rt2x00_get_field16(eeprom, 3523 EEPROM_TSSI_BOUND_A1_MINUS4); 3524 tssi_bounds[1] = rt2x00_get_field16(eeprom, 3525 EEPROM_TSSI_BOUND_A1_MINUS3); 3526 3527 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom); 3528 tssi_bounds[2] = rt2x00_get_field16(eeprom, 3529 EEPROM_TSSI_BOUND_A2_MINUS2); 3530 tssi_bounds[3] = rt2x00_get_field16(eeprom, 3531 EEPROM_TSSI_BOUND_A2_MINUS1); 3532 3533 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom); 3534 tssi_bounds[4] = rt2x00_get_field16(eeprom, 3535 EEPROM_TSSI_BOUND_A3_REF); 3536 tssi_bounds[5] = rt2x00_get_field16(eeprom, 3537 EEPROM_TSSI_BOUND_A3_PLUS1); 3538 3539 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom); 3540 tssi_bounds[6] = rt2x00_get_field16(eeprom, 3541 EEPROM_TSSI_BOUND_A4_PLUS2); 3542 tssi_bounds[7] = rt2x00_get_field16(eeprom, 3543 EEPROM_TSSI_BOUND_A4_PLUS3); 3544 3545 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom); 3546 tssi_bounds[8] = rt2x00_get_field16(eeprom, 3547 EEPROM_TSSI_BOUND_A5_PLUS4); 3548 3549 step = rt2x00_get_field16(eeprom, 3550 EEPROM_TSSI_BOUND_A5_AGC_STEP); 3551 } 3552 3553 /* 3554 * Check if temperature compensation is supported. 3555 */ 3556 if (tssi_bounds[4] == 0xff || step == 0xff) 3557 return 0; 3558 3559 /* 3560 * Read current TSSI (BBP 49). 3561 */ 3562 rt2800_bbp_read(rt2x00dev, 49, ¤t_tssi); 3563 3564 /* 3565 * Compare TSSI value (BBP49) with the compensation boundaries 3566 * from the EEPROM and increase or decrease tx power. 3567 */ 3568 for (i = 0; i <= 3; i++) { 3569 if (current_tssi > tssi_bounds[i]) 3570 break; 3571 } 3572 3573 if (i == 4) { 3574 for (i = 8; i >= 5; i--) { 3575 if (current_tssi < tssi_bounds[i]) 3576 break; 3577 } 3578 } 3579 3580 return (i - 4) * step; 3581 } 3582 3583 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, 3584 enum nl80211_band band) 3585 { 3586 u16 eeprom; 3587 u8 comp_en; 3588 u8 comp_type; 3589 int comp_value = 0; 3590 3591 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom); 3592 3593 /* 3594 * HT40 compensation not required. 3595 */ 3596 if (eeprom == 0xffff || 3597 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 3598 return 0; 3599 3600 if (band == NL80211_BAND_2GHZ) { 3601 comp_en = rt2x00_get_field16(eeprom, 3602 EEPROM_TXPOWER_DELTA_ENABLE_2G); 3603 if (comp_en) { 3604 comp_type = rt2x00_get_field16(eeprom, 3605 EEPROM_TXPOWER_DELTA_TYPE_2G); 3606 comp_value = rt2x00_get_field16(eeprom, 3607 EEPROM_TXPOWER_DELTA_VALUE_2G); 3608 if (!comp_type) 3609 comp_value = -comp_value; 3610 } 3611 } else { 3612 comp_en = rt2x00_get_field16(eeprom, 3613 EEPROM_TXPOWER_DELTA_ENABLE_5G); 3614 if (comp_en) { 3615 comp_type = rt2x00_get_field16(eeprom, 3616 EEPROM_TXPOWER_DELTA_TYPE_5G); 3617 comp_value = rt2x00_get_field16(eeprom, 3618 EEPROM_TXPOWER_DELTA_VALUE_5G); 3619 if (!comp_type) 3620 comp_value = -comp_value; 3621 } 3622 } 3623 3624 return comp_value; 3625 } 3626 3627 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev, 3628 int power_level, int max_power) 3629 { 3630 int delta; 3631 3632 if (rt2x00_has_cap_power_limit(rt2x00dev)) 3633 return 0; 3634 3635 /* 3636 * XXX: We don't know the maximum transmit power of our hardware since 3637 * the EEPROM doesn't expose it. We only know that we are calibrated 3638 * to 100% tx power. 3639 * 3640 * Hence, we assume the regulatory limit that cfg80211 calulated for 3641 * the current channel is our maximum and if we are requested to lower 3642 * the value we just reduce our tx power accordingly. 3643 */ 3644 delta = power_level - max_power; 3645 return min(delta, 0); 3646 } 3647 3648 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, 3649 enum nl80211_band band, int power_level, 3650 u8 txpower, int delta) 3651 { 3652 u16 eeprom; 3653 u8 criterion; 3654 u8 eirp_txpower; 3655 u8 eirp_txpower_criterion; 3656 u8 reg_limit; 3657 3658 if (rt2x00_rt(rt2x00dev, RT3593)) 3659 return min_t(u8, txpower, 0xc); 3660 3661 if (rt2x00_has_cap_power_limit(rt2x00dev)) { 3662 /* 3663 * Check if eirp txpower exceed txpower_limit. 3664 * We use OFDM 6M as criterion and its eirp txpower 3665 * is stored at EEPROM_EIRP_MAX_TX_POWER. 3666 * .11b data rate need add additional 4dbm 3667 * when calculating eirp txpower. 3668 */ 3669 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3670 1, &eeprom); 3671 criterion = rt2x00_get_field16(eeprom, 3672 EEPROM_TXPOWER_BYRATE_RATE0); 3673 3674 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, 3675 &eeprom); 3676 3677 if (band == NL80211_BAND_2GHZ) 3678 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 3679 EEPROM_EIRP_MAX_TX_POWER_2GHZ); 3680 else 3681 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 3682 EEPROM_EIRP_MAX_TX_POWER_5GHZ); 3683 3684 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) + 3685 (is_rate_b ? 4 : 0) + delta; 3686 3687 reg_limit = (eirp_txpower > power_level) ? 3688 (eirp_txpower - power_level) : 0; 3689 } else 3690 reg_limit = 0; 3691 3692 txpower = max(0, txpower + delta - reg_limit); 3693 return min_t(u8, txpower, 0xc); 3694 } 3695 3696 3697 enum { 3698 TX_PWR_CFG_0_IDX, 3699 TX_PWR_CFG_1_IDX, 3700 TX_PWR_CFG_2_IDX, 3701 TX_PWR_CFG_3_IDX, 3702 TX_PWR_CFG_4_IDX, 3703 TX_PWR_CFG_5_IDX, 3704 TX_PWR_CFG_6_IDX, 3705 TX_PWR_CFG_7_IDX, 3706 TX_PWR_CFG_8_IDX, 3707 TX_PWR_CFG_9_IDX, 3708 TX_PWR_CFG_0_EXT_IDX, 3709 TX_PWR_CFG_1_EXT_IDX, 3710 TX_PWR_CFG_2_EXT_IDX, 3711 TX_PWR_CFG_3_EXT_IDX, 3712 TX_PWR_CFG_4_EXT_IDX, 3713 TX_PWR_CFG_IDX_COUNT, 3714 }; 3715 3716 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, 3717 struct ieee80211_channel *chan, 3718 int power_level) 3719 { 3720 u8 txpower; 3721 u16 eeprom; 3722 u32 regs[TX_PWR_CFG_IDX_COUNT]; 3723 unsigned int offset; 3724 enum nl80211_band band = chan->band; 3725 int delta; 3726 int i; 3727 3728 memset(regs, '\0', sizeof(regs)); 3729 3730 /* TODO: adapt TX power reduction from the rt28xx code */ 3731 3732 /* calculate temperature compensation delta */ 3733 delta = rt2800_get_gain_calibration_delta(rt2x00dev); 3734 3735 if (band == NL80211_BAND_5GHZ) 3736 offset = 16; 3737 else 3738 offset = 0; 3739 3740 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 3741 offset += 8; 3742 3743 /* read the next four txpower values */ 3744 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3745 offset, &eeprom); 3746 3747 /* CCK 1MBS,2MBS */ 3748 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 3749 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 3750 txpower, delta); 3751 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3752 TX_PWR_CFG_0_CCK1_CH0, txpower); 3753 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3754 TX_PWR_CFG_0_CCK1_CH1, txpower); 3755 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 3756 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower); 3757 3758 /* CCK 5.5MBS,11MBS */ 3759 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 3760 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 3761 txpower, delta); 3762 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3763 TX_PWR_CFG_0_CCK5_CH0, txpower); 3764 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3765 TX_PWR_CFG_0_CCK5_CH1, txpower); 3766 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 3767 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower); 3768 3769 /* OFDM 6MBS,9MBS */ 3770 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 3771 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3772 txpower, delta); 3773 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3774 TX_PWR_CFG_0_OFDM6_CH0, txpower); 3775 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3776 TX_PWR_CFG_0_OFDM6_CH1, txpower); 3777 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 3778 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower); 3779 3780 /* OFDM 12MBS,18MBS */ 3781 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 3782 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3783 txpower, delta); 3784 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3785 TX_PWR_CFG_0_OFDM12_CH0, txpower); 3786 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3787 TX_PWR_CFG_0_OFDM12_CH1, txpower); 3788 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 3789 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower); 3790 3791 /* read the next four txpower values */ 3792 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3793 offset + 1, &eeprom); 3794 3795 /* OFDM 24MBS,36MBS */ 3796 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 3797 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3798 txpower, delta); 3799 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3800 TX_PWR_CFG_1_OFDM24_CH0, txpower); 3801 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3802 TX_PWR_CFG_1_OFDM24_CH1, txpower); 3803 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 3804 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower); 3805 3806 /* OFDM 48MBS */ 3807 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 3808 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3809 txpower, delta); 3810 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3811 TX_PWR_CFG_1_OFDM48_CH0, txpower); 3812 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3813 TX_PWR_CFG_1_OFDM48_CH1, txpower); 3814 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 3815 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower); 3816 3817 /* OFDM 54MBS */ 3818 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 3819 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3820 txpower, delta); 3821 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3822 TX_PWR_CFG_7_OFDM54_CH0, txpower); 3823 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3824 TX_PWR_CFG_7_OFDM54_CH1, txpower); 3825 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3826 TX_PWR_CFG_7_OFDM54_CH2, txpower); 3827 3828 /* read the next four txpower values */ 3829 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3830 offset + 2, &eeprom); 3831 3832 /* MCS 0,1 */ 3833 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 3834 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3835 txpower, delta); 3836 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3837 TX_PWR_CFG_1_MCS0_CH0, txpower); 3838 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3839 TX_PWR_CFG_1_MCS0_CH1, txpower); 3840 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 3841 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower); 3842 3843 /* MCS 2,3 */ 3844 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 3845 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3846 txpower, delta); 3847 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3848 TX_PWR_CFG_1_MCS2_CH0, txpower); 3849 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3850 TX_PWR_CFG_1_MCS2_CH1, txpower); 3851 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 3852 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower); 3853 3854 /* MCS 4,5 */ 3855 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 3856 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3857 txpower, delta); 3858 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3859 TX_PWR_CFG_2_MCS4_CH0, txpower); 3860 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3861 TX_PWR_CFG_2_MCS4_CH1, txpower); 3862 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 3863 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower); 3864 3865 /* MCS 6 */ 3866 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 3867 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3868 txpower, delta); 3869 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3870 TX_PWR_CFG_2_MCS6_CH0, txpower); 3871 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3872 TX_PWR_CFG_2_MCS6_CH1, txpower); 3873 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 3874 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower); 3875 3876 /* read the next four txpower values */ 3877 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3878 offset + 3, &eeprom); 3879 3880 /* MCS 7 */ 3881 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 3882 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3883 txpower, delta); 3884 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3885 TX_PWR_CFG_7_MCS7_CH0, txpower); 3886 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3887 TX_PWR_CFG_7_MCS7_CH1, txpower); 3888 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3889 TX_PWR_CFG_7_MCS7_CH2, txpower); 3890 3891 /* MCS 8,9 */ 3892 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 3893 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3894 txpower, delta); 3895 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3896 TX_PWR_CFG_2_MCS8_CH0, txpower); 3897 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3898 TX_PWR_CFG_2_MCS8_CH1, txpower); 3899 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 3900 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower); 3901 3902 /* MCS 10,11 */ 3903 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 3904 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3905 txpower, delta); 3906 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3907 TX_PWR_CFG_2_MCS10_CH0, txpower); 3908 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3909 TX_PWR_CFG_2_MCS10_CH1, txpower); 3910 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 3911 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower); 3912 3913 /* MCS 12,13 */ 3914 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 3915 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3916 txpower, delta); 3917 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 3918 TX_PWR_CFG_3_MCS12_CH0, txpower); 3919 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 3920 TX_PWR_CFG_3_MCS12_CH1, txpower); 3921 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 3922 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower); 3923 3924 /* read the next four txpower values */ 3925 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3926 offset + 4, &eeprom); 3927 3928 /* MCS 14 */ 3929 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 3930 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3931 txpower, delta); 3932 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 3933 TX_PWR_CFG_3_MCS14_CH0, txpower); 3934 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 3935 TX_PWR_CFG_3_MCS14_CH1, txpower); 3936 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 3937 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower); 3938 3939 /* MCS 15 */ 3940 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 3941 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3942 txpower, delta); 3943 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 3944 TX_PWR_CFG_8_MCS15_CH0, txpower); 3945 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 3946 TX_PWR_CFG_8_MCS15_CH1, txpower); 3947 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 3948 TX_PWR_CFG_8_MCS15_CH2, txpower); 3949 3950 /* MCS 16,17 */ 3951 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 3952 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3953 txpower, delta); 3954 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3955 TX_PWR_CFG_5_MCS16_CH0, txpower); 3956 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3957 TX_PWR_CFG_5_MCS16_CH1, txpower); 3958 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3959 TX_PWR_CFG_5_MCS16_CH2, txpower); 3960 3961 /* MCS 18,19 */ 3962 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 3963 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3964 txpower, delta); 3965 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3966 TX_PWR_CFG_5_MCS18_CH0, txpower); 3967 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3968 TX_PWR_CFG_5_MCS18_CH1, txpower); 3969 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3970 TX_PWR_CFG_5_MCS18_CH2, txpower); 3971 3972 /* read the next four txpower values */ 3973 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3974 offset + 5, &eeprom); 3975 3976 /* MCS 20,21 */ 3977 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 3978 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3979 txpower, delta); 3980 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 3981 TX_PWR_CFG_6_MCS20_CH0, txpower); 3982 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 3983 TX_PWR_CFG_6_MCS20_CH1, txpower); 3984 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 3985 TX_PWR_CFG_6_MCS20_CH2, txpower); 3986 3987 /* MCS 22 */ 3988 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 3989 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3990 txpower, delta); 3991 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 3992 TX_PWR_CFG_6_MCS22_CH0, txpower); 3993 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 3994 TX_PWR_CFG_6_MCS22_CH1, txpower); 3995 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 3996 TX_PWR_CFG_6_MCS22_CH2, txpower); 3997 3998 /* MCS 23 */ 3999 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4000 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4001 txpower, delta); 4002 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4003 TX_PWR_CFG_8_MCS23_CH0, txpower); 4004 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4005 TX_PWR_CFG_8_MCS23_CH1, txpower); 4006 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4007 TX_PWR_CFG_8_MCS23_CH2, txpower); 4008 4009 /* read the next four txpower values */ 4010 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4011 offset + 6, &eeprom); 4012 4013 /* STBC, MCS 0,1 */ 4014 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4015 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4016 txpower, delta); 4017 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4018 TX_PWR_CFG_3_STBC0_CH0, txpower); 4019 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4020 TX_PWR_CFG_3_STBC0_CH1, txpower); 4021 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4022 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower); 4023 4024 /* STBC, MCS 2,3 */ 4025 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4026 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4027 txpower, delta); 4028 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4029 TX_PWR_CFG_3_STBC2_CH0, txpower); 4030 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4031 TX_PWR_CFG_3_STBC2_CH1, txpower); 4032 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4033 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower); 4034 4035 /* STBC, MCS 4,5 */ 4036 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4037 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4038 txpower, delta); 4039 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); 4040 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); 4041 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, 4042 txpower); 4043 4044 /* STBC, MCS 6 */ 4045 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4046 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4047 txpower, delta); 4048 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); 4049 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); 4050 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, 4051 txpower); 4052 4053 /* read the next four txpower values */ 4054 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4055 offset + 7, &eeprom); 4056 4057 /* STBC, MCS 7 */ 4058 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4059 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4060 txpower, delta); 4061 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4062 TX_PWR_CFG_9_STBC7_CH0, txpower); 4063 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4064 TX_PWR_CFG_9_STBC7_CH1, txpower); 4065 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4066 TX_PWR_CFG_9_STBC7_CH2, txpower); 4067 4068 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]); 4069 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]); 4070 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]); 4071 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]); 4072 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]); 4073 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]); 4074 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]); 4075 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]); 4076 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]); 4077 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]); 4078 4079 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT, 4080 regs[TX_PWR_CFG_0_EXT_IDX]); 4081 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT, 4082 regs[TX_PWR_CFG_1_EXT_IDX]); 4083 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT, 4084 regs[TX_PWR_CFG_2_EXT_IDX]); 4085 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT, 4086 regs[TX_PWR_CFG_3_EXT_IDX]); 4087 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT, 4088 regs[TX_PWR_CFG_4_EXT_IDX]); 4089 4090 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++) 4091 rt2x00_dbg(rt2x00dev, 4092 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n", 4093 (band == NL80211_BAND_5GHZ) ? '5' : '2', 4094 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ? 4095 '4' : '2', 4096 (i > TX_PWR_CFG_9_IDX) ? 4097 (i - TX_PWR_CFG_9_IDX - 1) : i, 4098 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "", 4099 (unsigned long) regs[i]); 4100 } 4101 4102 /* 4103 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and 4104 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values, 4105 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power 4106 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm. 4107 * Reference per rate transmit power values are located in the EEPROM at 4108 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to 4109 * current conditions (i.e. band, bandwidth, temperature, user settings). 4110 */ 4111 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, 4112 struct ieee80211_channel *chan, 4113 int power_level) 4114 { 4115 u8 txpower, r1; 4116 u16 eeprom; 4117 u32 reg, offset; 4118 int i, is_rate_b, delta, power_ctrl; 4119 enum nl80211_band band = chan->band; 4120 4121 /* 4122 * Calculate HT40 compensation. For 40MHz we need to add or subtract 4123 * value read from EEPROM (different for 2GHz and for 5GHz). 4124 */ 4125 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 4126 4127 /* 4128 * Calculate temperature compensation. Depends on measurement of current 4129 * TSSI (Transmitter Signal Strength Indication) we know TX power (due 4130 * to temperature or maybe other factors) is smaller or bigger than 4131 * expected. We adjust it, based on TSSI reference and boundaries values 4132 * provided in EEPROM. 4133 */ 4134 switch (rt2x00dev->chip.rt) { 4135 case RT2860: 4136 case RT2872: 4137 case RT2883: 4138 case RT3070: 4139 case RT3071: 4140 case RT3090: 4141 case RT3572: 4142 delta += rt2800_get_gain_calibration_delta(rt2x00dev); 4143 break; 4144 default: 4145 /* TODO: temperature compensation code for other chips. */ 4146 break; 4147 } 4148 4149 /* 4150 * Decrease power according to user settings, on devices with unknown 4151 * maximum tx power. For other devices we take user power_level into 4152 * consideration on rt2800_compensate_txpower(). 4153 */ 4154 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level, 4155 chan->max_power); 4156 4157 /* 4158 * BBP_R1 controls TX power for all rates, it allow to set the following 4159 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively. 4160 * 4161 * TODO: we do not use +6 dBm option to do not increase power beyond 4162 * regulatory limit, however this could be utilized for devices with 4163 * CAPABILITY_POWER_LIMIT. 4164 */ 4165 if (delta <= -12) { 4166 power_ctrl = 2; 4167 delta += 12; 4168 } else if (delta <= -6) { 4169 power_ctrl = 1; 4170 delta += 6; 4171 } else { 4172 power_ctrl = 0; 4173 } 4174 rt2800_bbp_read(rt2x00dev, 1, &r1); 4175 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl); 4176 rt2800_bbp_write(rt2x00dev, 1, r1); 4177 4178 offset = TX_PWR_CFG_0; 4179 4180 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { 4181 /* just to be safe */ 4182 if (offset > TX_PWR_CFG_4) 4183 break; 4184 4185 rt2800_register_read(rt2x00dev, offset, ®); 4186 4187 /* read the next four txpower values */ 4188 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4189 i, &eeprom); 4190 4191 is_rate_b = i ? 0 : 1; 4192 /* 4193 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, 4194 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, 4195 * TX_PWR_CFG_4: unknown 4196 */ 4197 txpower = rt2x00_get_field16(eeprom, 4198 EEPROM_TXPOWER_BYRATE_RATE0); 4199 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4200 power_level, txpower, delta); 4201 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); 4202 4203 /* 4204 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, 4205 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, 4206 * TX_PWR_CFG_4: unknown 4207 */ 4208 txpower = rt2x00_get_field16(eeprom, 4209 EEPROM_TXPOWER_BYRATE_RATE1); 4210 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4211 power_level, txpower, delta); 4212 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); 4213 4214 /* 4215 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS, 4216 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, 4217 * TX_PWR_CFG_4: unknown 4218 */ 4219 txpower = rt2x00_get_field16(eeprom, 4220 EEPROM_TXPOWER_BYRATE_RATE2); 4221 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4222 power_level, txpower, delta); 4223 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); 4224 4225 /* 4226 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, 4227 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, 4228 * TX_PWR_CFG_4: unknown 4229 */ 4230 txpower = rt2x00_get_field16(eeprom, 4231 EEPROM_TXPOWER_BYRATE_RATE3); 4232 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4233 power_level, txpower, delta); 4234 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); 4235 4236 /* read the next four txpower values */ 4237 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4238 i + 1, &eeprom); 4239 4240 is_rate_b = 0; 4241 /* 4242 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, 4243 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, 4244 * TX_PWR_CFG_4: unknown 4245 */ 4246 txpower = rt2x00_get_field16(eeprom, 4247 EEPROM_TXPOWER_BYRATE_RATE0); 4248 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4249 power_level, txpower, delta); 4250 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); 4251 4252 /* 4253 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, 4254 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, 4255 * TX_PWR_CFG_4: unknown 4256 */ 4257 txpower = rt2x00_get_field16(eeprom, 4258 EEPROM_TXPOWER_BYRATE_RATE1); 4259 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4260 power_level, txpower, delta); 4261 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); 4262 4263 /* 4264 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, 4265 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, 4266 * TX_PWR_CFG_4: unknown 4267 */ 4268 txpower = rt2x00_get_field16(eeprom, 4269 EEPROM_TXPOWER_BYRATE_RATE2); 4270 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4271 power_level, txpower, delta); 4272 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); 4273 4274 /* 4275 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, 4276 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, 4277 * TX_PWR_CFG_4: unknown 4278 */ 4279 txpower = rt2x00_get_field16(eeprom, 4280 EEPROM_TXPOWER_BYRATE_RATE3); 4281 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4282 power_level, txpower, delta); 4283 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); 4284 4285 rt2800_register_write(rt2x00dev, offset, reg); 4286 4287 /* next TX_PWR_CFG register */ 4288 offset += 4; 4289 } 4290 } 4291 4292 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, 4293 struct ieee80211_channel *chan, 4294 int power_level) 4295 { 4296 if (rt2x00_rt(rt2x00dev, RT3593)) 4297 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level); 4298 else 4299 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level); 4300 } 4301 4302 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) 4303 { 4304 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan, 4305 rt2x00dev->tx_power); 4306 } 4307 EXPORT_SYMBOL_GPL(rt2800_gain_calibration); 4308 4309 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) 4310 { 4311 u32 tx_pin; 4312 u8 rfcsr; 4313 4314 /* 4315 * A voltage-controlled oscillator(VCO) is an electronic oscillator 4316 * designed to be controlled in oscillation frequency by a voltage 4317 * input. Maybe the temperature will affect the frequency of 4318 * oscillation to be shifted. The VCO calibration will be called 4319 * periodically to adjust the frequency to be precision. 4320 */ 4321 4322 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin); 4323 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE; 4324 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 4325 4326 switch (rt2x00dev->chip.rf) { 4327 case RF2020: 4328 case RF3020: 4329 case RF3021: 4330 case RF3022: 4331 case RF3320: 4332 case RF3052: 4333 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); 4334 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 4335 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 4336 break; 4337 case RF3053: 4338 case RF3070: 4339 case RF3290: 4340 case RF5360: 4341 case RF5362: 4342 case RF5370: 4343 case RF5372: 4344 case RF5390: 4345 case RF5392: 4346 case RF5592: 4347 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); 4348 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 4349 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 4350 break; 4351 default: 4352 WARN_ONCE(1, "Not supported RF chipet %x for VCO recalibration", 4353 rt2x00dev->chip.rf); 4354 return; 4355 } 4356 4357 usleep_range(1000, 1500); 4358 4359 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin); 4360 if (rt2x00dev->rf_channel <= 14) { 4361 switch (rt2x00dev->default_ant.tx_chain_num) { 4362 case 3: 4363 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); 4364 /* fall through */ 4365 case 2: 4366 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 4367 /* fall through */ 4368 case 1: 4369 default: 4370 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 4371 break; 4372 } 4373 } else { 4374 switch (rt2x00dev->default_ant.tx_chain_num) { 4375 case 3: 4376 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); 4377 /* fall through */ 4378 case 2: 4379 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 4380 /* fall through */ 4381 case 1: 4382 default: 4383 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); 4384 break; 4385 } 4386 } 4387 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 4388 4389 } 4390 EXPORT_SYMBOL_GPL(rt2800_vco_calibration); 4391 4392 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, 4393 struct rt2x00lib_conf *libconf) 4394 { 4395 u32 reg; 4396 4397 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); 4398 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 4399 libconf->conf->short_frame_max_tx_count); 4400 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 4401 libconf->conf->long_frame_max_tx_count); 4402 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 4403 } 4404 4405 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, 4406 struct rt2x00lib_conf *libconf) 4407 { 4408 enum dev_state state = 4409 (libconf->conf->flags & IEEE80211_CONF_PS) ? 4410 STATE_SLEEP : STATE_AWAKE; 4411 u32 reg; 4412 4413 if (state == STATE_SLEEP) { 4414 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); 4415 4416 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); 4417 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); 4418 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 4419 libconf->conf->listen_interval - 1); 4420 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); 4421 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 4422 4423 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 4424 } else { 4425 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); 4426 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 4427 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 4428 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); 4429 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 4430 4431 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 4432 } 4433 } 4434 4435 void rt2800_config(struct rt2x00_dev *rt2x00dev, 4436 struct rt2x00lib_conf *libconf, 4437 const unsigned int flags) 4438 { 4439 /* Always recalculate LNA gain before changing configuration */ 4440 rt2800_config_lna_gain(rt2x00dev, libconf); 4441 4442 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { 4443 rt2800_config_channel(rt2x00dev, libconf->conf, 4444 &libconf->rf, &libconf->channel); 4445 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 4446 libconf->conf->power_level); 4447 } 4448 if (flags & IEEE80211_CONF_CHANGE_POWER) 4449 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 4450 libconf->conf->power_level); 4451 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 4452 rt2800_config_retry_limit(rt2x00dev, libconf); 4453 if (flags & IEEE80211_CONF_CHANGE_PS) 4454 rt2800_config_ps(rt2x00dev, libconf); 4455 } 4456 EXPORT_SYMBOL_GPL(rt2800_config); 4457 4458 /* 4459 * Link tuning 4460 */ 4461 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 4462 { 4463 u32 reg; 4464 4465 /* 4466 * Update FCS error count from register. 4467 */ 4468 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); 4469 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); 4470 } 4471 EXPORT_SYMBOL_GPL(rt2800_link_stats); 4472 4473 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 4474 { 4475 u8 vgc; 4476 4477 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 4478 if (rt2x00_rt(rt2x00dev, RT3070) || 4479 rt2x00_rt(rt2x00dev, RT3071) || 4480 rt2x00_rt(rt2x00dev, RT3090) || 4481 rt2x00_rt(rt2x00dev, RT3290) || 4482 rt2x00_rt(rt2x00dev, RT3390) || 4483 rt2x00_rt(rt2x00dev, RT3572) || 4484 rt2x00_rt(rt2x00dev, RT3593) || 4485 rt2x00_rt(rt2x00dev, RT5390) || 4486 rt2x00_rt(rt2x00dev, RT5392) || 4487 rt2x00_rt(rt2x00dev, RT5592)) 4488 vgc = 0x1c + (2 * rt2x00dev->lna_gain); 4489 else 4490 vgc = 0x2e + rt2x00dev->lna_gain; 4491 } else { /* 5GHZ band */ 4492 if (rt2x00_rt(rt2x00dev, RT3593)) 4493 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3; 4494 else if (rt2x00_rt(rt2x00dev, RT5592)) 4495 vgc = 0x24 + (2 * rt2x00dev->lna_gain); 4496 else { 4497 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4498 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3; 4499 else 4500 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3; 4501 } 4502 } 4503 4504 return vgc; 4505 } 4506 4507 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, 4508 struct link_qual *qual, u8 vgc_level) 4509 { 4510 if (qual->vgc_level != vgc_level) { 4511 if (rt2x00_rt(rt2x00dev, RT3572) || 4512 rt2x00_rt(rt2x00dev, RT3593)) { 4513 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, 4514 vgc_level); 4515 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 4516 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a); 4517 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level); 4518 } else { 4519 rt2800_bbp_write(rt2x00dev, 66, vgc_level); 4520 } 4521 4522 qual->vgc_level = vgc_level; 4523 qual->vgc_level_reg = vgc_level; 4524 } 4525 } 4526 4527 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 4528 { 4529 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); 4530 } 4531 EXPORT_SYMBOL_GPL(rt2800_reset_tuner); 4532 4533 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 4534 const u32 count) 4535 { 4536 u8 vgc; 4537 4538 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) 4539 return; 4540 4541 /* When RSSI is better than a certain threshold, increase VGC 4542 * with a chip specific value in order to improve the balance 4543 * between sensibility and noise isolation. 4544 */ 4545 4546 vgc = rt2800_get_default_vgc(rt2x00dev); 4547 4548 switch (rt2x00dev->chip.rt) { 4549 case RT3572: 4550 case RT3593: 4551 if (qual->rssi > -65) { 4552 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) 4553 vgc += 0x20; 4554 else 4555 vgc += 0x10; 4556 } 4557 break; 4558 4559 case RT5592: 4560 if (qual->rssi > -65) 4561 vgc += 0x20; 4562 break; 4563 4564 default: 4565 if (qual->rssi > -80) 4566 vgc += 0x10; 4567 break; 4568 } 4569 4570 rt2800_set_vgc(rt2x00dev, qual, vgc); 4571 } 4572 EXPORT_SYMBOL_GPL(rt2800_link_tuner); 4573 4574 /* 4575 * Initialization functions. 4576 */ 4577 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 4578 { 4579 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 4580 u32 reg; 4581 u16 eeprom; 4582 unsigned int i; 4583 int ret; 4584 4585 rt2800_disable_wpdma(rt2x00dev); 4586 4587 ret = rt2800_drv_init_registers(rt2x00dev); 4588 if (ret) 4589 return ret; 4590 4591 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); 4592 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 4593 4594 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 4595 4596 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); 4597 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); 4598 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); 4599 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); 4600 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); 4601 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 4602 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 4603 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 4604 4605 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); 4606 4607 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); 4608 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); 4609 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 4610 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 4611 4612 if (rt2x00_rt(rt2x00dev, RT3290)) { 4613 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); 4614 if (rt2x00_get_field32(reg, WLAN_EN) == 1) { 4615 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); 4616 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 4617 } 4618 4619 rt2800_register_read(rt2x00dev, CMB_CTRL, ®); 4620 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { 4621 rt2x00_set_field32(®, LDO0_EN, 1); 4622 rt2x00_set_field32(®, LDO_BGSEL, 3); 4623 rt2800_register_write(rt2x00dev, CMB_CTRL, reg); 4624 } 4625 4626 rt2800_register_read(rt2x00dev, OSC_CTRL, ®); 4627 rt2x00_set_field32(®, OSC_ROSC_EN, 1); 4628 rt2x00_set_field32(®, OSC_CAL_REQ, 1); 4629 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); 4630 rt2800_register_write(rt2x00dev, OSC_CTRL, reg); 4631 4632 rt2800_register_read(rt2x00dev, COEX_CFG0, ®); 4633 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); 4634 rt2800_register_write(rt2x00dev, COEX_CFG0, reg); 4635 4636 rt2800_register_read(rt2x00dev, COEX_CFG2, ®); 4637 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); 4638 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); 4639 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); 4640 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); 4641 rt2800_register_write(rt2x00dev, COEX_CFG2, reg); 4642 4643 rt2800_register_read(rt2x00dev, PLL_CTRL, ®); 4644 rt2x00_set_field32(®, PLL_CONTROL, 1); 4645 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); 4646 } 4647 4648 if (rt2x00_rt(rt2x00dev, RT3071) || 4649 rt2x00_rt(rt2x00dev, RT3090) || 4650 rt2x00_rt(rt2x00dev, RT3290) || 4651 rt2x00_rt(rt2x00dev, RT3390)) { 4652 4653 if (rt2x00_rt(rt2x00dev, RT3290)) 4654 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 4655 0x00000404); 4656 else 4657 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 4658 0x00000400); 4659 4660 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 4661 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 4662 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 4663 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 4664 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, 4665 &eeprom); 4666 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 4667 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 4668 0x0000002c); 4669 else 4670 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 4671 0x0000000f); 4672 } else { 4673 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 4674 } 4675 } else if (rt2x00_rt(rt2x00dev, RT3070)) { 4676 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 4677 4678 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 4679 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 4680 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); 4681 } else { 4682 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 4683 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 4684 } 4685 } else if (rt2800_is_305x_soc(rt2x00dev)) { 4686 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 4687 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 4688 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); 4689 } else if (rt2x00_rt(rt2x00dev, RT3352)) { 4690 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 4691 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 4692 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 4693 } else if (rt2x00_rt(rt2x00dev, RT3572)) { 4694 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 4695 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 4696 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 4697 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 4698 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 4699 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) { 4700 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, 4701 &eeprom); 4702 if (rt2x00_get_field16(eeprom, 4703 EEPROM_NIC_CONF1_DAC_TEST)) 4704 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 4705 0x0000001f); 4706 else 4707 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 4708 0x0000000f); 4709 } else { 4710 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 4711 0x00000000); 4712 } 4713 } else if (rt2x00_rt(rt2x00dev, RT5390) || 4714 rt2x00_rt(rt2x00dev, RT5392)) { 4715 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 4716 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 4717 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 4718 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 4719 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 4720 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 4721 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 4722 } else { 4723 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 4724 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 4725 } 4726 4727 rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®); 4728 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); 4729 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); 4730 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); 4731 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); 4732 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); 4733 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); 4734 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); 4735 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); 4736 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); 4737 4738 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®); 4739 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 4740 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); 4741 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 4742 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 4743 4744 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®); 4745 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 4746 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || 4747 rt2x00_rt(rt2x00dev, RT2883) || 4748 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) { 4749 drv_data->max_psdu = 2; 4750 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2); 4751 } else { 4752 drv_data->max_psdu = 1; 4753 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1); 4754 } 4755 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); 4756 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); 4757 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 4758 4759 rt2800_register_read(rt2x00dev, LED_CFG, ®); 4760 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); 4761 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); 4762 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); 4763 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); 4764 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); 4765 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); 4766 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); 4767 rt2800_register_write(rt2x00dev, LED_CFG, reg); 4768 4769 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 4770 4771 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); 4772 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 15); 4773 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 31); 4774 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); 4775 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); 4776 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); 4777 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); 4778 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 4779 4780 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); 4781 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); 4782 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); 4783 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); 4784 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); 4785 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); 4786 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 4787 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 4788 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 4789 4790 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); 4791 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); 4792 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); 4793 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); 4794 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 4795 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4796 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4797 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); 4798 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4799 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); 4800 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); 4801 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 4802 4803 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); 4804 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); 4805 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); 4806 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); 4807 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 4808 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4809 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4810 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); 4811 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4812 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); 4813 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); 4814 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 4815 4816 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); 4817 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 4818 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); 4819 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); 4820 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 4821 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4822 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4823 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 4824 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4825 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 4826 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); 4827 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 4828 4829 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); 4830 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 4831 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); 4832 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); 4833 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 4834 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4835 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4836 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 4837 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4838 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 4839 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); 4840 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 4841 4842 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); 4843 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 4844 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); 4845 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); 4846 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 4847 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4848 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4849 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 4850 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4851 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 4852 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); 4853 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 4854 4855 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); 4856 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 4857 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); 4858 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); 4859 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 4860 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4861 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4862 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 4863 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4864 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 4865 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); 4866 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 4867 4868 if (rt2x00_is_usb(rt2x00dev)) { 4869 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); 4870 4871 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); 4872 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 4873 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 4874 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 4875 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 4876 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); 4877 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); 4878 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); 4879 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); 4880 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); 4881 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 4882 } 4883 4884 /* 4885 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 4886 * although it is reserved. 4887 */ 4888 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, ®); 4889 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); 4890 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); 4891 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); 4892 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); 4893 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); 4894 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); 4895 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); 4896 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); 4897 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); 4898 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); 4899 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); 4900 4901 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; 4902 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); 4903 4904 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); 4905 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32); 4906 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, 4907 IEEE80211_MAX_RTS_THRESHOLD); 4908 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0); 4909 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 4910 4911 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 4912 4913 /* 4914 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS 4915 * time should be set to 16. However, the original Ralink driver uses 4916 * 16 for both and indeed using a value of 10 for CCK SIFS results in 4917 * connection problems with 11g + CTS protection. Hence, use the same 4918 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. 4919 */ 4920 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); 4921 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); 4922 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); 4923 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); 4924 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); 4925 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); 4926 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 4927 4928 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 4929 4930 /* 4931 * ASIC will keep garbage value after boot, clear encryption keys. 4932 */ 4933 for (i = 0; i < 4; i++) 4934 rt2800_register_write(rt2x00dev, 4935 SHARED_KEY_MODE_ENTRY(i), 0); 4936 4937 for (i = 0; i < 256; i++) { 4938 rt2800_config_wcid(rt2x00dev, NULL, i); 4939 rt2800_delete_wcid_attr(rt2x00dev, i); 4940 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 4941 } 4942 4943 /* 4944 * Clear all beacons 4945 */ 4946 for (i = 0; i < 8; i++) 4947 rt2800_clear_beacon_register(rt2x00dev, i); 4948 4949 if (rt2x00_is_usb(rt2x00dev)) { 4950 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); 4951 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); 4952 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 4953 } else if (rt2x00_is_pcie(rt2x00dev)) { 4954 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); 4955 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); 4956 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 4957 } 4958 4959 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®); 4960 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); 4961 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); 4962 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); 4963 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); 4964 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); 4965 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); 4966 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); 4967 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); 4968 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); 4969 4970 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®); 4971 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); 4972 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); 4973 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); 4974 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); 4975 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); 4976 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); 4977 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); 4978 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); 4979 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); 4980 4981 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®); 4982 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); 4983 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); 4984 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); 4985 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); 4986 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); 4987 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); 4988 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); 4989 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); 4990 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); 4991 4992 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®); 4993 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); 4994 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); 4995 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); 4996 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); 4997 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); 4998 4999 /* 5000 * Do not force the BA window size, we use the TXWI to set it 5001 */ 5002 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, ®); 5003 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); 5004 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); 5005 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); 5006 5007 /* 5008 * We must clear the error counters. 5009 * These registers are cleared on read, 5010 * so we may pass a useless variable to store the value. 5011 */ 5012 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); 5013 rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®); 5014 rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®); 5015 rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®); 5016 rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®); 5017 rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®); 5018 5019 /* 5020 * Setup leadtime for pre tbtt interrupt to 6ms 5021 */ 5022 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, ®); 5023 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); 5024 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); 5025 5026 /* 5027 * Set up channel statistics timer 5028 */ 5029 rt2800_register_read(rt2x00dev, CH_TIME_CFG, ®); 5030 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); 5031 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); 5032 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); 5033 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); 5034 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); 5035 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); 5036 5037 return 0; 5038 } 5039 5040 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) 5041 { 5042 unsigned int i; 5043 u32 reg; 5044 5045 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 5046 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®); 5047 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) 5048 return 0; 5049 5050 udelay(REGISTER_BUSY_DELAY); 5051 } 5052 5053 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n"); 5054 return -EACCES; 5055 } 5056 5057 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 5058 { 5059 unsigned int i; 5060 u8 value; 5061 5062 /* 5063 * BBP was enabled after firmware was loaded, 5064 * but we need to reactivate it now. 5065 */ 5066 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 5067 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 5068 msleep(1); 5069 5070 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 5071 rt2800_bbp_read(rt2x00dev, 0, &value); 5072 if ((value != 0xff) && (value != 0x00)) 5073 return 0; 5074 udelay(REGISTER_BUSY_DELAY); 5075 } 5076 5077 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 5078 return -EACCES; 5079 } 5080 5081 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev) 5082 { 5083 u8 value; 5084 5085 rt2800_bbp_read(rt2x00dev, 4, &value); 5086 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); 5087 rt2800_bbp_write(rt2x00dev, 4, value); 5088 } 5089 5090 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev) 5091 { 5092 rt2800_bbp_write(rt2x00dev, 142, 1); 5093 rt2800_bbp_write(rt2x00dev, 143, 57); 5094 } 5095 5096 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev) 5097 { 5098 const u8 glrt_table[] = { 5099 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */ 5100 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */ 5101 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */ 5102 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */ 5103 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */ 5104 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */ 5105 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */ 5106 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */ 5107 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */ 5108 }; 5109 int i; 5110 5111 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) { 5112 rt2800_bbp_write(rt2x00dev, 195, 128 + i); 5113 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]); 5114 } 5115 }; 5116 5117 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev) 5118 { 5119 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 5120 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5121 rt2800_bbp_write(rt2x00dev, 68, 0x0B); 5122 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5123 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5124 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5125 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5126 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5127 rt2800_bbp_write(rt2x00dev, 83, 0x6A); 5128 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5129 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5130 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5131 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5132 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5133 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5134 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5135 } 5136 5137 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev) 5138 { 5139 u16 eeprom; 5140 u8 value; 5141 5142 rt2800_bbp_read(rt2x00dev, 138, &value); 5143 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 5144 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 5145 value |= 0x20; 5146 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 5147 value &= ~0x02; 5148 rt2800_bbp_write(rt2x00dev, 138, value); 5149 } 5150 5151 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev) 5152 { 5153 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5154 5155 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5156 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5157 5158 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5159 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5160 5161 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5162 5163 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 5164 rt2800_bbp_write(rt2x00dev, 80, 0x08); 5165 5166 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5167 5168 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5169 5170 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5171 5172 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5173 5174 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5175 5176 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5177 5178 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5179 5180 rt2800_bbp_write(rt2x00dev, 105, 0x01); 5181 5182 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5183 } 5184 5185 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev) 5186 { 5187 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5188 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5189 5190 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 5191 rt2800_bbp_write(rt2x00dev, 69, 0x16); 5192 rt2800_bbp_write(rt2x00dev, 73, 0x12); 5193 } else { 5194 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5195 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5196 } 5197 5198 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5199 5200 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5201 5202 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5203 5204 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5205 5206 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 5207 rt2800_bbp_write(rt2x00dev, 84, 0x19); 5208 else 5209 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5210 5211 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5212 5213 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5214 5215 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5216 5217 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5218 5219 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5220 5221 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5222 } 5223 5224 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev) 5225 { 5226 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5227 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5228 5229 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5230 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5231 5232 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5233 5234 rt2800_bbp_write(rt2x00dev, 79, 0x13); 5235 rt2800_bbp_write(rt2x00dev, 80, 0x05); 5236 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5237 5238 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5239 5240 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5241 5242 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5243 5244 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5245 5246 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5247 5248 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5249 5250 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 5251 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 5252 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E)) 5253 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5254 else 5255 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5256 5257 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5258 5259 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5260 5261 if (rt2x00_rt(rt2x00dev, RT3071) || 5262 rt2x00_rt(rt2x00dev, RT3090)) 5263 rt2800_disable_unused_dac_adc(rt2x00dev); 5264 } 5265 5266 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev) 5267 { 5268 u8 value; 5269 5270 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 5271 5272 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5273 5274 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5275 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5276 5277 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 5278 5279 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5280 rt2800_bbp_write(rt2x00dev, 73, 0x13); 5281 rt2800_bbp_write(rt2x00dev, 75, 0x46); 5282 rt2800_bbp_write(rt2x00dev, 76, 0x28); 5283 5284 rt2800_bbp_write(rt2x00dev, 77, 0x58); 5285 5286 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5287 5288 rt2800_bbp_write(rt2x00dev, 74, 0x0b); 5289 rt2800_bbp_write(rt2x00dev, 79, 0x18); 5290 rt2800_bbp_write(rt2x00dev, 80, 0x09); 5291 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5292 5293 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5294 5295 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 5296 5297 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 5298 5299 rt2800_bbp_write(rt2x00dev, 86, 0x38); 5300 5301 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5302 5303 rt2800_bbp_write(rt2x00dev, 92, 0x02); 5304 5305 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5306 5307 rt2800_bbp_write(rt2x00dev, 104, 0x92); 5308 5309 rt2800_bbp_write(rt2x00dev, 105, 0x1c); 5310 5311 rt2800_bbp_write(rt2x00dev, 106, 0x03); 5312 5313 rt2800_bbp_write(rt2x00dev, 128, 0x12); 5314 5315 rt2800_bbp_write(rt2x00dev, 67, 0x24); 5316 rt2800_bbp_write(rt2x00dev, 143, 0x04); 5317 rt2800_bbp_write(rt2x00dev, 142, 0x99); 5318 rt2800_bbp_write(rt2x00dev, 150, 0x30); 5319 rt2800_bbp_write(rt2x00dev, 151, 0x2e); 5320 rt2800_bbp_write(rt2x00dev, 152, 0x20); 5321 rt2800_bbp_write(rt2x00dev, 153, 0x34); 5322 rt2800_bbp_write(rt2x00dev, 154, 0x40); 5323 rt2800_bbp_write(rt2x00dev, 155, 0x3b); 5324 rt2800_bbp_write(rt2x00dev, 253, 0x04); 5325 5326 rt2800_bbp_read(rt2x00dev, 47, &value); 5327 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1); 5328 rt2800_bbp_write(rt2x00dev, 47, value); 5329 5330 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */ 5331 rt2800_bbp_read(rt2x00dev, 3, &value); 5332 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1); 5333 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1); 5334 rt2800_bbp_write(rt2x00dev, 3, value); 5335 } 5336 5337 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) 5338 { 5339 rt2800_bbp_write(rt2x00dev, 3, 0x00); 5340 rt2800_bbp_write(rt2x00dev, 4, 0x50); 5341 5342 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5343 5344 rt2800_bbp_write(rt2x00dev, 47, 0x48); 5345 5346 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5347 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5348 5349 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 5350 5351 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5352 rt2800_bbp_write(rt2x00dev, 73, 0x13); 5353 rt2800_bbp_write(rt2x00dev, 75, 0x46); 5354 rt2800_bbp_write(rt2x00dev, 76, 0x28); 5355 5356 rt2800_bbp_write(rt2x00dev, 77, 0x59); 5357 5358 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5359 5360 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 5361 rt2800_bbp_write(rt2x00dev, 80, 0x08); 5362 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5363 5364 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5365 5366 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5367 5368 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5369 5370 rt2800_bbp_write(rt2x00dev, 86, 0x38); 5371 5372 rt2800_bbp_write(rt2x00dev, 88, 0x90); 5373 5374 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5375 5376 rt2800_bbp_write(rt2x00dev, 92, 0x02); 5377 5378 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5379 5380 rt2800_bbp_write(rt2x00dev, 104, 0x92); 5381 5382 rt2800_bbp_write(rt2x00dev, 105, 0x34); 5383 5384 rt2800_bbp_write(rt2x00dev, 106, 0x05); 5385 5386 rt2800_bbp_write(rt2x00dev, 120, 0x50); 5387 5388 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 5389 5390 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 5391 /* Set ITxBF timeout to 0x9c40=1000msec */ 5392 rt2800_bbp_write(rt2x00dev, 179, 0x02); 5393 rt2800_bbp_write(rt2x00dev, 180, 0x00); 5394 rt2800_bbp_write(rt2x00dev, 182, 0x40); 5395 rt2800_bbp_write(rt2x00dev, 180, 0x01); 5396 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 5397 rt2800_bbp_write(rt2x00dev, 179, 0x00); 5398 /* Reprogram the inband interface to put right values in RXWI */ 5399 rt2800_bbp_write(rt2x00dev, 142, 0x04); 5400 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 5401 rt2800_bbp_write(rt2x00dev, 142, 0x06); 5402 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 5403 rt2800_bbp_write(rt2x00dev, 142, 0x07); 5404 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 5405 rt2800_bbp_write(rt2x00dev, 142, 0x08); 5406 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 5407 5408 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 5409 } 5410 5411 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev) 5412 { 5413 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5414 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5415 5416 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5417 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5418 5419 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5420 5421 rt2800_bbp_write(rt2x00dev, 79, 0x13); 5422 rt2800_bbp_write(rt2x00dev, 80, 0x05); 5423 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5424 5425 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5426 5427 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5428 5429 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5430 5431 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5432 5433 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5434 5435 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5436 5437 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E)) 5438 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5439 else 5440 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5441 5442 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5443 5444 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5445 5446 rt2800_disable_unused_dac_adc(rt2x00dev); 5447 } 5448 5449 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev) 5450 { 5451 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5452 5453 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5454 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5455 5456 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5457 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5458 5459 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5460 5461 rt2800_bbp_write(rt2x00dev, 79, 0x13); 5462 rt2800_bbp_write(rt2x00dev, 80, 0x05); 5463 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5464 5465 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5466 5467 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5468 5469 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5470 5471 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5472 5473 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5474 5475 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5476 5477 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5478 5479 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5480 5481 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5482 5483 rt2800_disable_unused_dac_adc(rt2x00dev); 5484 } 5485 5486 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev) 5487 { 5488 rt2800_init_bbp_early(rt2x00dev); 5489 5490 rt2800_bbp_write(rt2x00dev, 79, 0x13); 5491 rt2800_bbp_write(rt2x00dev, 80, 0x05); 5492 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5493 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 5494 5495 rt2800_bbp_write(rt2x00dev, 84, 0x19); 5496 5497 /* Enable DC filter */ 5498 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E)) 5499 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5500 } 5501 5502 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) 5503 { 5504 int ant, div_mode; 5505 u16 eeprom; 5506 u8 value; 5507 5508 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 5509 5510 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5511 5512 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5513 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5514 5515 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 5516 5517 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5518 rt2800_bbp_write(rt2x00dev, 73, 0x13); 5519 rt2800_bbp_write(rt2x00dev, 75, 0x46); 5520 rt2800_bbp_write(rt2x00dev, 76, 0x28); 5521 5522 rt2800_bbp_write(rt2x00dev, 77, 0x59); 5523 5524 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5525 5526 rt2800_bbp_write(rt2x00dev, 79, 0x13); 5527 rt2800_bbp_write(rt2x00dev, 80, 0x05); 5528 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5529 5530 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5531 5532 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 5533 5534 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 5535 5536 rt2800_bbp_write(rt2x00dev, 86, 0x38); 5537 5538 if (rt2x00_rt(rt2x00dev, RT5392)) 5539 rt2800_bbp_write(rt2x00dev, 88, 0x90); 5540 5541 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5542 5543 rt2800_bbp_write(rt2x00dev, 92, 0x02); 5544 5545 if (rt2x00_rt(rt2x00dev, RT5392)) { 5546 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 5547 rt2800_bbp_write(rt2x00dev, 98, 0x12); 5548 } 5549 5550 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5551 5552 rt2800_bbp_write(rt2x00dev, 104, 0x92); 5553 5554 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 5555 5556 if (rt2x00_rt(rt2x00dev, RT5390)) 5557 rt2800_bbp_write(rt2x00dev, 106, 0x03); 5558 else if (rt2x00_rt(rt2x00dev, RT5392)) 5559 rt2800_bbp_write(rt2x00dev, 106, 0x12); 5560 else 5561 WARN_ON(1); 5562 5563 rt2800_bbp_write(rt2x00dev, 128, 0x12); 5564 5565 if (rt2x00_rt(rt2x00dev, RT5392)) { 5566 rt2800_bbp_write(rt2x00dev, 134, 0xd0); 5567 rt2800_bbp_write(rt2x00dev, 135, 0xf6); 5568 } 5569 5570 rt2800_disable_unused_dac_adc(rt2x00dev); 5571 5572 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); 5573 div_mode = rt2x00_get_field16(eeprom, 5574 EEPROM_NIC_CONF1_ANT_DIVERSITY); 5575 ant = (div_mode == 3) ? 1 : 0; 5576 5577 /* check if this is a Bluetooth combo card */ 5578 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 5579 u32 reg; 5580 5581 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 5582 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 5583 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); 5584 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); 5585 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); 5586 if (ant == 0) 5587 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); 5588 else if (ant == 1) 5589 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); 5590 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 5591 } 5592 5593 /* This chip has hardware antenna diversity*/ 5594 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) { 5595 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */ 5596 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */ 5597 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */ 5598 } 5599 5600 rt2800_bbp_read(rt2x00dev, 152, &value); 5601 if (ant == 0) 5602 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 5603 else 5604 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 5605 rt2800_bbp_write(rt2x00dev, 152, value); 5606 5607 rt2800_init_freq_calibration(rt2x00dev); 5608 } 5609 5610 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) 5611 { 5612 int ant, div_mode; 5613 u16 eeprom; 5614 u8 value; 5615 5616 rt2800_init_bbp_early(rt2x00dev); 5617 5618 rt2800_bbp_read(rt2x00dev, 105, &value); 5619 rt2x00_set_field8(&value, BBP105_MLD, 5620 rt2x00dev->default_ant.rx_chain_num == 2); 5621 rt2800_bbp_write(rt2x00dev, 105, value); 5622 5623 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 5624 5625 rt2800_bbp_write(rt2x00dev, 20, 0x06); 5626 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5627 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 5628 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 5629 rt2800_bbp_write(rt2x00dev, 69, 0x1A); 5630 rt2800_bbp_write(rt2x00dev, 70, 0x05); 5631 rt2800_bbp_write(rt2x00dev, 73, 0x13); 5632 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 5633 rt2800_bbp_write(rt2x00dev, 75, 0x4F); 5634 rt2800_bbp_write(rt2x00dev, 76, 0x28); 5635 rt2800_bbp_write(rt2x00dev, 77, 0x59); 5636 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 5637 rt2800_bbp_write(rt2x00dev, 86, 0x38); 5638 rt2800_bbp_write(rt2x00dev, 88, 0x90); 5639 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5640 rt2800_bbp_write(rt2x00dev, 92, 0x02); 5641 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 5642 rt2800_bbp_write(rt2x00dev, 98, 0x12); 5643 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 5644 rt2800_bbp_write(rt2x00dev, 104, 0x92); 5645 /* FIXME BBP105 owerwrite */ 5646 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 5647 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5648 rt2800_bbp_write(rt2x00dev, 128, 0x12); 5649 rt2800_bbp_write(rt2x00dev, 134, 0xD0); 5650 rt2800_bbp_write(rt2x00dev, 135, 0xF6); 5651 rt2800_bbp_write(rt2x00dev, 137, 0x0F); 5652 5653 /* Initialize GLRT (Generalized Likehood Radio Test) */ 5654 rt2800_init_bbp_5592_glrt(rt2x00dev); 5655 5656 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 5657 5658 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); 5659 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); 5660 ant = (div_mode == 3) ? 1 : 0; 5661 rt2800_bbp_read(rt2x00dev, 152, &value); 5662 if (ant == 0) { 5663 /* Main antenna */ 5664 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 5665 } else { 5666 /* Auxiliary antenna */ 5667 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 5668 } 5669 rt2800_bbp_write(rt2x00dev, 152, value); 5670 5671 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) { 5672 rt2800_bbp_read(rt2x00dev, 254, &value); 5673 rt2x00_set_field8(&value, BBP254_BIT7, 1); 5674 rt2800_bbp_write(rt2x00dev, 254, value); 5675 } 5676 5677 rt2800_init_freq_calibration(rt2x00dev); 5678 5679 rt2800_bbp_write(rt2x00dev, 84, 0x19); 5680 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 5681 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5682 } 5683 5684 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) 5685 { 5686 unsigned int i; 5687 u16 eeprom; 5688 u8 reg_id; 5689 u8 value; 5690 5691 if (rt2800_is_305x_soc(rt2x00dev)) 5692 rt2800_init_bbp_305x_soc(rt2x00dev); 5693 5694 switch (rt2x00dev->chip.rt) { 5695 case RT2860: 5696 case RT2872: 5697 case RT2883: 5698 rt2800_init_bbp_28xx(rt2x00dev); 5699 break; 5700 case RT3070: 5701 case RT3071: 5702 case RT3090: 5703 rt2800_init_bbp_30xx(rt2x00dev); 5704 break; 5705 case RT3290: 5706 rt2800_init_bbp_3290(rt2x00dev); 5707 break; 5708 case RT3352: 5709 rt2800_init_bbp_3352(rt2x00dev); 5710 break; 5711 case RT3390: 5712 rt2800_init_bbp_3390(rt2x00dev); 5713 break; 5714 case RT3572: 5715 rt2800_init_bbp_3572(rt2x00dev); 5716 break; 5717 case RT3593: 5718 rt2800_init_bbp_3593(rt2x00dev); 5719 return; 5720 case RT5390: 5721 case RT5392: 5722 rt2800_init_bbp_53xx(rt2x00dev); 5723 break; 5724 case RT5592: 5725 rt2800_init_bbp_5592(rt2x00dev); 5726 return; 5727 } 5728 5729 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 5730 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i, 5731 &eeprom); 5732 5733 if (eeprom != 0xffff && eeprom != 0x0000) { 5734 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 5735 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 5736 rt2800_bbp_write(rt2x00dev, reg_id, value); 5737 } 5738 } 5739 } 5740 5741 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev) 5742 { 5743 u32 reg; 5744 5745 rt2800_register_read(rt2x00dev, OPT_14_CSR, ®); 5746 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); 5747 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 5748 } 5749 5750 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, 5751 u8 filter_target) 5752 { 5753 unsigned int i; 5754 u8 bbp; 5755 u8 rfcsr; 5756 u8 passband; 5757 u8 stopband; 5758 u8 overtuned = 0; 5759 u8 rfcsr24 = (bw40) ? 0x27 : 0x07; 5760 5761 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 5762 5763 rt2800_bbp_read(rt2x00dev, 4, &bbp); 5764 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); 5765 rt2800_bbp_write(rt2x00dev, 4, bbp); 5766 5767 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr); 5768 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); 5769 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 5770 5771 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); 5772 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); 5773 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 5774 5775 /* 5776 * Set power & frequency of passband test tone 5777 */ 5778 rt2800_bbp_write(rt2x00dev, 24, 0); 5779 5780 for (i = 0; i < 100; i++) { 5781 rt2800_bbp_write(rt2x00dev, 25, 0x90); 5782 msleep(1); 5783 5784 rt2800_bbp_read(rt2x00dev, 55, &passband); 5785 if (passband) 5786 break; 5787 } 5788 5789 /* 5790 * Set power & frequency of stopband test tone 5791 */ 5792 rt2800_bbp_write(rt2x00dev, 24, 0x06); 5793 5794 for (i = 0; i < 100; i++) { 5795 rt2800_bbp_write(rt2x00dev, 25, 0x90); 5796 msleep(1); 5797 5798 rt2800_bbp_read(rt2x00dev, 55, &stopband); 5799 5800 if ((passband - stopband) <= filter_target) { 5801 rfcsr24++; 5802 overtuned += ((passband - stopband) == filter_target); 5803 } else 5804 break; 5805 5806 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 5807 } 5808 5809 rfcsr24 -= !!overtuned; 5810 5811 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 5812 return rfcsr24; 5813 } 5814 5815 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev, 5816 const unsigned int rf_reg) 5817 { 5818 u8 rfcsr; 5819 5820 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr); 5821 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1); 5822 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 5823 msleep(1); 5824 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0); 5825 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 5826 } 5827 5828 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev) 5829 { 5830 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5831 u8 filter_tgt_bw20; 5832 u8 filter_tgt_bw40; 5833 u8 rfcsr, bbp; 5834 5835 /* 5836 * TODO: sync filter_tgt values with vendor driver 5837 */ 5838 if (rt2x00_rt(rt2x00dev, RT3070)) { 5839 filter_tgt_bw20 = 0x16; 5840 filter_tgt_bw40 = 0x19; 5841 } else { 5842 filter_tgt_bw20 = 0x13; 5843 filter_tgt_bw40 = 0x15; 5844 } 5845 5846 drv_data->calibration_bw20 = 5847 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20); 5848 drv_data->calibration_bw40 = 5849 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40); 5850 5851 /* 5852 * Save BBP 25 & 26 values for later use in channel switching (for 3052) 5853 */ 5854 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25); 5855 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26); 5856 5857 /* 5858 * Set back to initial state 5859 */ 5860 rt2800_bbp_write(rt2x00dev, 24, 0); 5861 5862 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); 5863 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 5864 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 5865 5866 /* 5867 * Set BBP back to BW20 5868 */ 5869 rt2800_bbp_read(rt2x00dev, 4, &bbp); 5870 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 5871 rt2800_bbp_write(rt2x00dev, 4, bbp); 5872 } 5873 5874 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) 5875 { 5876 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5877 u8 min_gain, rfcsr, bbp; 5878 u16 eeprom; 5879 5880 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); 5881 5882 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 5883 if (rt2x00_rt(rt2x00dev, RT3070) || 5884 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 5885 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 5886 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 5887 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev)) 5888 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 5889 } 5890 5891 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2; 5892 if (drv_data->txmixer_gain_24g >= min_gain) { 5893 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 5894 drv_data->txmixer_gain_24g); 5895 } 5896 5897 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 5898 5899 if (rt2x00_rt(rt2x00dev, RT3090)) { 5900 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 5901 rt2800_bbp_read(rt2x00dev, 138, &bbp); 5902 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 5903 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 5904 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); 5905 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 5906 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); 5907 rt2800_bbp_write(rt2x00dev, 138, bbp); 5908 } 5909 5910 if (rt2x00_rt(rt2x00dev, RT3070)) { 5911 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr); 5912 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) 5913 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); 5914 else 5915 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); 5916 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); 5917 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); 5918 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); 5919 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 5920 } else if (rt2x00_rt(rt2x00dev, RT3071) || 5921 rt2x00_rt(rt2x00dev, RT3090) || 5922 rt2x00_rt(rt2x00dev, RT3390)) { 5923 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 5924 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 5925 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 5926 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 5927 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 5928 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 5929 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 5930 5931 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr); 5932 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); 5933 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); 5934 5935 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr); 5936 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); 5937 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 5938 5939 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr); 5940 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); 5941 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 5942 } 5943 } 5944 5945 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev) 5946 { 5947 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5948 u8 rfcsr; 5949 u8 tx_gain; 5950 5951 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); 5952 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0); 5953 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 5954 5955 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr); 5956 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g, 5957 RFCSR17_TXMIXER_GAIN); 5958 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain); 5959 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 5960 5961 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr); 5962 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); 5963 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); 5964 5965 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr); 5966 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); 5967 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 5968 5969 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 5970 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 5971 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 5972 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 5973 5974 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 5975 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 5976 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 5977 5978 /* TODO: enable stream mode */ 5979 } 5980 5981 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev) 5982 { 5983 u8 reg; 5984 u16 eeprom; 5985 5986 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 5987 rt2800_bbp_read(rt2x00dev, 138, ®); 5988 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 5989 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 5990 rt2x00_set_field8(®, BBP138_RX_ADC1, 0); 5991 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 5992 rt2x00_set_field8(®, BBP138_TX_DAC1, 1); 5993 rt2800_bbp_write(rt2x00dev, 138, reg); 5994 5995 rt2800_rfcsr_read(rt2x00dev, 38, ®); 5996 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); 5997 rt2800_rfcsr_write(rt2x00dev, 38, reg); 5998 5999 rt2800_rfcsr_read(rt2x00dev, 39, ®); 6000 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); 6001 rt2800_rfcsr_write(rt2x00dev, 39, reg); 6002 6003 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6004 6005 rt2800_rfcsr_read(rt2x00dev, 30, ®); 6006 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); 6007 rt2800_rfcsr_write(rt2x00dev, 30, reg); 6008 } 6009 6010 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev) 6011 { 6012 rt2800_rf_init_calibration(rt2x00dev, 30); 6013 6014 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 6015 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 6016 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 6017 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 6018 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 6019 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 6020 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 6021 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 6022 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 6023 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 6024 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 6025 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 6026 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 6027 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 6028 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 6029 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 6030 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 6031 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 6032 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 6033 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 6034 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 6035 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 6036 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 6037 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 6038 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 6039 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 6040 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 6041 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 6042 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 6043 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 6044 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 6045 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 6046 } 6047 6048 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) 6049 { 6050 u8 rfcsr; 6051 u16 eeprom; 6052 u32 reg; 6053 6054 /* XXX vendor driver do this only for 3070 */ 6055 rt2800_rf_init_calibration(rt2x00dev, 30); 6056 6057 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 6058 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 6059 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 6060 rt2800_rfcsr_write(rt2x00dev, 7, 0x60); 6061 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 6062 rt2800_rfcsr_write(rt2x00dev, 10, 0x41); 6063 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 6064 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 6065 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 6066 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 6067 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 6068 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 6069 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 6070 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 6071 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 6072 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 6073 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 6074 rt2800_rfcsr_write(rt2x00dev, 25, 0x03); 6075 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 6076 6077 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 6078 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6079 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 6080 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 6081 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6082 } else if (rt2x00_rt(rt2x00dev, RT3071) || 6083 rt2x00_rt(rt2x00dev, RT3090)) { 6084 rt2800_rfcsr_write(rt2x00dev, 31, 0x14); 6085 6086 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 6087 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 6088 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 6089 6090 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6091 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 6092 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 6093 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { 6094 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, 6095 &eeprom); 6096 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 6097 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 6098 else 6099 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 6100 } 6101 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6102 6103 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); 6104 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 6105 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 6106 } 6107 6108 rt2800_rx_filter_calibration(rt2x00dev); 6109 6110 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 6111 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 6112 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) 6113 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 6114 6115 rt2800_led_open_drain_enable(rt2x00dev); 6116 rt2800_normal_mode_setup_3xxx(rt2x00dev); 6117 } 6118 6119 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) 6120 { 6121 u8 rfcsr; 6122 6123 rt2800_rf_init_calibration(rt2x00dev, 2); 6124 6125 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 6126 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 6127 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 6128 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 6129 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 6130 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3); 6131 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 6132 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 6133 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 6134 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 6135 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 6136 rt2800_rfcsr_write(rt2x00dev, 18, 0x02); 6137 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 6138 rt2800_rfcsr_write(rt2x00dev, 25, 0x83); 6139 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 6140 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 6141 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 6142 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 6143 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 6144 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 6145 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 6146 rt2800_rfcsr_write(rt2x00dev, 34, 0x05); 6147 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 6148 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 6149 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 6150 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 6151 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 6152 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 6153 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 6154 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b); 6155 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 6156 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 6157 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 6158 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 6159 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 6160 rt2800_rfcsr_write(rt2x00dev, 49, 0x98); 6161 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 6162 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 6163 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 6164 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 6165 rt2800_rfcsr_write(rt2x00dev, 56, 0x02); 6166 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 6167 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 6168 rt2800_rfcsr_write(rt2x00dev, 59, 0x09); 6169 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 6170 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); 6171 6172 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr); 6173 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3); 6174 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr); 6175 6176 rt2800_led_open_drain_enable(rt2x00dev); 6177 rt2800_normal_mode_setup_3xxx(rt2x00dev); 6178 } 6179 6180 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) 6181 { 6182 rt2800_rf_init_calibration(rt2x00dev, 30); 6183 6184 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 6185 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 6186 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 6187 rt2800_rfcsr_write(rt2x00dev, 3, 0x18); 6188 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 6189 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 6190 rt2800_rfcsr_write(rt2x00dev, 6, 0x33); 6191 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 6192 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 6193 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 6194 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2); 6195 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 6196 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 6197 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 6198 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a); 6199 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 6200 rt2800_rfcsr_write(rt2x00dev, 16, 0x01); 6201 rt2800_rfcsr_write(rt2x00dev, 18, 0x45); 6202 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 6203 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 6204 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 6205 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 6206 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 6207 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 6208 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 6209 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 6210 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 6211 rt2800_rfcsr_write(rt2x00dev, 28, 0x03); 6212 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 6213 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 6214 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 6215 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 6216 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 6217 rt2800_rfcsr_write(rt2x00dev, 34, 0x01); 6218 rt2800_rfcsr_write(rt2x00dev, 35, 0x03); 6219 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); 6220 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); 6221 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); 6222 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); 6223 rt2800_rfcsr_write(rt2x00dev, 40, 0x33); 6224 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b); 6225 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); 6226 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); 6227 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); 6228 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); 6229 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd); 6230 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); 6231 rt2800_rfcsr_write(rt2x00dev, 48, 0x14); 6232 rt2800_rfcsr_write(rt2x00dev, 49, 0x00); 6233 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d); 6234 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f); 6235 rt2800_rfcsr_write(rt2x00dev, 52, 0x00); 6236 rt2800_rfcsr_write(rt2x00dev, 53, 0x52); 6237 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b); 6238 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f); 6239 rt2800_rfcsr_write(rt2x00dev, 56, 0x00); 6240 rt2800_rfcsr_write(rt2x00dev, 57, 0x52); 6241 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b); 6242 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 6243 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 6244 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 6245 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 6246 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 6247 6248 rt2800_rx_filter_calibration(rt2x00dev); 6249 rt2800_led_open_drain_enable(rt2x00dev); 6250 rt2800_normal_mode_setup_3xxx(rt2x00dev); 6251 } 6252 6253 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) 6254 { 6255 u32 reg; 6256 6257 rt2800_rf_init_calibration(rt2x00dev, 30); 6258 6259 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 6260 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 6261 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 6262 rt2800_rfcsr_write(rt2x00dev, 3, 0x62); 6263 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 6264 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); 6265 rt2800_rfcsr_write(rt2x00dev, 6, 0x42); 6266 rt2800_rfcsr_write(rt2x00dev, 7, 0x34); 6267 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 6268 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 6269 rt2800_rfcsr_write(rt2x00dev, 10, 0x61); 6270 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 6271 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); 6272 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); 6273 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 6274 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 6275 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); 6276 rt2800_rfcsr_write(rt2x00dev, 17, 0x94); 6277 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); 6278 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); 6279 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); 6280 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); 6281 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 6282 rt2800_rfcsr_write(rt2x00dev, 23, 0x14); 6283 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 6284 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 6285 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 6286 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 6287 rt2800_rfcsr_write(rt2x00dev, 28, 0x41); 6288 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); 6289 rt2800_rfcsr_write(rt2x00dev, 30, 0x20); 6290 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); 6291 6292 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); 6293 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 6294 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 6295 6296 rt2800_rx_filter_calibration(rt2x00dev); 6297 6298 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) 6299 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 6300 6301 rt2800_led_open_drain_enable(rt2x00dev); 6302 rt2800_normal_mode_setup_3xxx(rt2x00dev); 6303 } 6304 6305 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) 6306 { 6307 u8 rfcsr; 6308 u32 reg; 6309 6310 rt2800_rf_init_calibration(rt2x00dev, 30); 6311 6312 rt2800_rfcsr_write(rt2x00dev, 0, 0x70); 6313 rt2800_rfcsr_write(rt2x00dev, 1, 0x81); 6314 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 6315 rt2800_rfcsr_write(rt2x00dev, 3, 0x02); 6316 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); 6317 rt2800_rfcsr_write(rt2x00dev, 5, 0x05); 6318 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); 6319 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 6320 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 6321 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 6322 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 6323 rt2800_rfcsr_write(rt2x00dev, 12, 0x70); 6324 rt2800_rfcsr_write(rt2x00dev, 13, 0x65); 6325 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); 6326 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 6327 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); 6328 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 6329 rt2800_rfcsr_write(rt2x00dev, 18, 0xac); 6330 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 6331 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 6332 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); 6333 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 6334 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); 6335 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 6336 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 6337 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 6338 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 6339 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 6340 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 6341 rt2800_rfcsr_write(rt2x00dev, 30, 0x09); 6342 rt2800_rfcsr_write(rt2x00dev, 31, 0x10); 6343 6344 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 6345 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 6346 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 6347 6348 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6349 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 6350 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 6351 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6352 msleep(1); 6353 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6354 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 6355 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 6356 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6357 6358 rt2800_rx_filter_calibration(rt2x00dev); 6359 rt2800_led_open_drain_enable(rt2x00dev); 6360 rt2800_normal_mode_setup_3xxx(rt2x00dev); 6361 } 6362 6363 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev) 6364 { 6365 u8 bbp; 6366 bool txbf_enabled = false; /* FIXME */ 6367 6368 rt2800_bbp_read(rt2x00dev, 105, &bbp); 6369 if (rt2x00dev->default_ant.rx_chain_num == 1) 6370 rt2x00_set_field8(&bbp, BBP105_MLD, 0); 6371 else 6372 rt2x00_set_field8(&bbp, BBP105_MLD, 1); 6373 rt2800_bbp_write(rt2x00dev, 105, bbp); 6374 6375 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6376 6377 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6378 rt2800_bbp_write(rt2x00dev, 82, 0x82); 6379 rt2800_bbp_write(rt2x00dev, 106, 0x05); 6380 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6381 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6382 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6383 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6384 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6385 6386 if (txbf_enabled) 6387 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 6388 else 6389 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 6390 6391 /* SNR mapping */ 6392 rt2800_bbp_write(rt2x00dev, 142, 6); 6393 rt2800_bbp_write(rt2x00dev, 143, 160); 6394 rt2800_bbp_write(rt2x00dev, 142, 7); 6395 rt2800_bbp_write(rt2x00dev, 143, 161); 6396 rt2800_bbp_write(rt2x00dev, 142, 8); 6397 rt2800_bbp_write(rt2x00dev, 143, 162); 6398 6399 /* ADC/DAC control */ 6400 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6401 6402 /* RX AGC energy lower bound in log2 */ 6403 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6404 6405 /* FIXME: BBP 105 owerwrite? */ 6406 rt2800_bbp_write(rt2x00dev, 105, 0x04); 6407 6408 } 6409 6410 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) 6411 { 6412 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 6413 u32 reg; 6414 u8 rfcsr; 6415 6416 /* Disable GPIO #4 and #7 function for LAN PE control */ 6417 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); 6418 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); 6419 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); 6420 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 6421 6422 /* Initialize default register values */ 6423 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 6424 rt2800_rfcsr_write(rt2x00dev, 3, 0x80); 6425 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 6426 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 6427 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 6428 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 6429 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 6430 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 6431 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e); 6432 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 6433 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 6434 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 6435 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 6436 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 6437 rt2800_rfcsr_write(rt2x00dev, 32, 0x78); 6438 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b); 6439 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 6440 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0); 6441 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 6442 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 6443 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3); 6444 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 6445 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 6446 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 6447 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 6448 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 6449 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 6450 rt2800_rfcsr_write(rt2x00dev, 53, 0x18); 6451 rt2800_rfcsr_write(rt2x00dev, 54, 0x18); 6452 rt2800_rfcsr_write(rt2x00dev, 55, 0x18); 6453 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 6454 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 6455 6456 /* Initiate calibration */ 6457 /* TODO: use rt2800_rf_init_calibration ? */ 6458 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr); 6459 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 6460 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 6461 6462 rt2800_freq_cal_mode1(rt2x00dev); 6463 6464 rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr); 6465 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1); 6466 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 6467 6468 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6469 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 6470 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 6471 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6472 usleep_range(1000, 1500); 6473 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6474 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 6475 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6476 6477 /* Set initial values for RX filter calibration */ 6478 drv_data->calibration_bw20 = 0x1f; 6479 drv_data->calibration_bw40 = 0x2f; 6480 6481 /* Save BBP 25 & 26 values for later use in channel switching */ 6482 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25); 6483 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26); 6484 6485 rt2800_led_open_drain_enable(rt2x00dev); 6486 rt2800_normal_mode_setup_3593(rt2x00dev); 6487 6488 rt3593_post_bbp_init(rt2x00dev); 6489 6490 /* TODO: enable stream mode support */ 6491 } 6492 6493 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) 6494 { 6495 rt2800_rf_init_calibration(rt2x00dev, 2); 6496 6497 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 6498 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 6499 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 6500 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 6501 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 6502 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 6503 else 6504 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 6505 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 6506 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 6507 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 6508 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 6509 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 6510 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 6511 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 6512 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 6513 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 6514 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 6515 6516 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 6517 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 6518 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 6519 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 6520 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 6521 if (rt2x00_is_usb(rt2x00dev) && 6522 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 6523 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 6524 else 6525 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); 6526 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 6527 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 6528 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 6529 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 6530 6531 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 6532 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 6533 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 6534 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 6535 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 6536 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 6537 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 6538 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 6539 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 6540 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 6541 6542 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 6543 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 6544 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); 6545 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); 6546 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 6547 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 6548 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 6549 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 6550 else 6551 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); 6552 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 6553 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 6554 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 6555 6556 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 6557 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 6558 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 6559 else 6560 rt2800_rfcsr_write(rt2x00dev, 53, 0x84); 6561 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 6562 rt2800_rfcsr_write(rt2x00dev, 55, 0x44); 6563 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 6564 rt2800_rfcsr_write(rt2x00dev, 56, 0x42); 6565 else 6566 rt2800_rfcsr_write(rt2x00dev, 56, 0x22); 6567 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 6568 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 6569 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f); 6570 6571 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 6572 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 6573 if (rt2x00_is_usb(rt2x00dev)) 6574 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 6575 else 6576 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5); 6577 } else { 6578 if (rt2x00_is_usb(rt2x00dev)) 6579 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); 6580 else 6581 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5); 6582 } 6583 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 6584 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 6585 6586 rt2800_normal_mode_setup_5xxx(rt2x00dev); 6587 6588 rt2800_led_open_drain_enable(rt2x00dev); 6589 } 6590 6591 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) 6592 { 6593 rt2800_rf_init_calibration(rt2x00dev, 2); 6594 6595 rt2800_rfcsr_write(rt2x00dev, 1, 0x17); 6596 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 6597 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 6598 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 6599 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 6600 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 6601 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 6602 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 6603 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 6604 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 6605 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 6606 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 6607 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 6608 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d); 6609 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 6610 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d); 6611 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 6612 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b); 6613 rt2800_rfcsr_write(rt2x00dev, 24, 0x44); 6614 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 6615 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 6616 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 6617 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 6618 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 6619 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 6620 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 6621 rt2800_rfcsr_write(rt2x00dev, 32, 0x20); 6622 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 6623 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 6624 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 6625 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 6626 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 6627 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 6628 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 6629 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f); 6630 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 6631 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 6632 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 6633 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 6634 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 6635 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 6636 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c); 6637 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 6638 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 6639 rt2800_rfcsr_write(rt2x00dev, 50, 0x94); 6640 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a); 6641 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 6642 rt2800_rfcsr_write(rt2x00dev, 53, 0x44); 6643 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 6644 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 6645 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1); 6646 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 6647 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 6648 rt2800_rfcsr_write(rt2x00dev, 59, 0x07); 6649 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 6650 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 6651 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 6652 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 6653 6654 rt2800_normal_mode_setup_5xxx(rt2x00dev); 6655 6656 rt2800_led_open_drain_enable(rt2x00dev); 6657 } 6658 6659 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev) 6660 { 6661 rt2800_rf_init_calibration(rt2x00dev, 30); 6662 6663 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F); 6664 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 6665 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 6666 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4); 6667 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 6668 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 6669 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 6670 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 6671 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 6672 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D); 6673 rt2800_rfcsr_write(rt2x00dev, 20, 0x10); 6674 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D); 6675 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 6676 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 6677 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 6678 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 6679 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 6680 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 6681 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C); 6682 rt2800_rfcsr_write(rt2x00dev, 53, 0x22); 6683 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 6684 6685 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 6686 msleep(1); 6687 6688 rt2800_freq_cal_mode1(rt2x00dev); 6689 6690 /* Enable DC filter */ 6691 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 6692 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6693 6694 rt2800_normal_mode_setup_5xxx(rt2x00dev); 6695 6696 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C)) 6697 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 6698 6699 rt2800_led_open_drain_enable(rt2x00dev); 6700 } 6701 6702 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) 6703 { 6704 if (rt2800_is_305x_soc(rt2x00dev)) { 6705 rt2800_init_rfcsr_305x_soc(rt2x00dev); 6706 return; 6707 } 6708 6709 switch (rt2x00dev->chip.rt) { 6710 case RT3070: 6711 case RT3071: 6712 case RT3090: 6713 rt2800_init_rfcsr_30xx(rt2x00dev); 6714 break; 6715 case RT3290: 6716 rt2800_init_rfcsr_3290(rt2x00dev); 6717 break; 6718 case RT3352: 6719 rt2800_init_rfcsr_3352(rt2x00dev); 6720 break; 6721 case RT3390: 6722 rt2800_init_rfcsr_3390(rt2x00dev); 6723 break; 6724 case RT3572: 6725 rt2800_init_rfcsr_3572(rt2x00dev); 6726 break; 6727 case RT3593: 6728 rt2800_init_rfcsr_3593(rt2x00dev); 6729 break; 6730 case RT5390: 6731 rt2800_init_rfcsr_5390(rt2x00dev); 6732 break; 6733 case RT5392: 6734 rt2800_init_rfcsr_5392(rt2x00dev); 6735 break; 6736 case RT5592: 6737 rt2800_init_rfcsr_5592(rt2x00dev); 6738 break; 6739 } 6740 } 6741 6742 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) 6743 { 6744 u32 reg; 6745 u16 word; 6746 6747 /* 6748 * Initialize MAC registers. 6749 */ 6750 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || 6751 rt2800_init_registers(rt2x00dev))) 6752 return -EIO; 6753 6754 /* 6755 * Wait BBP/RF to wake up. 6756 */ 6757 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev))) 6758 return -EIO; 6759 6760 /* 6761 * Send signal during boot time to initialize firmware. 6762 */ 6763 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 6764 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 6765 if (rt2x00_is_usb(rt2x00dev)) 6766 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 6767 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 6768 msleep(1); 6769 6770 /* 6771 * Make sure BBP is up and running. 6772 */ 6773 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev))) 6774 return -EIO; 6775 6776 /* 6777 * Initialize BBP/RF registers. 6778 */ 6779 rt2800_init_bbp(rt2x00dev); 6780 rt2800_init_rfcsr(rt2x00dev); 6781 6782 if (rt2x00_is_usb(rt2x00dev) && 6783 (rt2x00_rt(rt2x00dev, RT3070) || 6784 rt2x00_rt(rt2x00dev, RT3071) || 6785 rt2x00_rt(rt2x00dev, RT3572))) { 6786 udelay(200); 6787 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); 6788 udelay(10); 6789 } 6790 6791 /* 6792 * Enable RX. 6793 */ 6794 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); 6795 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 6796 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 6797 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 6798 6799 udelay(50); 6800 6801 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); 6802 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 6803 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 6804 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 6805 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 6806 6807 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); 6808 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 6809 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); 6810 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 6811 6812 /* 6813 * Initialize LED control 6814 */ 6815 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word); 6816 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, 6817 word & 0xff, (word >> 8) & 0xff); 6818 6819 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word); 6820 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, 6821 word & 0xff, (word >> 8) & 0xff); 6822 6823 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word); 6824 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, 6825 word & 0xff, (word >> 8) & 0xff); 6826 6827 return 0; 6828 } 6829 EXPORT_SYMBOL_GPL(rt2800_enable_radio); 6830 6831 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) 6832 { 6833 u32 reg; 6834 6835 rt2800_disable_wpdma(rt2x00dev); 6836 6837 /* Wait for DMA, ignore error */ 6838 rt2800_wait_wpdma_ready(rt2x00dev); 6839 6840 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); 6841 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); 6842 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 6843 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 6844 } 6845 EXPORT_SYMBOL_GPL(rt2800_disable_radio); 6846 6847 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 6848 { 6849 u32 reg; 6850 u16 efuse_ctrl_reg; 6851 6852 if (rt2x00_rt(rt2x00dev, RT3290)) 6853 efuse_ctrl_reg = EFUSE_CTRL_3290; 6854 else 6855 efuse_ctrl_reg = EFUSE_CTRL; 6856 6857 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, ®); 6858 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); 6859 } 6860 EXPORT_SYMBOL_GPL(rt2800_efuse_detect); 6861 6862 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) 6863 { 6864 u32 reg; 6865 u16 efuse_ctrl_reg; 6866 u16 efuse_data0_reg; 6867 u16 efuse_data1_reg; 6868 u16 efuse_data2_reg; 6869 u16 efuse_data3_reg; 6870 6871 if (rt2x00_rt(rt2x00dev, RT3290)) { 6872 efuse_ctrl_reg = EFUSE_CTRL_3290; 6873 efuse_data0_reg = EFUSE_DATA0_3290; 6874 efuse_data1_reg = EFUSE_DATA1_3290; 6875 efuse_data2_reg = EFUSE_DATA2_3290; 6876 efuse_data3_reg = EFUSE_DATA3_3290; 6877 } else { 6878 efuse_ctrl_reg = EFUSE_CTRL; 6879 efuse_data0_reg = EFUSE_DATA0; 6880 efuse_data1_reg = EFUSE_DATA1; 6881 efuse_data2_reg = EFUSE_DATA2; 6882 efuse_data3_reg = EFUSE_DATA3; 6883 } 6884 mutex_lock(&rt2x00dev->csr_mutex); 6885 6886 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, ®); 6887 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); 6888 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); 6889 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); 6890 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); 6891 6892 /* Wait until the EEPROM has been loaded */ 6893 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); 6894 /* Apparently the data is read from end to start */ 6895 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, ®); 6896 /* The returned value is in CPU order, but eeprom is le */ 6897 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); 6898 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, ®); 6899 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); 6900 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, ®); 6901 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); 6902 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, ®); 6903 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); 6904 6905 mutex_unlock(&rt2x00dev->csr_mutex); 6906 } 6907 6908 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 6909 { 6910 unsigned int i; 6911 6912 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) 6913 rt2800_efuse_read(rt2x00dev, i); 6914 6915 return 0; 6916 } 6917 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); 6918 6919 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev) 6920 { 6921 u16 word; 6922 6923 if (rt2x00_rt(rt2x00dev, RT3593)) 6924 return 0; 6925 6926 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word); 6927 if ((word & 0x00ff) != 0x00ff) 6928 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL); 6929 6930 return 0; 6931 } 6932 6933 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev) 6934 { 6935 u16 word; 6936 6937 if (rt2x00_rt(rt2x00dev, RT3593)) 6938 return 0; 6939 6940 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word); 6941 if ((word & 0x00ff) != 0x00ff) 6942 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL); 6943 6944 return 0; 6945 } 6946 6947 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) 6948 { 6949 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 6950 u16 word; 6951 u8 *mac; 6952 u8 default_lna_gain; 6953 int retval; 6954 6955 /* 6956 * Read the EEPROM. 6957 */ 6958 retval = rt2800_read_eeprom(rt2x00dev); 6959 if (retval) 6960 return retval; 6961 6962 /* 6963 * Start validation of the data that has been read. 6964 */ 6965 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 6966 rt2x00lib_set_mac_address(rt2x00dev, mac); 6967 6968 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word); 6969 if (word == 0xffff) { 6970 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 6971 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); 6972 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); 6973 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 6974 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 6975 } else if (rt2x00_rt(rt2x00dev, RT2860) || 6976 rt2x00_rt(rt2x00dev, RT2872)) { 6977 /* 6978 * There is a max of 2 RX streams for RT28x0 series 6979 */ 6980 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2) 6981 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 6982 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 6983 } 6984 6985 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word); 6986 if (word == 0xffff) { 6987 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); 6988 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); 6989 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0); 6990 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0); 6991 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0); 6992 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0); 6993 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0); 6994 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0); 6995 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0); 6996 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0); 6997 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0); 6998 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0); 6999 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0); 7000 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); 7001 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); 7002 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); 7003 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 7004 } 7005 7006 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); 7007 if ((word & 0x00ff) == 0x00ff) { 7008 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 7009 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 7010 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); 7011 } 7012 if ((word & 0xff00) == 0xff00) { 7013 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, 7014 LED_MODE_TXRX_ACTIVITY); 7015 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); 7016 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 7017 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); 7018 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); 7019 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); 7020 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word); 7021 } 7022 7023 /* 7024 * During the LNA validation we are going to use 7025 * lna0 as correct value. Note that EEPROM_LNA 7026 * is never validated. 7027 */ 7028 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word); 7029 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); 7030 7031 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word); 7032 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) 7033 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); 7034 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) 7035 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); 7036 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); 7037 7038 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev); 7039 7040 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word); 7041 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) 7042 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); 7043 if (!rt2x00_rt(rt2x00dev, RT3593)) { 7044 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || 7045 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) 7046 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, 7047 default_lna_gain); 7048 } 7049 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); 7050 7051 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev); 7052 7053 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word); 7054 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) 7055 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); 7056 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) 7057 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); 7058 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); 7059 7060 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word); 7061 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) 7062 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); 7063 if (!rt2x00_rt(rt2x00dev, RT3593)) { 7064 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || 7065 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) 7066 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, 7067 default_lna_gain); 7068 } 7069 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); 7070 7071 if (rt2x00_rt(rt2x00dev, RT3593)) { 7072 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word); 7073 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 || 7074 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff) 7075 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 7076 default_lna_gain); 7077 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 || 7078 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff) 7079 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 7080 default_lna_gain); 7081 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word); 7082 } 7083 7084 return 0; 7085 } 7086 7087 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) 7088 { 7089 u16 value; 7090 u16 eeprom; 7091 u16 rf; 7092 7093 /* 7094 * Read EEPROM word for configuration. 7095 */ 7096 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 7097 7098 /* 7099 * Identify RF chipset by EEPROM value 7100 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 7101 * RT53xx: defined in "EEPROM_CHIP_ID" field 7102 */ 7103 if (rt2x00_rt(rt2x00dev, RT3290) || 7104 rt2x00_rt(rt2x00dev, RT5390) || 7105 rt2x00_rt(rt2x00dev, RT5392)) 7106 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf); 7107 else 7108 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 7109 7110 switch (rf) { 7111 case RF2820: 7112 case RF2850: 7113 case RF2720: 7114 case RF2750: 7115 case RF3020: 7116 case RF2020: 7117 case RF3021: 7118 case RF3022: 7119 case RF3052: 7120 case RF3053: 7121 case RF3070: 7122 case RF3290: 7123 case RF3320: 7124 case RF3322: 7125 case RF5360: 7126 case RF5362: 7127 case RF5370: 7128 case RF5372: 7129 case RF5390: 7130 case RF5392: 7131 case RF5592: 7132 break; 7133 default: 7134 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n", 7135 rf); 7136 return -ENODEV; 7137 } 7138 7139 rt2x00_set_rf(rt2x00dev, rf); 7140 7141 /* 7142 * Identify default antenna configuration. 7143 */ 7144 rt2x00dev->default_ant.tx_chain_num = 7145 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); 7146 rt2x00dev->default_ant.rx_chain_num = 7147 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); 7148 7149 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); 7150 7151 if (rt2x00_rt(rt2x00dev, RT3070) || 7152 rt2x00_rt(rt2x00dev, RT3090) || 7153 rt2x00_rt(rt2x00dev, RT3352) || 7154 rt2x00_rt(rt2x00dev, RT3390)) { 7155 value = rt2x00_get_field16(eeprom, 7156 EEPROM_NIC_CONF1_ANT_DIVERSITY); 7157 switch (value) { 7158 case 0: 7159 case 1: 7160 case 2: 7161 rt2x00dev->default_ant.tx = ANTENNA_A; 7162 rt2x00dev->default_ant.rx = ANTENNA_A; 7163 break; 7164 case 3: 7165 rt2x00dev->default_ant.tx = ANTENNA_A; 7166 rt2x00dev->default_ant.rx = ANTENNA_B; 7167 break; 7168 } 7169 } else { 7170 rt2x00dev->default_ant.tx = ANTENNA_A; 7171 rt2x00dev->default_ant.rx = ANTENNA_A; 7172 } 7173 7174 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) { 7175 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */ 7176 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */ 7177 } 7178 7179 /* 7180 * Determine external LNA informations. 7181 */ 7182 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G)) 7183 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); 7184 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G)) 7185 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); 7186 7187 /* 7188 * Detect if this device has an hardware controlled radio. 7189 */ 7190 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO)) 7191 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 7192 7193 /* 7194 * Detect if this device has Bluetooth co-existence. 7195 */ 7196 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) 7197 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); 7198 7199 /* 7200 * Read frequency offset and RF programming sequence. 7201 */ 7202 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); 7203 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 7204 7205 /* 7206 * Store led settings, for correct led behaviour. 7207 */ 7208 #ifdef CONFIG_RT2X00_LIB_LEDS 7209 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 7210 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 7211 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 7212 7213 rt2x00dev->led_mcu_reg = eeprom; 7214 #endif /* CONFIG_RT2X00_LIB_LEDS */ 7215 7216 /* 7217 * Check if support EIRP tx power limit feature. 7218 */ 7219 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom); 7220 7221 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < 7222 EIRP_MAX_TX_POWER_LIMIT) 7223 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); 7224 7225 return 0; 7226 } 7227 7228 /* 7229 * RF value list for rt28xx 7230 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) 7231 */ 7232 static const struct rf_channel rf_vals[] = { 7233 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, 7234 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, 7235 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, 7236 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, 7237 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, 7238 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, 7239 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, 7240 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, 7241 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, 7242 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, 7243 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, 7244 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, 7245 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, 7246 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, 7247 7248 /* 802.11 UNI / HyperLan 2 */ 7249 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, 7250 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, 7251 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, 7252 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, 7253 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, 7254 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, 7255 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, 7256 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, 7257 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, 7258 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, 7259 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, 7260 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, 7261 7262 /* 802.11 HyperLan 2 */ 7263 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, 7264 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, 7265 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, 7266 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, 7267 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, 7268 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, 7269 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, 7270 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, 7271 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, 7272 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, 7273 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, 7274 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, 7275 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, 7276 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, 7277 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, 7278 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, 7279 7280 /* 802.11 UNII */ 7281 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, 7282 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, 7283 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, 7284 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, 7285 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, 7286 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, 7287 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, 7288 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, 7289 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, 7290 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, 7291 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, 7292 7293 /* 802.11 Japan */ 7294 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, 7295 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, 7296 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, 7297 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, 7298 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, 7299 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, 7300 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, 7301 }; 7302 7303 /* 7304 * RF value list for rt3xxx 7305 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053) 7306 */ 7307 static const struct rf_channel rf_vals_3x[] = { 7308 {1, 241, 2, 2 }, 7309 {2, 241, 2, 7 }, 7310 {3, 242, 2, 2 }, 7311 {4, 242, 2, 7 }, 7312 {5, 243, 2, 2 }, 7313 {6, 243, 2, 7 }, 7314 {7, 244, 2, 2 }, 7315 {8, 244, 2, 7 }, 7316 {9, 245, 2, 2 }, 7317 {10, 245, 2, 7 }, 7318 {11, 246, 2, 2 }, 7319 {12, 246, 2, 7 }, 7320 {13, 247, 2, 2 }, 7321 {14, 248, 2, 4 }, 7322 7323 /* 802.11 UNI / HyperLan 2 */ 7324 {36, 0x56, 0, 4}, 7325 {38, 0x56, 0, 6}, 7326 {40, 0x56, 0, 8}, 7327 {44, 0x57, 0, 0}, 7328 {46, 0x57, 0, 2}, 7329 {48, 0x57, 0, 4}, 7330 {52, 0x57, 0, 8}, 7331 {54, 0x57, 0, 10}, 7332 {56, 0x58, 0, 0}, 7333 {60, 0x58, 0, 4}, 7334 {62, 0x58, 0, 6}, 7335 {64, 0x58, 0, 8}, 7336 7337 /* 802.11 HyperLan 2 */ 7338 {100, 0x5b, 0, 8}, 7339 {102, 0x5b, 0, 10}, 7340 {104, 0x5c, 0, 0}, 7341 {108, 0x5c, 0, 4}, 7342 {110, 0x5c, 0, 6}, 7343 {112, 0x5c, 0, 8}, 7344 {116, 0x5d, 0, 0}, 7345 {118, 0x5d, 0, 2}, 7346 {120, 0x5d, 0, 4}, 7347 {124, 0x5d, 0, 8}, 7348 {126, 0x5d, 0, 10}, 7349 {128, 0x5e, 0, 0}, 7350 {132, 0x5e, 0, 4}, 7351 {134, 0x5e, 0, 6}, 7352 {136, 0x5e, 0, 8}, 7353 {140, 0x5f, 0, 0}, 7354 7355 /* 802.11 UNII */ 7356 {149, 0x5f, 0, 9}, 7357 {151, 0x5f, 0, 11}, 7358 {153, 0x60, 0, 1}, 7359 {157, 0x60, 0, 5}, 7360 {159, 0x60, 0, 7}, 7361 {161, 0x60, 0, 9}, 7362 {165, 0x61, 0, 1}, 7363 {167, 0x61, 0, 3}, 7364 {169, 0x61, 0, 5}, 7365 {171, 0x61, 0, 7}, 7366 {173, 0x61, 0, 9}, 7367 }; 7368 7369 static const struct rf_channel rf_vals_5592_xtal20[] = { 7370 /* Channel, N, K, mod, R */ 7371 {1, 482, 4, 10, 3}, 7372 {2, 483, 4, 10, 3}, 7373 {3, 484, 4, 10, 3}, 7374 {4, 485, 4, 10, 3}, 7375 {5, 486, 4, 10, 3}, 7376 {6, 487, 4, 10, 3}, 7377 {7, 488, 4, 10, 3}, 7378 {8, 489, 4, 10, 3}, 7379 {9, 490, 4, 10, 3}, 7380 {10, 491, 4, 10, 3}, 7381 {11, 492, 4, 10, 3}, 7382 {12, 493, 4, 10, 3}, 7383 {13, 494, 4, 10, 3}, 7384 {14, 496, 8, 10, 3}, 7385 {36, 172, 8, 12, 1}, 7386 {38, 173, 0, 12, 1}, 7387 {40, 173, 4, 12, 1}, 7388 {42, 173, 8, 12, 1}, 7389 {44, 174, 0, 12, 1}, 7390 {46, 174, 4, 12, 1}, 7391 {48, 174, 8, 12, 1}, 7392 {50, 175, 0, 12, 1}, 7393 {52, 175, 4, 12, 1}, 7394 {54, 175, 8, 12, 1}, 7395 {56, 176, 0, 12, 1}, 7396 {58, 176, 4, 12, 1}, 7397 {60, 176, 8, 12, 1}, 7398 {62, 177, 0, 12, 1}, 7399 {64, 177, 4, 12, 1}, 7400 {100, 183, 4, 12, 1}, 7401 {102, 183, 8, 12, 1}, 7402 {104, 184, 0, 12, 1}, 7403 {106, 184, 4, 12, 1}, 7404 {108, 184, 8, 12, 1}, 7405 {110, 185, 0, 12, 1}, 7406 {112, 185, 4, 12, 1}, 7407 {114, 185, 8, 12, 1}, 7408 {116, 186, 0, 12, 1}, 7409 {118, 186, 4, 12, 1}, 7410 {120, 186, 8, 12, 1}, 7411 {122, 187, 0, 12, 1}, 7412 {124, 187, 4, 12, 1}, 7413 {126, 187, 8, 12, 1}, 7414 {128, 188, 0, 12, 1}, 7415 {130, 188, 4, 12, 1}, 7416 {132, 188, 8, 12, 1}, 7417 {134, 189, 0, 12, 1}, 7418 {136, 189, 4, 12, 1}, 7419 {138, 189, 8, 12, 1}, 7420 {140, 190, 0, 12, 1}, 7421 {149, 191, 6, 12, 1}, 7422 {151, 191, 10, 12, 1}, 7423 {153, 192, 2, 12, 1}, 7424 {155, 192, 6, 12, 1}, 7425 {157, 192, 10, 12, 1}, 7426 {159, 193, 2, 12, 1}, 7427 {161, 193, 6, 12, 1}, 7428 {165, 194, 2, 12, 1}, 7429 {184, 164, 0, 12, 1}, 7430 {188, 164, 4, 12, 1}, 7431 {192, 165, 8, 12, 1}, 7432 {196, 166, 0, 12, 1}, 7433 }; 7434 7435 static const struct rf_channel rf_vals_5592_xtal40[] = { 7436 /* Channel, N, K, mod, R */ 7437 {1, 241, 2, 10, 3}, 7438 {2, 241, 7, 10, 3}, 7439 {3, 242, 2, 10, 3}, 7440 {4, 242, 7, 10, 3}, 7441 {5, 243, 2, 10, 3}, 7442 {6, 243, 7, 10, 3}, 7443 {7, 244, 2, 10, 3}, 7444 {8, 244, 7, 10, 3}, 7445 {9, 245, 2, 10, 3}, 7446 {10, 245, 7, 10, 3}, 7447 {11, 246, 2, 10, 3}, 7448 {12, 246, 7, 10, 3}, 7449 {13, 247, 2, 10, 3}, 7450 {14, 248, 4, 10, 3}, 7451 {36, 86, 4, 12, 1}, 7452 {38, 86, 6, 12, 1}, 7453 {40, 86, 8, 12, 1}, 7454 {42, 86, 10, 12, 1}, 7455 {44, 87, 0, 12, 1}, 7456 {46, 87, 2, 12, 1}, 7457 {48, 87, 4, 12, 1}, 7458 {50, 87, 6, 12, 1}, 7459 {52, 87, 8, 12, 1}, 7460 {54, 87, 10, 12, 1}, 7461 {56, 88, 0, 12, 1}, 7462 {58, 88, 2, 12, 1}, 7463 {60, 88, 4, 12, 1}, 7464 {62, 88, 6, 12, 1}, 7465 {64, 88, 8, 12, 1}, 7466 {100, 91, 8, 12, 1}, 7467 {102, 91, 10, 12, 1}, 7468 {104, 92, 0, 12, 1}, 7469 {106, 92, 2, 12, 1}, 7470 {108, 92, 4, 12, 1}, 7471 {110, 92, 6, 12, 1}, 7472 {112, 92, 8, 12, 1}, 7473 {114, 92, 10, 12, 1}, 7474 {116, 93, 0, 12, 1}, 7475 {118, 93, 2, 12, 1}, 7476 {120, 93, 4, 12, 1}, 7477 {122, 93, 6, 12, 1}, 7478 {124, 93, 8, 12, 1}, 7479 {126, 93, 10, 12, 1}, 7480 {128, 94, 0, 12, 1}, 7481 {130, 94, 2, 12, 1}, 7482 {132, 94, 4, 12, 1}, 7483 {134, 94, 6, 12, 1}, 7484 {136, 94, 8, 12, 1}, 7485 {138, 94, 10, 12, 1}, 7486 {140, 95, 0, 12, 1}, 7487 {149, 95, 9, 12, 1}, 7488 {151, 95, 11, 12, 1}, 7489 {153, 96, 1, 12, 1}, 7490 {155, 96, 3, 12, 1}, 7491 {157, 96, 5, 12, 1}, 7492 {159, 96, 7, 12, 1}, 7493 {161, 96, 9, 12, 1}, 7494 {165, 97, 1, 12, 1}, 7495 {184, 82, 0, 12, 1}, 7496 {188, 82, 4, 12, 1}, 7497 {192, 82, 8, 12, 1}, 7498 {196, 83, 0, 12, 1}, 7499 }; 7500 7501 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 7502 { 7503 struct hw_mode_spec *spec = &rt2x00dev->spec; 7504 struct channel_info *info; 7505 char *default_power1; 7506 char *default_power2; 7507 char *default_power3; 7508 unsigned int i, tx_chains, rx_chains; 7509 u32 reg; 7510 7511 /* 7512 * Disable powersaving as default. 7513 */ 7514 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 7515 7516 /* 7517 * Initialize all hw fields. 7518 */ 7519 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS); 7520 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION); 7521 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); 7522 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); 7523 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); 7524 7525 /* 7526 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices 7527 * unless we are capable of sending the buffered frames out after the 7528 * DTIM transmission using rt2x00lib_beacondone. This will send out 7529 * multicast and broadcast traffic immediately instead of buffering it 7530 * infinitly and thus dropping it after some time. 7531 */ 7532 if (!rt2x00_is_usb(rt2x00dev)) 7533 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); 7534 7535 /* Set MFP if HW crypto is disabled. */ 7536 if (rt2800_hwcrypt_disabled(rt2x00dev)) 7537 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE); 7538 7539 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 7540 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 7541 rt2800_eeprom_addr(rt2x00dev, 7542 EEPROM_MAC_ADDR_0)); 7543 7544 /* 7545 * As rt2800 has a global fallback table we cannot specify 7546 * more then one tx rate per frame but since the hw will 7547 * try several rates (based on the fallback table) we should 7548 * initialize max_report_rates to the maximum number of rates 7549 * we are going to try. Otherwise mac80211 will truncate our 7550 * reported tx rates and the rc algortihm will end up with 7551 * incorrect data. 7552 */ 7553 rt2x00dev->hw->max_rates = 1; 7554 rt2x00dev->hw->max_report_rates = 7; 7555 rt2x00dev->hw->max_rate_tries = 1; 7556 7557 /* 7558 * Initialize hw_mode information. 7559 */ 7560 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 7561 7562 switch (rt2x00dev->chip.rf) { 7563 case RF2720: 7564 case RF2820: 7565 spec->num_channels = 14; 7566 spec->channels = rf_vals; 7567 break; 7568 7569 case RF2750: 7570 case RF2850: 7571 spec->num_channels = ARRAY_SIZE(rf_vals); 7572 spec->channels = rf_vals; 7573 break; 7574 7575 case RF2020: 7576 case RF3020: 7577 case RF3021: 7578 case RF3022: 7579 case RF3070: 7580 case RF3290: 7581 case RF3320: 7582 case RF3322: 7583 case RF5360: 7584 case RF5362: 7585 case RF5370: 7586 case RF5372: 7587 case RF5390: 7588 case RF5392: 7589 spec->num_channels = 14; 7590 spec->channels = rf_vals_3x; 7591 break; 7592 7593 case RF3052: 7594 case RF3053: 7595 spec->num_channels = ARRAY_SIZE(rf_vals_3x); 7596 spec->channels = rf_vals_3x; 7597 break; 7598 7599 case RF5592: 7600 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, ®); 7601 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { 7602 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); 7603 spec->channels = rf_vals_5592_xtal40; 7604 } else { 7605 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20); 7606 spec->channels = rf_vals_5592_xtal20; 7607 } 7608 break; 7609 } 7610 7611 if (WARN_ON_ONCE(!spec->channels)) 7612 return -ENODEV; 7613 7614 spec->supported_bands = SUPPORT_BAND_2GHZ; 7615 if (spec->num_channels > 14) 7616 spec->supported_bands |= SUPPORT_BAND_5GHZ; 7617 7618 /* 7619 * Initialize HT information. 7620 */ 7621 if (!rt2x00_rf(rt2x00dev, RF2020)) 7622 spec->ht.ht_supported = true; 7623 else 7624 spec->ht.ht_supported = false; 7625 7626 spec->ht.cap = 7627 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 7628 IEEE80211_HT_CAP_GRN_FLD | 7629 IEEE80211_HT_CAP_SGI_20 | 7630 IEEE80211_HT_CAP_SGI_40; 7631 7632 tx_chains = rt2x00dev->default_ant.tx_chain_num; 7633 rx_chains = rt2x00dev->default_ant.rx_chain_num; 7634 7635 if (tx_chains >= 2) 7636 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; 7637 7638 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT; 7639 7640 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2; 7641 spec->ht.ampdu_density = 4; 7642 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 7643 if (tx_chains != rx_chains) { 7644 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 7645 spec->ht.mcs.tx_params |= 7646 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; 7647 } 7648 7649 switch (rx_chains) { 7650 case 3: 7651 spec->ht.mcs.rx_mask[2] = 0xff; 7652 case 2: 7653 spec->ht.mcs.rx_mask[1] = 0xff; 7654 case 1: 7655 spec->ht.mcs.rx_mask[0] = 0xff; 7656 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ 7657 break; 7658 } 7659 7660 /* 7661 * Create channel information array 7662 */ 7663 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 7664 if (!info) 7665 return -ENOMEM; 7666 7667 spec->channels_info = info; 7668 7669 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 7670 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 7671 7672 if (rt2x00dev->default_ant.tx_chain_num > 2) 7673 default_power3 = rt2800_eeprom_addr(rt2x00dev, 7674 EEPROM_EXT_TXPOWER_BG3); 7675 else 7676 default_power3 = NULL; 7677 7678 for (i = 0; i < 14; i++) { 7679 info[i].default_power1 = default_power1[i]; 7680 info[i].default_power2 = default_power2[i]; 7681 if (default_power3) 7682 info[i].default_power3 = default_power3[i]; 7683 } 7684 7685 if (spec->num_channels > 14) { 7686 default_power1 = rt2800_eeprom_addr(rt2x00dev, 7687 EEPROM_TXPOWER_A1); 7688 default_power2 = rt2800_eeprom_addr(rt2x00dev, 7689 EEPROM_TXPOWER_A2); 7690 7691 if (rt2x00dev->default_ant.tx_chain_num > 2) 7692 default_power3 = 7693 rt2800_eeprom_addr(rt2x00dev, 7694 EEPROM_EXT_TXPOWER_A3); 7695 else 7696 default_power3 = NULL; 7697 7698 for (i = 14; i < spec->num_channels; i++) { 7699 info[i].default_power1 = default_power1[i - 14]; 7700 info[i].default_power2 = default_power2[i - 14]; 7701 if (default_power3) 7702 info[i].default_power3 = default_power3[i - 14]; 7703 } 7704 } 7705 7706 switch (rt2x00dev->chip.rf) { 7707 case RF2020: 7708 case RF3020: 7709 case RF3021: 7710 case RF3022: 7711 case RF3320: 7712 case RF3052: 7713 case RF3053: 7714 case RF3070: 7715 case RF3290: 7716 case RF5360: 7717 case RF5362: 7718 case RF5370: 7719 case RF5372: 7720 case RF5390: 7721 case RF5392: 7722 case RF5592: 7723 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags); 7724 break; 7725 } 7726 7727 return 0; 7728 } 7729 7730 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) 7731 { 7732 u32 reg; 7733 u32 rt; 7734 u32 rev; 7735 7736 if (rt2x00_rt(rt2x00dev, RT3290)) 7737 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, ®); 7738 else 7739 rt2800_register_read(rt2x00dev, MAC_CSR0, ®); 7740 7741 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); 7742 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); 7743 7744 switch (rt) { 7745 case RT2860: 7746 case RT2872: 7747 case RT2883: 7748 case RT3070: 7749 case RT3071: 7750 case RT3090: 7751 case RT3290: 7752 case RT3352: 7753 case RT3390: 7754 case RT3572: 7755 case RT3593: 7756 case RT5390: 7757 case RT5392: 7758 case RT5592: 7759 break; 7760 default: 7761 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n", 7762 rt, rev); 7763 return -ENODEV; 7764 } 7765 7766 rt2x00_set_rt(rt2x00dev, rt, rev); 7767 7768 return 0; 7769 } 7770 7771 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) 7772 { 7773 int retval; 7774 u32 reg; 7775 7776 retval = rt2800_probe_rt(rt2x00dev); 7777 if (retval) 7778 return retval; 7779 7780 /* 7781 * Allocate eeprom data. 7782 */ 7783 retval = rt2800_validate_eeprom(rt2x00dev); 7784 if (retval) 7785 return retval; 7786 7787 retval = rt2800_init_eeprom(rt2x00dev); 7788 if (retval) 7789 return retval; 7790 7791 /* 7792 * Enable rfkill polling by setting GPIO direction of the 7793 * rfkill switch GPIO pin correctly. 7794 */ 7795 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 7796 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); 7797 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 7798 7799 /* 7800 * Initialize hw specifications. 7801 */ 7802 retval = rt2800_probe_hw_mode(rt2x00dev); 7803 if (retval) 7804 return retval; 7805 7806 /* 7807 * Set device capabilities. 7808 */ 7809 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); 7810 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags); 7811 if (!rt2x00_is_usb(rt2x00dev)) 7812 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags); 7813 7814 /* 7815 * Set device requirements. 7816 */ 7817 if (!rt2x00_is_soc(rt2x00dev)) 7818 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); 7819 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags); 7820 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags); 7821 if (!rt2800_hwcrypt_disabled(rt2x00dev)) 7822 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); 7823 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 7824 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags); 7825 if (rt2x00_is_usb(rt2x00dev)) 7826 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); 7827 else { 7828 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); 7829 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags); 7830 } 7831 7832 /* 7833 * Set the rssi offset. 7834 */ 7835 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 7836 7837 return 0; 7838 } 7839 EXPORT_SYMBOL_GPL(rt2800_probe_hw); 7840 7841 /* 7842 * IEEE80211 stack callback functions. 7843 */ 7844 void rt2800_get_key_seq(struct ieee80211_hw *hw, 7845 struct ieee80211_key_conf *key, 7846 struct ieee80211_key_seq *seq) 7847 { 7848 struct rt2x00_dev *rt2x00dev = hw->priv; 7849 struct mac_iveiv_entry iveiv_entry; 7850 u32 offset; 7851 7852 if (key->cipher != WLAN_CIPHER_SUITE_TKIP) 7853 return; 7854 7855 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 7856 rt2800_register_multiread(rt2x00dev, offset, 7857 &iveiv_entry, sizeof(iveiv_entry)); 7858 7859 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2); 7860 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4); 7861 } 7862 EXPORT_SYMBOL_GPL(rt2800_get_key_seq); 7863 7864 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) 7865 { 7866 struct rt2x00_dev *rt2x00dev = hw->priv; 7867 u32 reg; 7868 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); 7869 7870 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); 7871 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); 7872 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 7873 7874 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); 7875 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); 7876 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 7877 7878 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); 7879 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); 7880 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 7881 7882 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); 7883 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); 7884 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 7885 7886 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); 7887 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); 7888 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 7889 7890 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); 7891 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); 7892 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 7893 7894 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); 7895 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); 7896 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 7897 7898 return 0; 7899 } 7900 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold); 7901 7902 int rt2800_conf_tx(struct ieee80211_hw *hw, 7903 struct ieee80211_vif *vif, u16 queue_idx, 7904 const struct ieee80211_tx_queue_params *params) 7905 { 7906 struct rt2x00_dev *rt2x00dev = hw->priv; 7907 struct data_queue *queue; 7908 struct rt2x00_field32 field; 7909 int retval; 7910 u32 reg; 7911 u32 offset; 7912 7913 /* 7914 * First pass the configuration through rt2x00lib, that will 7915 * update the queue settings and validate the input. After that 7916 * we are free to update the registers based on the value 7917 * in the queue parameter. 7918 */ 7919 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params); 7920 if (retval) 7921 return retval; 7922 7923 /* 7924 * We only need to perform additional register initialization 7925 * for WMM queues/ 7926 */ 7927 if (queue_idx >= 4) 7928 return 0; 7929 7930 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 7931 7932 /* Update WMM TXOP register */ 7933 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); 7934 field.bit_offset = (queue_idx & 1) * 16; 7935 field.bit_mask = 0xffff << field.bit_offset; 7936 7937 rt2800_register_read(rt2x00dev, offset, ®); 7938 rt2x00_set_field32(®, field, queue->txop); 7939 rt2800_register_write(rt2x00dev, offset, reg); 7940 7941 /* Update WMM registers */ 7942 field.bit_offset = queue_idx * 4; 7943 field.bit_mask = 0xf << field.bit_offset; 7944 7945 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®); 7946 rt2x00_set_field32(®, field, queue->aifs); 7947 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); 7948 7949 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®); 7950 rt2x00_set_field32(®, field, queue->cw_min); 7951 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); 7952 7953 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®); 7954 rt2x00_set_field32(®, field, queue->cw_max); 7955 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); 7956 7957 /* Update EDCA registers */ 7958 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); 7959 7960 rt2800_register_read(rt2x00dev, offset, ®); 7961 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); 7962 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); 7963 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); 7964 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); 7965 rt2800_register_write(rt2x00dev, offset, reg); 7966 7967 return 0; 7968 } 7969 EXPORT_SYMBOL_GPL(rt2800_conf_tx); 7970 7971 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 7972 { 7973 struct rt2x00_dev *rt2x00dev = hw->priv; 7974 u64 tsf; 7975 u32 reg; 7976 7977 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®); 7978 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; 7979 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®); 7980 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); 7981 7982 return tsf; 7983 } 7984 EXPORT_SYMBOL_GPL(rt2800_get_tsf); 7985 7986 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 7987 struct ieee80211_ampdu_params *params) 7988 { 7989 struct ieee80211_sta *sta = params->sta; 7990 enum ieee80211_ampdu_mlme_action action = params->action; 7991 u16 tid = params->tid; 7992 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv; 7993 int ret = 0; 7994 7995 /* 7996 * Don't allow aggregation for stations the hardware isn't aware 7997 * of because tx status reports for frames to an unknown station 7998 * always contain wcid=WCID_END+1 and thus we can't distinguish 7999 * between multiple stations which leads to unwanted situations 8000 * when the hw reorders frames due to aggregation. 8001 */ 8002 if (sta_priv->wcid > WCID_END) 8003 return 1; 8004 8005 switch (action) { 8006 case IEEE80211_AMPDU_RX_START: 8007 case IEEE80211_AMPDU_RX_STOP: 8008 /* 8009 * The hw itself takes care of setting up BlockAck mechanisms. 8010 * So, we only have to allow mac80211 to nagotiate a BlockAck 8011 * agreement. Once that is done, the hw will BlockAck incoming 8012 * AMPDUs without further setup. 8013 */ 8014 break; 8015 case IEEE80211_AMPDU_TX_START: 8016 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 8017 break; 8018 case IEEE80211_AMPDU_TX_STOP_CONT: 8019 case IEEE80211_AMPDU_TX_STOP_FLUSH: 8020 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 8021 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 8022 break; 8023 case IEEE80211_AMPDU_TX_OPERATIONAL: 8024 break; 8025 default: 8026 rt2x00_warn((struct rt2x00_dev *)hw->priv, 8027 "Unknown AMPDU action\n"); 8028 } 8029 8030 return ret; 8031 } 8032 EXPORT_SYMBOL_GPL(rt2800_ampdu_action); 8033 8034 int rt2800_get_survey(struct ieee80211_hw *hw, int idx, 8035 struct survey_info *survey) 8036 { 8037 struct rt2x00_dev *rt2x00dev = hw->priv; 8038 struct ieee80211_conf *conf = &hw->conf; 8039 u32 idle, busy, busy_ext; 8040 8041 if (idx != 0) 8042 return -ENOENT; 8043 8044 survey->channel = conf->chandef.chan; 8045 8046 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle); 8047 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy); 8048 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext); 8049 8050 if (idle || busy) { 8051 survey->filled = SURVEY_INFO_TIME | 8052 SURVEY_INFO_TIME_BUSY | 8053 SURVEY_INFO_TIME_EXT_BUSY; 8054 8055 survey->time = (idle + busy) / 1000; 8056 survey->time_busy = busy / 1000; 8057 survey->time_ext_busy = busy_ext / 1000; 8058 } 8059 8060 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 8061 survey->filled |= SURVEY_INFO_IN_USE; 8062 8063 return 0; 8064 8065 } 8066 EXPORT_SYMBOL_GPL(rt2800_get_survey); 8067 8068 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); 8069 MODULE_VERSION(DRV_VERSION); 8070 MODULE_DESCRIPTION("Ralink RT2800 library"); 8071 MODULE_LICENSE("GPL"); 8072