1 /* 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> 6 7 Based on the original rt2800pci.c and rt2800usb.c. 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 14 <http://rt2x00.serialmonkey.com> 15 16 This program is free software; you can redistribute it and/or modify 17 it under the terms of the GNU General Public License as published by 18 the Free Software Foundation; either version 2 of the License, or 19 (at your option) any later version. 20 21 This program is distributed in the hope that it will be useful, 22 but WITHOUT ANY WARRANTY; without even the implied warranty of 23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 GNU General Public License for more details. 25 26 You should have received a copy of the GNU General Public License 27 along with this program; if not, see <http://www.gnu.org/licenses/>. 28 */ 29 30 /* 31 Module: rt2800lib 32 Abstract: rt2800 generic device routines. 33 */ 34 35 #include <linux/crc-ccitt.h> 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/slab.h> 39 40 #include "rt2x00.h" 41 #include "rt2800lib.h" 42 #include "rt2800.h" 43 44 /* 45 * Register access. 46 * All access to the CSR registers will go through the methods 47 * rt2800_register_read and rt2800_register_write. 48 * BBP and RF register require indirect register access, 49 * and use the CSR registers BBPCSR and RFCSR to achieve this. 50 * These indirect registers work with busy bits, 51 * and we will try maximal REGISTER_BUSY_COUNT times to access 52 * the register while taking a REGISTER_BUSY_DELAY us delay 53 * between each attampt. When the busy bit is still set at that time, 54 * the access attempt is considered to have failed, 55 * and we will print an error. 56 * The _lock versions must be used if you already hold the csr_mutex 57 */ 58 #define WAIT_FOR_BBP(__dev, __reg) \ 59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) 60 #define WAIT_FOR_RFCSR(__dev, __reg) \ 61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) 62 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \ 63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \ 64 (__reg)) 65 #define WAIT_FOR_RF(__dev, __reg) \ 66 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) 67 #define WAIT_FOR_MCU(__dev, __reg) \ 68 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 69 H2M_MAILBOX_CSR_OWNER, (__reg)) 70 71 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) 72 { 73 /* check for rt2872 on SoC */ 74 if (!rt2x00_is_soc(rt2x00dev) || 75 !rt2x00_rt(rt2x00dev, RT2872)) 76 return false; 77 78 /* we know for sure that these rf chipsets are used on rt305x boards */ 79 if (rt2x00_rf(rt2x00dev, RF3020) || 80 rt2x00_rf(rt2x00dev, RF3021) || 81 rt2x00_rf(rt2x00dev, RF3022)) 82 return true; 83 84 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n"); 85 return false; 86 } 87 88 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, 89 const unsigned int word, const u8 value) 90 { 91 u32 reg; 92 93 mutex_lock(&rt2x00dev->csr_mutex); 94 95 /* 96 * Wait until the BBP becomes available, afterwards we 97 * can safely write the new data into the register. 98 */ 99 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 100 reg = 0; 101 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); 102 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 103 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 104 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); 105 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 106 107 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 108 } 109 110 mutex_unlock(&rt2x00dev->csr_mutex); 111 } 112 113 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word) 114 { 115 u32 reg; 116 u8 value; 117 118 mutex_lock(&rt2x00dev->csr_mutex); 119 120 /* 121 * Wait until the BBP becomes available, afterwards we 122 * can safely write the read request into the register. 123 * After the data has been written, we wait until hardware 124 * returns the correct value, if at any time the register 125 * doesn't become available in time, reg will be 0xffffffff 126 * which means we return 0xff to the caller. 127 */ 128 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 129 reg = 0; 130 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 131 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 132 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); 133 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 134 135 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 136 137 WAIT_FOR_BBP(rt2x00dev, ®); 138 } 139 140 value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); 141 142 mutex_unlock(&rt2x00dev->csr_mutex); 143 144 return value; 145 } 146 147 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, 148 const unsigned int word, const u8 value) 149 { 150 u32 reg; 151 152 mutex_lock(&rt2x00dev->csr_mutex); 153 154 /* 155 * Wait until the RFCSR becomes available, afterwards we 156 * can safely write the new data into the register. 157 */ 158 switch (rt2x00dev->chip.rt) { 159 case RT6352: 160 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 161 reg = 0; 162 rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value); 163 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 164 word); 165 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1); 166 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 167 168 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 169 } 170 break; 171 172 default: 173 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 174 reg = 0; 175 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); 176 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 177 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); 178 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 179 180 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 181 } 182 break; 183 } 184 185 mutex_unlock(&rt2x00dev->csr_mutex); 186 } 187 188 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 189 const unsigned int reg, const u8 value) 190 { 191 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value); 192 } 193 194 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev, 195 const unsigned int reg, const u8 value) 196 { 197 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value); 198 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value); 199 } 200 201 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev, 202 const unsigned int reg, const u8 value) 203 { 204 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value); 205 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value); 206 } 207 208 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, 209 const unsigned int word) 210 { 211 u32 reg; 212 u8 value; 213 214 mutex_lock(&rt2x00dev->csr_mutex); 215 216 /* 217 * Wait until the RFCSR becomes available, afterwards we 218 * can safely write the read request into the register. 219 * After the data has been written, we wait until hardware 220 * returns the correct value, if at any time the register 221 * doesn't become available in time, reg will be 0xffffffff 222 * which means we return 0xff to the caller. 223 */ 224 switch (rt2x00dev->chip.rt) { 225 case RT6352: 226 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 227 reg = 0; 228 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 229 word); 230 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0); 231 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 232 233 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 234 235 WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®); 236 } 237 238 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620); 239 break; 240 241 default: 242 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 243 reg = 0; 244 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 245 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); 246 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 247 248 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 249 250 WAIT_FOR_RFCSR(rt2x00dev, ®); 251 } 252 253 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); 254 break; 255 } 256 257 mutex_unlock(&rt2x00dev->csr_mutex); 258 259 return value; 260 } 261 262 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 263 const unsigned int reg) 264 { 265 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6))); 266 } 267 268 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, 269 const unsigned int word, const u32 value) 270 { 271 u32 reg; 272 273 mutex_lock(&rt2x00dev->csr_mutex); 274 275 /* 276 * Wait until the RF becomes available, afterwards we 277 * can safely write the new data into the register. 278 */ 279 if (WAIT_FOR_RF(rt2x00dev, ®)) { 280 reg = 0; 281 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); 282 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); 283 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); 284 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); 285 286 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); 287 rt2x00_rf_write(rt2x00dev, word, value); 288 } 289 290 mutex_unlock(&rt2x00dev->csr_mutex); 291 } 292 293 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { 294 [EEPROM_CHIP_ID] = 0x0000, 295 [EEPROM_VERSION] = 0x0001, 296 [EEPROM_MAC_ADDR_0] = 0x0002, 297 [EEPROM_MAC_ADDR_1] = 0x0003, 298 [EEPROM_MAC_ADDR_2] = 0x0004, 299 [EEPROM_NIC_CONF0] = 0x001a, 300 [EEPROM_NIC_CONF1] = 0x001b, 301 [EEPROM_FREQ] = 0x001d, 302 [EEPROM_LED_AG_CONF] = 0x001e, 303 [EEPROM_LED_ACT_CONF] = 0x001f, 304 [EEPROM_LED_POLARITY] = 0x0020, 305 [EEPROM_NIC_CONF2] = 0x0021, 306 [EEPROM_LNA] = 0x0022, 307 [EEPROM_RSSI_BG] = 0x0023, 308 [EEPROM_RSSI_BG2] = 0x0024, 309 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */ 310 [EEPROM_RSSI_A] = 0x0025, 311 [EEPROM_RSSI_A2] = 0x0026, 312 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */ 313 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027, 314 [EEPROM_TXPOWER_DELTA] = 0x0028, 315 [EEPROM_TXPOWER_BG1] = 0x0029, 316 [EEPROM_TXPOWER_BG2] = 0x0030, 317 [EEPROM_TSSI_BOUND_BG1] = 0x0037, 318 [EEPROM_TSSI_BOUND_BG2] = 0x0038, 319 [EEPROM_TSSI_BOUND_BG3] = 0x0039, 320 [EEPROM_TSSI_BOUND_BG4] = 0x003a, 321 [EEPROM_TSSI_BOUND_BG5] = 0x003b, 322 [EEPROM_TXPOWER_A1] = 0x003c, 323 [EEPROM_TXPOWER_A2] = 0x0053, 324 [EEPROM_TXPOWER_INIT] = 0x0068, 325 [EEPROM_TSSI_BOUND_A1] = 0x006a, 326 [EEPROM_TSSI_BOUND_A2] = 0x006b, 327 [EEPROM_TSSI_BOUND_A3] = 0x006c, 328 [EEPROM_TSSI_BOUND_A4] = 0x006d, 329 [EEPROM_TSSI_BOUND_A5] = 0x006e, 330 [EEPROM_TXPOWER_BYRATE] = 0x006f, 331 [EEPROM_BBP_START] = 0x0078, 332 }; 333 334 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = { 335 [EEPROM_CHIP_ID] = 0x0000, 336 [EEPROM_VERSION] = 0x0001, 337 [EEPROM_MAC_ADDR_0] = 0x0002, 338 [EEPROM_MAC_ADDR_1] = 0x0003, 339 [EEPROM_MAC_ADDR_2] = 0x0004, 340 [EEPROM_NIC_CONF0] = 0x001a, 341 [EEPROM_NIC_CONF1] = 0x001b, 342 [EEPROM_NIC_CONF2] = 0x001c, 343 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020, 344 [EEPROM_FREQ] = 0x0022, 345 [EEPROM_LED_AG_CONF] = 0x0023, 346 [EEPROM_LED_ACT_CONF] = 0x0024, 347 [EEPROM_LED_POLARITY] = 0x0025, 348 [EEPROM_LNA] = 0x0026, 349 [EEPROM_EXT_LNA2] = 0x0027, 350 [EEPROM_RSSI_BG] = 0x0028, 351 [EEPROM_RSSI_BG2] = 0x0029, 352 [EEPROM_RSSI_A] = 0x002a, 353 [EEPROM_RSSI_A2] = 0x002b, 354 [EEPROM_TXPOWER_BG1] = 0x0030, 355 [EEPROM_TXPOWER_BG2] = 0x0037, 356 [EEPROM_EXT_TXPOWER_BG3] = 0x003e, 357 [EEPROM_TSSI_BOUND_BG1] = 0x0045, 358 [EEPROM_TSSI_BOUND_BG2] = 0x0046, 359 [EEPROM_TSSI_BOUND_BG3] = 0x0047, 360 [EEPROM_TSSI_BOUND_BG4] = 0x0048, 361 [EEPROM_TSSI_BOUND_BG5] = 0x0049, 362 [EEPROM_TXPOWER_A1] = 0x004b, 363 [EEPROM_TXPOWER_A2] = 0x0065, 364 [EEPROM_EXT_TXPOWER_A3] = 0x007f, 365 [EEPROM_TSSI_BOUND_A1] = 0x009a, 366 [EEPROM_TSSI_BOUND_A2] = 0x009b, 367 [EEPROM_TSSI_BOUND_A3] = 0x009c, 368 [EEPROM_TSSI_BOUND_A4] = 0x009d, 369 [EEPROM_TSSI_BOUND_A5] = 0x009e, 370 [EEPROM_TXPOWER_BYRATE] = 0x00a0, 371 }; 372 373 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev, 374 const enum rt2800_eeprom_word word) 375 { 376 const unsigned int *map; 377 unsigned int index; 378 379 if (WARN_ONCE(word >= EEPROM_WORD_COUNT, 380 "%s: invalid EEPROM word %d\n", 381 wiphy_name(rt2x00dev->hw->wiphy), word)) 382 return 0; 383 384 if (rt2x00_rt(rt2x00dev, RT3593)) 385 map = rt2800_eeprom_map_ext; 386 else 387 map = rt2800_eeprom_map; 388 389 index = map[word]; 390 391 /* Index 0 is valid only for EEPROM_CHIP_ID. 392 * Otherwise it means that the offset of the 393 * given word is not initialized in the map, 394 * or that the field is not usable on the 395 * actual chipset. 396 */ 397 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0, 398 "%s: invalid access of EEPROM word %d\n", 399 wiphy_name(rt2x00dev->hw->wiphy), word); 400 401 return index; 402 } 403 404 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev, 405 const enum rt2800_eeprom_word word) 406 { 407 unsigned int index; 408 409 index = rt2800_eeprom_word_index(rt2x00dev, word); 410 return rt2x00_eeprom_addr(rt2x00dev, index); 411 } 412 413 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, 414 const enum rt2800_eeprom_word word) 415 { 416 unsigned int index; 417 418 index = rt2800_eeprom_word_index(rt2x00dev, word); 419 return rt2x00_eeprom_read(rt2x00dev, index); 420 } 421 422 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, 423 const enum rt2800_eeprom_word word, u16 data) 424 { 425 unsigned int index; 426 427 index = rt2800_eeprom_word_index(rt2x00dev, word); 428 rt2x00_eeprom_write(rt2x00dev, index, data); 429 } 430 431 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, 432 const enum rt2800_eeprom_word array, 433 unsigned int offset) 434 { 435 unsigned int index; 436 437 index = rt2800_eeprom_word_index(rt2x00dev, array); 438 return rt2x00_eeprom_read(rt2x00dev, index + offset); 439 } 440 441 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) 442 { 443 u32 reg; 444 int i, count; 445 446 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 447 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); 448 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); 449 rt2x00_set_field32(®, WLAN_CLK_EN, 0); 450 rt2x00_set_field32(®, WLAN_EN, 1); 451 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 452 453 udelay(REGISTER_BUSY_DELAY); 454 455 count = 0; 456 do { 457 /* 458 * Check PLL_LD & XTAL_RDY. 459 */ 460 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 461 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 462 if (rt2x00_get_field32(reg, PLL_LD) && 463 rt2x00_get_field32(reg, XTAL_RDY)) 464 break; 465 udelay(REGISTER_BUSY_DELAY); 466 } 467 468 if (i >= REGISTER_BUSY_COUNT) { 469 470 if (count >= 10) 471 return -EIO; 472 473 rt2800_register_write(rt2x00dev, 0x58, 0x018); 474 udelay(REGISTER_BUSY_DELAY); 475 rt2800_register_write(rt2x00dev, 0x58, 0x418); 476 udelay(REGISTER_BUSY_DELAY); 477 rt2800_register_write(rt2x00dev, 0x58, 0x618); 478 udelay(REGISTER_BUSY_DELAY); 479 count++; 480 } else { 481 count = 0; 482 } 483 484 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 485 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); 486 rt2x00_set_field32(®, WLAN_CLK_EN, 1); 487 rt2x00_set_field32(®, WLAN_RESET, 1); 488 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 489 udelay(10); 490 rt2x00_set_field32(®, WLAN_RESET, 0); 491 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 492 udelay(10); 493 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff); 494 } while (count != 0); 495 496 return 0; 497 } 498 499 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 500 const u8 command, const u8 token, 501 const u8 arg0, const u8 arg1) 502 { 503 u32 reg; 504 505 /* 506 * SOC devices don't support MCU requests. 507 */ 508 if (rt2x00_is_soc(rt2x00dev)) 509 return; 510 511 mutex_lock(&rt2x00dev->csr_mutex); 512 513 /* 514 * Wait until the MCU becomes available, afterwards we 515 * can safely write the new data into the register. 516 */ 517 if (WAIT_FOR_MCU(rt2x00dev, ®)) { 518 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); 519 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); 520 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); 521 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); 522 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); 523 524 reg = 0; 525 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); 526 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); 527 } 528 529 mutex_unlock(&rt2x00dev->csr_mutex); 530 } 531 EXPORT_SYMBOL_GPL(rt2800_mcu_request); 532 533 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) 534 { 535 unsigned int i = 0; 536 u32 reg; 537 538 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 539 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 540 if (reg && reg != ~0) 541 return 0; 542 msleep(1); 543 } 544 545 rt2x00_err(rt2x00dev, "Unstable hardware\n"); 546 return -EBUSY; 547 } 548 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); 549 550 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 551 { 552 unsigned int i; 553 u32 reg; 554 555 /* 556 * Some devices are really slow to respond here. Wait a whole second 557 * before timing out. 558 */ 559 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 560 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 561 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 562 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 563 return 0; 564 565 msleep(10); 566 } 567 568 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); 569 return -EACCES; 570 } 571 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); 572 573 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) 574 { 575 u32 reg; 576 577 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 578 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 579 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 580 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 581 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 582 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 583 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 584 } 585 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma); 586 587 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev, 588 unsigned short *txwi_size, 589 unsigned short *rxwi_size) 590 { 591 switch (rt2x00dev->chip.rt) { 592 case RT3593: 593 *txwi_size = TXWI_DESC_SIZE_4WORDS; 594 *rxwi_size = RXWI_DESC_SIZE_5WORDS; 595 break; 596 597 case RT5592: 598 case RT6352: 599 *txwi_size = TXWI_DESC_SIZE_5WORDS; 600 *rxwi_size = RXWI_DESC_SIZE_6WORDS; 601 break; 602 603 default: 604 *txwi_size = TXWI_DESC_SIZE_4WORDS; 605 *rxwi_size = RXWI_DESC_SIZE_4WORDS; 606 break; 607 } 608 } 609 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size); 610 611 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) 612 { 613 u16 fw_crc; 614 u16 crc; 615 616 /* 617 * The last 2 bytes in the firmware array are the crc checksum itself, 618 * this means that we should never pass those 2 bytes to the crc 619 * algorithm. 620 */ 621 fw_crc = (data[len - 2] << 8 | data[len - 1]); 622 623 /* 624 * Use the crc ccitt algorithm. 625 * This will return the same value as the legacy driver which 626 * used bit ordering reversion on the both the firmware bytes 627 * before input input as well as on the final output. 628 * Obviously using crc ccitt directly is much more efficient. 629 */ 630 crc = crc_ccitt(~0, data, len - 2); 631 632 /* 633 * There is a small difference between the crc-itu-t + bitrev and 634 * the crc-ccitt crc calculation. In the latter method the 2 bytes 635 * will be swapped, use swab16 to convert the crc to the correct 636 * value. 637 */ 638 crc = swab16(crc); 639 640 return fw_crc == crc; 641 } 642 643 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, 644 const u8 *data, const size_t len) 645 { 646 size_t offset = 0; 647 size_t fw_len; 648 bool multiple; 649 650 /* 651 * PCI(e) & SOC devices require firmware with a length 652 * of 8kb. USB devices require firmware files with a length 653 * of 4kb. Certain USB chipsets however require different firmware, 654 * which Ralink only provides attached to the original firmware 655 * file. Thus for USB devices, firmware files have a length 656 * which is a multiple of 4kb. The firmware for rt3290 chip also 657 * have a length which is a multiple of 4kb. 658 */ 659 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290)) 660 fw_len = 4096; 661 else 662 fw_len = 8192; 663 664 multiple = true; 665 /* 666 * Validate the firmware length 667 */ 668 if (len != fw_len && (!multiple || (len % fw_len) != 0)) 669 return FW_BAD_LENGTH; 670 671 /* 672 * Check if the chipset requires one of the upper parts 673 * of the firmware. 674 */ 675 if (rt2x00_is_usb(rt2x00dev) && 676 !rt2x00_rt(rt2x00dev, RT2860) && 677 !rt2x00_rt(rt2x00dev, RT2872) && 678 !rt2x00_rt(rt2x00dev, RT3070) && 679 ((len / fw_len) == 1)) 680 return FW_BAD_VERSION; 681 682 /* 683 * 8kb firmware files must be checked as if it were 684 * 2 separate firmware files. 685 */ 686 while (offset < len) { 687 if (!rt2800_check_firmware_crc(data + offset, fw_len)) 688 return FW_BAD_CRC; 689 690 offset += fw_len; 691 } 692 693 return FW_OK; 694 } 695 EXPORT_SYMBOL_GPL(rt2800_check_firmware); 696 697 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, 698 const u8 *data, const size_t len) 699 { 700 unsigned int i; 701 u32 reg; 702 int retval; 703 704 if (rt2x00_rt(rt2x00dev, RT3290)) { 705 retval = rt2800_enable_wlan_rt3290(rt2x00dev); 706 if (retval) 707 return -EBUSY; 708 } 709 710 /* 711 * If driver doesn't wake up firmware here, 712 * rt2800_load_firmware will hang forever when interface is up again. 713 */ 714 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 715 716 /* 717 * Wait for stable hardware. 718 */ 719 if (rt2800_wait_csr_ready(rt2x00dev)) 720 return -EBUSY; 721 722 if (rt2x00_is_pci(rt2x00dev)) { 723 if (rt2x00_rt(rt2x00dev, RT3290) || 724 rt2x00_rt(rt2x00dev, RT3572) || 725 rt2x00_rt(rt2x00dev, RT5390) || 726 rt2x00_rt(rt2x00dev, RT5392)) { 727 reg = rt2800_register_read(rt2x00dev, AUX_CTRL); 728 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); 729 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); 730 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); 731 } 732 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 733 } 734 735 rt2800_disable_wpdma(rt2x00dev); 736 737 /* 738 * Write firmware to the device. 739 */ 740 rt2800_drv_write_firmware(rt2x00dev, data, len); 741 742 /* 743 * Wait for device to stabilize. 744 */ 745 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 746 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL); 747 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 748 break; 749 msleep(1); 750 } 751 752 if (i == REGISTER_BUSY_COUNT) { 753 rt2x00_err(rt2x00dev, "PBF system register not ready\n"); 754 return -EBUSY; 755 } 756 757 /* 758 * Disable DMA, will be reenabled later when enabling 759 * the radio. 760 */ 761 rt2800_disable_wpdma(rt2x00dev); 762 763 /* 764 * Initialize firmware. 765 */ 766 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 767 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 768 if (rt2x00_is_usb(rt2x00dev)) { 769 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 770 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 771 } 772 msleep(1); 773 774 return 0; 775 } 776 EXPORT_SYMBOL_GPL(rt2800_load_firmware); 777 778 void rt2800_write_tx_data(struct queue_entry *entry, 779 struct txentry_desc *txdesc) 780 { 781 __le32 *txwi = rt2800_drv_get_txwi(entry); 782 u32 word; 783 int i; 784 785 /* 786 * Initialize TX Info descriptor 787 */ 788 word = rt2x00_desc_read(txwi, 0); 789 rt2x00_set_field32(&word, TXWI_W0_FRAG, 790 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 791 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 792 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); 793 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); 794 rt2x00_set_field32(&word, TXWI_W0_TS, 795 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 796 rt2x00_set_field32(&word, TXWI_W0_AMPDU, 797 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); 798 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, 799 txdesc->u.ht.mpdu_density); 800 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); 801 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); 802 rt2x00_set_field32(&word, TXWI_W0_BW, 803 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); 804 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, 805 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); 806 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); 807 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); 808 rt2x00_desc_write(txwi, 0, word); 809 810 word = rt2x00_desc_read(txwi, 1); 811 rt2x00_set_field32(&word, TXWI_W1_ACK, 812 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 813 rt2x00_set_field32(&word, TXWI_W1_NSEQ, 814 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 815 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); 816 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 817 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 818 txdesc->key_idx : txdesc->u.ht.wcid); 819 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 820 txdesc->length); 821 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); 822 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); 823 rt2x00_desc_write(txwi, 1, word); 824 825 /* 826 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert 827 * the IV from the IVEIV register when TXD_W3_WIV is set to 0. 828 * When TXD_W3_WIV is set to 1 it will use the IV data 829 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 830 * crypto entry in the registers should be used to encrypt the frame. 831 * 832 * Nulify all remaining words as well, we don't know how to program them. 833 */ 834 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++) 835 _rt2x00_desc_write(txwi, i, 0); 836 } 837 EXPORT_SYMBOL_GPL(rt2800_write_tx_data); 838 839 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) 840 { 841 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); 842 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); 843 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); 844 u16 eeprom; 845 u8 offset0; 846 u8 offset1; 847 u8 offset2; 848 849 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 850 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 851 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); 852 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); 853 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 854 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); 855 } else { 856 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 857 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); 858 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); 859 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 860 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); 861 } 862 863 /* 864 * Convert the value from the descriptor into the RSSI value 865 * If the value in the descriptor is 0, it is considered invalid 866 * and the default (extremely low) rssi value is assumed 867 */ 868 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128; 869 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128; 870 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128; 871 872 /* 873 * mac80211 only accepts a single RSSI value. Calculating the 874 * average doesn't deliver a fair answer either since -60:-60 would 875 * be considered equally good as -50:-70 while the second is the one 876 * which gives less energy... 877 */ 878 rssi0 = max(rssi0, rssi1); 879 return (int)max(rssi0, rssi2); 880 } 881 882 void rt2800_process_rxwi(struct queue_entry *entry, 883 struct rxdone_entry_desc *rxdesc) 884 { 885 __le32 *rxwi = (__le32 *) entry->skb->data; 886 u32 word; 887 888 word = rt2x00_desc_read(rxwi, 0); 889 890 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); 891 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); 892 893 word = rt2x00_desc_read(rxwi, 1); 894 895 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) 896 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI; 897 898 if (rt2x00_get_field32(word, RXWI_W1_BW)) 899 rxdesc->bw = RATE_INFO_BW_40; 900 901 /* 902 * Detect RX rate, always use MCS as signal type. 903 */ 904 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; 905 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); 906 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); 907 908 /* 909 * Mask of 0x8 bit to remove the short preamble flag. 910 */ 911 if (rxdesc->rate_mode == RATE_MODE_CCK) 912 rxdesc->signal &= ~0x8; 913 914 word = rt2x00_desc_read(rxwi, 2); 915 916 /* 917 * Convert descriptor AGC value to RSSI value. 918 */ 919 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); 920 /* 921 * Remove RXWI descriptor from start of the buffer. 922 */ 923 skb_pull(entry->skb, entry->queue->winfo_size); 924 } 925 EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 926 927 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc, 928 u32 status, enum nl80211_band band) 929 { 930 u8 flags = 0; 931 u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 932 933 switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) { 934 case RATE_MODE_HT_GREENFIELD: 935 flags |= IEEE80211_TX_RC_GREEN_FIELD; 936 /* fall through */ 937 case RATE_MODE_HT_MIX: 938 flags |= IEEE80211_TX_RC_MCS; 939 break; 940 case RATE_MODE_OFDM: 941 if (band == NL80211_BAND_2GHZ) 942 idx += 4; 943 break; 944 case RATE_MODE_CCK: 945 if (idx >= 8) 946 idx -= 8; 947 break; 948 } 949 950 if (rt2x00_get_field32(status, TX_STA_FIFO_BW)) 951 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 952 953 if (rt2x00_get_field32(status, TX_STA_FIFO_SGI)) 954 flags |= IEEE80211_TX_RC_SHORT_GI; 955 956 skbdesc->tx_rate_idx = idx; 957 skbdesc->tx_rate_flags = flags; 958 } 959 960 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi, 961 bool match) 962 { 963 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 964 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 965 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 966 struct txdone_entry_desc txdesc; 967 u32 word; 968 u16 mcs, real_mcs; 969 int aggr, ampdu, wcid, ack_req; 970 971 /* 972 * Obtain the status about this packet. 973 */ 974 txdesc.flags = 0; 975 word = rt2x00_desc_read(txwi, 0); 976 977 mcs = rt2x00_get_field32(word, TXWI_W0_MCS); 978 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); 979 980 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 981 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); 982 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID); 983 ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED); 984 985 /* 986 * If a frame was meant to be sent as a single non-aggregated MPDU 987 * but ended up in an aggregate the used tx rate doesn't correlate 988 * with the one specified in the TXWI as the whole aggregate is sent 989 * with the same rate. 990 * 991 * For example: two frames are sent to rt2x00, the first one sets 992 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 993 * and requests MCS15. If the hw aggregates both frames into one 994 * AMDPU the tx status for both frames will contain MCS7 although 995 * the frame was sent successfully. 996 * 997 * Hence, replace the requested rate with the real tx rate to not 998 * confuse the rate control algortihm by providing clearly wrong 999 * data. 1000 * 1001 * FIXME: if we do not find matching entry, we tell that frame was 1002 * posted without any retries. We need to find a way to fix that 1003 * and provide retry count. 1004 */ 1005 if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) { 1006 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band); 1007 mcs = real_mcs; 1008 } 1009 1010 if (aggr == 1 || ampdu == 1) 1011 __set_bit(TXDONE_AMPDU, &txdesc.flags); 1012 1013 if (!ack_req) 1014 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags); 1015 1016 /* 1017 * Ralink has a retry mechanism using a global fallback 1018 * table. We setup this fallback table to try the immediate 1019 * lower rate for all rates. In the TX_STA_FIFO, the MCS field 1020 * always contains the MCS used for the last transmission, be 1021 * it successful or not. 1022 */ 1023 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { 1024 /* 1025 * Transmission succeeded. The number of retries is 1026 * mcs - real_mcs 1027 */ 1028 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 1029 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); 1030 } else { 1031 /* 1032 * Transmission failed. The number of retries is 1033 * always 7 in this case (for a total number of 8 1034 * frames sent). 1035 */ 1036 __set_bit(TXDONE_FAILURE, &txdesc.flags); 1037 txdesc.retry = rt2x00dev->long_retry; 1038 } 1039 1040 /* 1041 * the frame was retried at least once 1042 * -> hw used fallback rates 1043 */ 1044 if (txdesc.retry) 1045 __set_bit(TXDONE_FALLBACK, &txdesc.flags); 1046 1047 if (!match) { 1048 /* RCU assures non-null sta will not be freed by mac80211. */ 1049 rcu_read_lock(); 1050 if (likely(wcid >= WCID_START && wcid <= WCID_END)) 1051 skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START]; 1052 else 1053 skbdesc->sta = NULL; 1054 rt2x00lib_txdone_nomatch(entry, &txdesc); 1055 rcu_read_unlock(); 1056 } else { 1057 rt2x00lib_txdone(entry, &txdesc); 1058 } 1059 } 1060 EXPORT_SYMBOL_GPL(rt2800_txdone_entry); 1061 1062 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev, 1063 unsigned int index) 1064 { 1065 return HW_BEACON_BASE(index); 1066 } 1067 1068 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev, 1069 unsigned int index) 1070 { 1071 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index)); 1072 } 1073 1074 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev) 1075 { 1076 struct data_queue *queue = rt2x00dev->bcn; 1077 struct queue_entry *entry; 1078 int i, bcn_num = 0; 1079 u64 off, reg = 0; 1080 u32 bssid_dw1; 1081 1082 /* 1083 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers. 1084 */ 1085 for (i = 0; i < queue->limit; i++) { 1086 entry = &queue->entries[i]; 1087 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags)) 1088 continue; 1089 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx); 1090 reg |= off << (8 * bcn_num); 1091 bcn_num++; 1092 } 1093 1094 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); 1095 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); 1096 1097 /* 1098 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons. 1099 */ 1100 bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1); 1101 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, 1102 bcn_num > 0 ? bcn_num - 1 : 0); 1103 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1); 1104 } 1105 1106 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) 1107 { 1108 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1109 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1110 unsigned int beacon_base; 1111 unsigned int padding_len; 1112 u32 orig_reg, reg; 1113 const int txwi_desc_size = entry->queue->winfo_size; 1114 1115 /* 1116 * Disable beaconing while we are reloading the beacon data, 1117 * otherwise we might be sending out invalid data. 1118 */ 1119 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1120 orig_reg = reg; 1121 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1122 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1123 1124 /* 1125 * Add space for the TXWI in front of the skb. 1126 */ 1127 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size); 1128 1129 /* 1130 * Register descriptor details in skb frame descriptor. 1131 */ 1132 skbdesc->flags |= SKBDESC_DESC_IN_SKB; 1133 skbdesc->desc = entry->skb->data; 1134 skbdesc->desc_len = txwi_desc_size; 1135 1136 /* 1137 * Add the TXWI for the beacon to the skb. 1138 */ 1139 rt2800_write_tx_data(entry, txdesc); 1140 1141 /* 1142 * Dump beacon to userspace through debugfs. 1143 */ 1144 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); 1145 1146 /* 1147 * Write entire beacon with TXWI and padding to register. 1148 */ 1149 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 1150 if (padding_len && skb_pad(entry->skb, padding_len)) { 1151 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); 1152 /* skb freed by skb_pad() on failure */ 1153 entry->skb = NULL; 1154 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1155 return; 1156 } 1157 1158 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx); 1159 1160 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, 1161 entry->skb->len + padding_len); 1162 __set_bit(ENTRY_BCN_ENABLED, &entry->flags); 1163 1164 /* 1165 * Change global beacons settings. 1166 */ 1167 rt2800_update_beacons_setup(rt2x00dev); 1168 1169 /* 1170 * Restore beaconing state. 1171 */ 1172 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1173 1174 /* 1175 * Clean up beacon skb. 1176 */ 1177 dev_kfree_skb_any(entry->skb); 1178 entry->skb = NULL; 1179 } 1180 EXPORT_SYMBOL_GPL(rt2800_write_beacon); 1181 1182 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, 1183 unsigned int index) 1184 { 1185 int i; 1186 const int txwi_desc_size = rt2x00dev->bcn->winfo_size; 1187 unsigned int beacon_base; 1188 1189 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index); 1190 1191 /* 1192 * For the Beacon base registers we only need to clear 1193 * the whole TXWI which (when set to 0) will invalidate 1194 * the entire beacon. 1195 */ 1196 for (i = 0; i < txwi_desc_size; i += sizeof(__le32)) 1197 rt2800_register_write(rt2x00dev, beacon_base + i, 0); 1198 } 1199 1200 void rt2800_clear_beacon(struct queue_entry *entry) 1201 { 1202 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1203 u32 orig_reg, reg; 1204 1205 /* 1206 * Disable beaconing while we are reloading the beacon data, 1207 * otherwise we might be sending out invalid data. 1208 */ 1209 orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1210 reg = orig_reg; 1211 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1212 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1213 1214 /* 1215 * Clear beacon. 1216 */ 1217 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx); 1218 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags); 1219 1220 /* 1221 * Change global beacons settings. 1222 */ 1223 rt2800_update_beacons_setup(rt2x00dev); 1224 /* 1225 * Restore beaconing state. 1226 */ 1227 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1228 } 1229 EXPORT_SYMBOL_GPL(rt2800_clear_beacon); 1230 1231 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 1232 const struct rt2x00debug rt2800_rt2x00debug = { 1233 .owner = THIS_MODULE, 1234 .csr = { 1235 .read = rt2800_register_read, 1236 .write = rt2800_register_write, 1237 .flags = RT2X00DEBUGFS_OFFSET, 1238 .word_base = CSR_REG_BASE, 1239 .word_size = sizeof(u32), 1240 .word_count = CSR_REG_SIZE / sizeof(u32), 1241 }, 1242 .eeprom = { 1243 /* NOTE: The local EEPROM access functions can't 1244 * be used here, use the generic versions instead. 1245 */ 1246 .read = rt2x00_eeprom_read, 1247 .write = rt2x00_eeprom_write, 1248 .word_base = EEPROM_BASE, 1249 .word_size = sizeof(u16), 1250 .word_count = EEPROM_SIZE / sizeof(u16), 1251 }, 1252 .bbp = { 1253 .read = rt2800_bbp_read, 1254 .write = rt2800_bbp_write, 1255 .word_base = BBP_BASE, 1256 .word_size = sizeof(u8), 1257 .word_count = BBP_SIZE / sizeof(u8), 1258 }, 1259 .rf = { 1260 .read = rt2x00_rf_read, 1261 .write = rt2800_rf_write, 1262 .word_base = RF_BASE, 1263 .word_size = sizeof(u32), 1264 .word_count = RF_SIZE / sizeof(u32), 1265 }, 1266 .rfcsr = { 1267 .read = rt2800_rfcsr_read, 1268 .write = rt2800_rfcsr_write, 1269 .word_base = RFCSR_BASE, 1270 .word_size = sizeof(u8), 1271 .word_count = RFCSR_SIZE / sizeof(u8), 1272 }, 1273 }; 1274 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); 1275 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1276 1277 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) 1278 { 1279 u32 reg; 1280 1281 if (rt2x00_rt(rt2x00dev, RT3290)) { 1282 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 1283 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); 1284 } else { 1285 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 1286 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); 1287 } 1288 } 1289 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 1290 1291 #ifdef CONFIG_RT2X00_LIB_LEDS 1292 static void rt2800_brightness_set(struct led_classdev *led_cdev, 1293 enum led_brightness brightness) 1294 { 1295 struct rt2x00_led *led = 1296 container_of(led_cdev, struct rt2x00_led, led_dev); 1297 unsigned int enabled = brightness != LED_OFF; 1298 unsigned int bg_mode = 1299 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); 1300 unsigned int polarity = 1301 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1302 EEPROM_FREQ_LED_POLARITY); 1303 unsigned int ledmode = 1304 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1305 EEPROM_FREQ_LED_MODE); 1306 u32 reg; 1307 1308 /* Check for SoC (SOC devices don't support MCU requests) */ 1309 if (rt2x00_is_soc(led->rt2x00dev)) { 1310 reg = rt2800_register_read(led->rt2x00dev, LED_CFG); 1311 1312 /* Set LED Polarity */ 1313 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); 1314 1315 /* Set LED Mode */ 1316 if (led->type == LED_TYPE_RADIO) { 1317 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 1318 enabled ? 3 : 0); 1319 } else if (led->type == LED_TYPE_ASSOC) { 1320 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 1321 enabled ? 3 : 0); 1322 } else if (led->type == LED_TYPE_QUALITY) { 1323 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 1324 enabled ? 3 : 0); 1325 } 1326 1327 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 1328 1329 } else { 1330 if (led->type == LED_TYPE_RADIO) { 1331 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1332 enabled ? 0x20 : 0); 1333 } else if (led->type == LED_TYPE_ASSOC) { 1334 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1335 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); 1336 } else if (led->type == LED_TYPE_QUALITY) { 1337 /* 1338 * The brightness is divided into 6 levels (0 - 5), 1339 * The specs tell us the following levels: 1340 * 0, 1 ,3, 7, 15, 31 1341 * to determine the level in a simple way we can simply 1342 * work with bitshifting: 1343 * (1 << level) - 1 1344 */ 1345 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 1346 (1 << brightness / (LED_FULL / 6)) - 1, 1347 polarity); 1348 } 1349 } 1350 } 1351 1352 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, 1353 struct rt2x00_led *led, enum led_type type) 1354 { 1355 led->rt2x00dev = rt2x00dev; 1356 led->type = type; 1357 led->led_dev.brightness_set = rt2800_brightness_set; 1358 led->flags = LED_INITIALIZED; 1359 } 1360 #endif /* CONFIG_RT2X00_LIB_LEDS */ 1361 1362 /* 1363 * Configuration handlers. 1364 */ 1365 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, 1366 const u8 *address, 1367 int wcid) 1368 { 1369 struct mac_wcid_entry wcid_entry; 1370 u32 offset; 1371 1372 offset = MAC_WCID_ENTRY(wcid); 1373 1374 memset(&wcid_entry, 0xff, sizeof(wcid_entry)); 1375 if (address) 1376 memcpy(wcid_entry.mac, address, ETH_ALEN); 1377 1378 rt2800_register_multiwrite(rt2x00dev, offset, 1379 &wcid_entry, sizeof(wcid_entry)); 1380 } 1381 1382 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) 1383 { 1384 u32 offset; 1385 offset = MAC_WCID_ATTR_ENTRY(wcid); 1386 rt2800_register_write(rt2x00dev, offset, 0); 1387 } 1388 1389 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, 1390 int wcid, u32 bssidx) 1391 { 1392 u32 offset = MAC_WCID_ATTR_ENTRY(wcid); 1393 u32 reg; 1394 1395 /* 1396 * The BSS Idx numbers is split in a main value of 3 bits, 1397 * and a extended field for adding one additional bit to the value. 1398 */ 1399 reg = rt2800_register_read(rt2x00dev, offset); 1400 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); 1401 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, 1402 (bssidx & 0x8) >> 3); 1403 rt2800_register_write(rt2x00dev, offset, reg); 1404 } 1405 1406 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, 1407 struct rt2x00lib_crypto *crypto, 1408 struct ieee80211_key_conf *key) 1409 { 1410 struct mac_iveiv_entry iveiv_entry; 1411 u32 offset; 1412 u32 reg; 1413 1414 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); 1415 1416 if (crypto->cmd == SET_KEY) { 1417 reg = rt2800_register_read(rt2x00dev, offset); 1418 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 1419 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 1420 /* 1421 * Both the cipher as the BSS Idx numbers are split in a main 1422 * value of 3 bits, and a extended field for adding one additional 1423 * bit to the value. 1424 */ 1425 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 1426 (crypto->cipher & 0x7)); 1427 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 1428 (crypto->cipher & 0x8) >> 3); 1429 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); 1430 rt2800_register_write(rt2x00dev, offset, reg); 1431 } else { 1432 /* Delete the cipher without touching the bssidx */ 1433 reg = rt2800_register_read(rt2x00dev, offset); 1434 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); 1435 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); 1436 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); 1437 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); 1438 rt2800_register_write(rt2x00dev, offset, reg); 1439 } 1440 1441 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 1442 1443 memset(&iveiv_entry, 0, sizeof(iveiv_entry)); 1444 if ((crypto->cipher == CIPHER_TKIP) || 1445 (crypto->cipher == CIPHER_TKIP_NO_MIC) || 1446 (crypto->cipher == CIPHER_AES)) 1447 iveiv_entry.iv[3] |= 0x20; 1448 iveiv_entry.iv[3] |= key->keyidx << 6; 1449 rt2800_register_multiwrite(rt2x00dev, offset, 1450 &iveiv_entry, sizeof(iveiv_entry)); 1451 } 1452 1453 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, 1454 struct rt2x00lib_crypto *crypto, 1455 struct ieee80211_key_conf *key) 1456 { 1457 struct hw_key_entry key_entry; 1458 struct rt2x00_field32 field; 1459 u32 offset; 1460 u32 reg; 1461 1462 if (crypto->cmd == SET_KEY) { 1463 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; 1464 1465 memcpy(key_entry.key, crypto->key, 1466 sizeof(key_entry.key)); 1467 memcpy(key_entry.tx_mic, crypto->tx_mic, 1468 sizeof(key_entry.tx_mic)); 1469 memcpy(key_entry.rx_mic, crypto->rx_mic, 1470 sizeof(key_entry.rx_mic)); 1471 1472 offset = SHARED_KEY_ENTRY(key->hw_key_idx); 1473 rt2800_register_multiwrite(rt2x00dev, offset, 1474 &key_entry, sizeof(key_entry)); 1475 } 1476 1477 /* 1478 * The cipher types are stored over multiple registers 1479 * starting with SHARED_KEY_MODE_BASE each word will have 1480 * 32 bits and contains the cipher types for 2 bssidx each. 1481 * Using the correct defines correctly will cause overhead, 1482 * so just calculate the correct offset. 1483 */ 1484 field.bit_offset = 4 * (key->hw_key_idx % 8); 1485 field.bit_mask = 0x7 << field.bit_offset; 1486 1487 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); 1488 1489 reg = rt2800_register_read(rt2x00dev, offset); 1490 rt2x00_set_field32(®, field, 1491 (crypto->cmd == SET_KEY) * crypto->cipher); 1492 rt2800_register_write(rt2x00dev, offset, reg); 1493 1494 /* 1495 * Update WCID information 1496 */ 1497 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); 1498 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, 1499 crypto->bssidx); 1500 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1501 1502 return 0; 1503 } 1504 EXPORT_SYMBOL_GPL(rt2800_config_shared_key); 1505 1506 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 1507 struct rt2x00lib_crypto *crypto, 1508 struct ieee80211_key_conf *key) 1509 { 1510 struct hw_key_entry key_entry; 1511 u32 offset; 1512 1513 if (crypto->cmd == SET_KEY) { 1514 /* 1515 * Allow key configuration only for STAs that are 1516 * known by the hw. 1517 */ 1518 if (crypto->wcid > WCID_END) 1519 return -ENOSPC; 1520 key->hw_key_idx = crypto->wcid; 1521 1522 memcpy(key_entry.key, crypto->key, 1523 sizeof(key_entry.key)); 1524 memcpy(key_entry.tx_mic, crypto->tx_mic, 1525 sizeof(key_entry.tx_mic)); 1526 memcpy(key_entry.rx_mic, crypto->rx_mic, 1527 sizeof(key_entry.rx_mic)); 1528 1529 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 1530 rt2800_register_multiwrite(rt2x00dev, offset, 1531 &key_entry, sizeof(key_entry)); 1532 } 1533 1534 /* 1535 * Update WCID information 1536 */ 1537 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1538 1539 return 0; 1540 } 1541 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); 1542 1543 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev) 1544 { 1545 u8 i, max_psdu; 1546 u32 reg; 1547 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1548 1549 for (i = 0; i < 3; i++) 1550 if (drv_data->ampdu_factor_cnt[i] > 0) 1551 break; 1552 1553 max_psdu = min(drv_data->max_psdu, i); 1554 1555 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 1556 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); 1557 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1558 } 1559 1560 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1561 struct ieee80211_sta *sta) 1562 { 1563 struct rt2x00_dev *rt2x00dev = hw->priv; 1564 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1565 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1566 int wcid; 1567 1568 /* 1569 * Limit global maximum TX AMPDU length to smallest value of all 1570 * connected stations. In AP mode this can be suboptimal, but we 1571 * do not have a choice if some connected STA is not capable to 1572 * receive the same amount of data like the others. 1573 */ 1574 if (sta->ht_cap.ht_supported) { 1575 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++; 1576 rt2800_set_max_psdu_len(rt2x00dev); 1577 } 1578 1579 /* 1580 * Search for the first free WCID entry and return the corresponding 1581 * index. 1582 */ 1583 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START; 1584 1585 /* 1586 * Store selected wcid even if it is invalid so that we can 1587 * later decide if the STA is uploaded into the hw. 1588 */ 1589 sta_priv->wcid = wcid; 1590 1591 /* 1592 * No space left in the device, however, we can still communicate 1593 * with the STA -> No error. 1594 */ 1595 if (wcid > WCID_END) 1596 return 0; 1597 1598 __set_bit(wcid - WCID_START, drv_data->sta_ids); 1599 drv_data->wcid_to_sta[wcid - WCID_START] = sta; 1600 1601 /* 1602 * Clean up WCID attributes and write STA address to the device. 1603 */ 1604 rt2800_delete_wcid_attr(rt2x00dev, wcid); 1605 rt2800_config_wcid(rt2x00dev, sta->addr, wcid); 1606 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, 1607 rt2x00lib_get_bssidx(rt2x00dev, vif)); 1608 return 0; 1609 } 1610 EXPORT_SYMBOL_GPL(rt2800_sta_add); 1611 1612 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1613 struct ieee80211_sta *sta) 1614 { 1615 struct rt2x00_dev *rt2x00dev = hw->priv; 1616 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1617 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1618 int wcid = sta_priv->wcid; 1619 1620 if (sta->ht_cap.ht_supported) { 1621 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--; 1622 rt2800_set_max_psdu_len(rt2x00dev); 1623 } 1624 1625 if (wcid > WCID_END) 1626 return 0; 1627 /* 1628 * Remove WCID entry, no need to clean the attributes as they will 1629 * get renewed when the WCID is reused. 1630 */ 1631 rt2800_config_wcid(rt2x00dev, NULL, wcid); 1632 drv_data->wcid_to_sta[wcid - WCID_START] = NULL; 1633 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1634 1635 return 0; 1636 } 1637 EXPORT_SYMBOL_GPL(rt2800_sta_remove); 1638 1639 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, 1640 const unsigned int filter_flags) 1641 { 1642 u32 reg; 1643 1644 /* 1645 * Start configuration steps. 1646 * Note that the version error will always be dropped 1647 * and broadcast frames will always be accepted since 1648 * there is no filter for it at this time. 1649 */ 1650 reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG); 1651 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, 1652 !(filter_flags & FIF_FCSFAIL)); 1653 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, 1654 !(filter_flags & FIF_PLCPFAIL)); 1655 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, 1656 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); 1657 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); 1658 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); 1659 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, 1660 !(filter_flags & FIF_ALLMULTI)); 1661 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); 1662 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); 1663 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, 1664 !(filter_flags & FIF_CONTROL)); 1665 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, 1666 !(filter_flags & FIF_CONTROL)); 1667 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, 1668 !(filter_flags & FIF_CONTROL)); 1669 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, 1670 !(filter_flags & FIF_CONTROL)); 1671 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, 1672 !(filter_flags & FIF_CONTROL)); 1673 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, 1674 !(filter_flags & FIF_PSPOLL)); 1675 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); 1676 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 1677 !(filter_flags & FIF_CONTROL)); 1678 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, 1679 !(filter_flags & FIF_CONTROL)); 1680 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); 1681 } 1682 EXPORT_SYMBOL_GPL(rt2800_config_filter); 1683 1684 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, 1685 struct rt2x00intf_conf *conf, const unsigned int flags) 1686 { 1687 u32 reg; 1688 bool update_bssid = false; 1689 1690 if (flags & CONFIG_UPDATE_TYPE) { 1691 /* 1692 * Enable synchronisation. 1693 */ 1694 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1695 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); 1696 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1697 1698 if (conf->sync == TSF_SYNC_AP_NONE) { 1699 /* 1700 * Tune beacon queue transmit parameters for AP mode 1701 */ 1702 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1703 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); 1704 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); 1705 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1706 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); 1707 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1708 } else { 1709 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1710 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); 1711 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); 1712 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1713 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); 1714 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1715 } 1716 } 1717 1718 if (flags & CONFIG_UPDATE_MAC) { 1719 if (flags & CONFIG_UPDATE_TYPE && 1720 conf->sync == TSF_SYNC_AP_NONE) { 1721 /* 1722 * The BSSID register has to be set to our own mac 1723 * address in AP mode. 1724 */ 1725 memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); 1726 update_bssid = true; 1727 } 1728 1729 if (!is_zero_ether_addr((const u8 *)conf->mac)) { 1730 reg = le32_to_cpu(conf->mac[1]); 1731 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); 1732 conf->mac[1] = cpu_to_le32(reg); 1733 } 1734 1735 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, 1736 conf->mac, sizeof(conf->mac)); 1737 } 1738 1739 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { 1740 if (!is_zero_ether_addr((const u8 *)conf->bssid)) { 1741 reg = le32_to_cpu(conf->bssid[1]); 1742 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); 1743 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); 1744 conf->bssid[1] = cpu_to_le32(reg); 1745 } 1746 1747 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, 1748 conf->bssid, sizeof(conf->bssid)); 1749 } 1750 } 1751 EXPORT_SYMBOL_GPL(rt2800_config_intf); 1752 1753 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, 1754 struct rt2x00lib_erp *erp) 1755 { 1756 bool any_sta_nongf = !!(erp->ht_opmode & 1757 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 1758 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; 1759 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; 1760 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; 1761 u32 reg; 1762 1763 /* default protection rate for HT20: OFDM 24M */ 1764 mm20_rate = gf20_rate = 0x4004; 1765 1766 /* default protection rate for HT40: duplicate OFDM 24M */ 1767 mm40_rate = gf40_rate = 0x4084; 1768 1769 switch (protection) { 1770 case IEEE80211_HT_OP_MODE_PROTECTION_NONE: 1771 /* 1772 * All STAs in this BSS are HT20/40 but there might be 1773 * STAs not supporting greenfield mode. 1774 * => Disable protection for HT transmissions. 1775 */ 1776 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; 1777 1778 break; 1779 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 1780 /* 1781 * All STAs in this BSS are HT20 or HT20/40 but there 1782 * might be STAs not supporting greenfield mode. 1783 * => Protect all HT40 transmissions. 1784 */ 1785 mm20_mode = gf20_mode = 0; 1786 mm40_mode = gf40_mode = 1; 1787 1788 break; 1789 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 1790 /* 1791 * Nonmember protection: 1792 * According to 802.11n we _should_ protect all 1793 * HT transmissions (but we don't have to). 1794 * 1795 * But if cts_protection is enabled we _shall_ protect 1796 * all HT transmissions using a CCK rate. 1797 * 1798 * And if any station is non GF we _shall_ protect 1799 * GF transmissions. 1800 * 1801 * We decide to protect everything 1802 * -> fall through to mixed mode. 1803 */ 1804 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 1805 /* 1806 * Legacy STAs are present 1807 * => Protect all HT transmissions. 1808 */ 1809 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1; 1810 1811 /* 1812 * If erp protection is needed we have to protect HT 1813 * transmissions with CCK 11M long preamble. 1814 */ 1815 if (erp->cts_protection) { 1816 /* don't duplicate RTS/CTS in CCK mode */ 1817 mm20_rate = mm40_rate = 0x0003; 1818 gf20_rate = gf40_rate = 0x0003; 1819 } 1820 break; 1821 } 1822 1823 /* check for STAs not supporting greenfield mode */ 1824 if (any_sta_nongf) 1825 gf20_mode = gf40_mode = 1; 1826 1827 /* Update HT protection config */ 1828 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 1829 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); 1830 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); 1831 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 1832 1833 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 1834 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); 1835 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); 1836 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 1837 1838 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 1839 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); 1840 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); 1841 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 1842 1843 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 1844 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); 1845 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); 1846 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 1847 } 1848 1849 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, 1850 u32 changed) 1851 { 1852 u32 reg; 1853 1854 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 1855 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 1856 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 1857 !!erp->short_preamble); 1858 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 1859 } 1860 1861 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 1862 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 1863 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 1864 erp->cts_protection ? 2 : 0); 1865 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 1866 } 1867 1868 if (changed & BSS_CHANGED_BASIC_RATES) { 1869 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 1870 0xff0 | erp->basic_rates); 1871 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 1872 } 1873 1874 if (changed & BSS_CHANGED_ERP_SLOT) { 1875 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 1876 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 1877 erp->slot_time); 1878 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 1879 1880 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 1881 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); 1882 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 1883 } 1884 1885 if (changed & BSS_CHANGED_BEACON_INT) { 1886 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1887 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1888 erp->beacon_int * 16); 1889 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1890 } 1891 1892 if (changed & BSS_CHANGED_HT) 1893 rt2800_config_ht_opmode(rt2x00dev, erp); 1894 } 1895 EXPORT_SYMBOL_GPL(rt2800_config_erp); 1896 1897 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) 1898 { 1899 u32 reg; 1900 u16 eeprom; 1901 u8 led_ctrl, led_g_mode, led_r_mode; 1902 1903 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 1904 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { 1905 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); 1906 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); 1907 } else { 1908 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); 1909 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); 1910 } 1911 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 1912 1913 reg = rt2800_register_read(rt2x00dev, LED_CFG); 1914 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; 1915 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; 1916 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || 1917 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { 1918 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 1919 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); 1920 if (led_ctrl == 0 || led_ctrl > 0x40) { 1921 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); 1922 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); 1923 rt2800_register_write(rt2x00dev, LED_CFG, reg); 1924 } else { 1925 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, 1926 (led_g_mode << 2) | led_r_mode, 1); 1927 } 1928 } 1929 } 1930 1931 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, 1932 enum antenna ant) 1933 { 1934 u32 reg; 1935 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; 1936 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; 1937 1938 if (rt2x00_is_pci(rt2x00dev)) { 1939 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR); 1940 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); 1941 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); 1942 } else if (rt2x00_is_usb(rt2x00dev)) 1943 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, 1944 eesk_pin, 0); 1945 1946 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 1947 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 1948 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); 1949 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 1950 } 1951 1952 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 1953 { 1954 u8 r1; 1955 u8 r3; 1956 u16 eeprom; 1957 1958 r1 = rt2800_bbp_read(rt2x00dev, 1); 1959 r3 = rt2800_bbp_read(rt2x00dev, 3); 1960 1961 if (rt2x00_rt(rt2x00dev, RT3572) && 1962 rt2x00_has_cap_bt_coexist(rt2x00dev)) 1963 rt2800_config_3572bt_ant(rt2x00dev); 1964 1965 /* 1966 * Configure the TX antenna. 1967 */ 1968 switch (ant->tx_chain_num) { 1969 case 1: 1970 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 1971 break; 1972 case 2: 1973 if (rt2x00_rt(rt2x00dev, RT3572) && 1974 rt2x00_has_cap_bt_coexist(rt2x00dev)) 1975 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); 1976 else 1977 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 1978 break; 1979 case 3: 1980 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 1981 break; 1982 } 1983 1984 /* 1985 * Configure the RX antenna. 1986 */ 1987 switch (ant->rx_chain_num) { 1988 case 1: 1989 if (rt2x00_rt(rt2x00dev, RT3070) || 1990 rt2x00_rt(rt2x00dev, RT3090) || 1991 rt2x00_rt(rt2x00dev, RT3352) || 1992 rt2x00_rt(rt2x00dev, RT3390)) { 1993 eeprom = rt2800_eeprom_read(rt2x00dev, 1994 EEPROM_NIC_CONF1); 1995 if (rt2x00_get_field16(eeprom, 1996 EEPROM_NIC_CONF1_ANT_DIVERSITY)) 1997 rt2800_set_ant_diversity(rt2x00dev, 1998 rt2x00dev->default_ant.rx); 1999 } 2000 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 2001 break; 2002 case 2: 2003 if (rt2x00_rt(rt2x00dev, RT3572) && 2004 rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2005 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); 2006 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2007 rt2x00dev->curr_band == NL80211_BAND_5GHZ); 2008 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); 2009 } else { 2010 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); 2011 } 2012 break; 2013 case 3: 2014 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); 2015 break; 2016 } 2017 2018 rt2800_bbp_write(rt2x00dev, 3, r3); 2019 rt2800_bbp_write(rt2x00dev, 1, r1); 2020 2021 if (rt2x00_rt(rt2x00dev, RT3593)) { 2022 if (ant->rx_chain_num == 1) 2023 rt2800_bbp_write(rt2x00dev, 86, 0x00); 2024 else 2025 rt2800_bbp_write(rt2x00dev, 86, 0x46); 2026 } 2027 } 2028 EXPORT_SYMBOL_GPL(rt2800_config_ant); 2029 2030 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, 2031 struct rt2x00lib_conf *libconf) 2032 { 2033 u16 eeprom; 2034 short lna_gain; 2035 2036 if (libconf->rf.channel <= 14) { 2037 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2038 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); 2039 } else if (libconf->rf.channel <= 64) { 2040 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2041 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); 2042 } else if (libconf->rf.channel <= 128) { 2043 if (rt2x00_rt(rt2x00dev, RT3593)) { 2044 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2045 lna_gain = rt2x00_get_field16(eeprom, 2046 EEPROM_EXT_LNA2_A1); 2047 } else { 2048 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 2049 lna_gain = rt2x00_get_field16(eeprom, 2050 EEPROM_RSSI_BG2_LNA_A1); 2051 } 2052 } else { 2053 if (rt2x00_rt(rt2x00dev, RT3593)) { 2054 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2055 lna_gain = rt2x00_get_field16(eeprom, 2056 EEPROM_EXT_LNA2_A2); 2057 } else { 2058 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 2059 lna_gain = rt2x00_get_field16(eeprom, 2060 EEPROM_RSSI_A2_LNA_A2); 2061 } 2062 } 2063 2064 rt2x00dev->lna_gain = lna_gain; 2065 } 2066 2067 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev) 2068 { 2069 return clk_get_rate(rt2x00dev->clk) == 20000000; 2070 } 2071 2072 #define FREQ_OFFSET_BOUND 0x5f 2073 2074 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev) 2075 { 2076 u8 freq_offset, prev_freq_offset; 2077 u8 rfcsr, prev_rfcsr; 2078 2079 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE); 2080 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND); 2081 2082 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 2083 prev_rfcsr = rfcsr; 2084 2085 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset); 2086 if (rfcsr == prev_rfcsr) 2087 return; 2088 2089 if (rt2x00_is_usb(rt2x00dev)) { 2090 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff, 2091 freq_offset, prev_rfcsr); 2092 return; 2093 } 2094 2095 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE); 2096 while (prev_freq_offset != freq_offset) { 2097 if (prev_freq_offset < freq_offset) 2098 prev_freq_offset++; 2099 else 2100 prev_freq_offset--; 2101 2102 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset); 2103 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 2104 2105 usleep_range(1000, 1500); 2106 } 2107 } 2108 2109 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, 2110 struct ieee80211_conf *conf, 2111 struct rf_channel *rf, 2112 struct channel_info *info) 2113 { 2114 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 2115 2116 if (rt2x00dev->default_ant.tx_chain_num == 1) 2117 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); 2118 2119 if (rt2x00dev->default_ant.rx_chain_num == 1) { 2120 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); 2121 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2122 } else if (rt2x00dev->default_ant.rx_chain_num == 2) 2123 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2124 2125 if (rf->channel > 14) { 2126 /* 2127 * When TX power is below 0, we should increase it by 7 to 2128 * make it a positive value (Minimum value is -7). 2129 * However this means that values between 0 and 7 have 2130 * double meaning, and we should set a 7DBm boost flag. 2131 */ 2132 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, 2133 (info->default_power1 >= 0)); 2134 2135 if (info->default_power1 < 0) 2136 info->default_power1 += 7; 2137 2138 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); 2139 2140 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, 2141 (info->default_power2 >= 0)); 2142 2143 if (info->default_power2 < 0) 2144 info->default_power2 += 7; 2145 2146 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); 2147 } else { 2148 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); 2149 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); 2150 } 2151 2152 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); 2153 2154 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2155 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2156 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2157 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2158 2159 udelay(200); 2160 2161 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2162 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2163 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 2164 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2165 2166 udelay(200); 2167 2168 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2169 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2170 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2171 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2172 } 2173 2174 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, 2175 struct ieee80211_conf *conf, 2176 struct rf_channel *rf, 2177 struct channel_info *info) 2178 { 2179 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2180 u8 rfcsr, calib_tx, calib_rx; 2181 2182 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2183 2184 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2185 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3); 2186 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2187 2188 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2189 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2190 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2191 2192 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2193 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); 2194 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2195 2196 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2197 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); 2198 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2199 2200 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2201 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2202 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 2203 rt2x00dev->default_ant.rx_chain_num <= 1); 2204 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 2205 rt2x00dev->default_ant.rx_chain_num <= 2); 2206 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2207 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 2208 rt2x00dev->default_ant.tx_chain_num <= 1); 2209 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 2210 rt2x00dev->default_ant.tx_chain_num <= 2); 2211 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2212 2213 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2214 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2215 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2216 2217 if (rt2x00_rt(rt2x00dev, RT3390)) { 2218 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f; 2219 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f; 2220 } else { 2221 if (conf_is_ht40(conf)) { 2222 calib_tx = drv_data->calibration_bw40; 2223 calib_rx = drv_data->calibration_bw40; 2224 } else { 2225 calib_tx = drv_data->calibration_bw20; 2226 calib_rx = drv_data->calibration_bw20; 2227 } 2228 } 2229 2230 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24); 2231 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx); 2232 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr); 2233 2234 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 2235 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx); 2236 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2237 2238 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2239 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2240 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2241 2242 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2243 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 2244 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2245 2246 usleep_range(1000, 1500); 2247 2248 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 2249 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2250 } 2251 2252 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, 2253 struct ieee80211_conf *conf, 2254 struct rf_channel *rf, 2255 struct channel_info *info) 2256 { 2257 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2258 u8 rfcsr; 2259 u32 reg; 2260 2261 if (rf->channel <= 14) { 2262 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2263 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2264 } else { 2265 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2266 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2267 } 2268 2269 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2270 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 2271 2272 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2273 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2274 if (rf->channel <= 14) 2275 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); 2276 else 2277 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); 2278 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2279 2280 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5); 2281 if (rf->channel <= 14) 2282 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); 2283 else 2284 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); 2285 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); 2286 2287 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2288 if (rf->channel <= 14) { 2289 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); 2290 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2291 info->default_power1); 2292 } else { 2293 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); 2294 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2295 (info->default_power1 & 0x3) | 2296 ((info->default_power1 & 0xC) << 1)); 2297 } 2298 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2299 2300 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2301 if (rf->channel <= 14) { 2302 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); 2303 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2304 info->default_power2); 2305 } else { 2306 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); 2307 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2308 (info->default_power2 & 0x3) | 2309 ((info->default_power2 & 0xC) << 1)); 2310 } 2311 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2312 2313 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2314 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2315 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2316 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2317 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2318 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2319 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2320 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2321 if (rf->channel <= 14) { 2322 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2323 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2324 } 2325 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2326 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2327 } else { 2328 switch (rt2x00dev->default_ant.tx_chain_num) { 2329 case 1: 2330 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2331 case 2: 2332 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2333 break; 2334 } 2335 2336 switch (rt2x00dev->default_ant.rx_chain_num) { 2337 case 1: 2338 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2339 case 2: 2340 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2341 break; 2342 } 2343 } 2344 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2345 2346 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2347 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2348 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2349 2350 if (conf_is_ht40(conf)) { 2351 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40); 2352 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40); 2353 } else { 2354 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20); 2355 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20); 2356 } 2357 2358 if (rf->channel <= 14) { 2359 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 2360 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 2361 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2362 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 2363 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 2364 rfcsr = 0x4c; 2365 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2366 drv_data->txmixer_gain_24g); 2367 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2368 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2369 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 2370 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 2371 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 2372 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 2373 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 2374 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 2375 } else { 2376 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2377 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1); 2378 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0); 2379 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1); 2380 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0); 2381 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2382 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 2383 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2384 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 2385 rt2800_rfcsr_write(rt2x00dev, 15, 0x43); 2386 rfcsr = 0x7a; 2387 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2388 drv_data->txmixer_gain_5g); 2389 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2390 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2391 if (rf->channel <= 64) { 2392 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7); 2393 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6); 2394 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 2395 } else if (rf->channel <= 128) { 2396 rt2800_rfcsr_write(rt2x00dev, 19, 0x74); 2397 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4); 2398 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2399 } else { 2400 rt2800_rfcsr_write(rt2x00dev, 19, 0x72); 2401 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3); 2402 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2403 } 2404 rt2800_rfcsr_write(rt2x00dev, 26, 0x87); 2405 rt2800_rfcsr_write(rt2x00dev, 27, 0x01); 2406 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); 2407 } 2408 2409 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2410 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 2411 if (rf->channel <= 14) 2412 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 2413 else 2414 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); 2415 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2416 2417 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2418 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2419 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2420 } 2421 2422 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, 2423 struct ieee80211_conf *conf, 2424 struct rf_channel *rf, 2425 struct channel_info *info) 2426 { 2427 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2428 u8 txrx_agc_fc; 2429 u8 txrx_h20m; 2430 u8 rfcsr; 2431 u8 bbp; 2432 const bool txbf_enabled = false; /* TODO */ 2433 2434 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */ 2435 bbp = rt2800_bbp_read(rt2x00dev, 109); 2436 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0); 2437 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0); 2438 rt2800_bbp_write(rt2x00dev, 109, bbp); 2439 2440 bbp = rt2800_bbp_read(rt2x00dev, 110); 2441 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0); 2442 rt2800_bbp_write(rt2x00dev, 110, bbp); 2443 2444 if (rf->channel <= 14) { 2445 /* Restore BBP 25 & 26 for 2.4 GHz */ 2446 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2447 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2448 } else { 2449 /* Hard code BBP 25 & 26 for 5GHz */ 2450 2451 /* Enable IQ Phase correction */ 2452 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2453 /* Setup IQ Phase correction value */ 2454 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2455 } 2456 2457 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2458 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf); 2459 2460 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2461 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3)); 2462 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2463 2464 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2465 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1); 2466 if (rf->channel <= 14) 2467 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1); 2468 else 2469 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2); 2470 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2471 2472 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53); 2473 if (rf->channel <= 14) { 2474 rfcsr = 0; 2475 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2476 info->default_power1 & 0x1f); 2477 } else { 2478 if (rt2x00_is_usb(rt2x00dev)) 2479 rfcsr = 0x40; 2480 2481 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2482 ((info->default_power1 & 0x18) << 1) | 2483 (info->default_power1 & 7)); 2484 } 2485 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr); 2486 2487 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55); 2488 if (rf->channel <= 14) { 2489 rfcsr = 0; 2490 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2491 info->default_power2 & 0x1f); 2492 } else { 2493 if (rt2x00_is_usb(rt2x00dev)) 2494 rfcsr = 0x40; 2495 2496 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2497 ((info->default_power2 & 0x18) << 1) | 2498 (info->default_power2 & 7)); 2499 } 2500 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr); 2501 2502 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54); 2503 if (rf->channel <= 14) { 2504 rfcsr = 0; 2505 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2506 info->default_power3 & 0x1f); 2507 } else { 2508 if (rt2x00_is_usb(rt2x00dev)) 2509 rfcsr = 0x40; 2510 2511 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2512 ((info->default_power3 & 0x18) << 1) | 2513 (info->default_power3 & 7)); 2514 } 2515 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr); 2516 2517 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2518 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2519 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2520 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2521 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2522 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2523 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2524 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2525 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2526 2527 switch (rt2x00dev->default_ant.tx_chain_num) { 2528 case 3: 2529 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2530 /* fallthrough */ 2531 case 2: 2532 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2533 /* fallthrough */ 2534 case 1: 2535 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2536 break; 2537 } 2538 2539 switch (rt2x00dev->default_ant.rx_chain_num) { 2540 case 3: 2541 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2542 /* fallthrough */ 2543 case 2: 2544 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2545 /* fallthrough */ 2546 case 1: 2547 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2548 break; 2549 } 2550 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2551 2552 rt2800_freq_cal_mode1(rt2x00dev); 2553 2554 if (conf_is_ht40(conf)) { 2555 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40, 2556 RFCSR24_TX_AGC_FC); 2557 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40, 2558 RFCSR24_TX_H20M); 2559 } else { 2560 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20, 2561 RFCSR24_TX_AGC_FC); 2562 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20, 2563 RFCSR24_TX_H20M); 2564 } 2565 2566 /* NOTE: the reference driver does not writes the new value 2567 * back to RFCSR 32 2568 */ 2569 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32); 2570 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc); 2571 2572 if (rf->channel <= 14) 2573 rfcsr = 0xa0; 2574 else 2575 rfcsr = 0x80; 2576 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2577 2578 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2579 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m); 2580 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m); 2581 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2582 2583 /* Band selection */ 2584 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 2585 if (rf->channel <= 14) 2586 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 2587 else 2588 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 2589 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 2590 2591 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34); 2592 if (rf->channel <= 14) 2593 rfcsr = 0x3c; 2594 else 2595 rfcsr = 0x20; 2596 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 2597 2598 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2599 if (rf->channel <= 14) 2600 rfcsr = 0x1a; 2601 else 2602 rfcsr = 0x12; 2603 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2604 2605 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2606 if (rf->channel >= 1 && rf->channel <= 14) 2607 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2608 else if (rf->channel >= 36 && rf->channel <= 64) 2609 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2610 else if (rf->channel >= 100 && rf->channel <= 128) 2611 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2612 else 2613 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2614 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2615 2616 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2617 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 2618 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2619 2620 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 2621 2622 if (rf->channel <= 14) { 2623 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 2624 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 2625 } else { 2626 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8); 2627 rt2800_rfcsr_write(rt2x00dev, 13, 0x23); 2628 } 2629 2630 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2631 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1); 2632 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2633 2634 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2635 if (rf->channel <= 14) { 2636 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5); 2637 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3); 2638 } else { 2639 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4); 2640 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2); 2641 } 2642 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2643 2644 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2645 if (rf->channel <= 14) 2646 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3); 2647 else 2648 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2); 2649 2650 if (txbf_enabled) 2651 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1); 2652 2653 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2654 2655 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 2656 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0); 2657 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2658 2659 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 2660 if (rf->channel <= 14) 2661 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b); 2662 else 2663 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f); 2664 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr); 2665 2666 if (rf->channel <= 14) { 2667 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 2668 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 2669 } else { 2670 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 2671 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 2672 } 2673 2674 /* Initiate VCO calibration */ 2675 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2676 if (rf->channel <= 14) { 2677 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2678 } else { 2679 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1); 2680 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1); 2681 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1); 2682 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1); 2683 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1); 2684 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2685 } 2686 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2687 2688 if (rf->channel >= 1 && rf->channel <= 14) { 2689 rfcsr = 0x23; 2690 if (txbf_enabled) 2691 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2692 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2693 2694 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 2695 } else if (rf->channel >= 36 && rf->channel <= 64) { 2696 rfcsr = 0x36; 2697 if (txbf_enabled) 2698 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2699 rt2800_rfcsr_write(rt2x00dev, 39, 0x36); 2700 2701 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb); 2702 } else if (rf->channel >= 100 && rf->channel <= 128) { 2703 rfcsr = 0x32; 2704 if (txbf_enabled) 2705 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2706 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2707 2708 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3); 2709 } else { 2710 rfcsr = 0x30; 2711 if (txbf_enabled) 2712 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2713 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2714 2715 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b); 2716 } 2717 } 2718 2719 #define POWER_BOUND 0x27 2720 #define POWER_BOUND_5G 0x2b 2721 2722 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev, 2723 struct ieee80211_conf *conf, 2724 struct rf_channel *rf, 2725 struct channel_info *info) 2726 { 2727 u8 rfcsr; 2728 2729 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2730 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2731 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2732 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 2733 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2734 2735 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2736 if (info->default_power1 > POWER_BOUND) 2737 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 2738 else 2739 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2740 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2741 2742 rt2800_freq_cal_mode1(rt2x00dev); 2743 2744 if (rf->channel <= 14) { 2745 if (rf->channel == 6) 2746 rt2800_bbp_write(rt2x00dev, 68, 0x0c); 2747 else 2748 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 2749 2750 if (rf->channel >= 1 && rf->channel <= 6) 2751 rt2800_bbp_write(rt2x00dev, 59, 0x0f); 2752 else if (rf->channel >= 7 && rf->channel <= 11) 2753 rt2800_bbp_write(rt2x00dev, 59, 0x0e); 2754 else if (rf->channel >= 12 && rf->channel <= 14) 2755 rt2800_bbp_write(rt2x00dev, 59, 0x0d); 2756 } 2757 } 2758 2759 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev, 2760 struct ieee80211_conf *conf, 2761 struct rf_channel *rf, 2762 struct channel_info *info) 2763 { 2764 u8 rfcsr; 2765 2766 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2767 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2768 2769 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 2770 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 2771 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 2772 2773 if (info->default_power1 > POWER_BOUND) 2774 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND); 2775 else 2776 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1); 2777 2778 if (info->default_power2 > POWER_BOUND) 2779 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND); 2780 else 2781 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2); 2782 2783 rt2800_freq_cal_mode1(rt2x00dev); 2784 2785 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2786 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2787 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2788 2789 if ( rt2x00dev->default_ant.tx_chain_num == 2 ) 2790 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2791 else 2792 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2793 2794 if ( rt2x00dev->default_ant.rx_chain_num == 2 ) 2795 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2796 else 2797 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2798 2799 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2800 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2801 2802 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2803 2804 rt2800_rfcsr_write(rt2x00dev, 31, 80); 2805 } 2806 2807 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 2808 struct ieee80211_conf *conf, 2809 struct rf_channel *rf, 2810 struct channel_info *info) 2811 { 2812 u8 rfcsr; 2813 2814 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2815 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2816 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2817 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 2818 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2819 2820 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2821 if (info->default_power1 > POWER_BOUND) 2822 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 2823 else 2824 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2825 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2826 2827 if (rt2x00_rt(rt2x00dev, RT5392)) { 2828 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 2829 if (info->default_power2 > POWER_BOUND) 2830 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND); 2831 else 2832 rt2x00_set_field8(&rfcsr, RFCSR50_TX, 2833 info->default_power2); 2834 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2835 } 2836 2837 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2838 if (rt2x00_rt(rt2x00dev, RT5392)) { 2839 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2840 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2841 } 2842 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2843 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2844 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2845 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2846 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2847 2848 rt2800_freq_cal_mode1(rt2x00dev); 2849 2850 if (rf->channel <= 14) { 2851 int idx = rf->channel-1; 2852 2853 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2854 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 2855 /* r55/r59 value array of channel 1~14 */ 2856 static const char r55_bt_rev[] = {0x83, 0x83, 2857 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, 2858 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; 2859 static const char r59_bt_rev[] = {0x0e, 0x0e, 2860 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, 2861 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; 2862 2863 rt2800_rfcsr_write(rt2x00dev, 55, 2864 r55_bt_rev[idx]); 2865 rt2800_rfcsr_write(rt2x00dev, 59, 2866 r59_bt_rev[idx]); 2867 } else { 2868 static const char r59_bt[] = {0x8b, 0x8b, 0x8b, 2869 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, 2870 0x88, 0x88, 0x86, 0x85, 0x84}; 2871 2872 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); 2873 } 2874 } else { 2875 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 2876 static const char r55_nonbt_rev[] = {0x23, 0x23, 2877 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, 2878 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; 2879 static const char r59_nonbt_rev[] = {0x07, 0x07, 2880 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 2881 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; 2882 2883 rt2800_rfcsr_write(rt2x00dev, 55, 2884 r55_nonbt_rev[idx]); 2885 rt2800_rfcsr_write(rt2x00dev, 59, 2886 r59_nonbt_rev[idx]); 2887 } else if (rt2x00_rt(rt2x00dev, RT5390) || 2888 rt2x00_rt(rt2x00dev, RT5392) || 2889 rt2x00_rt(rt2x00dev, RT6352)) { 2890 static const char r59_non_bt[] = {0x8f, 0x8f, 2891 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, 2892 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; 2893 2894 rt2800_rfcsr_write(rt2x00dev, 59, 2895 r59_non_bt[idx]); 2896 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 2897 static const char r59_non_bt[] = {0x0b, 0x0b, 2898 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a, 2899 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06}; 2900 2901 rt2800_rfcsr_write(rt2x00dev, 59, 2902 r59_non_bt[idx]); 2903 } 2904 } 2905 } 2906 } 2907 2908 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, 2909 struct ieee80211_conf *conf, 2910 struct rf_channel *rf, 2911 struct channel_info *info) 2912 { 2913 u8 rfcsr, ep_reg; 2914 u32 reg; 2915 int power_bound; 2916 2917 /* TODO */ 2918 const bool is_11b = false; 2919 const bool is_type_ep = false; 2920 2921 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 2922 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 2923 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0); 2924 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 2925 2926 /* Order of values on rf_channel entry: N, K, mod, R */ 2927 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff); 2928 2929 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9); 2930 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf); 2931 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8); 2932 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2); 2933 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr); 2934 2935 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2936 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1); 2937 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3); 2938 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2939 2940 if (rf->channel <= 14) { 2941 rt2800_rfcsr_write(rt2x00dev, 10, 0x90); 2942 /* FIXME: RF11 owerwrite ? */ 2943 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A); 2944 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 2945 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 2946 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 2947 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A); 2948 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 2949 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 2950 rt2800_rfcsr_write(rt2x00dev, 36, 0x80); 2951 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 2952 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 2953 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B); 2954 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D); 2955 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B); 2956 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5); 2957 rt2800_rfcsr_write(rt2x00dev, 43, 0x72); 2958 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E); 2959 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2); 2960 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B); 2961 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 2962 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E); 2963 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 2964 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 2965 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1); 2966 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 2967 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 2968 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 2969 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 2970 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 2971 2972 /* TODO RF27 <- tssi */ 2973 2974 rfcsr = rf->channel <= 10 ? 0x07 : 0x06; 2975 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2976 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr); 2977 2978 if (is_11b) { 2979 /* CCK */ 2980 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8); 2981 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0); 2982 if (is_type_ep) 2983 rt2800_rfcsr_write(rt2x00dev, 55, 0x06); 2984 else 2985 rt2800_rfcsr_write(rt2x00dev, 55, 0x47); 2986 } else { 2987 /* OFDM */ 2988 if (is_type_ep) 2989 rt2800_rfcsr_write(rt2x00dev, 55, 0x03); 2990 else 2991 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 2992 } 2993 2994 power_bound = POWER_BOUND; 2995 ep_reg = 0x2; 2996 } else { 2997 rt2800_rfcsr_write(rt2x00dev, 10, 0x97); 2998 /* FIMXE: RF11 overwrite */ 2999 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 3000 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF); 3001 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3002 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 3003 rt2800_rfcsr_write(rt2x00dev, 37, 0x04); 3004 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 3005 rt2800_rfcsr_write(rt2x00dev, 40, 0x42); 3006 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB); 3007 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7); 3008 rt2800_rfcsr_write(rt2x00dev, 45, 0x41); 3009 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 3010 rt2800_rfcsr_write(rt2x00dev, 57, 0x77); 3011 rt2800_rfcsr_write(rt2x00dev, 60, 0x05); 3012 rt2800_rfcsr_write(rt2x00dev, 61, 0x01); 3013 3014 /* TODO RF27 <- tssi */ 3015 3016 if (rf->channel >= 36 && rf->channel <= 64) { 3017 3018 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E); 3019 rt2800_rfcsr_write(rt2x00dev, 13, 0x22); 3020 rt2800_rfcsr_write(rt2x00dev, 22, 0x60); 3021 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F); 3022 if (rf->channel <= 50) 3023 rt2800_rfcsr_write(rt2x00dev, 24, 0x09); 3024 else if (rf->channel >= 52) 3025 rt2800_rfcsr_write(rt2x00dev, 24, 0x07); 3026 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C); 3027 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B); 3028 rt2800_rfcsr_write(rt2x00dev, 44, 0X40); 3029 rt2800_rfcsr_write(rt2x00dev, 46, 0X00); 3030 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE); 3031 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C); 3032 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8); 3033 if (rf->channel <= 50) { 3034 rt2800_rfcsr_write(rt2x00dev, 55, 0x06), 3035 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3); 3036 } else if (rf->channel >= 52) { 3037 rt2800_rfcsr_write(rt2x00dev, 55, 0x04); 3038 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3039 } 3040 3041 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3042 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F); 3043 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3044 3045 } else if (rf->channel >= 100 && rf->channel <= 165) { 3046 3047 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E); 3048 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3049 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3050 if (rf->channel <= 153) { 3051 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C); 3052 rt2800_rfcsr_write(rt2x00dev, 24, 0x06); 3053 } else if (rf->channel >= 155) { 3054 rt2800_rfcsr_write(rt2x00dev, 23, 0x38); 3055 rt2800_rfcsr_write(rt2x00dev, 24, 0x05); 3056 } 3057 if (rf->channel <= 138) { 3058 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A); 3059 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B); 3060 rt2800_rfcsr_write(rt2x00dev, 44, 0x20); 3061 rt2800_rfcsr_write(rt2x00dev, 46, 0x18); 3062 } else if (rf->channel >= 140) { 3063 rt2800_rfcsr_write(rt2x00dev, 39, 0x18); 3064 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B); 3065 rt2800_rfcsr_write(rt2x00dev, 44, 0x10); 3066 rt2800_rfcsr_write(rt2x00dev, 46, 0X08); 3067 } 3068 if (rf->channel <= 124) 3069 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC); 3070 else if (rf->channel >= 126) 3071 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC); 3072 if (rf->channel <= 138) 3073 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3074 else if (rf->channel >= 140) 3075 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3076 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB); 3077 if (rf->channel <= 138) 3078 rt2800_rfcsr_write(rt2x00dev, 55, 0x01); 3079 else if (rf->channel >= 140) 3080 rt2800_rfcsr_write(rt2x00dev, 55, 0x00); 3081 if (rf->channel <= 128) 3082 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3083 else if (rf->channel >= 130) 3084 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB); 3085 if (rf->channel <= 116) 3086 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D); 3087 else if (rf->channel >= 118) 3088 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3089 if (rf->channel <= 138) 3090 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F); 3091 else if (rf->channel >= 140) 3092 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C); 3093 if (rf->channel <= 116) 3094 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D); 3095 else if (rf->channel >= 118) 3096 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3097 } 3098 3099 power_bound = POWER_BOUND_5G; 3100 ep_reg = 0x3; 3101 } 3102 3103 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3104 if (info->default_power1 > power_bound) 3105 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound); 3106 else 3107 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3108 if (is_type_ep) 3109 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg); 3110 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3111 3112 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3113 if (info->default_power2 > power_bound) 3114 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound); 3115 else 3116 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2); 3117 if (is_type_ep) 3118 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg); 3119 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3120 3121 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3122 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3123 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3124 3125 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 3126 rt2x00dev->default_ant.tx_chain_num >= 1); 3127 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 3128 rt2x00dev->default_ant.tx_chain_num == 2); 3129 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3130 3131 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 3132 rt2x00dev->default_ant.rx_chain_num >= 1); 3133 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 3134 rt2x00dev->default_ant.rx_chain_num == 2); 3135 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3136 3137 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3138 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4); 3139 3140 if (conf_is_ht40(conf)) 3141 rt2800_rfcsr_write(rt2x00dev, 30, 0x16); 3142 else 3143 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 3144 3145 if (!is_11b) { 3146 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3147 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3148 } 3149 3150 /* TODO proper frequency adjustment */ 3151 rt2800_freq_cal_mode1(rt2x00dev); 3152 3153 /* TODO merge with others */ 3154 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3155 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3156 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3157 3158 /* BBP settings */ 3159 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3160 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3161 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3162 3163 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18); 3164 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08); 3165 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38); 3166 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92); 3167 3168 /* GLRT band configuration */ 3169 rt2800_bbp_write(rt2x00dev, 195, 128); 3170 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0); 3171 rt2800_bbp_write(rt2x00dev, 195, 129); 3172 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E); 3173 rt2800_bbp_write(rt2x00dev, 195, 130); 3174 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28); 3175 rt2800_bbp_write(rt2x00dev, 195, 131); 3176 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20); 3177 rt2800_bbp_write(rt2x00dev, 195, 133); 3178 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F); 3179 rt2800_bbp_write(rt2x00dev, 195, 124); 3180 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F); 3181 } 3182 3183 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev, 3184 struct ieee80211_conf *conf, 3185 struct rf_channel *rf, 3186 struct channel_info *info) 3187 { 3188 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 3189 u8 rx_agc_fc, tx_agc_fc; 3190 u8 rfcsr; 3191 3192 /* Frequeny plan setting */ 3193 /* Rdiv setting (set 0x03 if Xtal==20) 3194 * R13[1:0] 3195 */ 3196 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 3197 rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620, 3198 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0); 3199 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 3200 3201 /* N setting 3202 * R20[7:0] in rf->rf1 3203 * R21[0] always 0 3204 */ 3205 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 3206 rfcsr = (rf->rf1 & 0x00ff); 3207 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 3208 3209 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3210 rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0); 3211 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3212 3213 /* K setting (always 0) 3214 * R16[3:0] (RF PLL freq selection) 3215 */ 3216 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3217 rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0); 3218 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3219 3220 /* D setting (always 0) 3221 * R22[2:0] (D=15, R22[2:0]=<111>) 3222 */ 3223 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 3224 rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0); 3225 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 3226 3227 /* Ksd setting 3228 * Ksd: R17<7:0> in rf->rf2 3229 * R18<7:0> in rf->rf3 3230 * R19<1:0> in rf->rf4 3231 */ 3232 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 3233 rfcsr = rf->rf2; 3234 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 3235 3236 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 3237 rfcsr = rf->rf3; 3238 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 3239 3240 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19); 3241 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4); 3242 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr); 3243 3244 /* Default: XO=20MHz , SDM mode */ 3245 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3246 rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80); 3247 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3248 3249 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3250 rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1); 3251 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3252 3253 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3254 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620, 3255 rt2x00dev->default_ant.tx_chain_num != 1); 3256 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3257 3258 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 3259 rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620, 3260 rt2x00dev->default_ant.tx_chain_num != 1); 3261 rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620, 3262 rt2x00dev->default_ant.rx_chain_num != 1); 3263 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 3264 3265 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42); 3266 rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620, 3267 rt2x00dev->default_ant.tx_chain_num != 1); 3268 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 3269 3270 /* RF for DC Cal BW */ 3271 if (conf_is_ht40(conf)) { 3272 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 3273 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 3274 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 3275 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 3276 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 3277 } else { 3278 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20); 3279 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20); 3280 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00); 3281 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20); 3282 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20); 3283 } 3284 3285 if (conf_is_ht40(conf)) { 3286 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08); 3287 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08); 3288 } else { 3289 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28); 3290 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28); 3291 } 3292 3293 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28); 3294 rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40, 3295 conf_is_ht40(conf) && (rf->channel == 11)); 3296 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr); 3297 3298 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) { 3299 if (conf_is_ht40(conf)) { 3300 rx_agc_fc = drv_data->rx_calibration_bw40; 3301 tx_agc_fc = drv_data->tx_calibration_bw40; 3302 } else { 3303 rx_agc_fc = drv_data->rx_calibration_bw20; 3304 tx_agc_fc = drv_data->tx_calibration_bw20; 3305 } 3306 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 3307 rfcsr &= (~0x3F); 3308 rfcsr |= rx_agc_fc; 3309 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr); 3310 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 3311 rfcsr &= (~0x3F); 3312 rfcsr |= rx_agc_fc; 3313 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr); 3314 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6); 3315 rfcsr &= (~0x3F); 3316 rfcsr |= rx_agc_fc; 3317 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr); 3318 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7); 3319 rfcsr &= (~0x3F); 3320 rfcsr |= rx_agc_fc; 3321 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr); 3322 3323 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 3324 rfcsr &= (~0x3F); 3325 rfcsr |= tx_agc_fc; 3326 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr); 3327 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 3328 rfcsr &= (~0x3F); 3329 rfcsr |= tx_agc_fc; 3330 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr); 3331 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58); 3332 rfcsr &= (~0x3F); 3333 rfcsr |= tx_agc_fc; 3334 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr); 3335 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59); 3336 rfcsr &= (~0x3F); 3337 rfcsr |= tx_agc_fc; 3338 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr); 3339 } 3340 } 3341 3342 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev, 3343 struct ieee80211_channel *chan, 3344 int power_level) { 3345 u16 eeprom, target_power, max_power; 3346 u32 mac_sys_ctrl, mac_status; 3347 u32 reg; 3348 u8 bbp; 3349 int i; 3350 3351 /* hardware unit is 0.5dBm, limited to 23.5dBm */ 3352 power_level *= 2; 3353 if (power_level > 0x2f) 3354 power_level = 0x2f; 3355 3356 max_power = chan->max_power * 2; 3357 if (max_power > 0x2f) 3358 max_power = 0x2f; 3359 3360 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0); 3361 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, power_level); 3362 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, power_level); 3363 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, max_power); 3364 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, max_power); 3365 3366 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 3367 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) { 3368 /* init base power by eeprom target power */ 3369 target_power = rt2800_eeprom_read(rt2x00dev, 3370 EEPROM_TXPOWER_INIT); 3371 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power); 3372 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power); 3373 } 3374 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg); 3375 3376 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 3377 rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0); 3378 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 3379 3380 /* Save MAC SYS CTRL registers */ 3381 mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 3382 /* Disable Tx/Rx */ 3383 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 3384 /* Check MAC Tx/Rx idle */ 3385 for (i = 0; i < 10000; i++) { 3386 mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 3387 if (mac_status & 0x3) 3388 usleep_range(50, 200); 3389 else 3390 break; 3391 } 3392 3393 if (i == 10000) 3394 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n"); 3395 3396 if (chan->center_freq > 2457) { 3397 bbp = rt2800_bbp_read(rt2x00dev, 30); 3398 bbp = 0x40; 3399 rt2800_bbp_write(rt2x00dev, 30, bbp); 3400 rt2800_rfcsr_write(rt2x00dev, 39, 0); 3401 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3402 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb); 3403 else 3404 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b); 3405 } else { 3406 bbp = rt2800_bbp_read(rt2x00dev, 30); 3407 bbp = 0x1f; 3408 rt2800_bbp_write(rt2x00dev, 30, bbp); 3409 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 3410 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3411 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb); 3412 else 3413 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); 3414 } 3415 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl); 3416 3417 rt2800_vco_calibration(rt2x00dev); 3418 } 3419 3420 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, 3421 const unsigned int word, 3422 const u8 value) 3423 { 3424 u8 chain, reg; 3425 3426 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) { 3427 reg = rt2800_bbp_read(rt2x00dev, 27); 3428 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); 3429 rt2800_bbp_write(rt2x00dev, 27, reg); 3430 3431 rt2800_bbp_write(rt2x00dev, word, value); 3432 } 3433 } 3434 3435 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel) 3436 { 3437 u8 cal; 3438 3439 /* TX0 IQ Gain */ 3440 rt2800_bbp_write(rt2x00dev, 158, 0x2c); 3441 if (channel <= 14) 3442 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G); 3443 else if (channel >= 36 && channel <= 64) 3444 cal = rt2x00_eeprom_byte(rt2x00dev, 3445 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G); 3446 else if (channel >= 100 && channel <= 138) 3447 cal = rt2x00_eeprom_byte(rt2x00dev, 3448 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G); 3449 else if (channel >= 140 && channel <= 165) 3450 cal = rt2x00_eeprom_byte(rt2x00dev, 3451 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G); 3452 else 3453 cal = 0; 3454 rt2800_bbp_write(rt2x00dev, 159, cal); 3455 3456 /* TX0 IQ Phase */ 3457 rt2800_bbp_write(rt2x00dev, 158, 0x2d); 3458 if (channel <= 14) 3459 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G); 3460 else if (channel >= 36 && channel <= 64) 3461 cal = rt2x00_eeprom_byte(rt2x00dev, 3462 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G); 3463 else if (channel >= 100 && channel <= 138) 3464 cal = rt2x00_eeprom_byte(rt2x00dev, 3465 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G); 3466 else if (channel >= 140 && channel <= 165) 3467 cal = rt2x00_eeprom_byte(rt2x00dev, 3468 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G); 3469 else 3470 cal = 0; 3471 rt2800_bbp_write(rt2x00dev, 159, cal); 3472 3473 /* TX1 IQ Gain */ 3474 rt2800_bbp_write(rt2x00dev, 158, 0x4a); 3475 if (channel <= 14) 3476 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G); 3477 else if (channel >= 36 && channel <= 64) 3478 cal = rt2x00_eeprom_byte(rt2x00dev, 3479 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G); 3480 else if (channel >= 100 && channel <= 138) 3481 cal = rt2x00_eeprom_byte(rt2x00dev, 3482 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G); 3483 else if (channel >= 140 && channel <= 165) 3484 cal = rt2x00_eeprom_byte(rt2x00dev, 3485 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G); 3486 else 3487 cal = 0; 3488 rt2800_bbp_write(rt2x00dev, 159, cal); 3489 3490 /* TX1 IQ Phase */ 3491 rt2800_bbp_write(rt2x00dev, 158, 0x4b); 3492 if (channel <= 14) 3493 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G); 3494 else if (channel >= 36 && channel <= 64) 3495 cal = rt2x00_eeprom_byte(rt2x00dev, 3496 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G); 3497 else if (channel >= 100 && channel <= 138) 3498 cal = rt2x00_eeprom_byte(rt2x00dev, 3499 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G); 3500 else if (channel >= 140 && channel <= 165) 3501 cal = rt2x00_eeprom_byte(rt2x00dev, 3502 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G); 3503 else 3504 cal = 0; 3505 rt2800_bbp_write(rt2x00dev, 159, cal); 3506 3507 /* FIXME: possible RX0, RX1 callibration ? */ 3508 3509 /* RF IQ compensation control */ 3510 rt2800_bbp_write(rt2x00dev, 158, 0x04); 3511 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL); 3512 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3513 3514 /* RF IQ imbalance compensation control */ 3515 rt2800_bbp_write(rt2x00dev, 158, 0x03); 3516 cal = rt2x00_eeprom_byte(rt2x00dev, 3517 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL); 3518 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3519 } 3520 3521 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev, 3522 unsigned int channel, 3523 char txpower) 3524 { 3525 if (rt2x00_rt(rt2x00dev, RT3593)) 3526 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC); 3527 3528 if (channel <= 14) 3529 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER); 3530 3531 if (rt2x00_rt(rt2x00dev, RT3593)) 3532 return clamp_t(char, txpower, MIN_A_TXPOWER_3593, 3533 MAX_A_TXPOWER_3593); 3534 else 3535 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER); 3536 } 3537 3538 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 3539 struct ieee80211_conf *conf, 3540 struct rf_channel *rf, 3541 struct channel_info *info) 3542 { 3543 u32 reg; 3544 u32 tx_pin; 3545 u8 bbp, rfcsr; 3546 3547 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3548 info->default_power1); 3549 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3550 info->default_power2); 3551 if (rt2x00dev->default_ant.tx_chain_num > 2) 3552 info->default_power3 = 3553 rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3554 info->default_power3); 3555 3556 switch (rt2x00dev->chip.rf) { 3557 case RF2020: 3558 case RF3020: 3559 case RF3021: 3560 case RF3022: 3561 case RF3320: 3562 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 3563 break; 3564 case RF3052: 3565 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); 3566 break; 3567 case RF3053: 3568 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info); 3569 break; 3570 case RF3290: 3571 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info); 3572 break; 3573 case RF3322: 3574 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); 3575 break; 3576 case RF3070: 3577 case RF5350: 3578 case RF5360: 3579 case RF5362: 3580 case RF5370: 3581 case RF5372: 3582 case RF5390: 3583 case RF5392: 3584 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); 3585 break; 3586 case RF5592: 3587 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info); 3588 break; 3589 case RF7620: 3590 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info); 3591 break; 3592 default: 3593 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 3594 } 3595 3596 if (rt2x00_rf(rt2x00dev, RF3070) || 3597 rt2x00_rf(rt2x00dev, RF3290) || 3598 rt2x00_rf(rt2x00dev, RF3322) || 3599 rt2x00_rf(rt2x00dev, RF5350) || 3600 rt2x00_rf(rt2x00dev, RF5360) || 3601 rt2x00_rf(rt2x00dev, RF5362) || 3602 rt2x00_rf(rt2x00dev, RF5370) || 3603 rt2x00_rf(rt2x00dev, RF5372) || 3604 rt2x00_rf(rt2x00dev, RF5390) || 3605 rt2x00_rf(rt2x00dev, RF5392)) { 3606 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 3607 if (rt2x00_rf(rt2x00dev, RF3322)) { 3608 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M, 3609 conf_is_ht40(conf)); 3610 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M, 3611 conf_is_ht40(conf)); 3612 } else { 3613 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 3614 conf_is_ht40(conf)); 3615 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 3616 conf_is_ht40(conf)); 3617 } 3618 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 3619 3620 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3621 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3622 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3623 } 3624 3625 /* 3626 * Change BBP settings 3627 */ 3628 3629 if (rt2x00_rt(rt2x00dev, RT3352)) { 3630 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3631 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3632 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3633 3634 rt2800_bbp_write(rt2x00dev, 27, 0x0); 3635 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 3636 rt2800_bbp_write(rt2x00dev, 27, 0x20); 3637 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 3638 rt2800_bbp_write(rt2x00dev, 86, 0x38); 3639 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 3640 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 3641 if (rf->channel > 14) { 3642 /* Disable CCK Packet detection on 5GHz */ 3643 rt2800_bbp_write(rt2x00dev, 70, 0x00); 3644 } else { 3645 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 3646 } 3647 3648 if (conf_is_ht40(conf)) 3649 rt2800_bbp_write(rt2x00dev, 105, 0x04); 3650 else 3651 rt2800_bbp_write(rt2x00dev, 105, 0x34); 3652 3653 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3654 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3655 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3656 rt2800_bbp_write(rt2x00dev, 77, 0x98); 3657 } else { 3658 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3659 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3660 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3661 rt2800_bbp_write(rt2x00dev, 86, 0); 3662 } 3663 3664 if (rf->channel <= 14) { 3665 if (!rt2x00_rt(rt2x00dev, RT5390) && 3666 !rt2x00_rt(rt2x00dev, RT5392) && 3667 !rt2x00_rt(rt2x00dev, RT6352)) { 3668 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 3669 rt2800_bbp_write(rt2x00dev, 82, 0x62); 3670 rt2800_bbp_write(rt2x00dev, 75, 0x46); 3671 } else { 3672 if (rt2x00_rt(rt2x00dev, RT3593)) 3673 rt2800_bbp_write(rt2x00dev, 82, 0x62); 3674 else 3675 rt2800_bbp_write(rt2x00dev, 82, 0x84); 3676 rt2800_bbp_write(rt2x00dev, 75, 0x50); 3677 } 3678 if (rt2x00_rt(rt2x00dev, RT3593)) 3679 rt2800_bbp_write(rt2x00dev, 83, 0x8a); 3680 } 3681 3682 } else { 3683 if (rt2x00_rt(rt2x00dev, RT3572)) 3684 rt2800_bbp_write(rt2x00dev, 82, 0x94); 3685 else if (rt2x00_rt(rt2x00dev, RT3593)) 3686 rt2800_bbp_write(rt2x00dev, 82, 0x82); 3687 else if (!rt2x00_rt(rt2x00dev, RT6352)) 3688 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 3689 3690 if (rt2x00_rt(rt2x00dev, RT3593)) 3691 rt2800_bbp_write(rt2x00dev, 83, 0x9a); 3692 3693 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) 3694 rt2800_bbp_write(rt2x00dev, 75, 0x46); 3695 else 3696 rt2800_bbp_write(rt2x00dev, 75, 0x50); 3697 } 3698 3699 reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG); 3700 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); 3701 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); 3702 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); 3703 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); 3704 3705 if (rt2x00_rt(rt2x00dev, RT3572)) 3706 rt2800_rfcsr_write(rt2x00dev, 8, 0); 3707 3708 if (rt2x00_rt(rt2x00dev, RT6352)) 3709 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 3710 else 3711 tx_pin = 0; 3712 3713 switch (rt2x00dev->default_ant.tx_chain_num) { 3714 case 3: 3715 /* Turn on tertiary PAs */ 3716 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 3717 rf->channel > 14); 3718 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 3719 rf->channel <= 14); 3720 /* fall-through */ 3721 case 2: 3722 /* Turn on secondary PAs */ 3723 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 3724 rf->channel > 14); 3725 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 3726 rf->channel <= 14); 3727 /* fall-through */ 3728 case 1: 3729 /* Turn on primary PAs */ 3730 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 3731 rf->channel > 14); 3732 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) 3733 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 3734 else 3735 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 3736 rf->channel <= 14); 3737 break; 3738 } 3739 3740 switch (rt2x00dev->default_ant.rx_chain_num) { 3741 case 3: 3742 /* Turn on tertiary LNAs */ 3743 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1); 3744 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1); 3745 /* fall-through */ 3746 case 2: 3747 /* Turn on secondary LNAs */ 3748 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); 3749 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); 3750 /* fall-through */ 3751 case 1: 3752 /* Turn on primary LNAs */ 3753 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); 3754 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); 3755 break; 3756 } 3757 3758 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); 3759 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); 3760 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); /* mt7620 */ 3761 3762 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 3763 3764 if (rt2x00_rt(rt2x00dev, RT3572)) { 3765 rt2800_rfcsr_write(rt2x00dev, 8, 0x80); 3766 3767 /* AGC init */ 3768 if (rf->channel <= 14) 3769 reg = 0x1c + (2 * rt2x00dev->lna_gain); 3770 else 3771 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 3772 3773 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3774 } 3775 3776 if (rt2x00_rt(rt2x00dev, RT3593)) { 3777 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 3778 3779 /* Band selection */ 3780 if (rt2x00_is_usb(rt2x00dev) || 3781 rt2x00_is_pcie(rt2x00dev)) { 3782 /* GPIO #8 controls all paths */ 3783 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); 3784 if (rf->channel <= 14) 3785 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); 3786 else 3787 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); 3788 } 3789 3790 /* LNA PE control. */ 3791 if (rt2x00_is_usb(rt2x00dev)) { 3792 /* GPIO #4 controls PE0 and PE1, 3793 * GPIO #7 controls PE2 3794 */ 3795 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 3796 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 3797 3798 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 3799 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 3800 } else if (rt2x00_is_pcie(rt2x00dev)) { 3801 /* GPIO #4 controls PE0, PE1 and PE2 */ 3802 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 3803 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 3804 } 3805 3806 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 3807 3808 /* AGC init */ 3809 if (rf->channel <= 14) 3810 reg = 0x1c + 2 * rt2x00dev->lna_gain; 3811 else 3812 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 3813 3814 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3815 3816 usleep_range(1000, 1500); 3817 } 3818 3819 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) { 3820 reg = 0x10; 3821 if (!conf_is_ht40(conf)) { 3822 if (rt2x00_rt(rt2x00dev, RT6352) && 3823 rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 3824 reg |= 0x5; 3825 } else { 3826 reg |= 0xa; 3827 } 3828 } 3829 rt2800_bbp_write(rt2x00dev, 195, 141); 3830 rt2800_bbp_write(rt2x00dev, 196, reg); 3831 3832 /* AGC init */ 3833 if (rt2x00_rt(rt2x00dev, RT6352)) 3834 reg = 0x04; 3835 else 3836 reg = rf->channel <= 14 ? 0x1c : 0x24; 3837 3838 reg += 2 * rt2x00dev->lna_gain; 3839 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3840 3841 rt2800_iq_calibrate(rt2x00dev, rf->channel); 3842 } 3843 3844 bbp = rt2800_bbp_read(rt2x00dev, 4); 3845 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 3846 rt2800_bbp_write(rt2x00dev, 4, bbp); 3847 3848 bbp = rt2800_bbp_read(rt2x00dev, 3); 3849 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); 3850 rt2800_bbp_write(rt2x00dev, 3, bbp); 3851 3852 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 3853 if (conf_is_ht40(conf)) { 3854 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 3855 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 3856 rt2800_bbp_write(rt2x00dev, 73, 0x16); 3857 } else { 3858 rt2800_bbp_write(rt2x00dev, 69, 0x16); 3859 rt2800_bbp_write(rt2x00dev, 70, 0x08); 3860 rt2800_bbp_write(rt2x00dev, 73, 0x11); 3861 } 3862 } 3863 3864 usleep_range(1000, 1500); 3865 3866 /* 3867 * Clear channel statistic counters 3868 */ 3869 reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 3870 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 3871 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 3872 3873 /* 3874 * Clear update flag 3875 */ 3876 if (rt2x00_rt(rt2x00dev, RT3352) || 3877 rt2x00_rt(rt2x00dev, RT5350)) { 3878 bbp = rt2800_bbp_read(rt2x00dev, 49); 3879 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0); 3880 rt2800_bbp_write(rt2x00dev, 49, bbp); 3881 } 3882 } 3883 3884 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) 3885 { 3886 u8 tssi_bounds[9]; 3887 u8 current_tssi; 3888 u16 eeprom; 3889 u8 step; 3890 int i; 3891 3892 /* 3893 * First check if temperature compensation is supported. 3894 */ 3895 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 3896 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC)) 3897 return 0; 3898 3899 /* 3900 * Read TSSI boundaries for temperature compensation from 3901 * the EEPROM. 3902 * 3903 * Array idx 0 1 2 3 4 5 6 7 8 3904 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4 3905 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 3906 */ 3907 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 3908 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1); 3909 tssi_bounds[0] = rt2x00_get_field16(eeprom, 3910 EEPROM_TSSI_BOUND_BG1_MINUS4); 3911 tssi_bounds[1] = rt2x00_get_field16(eeprom, 3912 EEPROM_TSSI_BOUND_BG1_MINUS3); 3913 3914 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2); 3915 tssi_bounds[2] = rt2x00_get_field16(eeprom, 3916 EEPROM_TSSI_BOUND_BG2_MINUS2); 3917 tssi_bounds[3] = rt2x00_get_field16(eeprom, 3918 EEPROM_TSSI_BOUND_BG2_MINUS1); 3919 3920 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3); 3921 tssi_bounds[4] = rt2x00_get_field16(eeprom, 3922 EEPROM_TSSI_BOUND_BG3_REF); 3923 tssi_bounds[5] = rt2x00_get_field16(eeprom, 3924 EEPROM_TSSI_BOUND_BG3_PLUS1); 3925 3926 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4); 3927 tssi_bounds[6] = rt2x00_get_field16(eeprom, 3928 EEPROM_TSSI_BOUND_BG4_PLUS2); 3929 tssi_bounds[7] = rt2x00_get_field16(eeprom, 3930 EEPROM_TSSI_BOUND_BG4_PLUS3); 3931 3932 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5); 3933 tssi_bounds[8] = rt2x00_get_field16(eeprom, 3934 EEPROM_TSSI_BOUND_BG5_PLUS4); 3935 3936 step = rt2x00_get_field16(eeprom, 3937 EEPROM_TSSI_BOUND_BG5_AGC_STEP); 3938 } else { 3939 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1); 3940 tssi_bounds[0] = rt2x00_get_field16(eeprom, 3941 EEPROM_TSSI_BOUND_A1_MINUS4); 3942 tssi_bounds[1] = rt2x00_get_field16(eeprom, 3943 EEPROM_TSSI_BOUND_A1_MINUS3); 3944 3945 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2); 3946 tssi_bounds[2] = rt2x00_get_field16(eeprom, 3947 EEPROM_TSSI_BOUND_A2_MINUS2); 3948 tssi_bounds[3] = rt2x00_get_field16(eeprom, 3949 EEPROM_TSSI_BOUND_A2_MINUS1); 3950 3951 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3); 3952 tssi_bounds[4] = rt2x00_get_field16(eeprom, 3953 EEPROM_TSSI_BOUND_A3_REF); 3954 tssi_bounds[5] = rt2x00_get_field16(eeprom, 3955 EEPROM_TSSI_BOUND_A3_PLUS1); 3956 3957 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4); 3958 tssi_bounds[6] = rt2x00_get_field16(eeprom, 3959 EEPROM_TSSI_BOUND_A4_PLUS2); 3960 tssi_bounds[7] = rt2x00_get_field16(eeprom, 3961 EEPROM_TSSI_BOUND_A4_PLUS3); 3962 3963 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5); 3964 tssi_bounds[8] = rt2x00_get_field16(eeprom, 3965 EEPROM_TSSI_BOUND_A5_PLUS4); 3966 3967 step = rt2x00_get_field16(eeprom, 3968 EEPROM_TSSI_BOUND_A5_AGC_STEP); 3969 } 3970 3971 /* 3972 * Check if temperature compensation is supported. 3973 */ 3974 if (tssi_bounds[4] == 0xff || step == 0xff) 3975 return 0; 3976 3977 /* 3978 * Read current TSSI (BBP 49). 3979 */ 3980 current_tssi = rt2800_bbp_read(rt2x00dev, 49); 3981 3982 /* 3983 * Compare TSSI value (BBP49) with the compensation boundaries 3984 * from the EEPROM and increase or decrease tx power. 3985 */ 3986 for (i = 0; i <= 3; i++) { 3987 if (current_tssi > tssi_bounds[i]) 3988 break; 3989 } 3990 3991 if (i == 4) { 3992 for (i = 8; i >= 5; i--) { 3993 if (current_tssi < tssi_bounds[i]) 3994 break; 3995 } 3996 } 3997 3998 return (i - 4) * step; 3999 } 4000 4001 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, 4002 enum nl80211_band band) 4003 { 4004 u16 eeprom; 4005 u8 comp_en; 4006 u8 comp_type; 4007 int comp_value = 0; 4008 4009 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA); 4010 4011 /* 4012 * HT40 compensation not required. 4013 */ 4014 if (eeprom == 0xffff || 4015 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4016 return 0; 4017 4018 if (band == NL80211_BAND_2GHZ) { 4019 comp_en = rt2x00_get_field16(eeprom, 4020 EEPROM_TXPOWER_DELTA_ENABLE_2G); 4021 if (comp_en) { 4022 comp_type = rt2x00_get_field16(eeprom, 4023 EEPROM_TXPOWER_DELTA_TYPE_2G); 4024 comp_value = rt2x00_get_field16(eeprom, 4025 EEPROM_TXPOWER_DELTA_VALUE_2G); 4026 if (!comp_type) 4027 comp_value = -comp_value; 4028 } 4029 } else { 4030 comp_en = rt2x00_get_field16(eeprom, 4031 EEPROM_TXPOWER_DELTA_ENABLE_5G); 4032 if (comp_en) { 4033 comp_type = rt2x00_get_field16(eeprom, 4034 EEPROM_TXPOWER_DELTA_TYPE_5G); 4035 comp_value = rt2x00_get_field16(eeprom, 4036 EEPROM_TXPOWER_DELTA_VALUE_5G); 4037 if (!comp_type) 4038 comp_value = -comp_value; 4039 } 4040 } 4041 4042 return comp_value; 4043 } 4044 4045 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev, 4046 int power_level, int max_power) 4047 { 4048 int delta; 4049 4050 if (rt2x00_has_cap_power_limit(rt2x00dev)) 4051 return 0; 4052 4053 /* 4054 * XXX: We don't know the maximum transmit power of our hardware since 4055 * the EEPROM doesn't expose it. We only know that we are calibrated 4056 * to 100% tx power. 4057 * 4058 * Hence, we assume the regulatory limit that cfg80211 calulated for 4059 * the current channel is our maximum and if we are requested to lower 4060 * the value we just reduce our tx power accordingly. 4061 */ 4062 delta = power_level - max_power; 4063 return min(delta, 0); 4064 } 4065 4066 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, 4067 enum nl80211_band band, int power_level, 4068 u8 txpower, int delta) 4069 { 4070 u16 eeprom; 4071 u8 criterion; 4072 u8 eirp_txpower; 4073 u8 eirp_txpower_criterion; 4074 u8 reg_limit; 4075 4076 if (rt2x00_rt(rt2x00dev, RT3593)) 4077 return min_t(u8, txpower, 0xc); 4078 4079 if (rt2x00_has_cap_power_limit(rt2x00dev)) { 4080 /* 4081 * Check if eirp txpower exceed txpower_limit. 4082 * We use OFDM 6M as criterion and its eirp txpower 4083 * is stored at EEPROM_EIRP_MAX_TX_POWER. 4084 * .11b data rate need add additional 4dbm 4085 * when calculating eirp txpower. 4086 */ 4087 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4088 EEPROM_TXPOWER_BYRATE, 4089 1); 4090 criterion = rt2x00_get_field16(eeprom, 4091 EEPROM_TXPOWER_BYRATE_RATE0); 4092 4093 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 4094 4095 if (band == NL80211_BAND_2GHZ) 4096 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4097 EEPROM_EIRP_MAX_TX_POWER_2GHZ); 4098 else 4099 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4100 EEPROM_EIRP_MAX_TX_POWER_5GHZ); 4101 4102 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) + 4103 (is_rate_b ? 4 : 0) + delta; 4104 4105 reg_limit = (eirp_txpower > power_level) ? 4106 (eirp_txpower - power_level) : 0; 4107 } else 4108 reg_limit = 0; 4109 4110 txpower = max(0, txpower + delta - reg_limit); 4111 return min_t(u8, txpower, 0xc); 4112 } 4113 4114 4115 enum { 4116 TX_PWR_CFG_0_IDX, 4117 TX_PWR_CFG_1_IDX, 4118 TX_PWR_CFG_2_IDX, 4119 TX_PWR_CFG_3_IDX, 4120 TX_PWR_CFG_4_IDX, 4121 TX_PWR_CFG_5_IDX, 4122 TX_PWR_CFG_6_IDX, 4123 TX_PWR_CFG_7_IDX, 4124 TX_PWR_CFG_8_IDX, 4125 TX_PWR_CFG_9_IDX, 4126 TX_PWR_CFG_0_EXT_IDX, 4127 TX_PWR_CFG_1_EXT_IDX, 4128 TX_PWR_CFG_2_EXT_IDX, 4129 TX_PWR_CFG_3_EXT_IDX, 4130 TX_PWR_CFG_4_EXT_IDX, 4131 TX_PWR_CFG_IDX_COUNT, 4132 }; 4133 4134 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, 4135 struct ieee80211_channel *chan, 4136 int power_level) 4137 { 4138 u8 txpower; 4139 u16 eeprom; 4140 u32 regs[TX_PWR_CFG_IDX_COUNT]; 4141 unsigned int offset; 4142 enum nl80211_band band = chan->band; 4143 int delta; 4144 int i; 4145 4146 memset(regs, '\0', sizeof(regs)); 4147 4148 /* TODO: adapt TX power reduction from the rt28xx code */ 4149 4150 /* calculate temperature compensation delta */ 4151 delta = rt2800_get_gain_calibration_delta(rt2x00dev); 4152 4153 if (band == NL80211_BAND_5GHZ) 4154 offset = 16; 4155 else 4156 offset = 0; 4157 4158 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4159 offset += 8; 4160 4161 /* read the next four txpower values */ 4162 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4163 offset); 4164 4165 /* CCK 1MBS,2MBS */ 4166 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4167 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4168 txpower, delta); 4169 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4170 TX_PWR_CFG_0_CCK1_CH0, txpower); 4171 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4172 TX_PWR_CFG_0_CCK1_CH1, txpower); 4173 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4174 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower); 4175 4176 /* CCK 5.5MBS,11MBS */ 4177 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4178 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4179 txpower, delta); 4180 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4181 TX_PWR_CFG_0_CCK5_CH0, txpower); 4182 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4183 TX_PWR_CFG_0_CCK5_CH1, txpower); 4184 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4185 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower); 4186 4187 /* OFDM 6MBS,9MBS */ 4188 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4189 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4190 txpower, delta); 4191 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4192 TX_PWR_CFG_0_OFDM6_CH0, txpower); 4193 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4194 TX_PWR_CFG_0_OFDM6_CH1, txpower); 4195 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4196 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower); 4197 4198 /* OFDM 12MBS,18MBS */ 4199 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4200 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4201 txpower, delta); 4202 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4203 TX_PWR_CFG_0_OFDM12_CH0, txpower); 4204 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4205 TX_PWR_CFG_0_OFDM12_CH1, txpower); 4206 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4207 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower); 4208 4209 /* read the next four txpower values */ 4210 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4211 offset + 1); 4212 4213 /* OFDM 24MBS,36MBS */ 4214 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4215 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4216 txpower, delta); 4217 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4218 TX_PWR_CFG_1_OFDM24_CH0, txpower); 4219 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4220 TX_PWR_CFG_1_OFDM24_CH1, txpower); 4221 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4222 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower); 4223 4224 /* OFDM 48MBS */ 4225 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4226 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4227 txpower, delta); 4228 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4229 TX_PWR_CFG_1_OFDM48_CH0, txpower); 4230 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4231 TX_PWR_CFG_1_OFDM48_CH1, txpower); 4232 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4233 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower); 4234 4235 /* OFDM 54MBS */ 4236 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4237 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4238 txpower, delta); 4239 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4240 TX_PWR_CFG_7_OFDM54_CH0, txpower); 4241 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4242 TX_PWR_CFG_7_OFDM54_CH1, txpower); 4243 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4244 TX_PWR_CFG_7_OFDM54_CH2, txpower); 4245 4246 /* read the next four txpower values */ 4247 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4248 offset + 2); 4249 4250 /* MCS 0,1 */ 4251 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4252 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4253 txpower, delta); 4254 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4255 TX_PWR_CFG_1_MCS0_CH0, txpower); 4256 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4257 TX_PWR_CFG_1_MCS0_CH1, txpower); 4258 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4259 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower); 4260 4261 /* MCS 2,3 */ 4262 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4263 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4264 txpower, delta); 4265 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4266 TX_PWR_CFG_1_MCS2_CH0, txpower); 4267 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4268 TX_PWR_CFG_1_MCS2_CH1, txpower); 4269 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4270 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower); 4271 4272 /* MCS 4,5 */ 4273 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4274 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4275 txpower, delta); 4276 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4277 TX_PWR_CFG_2_MCS4_CH0, txpower); 4278 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4279 TX_PWR_CFG_2_MCS4_CH1, txpower); 4280 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4281 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower); 4282 4283 /* MCS 6 */ 4284 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4285 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4286 txpower, delta); 4287 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4288 TX_PWR_CFG_2_MCS6_CH0, txpower); 4289 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4290 TX_PWR_CFG_2_MCS6_CH1, txpower); 4291 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4292 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower); 4293 4294 /* read the next four txpower values */ 4295 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4296 offset + 3); 4297 4298 /* MCS 7 */ 4299 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4300 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4301 txpower, delta); 4302 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4303 TX_PWR_CFG_7_MCS7_CH0, txpower); 4304 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4305 TX_PWR_CFG_7_MCS7_CH1, txpower); 4306 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4307 TX_PWR_CFG_7_MCS7_CH2, txpower); 4308 4309 /* MCS 8,9 */ 4310 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4311 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4312 txpower, delta); 4313 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4314 TX_PWR_CFG_2_MCS8_CH0, txpower); 4315 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4316 TX_PWR_CFG_2_MCS8_CH1, txpower); 4317 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4318 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower); 4319 4320 /* MCS 10,11 */ 4321 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4322 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4323 txpower, delta); 4324 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4325 TX_PWR_CFG_2_MCS10_CH0, txpower); 4326 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4327 TX_PWR_CFG_2_MCS10_CH1, txpower); 4328 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4329 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower); 4330 4331 /* MCS 12,13 */ 4332 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4333 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4334 txpower, delta); 4335 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4336 TX_PWR_CFG_3_MCS12_CH0, txpower); 4337 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4338 TX_PWR_CFG_3_MCS12_CH1, txpower); 4339 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4340 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower); 4341 4342 /* read the next four txpower values */ 4343 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4344 offset + 4); 4345 4346 /* MCS 14 */ 4347 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4348 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4349 txpower, delta); 4350 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4351 TX_PWR_CFG_3_MCS14_CH0, txpower); 4352 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4353 TX_PWR_CFG_3_MCS14_CH1, txpower); 4354 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4355 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower); 4356 4357 /* MCS 15 */ 4358 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4359 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4360 txpower, delta); 4361 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4362 TX_PWR_CFG_8_MCS15_CH0, txpower); 4363 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4364 TX_PWR_CFG_8_MCS15_CH1, txpower); 4365 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4366 TX_PWR_CFG_8_MCS15_CH2, txpower); 4367 4368 /* MCS 16,17 */ 4369 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4370 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4371 txpower, delta); 4372 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4373 TX_PWR_CFG_5_MCS16_CH0, txpower); 4374 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4375 TX_PWR_CFG_5_MCS16_CH1, txpower); 4376 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4377 TX_PWR_CFG_5_MCS16_CH2, txpower); 4378 4379 /* MCS 18,19 */ 4380 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4381 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4382 txpower, delta); 4383 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4384 TX_PWR_CFG_5_MCS18_CH0, txpower); 4385 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4386 TX_PWR_CFG_5_MCS18_CH1, txpower); 4387 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4388 TX_PWR_CFG_5_MCS18_CH2, txpower); 4389 4390 /* read the next four txpower values */ 4391 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4392 offset + 5); 4393 4394 /* MCS 20,21 */ 4395 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4396 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4397 txpower, delta); 4398 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4399 TX_PWR_CFG_6_MCS20_CH0, txpower); 4400 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4401 TX_PWR_CFG_6_MCS20_CH1, txpower); 4402 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4403 TX_PWR_CFG_6_MCS20_CH2, txpower); 4404 4405 /* MCS 22 */ 4406 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4407 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4408 txpower, delta); 4409 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4410 TX_PWR_CFG_6_MCS22_CH0, txpower); 4411 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4412 TX_PWR_CFG_6_MCS22_CH1, txpower); 4413 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4414 TX_PWR_CFG_6_MCS22_CH2, txpower); 4415 4416 /* MCS 23 */ 4417 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4418 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4419 txpower, delta); 4420 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4421 TX_PWR_CFG_8_MCS23_CH0, txpower); 4422 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4423 TX_PWR_CFG_8_MCS23_CH1, txpower); 4424 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4425 TX_PWR_CFG_8_MCS23_CH2, txpower); 4426 4427 /* read the next four txpower values */ 4428 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4429 offset + 6); 4430 4431 /* STBC, MCS 0,1 */ 4432 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4433 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4434 txpower, delta); 4435 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4436 TX_PWR_CFG_3_STBC0_CH0, txpower); 4437 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4438 TX_PWR_CFG_3_STBC0_CH1, txpower); 4439 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4440 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower); 4441 4442 /* STBC, MCS 2,3 */ 4443 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4444 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4445 txpower, delta); 4446 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4447 TX_PWR_CFG_3_STBC2_CH0, txpower); 4448 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4449 TX_PWR_CFG_3_STBC2_CH1, txpower); 4450 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4451 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower); 4452 4453 /* STBC, MCS 4,5 */ 4454 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4455 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4456 txpower, delta); 4457 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); 4458 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); 4459 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, 4460 txpower); 4461 4462 /* STBC, MCS 6 */ 4463 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4464 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4465 txpower, delta); 4466 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); 4467 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); 4468 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, 4469 txpower); 4470 4471 /* read the next four txpower values */ 4472 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4473 offset + 7); 4474 4475 /* STBC, MCS 7 */ 4476 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4477 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4478 txpower, delta); 4479 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4480 TX_PWR_CFG_9_STBC7_CH0, txpower); 4481 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4482 TX_PWR_CFG_9_STBC7_CH1, txpower); 4483 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4484 TX_PWR_CFG_9_STBC7_CH2, txpower); 4485 4486 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]); 4487 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]); 4488 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]); 4489 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]); 4490 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]); 4491 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]); 4492 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]); 4493 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]); 4494 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]); 4495 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]); 4496 4497 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT, 4498 regs[TX_PWR_CFG_0_EXT_IDX]); 4499 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT, 4500 regs[TX_PWR_CFG_1_EXT_IDX]); 4501 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT, 4502 regs[TX_PWR_CFG_2_EXT_IDX]); 4503 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT, 4504 regs[TX_PWR_CFG_3_EXT_IDX]); 4505 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT, 4506 regs[TX_PWR_CFG_4_EXT_IDX]); 4507 4508 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++) 4509 rt2x00_dbg(rt2x00dev, 4510 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n", 4511 (band == NL80211_BAND_5GHZ) ? '5' : '2', 4512 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ? 4513 '4' : '2', 4514 (i > TX_PWR_CFG_9_IDX) ? 4515 (i - TX_PWR_CFG_9_IDX - 1) : i, 4516 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "", 4517 (unsigned long) regs[i]); 4518 } 4519 4520 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev, 4521 struct ieee80211_channel *chan, 4522 int power_level) 4523 { 4524 u32 reg, pwreg; 4525 u16 eeprom; 4526 u32 data, gdata; 4527 u8 t, i; 4528 enum nl80211_band band = chan->band; 4529 int delta; 4530 4531 /* Warn user if bw_comp is set in EEPROM */ 4532 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 4533 4534 if (delta) 4535 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n", 4536 delta); 4537 4538 /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit 4539 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor 4540 * driver does as well, though it looks kinda wrong. 4541 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe 4542 * the hardware has a problem handling 0x20, and as the code initially 4543 * used a fixed offset between HT20 and HT40 rates they had to work- 4544 * around that issue and most likely just forgot about it later on. 4545 * Maybe we should use rt2800_get_txpower_bw_comp() here as well, 4546 * however, the corresponding EEPROM value is not respected by the 4547 * vendor driver, so maybe this is rather being taken care of the 4548 * TXALC and the driver doesn't need to handle it...? 4549 * Though this is all very awkward, just do as they did, as that's what 4550 * board vendors expected when they populated the EEPROM... 4551 */ 4552 for (i = 0; i < 5; i++) { 4553 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4554 EEPROM_TXPOWER_BYRATE, 4555 i * 2); 4556 4557 data = eeprom; 4558 4559 t = eeprom & 0x3f; 4560 if (t == 32) 4561 t++; 4562 4563 gdata = t; 4564 4565 t = (eeprom & 0x3f00) >> 8; 4566 if (t == 32) 4567 t++; 4568 4569 gdata |= (t << 8); 4570 4571 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4572 EEPROM_TXPOWER_BYRATE, 4573 (i * 2) + 1); 4574 4575 t = eeprom & 0x3f; 4576 if (t == 32) 4577 t++; 4578 4579 gdata |= (t << 16); 4580 4581 t = (eeprom & 0x3f00) >> 8; 4582 if (t == 32) 4583 t++; 4584 4585 gdata |= (t << 24); 4586 data |= (eeprom << 16); 4587 4588 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) { 4589 /* HT20 */ 4590 if (data != 0xffffffff) 4591 rt2800_register_write(rt2x00dev, 4592 TX_PWR_CFG_0 + (i * 4), 4593 data); 4594 } else { 4595 /* HT40 */ 4596 if (gdata != 0xffffffff) 4597 rt2800_register_write(rt2x00dev, 4598 TX_PWR_CFG_0 + (i * 4), 4599 gdata); 4600 } 4601 } 4602 4603 /* Aparently Ralink ran out of space in the BYRATE calibration section 4604 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x 4605 * registers. As recent 2T chips use 8-bit instead of 4-bit values for 4606 * power-offsets more space would be needed. Ralink decided to keep the 4607 * EEPROM layout untouched and rather have some shared values covering 4608 * multiple bitrates. 4609 * Populate the registers not covered by the EEPROM in the same way the 4610 * vendor driver does. 4611 */ 4612 4613 /* For OFDM 54MBS use value from OFDM 48MBS */ 4614 pwreg = 0; 4615 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1); 4616 t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS); 4617 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t); 4618 4619 /* For MCS 7 use value from MCS 6 */ 4620 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2); 4621 t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7); 4622 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t); 4623 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg); 4624 4625 /* For MCS 15 use value from MCS 14 */ 4626 pwreg = 0; 4627 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3); 4628 t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14); 4629 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t); 4630 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg); 4631 4632 /* For STBC MCS 7 use value from STBC MCS 6 */ 4633 pwreg = 0; 4634 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4); 4635 t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6); 4636 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); 4637 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg); 4638 4639 rt2800_config_alc(rt2x00dev, chan, power_level); 4640 4641 /* TODO: temperature compensation code! */ 4642 } 4643 4644 /* 4645 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and 4646 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values, 4647 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power 4648 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm. 4649 * Reference per rate transmit power values are located in the EEPROM at 4650 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to 4651 * current conditions (i.e. band, bandwidth, temperature, user settings). 4652 */ 4653 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, 4654 struct ieee80211_channel *chan, 4655 int power_level) 4656 { 4657 u8 txpower, r1; 4658 u16 eeprom; 4659 u32 reg, offset; 4660 int i, is_rate_b, delta, power_ctrl; 4661 enum nl80211_band band = chan->band; 4662 4663 /* 4664 * Calculate HT40 compensation. For 40MHz we need to add or subtract 4665 * value read from EEPROM (different for 2GHz and for 5GHz). 4666 */ 4667 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 4668 4669 /* 4670 * Calculate temperature compensation. Depends on measurement of current 4671 * TSSI (Transmitter Signal Strength Indication) we know TX power (due 4672 * to temperature or maybe other factors) is smaller or bigger than 4673 * expected. We adjust it, based on TSSI reference and boundaries values 4674 * provided in EEPROM. 4675 */ 4676 switch (rt2x00dev->chip.rt) { 4677 case RT2860: 4678 case RT2872: 4679 case RT2883: 4680 case RT3070: 4681 case RT3071: 4682 case RT3090: 4683 case RT3572: 4684 delta += rt2800_get_gain_calibration_delta(rt2x00dev); 4685 break; 4686 default: 4687 /* TODO: temperature compensation code for other chips. */ 4688 break; 4689 } 4690 4691 /* 4692 * Decrease power according to user settings, on devices with unknown 4693 * maximum tx power. For other devices we take user power_level into 4694 * consideration on rt2800_compensate_txpower(). 4695 */ 4696 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level, 4697 chan->max_power); 4698 4699 /* 4700 * BBP_R1 controls TX power for all rates, it allow to set the following 4701 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively. 4702 * 4703 * TODO: we do not use +6 dBm option to do not increase power beyond 4704 * regulatory limit, however this could be utilized for devices with 4705 * CAPABILITY_POWER_LIMIT. 4706 */ 4707 if (delta <= -12) { 4708 power_ctrl = 2; 4709 delta += 12; 4710 } else if (delta <= -6) { 4711 power_ctrl = 1; 4712 delta += 6; 4713 } else { 4714 power_ctrl = 0; 4715 } 4716 r1 = rt2800_bbp_read(rt2x00dev, 1); 4717 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl); 4718 rt2800_bbp_write(rt2x00dev, 1, r1); 4719 4720 offset = TX_PWR_CFG_0; 4721 4722 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { 4723 /* just to be safe */ 4724 if (offset > TX_PWR_CFG_4) 4725 break; 4726 4727 reg = rt2800_register_read(rt2x00dev, offset); 4728 4729 /* read the next four txpower values */ 4730 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4731 EEPROM_TXPOWER_BYRATE, 4732 i); 4733 4734 is_rate_b = i ? 0 : 1; 4735 /* 4736 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, 4737 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, 4738 * TX_PWR_CFG_4: unknown 4739 */ 4740 txpower = rt2x00_get_field16(eeprom, 4741 EEPROM_TXPOWER_BYRATE_RATE0); 4742 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4743 power_level, txpower, delta); 4744 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); 4745 4746 /* 4747 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, 4748 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, 4749 * TX_PWR_CFG_4: unknown 4750 */ 4751 txpower = rt2x00_get_field16(eeprom, 4752 EEPROM_TXPOWER_BYRATE_RATE1); 4753 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4754 power_level, txpower, delta); 4755 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); 4756 4757 /* 4758 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS, 4759 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, 4760 * TX_PWR_CFG_4: unknown 4761 */ 4762 txpower = rt2x00_get_field16(eeprom, 4763 EEPROM_TXPOWER_BYRATE_RATE2); 4764 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4765 power_level, txpower, delta); 4766 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); 4767 4768 /* 4769 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, 4770 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, 4771 * TX_PWR_CFG_4: unknown 4772 */ 4773 txpower = rt2x00_get_field16(eeprom, 4774 EEPROM_TXPOWER_BYRATE_RATE3); 4775 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4776 power_level, txpower, delta); 4777 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); 4778 4779 /* read the next four txpower values */ 4780 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4781 EEPROM_TXPOWER_BYRATE, 4782 i + 1); 4783 4784 is_rate_b = 0; 4785 /* 4786 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, 4787 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, 4788 * TX_PWR_CFG_4: unknown 4789 */ 4790 txpower = rt2x00_get_field16(eeprom, 4791 EEPROM_TXPOWER_BYRATE_RATE0); 4792 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4793 power_level, txpower, delta); 4794 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); 4795 4796 /* 4797 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, 4798 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, 4799 * TX_PWR_CFG_4: unknown 4800 */ 4801 txpower = rt2x00_get_field16(eeprom, 4802 EEPROM_TXPOWER_BYRATE_RATE1); 4803 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4804 power_level, txpower, delta); 4805 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); 4806 4807 /* 4808 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, 4809 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, 4810 * TX_PWR_CFG_4: unknown 4811 */ 4812 txpower = rt2x00_get_field16(eeprom, 4813 EEPROM_TXPOWER_BYRATE_RATE2); 4814 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4815 power_level, txpower, delta); 4816 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); 4817 4818 /* 4819 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, 4820 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, 4821 * TX_PWR_CFG_4: unknown 4822 */ 4823 txpower = rt2x00_get_field16(eeprom, 4824 EEPROM_TXPOWER_BYRATE_RATE3); 4825 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4826 power_level, txpower, delta); 4827 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); 4828 4829 rt2800_register_write(rt2x00dev, offset, reg); 4830 4831 /* next TX_PWR_CFG register */ 4832 offset += 4; 4833 } 4834 } 4835 4836 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, 4837 struct ieee80211_channel *chan, 4838 int power_level) 4839 { 4840 if (rt2x00_rt(rt2x00dev, RT3593)) 4841 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level); 4842 else if (rt2x00_rt(rt2x00dev, RT6352)) 4843 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level); 4844 else 4845 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level); 4846 } 4847 4848 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) 4849 { 4850 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan, 4851 rt2x00dev->tx_power); 4852 } 4853 EXPORT_SYMBOL_GPL(rt2800_gain_calibration); 4854 4855 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) 4856 { 4857 u32 tx_pin; 4858 u8 rfcsr; 4859 unsigned long min_sleep = 0; 4860 4861 /* 4862 * A voltage-controlled oscillator(VCO) is an electronic oscillator 4863 * designed to be controlled in oscillation frequency by a voltage 4864 * input. Maybe the temperature will affect the frequency of 4865 * oscillation to be shifted. The VCO calibration will be called 4866 * periodically to adjust the frequency to be precision. 4867 */ 4868 4869 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 4870 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE; 4871 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 4872 4873 switch (rt2x00dev->chip.rf) { 4874 case RF2020: 4875 case RF3020: 4876 case RF3021: 4877 case RF3022: 4878 case RF3320: 4879 case RF3052: 4880 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 4881 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 4882 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 4883 break; 4884 case RF3053: 4885 case RF3070: 4886 case RF3290: 4887 case RF5350: 4888 case RF5360: 4889 case RF5362: 4890 case RF5370: 4891 case RF5372: 4892 case RF5390: 4893 case RF5392: 4894 case RF5592: 4895 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 4896 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 4897 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 4898 min_sleep = 1000; 4899 break; 4900 case RF7620: 4901 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 4902 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 4903 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4); 4904 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1); 4905 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr); 4906 min_sleep = 2000; 4907 break; 4908 default: 4909 WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration", 4910 rt2x00dev->chip.rf); 4911 return; 4912 } 4913 4914 if (min_sleep > 0) 4915 usleep_range(min_sleep, min_sleep * 2); 4916 4917 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 4918 if (rt2x00dev->rf_channel <= 14) { 4919 switch (rt2x00dev->default_ant.tx_chain_num) { 4920 case 3: 4921 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); 4922 /* fall through */ 4923 case 2: 4924 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 4925 /* fall through */ 4926 case 1: 4927 default: 4928 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 4929 break; 4930 } 4931 } else { 4932 switch (rt2x00dev->default_ant.tx_chain_num) { 4933 case 3: 4934 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); 4935 /* fall through */ 4936 case 2: 4937 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 4938 /* fall through */ 4939 case 1: 4940 default: 4941 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); 4942 break; 4943 } 4944 } 4945 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 4946 4947 if (rt2x00_rt(rt2x00dev, RT6352)) { 4948 if (rt2x00dev->default_ant.rx_chain_num == 1) { 4949 rt2800_bbp_write(rt2x00dev, 91, 0x07); 4950 rt2800_bbp_write(rt2x00dev, 95, 0x1A); 4951 rt2800_bbp_write(rt2x00dev, 195, 128); 4952 rt2800_bbp_write(rt2x00dev, 196, 0xA0); 4953 rt2800_bbp_write(rt2x00dev, 195, 170); 4954 rt2800_bbp_write(rt2x00dev, 196, 0x12); 4955 rt2800_bbp_write(rt2x00dev, 195, 171); 4956 rt2800_bbp_write(rt2x00dev, 196, 0x10); 4957 } else { 4958 rt2800_bbp_write(rt2x00dev, 91, 0x06); 4959 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 4960 rt2800_bbp_write(rt2x00dev, 195, 128); 4961 rt2800_bbp_write(rt2x00dev, 196, 0xE0); 4962 rt2800_bbp_write(rt2x00dev, 195, 170); 4963 rt2800_bbp_write(rt2x00dev, 196, 0x30); 4964 rt2800_bbp_write(rt2x00dev, 195, 171); 4965 rt2800_bbp_write(rt2x00dev, 196, 0x30); 4966 } 4967 4968 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 4969 rt2800_bbp_write(rt2x00dev, 75, 0x68); 4970 rt2800_bbp_write(rt2x00dev, 76, 0x4C); 4971 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 4972 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 4973 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 4974 } 4975 4976 /* On 11A, We should delay and wait RF/BBP to be stable 4977 * and the appropriate time should be 1000 micro seconds 4978 * 2005/06/05 - On 11G, we also need this delay time. 4979 * Otherwise it's difficult to pass the WHQL. 4980 */ 4981 usleep_range(1000, 1500); 4982 } 4983 } 4984 EXPORT_SYMBOL_GPL(rt2800_vco_calibration); 4985 4986 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, 4987 struct rt2x00lib_conf *libconf) 4988 { 4989 u32 reg; 4990 4991 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 4992 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 4993 libconf->conf->short_frame_max_tx_count); 4994 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 4995 libconf->conf->long_frame_max_tx_count); 4996 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 4997 } 4998 4999 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, 5000 struct rt2x00lib_conf *libconf) 5001 { 5002 enum dev_state state = 5003 (libconf->conf->flags & IEEE80211_CONF_PS) ? 5004 STATE_SLEEP : STATE_AWAKE; 5005 u32 reg; 5006 5007 if (state == STATE_SLEEP) { 5008 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); 5009 5010 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5011 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); 5012 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 5013 libconf->conf->listen_interval - 1); 5014 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); 5015 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5016 5017 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5018 } else { 5019 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5020 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 5021 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 5022 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); 5023 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5024 5025 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5026 } 5027 } 5028 5029 void rt2800_config(struct rt2x00_dev *rt2x00dev, 5030 struct rt2x00lib_conf *libconf, 5031 const unsigned int flags) 5032 { 5033 /* Always recalculate LNA gain before changing configuration */ 5034 rt2800_config_lna_gain(rt2x00dev, libconf); 5035 5036 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { 5037 rt2800_config_channel(rt2x00dev, libconf->conf, 5038 &libconf->rf, &libconf->channel); 5039 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5040 libconf->conf->power_level); 5041 } 5042 if (flags & IEEE80211_CONF_CHANGE_POWER) 5043 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5044 libconf->conf->power_level); 5045 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 5046 rt2800_config_retry_limit(rt2x00dev, libconf); 5047 if (flags & IEEE80211_CONF_CHANGE_PS) 5048 rt2800_config_ps(rt2x00dev, libconf); 5049 } 5050 EXPORT_SYMBOL_GPL(rt2800_config); 5051 5052 /* 5053 * Link tuning 5054 */ 5055 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5056 { 5057 u32 reg; 5058 5059 /* 5060 * Update FCS error count from register. 5061 */ 5062 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 5063 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); 5064 } 5065 EXPORT_SYMBOL_GPL(rt2800_link_stats); 5066 5067 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 5068 { 5069 u8 vgc; 5070 5071 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 5072 if (rt2x00_rt(rt2x00dev, RT3070) || 5073 rt2x00_rt(rt2x00dev, RT3071) || 5074 rt2x00_rt(rt2x00dev, RT3090) || 5075 rt2x00_rt(rt2x00dev, RT3290) || 5076 rt2x00_rt(rt2x00dev, RT3390) || 5077 rt2x00_rt(rt2x00dev, RT3572) || 5078 rt2x00_rt(rt2x00dev, RT3593) || 5079 rt2x00_rt(rt2x00dev, RT5390) || 5080 rt2x00_rt(rt2x00dev, RT5392) || 5081 rt2x00_rt(rt2x00dev, RT5592) || 5082 rt2x00_rt(rt2x00dev, RT6352)) 5083 vgc = 0x1c + (2 * rt2x00dev->lna_gain); 5084 else 5085 vgc = 0x2e + rt2x00dev->lna_gain; 5086 } else { /* 5GHZ band */ 5087 if (rt2x00_rt(rt2x00dev, RT3593)) 5088 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3; 5089 else if (rt2x00_rt(rt2x00dev, RT5592)) 5090 vgc = 0x24 + (2 * rt2x00dev->lna_gain); 5091 else { 5092 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 5093 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3; 5094 else 5095 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3; 5096 } 5097 } 5098 5099 return vgc; 5100 } 5101 5102 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, 5103 struct link_qual *qual, u8 vgc_level) 5104 { 5105 if (qual->vgc_level != vgc_level) { 5106 if (rt2x00_rt(rt2x00dev, RT3572) || 5107 rt2x00_rt(rt2x00dev, RT3593)) { 5108 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, 5109 vgc_level); 5110 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5111 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a); 5112 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level); 5113 } else { 5114 rt2800_bbp_write(rt2x00dev, 66, vgc_level); 5115 } 5116 5117 qual->vgc_level = vgc_level; 5118 qual->vgc_level_reg = vgc_level; 5119 } 5120 } 5121 5122 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5123 { 5124 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); 5125 } 5126 EXPORT_SYMBOL_GPL(rt2800_reset_tuner); 5127 5128 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 5129 const u32 count) 5130 { 5131 u8 vgc; 5132 5133 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) 5134 return; 5135 5136 /* When RSSI is better than a certain threshold, increase VGC 5137 * with a chip specific value in order to improve the balance 5138 * between sensibility and noise isolation. 5139 */ 5140 5141 vgc = rt2800_get_default_vgc(rt2x00dev); 5142 5143 switch (rt2x00dev->chip.rt) { 5144 case RT3572: 5145 case RT3593: 5146 if (qual->rssi > -65) { 5147 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) 5148 vgc += 0x20; 5149 else 5150 vgc += 0x10; 5151 } 5152 break; 5153 5154 case RT5592: 5155 if (qual->rssi > -65) 5156 vgc += 0x20; 5157 break; 5158 5159 default: 5160 if (qual->rssi > -80) 5161 vgc += 0x10; 5162 break; 5163 } 5164 5165 rt2800_set_vgc(rt2x00dev, qual, vgc); 5166 } 5167 EXPORT_SYMBOL_GPL(rt2800_link_tuner); 5168 5169 /* 5170 * Initialization functions. 5171 */ 5172 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 5173 { 5174 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5175 u32 reg; 5176 u16 eeprom; 5177 unsigned int i; 5178 int ret; 5179 5180 rt2800_disable_wpdma(rt2x00dev); 5181 5182 ret = rt2800_drv_init_registers(rt2x00dev); 5183 if (ret) 5184 return ret; 5185 5186 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); 5187 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 5188 5189 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 5190 5191 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 5192 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); 5193 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); 5194 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); 5195 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); 5196 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 5197 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 5198 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 5199 5200 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); 5201 5202 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 5203 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); 5204 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 5205 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 5206 5207 if (rt2x00_rt(rt2x00dev, RT3290)) { 5208 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 5209 if (rt2x00_get_field32(reg, WLAN_EN) == 1) { 5210 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); 5211 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 5212 } 5213 5214 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 5215 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { 5216 rt2x00_set_field32(®, LDO0_EN, 1); 5217 rt2x00_set_field32(®, LDO_BGSEL, 3); 5218 rt2800_register_write(rt2x00dev, CMB_CTRL, reg); 5219 } 5220 5221 reg = rt2800_register_read(rt2x00dev, OSC_CTRL); 5222 rt2x00_set_field32(®, OSC_ROSC_EN, 1); 5223 rt2x00_set_field32(®, OSC_CAL_REQ, 1); 5224 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); 5225 rt2800_register_write(rt2x00dev, OSC_CTRL, reg); 5226 5227 reg = rt2800_register_read(rt2x00dev, COEX_CFG0); 5228 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); 5229 rt2800_register_write(rt2x00dev, COEX_CFG0, reg); 5230 5231 reg = rt2800_register_read(rt2x00dev, COEX_CFG2); 5232 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); 5233 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); 5234 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); 5235 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); 5236 rt2800_register_write(rt2x00dev, COEX_CFG2, reg); 5237 5238 reg = rt2800_register_read(rt2x00dev, PLL_CTRL); 5239 rt2x00_set_field32(®, PLL_CONTROL, 1); 5240 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); 5241 } 5242 5243 if (rt2x00_rt(rt2x00dev, RT3071) || 5244 rt2x00_rt(rt2x00dev, RT3090) || 5245 rt2x00_rt(rt2x00dev, RT3290) || 5246 rt2x00_rt(rt2x00dev, RT3390)) { 5247 5248 if (rt2x00_rt(rt2x00dev, RT3290)) 5249 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5250 0x00000404); 5251 else 5252 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5253 0x00000400); 5254 5255 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5256 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 5257 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 5258 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 5259 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5260 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 5261 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5262 0x0000002c); 5263 else 5264 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5265 0x0000000f); 5266 } else { 5267 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5268 } 5269 } else if (rt2x00_rt(rt2x00dev, RT3070)) { 5270 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5271 5272 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 5273 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5274 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); 5275 } else { 5276 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5277 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5278 } 5279 } else if (rt2800_is_305x_soc(rt2x00dev)) { 5280 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5281 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5282 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); 5283 } else if (rt2x00_rt(rt2x00dev, RT3352)) { 5284 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5285 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5286 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5287 } else if (rt2x00_rt(rt2x00dev, RT3572)) { 5288 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5289 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5290 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 5291 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5292 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5293 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) { 5294 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5295 if (rt2x00_get_field16(eeprom, 5296 EEPROM_NIC_CONF1_DAC_TEST)) 5297 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5298 0x0000001f); 5299 else 5300 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5301 0x0000000f); 5302 } else { 5303 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5304 0x00000000); 5305 } 5306 } else if (rt2x00_rt(rt2x00dev, RT5390) || 5307 rt2x00_rt(rt2x00dev, RT5392) || 5308 rt2x00_rt(rt2x00dev, RT6352)) { 5309 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5310 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5311 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5312 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5313 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5314 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5315 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5316 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 5317 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5318 } else if (rt2x00_rt(rt2x00dev, RT6352)) { 5319 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401); 5320 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000); 5321 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5322 rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002); 5323 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F); 5324 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x06060606); 5325 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0); 5326 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0); 5327 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C); 5328 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C); 5329 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 5330 0x3630363A); 5331 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT, 5332 0x3630363A); 5333 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 5334 rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); 5335 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 5336 } else { 5337 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 5338 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5339 } 5340 5341 reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG); 5342 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); 5343 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); 5344 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); 5345 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); 5346 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); 5347 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); 5348 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); 5349 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); 5350 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); 5351 5352 reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG); 5353 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 5354 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); 5355 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 5356 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 5357 5358 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 5359 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 5360 if (rt2x00_is_usb(rt2x00dev)) { 5361 drv_data->max_psdu = 3; 5362 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || 5363 rt2x00_rt(rt2x00dev, RT2883) || 5364 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) { 5365 drv_data->max_psdu = 2; 5366 } else { 5367 drv_data->max_psdu = 1; 5368 } 5369 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu); 5370 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); 5371 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); 5372 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 5373 5374 reg = rt2800_register_read(rt2x00dev, LED_CFG); 5375 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); 5376 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); 5377 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); 5378 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); 5379 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); 5380 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); 5381 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); 5382 rt2800_register_write(rt2x00dev, LED_CFG, reg); 5383 5384 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 5385 5386 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 5387 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); 5388 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); 5389 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); 5390 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); 5391 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); 5392 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); 5393 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5394 5395 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 5396 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); 5397 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); 5398 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); 5399 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); 5400 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); 5401 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 5402 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 5403 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 5404 5405 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 5406 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); 5407 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); 5408 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); 5409 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 5410 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5411 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5412 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5413 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5414 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5415 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); 5416 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 5417 5418 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 5419 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); 5420 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); 5421 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); 5422 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 5423 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5424 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5425 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5426 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5427 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5428 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); 5429 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 5430 5431 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 5432 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 5433 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); 5434 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); 5435 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5436 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5437 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5438 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5439 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5440 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5441 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); 5442 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 5443 5444 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 5445 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 5446 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); 5447 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); 5448 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5449 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5450 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5451 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 5452 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5453 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 5454 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); 5455 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 5456 5457 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 5458 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 5459 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); 5460 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); 5461 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5462 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5463 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5464 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5465 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5466 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5467 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); 5468 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 5469 5470 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 5471 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 5472 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); 5473 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); 5474 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5475 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5476 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5477 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 5478 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5479 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 5480 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); 5481 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 5482 5483 if (rt2x00_is_usb(rt2x00dev)) { 5484 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); 5485 5486 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 5487 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 5488 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 5489 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 5490 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 5491 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); 5492 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); 5493 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); 5494 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); 5495 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); 5496 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 5497 } 5498 5499 /* 5500 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 5501 * although it is reserved. 5502 */ 5503 reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG); 5504 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); 5505 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); 5506 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); 5507 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); 5508 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); 5509 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); 5510 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); 5511 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); 5512 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); 5513 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); 5514 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); 5515 5516 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; 5517 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); 5518 5519 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 5520 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); 5521 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, 5522 IEEE80211_MAX_RTS_THRESHOLD); 5523 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1); 5524 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 5525 5526 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 5527 5528 /* 5529 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS 5530 * time should be set to 16. However, the original Ralink driver uses 5531 * 16 for both and indeed using a value of 10 for CCK SIFS results in 5532 * connection problems with 11g + CTS protection. Hence, use the same 5533 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. 5534 */ 5535 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 5536 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); 5537 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); 5538 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); 5539 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); 5540 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); 5541 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 5542 5543 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 5544 5545 /* 5546 * ASIC will keep garbage value after boot, clear encryption keys. 5547 */ 5548 for (i = 0; i < 4; i++) 5549 rt2800_register_write(rt2x00dev, 5550 SHARED_KEY_MODE_ENTRY(i), 0); 5551 5552 for (i = 0; i < 256; i++) { 5553 rt2800_config_wcid(rt2x00dev, NULL, i); 5554 rt2800_delete_wcid_attr(rt2x00dev, i); 5555 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 5556 } 5557 5558 /* 5559 * Clear all beacons 5560 */ 5561 for (i = 0; i < 8; i++) 5562 rt2800_clear_beacon_register(rt2x00dev, i); 5563 5564 if (rt2x00_is_usb(rt2x00dev)) { 5565 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 5566 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); 5567 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 5568 } else if (rt2x00_is_pcie(rt2x00dev)) { 5569 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 5570 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); 5571 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 5572 } 5573 5574 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0); 5575 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); 5576 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); 5577 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); 5578 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); 5579 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); 5580 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); 5581 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); 5582 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); 5583 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); 5584 5585 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1); 5586 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); 5587 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); 5588 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); 5589 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); 5590 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); 5591 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); 5592 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); 5593 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); 5594 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); 5595 5596 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0); 5597 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); 5598 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); 5599 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); 5600 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); 5601 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); 5602 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); 5603 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); 5604 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); 5605 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); 5606 5607 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1); 5608 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); 5609 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); 5610 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); 5611 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); 5612 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); 5613 5614 /* 5615 * Do not force the BA window size, we use the TXWI to set it 5616 */ 5617 reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE); 5618 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); 5619 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); 5620 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); 5621 5622 /* 5623 * We must clear the error counters. 5624 * These registers are cleared on read, 5625 * so we may pass a useless variable to store the value. 5626 */ 5627 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 5628 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1); 5629 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2); 5630 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0); 5631 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1); 5632 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2); 5633 5634 /* 5635 * Setup leadtime for pre tbtt interrupt to 6ms 5636 */ 5637 reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG); 5638 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); 5639 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); 5640 5641 /* 5642 * Set up channel statistics timer 5643 */ 5644 reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG); 5645 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); 5646 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); 5647 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); 5648 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); 5649 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); 5650 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); 5651 5652 return 0; 5653 } 5654 5655 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) 5656 { 5657 unsigned int i; 5658 u32 reg; 5659 5660 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 5661 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 5662 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) 5663 return 0; 5664 5665 udelay(REGISTER_BUSY_DELAY); 5666 } 5667 5668 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n"); 5669 return -EACCES; 5670 } 5671 5672 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 5673 { 5674 unsigned int i; 5675 u8 value; 5676 5677 /* 5678 * BBP was enabled after firmware was loaded, 5679 * but we need to reactivate it now. 5680 */ 5681 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 5682 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 5683 msleep(1); 5684 5685 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 5686 value = rt2800_bbp_read(rt2x00dev, 0); 5687 if ((value != 0xff) && (value != 0x00)) 5688 return 0; 5689 udelay(REGISTER_BUSY_DELAY); 5690 } 5691 5692 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 5693 return -EACCES; 5694 } 5695 5696 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev) 5697 { 5698 u8 value; 5699 5700 value = rt2800_bbp_read(rt2x00dev, 4); 5701 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); 5702 rt2800_bbp_write(rt2x00dev, 4, value); 5703 } 5704 5705 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev) 5706 { 5707 rt2800_bbp_write(rt2x00dev, 142, 1); 5708 rt2800_bbp_write(rt2x00dev, 143, 57); 5709 } 5710 5711 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev) 5712 { 5713 static const u8 glrt_table[] = { 5714 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */ 5715 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */ 5716 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */ 5717 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */ 5718 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */ 5719 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */ 5720 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */ 5721 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */ 5722 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */ 5723 }; 5724 int i; 5725 5726 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) { 5727 rt2800_bbp_write(rt2x00dev, 195, 128 + i); 5728 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]); 5729 } 5730 }; 5731 5732 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev) 5733 { 5734 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 5735 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5736 rt2800_bbp_write(rt2x00dev, 68, 0x0B); 5737 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5738 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5739 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5740 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5741 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5742 rt2800_bbp_write(rt2x00dev, 83, 0x6A); 5743 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5744 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5745 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5746 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5747 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5748 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5749 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5750 } 5751 5752 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev) 5753 { 5754 u16 eeprom; 5755 u8 value; 5756 5757 value = rt2800_bbp_read(rt2x00dev, 138); 5758 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 5759 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 5760 value |= 0x20; 5761 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 5762 value &= ~0x02; 5763 rt2800_bbp_write(rt2x00dev, 138, value); 5764 } 5765 5766 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev) 5767 { 5768 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5769 5770 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5771 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5772 5773 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5774 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5775 5776 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5777 5778 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 5779 rt2800_bbp_write(rt2x00dev, 80, 0x08); 5780 5781 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5782 5783 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5784 5785 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5786 5787 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5788 5789 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5790 5791 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5792 5793 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5794 5795 rt2800_bbp_write(rt2x00dev, 105, 0x01); 5796 5797 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5798 } 5799 5800 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev) 5801 { 5802 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5803 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5804 5805 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 5806 rt2800_bbp_write(rt2x00dev, 69, 0x16); 5807 rt2800_bbp_write(rt2x00dev, 73, 0x12); 5808 } else { 5809 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5810 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5811 } 5812 5813 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5814 5815 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5816 5817 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5818 5819 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5820 5821 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 5822 rt2800_bbp_write(rt2x00dev, 84, 0x19); 5823 else 5824 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5825 5826 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5827 5828 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5829 5830 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5831 5832 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5833 5834 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5835 5836 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5837 } 5838 5839 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev) 5840 { 5841 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5842 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5843 5844 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5845 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5846 5847 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5848 5849 rt2800_bbp_write(rt2x00dev, 79, 0x13); 5850 rt2800_bbp_write(rt2x00dev, 80, 0x05); 5851 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5852 5853 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5854 5855 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5856 5857 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5858 5859 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5860 5861 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5862 5863 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5864 5865 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 5866 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 5867 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E)) 5868 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5869 else 5870 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5871 5872 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5873 5874 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5875 5876 if (rt2x00_rt(rt2x00dev, RT3071) || 5877 rt2x00_rt(rt2x00dev, RT3090)) 5878 rt2800_disable_unused_dac_adc(rt2x00dev); 5879 } 5880 5881 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev) 5882 { 5883 u8 value; 5884 5885 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 5886 5887 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5888 5889 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5890 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5891 5892 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 5893 5894 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5895 rt2800_bbp_write(rt2x00dev, 73, 0x13); 5896 rt2800_bbp_write(rt2x00dev, 75, 0x46); 5897 rt2800_bbp_write(rt2x00dev, 76, 0x28); 5898 5899 rt2800_bbp_write(rt2x00dev, 77, 0x58); 5900 5901 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5902 5903 rt2800_bbp_write(rt2x00dev, 74, 0x0b); 5904 rt2800_bbp_write(rt2x00dev, 79, 0x18); 5905 rt2800_bbp_write(rt2x00dev, 80, 0x09); 5906 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5907 5908 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5909 5910 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 5911 5912 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 5913 5914 rt2800_bbp_write(rt2x00dev, 86, 0x38); 5915 5916 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5917 5918 rt2800_bbp_write(rt2x00dev, 92, 0x02); 5919 5920 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5921 5922 rt2800_bbp_write(rt2x00dev, 104, 0x92); 5923 5924 rt2800_bbp_write(rt2x00dev, 105, 0x1c); 5925 5926 rt2800_bbp_write(rt2x00dev, 106, 0x03); 5927 5928 rt2800_bbp_write(rt2x00dev, 128, 0x12); 5929 5930 rt2800_bbp_write(rt2x00dev, 67, 0x24); 5931 rt2800_bbp_write(rt2x00dev, 143, 0x04); 5932 rt2800_bbp_write(rt2x00dev, 142, 0x99); 5933 rt2800_bbp_write(rt2x00dev, 150, 0x30); 5934 rt2800_bbp_write(rt2x00dev, 151, 0x2e); 5935 rt2800_bbp_write(rt2x00dev, 152, 0x20); 5936 rt2800_bbp_write(rt2x00dev, 153, 0x34); 5937 rt2800_bbp_write(rt2x00dev, 154, 0x40); 5938 rt2800_bbp_write(rt2x00dev, 155, 0x3b); 5939 rt2800_bbp_write(rt2x00dev, 253, 0x04); 5940 5941 value = rt2800_bbp_read(rt2x00dev, 47); 5942 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1); 5943 rt2800_bbp_write(rt2x00dev, 47, value); 5944 5945 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */ 5946 value = rt2800_bbp_read(rt2x00dev, 3); 5947 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1); 5948 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1); 5949 rt2800_bbp_write(rt2x00dev, 3, value); 5950 } 5951 5952 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) 5953 { 5954 rt2800_bbp_write(rt2x00dev, 3, 0x00); 5955 rt2800_bbp_write(rt2x00dev, 4, 0x50); 5956 5957 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5958 5959 rt2800_bbp_write(rt2x00dev, 47, 0x48); 5960 5961 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5962 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5963 5964 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 5965 5966 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5967 rt2800_bbp_write(rt2x00dev, 73, 0x13); 5968 rt2800_bbp_write(rt2x00dev, 75, 0x46); 5969 rt2800_bbp_write(rt2x00dev, 76, 0x28); 5970 5971 rt2800_bbp_write(rt2x00dev, 77, 0x59); 5972 5973 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5974 5975 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 5976 rt2800_bbp_write(rt2x00dev, 80, 0x08); 5977 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5978 5979 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5980 5981 if (rt2x00_rt(rt2x00dev, RT5350)) { 5982 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 5983 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 5984 } else { 5985 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5986 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5987 } 5988 5989 rt2800_bbp_write(rt2x00dev, 86, 0x38); 5990 5991 rt2800_bbp_write(rt2x00dev, 88, 0x90); 5992 5993 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5994 5995 rt2800_bbp_write(rt2x00dev, 92, 0x02); 5996 5997 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5998 5999 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6000 6001 if (rt2x00_rt(rt2x00dev, RT5350)) { 6002 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6003 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6004 } else { 6005 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6006 rt2800_bbp_write(rt2x00dev, 106, 0x05); 6007 } 6008 6009 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6010 6011 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6012 6013 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 6014 /* Set ITxBF timeout to 0x9c40=1000msec */ 6015 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6016 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6017 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6018 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6019 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6020 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6021 /* Reprogram the inband interface to put right values in RXWI */ 6022 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6023 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6024 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6025 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6026 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6027 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6028 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6029 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6030 6031 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6032 6033 if (rt2x00_rt(rt2x00dev, RT5350)) { 6034 /* Antenna Software OFDM */ 6035 rt2800_bbp_write(rt2x00dev, 150, 0x40); 6036 /* Antenna Software CCK */ 6037 rt2800_bbp_write(rt2x00dev, 151, 0x30); 6038 rt2800_bbp_write(rt2x00dev, 152, 0xa3); 6039 /* Clear previously selected antenna */ 6040 rt2800_bbp_write(rt2x00dev, 154, 0); 6041 } 6042 } 6043 6044 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev) 6045 { 6046 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6047 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6048 6049 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6050 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6051 6052 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6053 6054 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6055 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6056 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6057 6058 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6059 6060 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6061 6062 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6063 6064 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6065 6066 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6067 6068 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6069 6070 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E)) 6071 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6072 else 6073 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6074 6075 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6076 6077 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6078 6079 rt2800_disable_unused_dac_adc(rt2x00dev); 6080 } 6081 6082 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev) 6083 { 6084 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6085 6086 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6087 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6088 6089 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6090 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6091 6092 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6093 6094 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6095 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6096 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6097 6098 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6099 6100 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6101 6102 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6103 6104 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6105 6106 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6107 6108 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6109 6110 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6111 6112 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6113 6114 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6115 6116 rt2800_disable_unused_dac_adc(rt2x00dev); 6117 } 6118 6119 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev) 6120 { 6121 rt2800_init_bbp_early(rt2x00dev); 6122 6123 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6124 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6125 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6126 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6127 6128 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6129 6130 /* Enable DC filter */ 6131 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E)) 6132 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6133 } 6134 6135 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) 6136 { 6137 int ant, div_mode; 6138 u16 eeprom; 6139 u8 value; 6140 6141 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6142 6143 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6144 6145 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6146 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6147 6148 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6149 6150 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6151 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6152 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6153 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6154 6155 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6156 6157 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6158 6159 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6160 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6161 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6162 6163 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6164 6165 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6166 6167 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6168 6169 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6170 6171 if (rt2x00_rt(rt2x00dev, RT5392)) 6172 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6173 6174 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6175 6176 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6177 6178 if (rt2x00_rt(rt2x00dev, RT5392)) { 6179 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6180 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6181 } 6182 6183 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6184 6185 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6186 6187 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6188 6189 if (rt2x00_rt(rt2x00dev, RT5390)) 6190 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6191 else if (rt2x00_rt(rt2x00dev, RT5392)) 6192 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6193 else 6194 WARN_ON(1); 6195 6196 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6197 6198 if (rt2x00_rt(rt2x00dev, RT5392)) { 6199 rt2800_bbp_write(rt2x00dev, 134, 0xd0); 6200 rt2800_bbp_write(rt2x00dev, 135, 0xf6); 6201 } 6202 6203 rt2800_disable_unused_dac_adc(rt2x00dev); 6204 6205 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6206 div_mode = rt2x00_get_field16(eeprom, 6207 EEPROM_NIC_CONF1_ANT_DIVERSITY); 6208 ant = (div_mode == 3) ? 1 : 0; 6209 6210 /* check if this is a Bluetooth combo card */ 6211 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 6212 u32 reg; 6213 6214 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 6215 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 6216 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); 6217 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); 6218 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); 6219 if (ant == 0) 6220 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); 6221 else if (ant == 1) 6222 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); 6223 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 6224 } 6225 6226 /* These chips have hardware RX antenna diversity */ 6227 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 6228 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 6229 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */ 6230 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */ 6231 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */ 6232 } 6233 6234 value = rt2800_bbp_read(rt2x00dev, 152); 6235 if (ant == 0) 6236 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6237 else 6238 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6239 rt2800_bbp_write(rt2x00dev, 152, value); 6240 6241 rt2800_init_freq_calibration(rt2x00dev); 6242 } 6243 6244 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) 6245 { 6246 int ant, div_mode; 6247 u16 eeprom; 6248 u8 value; 6249 6250 rt2800_init_bbp_early(rt2x00dev); 6251 6252 value = rt2800_bbp_read(rt2x00dev, 105); 6253 rt2x00_set_field8(&value, BBP105_MLD, 6254 rt2x00dev->default_ant.rx_chain_num == 2); 6255 rt2800_bbp_write(rt2x00dev, 105, value); 6256 6257 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6258 6259 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6260 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6261 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6262 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6263 rt2800_bbp_write(rt2x00dev, 69, 0x1A); 6264 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6265 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6266 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6267 rt2800_bbp_write(rt2x00dev, 75, 0x4F); 6268 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6269 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6270 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 6271 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6272 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6273 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6274 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6275 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6276 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6277 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 6278 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6279 /* FIXME BBP105 owerwrite */ 6280 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 6281 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6282 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6283 rt2800_bbp_write(rt2x00dev, 134, 0xD0); 6284 rt2800_bbp_write(rt2x00dev, 135, 0xF6); 6285 rt2800_bbp_write(rt2x00dev, 137, 0x0F); 6286 6287 /* Initialize GLRT (Generalized Likehood Radio Test) */ 6288 rt2800_init_bbp_5592_glrt(rt2x00dev); 6289 6290 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6291 6292 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6293 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); 6294 ant = (div_mode == 3) ? 1 : 0; 6295 value = rt2800_bbp_read(rt2x00dev, 152); 6296 if (ant == 0) { 6297 /* Main antenna */ 6298 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6299 } else { 6300 /* Auxiliary antenna */ 6301 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6302 } 6303 rt2800_bbp_write(rt2x00dev, 152, value); 6304 6305 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) { 6306 value = rt2800_bbp_read(rt2x00dev, 254); 6307 rt2x00_set_field8(&value, BBP254_BIT7, 1); 6308 rt2800_bbp_write(rt2x00dev, 254, value); 6309 } 6310 6311 rt2800_init_freq_calibration(rt2x00dev); 6312 6313 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6314 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 6315 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6316 } 6317 6318 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev, 6319 const u8 reg, const u8 value) 6320 { 6321 rt2800_bbp_write(rt2x00dev, 195, reg); 6322 rt2800_bbp_write(rt2x00dev, 196, value); 6323 } 6324 6325 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev, 6326 const u8 reg, const u8 value) 6327 { 6328 rt2800_bbp_write(rt2x00dev, 158, reg); 6329 rt2800_bbp_write(rt2x00dev, 159, value); 6330 } 6331 6332 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg) 6333 { 6334 rt2800_bbp_write(rt2x00dev, 158, reg); 6335 return rt2800_bbp_read(rt2x00dev, 159); 6336 } 6337 6338 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev) 6339 { 6340 u8 bbp; 6341 6342 /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */ 6343 bbp = rt2800_bbp_read(rt2x00dev, 105); 6344 rt2x00_set_field8(&bbp, BBP105_MLD, 6345 rt2x00dev->default_ant.rx_chain_num == 2); 6346 rt2800_bbp_write(rt2x00dev, 105, bbp); 6347 6348 /* Avoid data loss and CRC errors */ 6349 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6350 6351 /* Fix I/Q swap issue */ 6352 bbp = rt2800_bbp_read(rt2x00dev, 1); 6353 bbp |= 0x04; 6354 rt2800_bbp_write(rt2x00dev, 1, bbp); 6355 6356 /* BBP for G band */ 6357 rt2800_bbp_write(rt2x00dev, 3, 0x08); 6358 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */ 6359 rt2800_bbp_write(rt2x00dev, 6, 0x08); 6360 rt2800_bbp_write(rt2x00dev, 14, 0x09); 6361 rt2800_bbp_write(rt2x00dev, 15, 0xFF); 6362 rt2800_bbp_write(rt2x00dev, 16, 0x01); 6363 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6364 rt2800_bbp_write(rt2x00dev, 21, 0x00); 6365 rt2800_bbp_write(rt2x00dev, 22, 0x00); 6366 rt2800_bbp_write(rt2x00dev, 27, 0x00); 6367 rt2800_bbp_write(rt2x00dev, 28, 0x00); 6368 rt2800_bbp_write(rt2x00dev, 30, 0x00); 6369 rt2800_bbp_write(rt2x00dev, 31, 0x48); 6370 rt2800_bbp_write(rt2x00dev, 47, 0x40); 6371 rt2800_bbp_write(rt2x00dev, 62, 0x00); 6372 rt2800_bbp_write(rt2x00dev, 63, 0x00); 6373 rt2800_bbp_write(rt2x00dev, 64, 0x00); 6374 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6375 rt2800_bbp_write(rt2x00dev, 66, 0x1C); 6376 rt2800_bbp_write(rt2x00dev, 67, 0x20); 6377 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6378 rt2800_bbp_write(rt2x00dev, 69, 0x10); 6379 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6380 rt2800_bbp_write(rt2x00dev, 73, 0x18); 6381 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6382 rt2800_bbp_write(rt2x00dev, 75, 0x60); 6383 rt2800_bbp_write(rt2x00dev, 76, 0x44); 6384 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6385 rt2800_bbp_write(rt2x00dev, 78, 0x1E); 6386 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 6387 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 6388 rt2800_bbp_write(rt2x00dev, 81, 0x3A); 6389 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 6390 rt2800_bbp_write(rt2x00dev, 83, 0x9A); 6391 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 6392 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6393 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6394 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6395 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6396 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 6397 rt2800_bbp_write(rt2x00dev, 96, 0x00); 6398 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 6399 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6400 /* FIXME BBP105 owerwrite */ 6401 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 6402 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6403 rt2800_bbp_write(rt2x00dev, 109, 0x00); 6404 rt2800_bbp_write(rt2x00dev, 134, 0x10); 6405 rt2800_bbp_write(rt2x00dev, 135, 0xA6); 6406 rt2800_bbp_write(rt2x00dev, 137, 0x04); 6407 rt2800_bbp_write(rt2x00dev, 142, 0x30); 6408 rt2800_bbp_write(rt2x00dev, 143, 0xF7); 6409 rt2800_bbp_write(rt2x00dev, 160, 0xEC); 6410 rt2800_bbp_write(rt2x00dev, 161, 0xC4); 6411 rt2800_bbp_write(rt2x00dev, 162, 0x77); 6412 rt2800_bbp_write(rt2x00dev, 163, 0xF9); 6413 rt2800_bbp_write(rt2x00dev, 164, 0x00); 6414 rt2800_bbp_write(rt2x00dev, 165, 0x00); 6415 rt2800_bbp_write(rt2x00dev, 186, 0x00); 6416 rt2800_bbp_write(rt2x00dev, 187, 0x00); 6417 rt2800_bbp_write(rt2x00dev, 188, 0x00); 6418 rt2800_bbp_write(rt2x00dev, 186, 0x00); 6419 rt2800_bbp_write(rt2x00dev, 187, 0x01); 6420 rt2800_bbp_write(rt2x00dev, 188, 0x00); 6421 rt2800_bbp_write(rt2x00dev, 189, 0x00); 6422 6423 rt2800_bbp_write(rt2x00dev, 91, 0x06); 6424 rt2800_bbp_write(rt2x00dev, 92, 0x04); 6425 rt2800_bbp_write(rt2x00dev, 93, 0x54); 6426 rt2800_bbp_write(rt2x00dev, 99, 0x50); 6427 rt2800_bbp_write(rt2x00dev, 148, 0x84); 6428 rt2800_bbp_write(rt2x00dev, 167, 0x80); 6429 rt2800_bbp_write(rt2x00dev, 178, 0xFF); 6430 rt2800_bbp_write(rt2x00dev, 106, 0x13); 6431 6432 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */ 6433 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00); 6434 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14); 6435 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20); 6436 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A); 6437 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16); 6438 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06); 6439 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02); 6440 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07); 6441 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05); 6442 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09); 6443 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20); 6444 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08); 6445 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A); 6446 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00); 6447 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00); 6448 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0); 6449 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F); 6450 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F); 6451 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32); 6452 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08); 6453 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28); 6454 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19); 6455 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A); 6456 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16); 6457 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10); 6458 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10); 6459 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A); 6460 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36); 6461 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C); 6462 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26); 6463 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24); 6464 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42); 6465 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40); 6466 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30); 6467 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29); 6468 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C); 6469 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46); 6470 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D); 6471 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40); 6472 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E); 6473 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38); 6474 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D); 6475 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F); 6476 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C); 6477 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34); 6478 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C); 6479 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F); 6480 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C); 6481 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35); 6482 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E); 6483 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F); 6484 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49); 6485 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41); 6486 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36); 6487 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39); 6488 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30); 6489 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30); 6490 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E); 6491 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D); 6492 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28); 6493 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21); 6494 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C); 6495 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16); 6496 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50); 6497 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A); 6498 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43); 6499 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50); 6500 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10); 6501 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10); 6502 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10); 6503 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10); 6504 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D); 6505 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14); 6506 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32); 6507 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C); 6508 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36); 6509 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C); 6510 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43); 6511 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C); 6512 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E); 6513 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36); 6514 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30); 6515 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E); 6516 6517 /* BBP for G band DCOC function */ 6518 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C); 6519 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00); 6520 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10); 6521 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10); 6522 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10); 6523 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10); 6524 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08); 6525 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40); 6526 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04); 6527 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04); 6528 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08); 6529 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08); 6530 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03); 6531 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03); 6532 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03); 6533 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02); 6534 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40); 6535 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40); 6536 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64); 6537 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64); 6538 6539 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6540 } 6541 6542 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) 6543 { 6544 unsigned int i; 6545 u16 eeprom; 6546 u8 reg_id; 6547 u8 value; 6548 6549 if (rt2800_is_305x_soc(rt2x00dev)) 6550 rt2800_init_bbp_305x_soc(rt2x00dev); 6551 6552 switch (rt2x00dev->chip.rt) { 6553 case RT2860: 6554 case RT2872: 6555 case RT2883: 6556 rt2800_init_bbp_28xx(rt2x00dev); 6557 break; 6558 case RT3070: 6559 case RT3071: 6560 case RT3090: 6561 rt2800_init_bbp_30xx(rt2x00dev); 6562 break; 6563 case RT3290: 6564 rt2800_init_bbp_3290(rt2x00dev); 6565 break; 6566 case RT3352: 6567 case RT5350: 6568 rt2800_init_bbp_3352(rt2x00dev); 6569 break; 6570 case RT3390: 6571 rt2800_init_bbp_3390(rt2x00dev); 6572 break; 6573 case RT3572: 6574 rt2800_init_bbp_3572(rt2x00dev); 6575 break; 6576 case RT3593: 6577 rt2800_init_bbp_3593(rt2x00dev); 6578 return; 6579 case RT5390: 6580 case RT5392: 6581 rt2800_init_bbp_53xx(rt2x00dev); 6582 break; 6583 case RT5592: 6584 rt2800_init_bbp_5592(rt2x00dev); 6585 return; 6586 case RT6352: 6587 rt2800_init_bbp_6352(rt2x00dev); 6588 break; 6589 } 6590 6591 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 6592 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 6593 EEPROM_BBP_START, i); 6594 6595 if (eeprom != 0xffff && eeprom != 0x0000) { 6596 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 6597 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 6598 rt2800_bbp_write(rt2x00dev, reg_id, value); 6599 } 6600 } 6601 } 6602 6603 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev) 6604 { 6605 u32 reg; 6606 6607 reg = rt2800_register_read(rt2x00dev, OPT_14_CSR); 6608 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); 6609 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 6610 } 6611 6612 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, 6613 u8 filter_target) 6614 { 6615 unsigned int i; 6616 u8 bbp; 6617 u8 rfcsr; 6618 u8 passband; 6619 u8 stopband; 6620 u8 overtuned = 0; 6621 u8 rfcsr24 = (bw40) ? 0x27 : 0x07; 6622 6623 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 6624 6625 bbp = rt2800_bbp_read(rt2x00dev, 4); 6626 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); 6627 rt2800_bbp_write(rt2x00dev, 4, bbp); 6628 6629 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 6630 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); 6631 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 6632 6633 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 6634 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); 6635 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 6636 6637 /* 6638 * Set power & frequency of passband test tone 6639 */ 6640 rt2800_bbp_write(rt2x00dev, 24, 0); 6641 6642 for (i = 0; i < 100; i++) { 6643 rt2800_bbp_write(rt2x00dev, 25, 0x90); 6644 msleep(1); 6645 6646 passband = rt2800_bbp_read(rt2x00dev, 55); 6647 if (passband) 6648 break; 6649 } 6650 6651 /* 6652 * Set power & frequency of stopband test tone 6653 */ 6654 rt2800_bbp_write(rt2x00dev, 24, 0x06); 6655 6656 for (i = 0; i < 100; i++) { 6657 rt2800_bbp_write(rt2x00dev, 25, 0x90); 6658 msleep(1); 6659 6660 stopband = rt2800_bbp_read(rt2x00dev, 55); 6661 6662 if ((passband - stopband) <= filter_target) { 6663 rfcsr24++; 6664 overtuned += ((passband - stopband) == filter_target); 6665 } else 6666 break; 6667 6668 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 6669 } 6670 6671 rfcsr24 -= !!overtuned; 6672 6673 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 6674 return rfcsr24; 6675 } 6676 6677 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev, 6678 const unsigned int rf_reg) 6679 { 6680 u8 rfcsr; 6681 6682 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg); 6683 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1); 6684 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 6685 msleep(1); 6686 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0); 6687 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 6688 } 6689 6690 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev) 6691 { 6692 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 6693 u8 filter_tgt_bw20; 6694 u8 filter_tgt_bw40; 6695 u8 rfcsr, bbp; 6696 6697 /* 6698 * TODO: sync filter_tgt values with vendor driver 6699 */ 6700 if (rt2x00_rt(rt2x00dev, RT3070)) { 6701 filter_tgt_bw20 = 0x16; 6702 filter_tgt_bw40 = 0x19; 6703 } else { 6704 filter_tgt_bw20 = 0x13; 6705 filter_tgt_bw40 = 0x15; 6706 } 6707 6708 drv_data->calibration_bw20 = 6709 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20); 6710 drv_data->calibration_bw40 = 6711 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40); 6712 6713 /* 6714 * Save BBP 25 & 26 values for later use in channel switching (for 3052) 6715 */ 6716 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 6717 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 6718 6719 /* 6720 * Set back to initial state 6721 */ 6722 rt2800_bbp_write(rt2x00dev, 24, 0); 6723 6724 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 6725 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 6726 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 6727 6728 /* 6729 * Set BBP back to BW20 6730 */ 6731 bbp = rt2800_bbp_read(rt2x00dev, 4); 6732 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 6733 rt2800_bbp_write(rt2x00dev, 4, bbp); 6734 } 6735 6736 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) 6737 { 6738 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 6739 u8 min_gain, rfcsr, bbp; 6740 u16 eeprom; 6741 6742 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 6743 6744 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 6745 if (rt2x00_rt(rt2x00dev, RT3070) || 6746 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 6747 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 6748 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 6749 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev)) 6750 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 6751 } 6752 6753 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2; 6754 if (drv_data->txmixer_gain_24g >= min_gain) { 6755 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 6756 drv_data->txmixer_gain_24g); 6757 } 6758 6759 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 6760 6761 if (rt2x00_rt(rt2x00dev, RT3090)) { 6762 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 6763 bbp = rt2800_bbp_read(rt2x00dev, 138); 6764 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 6765 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 6766 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); 6767 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 6768 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); 6769 rt2800_bbp_write(rt2x00dev, 138, bbp); 6770 } 6771 6772 if (rt2x00_rt(rt2x00dev, RT3070)) { 6773 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27); 6774 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) 6775 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); 6776 else 6777 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); 6778 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); 6779 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); 6780 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); 6781 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 6782 } else if (rt2x00_rt(rt2x00dev, RT3071) || 6783 rt2x00_rt(rt2x00dev, RT3090) || 6784 rt2x00_rt(rt2x00dev, RT3390)) { 6785 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 6786 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 6787 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 6788 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 6789 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 6790 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 6791 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 6792 6793 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15); 6794 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); 6795 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); 6796 6797 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 6798 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); 6799 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 6800 6801 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 6802 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); 6803 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 6804 } 6805 } 6806 6807 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev) 6808 { 6809 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 6810 u8 rfcsr; 6811 u8 tx_gain; 6812 6813 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 6814 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0); 6815 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 6816 6817 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 6818 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g, 6819 RFCSR17_TXMIXER_GAIN); 6820 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain); 6821 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 6822 6823 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38); 6824 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); 6825 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); 6826 6827 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39); 6828 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); 6829 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 6830 6831 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 6832 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 6833 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 6834 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 6835 6836 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 6837 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 6838 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 6839 6840 /* TODO: enable stream mode */ 6841 } 6842 6843 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev) 6844 { 6845 u8 reg; 6846 u16 eeprom; 6847 6848 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 6849 reg = rt2800_bbp_read(rt2x00dev, 138); 6850 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 6851 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 6852 rt2x00_set_field8(®, BBP138_RX_ADC1, 0); 6853 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 6854 rt2x00_set_field8(®, BBP138_TX_DAC1, 1); 6855 rt2800_bbp_write(rt2x00dev, 138, reg); 6856 6857 reg = rt2800_rfcsr_read(rt2x00dev, 38); 6858 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); 6859 rt2800_rfcsr_write(rt2x00dev, 38, reg); 6860 6861 reg = rt2800_rfcsr_read(rt2x00dev, 39); 6862 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); 6863 rt2800_rfcsr_write(rt2x00dev, 39, reg); 6864 6865 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6866 6867 reg = rt2800_rfcsr_read(rt2x00dev, 30); 6868 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); 6869 rt2800_rfcsr_write(rt2x00dev, 30, reg); 6870 } 6871 6872 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev) 6873 { 6874 rt2800_rf_init_calibration(rt2x00dev, 30); 6875 6876 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 6877 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 6878 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 6879 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 6880 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 6881 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 6882 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 6883 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 6884 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 6885 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 6886 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 6887 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 6888 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 6889 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 6890 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 6891 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 6892 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 6893 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 6894 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 6895 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 6896 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 6897 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 6898 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 6899 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 6900 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 6901 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 6902 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 6903 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 6904 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 6905 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 6906 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 6907 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 6908 } 6909 6910 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) 6911 { 6912 u8 rfcsr; 6913 u16 eeprom; 6914 u32 reg; 6915 6916 /* XXX vendor driver do this only for 3070 */ 6917 rt2800_rf_init_calibration(rt2x00dev, 30); 6918 6919 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 6920 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 6921 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 6922 rt2800_rfcsr_write(rt2x00dev, 7, 0x60); 6923 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 6924 rt2800_rfcsr_write(rt2x00dev, 10, 0x41); 6925 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 6926 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 6927 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 6928 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 6929 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 6930 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 6931 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 6932 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 6933 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 6934 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 6935 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 6936 rt2800_rfcsr_write(rt2x00dev, 25, 0x03); 6937 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 6938 6939 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 6940 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 6941 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 6942 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 6943 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6944 } else if (rt2x00_rt(rt2x00dev, RT3071) || 6945 rt2x00_rt(rt2x00dev, RT3090)) { 6946 rt2800_rfcsr_write(rt2x00dev, 31, 0x14); 6947 6948 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 6949 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 6950 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 6951 6952 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 6953 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 6954 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 6955 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { 6956 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6957 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 6958 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 6959 else 6960 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 6961 } 6962 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6963 6964 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 6965 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 6966 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 6967 } 6968 6969 rt2800_rx_filter_calibration(rt2x00dev); 6970 6971 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 6972 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 6973 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) 6974 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 6975 6976 rt2800_led_open_drain_enable(rt2x00dev); 6977 rt2800_normal_mode_setup_3xxx(rt2x00dev); 6978 } 6979 6980 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) 6981 { 6982 u8 rfcsr; 6983 6984 rt2800_rf_init_calibration(rt2x00dev, 2); 6985 6986 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 6987 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 6988 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 6989 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 6990 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 6991 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3); 6992 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 6993 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 6994 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 6995 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 6996 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 6997 rt2800_rfcsr_write(rt2x00dev, 18, 0x02); 6998 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 6999 rt2800_rfcsr_write(rt2x00dev, 25, 0x83); 7000 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7001 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7002 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7003 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7004 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7005 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7006 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7007 rt2800_rfcsr_write(rt2x00dev, 34, 0x05); 7008 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7009 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7010 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7011 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7012 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7013 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7014 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7015 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b); 7016 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7017 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7018 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7019 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7020 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7021 rt2800_rfcsr_write(rt2x00dev, 49, 0x98); 7022 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7023 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7024 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 7025 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7026 rt2800_rfcsr_write(rt2x00dev, 56, 0x02); 7027 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 7028 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 7029 rt2800_rfcsr_write(rt2x00dev, 59, 0x09); 7030 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7031 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); 7032 7033 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29); 7034 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3); 7035 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr); 7036 7037 rt2800_led_open_drain_enable(rt2x00dev); 7038 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7039 } 7040 7041 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) 7042 { 7043 int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0, 7044 &rt2x00dev->cap_flags); 7045 int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1, 7046 &rt2x00dev->cap_flags); 7047 u8 rfcsr; 7048 7049 rt2800_rf_init_calibration(rt2x00dev, 30); 7050 7051 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7052 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7053 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7054 rt2800_rfcsr_write(rt2x00dev, 3, 0x18); 7055 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7056 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7057 rt2800_rfcsr_write(rt2x00dev, 6, 0x33); 7058 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7059 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7060 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7061 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2); 7062 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 7063 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 7064 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 7065 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a); 7066 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7067 rt2800_rfcsr_write(rt2x00dev, 16, 0x01); 7068 rt2800_rfcsr_write(rt2x00dev, 18, 0x45); 7069 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7070 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7071 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7072 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7073 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7074 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7075 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7076 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7077 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7078 rt2800_rfcsr_write(rt2x00dev, 28, 0x03); 7079 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 7080 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7081 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7082 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7083 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7084 rfcsr = 0x01; 7085 if (tx0_ext_pa) 7086 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1); 7087 if (tx1_ext_pa) 7088 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1); 7089 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 7090 rt2800_rfcsr_write(rt2x00dev, 35, 0x03); 7091 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); 7092 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); 7093 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); 7094 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); 7095 rt2800_rfcsr_write(rt2x00dev, 40, 0x33); 7096 rfcsr = 0x52; 7097 if (!tx0_ext_pa) { 7098 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1); 7099 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1); 7100 } 7101 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr); 7102 rfcsr = 0x52; 7103 if (!tx1_ext_pa) { 7104 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1); 7105 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1); 7106 } 7107 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 7108 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); 7109 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); 7110 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); 7111 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd); 7112 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); 7113 rt2800_rfcsr_write(rt2x00dev, 48, 0x14); 7114 rt2800_rfcsr_write(rt2x00dev, 49, 0x00); 7115 rfcsr = 0x2d; 7116 if (tx0_ext_pa) 7117 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1); 7118 if (tx1_ext_pa) 7119 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1); 7120 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7121 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f)); 7122 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00)); 7123 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52)); 7124 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b)); 7125 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f)); 7126 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00)); 7127 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52)); 7128 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b)); 7129 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 7130 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 7131 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 7132 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7133 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7134 7135 rt2800_rx_filter_calibration(rt2x00dev); 7136 rt2800_led_open_drain_enable(rt2x00dev); 7137 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7138 } 7139 7140 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) 7141 { 7142 u32 reg; 7143 7144 rt2800_rf_init_calibration(rt2x00dev, 30); 7145 7146 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 7147 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 7148 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7149 rt2800_rfcsr_write(rt2x00dev, 3, 0x62); 7150 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7151 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); 7152 rt2800_rfcsr_write(rt2x00dev, 6, 0x42); 7153 rt2800_rfcsr_write(rt2x00dev, 7, 0x34); 7154 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 7155 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 7156 rt2800_rfcsr_write(rt2x00dev, 10, 0x61); 7157 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7158 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); 7159 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); 7160 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7161 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7162 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); 7163 rt2800_rfcsr_write(rt2x00dev, 17, 0x94); 7164 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); 7165 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); 7166 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); 7167 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); 7168 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7169 rt2800_rfcsr_write(rt2x00dev, 23, 0x14); 7170 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7171 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 7172 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7173 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7174 rt2800_rfcsr_write(rt2x00dev, 28, 0x41); 7175 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); 7176 rt2800_rfcsr_write(rt2x00dev, 30, 0x20); 7177 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); 7178 7179 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7180 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7181 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7182 7183 rt2800_rx_filter_calibration(rt2x00dev); 7184 7185 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) 7186 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7187 7188 rt2800_led_open_drain_enable(rt2x00dev); 7189 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7190 } 7191 7192 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) 7193 { 7194 u8 rfcsr; 7195 u32 reg; 7196 7197 rt2800_rf_init_calibration(rt2x00dev, 30); 7198 7199 rt2800_rfcsr_write(rt2x00dev, 0, 0x70); 7200 rt2800_rfcsr_write(rt2x00dev, 1, 0x81); 7201 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7202 rt2800_rfcsr_write(rt2x00dev, 3, 0x02); 7203 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); 7204 rt2800_rfcsr_write(rt2x00dev, 5, 0x05); 7205 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); 7206 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 7207 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 7208 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 7209 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 7210 rt2800_rfcsr_write(rt2x00dev, 12, 0x70); 7211 rt2800_rfcsr_write(rt2x00dev, 13, 0x65); 7212 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); 7213 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7214 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); 7215 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 7216 rt2800_rfcsr_write(rt2x00dev, 18, 0xac); 7217 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 7218 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 7219 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); 7220 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7221 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); 7222 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7223 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 7224 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7225 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7226 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7227 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 7228 rt2800_rfcsr_write(rt2x00dev, 30, 0x09); 7229 rt2800_rfcsr_write(rt2x00dev, 31, 0x10); 7230 7231 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7232 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7233 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7234 7235 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7236 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7237 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7238 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7239 msleep(1); 7240 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7241 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7242 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7243 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7244 7245 rt2800_rx_filter_calibration(rt2x00dev); 7246 rt2800_led_open_drain_enable(rt2x00dev); 7247 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7248 } 7249 7250 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev) 7251 { 7252 u8 bbp; 7253 bool txbf_enabled = false; /* FIXME */ 7254 7255 bbp = rt2800_bbp_read(rt2x00dev, 105); 7256 if (rt2x00dev->default_ant.rx_chain_num == 1) 7257 rt2x00_set_field8(&bbp, BBP105_MLD, 0); 7258 else 7259 rt2x00_set_field8(&bbp, BBP105_MLD, 1); 7260 rt2800_bbp_write(rt2x00dev, 105, bbp); 7261 7262 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7263 7264 rt2800_bbp_write(rt2x00dev, 92, 0x02); 7265 rt2800_bbp_write(rt2x00dev, 82, 0x82); 7266 rt2800_bbp_write(rt2x00dev, 106, 0x05); 7267 rt2800_bbp_write(rt2x00dev, 104, 0x92); 7268 rt2800_bbp_write(rt2x00dev, 88, 0x90); 7269 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 7270 rt2800_bbp_write(rt2x00dev, 47, 0x48); 7271 rt2800_bbp_write(rt2x00dev, 120, 0x50); 7272 7273 if (txbf_enabled) 7274 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 7275 else 7276 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 7277 7278 /* SNR mapping */ 7279 rt2800_bbp_write(rt2x00dev, 142, 6); 7280 rt2800_bbp_write(rt2x00dev, 143, 160); 7281 rt2800_bbp_write(rt2x00dev, 142, 7); 7282 rt2800_bbp_write(rt2x00dev, 143, 161); 7283 rt2800_bbp_write(rt2x00dev, 142, 8); 7284 rt2800_bbp_write(rt2x00dev, 143, 162); 7285 7286 /* ADC/DAC control */ 7287 rt2800_bbp_write(rt2x00dev, 31, 0x08); 7288 7289 /* RX AGC energy lower bound in log2 */ 7290 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 7291 7292 /* FIXME: BBP 105 owerwrite? */ 7293 rt2800_bbp_write(rt2x00dev, 105, 0x04); 7294 7295 } 7296 7297 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) 7298 { 7299 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7300 u32 reg; 7301 u8 rfcsr; 7302 7303 /* Disable GPIO #4 and #7 function for LAN PE control */ 7304 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7305 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); 7306 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); 7307 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7308 7309 /* Initialize default register values */ 7310 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 7311 rt2800_rfcsr_write(rt2x00dev, 3, 0x80); 7312 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7313 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 7314 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7315 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7316 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 7317 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 7318 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e); 7319 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 7320 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 7321 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7322 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7323 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7324 rt2800_rfcsr_write(rt2x00dev, 32, 0x78); 7325 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b); 7326 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 7327 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0); 7328 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 7329 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 7330 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3); 7331 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 7332 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 7333 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 7334 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 7335 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 7336 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 7337 rt2800_rfcsr_write(rt2x00dev, 53, 0x18); 7338 rt2800_rfcsr_write(rt2x00dev, 54, 0x18); 7339 rt2800_rfcsr_write(rt2x00dev, 55, 0x18); 7340 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 7341 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 7342 7343 /* Initiate calibration */ 7344 /* TODO: use rt2800_rf_init_calibration ? */ 7345 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 7346 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 7347 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 7348 7349 rt2800_freq_cal_mode1(rt2x00dev); 7350 7351 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 7352 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1); 7353 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 7354 7355 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7356 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7357 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7358 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7359 usleep_range(1000, 1500); 7360 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7361 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7362 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7363 7364 /* Set initial values for RX filter calibration */ 7365 drv_data->calibration_bw20 = 0x1f; 7366 drv_data->calibration_bw40 = 0x2f; 7367 7368 /* Save BBP 25 & 26 values for later use in channel switching */ 7369 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 7370 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 7371 7372 rt2800_led_open_drain_enable(rt2x00dev); 7373 rt2800_normal_mode_setup_3593(rt2x00dev); 7374 7375 rt3593_post_bbp_init(rt2x00dev); 7376 7377 /* TODO: enable stream mode support */ 7378 } 7379 7380 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev) 7381 { 7382 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7383 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7384 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7385 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7386 rt2800_rfcsr_write(rt2x00dev, 4, 0x49); 7387 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7388 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 7389 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7390 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7391 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7392 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7393 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7394 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7395 if (rt2800_clk_is_20mhz(rt2x00dev)) 7396 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f); 7397 else 7398 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7399 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7400 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7401 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0); 7402 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7403 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 7404 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7405 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7406 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7407 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7408 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7409 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7410 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7411 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7412 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7413 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0); 7414 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7415 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7416 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7417 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7418 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 7419 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7420 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7421 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 7422 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7423 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7424 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7425 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7426 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7427 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 7428 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c); 7429 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6); 7430 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7431 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7432 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7433 rt2800_rfcsr_write(rt2x00dev, 49, 0x80); 7434 rt2800_rfcsr_write(rt2x00dev, 50, 0x00); 7435 rt2800_rfcsr_write(rt2x00dev, 51, 0x00); 7436 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7437 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7438 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 7439 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7440 rt2800_rfcsr_write(rt2x00dev, 56, 0x82); 7441 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 7442 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 7443 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b); 7444 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7445 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 7446 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7447 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7448 } 7449 7450 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) 7451 { 7452 rt2800_rf_init_calibration(rt2x00dev, 2); 7453 7454 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 7455 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7456 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 7457 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7458 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7459 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 7460 else 7461 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 7462 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7463 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7464 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7465 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7466 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7467 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7468 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7469 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 7470 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7471 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 7472 7473 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7474 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7475 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7476 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7477 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7478 if (rt2x00_is_usb(rt2x00dev) && 7479 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7480 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7481 else 7482 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); 7483 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7484 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7485 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7486 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7487 7488 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7489 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7490 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7491 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7492 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 7493 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7494 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7495 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 7496 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7497 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7498 7499 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7500 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7501 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); 7502 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); 7503 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7504 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7505 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7506 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7507 else 7508 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); 7509 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7510 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7511 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 7512 7513 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7514 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7515 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7516 else 7517 rt2800_rfcsr_write(rt2x00dev, 53, 0x84); 7518 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 7519 rt2800_rfcsr_write(rt2x00dev, 55, 0x44); 7520 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7521 rt2800_rfcsr_write(rt2x00dev, 56, 0x42); 7522 else 7523 rt2800_rfcsr_write(rt2x00dev, 56, 0x22); 7524 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 7525 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 7526 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f); 7527 7528 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7529 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 7530 if (rt2x00_is_usb(rt2x00dev)) 7531 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 7532 else 7533 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5); 7534 } else { 7535 if (rt2x00_is_usb(rt2x00dev)) 7536 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); 7537 else 7538 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5); 7539 } 7540 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7541 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7542 7543 rt2800_normal_mode_setup_5xxx(rt2x00dev); 7544 7545 rt2800_led_open_drain_enable(rt2x00dev); 7546 } 7547 7548 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) 7549 { 7550 rt2800_rf_init_calibration(rt2x00dev, 2); 7551 7552 rt2800_rfcsr_write(rt2x00dev, 1, 0x17); 7553 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 7554 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7555 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 7556 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7557 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7558 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7559 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7560 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7561 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7562 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7563 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 7564 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7565 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d); 7566 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7567 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d); 7568 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7569 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b); 7570 rt2800_rfcsr_write(rt2x00dev, 24, 0x44); 7571 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7572 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7573 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7574 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7575 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7576 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7577 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7578 rt2800_rfcsr_write(rt2x00dev, 32, 0x20); 7579 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 7580 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 7581 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7582 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7583 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 7584 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 7585 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7586 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f); 7587 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7588 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7589 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 7590 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7591 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7592 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7593 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c); 7594 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7595 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 7596 rt2800_rfcsr_write(rt2x00dev, 50, 0x94); 7597 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a); 7598 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 7599 rt2800_rfcsr_write(rt2x00dev, 53, 0x44); 7600 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 7601 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7602 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1); 7603 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 7604 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 7605 rt2800_rfcsr_write(rt2x00dev, 59, 0x07); 7606 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7607 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 7608 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 7609 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 7610 7611 rt2800_normal_mode_setup_5xxx(rt2x00dev); 7612 7613 rt2800_led_open_drain_enable(rt2x00dev); 7614 } 7615 7616 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev) 7617 { 7618 rt2800_rf_init_calibration(rt2x00dev, 30); 7619 7620 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F); 7621 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7622 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7623 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4); 7624 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7625 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7626 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7627 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 7628 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7629 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D); 7630 rt2800_rfcsr_write(rt2x00dev, 20, 0x10); 7631 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D); 7632 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7633 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7634 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7635 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 7636 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 7637 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7638 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C); 7639 rt2800_rfcsr_write(rt2x00dev, 53, 0x22); 7640 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 7641 7642 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7643 msleep(1); 7644 7645 rt2800_freq_cal_mode1(rt2x00dev); 7646 7647 /* Enable DC filter */ 7648 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 7649 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 7650 7651 rt2800_normal_mode_setup_5xxx(rt2x00dev); 7652 7653 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C)) 7654 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7655 7656 rt2800_led_open_drain_enable(rt2x00dev); 7657 } 7658 7659 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev, 7660 bool set_bw, bool is_ht40) 7661 { 7662 u8 bbp_val; 7663 7664 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 7665 bbp_val |= 0x1; 7666 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 7667 usleep_range(100, 200); 7668 7669 if (set_bw) { 7670 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 7671 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40); 7672 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 7673 usleep_range(100, 200); 7674 } 7675 7676 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 7677 bbp_val &= (~0x1); 7678 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 7679 usleep_range(100, 200); 7680 } 7681 7682 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal) 7683 { 7684 u8 rf_val; 7685 7686 if (btxcal) 7687 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 7688 else 7689 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02); 7690 7691 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06); 7692 7693 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 7694 rf_val |= 0x80; 7695 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val); 7696 7697 if (btxcal) { 7698 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1); 7699 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20); 7700 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 7701 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 7702 rf_val &= (~0x3F); 7703 rf_val |= 0x3F; 7704 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 7705 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 7706 rf_val &= (~0x3F); 7707 rf_val |= 0x3F; 7708 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 7709 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31); 7710 } else { 7711 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1); 7712 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18); 7713 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 7714 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 7715 rf_val &= (~0x3F); 7716 rf_val |= 0x34; 7717 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 7718 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 7719 rf_val &= (~0x3F); 7720 rf_val |= 0x34; 7721 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 7722 } 7723 7724 return 0; 7725 } 7726 7727 static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev) 7728 { 7729 unsigned int cnt; 7730 u8 bbp_val; 7731 char cal_val; 7732 7733 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82); 7734 7735 cnt = 0; 7736 do { 7737 usleep_range(500, 2000); 7738 bbp_val = rt2800_bbp_read(rt2x00dev, 159); 7739 if (bbp_val == 0x02 || cnt == 20) 7740 break; 7741 7742 cnt++; 7743 } while (cnt < 20); 7744 7745 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39); 7746 cal_val = bbp_val & 0x7F; 7747 if (cal_val >= 0x40) 7748 cal_val -= 128; 7749 7750 return cal_val; 7751 } 7752 7753 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev, 7754 bool btxcal) 7755 { 7756 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7757 u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc; 7758 u8 filter_target; 7759 u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02; 7760 u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31; 7761 int loop = 0, is_ht40, cnt; 7762 u8 bbp_val, rf_val; 7763 char cal_r32_init, cal_r32_val, cal_diff; 7764 u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05; 7765 u8 saverfb5r06, saverfb5r07; 7766 u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20; 7767 u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41; 7768 u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46; 7769 u8 saverfb5r58, saverfb5r59; 7770 u8 savebbp159r0, savebbp159r2, savebbpr23; 7771 u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0; 7772 7773 /* Save MAC registers */ 7774 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 7775 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 7776 7777 /* save BBP registers */ 7778 savebbpr23 = rt2800_bbp_read(rt2x00dev, 23); 7779 7780 savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0); 7781 savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2); 7782 7783 /* Save RF registers */ 7784 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 7785 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 7786 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 7787 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 7788 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5); 7789 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 7790 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 7791 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 7792 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 7793 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 7794 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 7795 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 7796 7797 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37); 7798 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38); 7799 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39); 7800 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40); 7801 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41); 7802 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42); 7803 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43); 7804 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44); 7805 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45); 7806 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46); 7807 7808 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 7809 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 7810 7811 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 7812 rf_val |= 0x3; 7813 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 7814 7815 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 7816 rf_val |= 0x1; 7817 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val); 7818 7819 cnt = 0; 7820 do { 7821 usleep_range(500, 2000); 7822 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 7823 if (((rf_val & 0x1) == 0x00) || (cnt == 40)) 7824 break; 7825 cnt++; 7826 } while (cnt < 40); 7827 7828 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 7829 rf_val &= (~0x3); 7830 rf_val |= 0x1; 7831 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 7832 7833 /* I-3 */ 7834 bbp_val = rt2800_bbp_read(rt2x00dev, 23); 7835 bbp_val &= (~0x1F); 7836 bbp_val |= 0x10; 7837 rt2800_bbp_write(rt2x00dev, 23, bbp_val); 7838 7839 do { 7840 /* I-4,5,6,7,8,9 */ 7841 if (loop == 0) { 7842 is_ht40 = false; 7843 7844 if (btxcal) 7845 filter_target = tx_filter_target_20m; 7846 else 7847 filter_target = rx_filter_target_20m; 7848 } else { 7849 is_ht40 = true; 7850 7851 if (btxcal) 7852 filter_target = tx_filter_target_40m; 7853 else 7854 filter_target = rx_filter_target_40m; 7855 } 7856 7857 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 7858 rf_val &= (~0x04); 7859 if (loop == 1) 7860 rf_val |= 0x4; 7861 7862 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val); 7863 7864 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40); 7865 7866 rt2800_rf_lp_config(rt2x00dev, btxcal); 7867 if (btxcal) { 7868 tx_agc_fc = 0; 7869 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 7870 rf_val &= (~0x7F); 7871 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 7872 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 7873 rf_val &= (~0x7F); 7874 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 7875 } else { 7876 rx_agc_fc = 0; 7877 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 7878 rf_val &= (~0x7F); 7879 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 7880 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 7881 rf_val &= (~0x7F); 7882 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 7883 } 7884 7885 usleep_range(1000, 2000); 7886 7887 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 7888 bbp_val &= (~0x6); 7889 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 7890 7891 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 7892 7893 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 7894 7895 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 7896 bbp_val |= 0x6; 7897 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 7898 do_cal: 7899 if (btxcal) { 7900 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 7901 rf_val &= (~0x7F); 7902 rf_val |= tx_agc_fc; 7903 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 7904 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 7905 rf_val &= (~0x7F); 7906 rf_val |= tx_agc_fc; 7907 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 7908 } else { 7909 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 7910 rf_val &= (~0x7F); 7911 rf_val |= rx_agc_fc; 7912 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 7913 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 7914 rf_val &= (~0x7F); 7915 rf_val |= rx_agc_fc; 7916 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 7917 } 7918 7919 usleep_range(500, 1000); 7920 7921 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 7922 7923 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 7924 7925 cal_diff = cal_r32_init - cal_r32_val; 7926 7927 if (btxcal) 7928 cmm_agc_fc = tx_agc_fc; 7929 else 7930 cmm_agc_fc = rx_agc_fc; 7931 7932 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) || 7933 ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) { 7934 if (btxcal) 7935 tx_agc_fc = 0; 7936 else 7937 rx_agc_fc = 0; 7938 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) { 7939 if (btxcal) 7940 tx_agc_fc++; 7941 else 7942 rx_agc_fc++; 7943 goto do_cal; 7944 } 7945 7946 if (btxcal) { 7947 if (loop == 0) 7948 drv_data->tx_calibration_bw20 = tx_agc_fc; 7949 else 7950 drv_data->tx_calibration_bw40 = tx_agc_fc; 7951 } else { 7952 if (loop == 0) 7953 drv_data->rx_calibration_bw20 = rx_agc_fc; 7954 else 7955 drv_data->rx_calibration_bw40 = rx_agc_fc; 7956 } 7957 7958 loop++; 7959 } while (loop <= 1); 7960 7961 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00); 7962 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01); 7963 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03); 7964 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04); 7965 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05); 7966 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06); 7967 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07); 7968 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08); 7969 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); 7970 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); 7971 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); 7972 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); 7973 7974 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37); 7975 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38); 7976 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39); 7977 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40); 7978 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41); 7979 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42); 7980 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43); 7981 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44); 7982 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45); 7983 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46); 7984 7985 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58); 7986 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59); 7987 7988 rt2800_bbp_write(rt2x00dev, 23, savebbpr23); 7989 7990 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0); 7991 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2); 7992 7993 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 7994 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 7995 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)); 7996 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 7997 7998 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); 7999 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); 8000 } 8001 8002 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev) 8003 { 8004 /* Initialize RF central register to default value */ 8005 rt2800_rfcsr_write(rt2x00dev, 0, 0x02); 8006 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 8007 rt2800_rfcsr_write(rt2x00dev, 2, 0x33); 8008 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF); 8009 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 8010 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 8011 rt2800_rfcsr_write(rt2x00dev, 6, 0x00); 8012 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8013 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 8014 rt2800_rfcsr_write(rt2x00dev, 9, 0x00); 8015 rt2800_rfcsr_write(rt2x00dev, 10, 0x00); 8016 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 8017 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset); 8018 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 8019 rt2800_rfcsr_write(rt2x00dev, 14, 0x40); 8020 rt2800_rfcsr_write(rt2x00dev, 15, 0x22); 8021 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C); 8022 rt2800_rfcsr_write(rt2x00dev, 17, 0x00); 8023 rt2800_rfcsr_write(rt2x00dev, 18, 0x00); 8024 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8025 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0); 8026 rt2800_rfcsr_write(rt2x00dev, 21, 0x12); 8027 rt2800_rfcsr_write(rt2x00dev, 22, 0x07); 8028 rt2800_rfcsr_write(rt2x00dev, 23, 0x13); 8029 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE); 8030 rt2800_rfcsr_write(rt2x00dev, 25, 0x24); 8031 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A); 8032 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8033 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8034 rt2800_rfcsr_write(rt2x00dev, 29, 0x05); 8035 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 8036 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 8037 rt2800_rfcsr_write(rt2x00dev, 32, 0x00); 8038 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8039 rt2800_rfcsr_write(rt2x00dev, 34, 0x00); 8040 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 8041 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8042 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 8043 rt2800_rfcsr_write(rt2x00dev, 38, 0x00); 8044 rt2800_rfcsr_write(rt2x00dev, 39, 0x00); 8045 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 8046 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0); 8047 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B); 8048 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 8049 8050 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 8051 if (rt2800_clk_is_20mhz(rt2x00dev)) 8052 rt2800_rfcsr_write(rt2x00dev, 13, 0x03); 8053 else 8054 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 8055 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C); 8056 rt2800_rfcsr_write(rt2x00dev, 16, 0x80); 8057 rt2800_rfcsr_write(rt2x00dev, 17, 0x99); 8058 rt2800_rfcsr_write(rt2x00dev, 18, 0x99); 8059 rt2800_rfcsr_write(rt2x00dev, 19, 0x09); 8060 rt2800_rfcsr_write(rt2x00dev, 20, 0x50); 8061 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0); 8062 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 8063 rt2800_rfcsr_write(rt2x00dev, 23, 0x06); 8064 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8065 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 8066 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D); 8067 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8068 rt2800_rfcsr_write(rt2x00dev, 28, 0x61); 8069 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5); 8070 rt2800_rfcsr_write(rt2x00dev, 43, 0x02); 8071 8072 rt2800_rfcsr_write(rt2x00dev, 28, 0x62); 8073 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD); 8074 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 8075 8076 /* Initialize RF channel register to default value */ 8077 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03); 8078 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00); 8079 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00); 8080 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00); 8081 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00); 8082 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08); 8083 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00); 8084 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51); 8085 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53); 8086 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16); 8087 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61); 8088 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 8089 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22); 8090 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D); 8091 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 8092 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13); 8093 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22); 8094 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27); 8095 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02); 8096 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 8097 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01); 8098 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52); 8099 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80); 8100 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3); 8101 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00); 8102 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00); 8103 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00); 8104 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00); 8105 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C); 8106 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B); 8107 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B); 8108 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31); 8109 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D); 8110 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00); 8111 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6); 8112 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55); 8113 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00); 8114 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB); 8115 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3); 8116 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3); 8117 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03); 8118 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00); 8119 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00); 8120 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3); 8121 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3); 8122 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 8123 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07); 8124 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68); 8125 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF); 8126 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C); 8127 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07); 8128 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8); 8129 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85); 8130 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10); 8131 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07); 8132 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A); 8133 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85); 8134 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10); 8135 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C); 8136 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00); 8137 8138 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5); 8139 8140 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47); 8141 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71); 8142 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33); 8143 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E); 8144 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23); 8145 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4); 8146 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02); 8147 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12); 8148 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C); 8149 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB); 8150 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D); 8151 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6); 8152 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08); 8153 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4); 8154 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 8155 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3); 8156 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 8157 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); 8158 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67); 8159 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69); 8160 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF); 8161 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27); 8162 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20); 8163 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 8164 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF); 8165 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C); 8166 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20); 8167 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 8168 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7); 8169 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09); 8170 8171 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51); 8172 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 8173 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 8174 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C); 8175 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64); 8176 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51); 8177 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36); 8178 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 8179 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16); 8180 8181 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C); 8182 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC); 8183 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F); 8184 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); 8185 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 8186 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 8187 8188 /* Initialize RF channel register for DRQFN */ 8189 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 8190 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3); 8191 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5); 8192 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28); 8193 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68); 8194 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7); 8195 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02); 8196 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7); 8197 8198 /* Initialize RF DC calibration register to default value */ 8199 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47); 8200 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00); 8201 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00); 8202 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00); 8203 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00); 8204 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 8205 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 8206 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 8207 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 8208 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00); 8209 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07); 8210 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01); 8211 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07); 8212 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07); 8213 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07); 8214 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20); 8215 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22); 8216 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00); 8217 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00); 8218 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00); 8219 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00); 8220 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1); 8221 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11); 8222 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02); 8223 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41); 8224 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20); 8225 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00); 8226 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7); 8227 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2); 8228 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20); 8229 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49); 8230 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20); 8231 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04); 8232 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1); 8233 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1); 8234 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01); 8235 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00); 8236 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00); 8237 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00); 8238 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00); 8239 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00); 8240 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00); 8241 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E); 8242 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D); 8243 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E); 8244 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D); 8245 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E); 8246 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D); 8247 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00); 8248 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00); 8249 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00); 8250 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00); 8251 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00); 8252 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 8253 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 8254 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A); 8255 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00); 8256 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00); 8257 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00); 8258 8259 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08); 8260 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04); 8261 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20); 8262 8263 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 8264 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C); 8265 8266 rt2800_bw_filter_calibration(rt2x00dev, true); 8267 rt2800_bw_filter_calibration(rt2x00dev, false); 8268 } 8269 8270 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) 8271 { 8272 if (rt2800_is_305x_soc(rt2x00dev)) { 8273 rt2800_init_rfcsr_305x_soc(rt2x00dev); 8274 return; 8275 } 8276 8277 switch (rt2x00dev->chip.rt) { 8278 case RT3070: 8279 case RT3071: 8280 case RT3090: 8281 rt2800_init_rfcsr_30xx(rt2x00dev); 8282 break; 8283 case RT3290: 8284 rt2800_init_rfcsr_3290(rt2x00dev); 8285 break; 8286 case RT3352: 8287 rt2800_init_rfcsr_3352(rt2x00dev); 8288 break; 8289 case RT3390: 8290 rt2800_init_rfcsr_3390(rt2x00dev); 8291 break; 8292 case RT3572: 8293 rt2800_init_rfcsr_3572(rt2x00dev); 8294 break; 8295 case RT3593: 8296 rt2800_init_rfcsr_3593(rt2x00dev); 8297 break; 8298 case RT5350: 8299 rt2800_init_rfcsr_5350(rt2x00dev); 8300 break; 8301 case RT5390: 8302 rt2800_init_rfcsr_5390(rt2x00dev); 8303 break; 8304 case RT5392: 8305 rt2800_init_rfcsr_5392(rt2x00dev); 8306 break; 8307 case RT5592: 8308 rt2800_init_rfcsr_5592(rt2x00dev); 8309 break; 8310 case RT6352: 8311 rt2800_init_rfcsr_6352(rt2x00dev); 8312 break; 8313 } 8314 } 8315 8316 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) 8317 { 8318 u32 reg; 8319 u16 word; 8320 8321 /* 8322 * Initialize MAC registers. 8323 */ 8324 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || 8325 rt2800_init_registers(rt2x00dev))) 8326 return -EIO; 8327 8328 /* 8329 * Wait BBP/RF to wake up. 8330 */ 8331 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev))) 8332 return -EIO; 8333 8334 /* 8335 * Send signal during boot time to initialize firmware. 8336 */ 8337 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 8338 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 8339 if (rt2x00_is_usb(rt2x00dev)) 8340 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 8341 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 8342 msleep(1); 8343 8344 /* 8345 * Make sure BBP is up and running. 8346 */ 8347 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev))) 8348 return -EIO; 8349 8350 /* 8351 * Initialize BBP/RF registers. 8352 */ 8353 rt2800_init_bbp(rt2x00dev); 8354 rt2800_init_rfcsr(rt2x00dev); 8355 8356 if (rt2x00_is_usb(rt2x00dev) && 8357 (rt2x00_rt(rt2x00dev, RT3070) || 8358 rt2x00_rt(rt2x00dev, RT3071) || 8359 rt2x00_rt(rt2x00dev, RT3572))) { 8360 udelay(200); 8361 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); 8362 udelay(10); 8363 } 8364 8365 /* 8366 * Enable RX. 8367 */ 8368 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8369 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 8370 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 8371 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 8372 8373 udelay(50); 8374 8375 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 8376 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 8377 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 8378 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 8379 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 8380 8381 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8382 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 8383 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); 8384 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 8385 8386 /* 8387 * Initialize LED control 8388 */ 8389 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF); 8390 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, 8391 word & 0xff, (word >> 8) & 0xff); 8392 8393 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF); 8394 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, 8395 word & 0xff, (word >> 8) & 0xff); 8396 8397 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY); 8398 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, 8399 word & 0xff, (word >> 8) & 0xff); 8400 8401 return 0; 8402 } 8403 EXPORT_SYMBOL_GPL(rt2800_enable_radio); 8404 8405 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) 8406 { 8407 u32 reg; 8408 8409 rt2800_disable_wpdma(rt2x00dev); 8410 8411 /* Wait for DMA, ignore error */ 8412 rt2800_wait_wpdma_ready(rt2x00dev); 8413 8414 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8415 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); 8416 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 8417 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 8418 } 8419 EXPORT_SYMBOL_GPL(rt2800_disable_radio); 8420 8421 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 8422 { 8423 u32 reg; 8424 u16 efuse_ctrl_reg; 8425 8426 if (rt2x00_rt(rt2x00dev, RT3290)) 8427 efuse_ctrl_reg = EFUSE_CTRL_3290; 8428 else 8429 efuse_ctrl_reg = EFUSE_CTRL; 8430 8431 reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg); 8432 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); 8433 } 8434 EXPORT_SYMBOL_GPL(rt2800_efuse_detect); 8435 8436 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) 8437 { 8438 u32 reg; 8439 u16 efuse_ctrl_reg; 8440 u16 efuse_data0_reg; 8441 u16 efuse_data1_reg; 8442 u16 efuse_data2_reg; 8443 u16 efuse_data3_reg; 8444 8445 if (rt2x00_rt(rt2x00dev, RT3290)) { 8446 efuse_ctrl_reg = EFUSE_CTRL_3290; 8447 efuse_data0_reg = EFUSE_DATA0_3290; 8448 efuse_data1_reg = EFUSE_DATA1_3290; 8449 efuse_data2_reg = EFUSE_DATA2_3290; 8450 efuse_data3_reg = EFUSE_DATA3_3290; 8451 } else { 8452 efuse_ctrl_reg = EFUSE_CTRL; 8453 efuse_data0_reg = EFUSE_DATA0; 8454 efuse_data1_reg = EFUSE_DATA1; 8455 efuse_data2_reg = EFUSE_DATA2; 8456 efuse_data3_reg = EFUSE_DATA3; 8457 } 8458 mutex_lock(&rt2x00dev->csr_mutex); 8459 8460 reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg); 8461 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); 8462 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); 8463 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); 8464 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); 8465 8466 /* Wait until the EEPROM has been loaded */ 8467 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); 8468 /* Apparently the data is read from end to start */ 8469 reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg); 8470 /* The returned value is in CPU order, but eeprom is le */ 8471 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); 8472 reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg); 8473 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); 8474 reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg); 8475 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); 8476 reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg); 8477 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); 8478 8479 mutex_unlock(&rt2x00dev->csr_mutex); 8480 } 8481 8482 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 8483 { 8484 unsigned int i; 8485 8486 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) 8487 rt2800_efuse_read(rt2x00dev, i); 8488 8489 return 0; 8490 } 8491 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); 8492 8493 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev) 8494 { 8495 u16 word; 8496 8497 if (rt2x00_rt(rt2x00dev, RT3593)) 8498 return 0; 8499 8500 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG); 8501 if ((word & 0x00ff) != 0x00ff) 8502 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL); 8503 8504 return 0; 8505 } 8506 8507 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev) 8508 { 8509 u16 word; 8510 8511 if (rt2x00_rt(rt2x00dev, RT3593)) 8512 return 0; 8513 8514 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A); 8515 if ((word & 0x00ff) != 0x00ff) 8516 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL); 8517 8518 return 0; 8519 } 8520 8521 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) 8522 { 8523 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 8524 u16 word; 8525 u8 *mac; 8526 u8 default_lna_gain; 8527 int retval; 8528 8529 /* 8530 * Read the EEPROM. 8531 */ 8532 retval = rt2800_read_eeprom(rt2x00dev); 8533 if (retval) 8534 return retval; 8535 8536 /* 8537 * Start validation of the data that has been read. 8538 */ 8539 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 8540 rt2x00lib_set_mac_address(rt2x00dev, mac); 8541 8542 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 8543 if (word == 0xffff) { 8544 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 8545 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); 8546 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); 8547 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 8548 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 8549 } else if (rt2x00_rt(rt2x00dev, RT2860) || 8550 rt2x00_rt(rt2x00dev, RT2872)) { 8551 /* 8552 * There is a max of 2 RX streams for RT28x0 series 8553 */ 8554 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2) 8555 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 8556 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 8557 } 8558 8559 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 8560 if (word == 0xffff) { 8561 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); 8562 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); 8563 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0); 8564 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0); 8565 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0); 8566 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0); 8567 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0); 8568 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0); 8569 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0); 8570 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0); 8571 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0); 8572 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0); 8573 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0); 8574 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); 8575 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); 8576 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); 8577 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 8578 } 8579 8580 word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 8581 if ((word & 0x00ff) == 0x00ff) { 8582 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 8583 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 8584 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); 8585 } 8586 if ((word & 0xff00) == 0xff00) { 8587 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, 8588 LED_MODE_TXRX_ACTIVITY); 8589 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); 8590 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 8591 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); 8592 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); 8593 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); 8594 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word); 8595 } 8596 8597 /* 8598 * During the LNA validation we are going to use 8599 * lna0 as correct value. Note that EEPROM_LNA 8600 * is never validated. 8601 */ 8602 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 8603 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); 8604 8605 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 8606 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) 8607 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); 8608 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) 8609 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); 8610 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); 8611 8612 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev); 8613 8614 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 8615 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) 8616 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); 8617 if (!rt2x00_rt(rt2x00dev, RT3593)) { 8618 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || 8619 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) 8620 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, 8621 default_lna_gain); 8622 } 8623 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); 8624 8625 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev); 8626 8627 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 8628 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) 8629 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); 8630 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) 8631 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); 8632 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); 8633 8634 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 8635 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) 8636 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); 8637 if (!rt2x00_rt(rt2x00dev, RT3593)) { 8638 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || 8639 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) 8640 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, 8641 default_lna_gain); 8642 } 8643 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); 8644 8645 if (rt2x00_rt(rt2x00dev, RT3593)) { 8646 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 8647 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 || 8648 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff) 8649 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 8650 default_lna_gain); 8651 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 || 8652 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff) 8653 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 8654 default_lna_gain); 8655 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word); 8656 } 8657 8658 return 0; 8659 } 8660 8661 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) 8662 { 8663 u16 value; 8664 u16 eeprom; 8665 u16 rf; 8666 8667 /* 8668 * Read EEPROM word for configuration. 8669 */ 8670 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 8671 8672 /* 8673 * Identify RF chipset by EEPROM value 8674 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 8675 * RT53xx: defined in "EEPROM_CHIP_ID" field 8676 */ 8677 if (rt2x00_rt(rt2x00dev, RT3290) || 8678 rt2x00_rt(rt2x00dev, RT5390) || 8679 rt2x00_rt(rt2x00dev, RT5392) || 8680 rt2x00_rt(rt2x00dev, RT6352)) 8681 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID); 8682 else if (rt2x00_rt(rt2x00dev, RT3352)) 8683 rf = RF3322; 8684 else if (rt2x00_rt(rt2x00dev, RT5350)) 8685 rf = RF5350; 8686 else 8687 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 8688 8689 switch (rf) { 8690 case RF2820: 8691 case RF2850: 8692 case RF2720: 8693 case RF2750: 8694 case RF3020: 8695 case RF2020: 8696 case RF3021: 8697 case RF3022: 8698 case RF3052: 8699 case RF3053: 8700 case RF3070: 8701 case RF3290: 8702 case RF3320: 8703 case RF3322: 8704 case RF5350: 8705 case RF5360: 8706 case RF5362: 8707 case RF5370: 8708 case RF5372: 8709 case RF5390: 8710 case RF5392: 8711 case RF5592: 8712 case RF7620: 8713 break; 8714 default: 8715 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n", 8716 rf); 8717 return -ENODEV; 8718 } 8719 8720 rt2x00_set_rf(rt2x00dev, rf); 8721 8722 /* 8723 * Identify default antenna configuration. 8724 */ 8725 rt2x00dev->default_ant.tx_chain_num = 8726 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); 8727 rt2x00dev->default_ant.rx_chain_num = 8728 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); 8729 8730 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 8731 8732 if (rt2x00_rt(rt2x00dev, RT3070) || 8733 rt2x00_rt(rt2x00dev, RT3090) || 8734 rt2x00_rt(rt2x00dev, RT3352) || 8735 rt2x00_rt(rt2x00dev, RT3390)) { 8736 value = rt2x00_get_field16(eeprom, 8737 EEPROM_NIC_CONF1_ANT_DIVERSITY); 8738 switch (value) { 8739 case 0: 8740 case 1: 8741 case 2: 8742 rt2x00dev->default_ant.tx = ANTENNA_A; 8743 rt2x00dev->default_ant.rx = ANTENNA_A; 8744 break; 8745 case 3: 8746 rt2x00dev->default_ant.tx = ANTENNA_A; 8747 rt2x00dev->default_ant.rx = ANTENNA_B; 8748 break; 8749 } 8750 } else { 8751 rt2x00dev->default_ant.tx = ANTENNA_A; 8752 rt2x00dev->default_ant.rx = ANTENNA_A; 8753 } 8754 8755 /* These chips have hardware RX antenna diversity */ 8756 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 8757 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 8758 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */ 8759 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */ 8760 } 8761 8762 /* 8763 * Determine external LNA informations. 8764 */ 8765 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G)) 8766 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); 8767 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G)) 8768 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); 8769 8770 /* 8771 * Detect if this device has an hardware controlled radio. 8772 */ 8773 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO)) 8774 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 8775 8776 /* 8777 * Detect if this device has Bluetooth co-existence. 8778 */ 8779 if (!rt2x00_rt(rt2x00dev, RT3352) && 8780 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) 8781 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); 8782 8783 /* 8784 * Read frequency offset and RF programming sequence. 8785 */ 8786 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 8787 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 8788 8789 /* 8790 * Store led settings, for correct led behaviour. 8791 */ 8792 #ifdef CONFIG_RT2X00_LIB_LEDS 8793 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 8794 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 8795 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 8796 8797 rt2x00dev->led_mcu_reg = eeprom; 8798 #endif /* CONFIG_RT2X00_LIB_LEDS */ 8799 8800 /* 8801 * Check if support EIRP tx power limit feature. 8802 */ 8803 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 8804 8805 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < 8806 EIRP_MAX_TX_POWER_LIMIT) 8807 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); 8808 8809 /* 8810 * Detect if device uses internal or external PA 8811 */ 8812 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 8813 8814 if (rt2x00_rt(rt2x00dev, RT3352)) { 8815 if (rt2x00_get_field16(eeprom, 8816 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352)) 8817 __set_bit(CAPABILITY_EXTERNAL_PA_TX0, 8818 &rt2x00dev->cap_flags); 8819 if (rt2x00_get_field16(eeprom, 8820 EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352)) 8821 __set_bit(CAPABILITY_EXTERNAL_PA_TX1, 8822 &rt2x00dev->cap_flags); 8823 } 8824 8825 return 0; 8826 } 8827 8828 /* 8829 * RF value list for rt28xx 8830 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) 8831 */ 8832 static const struct rf_channel rf_vals[] = { 8833 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, 8834 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, 8835 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, 8836 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, 8837 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, 8838 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, 8839 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, 8840 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, 8841 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, 8842 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, 8843 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, 8844 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, 8845 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, 8846 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, 8847 8848 /* 802.11 UNI / HyperLan 2 */ 8849 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, 8850 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, 8851 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, 8852 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, 8853 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, 8854 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, 8855 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, 8856 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, 8857 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, 8858 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, 8859 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, 8860 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, 8861 8862 /* 802.11 HyperLan 2 */ 8863 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, 8864 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, 8865 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, 8866 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, 8867 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, 8868 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, 8869 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, 8870 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, 8871 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, 8872 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, 8873 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, 8874 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, 8875 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, 8876 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, 8877 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, 8878 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, 8879 8880 /* 802.11 UNII */ 8881 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, 8882 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, 8883 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, 8884 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, 8885 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, 8886 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, 8887 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, 8888 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, 8889 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, 8890 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, 8891 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, 8892 8893 /* 802.11 Japan */ 8894 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, 8895 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, 8896 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, 8897 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, 8898 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, 8899 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, 8900 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, 8901 }; 8902 8903 /* 8904 * RF value list for rt3xxx 8905 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053) 8906 */ 8907 static const struct rf_channel rf_vals_3x[] = { 8908 {1, 241, 2, 2 }, 8909 {2, 241, 2, 7 }, 8910 {3, 242, 2, 2 }, 8911 {4, 242, 2, 7 }, 8912 {5, 243, 2, 2 }, 8913 {6, 243, 2, 7 }, 8914 {7, 244, 2, 2 }, 8915 {8, 244, 2, 7 }, 8916 {9, 245, 2, 2 }, 8917 {10, 245, 2, 7 }, 8918 {11, 246, 2, 2 }, 8919 {12, 246, 2, 7 }, 8920 {13, 247, 2, 2 }, 8921 {14, 248, 2, 4 }, 8922 8923 /* 802.11 UNI / HyperLan 2 */ 8924 {36, 0x56, 0, 4}, 8925 {38, 0x56, 0, 6}, 8926 {40, 0x56, 0, 8}, 8927 {44, 0x57, 0, 0}, 8928 {46, 0x57, 0, 2}, 8929 {48, 0x57, 0, 4}, 8930 {52, 0x57, 0, 8}, 8931 {54, 0x57, 0, 10}, 8932 {56, 0x58, 0, 0}, 8933 {60, 0x58, 0, 4}, 8934 {62, 0x58, 0, 6}, 8935 {64, 0x58, 0, 8}, 8936 8937 /* 802.11 HyperLan 2 */ 8938 {100, 0x5b, 0, 8}, 8939 {102, 0x5b, 0, 10}, 8940 {104, 0x5c, 0, 0}, 8941 {108, 0x5c, 0, 4}, 8942 {110, 0x5c, 0, 6}, 8943 {112, 0x5c, 0, 8}, 8944 {116, 0x5d, 0, 0}, 8945 {118, 0x5d, 0, 2}, 8946 {120, 0x5d, 0, 4}, 8947 {124, 0x5d, 0, 8}, 8948 {126, 0x5d, 0, 10}, 8949 {128, 0x5e, 0, 0}, 8950 {132, 0x5e, 0, 4}, 8951 {134, 0x5e, 0, 6}, 8952 {136, 0x5e, 0, 8}, 8953 {140, 0x5f, 0, 0}, 8954 8955 /* 802.11 UNII */ 8956 {149, 0x5f, 0, 9}, 8957 {151, 0x5f, 0, 11}, 8958 {153, 0x60, 0, 1}, 8959 {157, 0x60, 0, 5}, 8960 {159, 0x60, 0, 7}, 8961 {161, 0x60, 0, 9}, 8962 {165, 0x61, 0, 1}, 8963 {167, 0x61, 0, 3}, 8964 {169, 0x61, 0, 5}, 8965 {171, 0x61, 0, 7}, 8966 {173, 0x61, 0, 9}, 8967 }; 8968 8969 /* 8970 * RF value list for rt3xxx with Xtal20MHz 8971 * Supports: 2.4 GHz (all) (RF3322) 8972 */ 8973 static const struct rf_channel rf_vals_3x_xtal20[] = { 8974 {1, 0xE2, 2, 0x14}, 8975 {2, 0xE3, 2, 0x14}, 8976 {3, 0xE4, 2, 0x14}, 8977 {4, 0xE5, 2, 0x14}, 8978 {5, 0xE6, 2, 0x14}, 8979 {6, 0xE7, 2, 0x14}, 8980 {7, 0xE8, 2, 0x14}, 8981 {8, 0xE9, 2, 0x14}, 8982 {9, 0xEA, 2, 0x14}, 8983 {10, 0xEB, 2, 0x14}, 8984 {11, 0xEC, 2, 0x14}, 8985 {12, 0xED, 2, 0x14}, 8986 {13, 0xEE, 2, 0x14}, 8987 {14, 0xF0, 2, 0x18}, 8988 }; 8989 8990 static const struct rf_channel rf_vals_5592_xtal20[] = { 8991 /* Channel, N, K, mod, R */ 8992 {1, 482, 4, 10, 3}, 8993 {2, 483, 4, 10, 3}, 8994 {3, 484, 4, 10, 3}, 8995 {4, 485, 4, 10, 3}, 8996 {5, 486, 4, 10, 3}, 8997 {6, 487, 4, 10, 3}, 8998 {7, 488, 4, 10, 3}, 8999 {8, 489, 4, 10, 3}, 9000 {9, 490, 4, 10, 3}, 9001 {10, 491, 4, 10, 3}, 9002 {11, 492, 4, 10, 3}, 9003 {12, 493, 4, 10, 3}, 9004 {13, 494, 4, 10, 3}, 9005 {14, 496, 8, 10, 3}, 9006 {36, 172, 8, 12, 1}, 9007 {38, 173, 0, 12, 1}, 9008 {40, 173, 4, 12, 1}, 9009 {42, 173, 8, 12, 1}, 9010 {44, 174, 0, 12, 1}, 9011 {46, 174, 4, 12, 1}, 9012 {48, 174, 8, 12, 1}, 9013 {50, 175, 0, 12, 1}, 9014 {52, 175, 4, 12, 1}, 9015 {54, 175, 8, 12, 1}, 9016 {56, 176, 0, 12, 1}, 9017 {58, 176, 4, 12, 1}, 9018 {60, 176, 8, 12, 1}, 9019 {62, 177, 0, 12, 1}, 9020 {64, 177, 4, 12, 1}, 9021 {100, 183, 4, 12, 1}, 9022 {102, 183, 8, 12, 1}, 9023 {104, 184, 0, 12, 1}, 9024 {106, 184, 4, 12, 1}, 9025 {108, 184, 8, 12, 1}, 9026 {110, 185, 0, 12, 1}, 9027 {112, 185, 4, 12, 1}, 9028 {114, 185, 8, 12, 1}, 9029 {116, 186, 0, 12, 1}, 9030 {118, 186, 4, 12, 1}, 9031 {120, 186, 8, 12, 1}, 9032 {122, 187, 0, 12, 1}, 9033 {124, 187, 4, 12, 1}, 9034 {126, 187, 8, 12, 1}, 9035 {128, 188, 0, 12, 1}, 9036 {130, 188, 4, 12, 1}, 9037 {132, 188, 8, 12, 1}, 9038 {134, 189, 0, 12, 1}, 9039 {136, 189, 4, 12, 1}, 9040 {138, 189, 8, 12, 1}, 9041 {140, 190, 0, 12, 1}, 9042 {149, 191, 6, 12, 1}, 9043 {151, 191, 10, 12, 1}, 9044 {153, 192, 2, 12, 1}, 9045 {155, 192, 6, 12, 1}, 9046 {157, 192, 10, 12, 1}, 9047 {159, 193, 2, 12, 1}, 9048 {161, 193, 6, 12, 1}, 9049 {165, 194, 2, 12, 1}, 9050 {184, 164, 0, 12, 1}, 9051 {188, 164, 4, 12, 1}, 9052 {192, 165, 8, 12, 1}, 9053 {196, 166, 0, 12, 1}, 9054 }; 9055 9056 static const struct rf_channel rf_vals_5592_xtal40[] = { 9057 /* Channel, N, K, mod, R */ 9058 {1, 241, 2, 10, 3}, 9059 {2, 241, 7, 10, 3}, 9060 {3, 242, 2, 10, 3}, 9061 {4, 242, 7, 10, 3}, 9062 {5, 243, 2, 10, 3}, 9063 {6, 243, 7, 10, 3}, 9064 {7, 244, 2, 10, 3}, 9065 {8, 244, 7, 10, 3}, 9066 {9, 245, 2, 10, 3}, 9067 {10, 245, 7, 10, 3}, 9068 {11, 246, 2, 10, 3}, 9069 {12, 246, 7, 10, 3}, 9070 {13, 247, 2, 10, 3}, 9071 {14, 248, 4, 10, 3}, 9072 {36, 86, 4, 12, 1}, 9073 {38, 86, 6, 12, 1}, 9074 {40, 86, 8, 12, 1}, 9075 {42, 86, 10, 12, 1}, 9076 {44, 87, 0, 12, 1}, 9077 {46, 87, 2, 12, 1}, 9078 {48, 87, 4, 12, 1}, 9079 {50, 87, 6, 12, 1}, 9080 {52, 87, 8, 12, 1}, 9081 {54, 87, 10, 12, 1}, 9082 {56, 88, 0, 12, 1}, 9083 {58, 88, 2, 12, 1}, 9084 {60, 88, 4, 12, 1}, 9085 {62, 88, 6, 12, 1}, 9086 {64, 88, 8, 12, 1}, 9087 {100, 91, 8, 12, 1}, 9088 {102, 91, 10, 12, 1}, 9089 {104, 92, 0, 12, 1}, 9090 {106, 92, 2, 12, 1}, 9091 {108, 92, 4, 12, 1}, 9092 {110, 92, 6, 12, 1}, 9093 {112, 92, 8, 12, 1}, 9094 {114, 92, 10, 12, 1}, 9095 {116, 93, 0, 12, 1}, 9096 {118, 93, 2, 12, 1}, 9097 {120, 93, 4, 12, 1}, 9098 {122, 93, 6, 12, 1}, 9099 {124, 93, 8, 12, 1}, 9100 {126, 93, 10, 12, 1}, 9101 {128, 94, 0, 12, 1}, 9102 {130, 94, 2, 12, 1}, 9103 {132, 94, 4, 12, 1}, 9104 {134, 94, 6, 12, 1}, 9105 {136, 94, 8, 12, 1}, 9106 {138, 94, 10, 12, 1}, 9107 {140, 95, 0, 12, 1}, 9108 {149, 95, 9, 12, 1}, 9109 {151, 95, 11, 12, 1}, 9110 {153, 96, 1, 12, 1}, 9111 {155, 96, 3, 12, 1}, 9112 {157, 96, 5, 12, 1}, 9113 {159, 96, 7, 12, 1}, 9114 {161, 96, 9, 12, 1}, 9115 {165, 97, 1, 12, 1}, 9116 {184, 82, 0, 12, 1}, 9117 {188, 82, 4, 12, 1}, 9118 {192, 82, 8, 12, 1}, 9119 {196, 83, 0, 12, 1}, 9120 }; 9121 9122 static const struct rf_channel rf_vals_7620[] = { 9123 {1, 0x50, 0x99, 0x99, 1}, 9124 {2, 0x50, 0x44, 0x44, 2}, 9125 {3, 0x50, 0xEE, 0xEE, 2}, 9126 {4, 0x50, 0x99, 0x99, 3}, 9127 {5, 0x51, 0x44, 0x44, 0}, 9128 {6, 0x51, 0xEE, 0xEE, 0}, 9129 {7, 0x51, 0x99, 0x99, 1}, 9130 {8, 0x51, 0x44, 0x44, 2}, 9131 {9, 0x51, 0xEE, 0xEE, 2}, 9132 {10, 0x51, 0x99, 0x99, 3}, 9133 {11, 0x52, 0x44, 0x44, 0}, 9134 {12, 0x52, 0xEE, 0xEE, 0}, 9135 {13, 0x52, 0x99, 0x99, 1}, 9136 {14, 0x52, 0x33, 0x33, 3}, 9137 }; 9138 9139 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 9140 { 9141 struct hw_mode_spec *spec = &rt2x00dev->spec; 9142 struct channel_info *info; 9143 char *default_power1; 9144 char *default_power2; 9145 char *default_power3; 9146 unsigned int i, tx_chains, rx_chains; 9147 u32 reg; 9148 9149 /* 9150 * Disable powersaving as default. 9151 */ 9152 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 9153 9154 /* 9155 * Change default retry settings to values corresponding more closely 9156 * to rate[0].count setting of minstrel rate control algorithm. 9157 */ 9158 rt2x00dev->hw->wiphy->retry_short = 2; 9159 rt2x00dev->hw->wiphy->retry_long = 2; 9160 9161 /* 9162 * Initialize all hw fields. 9163 */ 9164 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS); 9165 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION); 9166 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); 9167 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); 9168 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); 9169 9170 /* 9171 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices 9172 * unless we are capable of sending the buffered frames out after the 9173 * DTIM transmission using rt2x00lib_beacondone. This will send out 9174 * multicast and broadcast traffic immediately instead of buffering it 9175 * infinitly and thus dropping it after some time. 9176 */ 9177 if (!rt2x00_is_usb(rt2x00dev)) 9178 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); 9179 9180 /* Set MFP if HW crypto is disabled. */ 9181 if (rt2800_hwcrypt_disabled(rt2x00dev)) 9182 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE); 9183 9184 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 9185 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 9186 rt2800_eeprom_addr(rt2x00dev, 9187 EEPROM_MAC_ADDR_0)); 9188 9189 /* 9190 * As rt2800 has a global fallback table we cannot specify 9191 * more then one tx rate per frame but since the hw will 9192 * try several rates (based on the fallback table) we should 9193 * initialize max_report_rates to the maximum number of rates 9194 * we are going to try. Otherwise mac80211 will truncate our 9195 * reported tx rates and the rc algortihm will end up with 9196 * incorrect data. 9197 */ 9198 rt2x00dev->hw->max_rates = 1; 9199 rt2x00dev->hw->max_report_rates = 7; 9200 rt2x00dev->hw->max_rate_tries = 1; 9201 9202 /* 9203 * Initialize hw_mode information. 9204 */ 9205 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 9206 9207 switch (rt2x00dev->chip.rf) { 9208 case RF2720: 9209 case RF2820: 9210 spec->num_channels = 14; 9211 spec->channels = rf_vals; 9212 break; 9213 9214 case RF2750: 9215 case RF2850: 9216 spec->num_channels = ARRAY_SIZE(rf_vals); 9217 spec->channels = rf_vals; 9218 break; 9219 9220 case RF2020: 9221 case RF3020: 9222 case RF3021: 9223 case RF3022: 9224 case RF3070: 9225 case RF3290: 9226 case RF3320: 9227 case RF3322: 9228 case RF5350: 9229 case RF5360: 9230 case RF5362: 9231 case RF5370: 9232 case RF5372: 9233 case RF5390: 9234 case RF5392: 9235 spec->num_channels = 14; 9236 if (rt2800_clk_is_20mhz(rt2x00dev)) 9237 spec->channels = rf_vals_3x_xtal20; 9238 else 9239 spec->channels = rf_vals_3x; 9240 break; 9241 9242 case RF7620: 9243 spec->num_channels = ARRAY_SIZE(rf_vals_7620); 9244 spec->channels = rf_vals_7620; 9245 break; 9246 9247 case RF3052: 9248 case RF3053: 9249 spec->num_channels = ARRAY_SIZE(rf_vals_3x); 9250 spec->channels = rf_vals_3x; 9251 break; 9252 9253 case RF5592: 9254 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX); 9255 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { 9256 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); 9257 spec->channels = rf_vals_5592_xtal40; 9258 } else { 9259 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20); 9260 spec->channels = rf_vals_5592_xtal20; 9261 } 9262 break; 9263 } 9264 9265 if (WARN_ON_ONCE(!spec->channels)) 9266 return -ENODEV; 9267 9268 spec->supported_bands = SUPPORT_BAND_2GHZ; 9269 if (spec->num_channels > 14) 9270 spec->supported_bands |= SUPPORT_BAND_5GHZ; 9271 9272 /* 9273 * Initialize HT information. 9274 */ 9275 if (!rt2x00_rf(rt2x00dev, RF2020)) 9276 spec->ht.ht_supported = true; 9277 else 9278 spec->ht.ht_supported = false; 9279 9280 spec->ht.cap = 9281 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 9282 IEEE80211_HT_CAP_GRN_FLD | 9283 IEEE80211_HT_CAP_SGI_20 | 9284 IEEE80211_HT_CAP_SGI_40; 9285 9286 tx_chains = rt2x00dev->default_ant.tx_chain_num; 9287 rx_chains = rt2x00dev->default_ant.rx_chain_num; 9288 9289 if (tx_chains >= 2) 9290 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; 9291 9292 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT; 9293 9294 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2; 9295 spec->ht.ampdu_density = 4; 9296 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 9297 if (tx_chains != rx_chains) { 9298 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 9299 spec->ht.mcs.tx_params |= 9300 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; 9301 } 9302 9303 switch (rx_chains) { 9304 case 3: 9305 spec->ht.mcs.rx_mask[2] = 0xff; 9306 case 2: 9307 spec->ht.mcs.rx_mask[1] = 0xff; 9308 case 1: 9309 spec->ht.mcs.rx_mask[0] = 0xff; 9310 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ 9311 break; 9312 } 9313 9314 /* 9315 * Create channel information array 9316 */ 9317 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 9318 if (!info) 9319 return -ENOMEM; 9320 9321 spec->channels_info = info; 9322 9323 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 9324 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 9325 9326 if (rt2x00dev->default_ant.tx_chain_num > 2) 9327 default_power3 = rt2800_eeprom_addr(rt2x00dev, 9328 EEPROM_EXT_TXPOWER_BG3); 9329 else 9330 default_power3 = NULL; 9331 9332 for (i = 0; i < 14; i++) { 9333 info[i].default_power1 = default_power1[i]; 9334 info[i].default_power2 = default_power2[i]; 9335 if (default_power3) 9336 info[i].default_power3 = default_power3[i]; 9337 } 9338 9339 if (spec->num_channels > 14) { 9340 default_power1 = rt2800_eeprom_addr(rt2x00dev, 9341 EEPROM_TXPOWER_A1); 9342 default_power2 = rt2800_eeprom_addr(rt2x00dev, 9343 EEPROM_TXPOWER_A2); 9344 9345 if (rt2x00dev->default_ant.tx_chain_num > 2) 9346 default_power3 = 9347 rt2800_eeprom_addr(rt2x00dev, 9348 EEPROM_EXT_TXPOWER_A3); 9349 else 9350 default_power3 = NULL; 9351 9352 for (i = 14; i < spec->num_channels; i++) { 9353 info[i].default_power1 = default_power1[i - 14]; 9354 info[i].default_power2 = default_power2[i - 14]; 9355 if (default_power3) 9356 info[i].default_power3 = default_power3[i - 14]; 9357 } 9358 } 9359 9360 switch (rt2x00dev->chip.rf) { 9361 case RF2020: 9362 case RF3020: 9363 case RF3021: 9364 case RF3022: 9365 case RF3320: 9366 case RF3052: 9367 case RF3053: 9368 case RF3070: 9369 case RF3290: 9370 case RF5350: 9371 case RF5360: 9372 case RF5362: 9373 case RF5370: 9374 case RF5372: 9375 case RF5390: 9376 case RF5392: 9377 case RF5592: 9378 case RF7620: 9379 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags); 9380 break; 9381 } 9382 9383 return 0; 9384 } 9385 9386 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) 9387 { 9388 u32 reg; 9389 u32 rt; 9390 u32 rev; 9391 9392 if (rt2x00_rt(rt2x00dev, RT3290)) 9393 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290); 9394 else 9395 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 9396 9397 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); 9398 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); 9399 9400 switch (rt) { 9401 case RT2860: 9402 case RT2872: 9403 case RT2883: 9404 case RT3070: 9405 case RT3071: 9406 case RT3090: 9407 case RT3290: 9408 case RT3352: 9409 case RT3390: 9410 case RT3572: 9411 case RT3593: 9412 case RT5350: 9413 case RT5390: 9414 case RT5392: 9415 case RT5592: 9416 break; 9417 default: 9418 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n", 9419 rt, rev); 9420 return -ENODEV; 9421 } 9422 9423 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev)) 9424 rt = RT6352; 9425 9426 rt2x00_set_rt(rt2x00dev, rt, rev); 9427 9428 return 0; 9429 } 9430 9431 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) 9432 { 9433 int retval; 9434 u32 reg; 9435 9436 retval = rt2800_probe_rt(rt2x00dev); 9437 if (retval) 9438 return retval; 9439 9440 /* 9441 * Allocate eeprom data. 9442 */ 9443 retval = rt2800_validate_eeprom(rt2x00dev); 9444 if (retval) 9445 return retval; 9446 9447 retval = rt2800_init_eeprom(rt2x00dev); 9448 if (retval) 9449 return retval; 9450 9451 /* 9452 * Enable rfkill polling by setting GPIO direction of the 9453 * rfkill switch GPIO pin correctly. 9454 */ 9455 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 9456 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); 9457 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 9458 9459 /* 9460 * Initialize hw specifications. 9461 */ 9462 retval = rt2800_probe_hw_mode(rt2x00dev); 9463 if (retval) 9464 return retval; 9465 9466 /* 9467 * Set device capabilities. 9468 */ 9469 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); 9470 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags); 9471 if (!rt2x00_is_usb(rt2x00dev)) 9472 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags); 9473 9474 /* 9475 * Set device requirements. 9476 */ 9477 if (!rt2x00_is_soc(rt2x00dev)) 9478 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); 9479 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags); 9480 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags); 9481 if (!rt2800_hwcrypt_disabled(rt2x00dev)) 9482 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); 9483 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 9484 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags); 9485 if (rt2x00_is_usb(rt2x00dev)) 9486 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); 9487 else { 9488 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); 9489 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags); 9490 } 9491 9492 /* 9493 * Set the rssi offset. 9494 */ 9495 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 9496 9497 return 0; 9498 } 9499 EXPORT_SYMBOL_GPL(rt2800_probe_hw); 9500 9501 /* 9502 * IEEE80211 stack callback functions. 9503 */ 9504 void rt2800_get_key_seq(struct ieee80211_hw *hw, 9505 struct ieee80211_key_conf *key, 9506 struct ieee80211_key_seq *seq) 9507 { 9508 struct rt2x00_dev *rt2x00dev = hw->priv; 9509 struct mac_iveiv_entry iveiv_entry; 9510 u32 offset; 9511 9512 if (key->cipher != WLAN_CIPHER_SUITE_TKIP) 9513 return; 9514 9515 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 9516 rt2800_register_multiread(rt2x00dev, offset, 9517 &iveiv_entry, sizeof(iveiv_entry)); 9518 9519 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2); 9520 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4); 9521 } 9522 EXPORT_SYMBOL_GPL(rt2800_get_key_seq); 9523 9524 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) 9525 { 9526 struct rt2x00_dev *rt2x00dev = hw->priv; 9527 u32 reg; 9528 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); 9529 9530 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 9531 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); 9532 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 9533 9534 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 9535 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); 9536 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 9537 9538 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 9539 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); 9540 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 9541 9542 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 9543 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); 9544 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 9545 9546 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 9547 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); 9548 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 9549 9550 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 9551 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); 9552 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 9553 9554 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 9555 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); 9556 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 9557 9558 return 0; 9559 } 9560 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold); 9561 9562 int rt2800_conf_tx(struct ieee80211_hw *hw, 9563 struct ieee80211_vif *vif, u16 queue_idx, 9564 const struct ieee80211_tx_queue_params *params) 9565 { 9566 struct rt2x00_dev *rt2x00dev = hw->priv; 9567 struct data_queue *queue; 9568 struct rt2x00_field32 field; 9569 int retval; 9570 u32 reg; 9571 u32 offset; 9572 9573 /* 9574 * First pass the configuration through rt2x00lib, that will 9575 * update the queue settings and validate the input. After that 9576 * we are free to update the registers based on the value 9577 * in the queue parameter. 9578 */ 9579 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params); 9580 if (retval) 9581 return retval; 9582 9583 /* 9584 * We only need to perform additional register initialization 9585 * for WMM queues/ 9586 */ 9587 if (queue_idx >= 4) 9588 return 0; 9589 9590 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 9591 9592 /* Update WMM TXOP register */ 9593 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); 9594 field.bit_offset = (queue_idx & 1) * 16; 9595 field.bit_mask = 0xffff << field.bit_offset; 9596 9597 reg = rt2800_register_read(rt2x00dev, offset); 9598 rt2x00_set_field32(®, field, queue->txop); 9599 rt2800_register_write(rt2x00dev, offset, reg); 9600 9601 /* Update WMM registers */ 9602 field.bit_offset = queue_idx * 4; 9603 field.bit_mask = 0xf << field.bit_offset; 9604 9605 reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG); 9606 rt2x00_set_field32(®, field, queue->aifs); 9607 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); 9608 9609 reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG); 9610 rt2x00_set_field32(®, field, queue->cw_min); 9611 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); 9612 9613 reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG); 9614 rt2x00_set_field32(®, field, queue->cw_max); 9615 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); 9616 9617 /* Update EDCA registers */ 9618 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); 9619 9620 reg = rt2800_register_read(rt2x00dev, offset); 9621 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); 9622 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); 9623 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); 9624 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); 9625 rt2800_register_write(rt2x00dev, offset, reg); 9626 9627 return 0; 9628 } 9629 EXPORT_SYMBOL_GPL(rt2800_conf_tx); 9630 9631 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 9632 { 9633 struct rt2x00_dev *rt2x00dev = hw->priv; 9634 u64 tsf; 9635 u32 reg; 9636 9637 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1); 9638 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; 9639 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0); 9640 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); 9641 9642 return tsf; 9643 } 9644 EXPORT_SYMBOL_GPL(rt2800_get_tsf); 9645 9646 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 9647 struct ieee80211_ampdu_params *params) 9648 { 9649 struct ieee80211_sta *sta = params->sta; 9650 enum ieee80211_ampdu_mlme_action action = params->action; 9651 u16 tid = params->tid; 9652 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv; 9653 int ret = 0; 9654 9655 /* 9656 * Don't allow aggregation for stations the hardware isn't aware 9657 * of because tx status reports for frames to an unknown station 9658 * always contain wcid=WCID_END+1 and thus we can't distinguish 9659 * between multiple stations which leads to unwanted situations 9660 * when the hw reorders frames due to aggregation. 9661 */ 9662 if (sta_priv->wcid > WCID_END) 9663 return 1; 9664 9665 switch (action) { 9666 case IEEE80211_AMPDU_RX_START: 9667 case IEEE80211_AMPDU_RX_STOP: 9668 /* 9669 * The hw itself takes care of setting up BlockAck mechanisms. 9670 * So, we only have to allow mac80211 to nagotiate a BlockAck 9671 * agreement. Once that is done, the hw will BlockAck incoming 9672 * AMPDUs without further setup. 9673 */ 9674 break; 9675 case IEEE80211_AMPDU_TX_START: 9676 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 9677 break; 9678 case IEEE80211_AMPDU_TX_STOP_CONT: 9679 case IEEE80211_AMPDU_TX_STOP_FLUSH: 9680 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 9681 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 9682 break; 9683 case IEEE80211_AMPDU_TX_OPERATIONAL: 9684 break; 9685 default: 9686 rt2x00_warn((struct rt2x00_dev *)hw->priv, 9687 "Unknown AMPDU action\n"); 9688 } 9689 9690 return ret; 9691 } 9692 EXPORT_SYMBOL_GPL(rt2800_ampdu_action); 9693 9694 int rt2800_get_survey(struct ieee80211_hw *hw, int idx, 9695 struct survey_info *survey) 9696 { 9697 struct rt2x00_dev *rt2x00dev = hw->priv; 9698 struct ieee80211_conf *conf = &hw->conf; 9699 u32 idle, busy, busy_ext; 9700 9701 if (idx != 0) 9702 return -ENOENT; 9703 9704 survey->channel = conf->chandef.chan; 9705 9706 idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 9707 busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 9708 busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 9709 9710 if (idle || busy) { 9711 survey->filled = SURVEY_INFO_TIME | 9712 SURVEY_INFO_TIME_BUSY | 9713 SURVEY_INFO_TIME_EXT_BUSY; 9714 9715 survey->time = (idle + busy) / 1000; 9716 survey->time_busy = busy / 1000; 9717 survey->time_ext_busy = busy_ext / 1000; 9718 } 9719 9720 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 9721 survey->filled |= SURVEY_INFO_IN_USE; 9722 9723 return 0; 9724 9725 } 9726 EXPORT_SYMBOL_GPL(rt2800_get_survey); 9727 9728 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); 9729 MODULE_VERSION(DRV_VERSION); 9730 MODULE_DESCRIPTION("Ralink RT2800 library"); 9731 MODULE_LICENSE("GPL"); 9732