1 /* 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> 6 7 Based on the original rt2800pci.c and rt2800usb.c. 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 14 <http://rt2x00.serialmonkey.com> 15 16 This program is free software; you can redistribute it and/or modify 17 it under the terms of the GNU General Public License as published by 18 the Free Software Foundation; either version 2 of the License, or 19 (at your option) any later version. 20 21 This program is distributed in the hope that it will be useful, 22 but WITHOUT ANY WARRANTY; without even the implied warranty of 23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 GNU General Public License for more details. 25 26 You should have received a copy of the GNU General Public License 27 along with this program; if not, see <http://www.gnu.org/licenses/>. 28 */ 29 30 /* 31 Module: rt2800lib 32 Abstract: rt2800 generic device routines. 33 */ 34 35 #include <linux/crc-ccitt.h> 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/slab.h> 39 40 #include "rt2x00.h" 41 #include "rt2800lib.h" 42 #include "rt2800.h" 43 44 /* 45 * Register access. 46 * All access to the CSR registers will go through the methods 47 * rt2800_register_read and rt2800_register_write. 48 * BBP and RF register require indirect register access, 49 * and use the CSR registers BBPCSR and RFCSR to achieve this. 50 * These indirect registers work with busy bits, 51 * and we will try maximal REGISTER_BUSY_COUNT times to access 52 * the register while taking a REGISTER_BUSY_DELAY us delay 53 * between each attampt. When the busy bit is still set at that time, 54 * the access attempt is considered to have failed, 55 * and we will print an error. 56 * The _lock versions must be used if you already hold the csr_mutex 57 */ 58 #define WAIT_FOR_BBP(__dev, __reg) \ 59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) 60 #define WAIT_FOR_RFCSR(__dev, __reg) \ 61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) 62 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \ 63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \ 64 (__reg)) 65 #define WAIT_FOR_RF(__dev, __reg) \ 66 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) 67 #define WAIT_FOR_MCU(__dev, __reg) \ 68 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 69 H2M_MAILBOX_CSR_OWNER, (__reg)) 70 71 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) 72 { 73 /* check for rt2872 on SoC */ 74 if (!rt2x00_is_soc(rt2x00dev) || 75 !rt2x00_rt(rt2x00dev, RT2872)) 76 return false; 77 78 /* we know for sure that these rf chipsets are used on rt305x boards */ 79 if (rt2x00_rf(rt2x00dev, RF3020) || 80 rt2x00_rf(rt2x00dev, RF3021) || 81 rt2x00_rf(rt2x00dev, RF3022)) 82 return true; 83 84 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n"); 85 return false; 86 } 87 88 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, 89 const unsigned int word, const u8 value) 90 { 91 u32 reg; 92 93 mutex_lock(&rt2x00dev->csr_mutex); 94 95 /* 96 * Wait until the BBP becomes available, afterwards we 97 * can safely write the new data into the register. 98 */ 99 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 100 reg = 0; 101 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); 102 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 103 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 104 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); 105 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 106 107 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 108 } 109 110 mutex_unlock(&rt2x00dev->csr_mutex); 111 } 112 113 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word) 114 { 115 u32 reg; 116 u8 value; 117 118 mutex_lock(&rt2x00dev->csr_mutex); 119 120 /* 121 * Wait until the BBP becomes available, afterwards we 122 * can safely write the read request into the register. 123 * After the data has been written, we wait until hardware 124 * returns the correct value, if at any time the register 125 * doesn't become available in time, reg will be 0xffffffff 126 * which means we return 0xff to the caller. 127 */ 128 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 129 reg = 0; 130 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 131 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 132 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); 133 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 134 135 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 136 137 WAIT_FOR_BBP(rt2x00dev, ®); 138 } 139 140 value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); 141 142 mutex_unlock(&rt2x00dev->csr_mutex); 143 144 return value; 145 } 146 147 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, 148 const unsigned int word, const u8 value) 149 { 150 u32 reg; 151 152 mutex_lock(&rt2x00dev->csr_mutex); 153 154 /* 155 * Wait until the RFCSR becomes available, afterwards we 156 * can safely write the new data into the register. 157 */ 158 switch (rt2x00dev->chip.rt) { 159 case RT6352: 160 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 161 reg = 0; 162 rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value); 163 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 164 word); 165 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1); 166 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 167 168 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 169 } 170 break; 171 172 default: 173 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 174 reg = 0; 175 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); 176 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 177 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); 178 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 179 180 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 181 } 182 break; 183 } 184 185 mutex_unlock(&rt2x00dev->csr_mutex); 186 } 187 188 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 189 const unsigned int reg, const u8 value) 190 { 191 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value); 192 } 193 194 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev, 195 const unsigned int reg, const u8 value) 196 { 197 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value); 198 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value); 199 } 200 201 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev, 202 const unsigned int reg, const u8 value) 203 { 204 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value); 205 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value); 206 } 207 208 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, 209 const unsigned int word) 210 { 211 u32 reg; 212 u8 value; 213 214 mutex_lock(&rt2x00dev->csr_mutex); 215 216 /* 217 * Wait until the RFCSR becomes available, afterwards we 218 * can safely write the read request into the register. 219 * After the data has been written, we wait until hardware 220 * returns the correct value, if at any time the register 221 * doesn't become available in time, reg will be 0xffffffff 222 * which means we return 0xff to the caller. 223 */ 224 switch (rt2x00dev->chip.rt) { 225 case RT6352: 226 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 227 reg = 0; 228 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 229 word); 230 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0); 231 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 232 233 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 234 235 WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®); 236 } 237 238 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620); 239 break; 240 241 default: 242 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 243 reg = 0; 244 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 245 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); 246 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 247 248 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 249 250 WAIT_FOR_RFCSR(rt2x00dev, ®); 251 } 252 253 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); 254 break; 255 } 256 257 mutex_unlock(&rt2x00dev->csr_mutex); 258 259 return value; 260 } 261 262 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 263 const unsigned int reg) 264 { 265 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6))); 266 } 267 268 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, 269 const unsigned int word, const u32 value) 270 { 271 u32 reg; 272 273 mutex_lock(&rt2x00dev->csr_mutex); 274 275 /* 276 * Wait until the RF becomes available, afterwards we 277 * can safely write the new data into the register. 278 */ 279 if (WAIT_FOR_RF(rt2x00dev, ®)) { 280 reg = 0; 281 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); 282 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); 283 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); 284 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); 285 286 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); 287 rt2x00_rf_write(rt2x00dev, word, value); 288 } 289 290 mutex_unlock(&rt2x00dev->csr_mutex); 291 } 292 293 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { 294 [EEPROM_CHIP_ID] = 0x0000, 295 [EEPROM_VERSION] = 0x0001, 296 [EEPROM_MAC_ADDR_0] = 0x0002, 297 [EEPROM_MAC_ADDR_1] = 0x0003, 298 [EEPROM_MAC_ADDR_2] = 0x0004, 299 [EEPROM_NIC_CONF0] = 0x001a, 300 [EEPROM_NIC_CONF1] = 0x001b, 301 [EEPROM_FREQ] = 0x001d, 302 [EEPROM_LED_AG_CONF] = 0x001e, 303 [EEPROM_LED_ACT_CONF] = 0x001f, 304 [EEPROM_LED_POLARITY] = 0x0020, 305 [EEPROM_NIC_CONF2] = 0x0021, 306 [EEPROM_LNA] = 0x0022, 307 [EEPROM_RSSI_BG] = 0x0023, 308 [EEPROM_RSSI_BG2] = 0x0024, 309 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */ 310 [EEPROM_RSSI_A] = 0x0025, 311 [EEPROM_RSSI_A2] = 0x0026, 312 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */ 313 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027, 314 [EEPROM_TXPOWER_DELTA] = 0x0028, 315 [EEPROM_TXPOWER_BG1] = 0x0029, 316 [EEPROM_TXPOWER_BG2] = 0x0030, 317 [EEPROM_TSSI_BOUND_BG1] = 0x0037, 318 [EEPROM_TSSI_BOUND_BG2] = 0x0038, 319 [EEPROM_TSSI_BOUND_BG3] = 0x0039, 320 [EEPROM_TSSI_BOUND_BG4] = 0x003a, 321 [EEPROM_TSSI_BOUND_BG5] = 0x003b, 322 [EEPROM_TXPOWER_A1] = 0x003c, 323 [EEPROM_TXPOWER_A2] = 0x0053, 324 [EEPROM_TXPOWER_INIT] = 0x0068, 325 [EEPROM_TSSI_BOUND_A1] = 0x006a, 326 [EEPROM_TSSI_BOUND_A2] = 0x006b, 327 [EEPROM_TSSI_BOUND_A3] = 0x006c, 328 [EEPROM_TSSI_BOUND_A4] = 0x006d, 329 [EEPROM_TSSI_BOUND_A5] = 0x006e, 330 [EEPROM_TXPOWER_BYRATE] = 0x006f, 331 [EEPROM_BBP_START] = 0x0078, 332 }; 333 334 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = { 335 [EEPROM_CHIP_ID] = 0x0000, 336 [EEPROM_VERSION] = 0x0001, 337 [EEPROM_MAC_ADDR_0] = 0x0002, 338 [EEPROM_MAC_ADDR_1] = 0x0003, 339 [EEPROM_MAC_ADDR_2] = 0x0004, 340 [EEPROM_NIC_CONF0] = 0x001a, 341 [EEPROM_NIC_CONF1] = 0x001b, 342 [EEPROM_NIC_CONF2] = 0x001c, 343 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020, 344 [EEPROM_FREQ] = 0x0022, 345 [EEPROM_LED_AG_CONF] = 0x0023, 346 [EEPROM_LED_ACT_CONF] = 0x0024, 347 [EEPROM_LED_POLARITY] = 0x0025, 348 [EEPROM_LNA] = 0x0026, 349 [EEPROM_EXT_LNA2] = 0x0027, 350 [EEPROM_RSSI_BG] = 0x0028, 351 [EEPROM_RSSI_BG2] = 0x0029, 352 [EEPROM_RSSI_A] = 0x002a, 353 [EEPROM_RSSI_A2] = 0x002b, 354 [EEPROM_TXPOWER_BG1] = 0x0030, 355 [EEPROM_TXPOWER_BG2] = 0x0037, 356 [EEPROM_EXT_TXPOWER_BG3] = 0x003e, 357 [EEPROM_TSSI_BOUND_BG1] = 0x0045, 358 [EEPROM_TSSI_BOUND_BG2] = 0x0046, 359 [EEPROM_TSSI_BOUND_BG3] = 0x0047, 360 [EEPROM_TSSI_BOUND_BG4] = 0x0048, 361 [EEPROM_TSSI_BOUND_BG5] = 0x0049, 362 [EEPROM_TXPOWER_A1] = 0x004b, 363 [EEPROM_TXPOWER_A2] = 0x0065, 364 [EEPROM_EXT_TXPOWER_A3] = 0x007f, 365 [EEPROM_TSSI_BOUND_A1] = 0x009a, 366 [EEPROM_TSSI_BOUND_A2] = 0x009b, 367 [EEPROM_TSSI_BOUND_A3] = 0x009c, 368 [EEPROM_TSSI_BOUND_A4] = 0x009d, 369 [EEPROM_TSSI_BOUND_A5] = 0x009e, 370 [EEPROM_TXPOWER_BYRATE] = 0x00a0, 371 }; 372 373 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev, 374 const enum rt2800_eeprom_word word) 375 { 376 const unsigned int *map; 377 unsigned int index; 378 379 if (WARN_ONCE(word >= EEPROM_WORD_COUNT, 380 "%s: invalid EEPROM word %d\n", 381 wiphy_name(rt2x00dev->hw->wiphy), word)) 382 return 0; 383 384 if (rt2x00_rt(rt2x00dev, RT3593)) 385 map = rt2800_eeprom_map_ext; 386 else 387 map = rt2800_eeprom_map; 388 389 index = map[word]; 390 391 /* Index 0 is valid only for EEPROM_CHIP_ID. 392 * Otherwise it means that the offset of the 393 * given word is not initialized in the map, 394 * or that the field is not usable on the 395 * actual chipset. 396 */ 397 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0, 398 "%s: invalid access of EEPROM word %d\n", 399 wiphy_name(rt2x00dev->hw->wiphy), word); 400 401 return index; 402 } 403 404 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev, 405 const enum rt2800_eeprom_word word) 406 { 407 unsigned int index; 408 409 index = rt2800_eeprom_word_index(rt2x00dev, word); 410 return rt2x00_eeprom_addr(rt2x00dev, index); 411 } 412 413 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, 414 const enum rt2800_eeprom_word word) 415 { 416 unsigned int index; 417 418 index = rt2800_eeprom_word_index(rt2x00dev, word); 419 return rt2x00_eeprom_read(rt2x00dev, index); 420 } 421 422 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, 423 const enum rt2800_eeprom_word word, u16 data) 424 { 425 unsigned int index; 426 427 index = rt2800_eeprom_word_index(rt2x00dev, word); 428 rt2x00_eeprom_write(rt2x00dev, index, data); 429 } 430 431 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, 432 const enum rt2800_eeprom_word array, 433 unsigned int offset) 434 { 435 unsigned int index; 436 437 index = rt2800_eeprom_word_index(rt2x00dev, array); 438 return rt2x00_eeprom_read(rt2x00dev, index + offset); 439 } 440 441 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) 442 { 443 u32 reg; 444 int i, count; 445 446 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 447 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); 448 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); 449 rt2x00_set_field32(®, WLAN_CLK_EN, 0); 450 rt2x00_set_field32(®, WLAN_EN, 1); 451 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 452 453 udelay(REGISTER_BUSY_DELAY); 454 455 count = 0; 456 do { 457 /* 458 * Check PLL_LD & XTAL_RDY. 459 */ 460 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 461 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 462 if (rt2x00_get_field32(reg, PLL_LD) && 463 rt2x00_get_field32(reg, XTAL_RDY)) 464 break; 465 udelay(REGISTER_BUSY_DELAY); 466 } 467 468 if (i >= REGISTER_BUSY_COUNT) { 469 470 if (count >= 10) 471 return -EIO; 472 473 rt2800_register_write(rt2x00dev, 0x58, 0x018); 474 udelay(REGISTER_BUSY_DELAY); 475 rt2800_register_write(rt2x00dev, 0x58, 0x418); 476 udelay(REGISTER_BUSY_DELAY); 477 rt2800_register_write(rt2x00dev, 0x58, 0x618); 478 udelay(REGISTER_BUSY_DELAY); 479 count++; 480 } else { 481 count = 0; 482 } 483 484 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 485 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); 486 rt2x00_set_field32(®, WLAN_CLK_EN, 1); 487 rt2x00_set_field32(®, WLAN_RESET, 1); 488 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 489 udelay(10); 490 rt2x00_set_field32(®, WLAN_RESET, 0); 491 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 492 udelay(10); 493 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff); 494 } while (count != 0); 495 496 return 0; 497 } 498 499 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 500 const u8 command, const u8 token, 501 const u8 arg0, const u8 arg1) 502 { 503 u32 reg; 504 505 /* 506 * SOC devices don't support MCU requests. 507 */ 508 if (rt2x00_is_soc(rt2x00dev)) 509 return; 510 511 mutex_lock(&rt2x00dev->csr_mutex); 512 513 /* 514 * Wait until the MCU becomes available, afterwards we 515 * can safely write the new data into the register. 516 */ 517 if (WAIT_FOR_MCU(rt2x00dev, ®)) { 518 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); 519 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); 520 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); 521 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); 522 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); 523 524 reg = 0; 525 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); 526 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); 527 } 528 529 mutex_unlock(&rt2x00dev->csr_mutex); 530 } 531 EXPORT_SYMBOL_GPL(rt2800_mcu_request); 532 533 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) 534 { 535 unsigned int i = 0; 536 u32 reg; 537 538 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 539 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 540 if (reg && reg != ~0) 541 return 0; 542 msleep(1); 543 } 544 545 rt2x00_err(rt2x00dev, "Unstable hardware\n"); 546 return -EBUSY; 547 } 548 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); 549 550 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 551 { 552 unsigned int i; 553 u32 reg; 554 555 /* 556 * Some devices are really slow to respond here. Wait a whole second 557 * before timing out. 558 */ 559 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 560 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 561 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 562 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 563 return 0; 564 565 msleep(10); 566 } 567 568 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); 569 return -EACCES; 570 } 571 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); 572 573 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) 574 { 575 u32 reg; 576 577 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 578 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 579 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 580 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 581 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 582 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 583 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 584 } 585 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma); 586 587 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev, 588 unsigned short *txwi_size, 589 unsigned short *rxwi_size) 590 { 591 switch (rt2x00dev->chip.rt) { 592 case RT3593: 593 *txwi_size = TXWI_DESC_SIZE_4WORDS; 594 *rxwi_size = RXWI_DESC_SIZE_5WORDS; 595 break; 596 597 case RT5592: 598 case RT6352: 599 *txwi_size = TXWI_DESC_SIZE_5WORDS; 600 *rxwi_size = RXWI_DESC_SIZE_6WORDS; 601 break; 602 603 default: 604 *txwi_size = TXWI_DESC_SIZE_4WORDS; 605 *rxwi_size = RXWI_DESC_SIZE_4WORDS; 606 break; 607 } 608 } 609 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size); 610 611 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) 612 { 613 u16 fw_crc; 614 u16 crc; 615 616 /* 617 * The last 2 bytes in the firmware array are the crc checksum itself, 618 * this means that we should never pass those 2 bytes to the crc 619 * algorithm. 620 */ 621 fw_crc = (data[len - 2] << 8 | data[len - 1]); 622 623 /* 624 * Use the crc ccitt algorithm. 625 * This will return the same value as the legacy driver which 626 * used bit ordering reversion on the both the firmware bytes 627 * before input input as well as on the final output. 628 * Obviously using crc ccitt directly is much more efficient. 629 */ 630 crc = crc_ccitt(~0, data, len - 2); 631 632 /* 633 * There is a small difference between the crc-itu-t + bitrev and 634 * the crc-ccitt crc calculation. In the latter method the 2 bytes 635 * will be swapped, use swab16 to convert the crc to the correct 636 * value. 637 */ 638 crc = swab16(crc); 639 640 return fw_crc == crc; 641 } 642 643 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, 644 const u8 *data, const size_t len) 645 { 646 size_t offset = 0; 647 size_t fw_len; 648 bool multiple; 649 650 /* 651 * PCI(e) & SOC devices require firmware with a length 652 * of 8kb. USB devices require firmware files with a length 653 * of 4kb. Certain USB chipsets however require different firmware, 654 * which Ralink only provides attached to the original firmware 655 * file. Thus for USB devices, firmware files have a length 656 * which is a multiple of 4kb. The firmware for rt3290 chip also 657 * have a length which is a multiple of 4kb. 658 */ 659 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290)) 660 fw_len = 4096; 661 else 662 fw_len = 8192; 663 664 multiple = true; 665 /* 666 * Validate the firmware length 667 */ 668 if (len != fw_len && (!multiple || (len % fw_len) != 0)) 669 return FW_BAD_LENGTH; 670 671 /* 672 * Check if the chipset requires one of the upper parts 673 * of the firmware. 674 */ 675 if (rt2x00_is_usb(rt2x00dev) && 676 !rt2x00_rt(rt2x00dev, RT2860) && 677 !rt2x00_rt(rt2x00dev, RT2872) && 678 !rt2x00_rt(rt2x00dev, RT3070) && 679 ((len / fw_len) == 1)) 680 return FW_BAD_VERSION; 681 682 /* 683 * 8kb firmware files must be checked as if it were 684 * 2 separate firmware files. 685 */ 686 while (offset < len) { 687 if (!rt2800_check_firmware_crc(data + offset, fw_len)) 688 return FW_BAD_CRC; 689 690 offset += fw_len; 691 } 692 693 return FW_OK; 694 } 695 EXPORT_SYMBOL_GPL(rt2800_check_firmware); 696 697 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, 698 const u8 *data, const size_t len) 699 { 700 unsigned int i; 701 u32 reg; 702 int retval; 703 704 if (rt2x00_rt(rt2x00dev, RT3290)) { 705 retval = rt2800_enable_wlan_rt3290(rt2x00dev); 706 if (retval) 707 return -EBUSY; 708 } 709 710 /* 711 * If driver doesn't wake up firmware here, 712 * rt2800_load_firmware will hang forever when interface is up again. 713 */ 714 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 715 716 /* 717 * Wait for stable hardware. 718 */ 719 if (rt2800_wait_csr_ready(rt2x00dev)) 720 return -EBUSY; 721 722 if (rt2x00_is_pci(rt2x00dev)) { 723 if (rt2x00_rt(rt2x00dev, RT3290) || 724 rt2x00_rt(rt2x00dev, RT3572) || 725 rt2x00_rt(rt2x00dev, RT5390) || 726 rt2x00_rt(rt2x00dev, RT5392)) { 727 reg = rt2800_register_read(rt2x00dev, AUX_CTRL); 728 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); 729 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); 730 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); 731 } 732 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 733 } 734 735 rt2800_disable_wpdma(rt2x00dev); 736 737 /* 738 * Write firmware to the device. 739 */ 740 rt2800_drv_write_firmware(rt2x00dev, data, len); 741 742 /* 743 * Wait for device to stabilize. 744 */ 745 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 746 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL); 747 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 748 break; 749 msleep(1); 750 } 751 752 if (i == REGISTER_BUSY_COUNT) { 753 rt2x00_err(rt2x00dev, "PBF system register not ready\n"); 754 return -EBUSY; 755 } 756 757 /* 758 * Disable DMA, will be reenabled later when enabling 759 * the radio. 760 */ 761 rt2800_disable_wpdma(rt2x00dev); 762 763 /* 764 * Initialize firmware. 765 */ 766 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 767 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 768 if (rt2x00_is_usb(rt2x00dev)) { 769 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 770 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 771 } 772 msleep(1); 773 774 return 0; 775 } 776 EXPORT_SYMBOL_GPL(rt2800_load_firmware); 777 778 void rt2800_write_tx_data(struct queue_entry *entry, 779 struct txentry_desc *txdesc) 780 { 781 __le32 *txwi = rt2800_drv_get_txwi(entry); 782 u32 word; 783 int i; 784 785 /* 786 * Initialize TX Info descriptor 787 */ 788 word = rt2x00_desc_read(txwi, 0); 789 rt2x00_set_field32(&word, TXWI_W0_FRAG, 790 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 791 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 792 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); 793 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); 794 rt2x00_set_field32(&word, TXWI_W0_TS, 795 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 796 rt2x00_set_field32(&word, TXWI_W0_AMPDU, 797 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); 798 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, 799 txdesc->u.ht.mpdu_density); 800 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); 801 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); 802 rt2x00_set_field32(&word, TXWI_W0_BW, 803 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); 804 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, 805 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); 806 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); 807 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); 808 rt2x00_desc_write(txwi, 0, word); 809 810 word = rt2x00_desc_read(txwi, 1); 811 rt2x00_set_field32(&word, TXWI_W1_ACK, 812 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 813 rt2x00_set_field32(&word, TXWI_W1_NSEQ, 814 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 815 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); 816 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 817 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 818 txdesc->key_idx : txdesc->u.ht.wcid); 819 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 820 txdesc->length); 821 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); 822 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); 823 rt2x00_desc_write(txwi, 1, word); 824 825 /* 826 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert 827 * the IV from the IVEIV register when TXD_W3_WIV is set to 0. 828 * When TXD_W3_WIV is set to 1 it will use the IV data 829 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 830 * crypto entry in the registers should be used to encrypt the frame. 831 * 832 * Nulify all remaining words as well, we don't know how to program them. 833 */ 834 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++) 835 _rt2x00_desc_write(txwi, i, 0); 836 } 837 EXPORT_SYMBOL_GPL(rt2800_write_tx_data); 838 839 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) 840 { 841 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); 842 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); 843 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); 844 u16 eeprom; 845 u8 offset0; 846 u8 offset1; 847 u8 offset2; 848 849 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 850 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 851 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); 852 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); 853 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 854 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); 855 } else { 856 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 857 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); 858 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); 859 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 860 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); 861 } 862 863 /* 864 * Convert the value from the descriptor into the RSSI value 865 * If the value in the descriptor is 0, it is considered invalid 866 * and the default (extremely low) rssi value is assumed 867 */ 868 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128; 869 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128; 870 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128; 871 872 /* 873 * mac80211 only accepts a single RSSI value. Calculating the 874 * average doesn't deliver a fair answer either since -60:-60 would 875 * be considered equally good as -50:-70 while the second is the one 876 * which gives less energy... 877 */ 878 rssi0 = max(rssi0, rssi1); 879 return (int)max(rssi0, rssi2); 880 } 881 882 void rt2800_process_rxwi(struct queue_entry *entry, 883 struct rxdone_entry_desc *rxdesc) 884 { 885 __le32 *rxwi = (__le32 *) entry->skb->data; 886 u32 word; 887 888 word = rt2x00_desc_read(rxwi, 0); 889 890 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); 891 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); 892 893 word = rt2x00_desc_read(rxwi, 1); 894 895 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) 896 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI; 897 898 if (rt2x00_get_field32(word, RXWI_W1_BW)) 899 rxdesc->bw = RATE_INFO_BW_40; 900 901 /* 902 * Detect RX rate, always use MCS as signal type. 903 */ 904 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; 905 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); 906 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); 907 908 /* 909 * Mask of 0x8 bit to remove the short preamble flag. 910 */ 911 if (rxdesc->rate_mode == RATE_MODE_CCK) 912 rxdesc->signal &= ~0x8; 913 914 word = rt2x00_desc_read(rxwi, 2); 915 916 /* 917 * Convert descriptor AGC value to RSSI value. 918 */ 919 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); 920 /* 921 * Remove RXWI descriptor from start of the buffer. 922 */ 923 skb_pull(entry->skb, entry->queue->winfo_size); 924 } 925 EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 926 927 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc, 928 u32 status, enum nl80211_band band) 929 { 930 u8 flags = 0; 931 u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 932 933 switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) { 934 case RATE_MODE_HT_GREENFIELD: 935 flags |= IEEE80211_TX_RC_GREEN_FIELD; 936 /* fall through */ 937 case RATE_MODE_HT_MIX: 938 flags |= IEEE80211_TX_RC_MCS; 939 break; 940 case RATE_MODE_OFDM: 941 if (band == NL80211_BAND_2GHZ) 942 idx += 4; 943 break; 944 case RATE_MODE_CCK: 945 if (idx >= 8) 946 idx -= 8; 947 break; 948 } 949 950 if (rt2x00_get_field32(status, TX_STA_FIFO_BW)) 951 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 952 953 if (rt2x00_get_field32(status, TX_STA_FIFO_SGI)) 954 flags |= IEEE80211_TX_RC_SHORT_GI; 955 956 skbdesc->tx_rate_idx = idx; 957 skbdesc->tx_rate_flags = flags; 958 } 959 960 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg) 961 { 962 __le32 *txwi; 963 u32 word; 964 int wcid, ack, pid; 965 int tx_wcid, tx_ack, tx_pid, is_agg; 966 967 /* 968 * This frames has returned with an IO error, 969 * so the status report is not intended for this 970 * frame. 971 */ 972 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) 973 return false; 974 975 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID); 976 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED); 977 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE); 978 is_agg = rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE); 979 980 /* 981 * Validate if this TX status report is intended for 982 * this entry by comparing the WCID/ACK/PID fields. 983 */ 984 txwi = rt2800_drv_get_txwi(entry); 985 986 word = rt2x00_desc_read(txwi, 1); 987 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID); 988 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK); 989 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID); 990 991 if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) { 992 rt2x00_dbg(entry->queue->rt2x00dev, 993 "TX status report missed for queue %d entry %d\n", 994 entry->queue->qid, entry->entry_idx); 995 return false; 996 } 997 998 return true; 999 } 1000 1001 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi, 1002 bool match) 1003 { 1004 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1005 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1006 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1007 struct txdone_entry_desc txdesc; 1008 u32 word; 1009 u16 mcs, real_mcs; 1010 int aggr, ampdu, wcid, ack_req; 1011 1012 /* 1013 * Obtain the status about this packet. 1014 */ 1015 txdesc.flags = 0; 1016 word = rt2x00_desc_read(txwi, 0); 1017 1018 mcs = rt2x00_get_field32(word, TXWI_W0_MCS); 1019 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); 1020 1021 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 1022 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); 1023 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID); 1024 ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED); 1025 1026 /* 1027 * If a frame was meant to be sent as a single non-aggregated MPDU 1028 * but ended up in an aggregate the used tx rate doesn't correlate 1029 * with the one specified in the TXWI as the whole aggregate is sent 1030 * with the same rate. 1031 * 1032 * For example: two frames are sent to rt2x00, the first one sets 1033 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 1034 * and requests MCS15. If the hw aggregates both frames into one 1035 * AMDPU the tx status for both frames will contain MCS7 although 1036 * the frame was sent successfully. 1037 * 1038 * Hence, replace the requested rate with the real tx rate to not 1039 * confuse the rate control algortihm by providing clearly wrong 1040 * data. 1041 * 1042 * FIXME: if we do not find matching entry, we tell that frame was 1043 * posted without any retries. We need to find a way to fix that 1044 * and provide retry count. 1045 */ 1046 if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) { 1047 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band); 1048 mcs = real_mcs; 1049 } 1050 1051 if (aggr == 1 || ampdu == 1) 1052 __set_bit(TXDONE_AMPDU, &txdesc.flags); 1053 1054 if (!ack_req) 1055 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags); 1056 1057 /* 1058 * Ralink has a retry mechanism using a global fallback 1059 * table. We setup this fallback table to try the immediate 1060 * lower rate for all rates. In the TX_STA_FIFO, the MCS field 1061 * always contains the MCS used for the last transmission, be 1062 * it successful or not. 1063 */ 1064 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { 1065 /* 1066 * Transmission succeeded. The number of retries is 1067 * mcs - real_mcs 1068 */ 1069 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 1070 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); 1071 } else { 1072 /* 1073 * Transmission failed. The number of retries is 1074 * always 7 in this case (for a total number of 8 1075 * frames sent). 1076 */ 1077 __set_bit(TXDONE_FAILURE, &txdesc.flags); 1078 txdesc.retry = rt2x00dev->long_retry; 1079 } 1080 1081 /* 1082 * the frame was retried at least once 1083 * -> hw used fallback rates 1084 */ 1085 if (txdesc.retry) 1086 __set_bit(TXDONE_FALLBACK, &txdesc.flags); 1087 1088 if (!match) { 1089 /* RCU assures non-null sta will not be freed by mac80211. */ 1090 rcu_read_lock(); 1091 if (likely(wcid >= WCID_START && wcid <= WCID_END)) 1092 skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START]; 1093 else 1094 skbdesc->sta = NULL; 1095 rt2x00lib_txdone_nomatch(entry, &txdesc); 1096 rcu_read_unlock(); 1097 } else { 1098 rt2x00lib_txdone(entry, &txdesc); 1099 } 1100 } 1101 EXPORT_SYMBOL_GPL(rt2800_txdone_entry); 1102 1103 void rt2800_txdone(struct rt2x00_dev *rt2x00dev) 1104 { 1105 struct data_queue *queue; 1106 struct queue_entry *entry; 1107 u32 reg; 1108 u8 qid; 1109 bool match; 1110 1111 while (kfifo_get(&rt2x00dev->txstatus_fifo, ®)) { 1112 /* 1113 * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is 1114 * guaranteed to be one of the TX QIDs . 1115 */ 1116 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE); 1117 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid); 1118 1119 if (unlikely(rt2x00queue_empty(queue))) { 1120 rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n", 1121 qid); 1122 break; 1123 } 1124 1125 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1126 1127 if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1128 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) { 1129 rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n", 1130 entry->entry_idx, qid); 1131 break; 1132 } 1133 1134 match = rt2800_txdone_entry_check(entry, reg); 1135 rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match); 1136 } 1137 } 1138 EXPORT_SYMBOL_GPL(rt2800_txdone); 1139 1140 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev, 1141 struct queue_entry *entry) 1142 { 1143 bool ret; 1144 unsigned long tout; 1145 1146 if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1147 return false; 1148 1149 if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags)) 1150 tout = msecs_to_jiffies(50); 1151 else 1152 tout = msecs_to_jiffies(2000); 1153 1154 ret = time_after(jiffies, entry->last_action + tout); 1155 if (unlikely(ret)) 1156 rt2x00_dbg(entry->queue->rt2x00dev, 1157 "TX status timeout for entry %d in queue %d\n", 1158 entry->entry_idx, entry->queue->qid); 1159 return ret; 1160 } 1161 1162 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev) 1163 { 1164 struct data_queue *queue; 1165 struct queue_entry *entry; 1166 1167 if (!test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags)) { 1168 unsigned long tout = msecs_to_jiffies(1000); 1169 1170 if (time_before(jiffies, rt2x00dev->last_nostatus_check + tout)) 1171 return false; 1172 } 1173 1174 rt2x00dev->last_nostatus_check = jiffies; 1175 1176 tx_queue_for_each(rt2x00dev, queue) { 1177 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1178 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1179 return true; 1180 } 1181 1182 return false; 1183 } 1184 EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout); 1185 1186 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev) 1187 { 1188 struct data_queue *queue; 1189 struct queue_entry *entry; 1190 1191 /* 1192 * Process any trailing TX status reports for IO failures, 1193 * we loop until we find the first non-IO error entry. This 1194 * can either be a frame which is free, is being uploaded, 1195 * or has completed the upload but didn't have an entry 1196 * in the TX_STAT_FIFO register yet. 1197 */ 1198 tx_queue_for_each(rt2x00dev, queue) { 1199 while (!rt2x00queue_empty(queue)) { 1200 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1201 1202 if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1203 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1204 break; 1205 1206 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) || 1207 rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1208 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE); 1209 else 1210 break; 1211 } 1212 } 1213 } 1214 EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus); 1215 1216 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev, 1217 unsigned int index) 1218 { 1219 return HW_BEACON_BASE(index); 1220 } 1221 1222 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev, 1223 unsigned int index) 1224 { 1225 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index)); 1226 } 1227 1228 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev) 1229 { 1230 struct data_queue *queue = rt2x00dev->bcn; 1231 struct queue_entry *entry; 1232 int i, bcn_num = 0; 1233 u64 off, reg = 0; 1234 u32 bssid_dw1; 1235 1236 /* 1237 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers. 1238 */ 1239 for (i = 0; i < queue->limit; i++) { 1240 entry = &queue->entries[i]; 1241 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags)) 1242 continue; 1243 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx); 1244 reg |= off << (8 * bcn_num); 1245 bcn_num++; 1246 } 1247 1248 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); 1249 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); 1250 1251 /* 1252 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons. 1253 */ 1254 bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1); 1255 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, 1256 bcn_num > 0 ? bcn_num - 1 : 0); 1257 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1); 1258 } 1259 1260 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) 1261 { 1262 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1263 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1264 unsigned int beacon_base; 1265 unsigned int padding_len; 1266 u32 orig_reg, reg; 1267 const int txwi_desc_size = entry->queue->winfo_size; 1268 1269 /* 1270 * Disable beaconing while we are reloading the beacon data, 1271 * otherwise we might be sending out invalid data. 1272 */ 1273 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1274 orig_reg = reg; 1275 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1276 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1277 1278 /* 1279 * Add space for the TXWI in front of the skb. 1280 */ 1281 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size); 1282 1283 /* 1284 * Register descriptor details in skb frame descriptor. 1285 */ 1286 skbdesc->flags |= SKBDESC_DESC_IN_SKB; 1287 skbdesc->desc = entry->skb->data; 1288 skbdesc->desc_len = txwi_desc_size; 1289 1290 /* 1291 * Add the TXWI for the beacon to the skb. 1292 */ 1293 rt2800_write_tx_data(entry, txdesc); 1294 1295 /* 1296 * Dump beacon to userspace through debugfs. 1297 */ 1298 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); 1299 1300 /* 1301 * Write entire beacon with TXWI and padding to register. 1302 */ 1303 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 1304 if (padding_len && skb_pad(entry->skb, padding_len)) { 1305 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); 1306 /* skb freed by skb_pad() on failure */ 1307 entry->skb = NULL; 1308 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1309 return; 1310 } 1311 1312 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx); 1313 1314 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, 1315 entry->skb->len + padding_len); 1316 __set_bit(ENTRY_BCN_ENABLED, &entry->flags); 1317 1318 /* 1319 * Change global beacons settings. 1320 */ 1321 rt2800_update_beacons_setup(rt2x00dev); 1322 1323 /* 1324 * Restore beaconing state. 1325 */ 1326 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1327 1328 /* 1329 * Clean up beacon skb. 1330 */ 1331 dev_kfree_skb_any(entry->skb); 1332 entry->skb = NULL; 1333 } 1334 EXPORT_SYMBOL_GPL(rt2800_write_beacon); 1335 1336 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, 1337 unsigned int index) 1338 { 1339 int i; 1340 const int txwi_desc_size = rt2x00dev->bcn->winfo_size; 1341 unsigned int beacon_base; 1342 1343 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index); 1344 1345 /* 1346 * For the Beacon base registers we only need to clear 1347 * the whole TXWI which (when set to 0) will invalidate 1348 * the entire beacon. 1349 */ 1350 for (i = 0; i < txwi_desc_size; i += sizeof(__le32)) 1351 rt2800_register_write(rt2x00dev, beacon_base + i, 0); 1352 } 1353 1354 void rt2800_clear_beacon(struct queue_entry *entry) 1355 { 1356 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1357 u32 orig_reg, reg; 1358 1359 /* 1360 * Disable beaconing while we are reloading the beacon data, 1361 * otherwise we might be sending out invalid data. 1362 */ 1363 orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1364 reg = orig_reg; 1365 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1366 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1367 1368 /* 1369 * Clear beacon. 1370 */ 1371 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx); 1372 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags); 1373 1374 /* 1375 * Change global beacons settings. 1376 */ 1377 rt2800_update_beacons_setup(rt2x00dev); 1378 /* 1379 * Restore beaconing state. 1380 */ 1381 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1382 } 1383 EXPORT_SYMBOL_GPL(rt2800_clear_beacon); 1384 1385 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 1386 const struct rt2x00debug rt2800_rt2x00debug = { 1387 .owner = THIS_MODULE, 1388 .csr = { 1389 .read = rt2800_register_read, 1390 .write = rt2800_register_write, 1391 .flags = RT2X00DEBUGFS_OFFSET, 1392 .word_base = CSR_REG_BASE, 1393 .word_size = sizeof(u32), 1394 .word_count = CSR_REG_SIZE / sizeof(u32), 1395 }, 1396 .eeprom = { 1397 /* NOTE: The local EEPROM access functions can't 1398 * be used here, use the generic versions instead. 1399 */ 1400 .read = rt2x00_eeprom_read, 1401 .write = rt2x00_eeprom_write, 1402 .word_base = EEPROM_BASE, 1403 .word_size = sizeof(u16), 1404 .word_count = EEPROM_SIZE / sizeof(u16), 1405 }, 1406 .bbp = { 1407 .read = rt2800_bbp_read, 1408 .write = rt2800_bbp_write, 1409 .word_base = BBP_BASE, 1410 .word_size = sizeof(u8), 1411 .word_count = BBP_SIZE / sizeof(u8), 1412 }, 1413 .rf = { 1414 .read = rt2x00_rf_read, 1415 .write = rt2800_rf_write, 1416 .word_base = RF_BASE, 1417 .word_size = sizeof(u32), 1418 .word_count = RF_SIZE / sizeof(u32), 1419 }, 1420 .rfcsr = { 1421 .read = rt2800_rfcsr_read, 1422 .write = rt2800_rfcsr_write, 1423 .word_base = RFCSR_BASE, 1424 .word_size = sizeof(u8), 1425 .word_count = RFCSR_SIZE / sizeof(u8), 1426 }, 1427 }; 1428 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); 1429 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1430 1431 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) 1432 { 1433 u32 reg; 1434 1435 if (rt2x00_rt(rt2x00dev, RT3290)) { 1436 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 1437 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); 1438 } else { 1439 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 1440 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); 1441 } 1442 } 1443 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 1444 1445 #ifdef CONFIG_RT2X00_LIB_LEDS 1446 static void rt2800_brightness_set(struct led_classdev *led_cdev, 1447 enum led_brightness brightness) 1448 { 1449 struct rt2x00_led *led = 1450 container_of(led_cdev, struct rt2x00_led, led_dev); 1451 unsigned int enabled = brightness != LED_OFF; 1452 unsigned int bg_mode = 1453 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); 1454 unsigned int polarity = 1455 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1456 EEPROM_FREQ_LED_POLARITY); 1457 unsigned int ledmode = 1458 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1459 EEPROM_FREQ_LED_MODE); 1460 u32 reg; 1461 1462 /* Check for SoC (SOC devices don't support MCU requests) */ 1463 if (rt2x00_is_soc(led->rt2x00dev)) { 1464 reg = rt2800_register_read(led->rt2x00dev, LED_CFG); 1465 1466 /* Set LED Polarity */ 1467 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); 1468 1469 /* Set LED Mode */ 1470 if (led->type == LED_TYPE_RADIO) { 1471 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 1472 enabled ? 3 : 0); 1473 } else if (led->type == LED_TYPE_ASSOC) { 1474 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 1475 enabled ? 3 : 0); 1476 } else if (led->type == LED_TYPE_QUALITY) { 1477 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 1478 enabled ? 3 : 0); 1479 } 1480 1481 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 1482 1483 } else { 1484 if (led->type == LED_TYPE_RADIO) { 1485 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1486 enabled ? 0x20 : 0); 1487 } else if (led->type == LED_TYPE_ASSOC) { 1488 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1489 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); 1490 } else if (led->type == LED_TYPE_QUALITY) { 1491 /* 1492 * The brightness is divided into 6 levels (0 - 5), 1493 * The specs tell us the following levels: 1494 * 0, 1 ,3, 7, 15, 31 1495 * to determine the level in a simple way we can simply 1496 * work with bitshifting: 1497 * (1 << level) - 1 1498 */ 1499 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 1500 (1 << brightness / (LED_FULL / 6)) - 1, 1501 polarity); 1502 } 1503 } 1504 } 1505 1506 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, 1507 struct rt2x00_led *led, enum led_type type) 1508 { 1509 led->rt2x00dev = rt2x00dev; 1510 led->type = type; 1511 led->led_dev.brightness_set = rt2800_brightness_set; 1512 led->flags = LED_INITIALIZED; 1513 } 1514 #endif /* CONFIG_RT2X00_LIB_LEDS */ 1515 1516 /* 1517 * Configuration handlers. 1518 */ 1519 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, 1520 const u8 *address, 1521 int wcid) 1522 { 1523 struct mac_wcid_entry wcid_entry; 1524 u32 offset; 1525 1526 offset = MAC_WCID_ENTRY(wcid); 1527 1528 memset(&wcid_entry, 0xff, sizeof(wcid_entry)); 1529 if (address) 1530 memcpy(wcid_entry.mac, address, ETH_ALEN); 1531 1532 rt2800_register_multiwrite(rt2x00dev, offset, 1533 &wcid_entry, sizeof(wcid_entry)); 1534 } 1535 1536 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) 1537 { 1538 u32 offset; 1539 offset = MAC_WCID_ATTR_ENTRY(wcid); 1540 rt2800_register_write(rt2x00dev, offset, 0); 1541 } 1542 1543 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, 1544 int wcid, u32 bssidx) 1545 { 1546 u32 offset = MAC_WCID_ATTR_ENTRY(wcid); 1547 u32 reg; 1548 1549 /* 1550 * The BSS Idx numbers is split in a main value of 3 bits, 1551 * and a extended field for adding one additional bit to the value. 1552 */ 1553 reg = rt2800_register_read(rt2x00dev, offset); 1554 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); 1555 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, 1556 (bssidx & 0x8) >> 3); 1557 rt2800_register_write(rt2x00dev, offset, reg); 1558 } 1559 1560 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, 1561 struct rt2x00lib_crypto *crypto, 1562 struct ieee80211_key_conf *key) 1563 { 1564 struct mac_iveiv_entry iveiv_entry; 1565 u32 offset; 1566 u32 reg; 1567 1568 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); 1569 1570 if (crypto->cmd == SET_KEY) { 1571 reg = rt2800_register_read(rt2x00dev, offset); 1572 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 1573 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 1574 /* 1575 * Both the cipher as the BSS Idx numbers are split in a main 1576 * value of 3 bits, and a extended field for adding one additional 1577 * bit to the value. 1578 */ 1579 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 1580 (crypto->cipher & 0x7)); 1581 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 1582 (crypto->cipher & 0x8) >> 3); 1583 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); 1584 rt2800_register_write(rt2x00dev, offset, reg); 1585 } else { 1586 /* Delete the cipher without touching the bssidx */ 1587 reg = rt2800_register_read(rt2x00dev, offset); 1588 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); 1589 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); 1590 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); 1591 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); 1592 rt2800_register_write(rt2x00dev, offset, reg); 1593 } 1594 1595 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 1596 1597 memset(&iveiv_entry, 0, sizeof(iveiv_entry)); 1598 if ((crypto->cipher == CIPHER_TKIP) || 1599 (crypto->cipher == CIPHER_TKIP_NO_MIC) || 1600 (crypto->cipher == CIPHER_AES)) 1601 iveiv_entry.iv[3] |= 0x20; 1602 iveiv_entry.iv[3] |= key->keyidx << 6; 1603 rt2800_register_multiwrite(rt2x00dev, offset, 1604 &iveiv_entry, sizeof(iveiv_entry)); 1605 } 1606 1607 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, 1608 struct rt2x00lib_crypto *crypto, 1609 struct ieee80211_key_conf *key) 1610 { 1611 struct hw_key_entry key_entry; 1612 struct rt2x00_field32 field; 1613 u32 offset; 1614 u32 reg; 1615 1616 if (crypto->cmd == SET_KEY) { 1617 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; 1618 1619 memcpy(key_entry.key, crypto->key, 1620 sizeof(key_entry.key)); 1621 memcpy(key_entry.tx_mic, crypto->tx_mic, 1622 sizeof(key_entry.tx_mic)); 1623 memcpy(key_entry.rx_mic, crypto->rx_mic, 1624 sizeof(key_entry.rx_mic)); 1625 1626 offset = SHARED_KEY_ENTRY(key->hw_key_idx); 1627 rt2800_register_multiwrite(rt2x00dev, offset, 1628 &key_entry, sizeof(key_entry)); 1629 } 1630 1631 /* 1632 * The cipher types are stored over multiple registers 1633 * starting with SHARED_KEY_MODE_BASE each word will have 1634 * 32 bits and contains the cipher types for 2 bssidx each. 1635 * Using the correct defines correctly will cause overhead, 1636 * so just calculate the correct offset. 1637 */ 1638 field.bit_offset = 4 * (key->hw_key_idx % 8); 1639 field.bit_mask = 0x7 << field.bit_offset; 1640 1641 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); 1642 1643 reg = rt2800_register_read(rt2x00dev, offset); 1644 rt2x00_set_field32(®, field, 1645 (crypto->cmd == SET_KEY) * crypto->cipher); 1646 rt2800_register_write(rt2x00dev, offset, reg); 1647 1648 /* 1649 * Update WCID information 1650 */ 1651 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); 1652 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, 1653 crypto->bssidx); 1654 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1655 1656 return 0; 1657 } 1658 EXPORT_SYMBOL_GPL(rt2800_config_shared_key); 1659 1660 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 1661 struct rt2x00lib_crypto *crypto, 1662 struct ieee80211_key_conf *key) 1663 { 1664 struct hw_key_entry key_entry; 1665 u32 offset; 1666 1667 if (crypto->cmd == SET_KEY) { 1668 /* 1669 * Allow key configuration only for STAs that are 1670 * known by the hw. 1671 */ 1672 if (crypto->wcid > WCID_END) 1673 return -ENOSPC; 1674 key->hw_key_idx = crypto->wcid; 1675 1676 memcpy(key_entry.key, crypto->key, 1677 sizeof(key_entry.key)); 1678 memcpy(key_entry.tx_mic, crypto->tx_mic, 1679 sizeof(key_entry.tx_mic)); 1680 memcpy(key_entry.rx_mic, crypto->rx_mic, 1681 sizeof(key_entry.rx_mic)); 1682 1683 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 1684 rt2800_register_multiwrite(rt2x00dev, offset, 1685 &key_entry, sizeof(key_entry)); 1686 } 1687 1688 /* 1689 * Update WCID information 1690 */ 1691 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1692 1693 return 0; 1694 } 1695 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); 1696 1697 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev) 1698 { 1699 u8 i, max_psdu; 1700 u32 reg; 1701 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1702 1703 for (i = 0; i < 3; i++) 1704 if (drv_data->ampdu_factor_cnt[i] > 0) 1705 break; 1706 1707 max_psdu = min(drv_data->max_psdu, i); 1708 1709 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 1710 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); 1711 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1712 } 1713 1714 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1715 struct ieee80211_sta *sta) 1716 { 1717 struct rt2x00_dev *rt2x00dev = hw->priv; 1718 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1719 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1720 int wcid; 1721 1722 /* 1723 * Limit global maximum TX AMPDU length to smallest value of all 1724 * connected stations. In AP mode this can be suboptimal, but we 1725 * do not have a choice if some connected STA is not capable to 1726 * receive the same amount of data like the others. 1727 */ 1728 if (sta->ht_cap.ht_supported) { 1729 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++; 1730 rt2800_set_max_psdu_len(rt2x00dev); 1731 } 1732 1733 /* 1734 * Search for the first free WCID entry and return the corresponding 1735 * index. 1736 */ 1737 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START; 1738 1739 /* 1740 * Store selected wcid even if it is invalid so that we can 1741 * later decide if the STA is uploaded into the hw. 1742 */ 1743 sta_priv->wcid = wcid; 1744 1745 /* 1746 * No space left in the device, however, we can still communicate 1747 * with the STA -> No error. 1748 */ 1749 if (wcid > WCID_END) 1750 return 0; 1751 1752 __set_bit(wcid - WCID_START, drv_data->sta_ids); 1753 drv_data->wcid_to_sta[wcid - WCID_START] = sta; 1754 1755 /* 1756 * Clean up WCID attributes and write STA address to the device. 1757 */ 1758 rt2800_delete_wcid_attr(rt2x00dev, wcid); 1759 rt2800_config_wcid(rt2x00dev, sta->addr, wcid); 1760 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, 1761 rt2x00lib_get_bssidx(rt2x00dev, vif)); 1762 return 0; 1763 } 1764 EXPORT_SYMBOL_GPL(rt2800_sta_add); 1765 1766 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1767 struct ieee80211_sta *sta) 1768 { 1769 struct rt2x00_dev *rt2x00dev = hw->priv; 1770 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1771 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1772 int wcid = sta_priv->wcid; 1773 1774 if (sta->ht_cap.ht_supported) { 1775 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--; 1776 rt2800_set_max_psdu_len(rt2x00dev); 1777 } 1778 1779 if (wcid > WCID_END) 1780 return 0; 1781 /* 1782 * Remove WCID entry, no need to clean the attributes as they will 1783 * get renewed when the WCID is reused. 1784 */ 1785 rt2800_config_wcid(rt2x00dev, NULL, wcid); 1786 drv_data->wcid_to_sta[wcid - WCID_START] = NULL; 1787 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1788 1789 return 0; 1790 } 1791 EXPORT_SYMBOL_GPL(rt2800_sta_remove); 1792 1793 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, 1794 const unsigned int filter_flags) 1795 { 1796 u32 reg; 1797 1798 /* 1799 * Start configuration steps. 1800 * Note that the version error will always be dropped 1801 * and broadcast frames will always be accepted since 1802 * there is no filter for it at this time. 1803 */ 1804 reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG); 1805 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, 1806 !(filter_flags & FIF_FCSFAIL)); 1807 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, 1808 !(filter_flags & FIF_PLCPFAIL)); 1809 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, 1810 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); 1811 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); 1812 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); 1813 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, 1814 !(filter_flags & FIF_ALLMULTI)); 1815 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); 1816 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); 1817 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, 1818 !(filter_flags & FIF_CONTROL)); 1819 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, 1820 !(filter_flags & FIF_CONTROL)); 1821 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, 1822 !(filter_flags & FIF_CONTROL)); 1823 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, 1824 !(filter_flags & FIF_CONTROL)); 1825 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, 1826 !(filter_flags & FIF_CONTROL)); 1827 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, 1828 !(filter_flags & FIF_PSPOLL)); 1829 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); 1830 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 1831 !(filter_flags & FIF_CONTROL)); 1832 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, 1833 !(filter_flags & FIF_CONTROL)); 1834 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); 1835 } 1836 EXPORT_SYMBOL_GPL(rt2800_config_filter); 1837 1838 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, 1839 struct rt2x00intf_conf *conf, const unsigned int flags) 1840 { 1841 u32 reg; 1842 bool update_bssid = false; 1843 1844 if (flags & CONFIG_UPDATE_TYPE) { 1845 /* 1846 * Enable synchronisation. 1847 */ 1848 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1849 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); 1850 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1851 1852 if (conf->sync == TSF_SYNC_AP_NONE) { 1853 /* 1854 * Tune beacon queue transmit parameters for AP mode 1855 */ 1856 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1857 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); 1858 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); 1859 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1860 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); 1861 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1862 } else { 1863 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1864 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); 1865 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); 1866 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1867 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); 1868 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1869 } 1870 } 1871 1872 if (flags & CONFIG_UPDATE_MAC) { 1873 if (flags & CONFIG_UPDATE_TYPE && 1874 conf->sync == TSF_SYNC_AP_NONE) { 1875 /* 1876 * The BSSID register has to be set to our own mac 1877 * address in AP mode. 1878 */ 1879 memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); 1880 update_bssid = true; 1881 } 1882 1883 if (!is_zero_ether_addr((const u8 *)conf->mac)) { 1884 reg = le32_to_cpu(conf->mac[1]); 1885 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); 1886 conf->mac[1] = cpu_to_le32(reg); 1887 } 1888 1889 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, 1890 conf->mac, sizeof(conf->mac)); 1891 } 1892 1893 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { 1894 if (!is_zero_ether_addr((const u8 *)conf->bssid)) { 1895 reg = le32_to_cpu(conf->bssid[1]); 1896 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); 1897 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); 1898 conf->bssid[1] = cpu_to_le32(reg); 1899 } 1900 1901 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, 1902 conf->bssid, sizeof(conf->bssid)); 1903 } 1904 } 1905 EXPORT_SYMBOL_GPL(rt2800_config_intf); 1906 1907 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, 1908 struct rt2x00lib_erp *erp) 1909 { 1910 bool any_sta_nongf = !!(erp->ht_opmode & 1911 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 1912 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; 1913 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; 1914 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; 1915 u32 reg; 1916 1917 /* default protection rate for HT20: OFDM 24M */ 1918 mm20_rate = gf20_rate = 0x4004; 1919 1920 /* default protection rate for HT40: duplicate OFDM 24M */ 1921 mm40_rate = gf40_rate = 0x4084; 1922 1923 switch (protection) { 1924 case IEEE80211_HT_OP_MODE_PROTECTION_NONE: 1925 /* 1926 * All STAs in this BSS are HT20/40 but there might be 1927 * STAs not supporting greenfield mode. 1928 * => Disable protection for HT transmissions. 1929 */ 1930 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; 1931 1932 break; 1933 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 1934 /* 1935 * All STAs in this BSS are HT20 or HT20/40 but there 1936 * might be STAs not supporting greenfield mode. 1937 * => Protect all HT40 transmissions. 1938 */ 1939 mm20_mode = gf20_mode = 0; 1940 mm40_mode = gf40_mode = 1; 1941 1942 break; 1943 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 1944 /* 1945 * Nonmember protection: 1946 * According to 802.11n we _should_ protect all 1947 * HT transmissions (but we don't have to). 1948 * 1949 * But if cts_protection is enabled we _shall_ protect 1950 * all HT transmissions using a CCK rate. 1951 * 1952 * And if any station is non GF we _shall_ protect 1953 * GF transmissions. 1954 * 1955 * We decide to protect everything 1956 * -> fall through to mixed mode. 1957 */ 1958 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 1959 /* 1960 * Legacy STAs are present 1961 * => Protect all HT transmissions. 1962 */ 1963 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1; 1964 1965 /* 1966 * If erp protection is needed we have to protect HT 1967 * transmissions with CCK 11M long preamble. 1968 */ 1969 if (erp->cts_protection) { 1970 /* don't duplicate RTS/CTS in CCK mode */ 1971 mm20_rate = mm40_rate = 0x0003; 1972 gf20_rate = gf40_rate = 0x0003; 1973 } 1974 break; 1975 } 1976 1977 /* check for STAs not supporting greenfield mode */ 1978 if (any_sta_nongf) 1979 gf20_mode = gf40_mode = 1; 1980 1981 /* Update HT protection config */ 1982 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 1983 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); 1984 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); 1985 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 1986 1987 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 1988 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); 1989 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); 1990 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 1991 1992 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 1993 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); 1994 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); 1995 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 1996 1997 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 1998 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); 1999 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); 2000 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 2001 } 2002 2003 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, 2004 u32 changed) 2005 { 2006 u32 reg; 2007 2008 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 2009 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 2010 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 2011 !!erp->short_preamble); 2012 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 2013 } 2014 2015 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 2016 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 2017 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 2018 erp->cts_protection ? 2 : 0); 2019 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 2020 } 2021 2022 if (changed & BSS_CHANGED_BASIC_RATES) { 2023 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 2024 0xff0 | erp->basic_rates); 2025 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 2026 } 2027 2028 if (changed & BSS_CHANGED_ERP_SLOT) { 2029 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 2030 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 2031 erp->slot_time); 2032 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 2033 2034 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 2035 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); 2036 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 2037 } 2038 2039 if (changed & BSS_CHANGED_BEACON_INT) { 2040 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 2041 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 2042 erp->beacon_int * 16); 2043 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 2044 } 2045 2046 if (changed & BSS_CHANGED_HT) 2047 rt2800_config_ht_opmode(rt2x00dev, erp); 2048 } 2049 EXPORT_SYMBOL_GPL(rt2800_config_erp); 2050 2051 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) 2052 { 2053 u32 reg; 2054 u16 eeprom; 2055 u8 led_ctrl, led_g_mode, led_r_mode; 2056 2057 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 2058 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { 2059 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); 2060 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); 2061 } else { 2062 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); 2063 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); 2064 } 2065 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 2066 2067 reg = rt2800_register_read(rt2x00dev, LED_CFG); 2068 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; 2069 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; 2070 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || 2071 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { 2072 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 2073 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); 2074 if (led_ctrl == 0 || led_ctrl > 0x40) { 2075 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); 2076 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); 2077 rt2800_register_write(rt2x00dev, LED_CFG, reg); 2078 } else { 2079 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, 2080 (led_g_mode << 2) | led_r_mode, 1); 2081 } 2082 } 2083 } 2084 2085 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, 2086 enum antenna ant) 2087 { 2088 u32 reg; 2089 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; 2090 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; 2091 2092 if (rt2x00_is_pci(rt2x00dev)) { 2093 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR); 2094 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); 2095 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); 2096 } else if (rt2x00_is_usb(rt2x00dev)) 2097 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, 2098 eesk_pin, 0); 2099 2100 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2101 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 2102 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); 2103 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2104 } 2105 2106 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 2107 { 2108 u8 r1; 2109 u8 r3; 2110 u16 eeprom; 2111 2112 r1 = rt2800_bbp_read(rt2x00dev, 1); 2113 r3 = rt2800_bbp_read(rt2x00dev, 3); 2114 2115 if (rt2x00_rt(rt2x00dev, RT3572) && 2116 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2117 rt2800_config_3572bt_ant(rt2x00dev); 2118 2119 /* 2120 * Configure the TX antenna. 2121 */ 2122 switch (ant->tx_chain_num) { 2123 case 1: 2124 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 2125 break; 2126 case 2: 2127 if (rt2x00_rt(rt2x00dev, RT3572) && 2128 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2129 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); 2130 else 2131 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2132 break; 2133 case 3: 2134 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2135 break; 2136 } 2137 2138 /* 2139 * Configure the RX antenna. 2140 */ 2141 switch (ant->rx_chain_num) { 2142 case 1: 2143 if (rt2x00_rt(rt2x00dev, RT3070) || 2144 rt2x00_rt(rt2x00dev, RT3090) || 2145 rt2x00_rt(rt2x00dev, RT3352) || 2146 rt2x00_rt(rt2x00dev, RT3390)) { 2147 eeprom = rt2800_eeprom_read(rt2x00dev, 2148 EEPROM_NIC_CONF1); 2149 if (rt2x00_get_field16(eeprom, 2150 EEPROM_NIC_CONF1_ANT_DIVERSITY)) 2151 rt2800_set_ant_diversity(rt2x00dev, 2152 rt2x00dev->default_ant.rx); 2153 } 2154 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 2155 break; 2156 case 2: 2157 if (rt2x00_rt(rt2x00dev, RT3572) && 2158 rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2159 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); 2160 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2161 rt2x00dev->curr_band == NL80211_BAND_5GHZ); 2162 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); 2163 } else { 2164 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); 2165 } 2166 break; 2167 case 3: 2168 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); 2169 break; 2170 } 2171 2172 rt2800_bbp_write(rt2x00dev, 3, r3); 2173 rt2800_bbp_write(rt2x00dev, 1, r1); 2174 2175 if (rt2x00_rt(rt2x00dev, RT3593)) { 2176 if (ant->rx_chain_num == 1) 2177 rt2800_bbp_write(rt2x00dev, 86, 0x00); 2178 else 2179 rt2800_bbp_write(rt2x00dev, 86, 0x46); 2180 } 2181 } 2182 EXPORT_SYMBOL_GPL(rt2800_config_ant); 2183 2184 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, 2185 struct rt2x00lib_conf *libconf) 2186 { 2187 u16 eeprom; 2188 short lna_gain; 2189 2190 if (libconf->rf.channel <= 14) { 2191 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2192 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); 2193 } else if (libconf->rf.channel <= 64) { 2194 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2195 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); 2196 } else if (libconf->rf.channel <= 128) { 2197 if (rt2x00_rt(rt2x00dev, RT3593)) { 2198 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2199 lna_gain = rt2x00_get_field16(eeprom, 2200 EEPROM_EXT_LNA2_A1); 2201 } else { 2202 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 2203 lna_gain = rt2x00_get_field16(eeprom, 2204 EEPROM_RSSI_BG2_LNA_A1); 2205 } 2206 } else { 2207 if (rt2x00_rt(rt2x00dev, RT3593)) { 2208 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2209 lna_gain = rt2x00_get_field16(eeprom, 2210 EEPROM_EXT_LNA2_A2); 2211 } else { 2212 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 2213 lna_gain = rt2x00_get_field16(eeprom, 2214 EEPROM_RSSI_A2_LNA_A2); 2215 } 2216 } 2217 2218 rt2x00dev->lna_gain = lna_gain; 2219 } 2220 2221 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev) 2222 { 2223 return clk_get_rate(rt2x00dev->clk) == 20000000; 2224 } 2225 2226 #define FREQ_OFFSET_BOUND 0x5f 2227 2228 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev) 2229 { 2230 u8 freq_offset, prev_freq_offset; 2231 u8 rfcsr, prev_rfcsr; 2232 2233 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE); 2234 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND); 2235 2236 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 2237 prev_rfcsr = rfcsr; 2238 2239 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset); 2240 if (rfcsr == prev_rfcsr) 2241 return; 2242 2243 if (rt2x00_is_usb(rt2x00dev)) { 2244 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff, 2245 freq_offset, prev_rfcsr); 2246 return; 2247 } 2248 2249 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE); 2250 while (prev_freq_offset != freq_offset) { 2251 if (prev_freq_offset < freq_offset) 2252 prev_freq_offset++; 2253 else 2254 prev_freq_offset--; 2255 2256 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset); 2257 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 2258 2259 usleep_range(1000, 1500); 2260 } 2261 } 2262 2263 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, 2264 struct ieee80211_conf *conf, 2265 struct rf_channel *rf, 2266 struct channel_info *info) 2267 { 2268 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 2269 2270 if (rt2x00dev->default_ant.tx_chain_num == 1) 2271 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); 2272 2273 if (rt2x00dev->default_ant.rx_chain_num == 1) { 2274 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); 2275 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2276 } else if (rt2x00dev->default_ant.rx_chain_num == 2) 2277 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2278 2279 if (rf->channel > 14) { 2280 /* 2281 * When TX power is below 0, we should increase it by 7 to 2282 * make it a positive value (Minimum value is -7). 2283 * However this means that values between 0 and 7 have 2284 * double meaning, and we should set a 7DBm boost flag. 2285 */ 2286 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, 2287 (info->default_power1 >= 0)); 2288 2289 if (info->default_power1 < 0) 2290 info->default_power1 += 7; 2291 2292 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); 2293 2294 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, 2295 (info->default_power2 >= 0)); 2296 2297 if (info->default_power2 < 0) 2298 info->default_power2 += 7; 2299 2300 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); 2301 } else { 2302 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); 2303 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); 2304 } 2305 2306 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); 2307 2308 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2309 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2310 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2311 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2312 2313 udelay(200); 2314 2315 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2316 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2317 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 2318 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2319 2320 udelay(200); 2321 2322 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2323 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2324 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2325 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2326 } 2327 2328 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, 2329 struct ieee80211_conf *conf, 2330 struct rf_channel *rf, 2331 struct channel_info *info) 2332 { 2333 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2334 u8 rfcsr, calib_tx, calib_rx; 2335 2336 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2337 2338 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2339 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3); 2340 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2341 2342 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2343 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2344 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2345 2346 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2347 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); 2348 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2349 2350 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2351 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); 2352 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2353 2354 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2355 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2356 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 2357 rt2x00dev->default_ant.rx_chain_num <= 1); 2358 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 2359 rt2x00dev->default_ant.rx_chain_num <= 2); 2360 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2361 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 2362 rt2x00dev->default_ant.tx_chain_num <= 1); 2363 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 2364 rt2x00dev->default_ant.tx_chain_num <= 2); 2365 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2366 2367 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2368 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2369 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2370 2371 if (rt2x00_rt(rt2x00dev, RT3390)) { 2372 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f; 2373 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f; 2374 } else { 2375 if (conf_is_ht40(conf)) { 2376 calib_tx = drv_data->calibration_bw40; 2377 calib_rx = drv_data->calibration_bw40; 2378 } else { 2379 calib_tx = drv_data->calibration_bw20; 2380 calib_rx = drv_data->calibration_bw20; 2381 } 2382 } 2383 2384 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24); 2385 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx); 2386 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr); 2387 2388 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 2389 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx); 2390 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2391 2392 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2393 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2394 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2395 2396 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2397 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 2398 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2399 2400 usleep_range(1000, 1500); 2401 2402 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 2403 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2404 } 2405 2406 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, 2407 struct ieee80211_conf *conf, 2408 struct rf_channel *rf, 2409 struct channel_info *info) 2410 { 2411 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2412 u8 rfcsr; 2413 u32 reg; 2414 2415 if (rf->channel <= 14) { 2416 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2417 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2418 } else { 2419 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2420 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2421 } 2422 2423 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2424 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 2425 2426 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2427 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2428 if (rf->channel <= 14) 2429 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); 2430 else 2431 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); 2432 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2433 2434 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5); 2435 if (rf->channel <= 14) 2436 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); 2437 else 2438 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); 2439 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); 2440 2441 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2442 if (rf->channel <= 14) { 2443 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); 2444 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2445 info->default_power1); 2446 } else { 2447 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); 2448 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2449 (info->default_power1 & 0x3) | 2450 ((info->default_power1 & 0xC) << 1)); 2451 } 2452 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2453 2454 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2455 if (rf->channel <= 14) { 2456 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); 2457 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2458 info->default_power2); 2459 } else { 2460 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); 2461 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2462 (info->default_power2 & 0x3) | 2463 ((info->default_power2 & 0xC) << 1)); 2464 } 2465 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2466 2467 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2468 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2469 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2470 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2471 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2472 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2473 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2474 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2475 if (rf->channel <= 14) { 2476 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2477 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2478 } 2479 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2480 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2481 } else { 2482 switch (rt2x00dev->default_ant.tx_chain_num) { 2483 case 1: 2484 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2485 case 2: 2486 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2487 break; 2488 } 2489 2490 switch (rt2x00dev->default_ant.rx_chain_num) { 2491 case 1: 2492 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2493 case 2: 2494 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2495 break; 2496 } 2497 } 2498 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2499 2500 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2501 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2502 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2503 2504 if (conf_is_ht40(conf)) { 2505 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40); 2506 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40); 2507 } else { 2508 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20); 2509 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20); 2510 } 2511 2512 if (rf->channel <= 14) { 2513 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 2514 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 2515 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2516 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 2517 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 2518 rfcsr = 0x4c; 2519 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2520 drv_data->txmixer_gain_24g); 2521 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2522 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2523 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 2524 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 2525 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 2526 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 2527 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 2528 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 2529 } else { 2530 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2531 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1); 2532 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0); 2533 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1); 2534 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0); 2535 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2536 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 2537 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2538 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 2539 rt2800_rfcsr_write(rt2x00dev, 15, 0x43); 2540 rfcsr = 0x7a; 2541 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2542 drv_data->txmixer_gain_5g); 2543 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2544 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2545 if (rf->channel <= 64) { 2546 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7); 2547 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6); 2548 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 2549 } else if (rf->channel <= 128) { 2550 rt2800_rfcsr_write(rt2x00dev, 19, 0x74); 2551 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4); 2552 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2553 } else { 2554 rt2800_rfcsr_write(rt2x00dev, 19, 0x72); 2555 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3); 2556 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2557 } 2558 rt2800_rfcsr_write(rt2x00dev, 26, 0x87); 2559 rt2800_rfcsr_write(rt2x00dev, 27, 0x01); 2560 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); 2561 } 2562 2563 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2564 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 2565 if (rf->channel <= 14) 2566 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 2567 else 2568 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); 2569 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2570 2571 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2572 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2573 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2574 } 2575 2576 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, 2577 struct ieee80211_conf *conf, 2578 struct rf_channel *rf, 2579 struct channel_info *info) 2580 { 2581 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2582 u8 txrx_agc_fc; 2583 u8 txrx_h20m; 2584 u8 rfcsr; 2585 u8 bbp; 2586 const bool txbf_enabled = false; /* TODO */ 2587 2588 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */ 2589 bbp = rt2800_bbp_read(rt2x00dev, 109); 2590 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0); 2591 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0); 2592 rt2800_bbp_write(rt2x00dev, 109, bbp); 2593 2594 bbp = rt2800_bbp_read(rt2x00dev, 110); 2595 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0); 2596 rt2800_bbp_write(rt2x00dev, 110, bbp); 2597 2598 if (rf->channel <= 14) { 2599 /* Restore BBP 25 & 26 for 2.4 GHz */ 2600 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2601 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2602 } else { 2603 /* Hard code BBP 25 & 26 for 5GHz */ 2604 2605 /* Enable IQ Phase correction */ 2606 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2607 /* Setup IQ Phase correction value */ 2608 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2609 } 2610 2611 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2612 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf); 2613 2614 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2615 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3)); 2616 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2617 2618 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2619 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1); 2620 if (rf->channel <= 14) 2621 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1); 2622 else 2623 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2); 2624 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2625 2626 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53); 2627 if (rf->channel <= 14) { 2628 rfcsr = 0; 2629 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2630 info->default_power1 & 0x1f); 2631 } else { 2632 if (rt2x00_is_usb(rt2x00dev)) 2633 rfcsr = 0x40; 2634 2635 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2636 ((info->default_power1 & 0x18) << 1) | 2637 (info->default_power1 & 7)); 2638 } 2639 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr); 2640 2641 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55); 2642 if (rf->channel <= 14) { 2643 rfcsr = 0; 2644 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2645 info->default_power2 & 0x1f); 2646 } else { 2647 if (rt2x00_is_usb(rt2x00dev)) 2648 rfcsr = 0x40; 2649 2650 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2651 ((info->default_power2 & 0x18) << 1) | 2652 (info->default_power2 & 7)); 2653 } 2654 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr); 2655 2656 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54); 2657 if (rf->channel <= 14) { 2658 rfcsr = 0; 2659 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2660 info->default_power3 & 0x1f); 2661 } else { 2662 if (rt2x00_is_usb(rt2x00dev)) 2663 rfcsr = 0x40; 2664 2665 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2666 ((info->default_power3 & 0x18) << 1) | 2667 (info->default_power3 & 7)); 2668 } 2669 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr); 2670 2671 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2672 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2673 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2674 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2675 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2676 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2677 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2678 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2679 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2680 2681 switch (rt2x00dev->default_ant.tx_chain_num) { 2682 case 3: 2683 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2684 /* fallthrough */ 2685 case 2: 2686 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2687 /* fallthrough */ 2688 case 1: 2689 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2690 break; 2691 } 2692 2693 switch (rt2x00dev->default_ant.rx_chain_num) { 2694 case 3: 2695 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2696 /* fallthrough */ 2697 case 2: 2698 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2699 /* fallthrough */ 2700 case 1: 2701 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2702 break; 2703 } 2704 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2705 2706 rt2800_freq_cal_mode1(rt2x00dev); 2707 2708 if (conf_is_ht40(conf)) { 2709 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40, 2710 RFCSR24_TX_AGC_FC); 2711 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40, 2712 RFCSR24_TX_H20M); 2713 } else { 2714 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20, 2715 RFCSR24_TX_AGC_FC); 2716 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20, 2717 RFCSR24_TX_H20M); 2718 } 2719 2720 /* NOTE: the reference driver does not writes the new value 2721 * back to RFCSR 32 2722 */ 2723 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32); 2724 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc); 2725 2726 if (rf->channel <= 14) 2727 rfcsr = 0xa0; 2728 else 2729 rfcsr = 0x80; 2730 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2731 2732 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2733 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m); 2734 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m); 2735 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2736 2737 /* Band selection */ 2738 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 2739 if (rf->channel <= 14) 2740 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 2741 else 2742 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 2743 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 2744 2745 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34); 2746 if (rf->channel <= 14) 2747 rfcsr = 0x3c; 2748 else 2749 rfcsr = 0x20; 2750 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 2751 2752 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2753 if (rf->channel <= 14) 2754 rfcsr = 0x1a; 2755 else 2756 rfcsr = 0x12; 2757 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2758 2759 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2760 if (rf->channel >= 1 && rf->channel <= 14) 2761 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2762 else if (rf->channel >= 36 && rf->channel <= 64) 2763 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2764 else if (rf->channel >= 100 && rf->channel <= 128) 2765 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2766 else 2767 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2768 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2769 2770 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2771 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 2772 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2773 2774 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 2775 2776 if (rf->channel <= 14) { 2777 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 2778 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 2779 } else { 2780 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8); 2781 rt2800_rfcsr_write(rt2x00dev, 13, 0x23); 2782 } 2783 2784 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2785 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1); 2786 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2787 2788 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2789 if (rf->channel <= 14) { 2790 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5); 2791 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3); 2792 } else { 2793 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4); 2794 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2); 2795 } 2796 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2797 2798 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2799 if (rf->channel <= 14) 2800 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3); 2801 else 2802 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2); 2803 2804 if (txbf_enabled) 2805 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1); 2806 2807 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2808 2809 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 2810 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0); 2811 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2812 2813 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 2814 if (rf->channel <= 14) 2815 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b); 2816 else 2817 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f); 2818 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr); 2819 2820 if (rf->channel <= 14) { 2821 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 2822 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 2823 } else { 2824 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 2825 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 2826 } 2827 2828 /* Initiate VCO calibration */ 2829 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2830 if (rf->channel <= 14) { 2831 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2832 } else { 2833 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1); 2834 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1); 2835 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1); 2836 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1); 2837 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1); 2838 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2839 } 2840 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2841 2842 if (rf->channel >= 1 && rf->channel <= 14) { 2843 rfcsr = 0x23; 2844 if (txbf_enabled) 2845 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2846 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2847 2848 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 2849 } else if (rf->channel >= 36 && rf->channel <= 64) { 2850 rfcsr = 0x36; 2851 if (txbf_enabled) 2852 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2853 rt2800_rfcsr_write(rt2x00dev, 39, 0x36); 2854 2855 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb); 2856 } else if (rf->channel >= 100 && rf->channel <= 128) { 2857 rfcsr = 0x32; 2858 if (txbf_enabled) 2859 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2860 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2861 2862 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3); 2863 } else { 2864 rfcsr = 0x30; 2865 if (txbf_enabled) 2866 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2867 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2868 2869 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b); 2870 } 2871 } 2872 2873 #define POWER_BOUND 0x27 2874 #define POWER_BOUND_5G 0x2b 2875 2876 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev, 2877 struct ieee80211_conf *conf, 2878 struct rf_channel *rf, 2879 struct channel_info *info) 2880 { 2881 u8 rfcsr; 2882 2883 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2884 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2885 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2886 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 2887 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2888 2889 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2890 if (info->default_power1 > POWER_BOUND) 2891 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 2892 else 2893 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2894 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2895 2896 rt2800_freq_cal_mode1(rt2x00dev); 2897 2898 if (rf->channel <= 14) { 2899 if (rf->channel == 6) 2900 rt2800_bbp_write(rt2x00dev, 68, 0x0c); 2901 else 2902 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 2903 2904 if (rf->channel >= 1 && rf->channel <= 6) 2905 rt2800_bbp_write(rt2x00dev, 59, 0x0f); 2906 else if (rf->channel >= 7 && rf->channel <= 11) 2907 rt2800_bbp_write(rt2x00dev, 59, 0x0e); 2908 else if (rf->channel >= 12 && rf->channel <= 14) 2909 rt2800_bbp_write(rt2x00dev, 59, 0x0d); 2910 } 2911 } 2912 2913 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev, 2914 struct ieee80211_conf *conf, 2915 struct rf_channel *rf, 2916 struct channel_info *info) 2917 { 2918 u8 rfcsr; 2919 2920 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2921 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2922 2923 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 2924 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 2925 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 2926 2927 if (info->default_power1 > POWER_BOUND) 2928 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND); 2929 else 2930 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1); 2931 2932 if (info->default_power2 > POWER_BOUND) 2933 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND); 2934 else 2935 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2); 2936 2937 rt2800_freq_cal_mode1(rt2x00dev); 2938 2939 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2940 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2941 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2942 2943 if ( rt2x00dev->default_ant.tx_chain_num == 2 ) 2944 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2945 else 2946 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2947 2948 if ( rt2x00dev->default_ant.rx_chain_num == 2 ) 2949 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2950 else 2951 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2952 2953 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2954 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2955 2956 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2957 2958 rt2800_rfcsr_write(rt2x00dev, 31, 80); 2959 } 2960 2961 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 2962 struct ieee80211_conf *conf, 2963 struct rf_channel *rf, 2964 struct channel_info *info) 2965 { 2966 u8 rfcsr; 2967 2968 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2969 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2970 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2971 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 2972 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2973 2974 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2975 if (info->default_power1 > POWER_BOUND) 2976 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 2977 else 2978 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2979 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2980 2981 if (rt2x00_rt(rt2x00dev, RT5392)) { 2982 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 2983 if (info->default_power2 > POWER_BOUND) 2984 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND); 2985 else 2986 rt2x00_set_field8(&rfcsr, RFCSR50_TX, 2987 info->default_power2); 2988 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2989 } 2990 2991 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2992 if (rt2x00_rt(rt2x00dev, RT5392)) { 2993 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2994 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2995 } 2996 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2997 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2998 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2999 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3000 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3001 3002 rt2800_freq_cal_mode1(rt2x00dev); 3003 3004 if (rf->channel <= 14) { 3005 int idx = rf->channel-1; 3006 3007 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 3008 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3009 /* r55/r59 value array of channel 1~14 */ 3010 static const char r55_bt_rev[] = {0x83, 0x83, 3011 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, 3012 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; 3013 static const char r59_bt_rev[] = {0x0e, 0x0e, 3014 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, 3015 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; 3016 3017 rt2800_rfcsr_write(rt2x00dev, 55, 3018 r55_bt_rev[idx]); 3019 rt2800_rfcsr_write(rt2x00dev, 59, 3020 r59_bt_rev[idx]); 3021 } else { 3022 static const char r59_bt[] = {0x8b, 0x8b, 0x8b, 3023 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, 3024 0x88, 0x88, 0x86, 0x85, 0x84}; 3025 3026 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); 3027 } 3028 } else { 3029 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3030 static const char r55_nonbt_rev[] = {0x23, 0x23, 3031 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, 3032 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; 3033 static const char r59_nonbt_rev[] = {0x07, 0x07, 3034 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 3035 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; 3036 3037 rt2800_rfcsr_write(rt2x00dev, 55, 3038 r55_nonbt_rev[idx]); 3039 rt2800_rfcsr_write(rt2x00dev, 59, 3040 r59_nonbt_rev[idx]); 3041 } else if (rt2x00_rt(rt2x00dev, RT5390) || 3042 rt2x00_rt(rt2x00dev, RT5392) || 3043 rt2x00_rt(rt2x00dev, RT6352)) { 3044 static const char r59_non_bt[] = {0x8f, 0x8f, 3045 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, 3046 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; 3047 3048 rt2800_rfcsr_write(rt2x00dev, 59, 3049 r59_non_bt[idx]); 3050 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 3051 static const char r59_non_bt[] = {0x0b, 0x0b, 3052 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a, 3053 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06}; 3054 3055 rt2800_rfcsr_write(rt2x00dev, 59, 3056 r59_non_bt[idx]); 3057 } 3058 } 3059 } 3060 } 3061 3062 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, 3063 struct ieee80211_conf *conf, 3064 struct rf_channel *rf, 3065 struct channel_info *info) 3066 { 3067 u8 rfcsr, ep_reg; 3068 u32 reg; 3069 int power_bound; 3070 3071 /* TODO */ 3072 const bool is_11b = false; 3073 const bool is_type_ep = false; 3074 3075 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 3076 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3077 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0); 3078 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 3079 3080 /* Order of values on rf_channel entry: N, K, mod, R */ 3081 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff); 3082 3083 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9); 3084 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf); 3085 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8); 3086 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2); 3087 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr); 3088 3089 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3090 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1); 3091 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3); 3092 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3093 3094 if (rf->channel <= 14) { 3095 rt2800_rfcsr_write(rt2x00dev, 10, 0x90); 3096 /* FIXME: RF11 owerwrite ? */ 3097 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A); 3098 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 3099 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3100 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3101 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A); 3102 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 3103 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3104 rt2800_rfcsr_write(rt2x00dev, 36, 0x80); 3105 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 3106 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 3107 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B); 3108 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D); 3109 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B); 3110 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5); 3111 rt2800_rfcsr_write(rt2x00dev, 43, 0x72); 3112 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E); 3113 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2); 3114 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B); 3115 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 3116 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E); 3117 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 3118 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 3119 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1); 3120 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 3121 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 3122 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 3123 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 3124 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 3125 3126 /* TODO RF27 <- tssi */ 3127 3128 rfcsr = rf->channel <= 10 ? 0x07 : 0x06; 3129 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 3130 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr); 3131 3132 if (is_11b) { 3133 /* CCK */ 3134 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8); 3135 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0); 3136 if (is_type_ep) 3137 rt2800_rfcsr_write(rt2x00dev, 55, 0x06); 3138 else 3139 rt2800_rfcsr_write(rt2x00dev, 55, 0x47); 3140 } else { 3141 /* OFDM */ 3142 if (is_type_ep) 3143 rt2800_rfcsr_write(rt2x00dev, 55, 0x03); 3144 else 3145 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 3146 } 3147 3148 power_bound = POWER_BOUND; 3149 ep_reg = 0x2; 3150 } else { 3151 rt2800_rfcsr_write(rt2x00dev, 10, 0x97); 3152 /* FIMXE: RF11 overwrite */ 3153 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 3154 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF); 3155 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3156 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 3157 rt2800_rfcsr_write(rt2x00dev, 37, 0x04); 3158 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 3159 rt2800_rfcsr_write(rt2x00dev, 40, 0x42); 3160 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB); 3161 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7); 3162 rt2800_rfcsr_write(rt2x00dev, 45, 0x41); 3163 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 3164 rt2800_rfcsr_write(rt2x00dev, 57, 0x77); 3165 rt2800_rfcsr_write(rt2x00dev, 60, 0x05); 3166 rt2800_rfcsr_write(rt2x00dev, 61, 0x01); 3167 3168 /* TODO RF27 <- tssi */ 3169 3170 if (rf->channel >= 36 && rf->channel <= 64) { 3171 3172 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E); 3173 rt2800_rfcsr_write(rt2x00dev, 13, 0x22); 3174 rt2800_rfcsr_write(rt2x00dev, 22, 0x60); 3175 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F); 3176 if (rf->channel <= 50) 3177 rt2800_rfcsr_write(rt2x00dev, 24, 0x09); 3178 else if (rf->channel >= 52) 3179 rt2800_rfcsr_write(rt2x00dev, 24, 0x07); 3180 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C); 3181 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B); 3182 rt2800_rfcsr_write(rt2x00dev, 44, 0X40); 3183 rt2800_rfcsr_write(rt2x00dev, 46, 0X00); 3184 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE); 3185 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C); 3186 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8); 3187 if (rf->channel <= 50) { 3188 rt2800_rfcsr_write(rt2x00dev, 55, 0x06), 3189 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3); 3190 } else if (rf->channel >= 52) { 3191 rt2800_rfcsr_write(rt2x00dev, 55, 0x04); 3192 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3193 } 3194 3195 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3196 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F); 3197 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3198 3199 } else if (rf->channel >= 100 && rf->channel <= 165) { 3200 3201 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E); 3202 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3203 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3204 if (rf->channel <= 153) { 3205 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C); 3206 rt2800_rfcsr_write(rt2x00dev, 24, 0x06); 3207 } else if (rf->channel >= 155) { 3208 rt2800_rfcsr_write(rt2x00dev, 23, 0x38); 3209 rt2800_rfcsr_write(rt2x00dev, 24, 0x05); 3210 } 3211 if (rf->channel <= 138) { 3212 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A); 3213 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B); 3214 rt2800_rfcsr_write(rt2x00dev, 44, 0x20); 3215 rt2800_rfcsr_write(rt2x00dev, 46, 0x18); 3216 } else if (rf->channel >= 140) { 3217 rt2800_rfcsr_write(rt2x00dev, 39, 0x18); 3218 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B); 3219 rt2800_rfcsr_write(rt2x00dev, 44, 0x10); 3220 rt2800_rfcsr_write(rt2x00dev, 46, 0X08); 3221 } 3222 if (rf->channel <= 124) 3223 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC); 3224 else if (rf->channel >= 126) 3225 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC); 3226 if (rf->channel <= 138) 3227 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3228 else if (rf->channel >= 140) 3229 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3230 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB); 3231 if (rf->channel <= 138) 3232 rt2800_rfcsr_write(rt2x00dev, 55, 0x01); 3233 else if (rf->channel >= 140) 3234 rt2800_rfcsr_write(rt2x00dev, 55, 0x00); 3235 if (rf->channel <= 128) 3236 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3237 else if (rf->channel >= 130) 3238 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB); 3239 if (rf->channel <= 116) 3240 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D); 3241 else if (rf->channel >= 118) 3242 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3243 if (rf->channel <= 138) 3244 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F); 3245 else if (rf->channel >= 140) 3246 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C); 3247 if (rf->channel <= 116) 3248 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D); 3249 else if (rf->channel >= 118) 3250 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3251 } 3252 3253 power_bound = POWER_BOUND_5G; 3254 ep_reg = 0x3; 3255 } 3256 3257 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3258 if (info->default_power1 > power_bound) 3259 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound); 3260 else 3261 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3262 if (is_type_ep) 3263 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg); 3264 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3265 3266 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3267 if (info->default_power2 > power_bound) 3268 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound); 3269 else 3270 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2); 3271 if (is_type_ep) 3272 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg); 3273 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3274 3275 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3276 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3277 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3278 3279 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 3280 rt2x00dev->default_ant.tx_chain_num >= 1); 3281 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 3282 rt2x00dev->default_ant.tx_chain_num == 2); 3283 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3284 3285 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 3286 rt2x00dev->default_ant.rx_chain_num >= 1); 3287 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 3288 rt2x00dev->default_ant.rx_chain_num == 2); 3289 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3290 3291 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3292 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4); 3293 3294 if (conf_is_ht40(conf)) 3295 rt2800_rfcsr_write(rt2x00dev, 30, 0x16); 3296 else 3297 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 3298 3299 if (!is_11b) { 3300 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3301 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3302 } 3303 3304 /* TODO proper frequency adjustment */ 3305 rt2800_freq_cal_mode1(rt2x00dev); 3306 3307 /* TODO merge with others */ 3308 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3309 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3310 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3311 3312 /* BBP settings */ 3313 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3314 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3315 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3316 3317 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18); 3318 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08); 3319 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38); 3320 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92); 3321 3322 /* GLRT band configuration */ 3323 rt2800_bbp_write(rt2x00dev, 195, 128); 3324 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0); 3325 rt2800_bbp_write(rt2x00dev, 195, 129); 3326 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E); 3327 rt2800_bbp_write(rt2x00dev, 195, 130); 3328 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28); 3329 rt2800_bbp_write(rt2x00dev, 195, 131); 3330 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20); 3331 rt2800_bbp_write(rt2x00dev, 195, 133); 3332 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F); 3333 rt2800_bbp_write(rt2x00dev, 195, 124); 3334 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F); 3335 } 3336 3337 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev, 3338 struct ieee80211_conf *conf, 3339 struct rf_channel *rf, 3340 struct channel_info *info) 3341 { 3342 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 3343 u8 rx_agc_fc, tx_agc_fc; 3344 u8 rfcsr; 3345 3346 /* Frequeny plan setting */ 3347 /* Rdiv setting (set 0x03 if Xtal==20) 3348 * R13[1:0] 3349 */ 3350 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 3351 rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620, 3352 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0); 3353 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 3354 3355 /* N setting 3356 * R20[7:0] in rf->rf1 3357 * R21[0] always 0 3358 */ 3359 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 3360 rfcsr = (rf->rf1 & 0x00ff); 3361 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 3362 3363 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3364 rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0); 3365 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3366 3367 /* K setting (always 0) 3368 * R16[3:0] (RF PLL freq selection) 3369 */ 3370 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3371 rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0); 3372 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3373 3374 /* D setting (always 0) 3375 * R22[2:0] (D=15, R22[2:0]=<111>) 3376 */ 3377 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 3378 rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0); 3379 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 3380 3381 /* Ksd setting 3382 * Ksd: R17<7:0> in rf->rf2 3383 * R18<7:0> in rf->rf3 3384 * R19<1:0> in rf->rf4 3385 */ 3386 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 3387 rfcsr = rf->rf2; 3388 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 3389 3390 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 3391 rfcsr = rf->rf3; 3392 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 3393 3394 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19); 3395 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4); 3396 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr); 3397 3398 /* Default: XO=20MHz , SDM mode */ 3399 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3400 rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80); 3401 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3402 3403 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3404 rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1); 3405 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3406 3407 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3408 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620, 3409 rt2x00dev->default_ant.tx_chain_num != 1); 3410 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3411 3412 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 3413 rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620, 3414 rt2x00dev->default_ant.tx_chain_num != 1); 3415 rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620, 3416 rt2x00dev->default_ant.rx_chain_num != 1); 3417 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 3418 3419 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42); 3420 rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620, 3421 rt2x00dev->default_ant.tx_chain_num != 1); 3422 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 3423 3424 /* RF for DC Cal BW */ 3425 if (conf_is_ht40(conf)) { 3426 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 3427 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 3428 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 3429 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 3430 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 3431 } else { 3432 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20); 3433 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20); 3434 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00); 3435 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20); 3436 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20); 3437 } 3438 3439 if (conf_is_ht40(conf)) { 3440 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08); 3441 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08); 3442 } else { 3443 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28); 3444 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28); 3445 } 3446 3447 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28); 3448 rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40, 3449 conf_is_ht40(conf) && (rf->channel == 11)); 3450 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr); 3451 3452 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) { 3453 if (conf_is_ht40(conf)) { 3454 rx_agc_fc = drv_data->rx_calibration_bw40; 3455 tx_agc_fc = drv_data->tx_calibration_bw40; 3456 } else { 3457 rx_agc_fc = drv_data->rx_calibration_bw20; 3458 tx_agc_fc = drv_data->tx_calibration_bw20; 3459 } 3460 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 3461 rfcsr &= (~0x3F); 3462 rfcsr |= rx_agc_fc; 3463 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr); 3464 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 3465 rfcsr &= (~0x3F); 3466 rfcsr |= rx_agc_fc; 3467 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr); 3468 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6); 3469 rfcsr &= (~0x3F); 3470 rfcsr |= rx_agc_fc; 3471 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr); 3472 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7); 3473 rfcsr &= (~0x3F); 3474 rfcsr |= rx_agc_fc; 3475 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr); 3476 3477 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 3478 rfcsr &= (~0x3F); 3479 rfcsr |= tx_agc_fc; 3480 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr); 3481 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 3482 rfcsr &= (~0x3F); 3483 rfcsr |= tx_agc_fc; 3484 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr); 3485 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58); 3486 rfcsr &= (~0x3F); 3487 rfcsr |= tx_agc_fc; 3488 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr); 3489 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59); 3490 rfcsr &= (~0x3F); 3491 rfcsr |= tx_agc_fc; 3492 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr); 3493 } 3494 } 3495 3496 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev, 3497 struct ieee80211_channel *chan, 3498 int power_level) { 3499 u16 eeprom, target_power, max_power; 3500 u32 mac_sys_ctrl, mac_status; 3501 u32 reg; 3502 u8 bbp; 3503 int i; 3504 3505 /* hardware unit is 0.5dBm, limited to 23.5dBm */ 3506 power_level *= 2; 3507 if (power_level > 0x2f) 3508 power_level = 0x2f; 3509 3510 max_power = chan->max_power * 2; 3511 if (max_power > 0x2f) 3512 max_power = 0x2f; 3513 3514 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0); 3515 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, power_level); 3516 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, power_level); 3517 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, max_power); 3518 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, max_power); 3519 3520 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 3521 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) { 3522 /* init base power by eeprom target power */ 3523 target_power = rt2800_eeprom_read(rt2x00dev, 3524 EEPROM_TXPOWER_INIT); 3525 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power); 3526 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power); 3527 } 3528 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg); 3529 3530 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 3531 rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0); 3532 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 3533 3534 /* Save MAC SYS CTRL registers */ 3535 mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 3536 /* Disable Tx/Rx */ 3537 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 3538 /* Check MAC Tx/Rx idle */ 3539 for (i = 0; i < 10000; i++) { 3540 mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 3541 if (mac_status & 0x3) 3542 usleep_range(50, 200); 3543 else 3544 break; 3545 } 3546 3547 if (i == 10000) 3548 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n"); 3549 3550 if (chan->center_freq > 2457) { 3551 bbp = rt2800_bbp_read(rt2x00dev, 30); 3552 bbp = 0x40; 3553 rt2800_bbp_write(rt2x00dev, 30, bbp); 3554 rt2800_rfcsr_write(rt2x00dev, 39, 0); 3555 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3556 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb); 3557 else 3558 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b); 3559 } else { 3560 bbp = rt2800_bbp_read(rt2x00dev, 30); 3561 bbp = 0x1f; 3562 rt2800_bbp_write(rt2x00dev, 30, bbp); 3563 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 3564 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3565 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb); 3566 else 3567 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); 3568 } 3569 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl); 3570 3571 rt2800_vco_calibration(rt2x00dev); 3572 } 3573 3574 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, 3575 const unsigned int word, 3576 const u8 value) 3577 { 3578 u8 chain, reg; 3579 3580 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) { 3581 reg = rt2800_bbp_read(rt2x00dev, 27); 3582 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); 3583 rt2800_bbp_write(rt2x00dev, 27, reg); 3584 3585 rt2800_bbp_write(rt2x00dev, word, value); 3586 } 3587 } 3588 3589 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel) 3590 { 3591 u8 cal; 3592 3593 /* TX0 IQ Gain */ 3594 rt2800_bbp_write(rt2x00dev, 158, 0x2c); 3595 if (channel <= 14) 3596 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G); 3597 else if (channel >= 36 && channel <= 64) 3598 cal = rt2x00_eeprom_byte(rt2x00dev, 3599 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G); 3600 else if (channel >= 100 && channel <= 138) 3601 cal = rt2x00_eeprom_byte(rt2x00dev, 3602 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G); 3603 else if (channel >= 140 && channel <= 165) 3604 cal = rt2x00_eeprom_byte(rt2x00dev, 3605 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G); 3606 else 3607 cal = 0; 3608 rt2800_bbp_write(rt2x00dev, 159, cal); 3609 3610 /* TX0 IQ Phase */ 3611 rt2800_bbp_write(rt2x00dev, 158, 0x2d); 3612 if (channel <= 14) 3613 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G); 3614 else if (channel >= 36 && channel <= 64) 3615 cal = rt2x00_eeprom_byte(rt2x00dev, 3616 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G); 3617 else if (channel >= 100 && channel <= 138) 3618 cal = rt2x00_eeprom_byte(rt2x00dev, 3619 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G); 3620 else if (channel >= 140 && channel <= 165) 3621 cal = rt2x00_eeprom_byte(rt2x00dev, 3622 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G); 3623 else 3624 cal = 0; 3625 rt2800_bbp_write(rt2x00dev, 159, cal); 3626 3627 /* TX1 IQ Gain */ 3628 rt2800_bbp_write(rt2x00dev, 158, 0x4a); 3629 if (channel <= 14) 3630 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G); 3631 else if (channel >= 36 && channel <= 64) 3632 cal = rt2x00_eeprom_byte(rt2x00dev, 3633 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G); 3634 else if (channel >= 100 && channel <= 138) 3635 cal = rt2x00_eeprom_byte(rt2x00dev, 3636 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G); 3637 else if (channel >= 140 && channel <= 165) 3638 cal = rt2x00_eeprom_byte(rt2x00dev, 3639 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G); 3640 else 3641 cal = 0; 3642 rt2800_bbp_write(rt2x00dev, 159, cal); 3643 3644 /* TX1 IQ Phase */ 3645 rt2800_bbp_write(rt2x00dev, 158, 0x4b); 3646 if (channel <= 14) 3647 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G); 3648 else if (channel >= 36 && channel <= 64) 3649 cal = rt2x00_eeprom_byte(rt2x00dev, 3650 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G); 3651 else if (channel >= 100 && channel <= 138) 3652 cal = rt2x00_eeprom_byte(rt2x00dev, 3653 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G); 3654 else if (channel >= 140 && channel <= 165) 3655 cal = rt2x00_eeprom_byte(rt2x00dev, 3656 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G); 3657 else 3658 cal = 0; 3659 rt2800_bbp_write(rt2x00dev, 159, cal); 3660 3661 /* FIXME: possible RX0, RX1 callibration ? */ 3662 3663 /* RF IQ compensation control */ 3664 rt2800_bbp_write(rt2x00dev, 158, 0x04); 3665 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL); 3666 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3667 3668 /* RF IQ imbalance compensation control */ 3669 rt2800_bbp_write(rt2x00dev, 158, 0x03); 3670 cal = rt2x00_eeprom_byte(rt2x00dev, 3671 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL); 3672 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3673 } 3674 3675 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev, 3676 unsigned int channel, 3677 char txpower) 3678 { 3679 if (rt2x00_rt(rt2x00dev, RT3593)) 3680 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC); 3681 3682 if (channel <= 14) 3683 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER); 3684 3685 if (rt2x00_rt(rt2x00dev, RT3593)) 3686 return clamp_t(char, txpower, MIN_A_TXPOWER_3593, 3687 MAX_A_TXPOWER_3593); 3688 else 3689 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER); 3690 } 3691 3692 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 3693 struct ieee80211_conf *conf, 3694 struct rf_channel *rf, 3695 struct channel_info *info) 3696 { 3697 u32 reg; 3698 u32 tx_pin; 3699 u8 bbp, rfcsr; 3700 3701 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3702 info->default_power1); 3703 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3704 info->default_power2); 3705 if (rt2x00dev->default_ant.tx_chain_num > 2) 3706 info->default_power3 = 3707 rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3708 info->default_power3); 3709 3710 switch (rt2x00dev->chip.rf) { 3711 case RF2020: 3712 case RF3020: 3713 case RF3021: 3714 case RF3022: 3715 case RF3320: 3716 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 3717 break; 3718 case RF3052: 3719 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); 3720 break; 3721 case RF3053: 3722 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info); 3723 break; 3724 case RF3290: 3725 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info); 3726 break; 3727 case RF3322: 3728 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); 3729 break; 3730 case RF3070: 3731 case RF5350: 3732 case RF5360: 3733 case RF5362: 3734 case RF5370: 3735 case RF5372: 3736 case RF5390: 3737 case RF5392: 3738 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); 3739 break; 3740 case RF5592: 3741 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info); 3742 break; 3743 case RF7620: 3744 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info); 3745 break; 3746 default: 3747 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 3748 } 3749 3750 if (rt2x00_rf(rt2x00dev, RF3070) || 3751 rt2x00_rf(rt2x00dev, RF3290) || 3752 rt2x00_rf(rt2x00dev, RF3322) || 3753 rt2x00_rf(rt2x00dev, RF5350) || 3754 rt2x00_rf(rt2x00dev, RF5360) || 3755 rt2x00_rf(rt2x00dev, RF5362) || 3756 rt2x00_rf(rt2x00dev, RF5370) || 3757 rt2x00_rf(rt2x00dev, RF5372) || 3758 rt2x00_rf(rt2x00dev, RF5390) || 3759 rt2x00_rf(rt2x00dev, RF5392)) { 3760 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 3761 if (rt2x00_rf(rt2x00dev, RF3322)) { 3762 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M, 3763 conf_is_ht40(conf)); 3764 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M, 3765 conf_is_ht40(conf)); 3766 } else { 3767 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 3768 conf_is_ht40(conf)); 3769 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 3770 conf_is_ht40(conf)); 3771 } 3772 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 3773 3774 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3775 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3776 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3777 } 3778 3779 /* 3780 * Change BBP settings 3781 */ 3782 3783 if (rt2x00_rt(rt2x00dev, RT3352)) { 3784 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3785 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3786 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3787 3788 rt2800_bbp_write(rt2x00dev, 27, 0x0); 3789 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 3790 rt2800_bbp_write(rt2x00dev, 27, 0x20); 3791 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 3792 rt2800_bbp_write(rt2x00dev, 86, 0x38); 3793 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 3794 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 3795 if (rf->channel > 14) { 3796 /* Disable CCK Packet detection on 5GHz */ 3797 rt2800_bbp_write(rt2x00dev, 70, 0x00); 3798 } else { 3799 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 3800 } 3801 3802 if (conf_is_ht40(conf)) 3803 rt2800_bbp_write(rt2x00dev, 105, 0x04); 3804 else 3805 rt2800_bbp_write(rt2x00dev, 105, 0x34); 3806 3807 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3808 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3809 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3810 rt2800_bbp_write(rt2x00dev, 77, 0x98); 3811 } else { 3812 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3813 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3814 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3815 rt2800_bbp_write(rt2x00dev, 86, 0); 3816 } 3817 3818 if (rf->channel <= 14) { 3819 if (!rt2x00_rt(rt2x00dev, RT5390) && 3820 !rt2x00_rt(rt2x00dev, RT5392) && 3821 !rt2x00_rt(rt2x00dev, RT6352)) { 3822 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 3823 rt2800_bbp_write(rt2x00dev, 82, 0x62); 3824 rt2800_bbp_write(rt2x00dev, 75, 0x46); 3825 } else { 3826 if (rt2x00_rt(rt2x00dev, RT3593)) 3827 rt2800_bbp_write(rt2x00dev, 82, 0x62); 3828 else 3829 rt2800_bbp_write(rt2x00dev, 82, 0x84); 3830 rt2800_bbp_write(rt2x00dev, 75, 0x50); 3831 } 3832 if (rt2x00_rt(rt2x00dev, RT3593)) 3833 rt2800_bbp_write(rt2x00dev, 83, 0x8a); 3834 } 3835 3836 } else { 3837 if (rt2x00_rt(rt2x00dev, RT3572)) 3838 rt2800_bbp_write(rt2x00dev, 82, 0x94); 3839 else if (rt2x00_rt(rt2x00dev, RT3593)) 3840 rt2800_bbp_write(rt2x00dev, 82, 0x82); 3841 else if (!rt2x00_rt(rt2x00dev, RT6352)) 3842 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 3843 3844 if (rt2x00_rt(rt2x00dev, RT3593)) 3845 rt2800_bbp_write(rt2x00dev, 83, 0x9a); 3846 3847 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) 3848 rt2800_bbp_write(rt2x00dev, 75, 0x46); 3849 else 3850 rt2800_bbp_write(rt2x00dev, 75, 0x50); 3851 } 3852 3853 reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG); 3854 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); 3855 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); 3856 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); 3857 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); 3858 3859 if (rt2x00_rt(rt2x00dev, RT3572)) 3860 rt2800_rfcsr_write(rt2x00dev, 8, 0); 3861 3862 if (rt2x00_rt(rt2x00dev, RT6352)) 3863 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 3864 else 3865 tx_pin = 0; 3866 3867 switch (rt2x00dev->default_ant.tx_chain_num) { 3868 case 3: 3869 /* Turn on tertiary PAs */ 3870 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 3871 rf->channel > 14); 3872 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 3873 rf->channel <= 14); 3874 /* fall-through */ 3875 case 2: 3876 /* Turn on secondary PAs */ 3877 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 3878 rf->channel > 14); 3879 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 3880 rf->channel <= 14); 3881 /* fall-through */ 3882 case 1: 3883 /* Turn on primary PAs */ 3884 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 3885 rf->channel > 14); 3886 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) 3887 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 3888 else 3889 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 3890 rf->channel <= 14); 3891 break; 3892 } 3893 3894 switch (rt2x00dev->default_ant.rx_chain_num) { 3895 case 3: 3896 /* Turn on tertiary LNAs */ 3897 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1); 3898 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1); 3899 /* fall-through */ 3900 case 2: 3901 /* Turn on secondary LNAs */ 3902 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); 3903 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); 3904 /* fall-through */ 3905 case 1: 3906 /* Turn on primary LNAs */ 3907 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); 3908 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); 3909 break; 3910 } 3911 3912 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); 3913 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); 3914 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); /* mt7620 */ 3915 3916 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 3917 3918 if (rt2x00_rt(rt2x00dev, RT3572)) { 3919 rt2800_rfcsr_write(rt2x00dev, 8, 0x80); 3920 3921 /* AGC init */ 3922 if (rf->channel <= 14) 3923 reg = 0x1c + (2 * rt2x00dev->lna_gain); 3924 else 3925 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 3926 3927 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3928 } 3929 3930 if (rt2x00_rt(rt2x00dev, RT3593)) { 3931 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 3932 3933 /* Band selection */ 3934 if (rt2x00_is_usb(rt2x00dev) || 3935 rt2x00_is_pcie(rt2x00dev)) { 3936 /* GPIO #8 controls all paths */ 3937 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); 3938 if (rf->channel <= 14) 3939 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); 3940 else 3941 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); 3942 } 3943 3944 /* LNA PE control. */ 3945 if (rt2x00_is_usb(rt2x00dev)) { 3946 /* GPIO #4 controls PE0 and PE1, 3947 * GPIO #7 controls PE2 3948 */ 3949 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 3950 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 3951 3952 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 3953 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 3954 } else if (rt2x00_is_pcie(rt2x00dev)) { 3955 /* GPIO #4 controls PE0, PE1 and PE2 */ 3956 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 3957 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 3958 } 3959 3960 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 3961 3962 /* AGC init */ 3963 if (rf->channel <= 14) 3964 reg = 0x1c + 2 * rt2x00dev->lna_gain; 3965 else 3966 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 3967 3968 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3969 3970 usleep_range(1000, 1500); 3971 } 3972 3973 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) { 3974 reg = 0x10; 3975 if (!conf_is_ht40(conf)) { 3976 if (rt2x00_rt(rt2x00dev, RT6352) && 3977 rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 3978 reg |= 0x5; 3979 } else { 3980 reg |= 0xa; 3981 } 3982 } 3983 rt2800_bbp_write(rt2x00dev, 195, 141); 3984 rt2800_bbp_write(rt2x00dev, 196, reg); 3985 3986 /* AGC init */ 3987 if (rt2x00_rt(rt2x00dev, RT6352)) 3988 reg = 0x04; 3989 else 3990 reg = rf->channel <= 14 ? 0x1c : 0x24; 3991 3992 reg += 2 * rt2x00dev->lna_gain; 3993 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3994 3995 rt2800_iq_calibrate(rt2x00dev, rf->channel); 3996 } 3997 3998 bbp = rt2800_bbp_read(rt2x00dev, 4); 3999 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 4000 rt2800_bbp_write(rt2x00dev, 4, bbp); 4001 4002 bbp = rt2800_bbp_read(rt2x00dev, 3); 4003 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); 4004 rt2800_bbp_write(rt2x00dev, 3, bbp); 4005 4006 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 4007 if (conf_is_ht40(conf)) { 4008 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 4009 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4010 rt2800_bbp_write(rt2x00dev, 73, 0x16); 4011 } else { 4012 rt2800_bbp_write(rt2x00dev, 69, 0x16); 4013 rt2800_bbp_write(rt2x00dev, 70, 0x08); 4014 rt2800_bbp_write(rt2x00dev, 73, 0x11); 4015 } 4016 } 4017 4018 usleep_range(1000, 1500); 4019 4020 /* 4021 * Clear channel statistic counters 4022 */ 4023 reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 4024 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 4025 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 4026 4027 /* 4028 * Clear update flag 4029 */ 4030 if (rt2x00_rt(rt2x00dev, RT3352) || 4031 rt2x00_rt(rt2x00dev, RT5350)) { 4032 bbp = rt2800_bbp_read(rt2x00dev, 49); 4033 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0); 4034 rt2800_bbp_write(rt2x00dev, 49, bbp); 4035 } 4036 } 4037 4038 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) 4039 { 4040 u8 tssi_bounds[9]; 4041 u8 current_tssi; 4042 u16 eeprom; 4043 u8 step; 4044 int i; 4045 4046 /* 4047 * First check if temperature compensation is supported. 4048 */ 4049 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 4050 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC)) 4051 return 0; 4052 4053 /* 4054 * Read TSSI boundaries for temperature compensation from 4055 * the EEPROM. 4056 * 4057 * Array idx 0 1 2 3 4 5 6 7 8 4058 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4 4059 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 4060 */ 4061 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 4062 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1); 4063 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4064 EEPROM_TSSI_BOUND_BG1_MINUS4); 4065 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4066 EEPROM_TSSI_BOUND_BG1_MINUS3); 4067 4068 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2); 4069 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4070 EEPROM_TSSI_BOUND_BG2_MINUS2); 4071 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4072 EEPROM_TSSI_BOUND_BG2_MINUS1); 4073 4074 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3); 4075 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4076 EEPROM_TSSI_BOUND_BG3_REF); 4077 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4078 EEPROM_TSSI_BOUND_BG3_PLUS1); 4079 4080 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4); 4081 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4082 EEPROM_TSSI_BOUND_BG4_PLUS2); 4083 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4084 EEPROM_TSSI_BOUND_BG4_PLUS3); 4085 4086 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5); 4087 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4088 EEPROM_TSSI_BOUND_BG5_PLUS4); 4089 4090 step = rt2x00_get_field16(eeprom, 4091 EEPROM_TSSI_BOUND_BG5_AGC_STEP); 4092 } else { 4093 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1); 4094 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4095 EEPROM_TSSI_BOUND_A1_MINUS4); 4096 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4097 EEPROM_TSSI_BOUND_A1_MINUS3); 4098 4099 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2); 4100 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4101 EEPROM_TSSI_BOUND_A2_MINUS2); 4102 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4103 EEPROM_TSSI_BOUND_A2_MINUS1); 4104 4105 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3); 4106 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4107 EEPROM_TSSI_BOUND_A3_REF); 4108 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4109 EEPROM_TSSI_BOUND_A3_PLUS1); 4110 4111 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4); 4112 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4113 EEPROM_TSSI_BOUND_A4_PLUS2); 4114 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4115 EEPROM_TSSI_BOUND_A4_PLUS3); 4116 4117 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5); 4118 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4119 EEPROM_TSSI_BOUND_A5_PLUS4); 4120 4121 step = rt2x00_get_field16(eeprom, 4122 EEPROM_TSSI_BOUND_A5_AGC_STEP); 4123 } 4124 4125 /* 4126 * Check if temperature compensation is supported. 4127 */ 4128 if (tssi_bounds[4] == 0xff || step == 0xff) 4129 return 0; 4130 4131 /* 4132 * Read current TSSI (BBP 49). 4133 */ 4134 current_tssi = rt2800_bbp_read(rt2x00dev, 49); 4135 4136 /* 4137 * Compare TSSI value (BBP49) with the compensation boundaries 4138 * from the EEPROM and increase or decrease tx power. 4139 */ 4140 for (i = 0; i <= 3; i++) { 4141 if (current_tssi > tssi_bounds[i]) 4142 break; 4143 } 4144 4145 if (i == 4) { 4146 for (i = 8; i >= 5; i--) { 4147 if (current_tssi < tssi_bounds[i]) 4148 break; 4149 } 4150 } 4151 4152 return (i - 4) * step; 4153 } 4154 4155 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, 4156 enum nl80211_band band) 4157 { 4158 u16 eeprom; 4159 u8 comp_en; 4160 u8 comp_type; 4161 int comp_value = 0; 4162 4163 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA); 4164 4165 /* 4166 * HT40 compensation not required. 4167 */ 4168 if (eeprom == 0xffff || 4169 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4170 return 0; 4171 4172 if (band == NL80211_BAND_2GHZ) { 4173 comp_en = rt2x00_get_field16(eeprom, 4174 EEPROM_TXPOWER_DELTA_ENABLE_2G); 4175 if (comp_en) { 4176 comp_type = rt2x00_get_field16(eeprom, 4177 EEPROM_TXPOWER_DELTA_TYPE_2G); 4178 comp_value = rt2x00_get_field16(eeprom, 4179 EEPROM_TXPOWER_DELTA_VALUE_2G); 4180 if (!comp_type) 4181 comp_value = -comp_value; 4182 } 4183 } else { 4184 comp_en = rt2x00_get_field16(eeprom, 4185 EEPROM_TXPOWER_DELTA_ENABLE_5G); 4186 if (comp_en) { 4187 comp_type = rt2x00_get_field16(eeprom, 4188 EEPROM_TXPOWER_DELTA_TYPE_5G); 4189 comp_value = rt2x00_get_field16(eeprom, 4190 EEPROM_TXPOWER_DELTA_VALUE_5G); 4191 if (!comp_type) 4192 comp_value = -comp_value; 4193 } 4194 } 4195 4196 return comp_value; 4197 } 4198 4199 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev, 4200 int power_level, int max_power) 4201 { 4202 int delta; 4203 4204 if (rt2x00_has_cap_power_limit(rt2x00dev)) 4205 return 0; 4206 4207 /* 4208 * XXX: We don't know the maximum transmit power of our hardware since 4209 * the EEPROM doesn't expose it. We only know that we are calibrated 4210 * to 100% tx power. 4211 * 4212 * Hence, we assume the regulatory limit that cfg80211 calulated for 4213 * the current channel is our maximum and if we are requested to lower 4214 * the value we just reduce our tx power accordingly. 4215 */ 4216 delta = power_level - max_power; 4217 return min(delta, 0); 4218 } 4219 4220 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, 4221 enum nl80211_band band, int power_level, 4222 u8 txpower, int delta) 4223 { 4224 u16 eeprom; 4225 u8 criterion; 4226 u8 eirp_txpower; 4227 u8 eirp_txpower_criterion; 4228 u8 reg_limit; 4229 4230 if (rt2x00_rt(rt2x00dev, RT3593)) 4231 return min_t(u8, txpower, 0xc); 4232 4233 if (rt2x00_has_cap_power_limit(rt2x00dev)) { 4234 /* 4235 * Check if eirp txpower exceed txpower_limit. 4236 * We use OFDM 6M as criterion and its eirp txpower 4237 * is stored at EEPROM_EIRP_MAX_TX_POWER. 4238 * .11b data rate need add additional 4dbm 4239 * when calculating eirp txpower. 4240 */ 4241 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4242 EEPROM_TXPOWER_BYRATE, 4243 1); 4244 criterion = rt2x00_get_field16(eeprom, 4245 EEPROM_TXPOWER_BYRATE_RATE0); 4246 4247 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 4248 4249 if (band == NL80211_BAND_2GHZ) 4250 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4251 EEPROM_EIRP_MAX_TX_POWER_2GHZ); 4252 else 4253 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4254 EEPROM_EIRP_MAX_TX_POWER_5GHZ); 4255 4256 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) + 4257 (is_rate_b ? 4 : 0) + delta; 4258 4259 reg_limit = (eirp_txpower > power_level) ? 4260 (eirp_txpower - power_level) : 0; 4261 } else 4262 reg_limit = 0; 4263 4264 txpower = max(0, txpower + delta - reg_limit); 4265 return min_t(u8, txpower, 0xc); 4266 } 4267 4268 4269 enum { 4270 TX_PWR_CFG_0_IDX, 4271 TX_PWR_CFG_1_IDX, 4272 TX_PWR_CFG_2_IDX, 4273 TX_PWR_CFG_3_IDX, 4274 TX_PWR_CFG_4_IDX, 4275 TX_PWR_CFG_5_IDX, 4276 TX_PWR_CFG_6_IDX, 4277 TX_PWR_CFG_7_IDX, 4278 TX_PWR_CFG_8_IDX, 4279 TX_PWR_CFG_9_IDX, 4280 TX_PWR_CFG_0_EXT_IDX, 4281 TX_PWR_CFG_1_EXT_IDX, 4282 TX_PWR_CFG_2_EXT_IDX, 4283 TX_PWR_CFG_3_EXT_IDX, 4284 TX_PWR_CFG_4_EXT_IDX, 4285 TX_PWR_CFG_IDX_COUNT, 4286 }; 4287 4288 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, 4289 struct ieee80211_channel *chan, 4290 int power_level) 4291 { 4292 u8 txpower; 4293 u16 eeprom; 4294 u32 regs[TX_PWR_CFG_IDX_COUNT]; 4295 unsigned int offset; 4296 enum nl80211_band band = chan->band; 4297 int delta; 4298 int i; 4299 4300 memset(regs, '\0', sizeof(regs)); 4301 4302 /* TODO: adapt TX power reduction from the rt28xx code */ 4303 4304 /* calculate temperature compensation delta */ 4305 delta = rt2800_get_gain_calibration_delta(rt2x00dev); 4306 4307 if (band == NL80211_BAND_5GHZ) 4308 offset = 16; 4309 else 4310 offset = 0; 4311 4312 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4313 offset += 8; 4314 4315 /* read the next four txpower values */ 4316 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4317 offset); 4318 4319 /* CCK 1MBS,2MBS */ 4320 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4321 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4322 txpower, delta); 4323 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4324 TX_PWR_CFG_0_CCK1_CH0, txpower); 4325 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4326 TX_PWR_CFG_0_CCK1_CH1, txpower); 4327 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4328 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower); 4329 4330 /* CCK 5.5MBS,11MBS */ 4331 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4332 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4333 txpower, delta); 4334 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4335 TX_PWR_CFG_0_CCK5_CH0, txpower); 4336 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4337 TX_PWR_CFG_0_CCK5_CH1, txpower); 4338 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4339 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower); 4340 4341 /* OFDM 6MBS,9MBS */ 4342 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4343 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4344 txpower, delta); 4345 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4346 TX_PWR_CFG_0_OFDM6_CH0, txpower); 4347 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4348 TX_PWR_CFG_0_OFDM6_CH1, txpower); 4349 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4350 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower); 4351 4352 /* OFDM 12MBS,18MBS */ 4353 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4354 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4355 txpower, delta); 4356 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4357 TX_PWR_CFG_0_OFDM12_CH0, txpower); 4358 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4359 TX_PWR_CFG_0_OFDM12_CH1, txpower); 4360 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4361 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower); 4362 4363 /* read the next four txpower values */ 4364 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4365 offset + 1); 4366 4367 /* OFDM 24MBS,36MBS */ 4368 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4369 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4370 txpower, delta); 4371 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4372 TX_PWR_CFG_1_OFDM24_CH0, txpower); 4373 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4374 TX_PWR_CFG_1_OFDM24_CH1, txpower); 4375 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4376 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower); 4377 4378 /* OFDM 48MBS */ 4379 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4380 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4381 txpower, delta); 4382 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4383 TX_PWR_CFG_1_OFDM48_CH0, txpower); 4384 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4385 TX_PWR_CFG_1_OFDM48_CH1, txpower); 4386 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4387 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower); 4388 4389 /* OFDM 54MBS */ 4390 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4391 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4392 txpower, delta); 4393 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4394 TX_PWR_CFG_7_OFDM54_CH0, txpower); 4395 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4396 TX_PWR_CFG_7_OFDM54_CH1, txpower); 4397 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4398 TX_PWR_CFG_7_OFDM54_CH2, txpower); 4399 4400 /* read the next four txpower values */ 4401 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4402 offset + 2); 4403 4404 /* MCS 0,1 */ 4405 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4406 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4407 txpower, delta); 4408 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4409 TX_PWR_CFG_1_MCS0_CH0, txpower); 4410 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4411 TX_PWR_CFG_1_MCS0_CH1, txpower); 4412 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4413 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower); 4414 4415 /* MCS 2,3 */ 4416 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4417 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4418 txpower, delta); 4419 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4420 TX_PWR_CFG_1_MCS2_CH0, txpower); 4421 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4422 TX_PWR_CFG_1_MCS2_CH1, txpower); 4423 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4424 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower); 4425 4426 /* MCS 4,5 */ 4427 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4428 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4429 txpower, delta); 4430 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4431 TX_PWR_CFG_2_MCS4_CH0, txpower); 4432 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4433 TX_PWR_CFG_2_MCS4_CH1, txpower); 4434 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4435 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower); 4436 4437 /* MCS 6 */ 4438 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4439 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4440 txpower, delta); 4441 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4442 TX_PWR_CFG_2_MCS6_CH0, txpower); 4443 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4444 TX_PWR_CFG_2_MCS6_CH1, txpower); 4445 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4446 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower); 4447 4448 /* read the next four txpower values */ 4449 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4450 offset + 3); 4451 4452 /* MCS 7 */ 4453 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4454 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4455 txpower, delta); 4456 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4457 TX_PWR_CFG_7_MCS7_CH0, txpower); 4458 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4459 TX_PWR_CFG_7_MCS7_CH1, txpower); 4460 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4461 TX_PWR_CFG_7_MCS7_CH2, txpower); 4462 4463 /* MCS 8,9 */ 4464 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4465 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4466 txpower, delta); 4467 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4468 TX_PWR_CFG_2_MCS8_CH0, txpower); 4469 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4470 TX_PWR_CFG_2_MCS8_CH1, txpower); 4471 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4472 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower); 4473 4474 /* MCS 10,11 */ 4475 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4476 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4477 txpower, delta); 4478 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4479 TX_PWR_CFG_2_MCS10_CH0, txpower); 4480 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4481 TX_PWR_CFG_2_MCS10_CH1, txpower); 4482 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4483 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower); 4484 4485 /* MCS 12,13 */ 4486 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4487 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4488 txpower, delta); 4489 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4490 TX_PWR_CFG_3_MCS12_CH0, txpower); 4491 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4492 TX_PWR_CFG_3_MCS12_CH1, txpower); 4493 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4494 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower); 4495 4496 /* read the next four txpower values */ 4497 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4498 offset + 4); 4499 4500 /* MCS 14 */ 4501 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4502 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4503 txpower, delta); 4504 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4505 TX_PWR_CFG_3_MCS14_CH0, txpower); 4506 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4507 TX_PWR_CFG_3_MCS14_CH1, txpower); 4508 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4509 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower); 4510 4511 /* MCS 15 */ 4512 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4513 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4514 txpower, delta); 4515 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4516 TX_PWR_CFG_8_MCS15_CH0, txpower); 4517 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4518 TX_PWR_CFG_8_MCS15_CH1, txpower); 4519 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4520 TX_PWR_CFG_8_MCS15_CH2, txpower); 4521 4522 /* MCS 16,17 */ 4523 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4524 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4525 txpower, delta); 4526 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4527 TX_PWR_CFG_5_MCS16_CH0, txpower); 4528 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4529 TX_PWR_CFG_5_MCS16_CH1, txpower); 4530 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4531 TX_PWR_CFG_5_MCS16_CH2, txpower); 4532 4533 /* MCS 18,19 */ 4534 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4535 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4536 txpower, delta); 4537 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4538 TX_PWR_CFG_5_MCS18_CH0, txpower); 4539 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4540 TX_PWR_CFG_5_MCS18_CH1, txpower); 4541 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4542 TX_PWR_CFG_5_MCS18_CH2, txpower); 4543 4544 /* read the next four txpower values */ 4545 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4546 offset + 5); 4547 4548 /* MCS 20,21 */ 4549 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4550 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4551 txpower, delta); 4552 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4553 TX_PWR_CFG_6_MCS20_CH0, txpower); 4554 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4555 TX_PWR_CFG_6_MCS20_CH1, txpower); 4556 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4557 TX_PWR_CFG_6_MCS20_CH2, txpower); 4558 4559 /* MCS 22 */ 4560 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4561 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4562 txpower, delta); 4563 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4564 TX_PWR_CFG_6_MCS22_CH0, txpower); 4565 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4566 TX_PWR_CFG_6_MCS22_CH1, txpower); 4567 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4568 TX_PWR_CFG_6_MCS22_CH2, txpower); 4569 4570 /* MCS 23 */ 4571 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4572 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4573 txpower, delta); 4574 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4575 TX_PWR_CFG_8_MCS23_CH0, txpower); 4576 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4577 TX_PWR_CFG_8_MCS23_CH1, txpower); 4578 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4579 TX_PWR_CFG_8_MCS23_CH2, txpower); 4580 4581 /* read the next four txpower values */ 4582 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4583 offset + 6); 4584 4585 /* STBC, MCS 0,1 */ 4586 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4587 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4588 txpower, delta); 4589 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4590 TX_PWR_CFG_3_STBC0_CH0, txpower); 4591 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4592 TX_PWR_CFG_3_STBC0_CH1, txpower); 4593 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4594 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower); 4595 4596 /* STBC, MCS 2,3 */ 4597 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4598 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4599 txpower, delta); 4600 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4601 TX_PWR_CFG_3_STBC2_CH0, txpower); 4602 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4603 TX_PWR_CFG_3_STBC2_CH1, txpower); 4604 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4605 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower); 4606 4607 /* STBC, MCS 4,5 */ 4608 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4609 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4610 txpower, delta); 4611 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); 4612 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); 4613 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, 4614 txpower); 4615 4616 /* STBC, MCS 6 */ 4617 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4618 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4619 txpower, delta); 4620 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); 4621 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); 4622 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, 4623 txpower); 4624 4625 /* read the next four txpower values */ 4626 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4627 offset + 7); 4628 4629 /* STBC, MCS 7 */ 4630 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4631 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4632 txpower, delta); 4633 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4634 TX_PWR_CFG_9_STBC7_CH0, txpower); 4635 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4636 TX_PWR_CFG_9_STBC7_CH1, txpower); 4637 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4638 TX_PWR_CFG_9_STBC7_CH2, txpower); 4639 4640 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]); 4641 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]); 4642 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]); 4643 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]); 4644 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]); 4645 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]); 4646 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]); 4647 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]); 4648 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]); 4649 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]); 4650 4651 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT, 4652 regs[TX_PWR_CFG_0_EXT_IDX]); 4653 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT, 4654 regs[TX_PWR_CFG_1_EXT_IDX]); 4655 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT, 4656 regs[TX_PWR_CFG_2_EXT_IDX]); 4657 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT, 4658 regs[TX_PWR_CFG_3_EXT_IDX]); 4659 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT, 4660 regs[TX_PWR_CFG_4_EXT_IDX]); 4661 4662 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++) 4663 rt2x00_dbg(rt2x00dev, 4664 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n", 4665 (band == NL80211_BAND_5GHZ) ? '5' : '2', 4666 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ? 4667 '4' : '2', 4668 (i > TX_PWR_CFG_9_IDX) ? 4669 (i - TX_PWR_CFG_9_IDX - 1) : i, 4670 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "", 4671 (unsigned long) regs[i]); 4672 } 4673 4674 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev, 4675 struct ieee80211_channel *chan, 4676 int power_level) 4677 { 4678 u32 reg, pwreg; 4679 u16 eeprom; 4680 u32 data, gdata; 4681 u8 t, i; 4682 enum nl80211_band band = chan->band; 4683 int delta; 4684 4685 /* Warn user if bw_comp is set in EEPROM */ 4686 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 4687 4688 if (delta) 4689 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n", 4690 delta); 4691 4692 /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit 4693 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor 4694 * driver does as well, though it looks kinda wrong. 4695 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe 4696 * the hardware has a problem handling 0x20, and as the code initially 4697 * used a fixed offset between HT20 and HT40 rates they had to work- 4698 * around that issue and most likely just forgot about it later on. 4699 * Maybe we should use rt2800_get_txpower_bw_comp() here as well, 4700 * however, the corresponding EEPROM value is not respected by the 4701 * vendor driver, so maybe this is rather being taken care of the 4702 * TXALC and the driver doesn't need to handle it...? 4703 * Though this is all very awkward, just do as they did, as that's what 4704 * board vendors expected when they populated the EEPROM... 4705 */ 4706 for (i = 0; i < 5; i++) { 4707 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4708 EEPROM_TXPOWER_BYRATE, 4709 i * 2); 4710 4711 data = eeprom; 4712 4713 t = eeprom & 0x3f; 4714 if (t == 32) 4715 t++; 4716 4717 gdata = t; 4718 4719 t = (eeprom & 0x3f00) >> 8; 4720 if (t == 32) 4721 t++; 4722 4723 gdata |= (t << 8); 4724 4725 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4726 EEPROM_TXPOWER_BYRATE, 4727 (i * 2) + 1); 4728 4729 t = eeprom & 0x3f; 4730 if (t == 32) 4731 t++; 4732 4733 gdata |= (t << 16); 4734 4735 t = (eeprom & 0x3f00) >> 8; 4736 if (t == 32) 4737 t++; 4738 4739 gdata |= (t << 24); 4740 data |= (eeprom << 16); 4741 4742 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) { 4743 /* HT20 */ 4744 if (data != 0xffffffff) 4745 rt2800_register_write(rt2x00dev, 4746 TX_PWR_CFG_0 + (i * 4), 4747 data); 4748 } else { 4749 /* HT40 */ 4750 if (gdata != 0xffffffff) 4751 rt2800_register_write(rt2x00dev, 4752 TX_PWR_CFG_0 + (i * 4), 4753 gdata); 4754 } 4755 } 4756 4757 /* Aparently Ralink ran out of space in the BYRATE calibration section 4758 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x 4759 * registers. As recent 2T chips use 8-bit instead of 4-bit values for 4760 * power-offsets more space would be needed. Ralink decided to keep the 4761 * EEPROM layout untouched and rather have some shared values covering 4762 * multiple bitrates. 4763 * Populate the registers not covered by the EEPROM in the same way the 4764 * vendor driver does. 4765 */ 4766 4767 /* For OFDM 54MBS use value from OFDM 48MBS */ 4768 pwreg = 0; 4769 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1); 4770 t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS); 4771 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t); 4772 4773 /* For MCS 7 use value from MCS 6 */ 4774 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2); 4775 t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7); 4776 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t); 4777 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg); 4778 4779 /* For MCS 15 use value from MCS 14 */ 4780 pwreg = 0; 4781 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3); 4782 t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14); 4783 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t); 4784 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg); 4785 4786 /* For STBC MCS 7 use value from STBC MCS 6 */ 4787 pwreg = 0; 4788 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4); 4789 t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6); 4790 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); 4791 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg); 4792 4793 rt2800_config_alc(rt2x00dev, chan, power_level); 4794 4795 /* TODO: temperature compensation code! */ 4796 } 4797 4798 /* 4799 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and 4800 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values, 4801 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power 4802 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm. 4803 * Reference per rate transmit power values are located in the EEPROM at 4804 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to 4805 * current conditions (i.e. band, bandwidth, temperature, user settings). 4806 */ 4807 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, 4808 struct ieee80211_channel *chan, 4809 int power_level) 4810 { 4811 u8 txpower, r1; 4812 u16 eeprom; 4813 u32 reg, offset; 4814 int i, is_rate_b, delta, power_ctrl; 4815 enum nl80211_band band = chan->band; 4816 4817 /* 4818 * Calculate HT40 compensation. For 40MHz we need to add or subtract 4819 * value read from EEPROM (different for 2GHz and for 5GHz). 4820 */ 4821 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 4822 4823 /* 4824 * Calculate temperature compensation. Depends on measurement of current 4825 * TSSI (Transmitter Signal Strength Indication) we know TX power (due 4826 * to temperature or maybe other factors) is smaller or bigger than 4827 * expected. We adjust it, based on TSSI reference and boundaries values 4828 * provided in EEPROM. 4829 */ 4830 switch (rt2x00dev->chip.rt) { 4831 case RT2860: 4832 case RT2872: 4833 case RT2883: 4834 case RT3070: 4835 case RT3071: 4836 case RT3090: 4837 case RT3572: 4838 delta += rt2800_get_gain_calibration_delta(rt2x00dev); 4839 break; 4840 default: 4841 /* TODO: temperature compensation code for other chips. */ 4842 break; 4843 } 4844 4845 /* 4846 * Decrease power according to user settings, on devices with unknown 4847 * maximum tx power. For other devices we take user power_level into 4848 * consideration on rt2800_compensate_txpower(). 4849 */ 4850 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level, 4851 chan->max_power); 4852 4853 /* 4854 * BBP_R1 controls TX power for all rates, it allow to set the following 4855 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively. 4856 * 4857 * TODO: we do not use +6 dBm option to do not increase power beyond 4858 * regulatory limit, however this could be utilized for devices with 4859 * CAPABILITY_POWER_LIMIT. 4860 */ 4861 if (delta <= -12) { 4862 power_ctrl = 2; 4863 delta += 12; 4864 } else if (delta <= -6) { 4865 power_ctrl = 1; 4866 delta += 6; 4867 } else { 4868 power_ctrl = 0; 4869 } 4870 r1 = rt2800_bbp_read(rt2x00dev, 1); 4871 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl); 4872 rt2800_bbp_write(rt2x00dev, 1, r1); 4873 4874 offset = TX_PWR_CFG_0; 4875 4876 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { 4877 /* just to be safe */ 4878 if (offset > TX_PWR_CFG_4) 4879 break; 4880 4881 reg = rt2800_register_read(rt2x00dev, offset); 4882 4883 /* read the next four txpower values */ 4884 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4885 EEPROM_TXPOWER_BYRATE, 4886 i); 4887 4888 is_rate_b = i ? 0 : 1; 4889 /* 4890 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, 4891 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, 4892 * TX_PWR_CFG_4: unknown 4893 */ 4894 txpower = rt2x00_get_field16(eeprom, 4895 EEPROM_TXPOWER_BYRATE_RATE0); 4896 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4897 power_level, txpower, delta); 4898 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); 4899 4900 /* 4901 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, 4902 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, 4903 * TX_PWR_CFG_4: unknown 4904 */ 4905 txpower = rt2x00_get_field16(eeprom, 4906 EEPROM_TXPOWER_BYRATE_RATE1); 4907 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4908 power_level, txpower, delta); 4909 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); 4910 4911 /* 4912 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS, 4913 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, 4914 * TX_PWR_CFG_4: unknown 4915 */ 4916 txpower = rt2x00_get_field16(eeprom, 4917 EEPROM_TXPOWER_BYRATE_RATE2); 4918 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4919 power_level, txpower, delta); 4920 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); 4921 4922 /* 4923 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, 4924 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, 4925 * TX_PWR_CFG_4: unknown 4926 */ 4927 txpower = rt2x00_get_field16(eeprom, 4928 EEPROM_TXPOWER_BYRATE_RATE3); 4929 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4930 power_level, txpower, delta); 4931 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); 4932 4933 /* read the next four txpower values */ 4934 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4935 EEPROM_TXPOWER_BYRATE, 4936 i + 1); 4937 4938 is_rate_b = 0; 4939 /* 4940 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, 4941 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, 4942 * TX_PWR_CFG_4: unknown 4943 */ 4944 txpower = rt2x00_get_field16(eeprom, 4945 EEPROM_TXPOWER_BYRATE_RATE0); 4946 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4947 power_level, txpower, delta); 4948 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); 4949 4950 /* 4951 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, 4952 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, 4953 * TX_PWR_CFG_4: unknown 4954 */ 4955 txpower = rt2x00_get_field16(eeprom, 4956 EEPROM_TXPOWER_BYRATE_RATE1); 4957 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4958 power_level, txpower, delta); 4959 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); 4960 4961 /* 4962 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, 4963 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, 4964 * TX_PWR_CFG_4: unknown 4965 */ 4966 txpower = rt2x00_get_field16(eeprom, 4967 EEPROM_TXPOWER_BYRATE_RATE2); 4968 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4969 power_level, txpower, delta); 4970 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); 4971 4972 /* 4973 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, 4974 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, 4975 * TX_PWR_CFG_4: unknown 4976 */ 4977 txpower = rt2x00_get_field16(eeprom, 4978 EEPROM_TXPOWER_BYRATE_RATE3); 4979 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4980 power_level, txpower, delta); 4981 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); 4982 4983 rt2800_register_write(rt2x00dev, offset, reg); 4984 4985 /* next TX_PWR_CFG register */ 4986 offset += 4; 4987 } 4988 } 4989 4990 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, 4991 struct ieee80211_channel *chan, 4992 int power_level) 4993 { 4994 if (rt2x00_rt(rt2x00dev, RT3593)) 4995 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level); 4996 else if (rt2x00_rt(rt2x00dev, RT6352)) 4997 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level); 4998 else 4999 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level); 5000 } 5001 5002 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) 5003 { 5004 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan, 5005 rt2x00dev->tx_power); 5006 } 5007 EXPORT_SYMBOL_GPL(rt2800_gain_calibration); 5008 5009 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) 5010 { 5011 u32 tx_pin; 5012 u8 rfcsr; 5013 unsigned long min_sleep = 0; 5014 5015 /* 5016 * A voltage-controlled oscillator(VCO) is an electronic oscillator 5017 * designed to be controlled in oscillation frequency by a voltage 5018 * input. Maybe the temperature will affect the frequency of 5019 * oscillation to be shifted. The VCO calibration will be called 5020 * periodically to adjust the frequency to be precision. 5021 */ 5022 5023 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5024 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE; 5025 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5026 5027 switch (rt2x00dev->chip.rf) { 5028 case RF2020: 5029 case RF3020: 5030 case RF3021: 5031 case RF3022: 5032 case RF3320: 5033 case RF3052: 5034 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 5035 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 5036 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 5037 break; 5038 case RF3053: 5039 case RF3070: 5040 case RF3290: 5041 case RF5350: 5042 case RF5360: 5043 case RF5362: 5044 case RF5370: 5045 case RF5372: 5046 case RF5390: 5047 case RF5392: 5048 case RF5592: 5049 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 5050 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 5051 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 5052 min_sleep = 1000; 5053 break; 5054 case RF7620: 5055 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 5056 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 5057 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4); 5058 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1); 5059 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr); 5060 min_sleep = 2000; 5061 break; 5062 default: 5063 WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration", 5064 rt2x00dev->chip.rf); 5065 return; 5066 } 5067 5068 if (min_sleep > 0) 5069 usleep_range(min_sleep, min_sleep * 2); 5070 5071 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5072 if (rt2x00dev->rf_channel <= 14) { 5073 switch (rt2x00dev->default_ant.tx_chain_num) { 5074 case 3: 5075 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); 5076 /* fall through */ 5077 case 2: 5078 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 5079 /* fall through */ 5080 case 1: 5081 default: 5082 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 5083 break; 5084 } 5085 } else { 5086 switch (rt2x00dev->default_ant.tx_chain_num) { 5087 case 3: 5088 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); 5089 /* fall through */ 5090 case 2: 5091 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 5092 /* fall through */ 5093 case 1: 5094 default: 5095 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); 5096 break; 5097 } 5098 } 5099 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5100 5101 if (rt2x00_rt(rt2x00dev, RT6352)) { 5102 if (rt2x00dev->default_ant.rx_chain_num == 1) { 5103 rt2800_bbp_write(rt2x00dev, 91, 0x07); 5104 rt2800_bbp_write(rt2x00dev, 95, 0x1A); 5105 rt2800_bbp_write(rt2x00dev, 195, 128); 5106 rt2800_bbp_write(rt2x00dev, 196, 0xA0); 5107 rt2800_bbp_write(rt2x00dev, 195, 170); 5108 rt2800_bbp_write(rt2x00dev, 196, 0x12); 5109 rt2800_bbp_write(rt2x00dev, 195, 171); 5110 rt2800_bbp_write(rt2x00dev, 196, 0x10); 5111 } else { 5112 rt2800_bbp_write(rt2x00dev, 91, 0x06); 5113 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 5114 rt2800_bbp_write(rt2x00dev, 195, 128); 5115 rt2800_bbp_write(rt2x00dev, 196, 0xE0); 5116 rt2800_bbp_write(rt2x00dev, 195, 170); 5117 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5118 rt2800_bbp_write(rt2x00dev, 195, 171); 5119 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5120 } 5121 5122 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 5123 rt2800_bbp_write(rt2x00dev, 75, 0x68); 5124 rt2800_bbp_write(rt2x00dev, 76, 0x4C); 5125 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 5126 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 5127 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 5128 } 5129 5130 /* On 11A, We should delay and wait RF/BBP to be stable 5131 * and the appropriate time should be 1000 micro seconds 5132 * 2005/06/05 - On 11G, we also need this delay time. 5133 * Otherwise it's difficult to pass the WHQL. 5134 */ 5135 usleep_range(1000, 1500); 5136 } 5137 } 5138 EXPORT_SYMBOL_GPL(rt2800_vco_calibration); 5139 5140 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, 5141 struct rt2x00lib_conf *libconf) 5142 { 5143 u32 reg; 5144 5145 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 5146 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 5147 libconf->conf->short_frame_max_tx_count); 5148 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 5149 libconf->conf->long_frame_max_tx_count); 5150 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5151 } 5152 5153 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, 5154 struct rt2x00lib_conf *libconf) 5155 { 5156 enum dev_state state = 5157 (libconf->conf->flags & IEEE80211_CONF_PS) ? 5158 STATE_SLEEP : STATE_AWAKE; 5159 u32 reg; 5160 5161 if (state == STATE_SLEEP) { 5162 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); 5163 5164 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5165 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); 5166 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 5167 libconf->conf->listen_interval - 1); 5168 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); 5169 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5170 5171 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5172 } else { 5173 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5174 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 5175 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 5176 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); 5177 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5178 5179 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5180 } 5181 } 5182 5183 void rt2800_config(struct rt2x00_dev *rt2x00dev, 5184 struct rt2x00lib_conf *libconf, 5185 const unsigned int flags) 5186 { 5187 /* Always recalculate LNA gain before changing configuration */ 5188 rt2800_config_lna_gain(rt2x00dev, libconf); 5189 5190 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { 5191 rt2800_config_channel(rt2x00dev, libconf->conf, 5192 &libconf->rf, &libconf->channel); 5193 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5194 libconf->conf->power_level); 5195 } 5196 if (flags & IEEE80211_CONF_CHANGE_POWER) 5197 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5198 libconf->conf->power_level); 5199 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 5200 rt2800_config_retry_limit(rt2x00dev, libconf); 5201 if (flags & IEEE80211_CONF_CHANGE_PS) 5202 rt2800_config_ps(rt2x00dev, libconf); 5203 } 5204 EXPORT_SYMBOL_GPL(rt2800_config); 5205 5206 /* 5207 * Link tuning 5208 */ 5209 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5210 { 5211 u32 reg; 5212 5213 /* 5214 * Update FCS error count from register. 5215 */ 5216 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 5217 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); 5218 } 5219 EXPORT_SYMBOL_GPL(rt2800_link_stats); 5220 5221 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 5222 { 5223 u8 vgc; 5224 5225 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 5226 if (rt2x00_rt(rt2x00dev, RT3070) || 5227 rt2x00_rt(rt2x00dev, RT3071) || 5228 rt2x00_rt(rt2x00dev, RT3090) || 5229 rt2x00_rt(rt2x00dev, RT3290) || 5230 rt2x00_rt(rt2x00dev, RT3390) || 5231 rt2x00_rt(rt2x00dev, RT3572) || 5232 rt2x00_rt(rt2x00dev, RT3593) || 5233 rt2x00_rt(rt2x00dev, RT5390) || 5234 rt2x00_rt(rt2x00dev, RT5392) || 5235 rt2x00_rt(rt2x00dev, RT5592) || 5236 rt2x00_rt(rt2x00dev, RT6352)) 5237 vgc = 0x1c + (2 * rt2x00dev->lna_gain); 5238 else 5239 vgc = 0x2e + rt2x00dev->lna_gain; 5240 } else { /* 5GHZ band */ 5241 if (rt2x00_rt(rt2x00dev, RT3593)) 5242 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3; 5243 else if (rt2x00_rt(rt2x00dev, RT5592)) 5244 vgc = 0x24 + (2 * rt2x00dev->lna_gain); 5245 else { 5246 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 5247 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3; 5248 else 5249 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3; 5250 } 5251 } 5252 5253 return vgc; 5254 } 5255 5256 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, 5257 struct link_qual *qual, u8 vgc_level) 5258 { 5259 if (qual->vgc_level != vgc_level) { 5260 if (rt2x00_rt(rt2x00dev, RT3572) || 5261 rt2x00_rt(rt2x00dev, RT3593)) { 5262 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, 5263 vgc_level); 5264 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5265 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a); 5266 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level); 5267 } else { 5268 rt2800_bbp_write(rt2x00dev, 66, vgc_level); 5269 } 5270 5271 qual->vgc_level = vgc_level; 5272 qual->vgc_level_reg = vgc_level; 5273 } 5274 } 5275 5276 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5277 { 5278 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); 5279 } 5280 EXPORT_SYMBOL_GPL(rt2800_reset_tuner); 5281 5282 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 5283 const u32 count) 5284 { 5285 u8 vgc; 5286 5287 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) 5288 return; 5289 5290 /* When RSSI is better than a certain threshold, increase VGC 5291 * with a chip specific value in order to improve the balance 5292 * between sensibility and noise isolation. 5293 */ 5294 5295 vgc = rt2800_get_default_vgc(rt2x00dev); 5296 5297 switch (rt2x00dev->chip.rt) { 5298 case RT3572: 5299 case RT3593: 5300 if (qual->rssi > -65) { 5301 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) 5302 vgc += 0x20; 5303 else 5304 vgc += 0x10; 5305 } 5306 break; 5307 5308 case RT5592: 5309 if (qual->rssi > -65) 5310 vgc += 0x20; 5311 break; 5312 5313 default: 5314 if (qual->rssi > -80) 5315 vgc += 0x10; 5316 break; 5317 } 5318 5319 rt2800_set_vgc(rt2x00dev, qual, vgc); 5320 } 5321 EXPORT_SYMBOL_GPL(rt2800_link_tuner); 5322 5323 /* 5324 * Initialization functions. 5325 */ 5326 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 5327 { 5328 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5329 u32 reg; 5330 u16 eeprom; 5331 unsigned int i; 5332 int ret; 5333 5334 rt2800_disable_wpdma(rt2x00dev); 5335 5336 ret = rt2800_drv_init_registers(rt2x00dev); 5337 if (ret) 5338 return ret; 5339 5340 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); 5341 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 5342 5343 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 5344 5345 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 5346 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); 5347 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); 5348 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); 5349 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); 5350 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 5351 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 5352 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 5353 5354 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); 5355 5356 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 5357 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); 5358 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 5359 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 5360 5361 if (rt2x00_rt(rt2x00dev, RT3290)) { 5362 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 5363 if (rt2x00_get_field32(reg, WLAN_EN) == 1) { 5364 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); 5365 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 5366 } 5367 5368 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 5369 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { 5370 rt2x00_set_field32(®, LDO0_EN, 1); 5371 rt2x00_set_field32(®, LDO_BGSEL, 3); 5372 rt2800_register_write(rt2x00dev, CMB_CTRL, reg); 5373 } 5374 5375 reg = rt2800_register_read(rt2x00dev, OSC_CTRL); 5376 rt2x00_set_field32(®, OSC_ROSC_EN, 1); 5377 rt2x00_set_field32(®, OSC_CAL_REQ, 1); 5378 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); 5379 rt2800_register_write(rt2x00dev, OSC_CTRL, reg); 5380 5381 reg = rt2800_register_read(rt2x00dev, COEX_CFG0); 5382 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); 5383 rt2800_register_write(rt2x00dev, COEX_CFG0, reg); 5384 5385 reg = rt2800_register_read(rt2x00dev, COEX_CFG2); 5386 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); 5387 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); 5388 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); 5389 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); 5390 rt2800_register_write(rt2x00dev, COEX_CFG2, reg); 5391 5392 reg = rt2800_register_read(rt2x00dev, PLL_CTRL); 5393 rt2x00_set_field32(®, PLL_CONTROL, 1); 5394 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); 5395 } 5396 5397 if (rt2x00_rt(rt2x00dev, RT3071) || 5398 rt2x00_rt(rt2x00dev, RT3090) || 5399 rt2x00_rt(rt2x00dev, RT3290) || 5400 rt2x00_rt(rt2x00dev, RT3390)) { 5401 5402 if (rt2x00_rt(rt2x00dev, RT3290)) 5403 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5404 0x00000404); 5405 else 5406 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5407 0x00000400); 5408 5409 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5410 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 5411 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 5412 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 5413 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5414 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 5415 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5416 0x0000002c); 5417 else 5418 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5419 0x0000000f); 5420 } else { 5421 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5422 } 5423 } else if (rt2x00_rt(rt2x00dev, RT3070)) { 5424 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5425 5426 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 5427 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5428 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); 5429 } else { 5430 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5431 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5432 } 5433 } else if (rt2800_is_305x_soc(rt2x00dev)) { 5434 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5435 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5436 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); 5437 } else if (rt2x00_rt(rt2x00dev, RT3352)) { 5438 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5439 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5440 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5441 } else if (rt2x00_rt(rt2x00dev, RT3572)) { 5442 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5443 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5444 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 5445 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5446 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5447 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) { 5448 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5449 if (rt2x00_get_field16(eeprom, 5450 EEPROM_NIC_CONF1_DAC_TEST)) 5451 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5452 0x0000001f); 5453 else 5454 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5455 0x0000000f); 5456 } else { 5457 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5458 0x00000000); 5459 } 5460 } else if (rt2x00_rt(rt2x00dev, RT5390) || 5461 rt2x00_rt(rt2x00dev, RT5392) || 5462 rt2x00_rt(rt2x00dev, RT6352)) { 5463 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5464 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5465 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5466 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5467 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5468 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5469 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5470 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 5471 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5472 } else if (rt2x00_rt(rt2x00dev, RT6352)) { 5473 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401); 5474 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000); 5475 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5476 rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002); 5477 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F); 5478 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x06060606); 5479 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0); 5480 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0); 5481 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C); 5482 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C); 5483 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 5484 0x3630363A); 5485 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT, 5486 0x3630363A); 5487 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 5488 rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); 5489 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 5490 } else { 5491 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 5492 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5493 } 5494 5495 reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG); 5496 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); 5497 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); 5498 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); 5499 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); 5500 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); 5501 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); 5502 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); 5503 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); 5504 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); 5505 5506 reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG); 5507 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 5508 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); 5509 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 5510 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 5511 5512 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 5513 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 5514 if (rt2x00_is_usb(rt2x00dev)) { 5515 drv_data->max_psdu = 3; 5516 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || 5517 rt2x00_rt(rt2x00dev, RT2883) || 5518 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) { 5519 drv_data->max_psdu = 2; 5520 } else { 5521 drv_data->max_psdu = 1; 5522 } 5523 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu); 5524 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); 5525 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); 5526 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 5527 5528 reg = rt2800_register_read(rt2x00dev, LED_CFG); 5529 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); 5530 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); 5531 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); 5532 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); 5533 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); 5534 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); 5535 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); 5536 rt2800_register_write(rt2x00dev, LED_CFG, reg); 5537 5538 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 5539 5540 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 5541 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); 5542 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); 5543 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); 5544 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); 5545 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); 5546 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); 5547 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5548 5549 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 5550 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); 5551 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); 5552 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); 5553 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); 5554 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); 5555 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 5556 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 5557 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 5558 5559 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 5560 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); 5561 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); 5562 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); 5563 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 5564 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5565 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5566 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5567 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5568 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5569 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); 5570 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 5571 5572 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 5573 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); 5574 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); 5575 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); 5576 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 5577 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5578 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5579 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5580 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5581 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5582 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); 5583 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 5584 5585 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 5586 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 5587 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); 5588 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); 5589 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5590 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5591 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5592 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5593 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5594 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5595 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); 5596 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 5597 5598 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 5599 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 5600 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); 5601 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); 5602 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5603 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5604 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5605 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 5606 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5607 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 5608 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); 5609 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 5610 5611 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 5612 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 5613 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); 5614 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); 5615 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5616 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5617 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5618 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5619 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5620 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5621 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); 5622 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 5623 5624 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 5625 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 5626 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); 5627 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); 5628 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5629 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5630 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5631 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 5632 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5633 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 5634 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); 5635 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 5636 5637 if (rt2x00_is_usb(rt2x00dev)) { 5638 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); 5639 5640 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 5641 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 5642 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 5643 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 5644 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 5645 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); 5646 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); 5647 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); 5648 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); 5649 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); 5650 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 5651 } 5652 5653 /* 5654 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 5655 * although it is reserved. 5656 */ 5657 reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG); 5658 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); 5659 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); 5660 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); 5661 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); 5662 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); 5663 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); 5664 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); 5665 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); 5666 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); 5667 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); 5668 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); 5669 5670 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; 5671 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); 5672 5673 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 5674 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); 5675 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, 5676 IEEE80211_MAX_RTS_THRESHOLD); 5677 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1); 5678 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 5679 5680 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 5681 5682 /* 5683 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS 5684 * time should be set to 16. However, the original Ralink driver uses 5685 * 16 for both and indeed using a value of 10 for CCK SIFS results in 5686 * connection problems with 11g + CTS protection. Hence, use the same 5687 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. 5688 */ 5689 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 5690 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); 5691 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); 5692 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); 5693 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); 5694 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); 5695 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 5696 5697 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 5698 5699 /* 5700 * ASIC will keep garbage value after boot, clear encryption keys. 5701 */ 5702 for (i = 0; i < 4; i++) 5703 rt2800_register_write(rt2x00dev, 5704 SHARED_KEY_MODE_ENTRY(i), 0); 5705 5706 for (i = 0; i < 256; i++) { 5707 rt2800_config_wcid(rt2x00dev, NULL, i); 5708 rt2800_delete_wcid_attr(rt2x00dev, i); 5709 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 5710 } 5711 5712 /* 5713 * Clear all beacons 5714 */ 5715 for (i = 0; i < 8; i++) 5716 rt2800_clear_beacon_register(rt2x00dev, i); 5717 5718 if (rt2x00_is_usb(rt2x00dev)) { 5719 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 5720 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); 5721 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 5722 } else if (rt2x00_is_pcie(rt2x00dev)) { 5723 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 5724 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); 5725 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 5726 } 5727 5728 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0); 5729 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); 5730 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); 5731 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); 5732 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); 5733 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); 5734 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); 5735 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); 5736 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); 5737 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); 5738 5739 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1); 5740 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); 5741 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); 5742 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); 5743 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); 5744 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); 5745 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); 5746 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); 5747 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); 5748 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); 5749 5750 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0); 5751 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); 5752 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); 5753 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); 5754 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); 5755 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); 5756 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); 5757 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); 5758 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); 5759 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); 5760 5761 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1); 5762 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); 5763 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); 5764 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); 5765 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); 5766 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); 5767 5768 /* 5769 * Do not force the BA window size, we use the TXWI to set it 5770 */ 5771 reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE); 5772 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); 5773 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); 5774 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); 5775 5776 /* 5777 * We must clear the error counters. 5778 * These registers are cleared on read, 5779 * so we may pass a useless variable to store the value. 5780 */ 5781 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 5782 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1); 5783 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2); 5784 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0); 5785 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1); 5786 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2); 5787 5788 /* 5789 * Setup leadtime for pre tbtt interrupt to 6ms 5790 */ 5791 reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG); 5792 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); 5793 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); 5794 5795 /* 5796 * Set up channel statistics timer 5797 */ 5798 reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG); 5799 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); 5800 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); 5801 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); 5802 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); 5803 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); 5804 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); 5805 5806 return 0; 5807 } 5808 5809 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) 5810 { 5811 unsigned int i; 5812 u32 reg; 5813 5814 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 5815 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 5816 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) 5817 return 0; 5818 5819 udelay(REGISTER_BUSY_DELAY); 5820 } 5821 5822 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n"); 5823 return -EACCES; 5824 } 5825 5826 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 5827 { 5828 unsigned int i; 5829 u8 value; 5830 5831 /* 5832 * BBP was enabled after firmware was loaded, 5833 * but we need to reactivate it now. 5834 */ 5835 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 5836 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 5837 msleep(1); 5838 5839 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 5840 value = rt2800_bbp_read(rt2x00dev, 0); 5841 if ((value != 0xff) && (value != 0x00)) 5842 return 0; 5843 udelay(REGISTER_BUSY_DELAY); 5844 } 5845 5846 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 5847 return -EACCES; 5848 } 5849 5850 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev) 5851 { 5852 u8 value; 5853 5854 value = rt2800_bbp_read(rt2x00dev, 4); 5855 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); 5856 rt2800_bbp_write(rt2x00dev, 4, value); 5857 } 5858 5859 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev) 5860 { 5861 rt2800_bbp_write(rt2x00dev, 142, 1); 5862 rt2800_bbp_write(rt2x00dev, 143, 57); 5863 } 5864 5865 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev) 5866 { 5867 static const u8 glrt_table[] = { 5868 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */ 5869 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */ 5870 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */ 5871 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */ 5872 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */ 5873 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */ 5874 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */ 5875 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */ 5876 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */ 5877 }; 5878 int i; 5879 5880 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) { 5881 rt2800_bbp_write(rt2x00dev, 195, 128 + i); 5882 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]); 5883 } 5884 }; 5885 5886 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev) 5887 { 5888 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 5889 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5890 rt2800_bbp_write(rt2x00dev, 68, 0x0B); 5891 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5892 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5893 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5894 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5895 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5896 rt2800_bbp_write(rt2x00dev, 83, 0x6A); 5897 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5898 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5899 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5900 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5901 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5902 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5903 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5904 } 5905 5906 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev) 5907 { 5908 u16 eeprom; 5909 u8 value; 5910 5911 value = rt2800_bbp_read(rt2x00dev, 138); 5912 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 5913 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 5914 value |= 0x20; 5915 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 5916 value &= ~0x02; 5917 rt2800_bbp_write(rt2x00dev, 138, value); 5918 } 5919 5920 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev) 5921 { 5922 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5923 5924 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5925 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5926 5927 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5928 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5929 5930 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5931 5932 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 5933 rt2800_bbp_write(rt2x00dev, 80, 0x08); 5934 5935 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5936 5937 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5938 5939 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5940 5941 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5942 5943 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5944 5945 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5946 5947 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5948 5949 rt2800_bbp_write(rt2x00dev, 105, 0x01); 5950 5951 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5952 } 5953 5954 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev) 5955 { 5956 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5957 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5958 5959 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 5960 rt2800_bbp_write(rt2x00dev, 69, 0x16); 5961 rt2800_bbp_write(rt2x00dev, 73, 0x12); 5962 } else { 5963 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5964 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5965 } 5966 5967 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5968 5969 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5970 5971 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5972 5973 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5974 5975 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 5976 rt2800_bbp_write(rt2x00dev, 84, 0x19); 5977 else 5978 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5979 5980 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5981 5982 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5983 5984 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5985 5986 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5987 5988 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5989 5990 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5991 } 5992 5993 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev) 5994 { 5995 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5996 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5997 5998 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5999 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6000 6001 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6002 6003 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6004 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6005 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6006 6007 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6008 6009 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6010 6011 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6012 6013 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6014 6015 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6016 6017 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6018 6019 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 6020 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 6021 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E)) 6022 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6023 else 6024 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6025 6026 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6027 6028 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6029 6030 if (rt2x00_rt(rt2x00dev, RT3071) || 6031 rt2x00_rt(rt2x00dev, RT3090)) 6032 rt2800_disable_unused_dac_adc(rt2x00dev); 6033 } 6034 6035 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev) 6036 { 6037 u8 value; 6038 6039 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6040 6041 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6042 6043 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6044 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6045 6046 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6047 6048 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6049 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6050 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6051 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6052 6053 rt2800_bbp_write(rt2x00dev, 77, 0x58); 6054 6055 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6056 6057 rt2800_bbp_write(rt2x00dev, 74, 0x0b); 6058 rt2800_bbp_write(rt2x00dev, 79, 0x18); 6059 rt2800_bbp_write(rt2x00dev, 80, 0x09); 6060 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6061 6062 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6063 6064 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6065 6066 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6067 6068 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6069 6070 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6071 6072 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6073 6074 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6075 6076 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6077 6078 rt2800_bbp_write(rt2x00dev, 105, 0x1c); 6079 6080 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6081 6082 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6083 6084 rt2800_bbp_write(rt2x00dev, 67, 0x24); 6085 rt2800_bbp_write(rt2x00dev, 143, 0x04); 6086 rt2800_bbp_write(rt2x00dev, 142, 0x99); 6087 rt2800_bbp_write(rt2x00dev, 150, 0x30); 6088 rt2800_bbp_write(rt2x00dev, 151, 0x2e); 6089 rt2800_bbp_write(rt2x00dev, 152, 0x20); 6090 rt2800_bbp_write(rt2x00dev, 153, 0x34); 6091 rt2800_bbp_write(rt2x00dev, 154, 0x40); 6092 rt2800_bbp_write(rt2x00dev, 155, 0x3b); 6093 rt2800_bbp_write(rt2x00dev, 253, 0x04); 6094 6095 value = rt2800_bbp_read(rt2x00dev, 47); 6096 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1); 6097 rt2800_bbp_write(rt2x00dev, 47, value); 6098 6099 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */ 6100 value = rt2800_bbp_read(rt2x00dev, 3); 6101 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1); 6102 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1); 6103 rt2800_bbp_write(rt2x00dev, 3, value); 6104 } 6105 6106 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) 6107 { 6108 rt2800_bbp_write(rt2x00dev, 3, 0x00); 6109 rt2800_bbp_write(rt2x00dev, 4, 0x50); 6110 6111 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6112 6113 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6114 6115 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6116 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6117 6118 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6119 6120 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6121 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6122 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6123 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6124 6125 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6126 6127 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6128 6129 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 6130 rt2800_bbp_write(rt2x00dev, 80, 0x08); 6131 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6132 6133 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6134 6135 if (rt2x00_rt(rt2x00dev, RT5350)) { 6136 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6137 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6138 } else { 6139 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6140 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6141 } 6142 6143 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6144 6145 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6146 6147 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6148 6149 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6150 6151 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6152 6153 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6154 6155 if (rt2x00_rt(rt2x00dev, RT5350)) { 6156 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6157 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6158 } else { 6159 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6160 rt2800_bbp_write(rt2x00dev, 106, 0x05); 6161 } 6162 6163 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6164 6165 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6166 6167 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 6168 /* Set ITxBF timeout to 0x9c40=1000msec */ 6169 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6170 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6171 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6172 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6173 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6174 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6175 /* Reprogram the inband interface to put right values in RXWI */ 6176 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6177 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6178 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6179 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6180 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6181 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6182 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6183 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6184 6185 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6186 6187 if (rt2x00_rt(rt2x00dev, RT5350)) { 6188 /* Antenna Software OFDM */ 6189 rt2800_bbp_write(rt2x00dev, 150, 0x40); 6190 /* Antenna Software CCK */ 6191 rt2800_bbp_write(rt2x00dev, 151, 0x30); 6192 rt2800_bbp_write(rt2x00dev, 152, 0xa3); 6193 /* Clear previously selected antenna */ 6194 rt2800_bbp_write(rt2x00dev, 154, 0); 6195 } 6196 } 6197 6198 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev) 6199 { 6200 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6201 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6202 6203 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6204 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6205 6206 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6207 6208 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6209 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6210 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6211 6212 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6213 6214 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6215 6216 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6217 6218 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6219 6220 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6221 6222 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6223 6224 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E)) 6225 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6226 else 6227 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6228 6229 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6230 6231 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6232 6233 rt2800_disable_unused_dac_adc(rt2x00dev); 6234 } 6235 6236 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev) 6237 { 6238 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6239 6240 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6241 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6242 6243 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6244 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6245 6246 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6247 6248 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6249 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6250 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6251 6252 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6253 6254 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6255 6256 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6257 6258 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6259 6260 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6261 6262 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6263 6264 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6265 6266 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6267 6268 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6269 6270 rt2800_disable_unused_dac_adc(rt2x00dev); 6271 } 6272 6273 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev) 6274 { 6275 rt2800_init_bbp_early(rt2x00dev); 6276 6277 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6278 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6279 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6280 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6281 6282 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6283 6284 /* Enable DC filter */ 6285 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E)) 6286 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6287 } 6288 6289 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) 6290 { 6291 int ant, div_mode; 6292 u16 eeprom; 6293 u8 value; 6294 6295 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6296 6297 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6298 6299 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6300 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6301 6302 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6303 6304 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6305 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6306 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6307 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6308 6309 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6310 6311 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6312 6313 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6314 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6315 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6316 6317 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6318 6319 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6320 6321 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6322 6323 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6324 6325 if (rt2x00_rt(rt2x00dev, RT5392)) 6326 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6327 6328 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6329 6330 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6331 6332 if (rt2x00_rt(rt2x00dev, RT5392)) { 6333 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6334 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6335 } 6336 6337 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6338 6339 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6340 6341 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6342 6343 if (rt2x00_rt(rt2x00dev, RT5390)) 6344 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6345 else if (rt2x00_rt(rt2x00dev, RT5392)) 6346 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6347 else 6348 WARN_ON(1); 6349 6350 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6351 6352 if (rt2x00_rt(rt2x00dev, RT5392)) { 6353 rt2800_bbp_write(rt2x00dev, 134, 0xd0); 6354 rt2800_bbp_write(rt2x00dev, 135, 0xf6); 6355 } 6356 6357 rt2800_disable_unused_dac_adc(rt2x00dev); 6358 6359 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6360 div_mode = rt2x00_get_field16(eeprom, 6361 EEPROM_NIC_CONF1_ANT_DIVERSITY); 6362 ant = (div_mode == 3) ? 1 : 0; 6363 6364 /* check if this is a Bluetooth combo card */ 6365 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 6366 u32 reg; 6367 6368 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 6369 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 6370 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); 6371 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); 6372 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); 6373 if (ant == 0) 6374 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); 6375 else if (ant == 1) 6376 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); 6377 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 6378 } 6379 6380 /* These chips have hardware RX antenna diversity */ 6381 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 6382 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 6383 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */ 6384 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */ 6385 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */ 6386 } 6387 6388 value = rt2800_bbp_read(rt2x00dev, 152); 6389 if (ant == 0) 6390 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6391 else 6392 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6393 rt2800_bbp_write(rt2x00dev, 152, value); 6394 6395 rt2800_init_freq_calibration(rt2x00dev); 6396 } 6397 6398 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) 6399 { 6400 int ant, div_mode; 6401 u16 eeprom; 6402 u8 value; 6403 6404 rt2800_init_bbp_early(rt2x00dev); 6405 6406 value = rt2800_bbp_read(rt2x00dev, 105); 6407 rt2x00_set_field8(&value, BBP105_MLD, 6408 rt2x00dev->default_ant.rx_chain_num == 2); 6409 rt2800_bbp_write(rt2x00dev, 105, value); 6410 6411 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6412 6413 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6414 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6415 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6416 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6417 rt2800_bbp_write(rt2x00dev, 69, 0x1A); 6418 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6419 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6420 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6421 rt2800_bbp_write(rt2x00dev, 75, 0x4F); 6422 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6423 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6424 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 6425 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6426 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6427 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6428 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6429 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6430 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6431 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 6432 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6433 /* FIXME BBP105 owerwrite */ 6434 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 6435 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6436 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6437 rt2800_bbp_write(rt2x00dev, 134, 0xD0); 6438 rt2800_bbp_write(rt2x00dev, 135, 0xF6); 6439 rt2800_bbp_write(rt2x00dev, 137, 0x0F); 6440 6441 /* Initialize GLRT (Generalized Likehood Radio Test) */ 6442 rt2800_init_bbp_5592_glrt(rt2x00dev); 6443 6444 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6445 6446 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6447 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); 6448 ant = (div_mode == 3) ? 1 : 0; 6449 value = rt2800_bbp_read(rt2x00dev, 152); 6450 if (ant == 0) { 6451 /* Main antenna */ 6452 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6453 } else { 6454 /* Auxiliary antenna */ 6455 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6456 } 6457 rt2800_bbp_write(rt2x00dev, 152, value); 6458 6459 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) { 6460 value = rt2800_bbp_read(rt2x00dev, 254); 6461 rt2x00_set_field8(&value, BBP254_BIT7, 1); 6462 rt2800_bbp_write(rt2x00dev, 254, value); 6463 } 6464 6465 rt2800_init_freq_calibration(rt2x00dev); 6466 6467 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6468 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 6469 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6470 } 6471 6472 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev, 6473 const u8 reg, const u8 value) 6474 { 6475 rt2800_bbp_write(rt2x00dev, 195, reg); 6476 rt2800_bbp_write(rt2x00dev, 196, value); 6477 } 6478 6479 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev, 6480 const u8 reg, const u8 value) 6481 { 6482 rt2800_bbp_write(rt2x00dev, 158, reg); 6483 rt2800_bbp_write(rt2x00dev, 159, value); 6484 } 6485 6486 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg) 6487 { 6488 rt2800_bbp_write(rt2x00dev, 158, reg); 6489 return rt2800_bbp_read(rt2x00dev, 159); 6490 } 6491 6492 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev) 6493 { 6494 u8 bbp; 6495 6496 /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */ 6497 bbp = rt2800_bbp_read(rt2x00dev, 105); 6498 rt2x00_set_field8(&bbp, BBP105_MLD, 6499 rt2x00dev->default_ant.rx_chain_num == 2); 6500 rt2800_bbp_write(rt2x00dev, 105, bbp); 6501 6502 /* Avoid data loss and CRC errors */ 6503 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6504 6505 /* Fix I/Q swap issue */ 6506 bbp = rt2800_bbp_read(rt2x00dev, 1); 6507 bbp |= 0x04; 6508 rt2800_bbp_write(rt2x00dev, 1, bbp); 6509 6510 /* BBP for G band */ 6511 rt2800_bbp_write(rt2x00dev, 3, 0x08); 6512 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */ 6513 rt2800_bbp_write(rt2x00dev, 6, 0x08); 6514 rt2800_bbp_write(rt2x00dev, 14, 0x09); 6515 rt2800_bbp_write(rt2x00dev, 15, 0xFF); 6516 rt2800_bbp_write(rt2x00dev, 16, 0x01); 6517 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6518 rt2800_bbp_write(rt2x00dev, 21, 0x00); 6519 rt2800_bbp_write(rt2x00dev, 22, 0x00); 6520 rt2800_bbp_write(rt2x00dev, 27, 0x00); 6521 rt2800_bbp_write(rt2x00dev, 28, 0x00); 6522 rt2800_bbp_write(rt2x00dev, 30, 0x00); 6523 rt2800_bbp_write(rt2x00dev, 31, 0x48); 6524 rt2800_bbp_write(rt2x00dev, 47, 0x40); 6525 rt2800_bbp_write(rt2x00dev, 62, 0x00); 6526 rt2800_bbp_write(rt2x00dev, 63, 0x00); 6527 rt2800_bbp_write(rt2x00dev, 64, 0x00); 6528 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6529 rt2800_bbp_write(rt2x00dev, 66, 0x1C); 6530 rt2800_bbp_write(rt2x00dev, 67, 0x20); 6531 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6532 rt2800_bbp_write(rt2x00dev, 69, 0x10); 6533 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6534 rt2800_bbp_write(rt2x00dev, 73, 0x18); 6535 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6536 rt2800_bbp_write(rt2x00dev, 75, 0x60); 6537 rt2800_bbp_write(rt2x00dev, 76, 0x44); 6538 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6539 rt2800_bbp_write(rt2x00dev, 78, 0x1E); 6540 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 6541 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 6542 rt2800_bbp_write(rt2x00dev, 81, 0x3A); 6543 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 6544 rt2800_bbp_write(rt2x00dev, 83, 0x9A); 6545 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 6546 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6547 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6548 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6549 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6550 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 6551 rt2800_bbp_write(rt2x00dev, 96, 0x00); 6552 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 6553 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6554 /* FIXME BBP105 owerwrite */ 6555 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 6556 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6557 rt2800_bbp_write(rt2x00dev, 109, 0x00); 6558 rt2800_bbp_write(rt2x00dev, 134, 0x10); 6559 rt2800_bbp_write(rt2x00dev, 135, 0xA6); 6560 rt2800_bbp_write(rt2x00dev, 137, 0x04); 6561 rt2800_bbp_write(rt2x00dev, 142, 0x30); 6562 rt2800_bbp_write(rt2x00dev, 143, 0xF7); 6563 rt2800_bbp_write(rt2x00dev, 160, 0xEC); 6564 rt2800_bbp_write(rt2x00dev, 161, 0xC4); 6565 rt2800_bbp_write(rt2x00dev, 162, 0x77); 6566 rt2800_bbp_write(rt2x00dev, 163, 0xF9); 6567 rt2800_bbp_write(rt2x00dev, 164, 0x00); 6568 rt2800_bbp_write(rt2x00dev, 165, 0x00); 6569 rt2800_bbp_write(rt2x00dev, 186, 0x00); 6570 rt2800_bbp_write(rt2x00dev, 187, 0x00); 6571 rt2800_bbp_write(rt2x00dev, 188, 0x00); 6572 rt2800_bbp_write(rt2x00dev, 186, 0x00); 6573 rt2800_bbp_write(rt2x00dev, 187, 0x01); 6574 rt2800_bbp_write(rt2x00dev, 188, 0x00); 6575 rt2800_bbp_write(rt2x00dev, 189, 0x00); 6576 6577 rt2800_bbp_write(rt2x00dev, 91, 0x06); 6578 rt2800_bbp_write(rt2x00dev, 92, 0x04); 6579 rt2800_bbp_write(rt2x00dev, 93, 0x54); 6580 rt2800_bbp_write(rt2x00dev, 99, 0x50); 6581 rt2800_bbp_write(rt2x00dev, 148, 0x84); 6582 rt2800_bbp_write(rt2x00dev, 167, 0x80); 6583 rt2800_bbp_write(rt2x00dev, 178, 0xFF); 6584 rt2800_bbp_write(rt2x00dev, 106, 0x13); 6585 6586 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */ 6587 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00); 6588 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14); 6589 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20); 6590 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A); 6591 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16); 6592 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06); 6593 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02); 6594 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07); 6595 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05); 6596 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09); 6597 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20); 6598 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08); 6599 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A); 6600 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00); 6601 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00); 6602 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0); 6603 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F); 6604 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F); 6605 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32); 6606 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08); 6607 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28); 6608 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19); 6609 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A); 6610 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16); 6611 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10); 6612 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10); 6613 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A); 6614 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36); 6615 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C); 6616 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26); 6617 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24); 6618 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42); 6619 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40); 6620 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30); 6621 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29); 6622 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C); 6623 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46); 6624 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D); 6625 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40); 6626 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E); 6627 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38); 6628 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D); 6629 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F); 6630 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C); 6631 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34); 6632 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C); 6633 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F); 6634 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C); 6635 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35); 6636 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E); 6637 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F); 6638 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49); 6639 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41); 6640 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36); 6641 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39); 6642 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30); 6643 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30); 6644 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E); 6645 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D); 6646 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28); 6647 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21); 6648 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C); 6649 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16); 6650 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50); 6651 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A); 6652 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43); 6653 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50); 6654 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10); 6655 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10); 6656 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10); 6657 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10); 6658 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D); 6659 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14); 6660 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32); 6661 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C); 6662 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36); 6663 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C); 6664 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43); 6665 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C); 6666 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E); 6667 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36); 6668 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30); 6669 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E); 6670 6671 /* BBP for G band DCOC function */ 6672 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C); 6673 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00); 6674 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10); 6675 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10); 6676 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10); 6677 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10); 6678 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08); 6679 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40); 6680 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04); 6681 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04); 6682 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08); 6683 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08); 6684 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03); 6685 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03); 6686 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03); 6687 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02); 6688 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40); 6689 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40); 6690 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64); 6691 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64); 6692 6693 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6694 } 6695 6696 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) 6697 { 6698 unsigned int i; 6699 u16 eeprom; 6700 u8 reg_id; 6701 u8 value; 6702 6703 if (rt2800_is_305x_soc(rt2x00dev)) 6704 rt2800_init_bbp_305x_soc(rt2x00dev); 6705 6706 switch (rt2x00dev->chip.rt) { 6707 case RT2860: 6708 case RT2872: 6709 case RT2883: 6710 rt2800_init_bbp_28xx(rt2x00dev); 6711 break; 6712 case RT3070: 6713 case RT3071: 6714 case RT3090: 6715 rt2800_init_bbp_30xx(rt2x00dev); 6716 break; 6717 case RT3290: 6718 rt2800_init_bbp_3290(rt2x00dev); 6719 break; 6720 case RT3352: 6721 case RT5350: 6722 rt2800_init_bbp_3352(rt2x00dev); 6723 break; 6724 case RT3390: 6725 rt2800_init_bbp_3390(rt2x00dev); 6726 break; 6727 case RT3572: 6728 rt2800_init_bbp_3572(rt2x00dev); 6729 break; 6730 case RT3593: 6731 rt2800_init_bbp_3593(rt2x00dev); 6732 return; 6733 case RT5390: 6734 case RT5392: 6735 rt2800_init_bbp_53xx(rt2x00dev); 6736 break; 6737 case RT5592: 6738 rt2800_init_bbp_5592(rt2x00dev); 6739 return; 6740 case RT6352: 6741 rt2800_init_bbp_6352(rt2x00dev); 6742 break; 6743 } 6744 6745 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 6746 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 6747 EEPROM_BBP_START, i); 6748 6749 if (eeprom != 0xffff && eeprom != 0x0000) { 6750 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 6751 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 6752 rt2800_bbp_write(rt2x00dev, reg_id, value); 6753 } 6754 } 6755 } 6756 6757 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev) 6758 { 6759 u32 reg; 6760 6761 reg = rt2800_register_read(rt2x00dev, OPT_14_CSR); 6762 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); 6763 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 6764 } 6765 6766 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, 6767 u8 filter_target) 6768 { 6769 unsigned int i; 6770 u8 bbp; 6771 u8 rfcsr; 6772 u8 passband; 6773 u8 stopband; 6774 u8 overtuned = 0; 6775 u8 rfcsr24 = (bw40) ? 0x27 : 0x07; 6776 6777 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 6778 6779 bbp = rt2800_bbp_read(rt2x00dev, 4); 6780 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); 6781 rt2800_bbp_write(rt2x00dev, 4, bbp); 6782 6783 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 6784 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); 6785 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 6786 6787 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 6788 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); 6789 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 6790 6791 /* 6792 * Set power & frequency of passband test tone 6793 */ 6794 rt2800_bbp_write(rt2x00dev, 24, 0); 6795 6796 for (i = 0; i < 100; i++) { 6797 rt2800_bbp_write(rt2x00dev, 25, 0x90); 6798 msleep(1); 6799 6800 passband = rt2800_bbp_read(rt2x00dev, 55); 6801 if (passband) 6802 break; 6803 } 6804 6805 /* 6806 * Set power & frequency of stopband test tone 6807 */ 6808 rt2800_bbp_write(rt2x00dev, 24, 0x06); 6809 6810 for (i = 0; i < 100; i++) { 6811 rt2800_bbp_write(rt2x00dev, 25, 0x90); 6812 msleep(1); 6813 6814 stopband = rt2800_bbp_read(rt2x00dev, 55); 6815 6816 if ((passband - stopband) <= filter_target) { 6817 rfcsr24++; 6818 overtuned += ((passband - stopband) == filter_target); 6819 } else 6820 break; 6821 6822 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 6823 } 6824 6825 rfcsr24 -= !!overtuned; 6826 6827 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 6828 return rfcsr24; 6829 } 6830 6831 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev, 6832 const unsigned int rf_reg) 6833 { 6834 u8 rfcsr; 6835 6836 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg); 6837 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1); 6838 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 6839 msleep(1); 6840 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0); 6841 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 6842 } 6843 6844 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev) 6845 { 6846 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 6847 u8 filter_tgt_bw20; 6848 u8 filter_tgt_bw40; 6849 u8 rfcsr, bbp; 6850 6851 /* 6852 * TODO: sync filter_tgt values with vendor driver 6853 */ 6854 if (rt2x00_rt(rt2x00dev, RT3070)) { 6855 filter_tgt_bw20 = 0x16; 6856 filter_tgt_bw40 = 0x19; 6857 } else { 6858 filter_tgt_bw20 = 0x13; 6859 filter_tgt_bw40 = 0x15; 6860 } 6861 6862 drv_data->calibration_bw20 = 6863 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20); 6864 drv_data->calibration_bw40 = 6865 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40); 6866 6867 /* 6868 * Save BBP 25 & 26 values for later use in channel switching (for 3052) 6869 */ 6870 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 6871 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 6872 6873 /* 6874 * Set back to initial state 6875 */ 6876 rt2800_bbp_write(rt2x00dev, 24, 0); 6877 6878 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 6879 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 6880 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 6881 6882 /* 6883 * Set BBP back to BW20 6884 */ 6885 bbp = rt2800_bbp_read(rt2x00dev, 4); 6886 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 6887 rt2800_bbp_write(rt2x00dev, 4, bbp); 6888 } 6889 6890 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) 6891 { 6892 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 6893 u8 min_gain, rfcsr, bbp; 6894 u16 eeprom; 6895 6896 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 6897 6898 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 6899 if (rt2x00_rt(rt2x00dev, RT3070) || 6900 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 6901 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 6902 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 6903 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev)) 6904 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 6905 } 6906 6907 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2; 6908 if (drv_data->txmixer_gain_24g >= min_gain) { 6909 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 6910 drv_data->txmixer_gain_24g); 6911 } 6912 6913 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 6914 6915 if (rt2x00_rt(rt2x00dev, RT3090)) { 6916 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 6917 bbp = rt2800_bbp_read(rt2x00dev, 138); 6918 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 6919 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 6920 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); 6921 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 6922 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); 6923 rt2800_bbp_write(rt2x00dev, 138, bbp); 6924 } 6925 6926 if (rt2x00_rt(rt2x00dev, RT3070)) { 6927 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27); 6928 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) 6929 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); 6930 else 6931 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); 6932 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); 6933 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); 6934 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); 6935 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 6936 } else if (rt2x00_rt(rt2x00dev, RT3071) || 6937 rt2x00_rt(rt2x00dev, RT3090) || 6938 rt2x00_rt(rt2x00dev, RT3390)) { 6939 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 6940 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 6941 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 6942 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 6943 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 6944 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 6945 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 6946 6947 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15); 6948 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); 6949 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); 6950 6951 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 6952 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); 6953 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 6954 6955 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 6956 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); 6957 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 6958 } 6959 } 6960 6961 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev) 6962 { 6963 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 6964 u8 rfcsr; 6965 u8 tx_gain; 6966 6967 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 6968 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0); 6969 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 6970 6971 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 6972 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g, 6973 RFCSR17_TXMIXER_GAIN); 6974 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain); 6975 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 6976 6977 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38); 6978 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); 6979 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); 6980 6981 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39); 6982 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); 6983 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 6984 6985 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 6986 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 6987 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 6988 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 6989 6990 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 6991 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 6992 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 6993 6994 /* TODO: enable stream mode */ 6995 } 6996 6997 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev) 6998 { 6999 u8 reg; 7000 u16 eeprom; 7001 7002 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 7003 reg = rt2800_bbp_read(rt2x00dev, 138); 7004 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 7005 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 7006 rt2x00_set_field8(®, BBP138_RX_ADC1, 0); 7007 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 7008 rt2x00_set_field8(®, BBP138_TX_DAC1, 1); 7009 rt2800_bbp_write(rt2x00dev, 138, reg); 7010 7011 reg = rt2800_rfcsr_read(rt2x00dev, 38); 7012 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); 7013 rt2800_rfcsr_write(rt2x00dev, 38, reg); 7014 7015 reg = rt2800_rfcsr_read(rt2x00dev, 39); 7016 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); 7017 rt2800_rfcsr_write(rt2x00dev, 39, reg); 7018 7019 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7020 7021 reg = rt2800_rfcsr_read(rt2x00dev, 30); 7022 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); 7023 rt2800_rfcsr_write(rt2x00dev, 30, reg); 7024 } 7025 7026 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev) 7027 { 7028 rt2800_rf_init_calibration(rt2x00dev, 30); 7029 7030 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 7031 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 7032 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 7033 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 7034 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7035 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7036 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7037 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 7038 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 7039 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7040 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 7041 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7042 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 7043 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 7044 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7045 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7046 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7047 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7048 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7049 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7050 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7051 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7052 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7053 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 7054 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7055 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 7056 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 7057 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 7058 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 7059 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 7060 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 7061 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 7062 } 7063 7064 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) 7065 { 7066 u8 rfcsr; 7067 u16 eeprom; 7068 u32 reg; 7069 7070 /* XXX vendor driver do this only for 3070 */ 7071 rt2800_rf_init_calibration(rt2x00dev, 30); 7072 7073 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7074 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7075 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7076 rt2800_rfcsr_write(rt2x00dev, 7, 0x60); 7077 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7078 rt2800_rfcsr_write(rt2x00dev, 10, 0x41); 7079 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7080 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 7081 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7082 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7083 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7084 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7085 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7086 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7087 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7088 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7089 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7090 rt2800_rfcsr_write(rt2x00dev, 25, 0x03); 7091 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 7092 7093 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 7094 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7095 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7096 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7097 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7098 } else if (rt2x00_rt(rt2x00dev, RT3071) || 7099 rt2x00_rt(rt2x00dev, RT3090)) { 7100 rt2800_rfcsr_write(rt2x00dev, 31, 0x14); 7101 7102 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7103 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7104 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7105 7106 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7107 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7108 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7109 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { 7110 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 7111 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 7112 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7113 else 7114 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7115 } 7116 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7117 7118 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7119 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7120 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7121 } 7122 7123 rt2800_rx_filter_calibration(rt2x00dev); 7124 7125 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 7126 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7127 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) 7128 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7129 7130 rt2800_led_open_drain_enable(rt2x00dev); 7131 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7132 } 7133 7134 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) 7135 { 7136 u8 rfcsr; 7137 7138 rt2800_rf_init_calibration(rt2x00dev, 2); 7139 7140 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 7141 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7142 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7143 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7144 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 7145 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3); 7146 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7147 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7148 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7149 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7150 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7151 rt2800_rfcsr_write(rt2x00dev, 18, 0x02); 7152 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7153 rt2800_rfcsr_write(rt2x00dev, 25, 0x83); 7154 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7155 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7156 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7157 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7158 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7159 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7160 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7161 rt2800_rfcsr_write(rt2x00dev, 34, 0x05); 7162 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7163 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7164 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7165 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7166 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7167 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7168 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7169 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b); 7170 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7171 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7172 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7173 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7174 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7175 rt2800_rfcsr_write(rt2x00dev, 49, 0x98); 7176 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7177 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7178 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 7179 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7180 rt2800_rfcsr_write(rt2x00dev, 56, 0x02); 7181 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 7182 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 7183 rt2800_rfcsr_write(rt2x00dev, 59, 0x09); 7184 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7185 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); 7186 7187 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29); 7188 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3); 7189 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr); 7190 7191 rt2800_led_open_drain_enable(rt2x00dev); 7192 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7193 } 7194 7195 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) 7196 { 7197 int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0, 7198 &rt2x00dev->cap_flags); 7199 int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1, 7200 &rt2x00dev->cap_flags); 7201 u8 rfcsr; 7202 7203 rt2800_rf_init_calibration(rt2x00dev, 30); 7204 7205 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7206 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7207 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7208 rt2800_rfcsr_write(rt2x00dev, 3, 0x18); 7209 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7210 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7211 rt2800_rfcsr_write(rt2x00dev, 6, 0x33); 7212 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7213 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7214 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7215 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2); 7216 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 7217 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 7218 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 7219 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a); 7220 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7221 rt2800_rfcsr_write(rt2x00dev, 16, 0x01); 7222 rt2800_rfcsr_write(rt2x00dev, 18, 0x45); 7223 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7224 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7225 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7226 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7227 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7228 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7229 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7230 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7231 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7232 rt2800_rfcsr_write(rt2x00dev, 28, 0x03); 7233 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 7234 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7235 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7236 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7237 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7238 rfcsr = 0x01; 7239 if (tx0_ext_pa) 7240 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1); 7241 if (tx1_ext_pa) 7242 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1); 7243 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 7244 rt2800_rfcsr_write(rt2x00dev, 35, 0x03); 7245 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); 7246 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); 7247 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); 7248 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); 7249 rt2800_rfcsr_write(rt2x00dev, 40, 0x33); 7250 rfcsr = 0x52; 7251 if (!tx0_ext_pa) { 7252 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1); 7253 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1); 7254 } 7255 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr); 7256 rfcsr = 0x52; 7257 if (!tx1_ext_pa) { 7258 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1); 7259 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1); 7260 } 7261 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 7262 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); 7263 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); 7264 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); 7265 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd); 7266 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); 7267 rt2800_rfcsr_write(rt2x00dev, 48, 0x14); 7268 rt2800_rfcsr_write(rt2x00dev, 49, 0x00); 7269 rfcsr = 0x2d; 7270 if (tx0_ext_pa) 7271 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1); 7272 if (tx1_ext_pa) 7273 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1); 7274 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7275 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f)); 7276 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00)); 7277 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52)); 7278 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b)); 7279 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f)); 7280 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00)); 7281 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52)); 7282 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b)); 7283 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 7284 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 7285 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 7286 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7287 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7288 7289 rt2800_rx_filter_calibration(rt2x00dev); 7290 rt2800_led_open_drain_enable(rt2x00dev); 7291 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7292 } 7293 7294 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) 7295 { 7296 u32 reg; 7297 7298 rt2800_rf_init_calibration(rt2x00dev, 30); 7299 7300 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 7301 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 7302 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7303 rt2800_rfcsr_write(rt2x00dev, 3, 0x62); 7304 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7305 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); 7306 rt2800_rfcsr_write(rt2x00dev, 6, 0x42); 7307 rt2800_rfcsr_write(rt2x00dev, 7, 0x34); 7308 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 7309 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 7310 rt2800_rfcsr_write(rt2x00dev, 10, 0x61); 7311 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7312 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); 7313 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); 7314 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7315 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7316 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); 7317 rt2800_rfcsr_write(rt2x00dev, 17, 0x94); 7318 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); 7319 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); 7320 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); 7321 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); 7322 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7323 rt2800_rfcsr_write(rt2x00dev, 23, 0x14); 7324 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7325 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 7326 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7327 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7328 rt2800_rfcsr_write(rt2x00dev, 28, 0x41); 7329 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); 7330 rt2800_rfcsr_write(rt2x00dev, 30, 0x20); 7331 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); 7332 7333 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7334 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7335 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7336 7337 rt2800_rx_filter_calibration(rt2x00dev); 7338 7339 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) 7340 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7341 7342 rt2800_led_open_drain_enable(rt2x00dev); 7343 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7344 } 7345 7346 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) 7347 { 7348 u8 rfcsr; 7349 u32 reg; 7350 7351 rt2800_rf_init_calibration(rt2x00dev, 30); 7352 7353 rt2800_rfcsr_write(rt2x00dev, 0, 0x70); 7354 rt2800_rfcsr_write(rt2x00dev, 1, 0x81); 7355 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7356 rt2800_rfcsr_write(rt2x00dev, 3, 0x02); 7357 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); 7358 rt2800_rfcsr_write(rt2x00dev, 5, 0x05); 7359 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); 7360 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 7361 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 7362 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 7363 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 7364 rt2800_rfcsr_write(rt2x00dev, 12, 0x70); 7365 rt2800_rfcsr_write(rt2x00dev, 13, 0x65); 7366 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); 7367 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7368 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); 7369 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 7370 rt2800_rfcsr_write(rt2x00dev, 18, 0xac); 7371 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 7372 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 7373 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); 7374 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7375 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); 7376 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7377 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 7378 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7379 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7380 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7381 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 7382 rt2800_rfcsr_write(rt2x00dev, 30, 0x09); 7383 rt2800_rfcsr_write(rt2x00dev, 31, 0x10); 7384 7385 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7386 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7387 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7388 7389 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7390 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7391 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7392 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7393 msleep(1); 7394 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7395 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7396 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7397 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7398 7399 rt2800_rx_filter_calibration(rt2x00dev); 7400 rt2800_led_open_drain_enable(rt2x00dev); 7401 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7402 } 7403 7404 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev) 7405 { 7406 u8 bbp; 7407 bool txbf_enabled = false; /* FIXME */ 7408 7409 bbp = rt2800_bbp_read(rt2x00dev, 105); 7410 if (rt2x00dev->default_ant.rx_chain_num == 1) 7411 rt2x00_set_field8(&bbp, BBP105_MLD, 0); 7412 else 7413 rt2x00_set_field8(&bbp, BBP105_MLD, 1); 7414 rt2800_bbp_write(rt2x00dev, 105, bbp); 7415 7416 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7417 7418 rt2800_bbp_write(rt2x00dev, 92, 0x02); 7419 rt2800_bbp_write(rt2x00dev, 82, 0x82); 7420 rt2800_bbp_write(rt2x00dev, 106, 0x05); 7421 rt2800_bbp_write(rt2x00dev, 104, 0x92); 7422 rt2800_bbp_write(rt2x00dev, 88, 0x90); 7423 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 7424 rt2800_bbp_write(rt2x00dev, 47, 0x48); 7425 rt2800_bbp_write(rt2x00dev, 120, 0x50); 7426 7427 if (txbf_enabled) 7428 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 7429 else 7430 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 7431 7432 /* SNR mapping */ 7433 rt2800_bbp_write(rt2x00dev, 142, 6); 7434 rt2800_bbp_write(rt2x00dev, 143, 160); 7435 rt2800_bbp_write(rt2x00dev, 142, 7); 7436 rt2800_bbp_write(rt2x00dev, 143, 161); 7437 rt2800_bbp_write(rt2x00dev, 142, 8); 7438 rt2800_bbp_write(rt2x00dev, 143, 162); 7439 7440 /* ADC/DAC control */ 7441 rt2800_bbp_write(rt2x00dev, 31, 0x08); 7442 7443 /* RX AGC energy lower bound in log2 */ 7444 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 7445 7446 /* FIXME: BBP 105 owerwrite? */ 7447 rt2800_bbp_write(rt2x00dev, 105, 0x04); 7448 7449 } 7450 7451 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) 7452 { 7453 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7454 u32 reg; 7455 u8 rfcsr; 7456 7457 /* Disable GPIO #4 and #7 function for LAN PE control */ 7458 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7459 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); 7460 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); 7461 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7462 7463 /* Initialize default register values */ 7464 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 7465 rt2800_rfcsr_write(rt2x00dev, 3, 0x80); 7466 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7467 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 7468 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7469 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7470 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 7471 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 7472 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e); 7473 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 7474 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 7475 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7476 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7477 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7478 rt2800_rfcsr_write(rt2x00dev, 32, 0x78); 7479 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b); 7480 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 7481 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0); 7482 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 7483 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 7484 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3); 7485 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 7486 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 7487 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 7488 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 7489 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 7490 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 7491 rt2800_rfcsr_write(rt2x00dev, 53, 0x18); 7492 rt2800_rfcsr_write(rt2x00dev, 54, 0x18); 7493 rt2800_rfcsr_write(rt2x00dev, 55, 0x18); 7494 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 7495 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 7496 7497 /* Initiate calibration */ 7498 /* TODO: use rt2800_rf_init_calibration ? */ 7499 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 7500 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 7501 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 7502 7503 rt2800_freq_cal_mode1(rt2x00dev); 7504 7505 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 7506 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1); 7507 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 7508 7509 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7510 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7511 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7512 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7513 usleep_range(1000, 1500); 7514 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7515 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7516 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7517 7518 /* Set initial values for RX filter calibration */ 7519 drv_data->calibration_bw20 = 0x1f; 7520 drv_data->calibration_bw40 = 0x2f; 7521 7522 /* Save BBP 25 & 26 values for later use in channel switching */ 7523 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 7524 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 7525 7526 rt2800_led_open_drain_enable(rt2x00dev); 7527 rt2800_normal_mode_setup_3593(rt2x00dev); 7528 7529 rt3593_post_bbp_init(rt2x00dev); 7530 7531 /* TODO: enable stream mode support */ 7532 } 7533 7534 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev) 7535 { 7536 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7537 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7538 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7539 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7540 rt2800_rfcsr_write(rt2x00dev, 4, 0x49); 7541 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7542 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 7543 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7544 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7545 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7546 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7547 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7548 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7549 if (rt2800_clk_is_20mhz(rt2x00dev)) 7550 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f); 7551 else 7552 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7553 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7554 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7555 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0); 7556 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7557 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 7558 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7559 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7560 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7561 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7562 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7563 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7564 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7565 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7566 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7567 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0); 7568 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7569 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7570 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7571 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7572 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 7573 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7574 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7575 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 7576 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7577 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7578 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7579 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7580 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7581 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 7582 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c); 7583 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6); 7584 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7585 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7586 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7587 rt2800_rfcsr_write(rt2x00dev, 49, 0x80); 7588 rt2800_rfcsr_write(rt2x00dev, 50, 0x00); 7589 rt2800_rfcsr_write(rt2x00dev, 51, 0x00); 7590 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7591 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7592 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 7593 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7594 rt2800_rfcsr_write(rt2x00dev, 56, 0x82); 7595 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 7596 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 7597 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b); 7598 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7599 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 7600 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7601 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7602 } 7603 7604 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) 7605 { 7606 rt2800_rf_init_calibration(rt2x00dev, 2); 7607 7608 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 7609 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7610 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 7611 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7612 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7613 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 7614 else 7615 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 7616 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7617 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7618 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7619 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7620 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7621 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7622 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7623 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 7624 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7625 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 7626 7627 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7628 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7629 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7630 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7631 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7632 if (rt2x00_is_usb(rt2x00dev) && 7633 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7634 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7635 else 7636 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); 7637 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7638 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7639 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7640 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7641 7642 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7643 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7644 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7645 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7646 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 7647 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7648 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7649 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 7650 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7651 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7652 7653 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7654 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7655 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); 7656 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); 7657 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7658 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7659 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7660 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7661 else 7662 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); 7663 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7664 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7665 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 7666 7667 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7668 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7669 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7670 else 7671 rt2800_rfcsr_write(rt2x00dev, 53, 0x84); 7672 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 7673 rt2800_rfcsr_write(rt2x00dev, 55, 0x44); 7674 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7675 rt2800_rfcsr_write(rt2x00dev, 56, 0x42); 7676 else 7677 rt2800_rfcsr_write(rt2x00dev, 56, 0x22); 7678 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 7679 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 7680 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f); 7681 7682 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7683 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 7684 if (rt2x00_is_usb(rt2x00dev)) 7685 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 7686 else 7687 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5); 7688 } else { 7689 if (rt2x00_is_usb(rt2x00dev)) 7690 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); 7691 else 7692 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5); 7693 } 7694 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7695 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7696 7697 rt2800_normal_mode_setup_5xxx(rt2x00dev); 7698 7699 rt2800_led_open_drain_enable(rt2x00dev); 7700 } 7701 7702 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) 7703 { 7704 rt2800_rf_init_calibration(rt2x00dev, 2); 7705 7706 rt2800_rfcsr_write(rt2x00dev, 1, 0x17); 7707 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 7708 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7709 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 7710 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7711 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7712 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7713 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7714 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7715 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7716 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7717 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 7718 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7719 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d); 7720 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7721 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d); 7722 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7723 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b); 7724 rt2800_rfcsr_write(rt2x00dev, 24, 0x44); 7725 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7726 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7727 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7728 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7729 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7730 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7731 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7732 rt2800_rfcsr_write(rt2x00dev, 32, 0x20); 7733 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 7734 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 7735 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7736 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7737 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 7738 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 7739 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7740 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f); 7741 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7742 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7743 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 7744 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7745 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7746 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7747 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c); 7748 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7749 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 7750 rt2800_rfcsr_write(rt2x00dev, 50, 0x94); 7751 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a); 7752 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 7753 rt2800_rfcsr_write(rt2x00dev, 53, 0x44); 7754 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 7755 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7756 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1); 7757 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 7758 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 7759 rt2800_rfcsr_write(rt2x00dev, 59, 0x07); 7760 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7761 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 7762 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 7763 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 7764 7765 rt2800_normal_mode_setup_5xxx(rt2x00dev); 7766 7767 rt2800_led_open_drain_enable(rt2x00dev); 7768 } 7769 7770 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev) 7771 { 7772 rt2800_rf_init_calibration(rt2x00dev, 30); 7773 7774 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F); 7775 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7776 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7777 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4); 7778 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7779 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7780 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7781 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 7782 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7783 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D); 7784 rt2800_rfcsr_write(rt2x00dev, 20, 0x10); 7785 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D); 7786 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7787 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7788 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7789 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 7790 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 7791 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7792 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C); 7793 rt2800_rfcsr_write(rt2x00dev, 53, 0x22); 7794 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 7795 7796 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7797 msleep(1); 7798 7799 rt2800_freq_cal_mode1(rt2x00dev); 7800 7801 /* Enable DC filter */ 7802 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 7803 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 7804 7805 rt2800_normal_mode_setup_5xxx(rt2x00dev); 7806 7807 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C)) 7808 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7809 7810 rt2800_led_open_drain_enable(rt2x00dev); 7811 } 7812 7813 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev, 7814 bool set_bw, bool is_ht40) 7815 { 7816 u8 bbp_val; 7817 7818 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 7819 bbp_val |= 0x1; 7820 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 7821 usleep_range(100, 200); 7822 7823 if (set_bw) { 7824 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 7825 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40); 7826 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 7827 usleep_range(100, 200); 7828 } 7829 7830 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 7831 bbp_val &= (~0x1); 7832 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 7833 usleep_range(100, 200); 7834 } 7835 7836 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal) 7837 { 7838 u8 rf_val; 7839 7840 if (btxcal) 7841 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 7842 else 7843 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02); 7844 7845 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06); 7846 7847 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 7848 rf_val |= 0x80; 7849 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val); 7850 7851 if (btxcal) { 7852 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1); 7853 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20); 7854 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 7855 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 7856 rf_val &= (~0x3F); 7857 rf_val |= 0x3F; 7858 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 7859 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 7860 rf_val &= (~0x3F); 7861 rf_val |= 0x3F; 7862 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 7863 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31); 7864 } else { 7865 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1); 7866 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18); 7867 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 7868 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 7869 rf_val &= (~0x3F); 7870 rf_val |= 0x34; 7871 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 7872 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 7873 rf_val &= (~0x3F); 7874 rf_val |= 0x34; 7875 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 7876 } 7877 7878 return 0; 7879 } 7880 7881 static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev) 7882 { 7883 unsigned int cnt; 7884 u8 bbp_val; 7885 char cal_val; 7886 7887 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82); 7888 7889 cnt = 0; 7890 do { 7891 usleep_range(500, 2000); 7892 bbp_val = rt2800_bbp_read(rt2x00dev, 159); 7893 if (bbp_val == 0x02 || cnt == 20) 7894 break; 7895 7896 cnt++; 7897 } while (cnt < 20); 7898 7899 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39); 7900 cal_val = bbp_val & 0x7F; 7901 if (cal_val >= 0x40) 7902 cal_val -= 128; 7903 7904 return cal_val; 7905 } 7906 7907 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev, 7908 bool btxcal) 7909 { 7910 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7911 u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc; 7912 u8 filter_target; 7913 u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02; 7914 u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31; 7915 int loop = 0, is_ht40, cnt; 7916 u8 bbp_val, rf_val; 7917 char cal_r32_init, cal_r32_val, cal_diff; 7918 u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05; 7919 u8 saverfb5r06, saverfb5r07; 7920 u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20; 7921 u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41; 7922 u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46; 7923 u8 saverfb5r58, saverfb5r59; 7924 u8 savebbp159r0, savebbp159r2, savebbpr23; 7925 u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0; 7926 7927 /* Save MAC registers */ 7928 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 7929 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 7930 7931 /* save BBP registers */ 7932 savebbpr23 = rt2800_bbp_read(rt2x00dev, 23); 7933 7934 savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0); 7935 savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2); 7936 7937 /* Save RF registers */ 7938 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 7939 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 7940 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 7941 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 7942 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5); 7943 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 7944 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 7945 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 7946 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 7947 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 7948 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 7949 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 7950 7951 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37); 7952 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38); 7953 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39); 7954 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40); 7955 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41); 7956 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42); 7957 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43); 7958 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44); 7959 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45); 7960 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46); 7961 7962 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 7963 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 7964 7965 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 7966 rf_val |= 0x3; 7967 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 7968 7969 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 7970 rf_val |= 0x1; 7971 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val); 7972 7973 cnt = 0; 7974 do { 7975 usleep_range(500, 2000); 7976 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 7977 if (((rf_val & 0x1) == 0x00) || (cnt == 40)) 7978 break; 7979 cnt++; 7980 } while (cnt < 40); 7981 7982 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 7983 rf_val &= (~0x3); 7984 rf_val |= 0x1; 7985 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 7986 7987 /* I-3 */ 7988 bbp_val = rt2800_bbp_read(rt2x00dev, 23); 7989 bbp_val &= (~0x1F); 7990 bbp_val |= 0x10; 7991 rt2800_bbp_write(rt2x00dev, 23, bbp_val); 7992 7993 do { 7994 /* I-4,5,6,7,8,9 */ 7995 if (loop == 0) { 7996 is_ht40 = false; 7997 7998 if (btxcal) 7999 filter_target = tx_filter_target_20m; 8000 else 8001 filter_target = rx_filter_target_20m; 8002 } else { 8003 is_ht40 = true; 8004 8005 if (btxcal) 8006 filter_target = tx_filter_target_40m; 8007 else 8008 filter_target = rx_filter_target_40m; 8009 } 8010 8011 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 8012 rf_val &= (~0x04); 8013 if (loop == 1) 8014 rf_val |= 0x4; 8015 8016 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val); 8017 8018 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40); 8019 8020 rt2800_rf_lp_config(rt2x00dev, btxcal); 8021 if (btxcal) { 8022 tx_agc_fc = 0; 8023 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 8024 rf_val &= (~0x7F); 8025 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 8026 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 8027 rf_val &= (~0x7F); 8028 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 8029 } else { 8030 rx_agc_fc = 0; 8031 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 8032 rf_val &= (~0x7F); 8033 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 8034 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 8035 rf_val &= (~0x7F); 8036 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 8037 } 8038 8039 usleep_range(1000, 2000); 8040 8041 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 8042 bbp_val &= (~0x6); 8043 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 8044 8045 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 8046 8047 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 8048 8049 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 8050 bbp_val |= 0x6; 8051 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 8052 do_cal: 8053 if (btxcal) { 8054 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 8055 rf_val &= (~0x7F); 8056 rf_val |= tx_agc_fc; 8057 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 8058 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 8059 rf_val &= (~0x7F); 8060 rf_val |= tx_agc_fc; 8061 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 8062 } else { 8063 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 8064 rf_val &= (~0x7F); 8065 rf_val |= rx_agc_fc; 8066 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 8067 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 8068 rf_val &= (~0x7F); 8069 rf_val |= rx_agc_fc; 8070 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 8071 } 8072 8073 usleep_range(500, 1000); 8074 8075 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 8076 8077 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 8078 8079 cal_diff = cal_r32_init - cal_r32_val; 8080 8081 if (btxcal) 8082 cmm_agc_fc = tx_agc_fc; 8083 else 8084 cmm_agc_fc = rx_agc_fc; 8085 8086 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) || 8087 ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) { 8088 if (btxcal) 8089 tx_agc_fc = 0; 8090 else 8091 rx_agc_fc = 0; 8092 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) { 8093 if (btxcal) 8094 tx_agc_fc++; 8095 else 8096 rx_agc_fc++; 8097 goto do_cal; 8098 } 8099 8100 if (btxcal) { 8101 if (loop == 0) 8102 drv_data->tx_calibration_bw20 = tx_agc_fc; 8103 else 8104 drv_data->tx_calibration_bw40 = tx_agc_fc; 8105 } else { 8106 if (loop == 0) 8107 drv_data->rx_calibration_bw20 = rx_agc_fc; 8108 else 8109 drv_data->rx_calibration_bw40 = rx_agc_fc; 8110 } 8111 8112 loop++; 8113 } while (loop <= 1); 8114 8115 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00); 8116 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01); 8117 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03); 8118 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04); 8119 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05); 8120 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06); 8121 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07); 8122 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08); 8123 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); 8124 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); 8125 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); 8126 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); 8127 8128 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37); 8129 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38); 8130 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39); 8131 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40); 8132 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41); 8133 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42); 8134 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43); 8135 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44); 8136 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45); 8137 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46); 8138 8139 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58); 8140 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59); 8141 8142 rt2800_bbp_write(rt2x00dev, 23, savebbpr23); 8143 8144 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0); 8145 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2); 8146 8147 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 8148 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 8149 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)); 8150 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 8151 8152 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); 8153 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); 8154 } 8155 8156 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev) 8157 { 8158 /* Initialize RF central register to default value */ 8159 rt2800_rfcsr_write(rt2x00dev, 0, 0x02); 8160 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 8161 rt2800_rfcsr_write(rt2x00dev, 2, 0x33); 8162 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF); 8163 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 8164 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 8165 rt2800_rfcsr_write(rt2x00dev, 6, 0x00); 8166 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8167 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 8168 rt2800_rfcsr_write(rt2x00dev, 9, 0x00); 8169 rt2800_rfcsr_write(rt2x00dev, 10, 0x00); 8170 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 8171 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset); 8172 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 8173 rt2800_rfcsr_write(rt2x00dev, 14, 0x40); 8174 rt2800_rfcsr_write(rt2x00dev, 15, 0x22); 8175 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C); 8176 rt2800_rfcsr_write(rt2x00dev, 17, 0x00); 8177 rt2800_rfcsr_write(rt2x00dev, 18, 0x00); 8178 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8179 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0); 8180 rt2800_rfcsr_write(rt2x00dev, 21, 0x12); 8181 rt2800_rfcsr_write(rt2x00dev, 22, 0x07); 8182 rt2800_rfcsr_write(rt2x00dev, 23, 0x13); 8183 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE); 8184 rt2800_rfcsr_write(rt2x00dev, 25, 0x24); 8185 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A); 8186 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8187 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8188 rt2800_rfcsr_write(rt2x00dev, 29, 0x05); 8189 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 8190 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 8191 rt2800_rfcsr_write(rt2x00dev, 32, 0x00); 8192 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8193 rt2800_rfcsr_write(rt2x00dev, 34, 0x00); 8194 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 8195 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8196 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 8197 rt2800_rfcsr_write(rt2x00dev, 38, 0x00); 8198 rt2800_rfcsr_write(rt2x00dev, 39, 0x00); 8199 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 8200 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0); 8201 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B); 8202 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 8203 8204 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 8205 if (rt2800_clk_is_20mhz(rt2x00dev)) 8206 rt2800_rfcsr_write(rt2x00dev, 13, 0x03); 8207 else 8208 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 8209 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C); 8210 rt2800_rfcsr_write(rt2x00dev, 16, 0x80); 8211 rt2800_rfcsr_write(rt2x00dev, 17, 0x99); 8212 rt2800_rfcsr_write(rt2x00dev, 18, 0x99); 8213 rt2800_rfcsr_write(rt2x00dev, 19, 0x09); 8214 rt2800_rfcsr_write(rt2x00dev, 20, 0x50); 8215 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0); 8216 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 8217 rt2800_rfcsr_write(rt2x00dev, 23, 0x06); 8218 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8219 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 8220 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D); 8221 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8222 rt2800_rfcsr_write(rt2x00dev, 28, 0x61); 8223 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5); 8224 rt2800_rfcsr_write(rt2x00dev, 43, 0x02); 8225 8226 rt2800_rfcsr_write(rt2x00dev, 28, 0x62); 8227 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD); 8228 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 8229 8230 /* Initialize RF channel register to default value */ 8231 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03); 8232 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00); 8233 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00); 8234 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00); 8235 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00); 8236 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08); 8237 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00); 8238 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51); 8239 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53); 8240 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16); 8241 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61); 8242 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 8243 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22); 8244 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D); 8245 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 8246 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13); 8247 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22); 8248 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27); 8249 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02); 8250 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 8251 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01); 8252 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52); 8253 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80); 8254 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3); 8255 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00); 8256 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00); 8257 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00); 8258 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00); 8259 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C); 8260 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B); 8261 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B); 8262 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31); 8263 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D); 8264 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00); 8265 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6); 8266 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55); 8267 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00); 8268 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB); 8269 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3); 8270 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3); 8271 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03); 8272 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00); 8273 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00); 8274 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3); 8275 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3); 8276 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 8277 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07); 8278 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68); 8279 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF); 8280 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C); 8281 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07); 8282 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8); 8283 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85); 8284 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10); 8285 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07); 8286 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A); 8287 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85); 8288 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10); 8289 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C); 8290 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00); 8291 8292 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5); 8293 8294 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47); 8295 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71); 8296 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33); 8297 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E); 8298 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23); 8299 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4); 8300 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02); 8301 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12); 8302 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C); 8303 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB); 8304 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D); 8305 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6); 8306 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08); 8307 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4); 8308 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 8309 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3); 8310 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 8311 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); 8312 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67); 8313 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69); 8314 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF); 8315 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27); 8316 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20); 8317 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 8318 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF); 8319 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C); 8320 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20); 8321 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 8322 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7); 8323 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09); 8324 8325 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51); 8326 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 8327 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 8328 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C); 8329 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64); 8330 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51); 8331 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36); 8332 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 8333 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16); 8334 8335 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C); 8336 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC); 8337 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F); 8338 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); 8339 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 8340 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 8341 8342 /* Initialize RF channel register for DRQFN */ 8343 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 8344 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3); 8345 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5); 8346 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28); 8347 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68); 8348 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7); 8349 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02); 8350 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7); 8351 8352 /* Initialize RF DC calibration register to default value */ 8353 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47); 8354 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00); 8355 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00); 8356 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00); 8357 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00); 8358 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 8359 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 8360 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 8361 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 8362 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00); 8363 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07); 8364 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01); 8365 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07); 8366 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07); 8367 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07); 8368 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20); 8369 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22); 8370 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00); 8371 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00); 8372 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00); 8373 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00); 8374 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1); 8375 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11); 8376 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02); 8377 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41); 8378 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20); 8379 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00); 8380 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7); 8381 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2); 8382 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20); 8383 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49); 8384 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20); 8385 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04); 8386 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1); 8387 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1); 8388 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01); 8389 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00); 8390 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00); 8391 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00); 8392 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00); 8393 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00); 8394 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00); 8395 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E); 8396 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D); 8397 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E); 8398 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D); 8399 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E); 8400 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D); 8401 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00); 8402 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00); 8403 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00); 8404 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00); 8405 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00); 8406 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 8407 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 8408 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A); 8409 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00); 8410 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00); 8411 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00); 8412 8413 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08); 8414 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04); 8415 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20); 8416 8417 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 8418 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C); 8419 8420 rt2800_bw_filter_calibration(rt2x00dev, true); 8421 rt2800_bw_filter_calibration(rt2x00dev, false); 8422 } 8423 8424 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) 8425 { 8426 if (rt2800_is_305x_soc(rt2x00dev)) { 8427 rt2800_init_rfcsr_305x_soc(rt2x00dev); 8428 return; 8429 } 8430 8431 switch (rt2x00dev->chip.rt) { 8432 case RT3070: 8433 case RT3071: 8434 case RT3090: 8435 rt2800_init_rfcsr_30xx(rt2x00dev); 8436 break; 8437 case RT3290: 8438 rt2800_init_rfcsr_3290(rt2x00dev); 8439 break; 8440 case RT3352: 8441 rt2800_init_rfcsr_3352(rt2x00dev); 8442 break; 8443 case RT3390: 8444 rt2800_init_rfcsr_3390(rt2x00dev); 8445 break; 8446 case RT3572: 8447 rt2800_init_rfcsr_3572(rt2x00dev); 8448 break; 8449 case RT3593: 8450 rt2800_init_rfcsr_3593(rt2x00dev); 8451 break; 8452 case RT5350: 8453 rt2800_init_rfcsr_5350(rt2x00dev); 8454 break; 8455 case RT5390: 8456 rt2800_init_rfcsr_5390(rt2x00dev); 8457 break; 8458 case RT5392: 8459 rt2800_init_rfcsr_5392(rt2x00dev); 8460 break; 8461 case RT5592: 8462 rt2800_init_rfcsr_5592(rt2x00dev); 8463 break; 8464 case RT6352: 8465 rt2800_init_rfcsr_6352(rt2x00dev); 8466 break; 8467 } 8468 } 8469 8470 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) 8471 { 8472 u32 reg; 8473 u16 word; 8474 8475 /* 8476 * Initialize MAC registers. 8477 */ 8478 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || 8479 rt2800_init_registers(rt2x00dev))) 8480 return -EIO; 8481 8482 /* 8483 * Wait BBP/RF to wake up. 8484 */ 8485 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev))) 8486 return -EIO; 8487 8488 /* 8489 * Send signal during boot time to initialize firmware. 8490 */ 8491 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 8492 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 8493 if (rt2x00_is_usb(rt2x00dev)) 8494 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 8495 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 8496 msleep(1); 8497 8498 /* 8499 * Make sure BBP is up and running. 8500 */ 8501 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev))) 8502 return -EIO; 8503 8504 /* 8505 * Initialize BBP/RF registers. 8506 */ 8507 rt2800_init_bbp(rt2x00dev); 8508 rt2800_init_rfcsr(rt2x00dev); 8509 8510 if (rt2x00_is_usb(rt2x00dev) && 8511 (rt2x00_rt(rt2x00dev, RT3070) || 8512 rt2x00_rt(rt2x00dev, RT3071) || 8513 rt2x00_rt(rt2x00dev, RT3572))) { 8514 udelay(200); 8515 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); 8516 udelay(10); 8517 } 8518 8519 /* 8520 * Enable RX. 8521 */ 8522 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8523 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 8524 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 8525 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 8526 8527 udelay(50); 8528 8529 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 8530 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 8531 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 8532 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 8533 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 8534 8535 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8536 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 8537 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); 8538 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 8539 8540 /* 8541 * Initialize LED control 8542 */ 8543 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF); 8544 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, 8545 word & 0xff, (word >> 8) & 0xff); 8546 8547 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF); 8548 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, 8549 word & 0xff, (word >> 8) & 0xff); 8550 8551 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY); 8552 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, 8553 word & 0xff, (word >> 8) & 0xff); 8554 8555 return 0; 8556 } 8557 EXPORT_SYMBOL_GPL(rt2800_enable_radio); 8558 8559 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) 8560 { 8561 u32 reg; 8562 8563 rt2800_disable_wpdma(rt2x00dev); 8564 8565 /* Wait for DMA, ignore error */ 8566 rt2800_wait_wpdma_ready(rt2x00dev); 8567 8568 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8569 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); 8570 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 8571 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 8572 } 8573 EXPORT_SYMBOL_GPL(rt2800_disable_radio); 8574 8575 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 8576 { 8577 u32 reg; 8578 u16 efuse_ctrl_reg; 8579 8580 if (rt2x00_rt(rt2x00dev, RT3290)) 8581 efuse_ctrl_reg = EFUSE_CTRL_3290; 8582 else 8583 efuse_ctrl_reg = EFUSE_CTRL; 8584 8585 reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg); 8586 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); 8587 } 8588 EXPORT_SYMBOL_GPL(rt2800_efuse_detect); 8589 8590 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) 8591 { 8592 u32 reg; 8593 u16 efuse_ctrl_reg; 8594 u16 efuse_data0_reg; 8595 u16 efuse_data1_reg; 8596 u16 efuse_data2_reg; 8597 u16 efuse_data3_reg; 8598 8599 if (rt2x00_rt(rt2x00dev, RT3290)) { 8600 efuse_ctrl_reg = EFUSE_CTRL_3290; 8601 efuse_data0_reg = EFUSE_DATA0_3290; 8602 efuse_data1_reg = EFUSE_DATA1_3290; 8603 efuse_data2_reg = EFUSE_DATA2_3290; 8604 efuse_data3_reg = EFUSE_DATA3_3290; 8605 } else { 8606 efuse_ctrl_reg = EFUSE_CTRL; 8607 efuse_data0_reg = EFUSE_DATA0; 8608 efuse_data1_reg = EFUSE_DATA1; 8609 efuse_data2_reg = EFUSE_DATA2; 8610 efuse_data3_reg = EFUSE_DATA3; 8611 } 8612 mutex_lock(&rt2x00dev->csr_mutex); 8613 8614 reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg); 8615 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); 8616 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); 8617 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); 8618 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); 8619 8620 /* Wait until the EEPROM has been loaded */ 8621 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); 8622 /* Apparently the data is read from end to start */ 8623 reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg); 8624 /* The returned value is in CPU order, but eeprom is le */ 8625 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); 8626 reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg); 8627 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); 8628 reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg); 8629 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); 8630 reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg); 8631 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); 8632 8633 mutex_unlock(&rt2x00dev->csr_mutex); 8634 } 8635 8636 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 8637 { 8638 unsigned int i; 8639 8640 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) 8641 rt2800_efuse_read(rt2x00dev, i); 8642 8643 return 0; 8644 } 8645 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); 8646 8647 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev) 8648 { 8649 u16 word; 8650 8651 if (rt2x00_rt(rt2x00dev, RT3593)) 8652 return 0; 8653 8654 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG); 8655 if ((word & 0x00ff) != 0x00ff) 8656 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL); 8657 8658 return 0; 8659 } 8660 8661 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev) 8662 { 8663 u16 word; 8664 8665 if (rt2x00_rt(rt2x00dev, RT3593)) 8666 return 0; 8667 8668 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A); 8669 if ((word & 0x00ff) != 0x00ff) 8670 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL); 8671 8672 return 0; 8673 } 8674 8675 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) 8676 { 8677 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 8678 u16 word; 8679 u8 *mac; 8680 u8 default_lna_gain; 8681 int retval; 8682 8683 /* 8684 * Read the EEPROM. 8685 */ 8686 retval = rt2800_read_eeprom(rt2x00dev); 8687 if (retval) 8688 return retval; 8689 8690 /* 8691 * Start validation of the data that has been read. 8692 */ 8693 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 8694 rt2x00lib_set_mac_address(rt2x00dev, mac); 8695 8696 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 8697 if (word == 0xffff) { 8698 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 8699 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); 8700 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); 8701 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 8702 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 8703 } else if (rt2x00_rt(rt2x00dev, RT2860) || 8704 rt2x00_rt(rt2x00dev, RT2872)) { 8705 /* 8706 * There is a max of 2 RX streams for RT28x0 series 8707 */ 8708 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2) 8709 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 8710 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 8711 } 8712 8713 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 8714 if (word == 0xffff) { 8715 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); 8716 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); 8717 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0); 8718 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0); 8719 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0); 8720 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0); 8721 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0); 8722 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0); 8723 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0); 8724 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0); 8725 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0); 8726 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0); 8727 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0); 8728 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); 8729 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); 8730 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); 8731 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 8732 } 8733 8734 word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 8735 if ((word & 0x00ff) == 0x00ff) { 8736 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 8737 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 8738 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); 8739 } 8740 if ((word & 0xff00) == 0xff00) { 8741 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, 8742 LED_MODE_TXRX_ACTIVITY); 8743 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); 8744 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 8745 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); 8746 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); 8747 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); 8748 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word); 8749 } 8750 8751 /* 8752 * During the LNA validation we are going to use 8753 * lna0 as correct value. Note that EEPROM_LNA 8754 * is never validated. 8755 */ 8756 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 8757 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); 8758 8759 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 8760 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) 8761 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); 8762 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) 8763 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); 8764 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); 8765 8766 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev); 8767 8768 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 8769 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) 8770 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); 8771 if (!rt2x00_rt(rt2x00dev, RT3593)) { 8772 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || 8773 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) 8774 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, 8775 default_lna_gain); 8776 } 8777 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); 8778 8779 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev); 8780 8781 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 8782 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) 8783 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); 8784 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) 8785 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); 8786 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); 8787 8788 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 8789 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) 8790 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); 8791 if (!rt2x00_rt(rt2x00dev, RT3593)) { 8792 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || 8793 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) 8794 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, 8795 default_lna_gain); 8796 } 8797 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); 8798 8799 if (rt2x00_rt(rt2x00dev, RT3593)) { 8800 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 8801 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 || 8802 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff) 8803 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 8804 default_lna_gain); 8805 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 || 8806 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff) 8807 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 8808 default_lna_gain); 8809 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word); 8810 } 8811 8812 return 0; 8813 } 8814 8815 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) 8816 { 8817 u16 value; 8818 u16 eeprom; 8819 u16 rf; 8820 8821 /* 8822 * Read EEPROM word for configuration. 8823 */ 8824 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 8825 8826 /* 8827 * Identify RF chipset by EEPROM value 8828 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 8829 * RT53xx: defined in "EEPROM_CHIP_ID" field 8830 */ 8831 if (rt2x00_rt(rt2x00dev, RT3290) || 8832 rt2x00_rt(rt2x00dev, RT5390) || 8833 rt2x00_rt(rt2x00dev, RT5392) || 8834 rt2x00_rt(rt2x00dev, RT6352)) 8835 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID); 8836 else if (rt2x00_rt(rt2x00dev, RT3352)) 8837 rf = RF3322; 8838 else if (rt2x00_rt(rt2x00dev, RT5350)) 8839 rf = RF5350; 8840 else 8841 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 8842 8843 switch (rf) { 8844 case RF2820: 8845 case RF2850: 8846 case RF2720: 8847 case RF2750: 8848 case RF3020: 8849 case RF2020: 8850 case RF3021: 8851 case RF3022: 8852 case RF3052: 8853 case RF3053: 8854 case RF3070: 8855 case RF3290: 8856 case RF3320: 8857 case RF3322: 8858 case RF5350: 8859 case RF5360: 8860 case RF5362: 8861 case RF5370: 8862 case RF5372: 8863 case RF5390: 8864 case RF5392: 8865 case RF5592: 8866 case RF7620: 8867 break; 8868 default: 8869 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n", 8870 rf); 8871 return -ENODEV; 8872 } 8873 8874 rt2x00_set_rf(rt2x00dev, rf); 8875 8876 /* 8877 * Identify default antenna configuration. 8878 */ 8879 rt2x00dev->default_ant.tx_chain_num = 8880 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); 8881 rt2x00dev->default_ant.rx_chain_num = 8882 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); 8883 8884 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 8885 8886 if (rt2x00_rt(rt2x00dev, RT3070) || 8887 rt2x00_rt(rt2x00dev, RT3090) || 8888 rt2x00_rt(rt2x00dev, RT3352) || 8889 rt2x00_rt(rt2x00dev, RT3390)) { 8890 value = rt2x00_get_field16(eeprom, 8891 EEPROM_NIC_CONF1_ANT_DIVERSITY); 8892 switch (value) { 8893 case 0: 8894 case 1: 8895 case 2: 8896 rt2x00dev->default_ant.tx = ANTENNA_A; 8897 rt2x00dev->default_ant.rx = ANTENNA_A; 8898 break; 8899 case 3: 8900 rt2x00dev->default_ant.tx = ANTENNA_A; 8901 rt2x00dev->default_ant.rx = ANTENNA_B; 8902 break; 8903 } 8904 } else { 8905 rt2x00dev->default_ant.tx = ANTENNA_A; 8906 rt2x00dev->default_ant.rx = ANTENNA_A; 8907 } 8908 8909 /* These chips have hardware RX antenna diversity */ 8910 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 8911 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 8912 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */ 8913 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */ 8914 } 8915 8916 /* 8917 * Determine external LNA informations. 8918 */ 8919 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G)) 8920 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); 8921 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G)) 8922 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); 8923 8924 /* 8925 * Detect if this device has an hardware controlled radio. 8926 */ 8927 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO)) 8928 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 8929 8930 /* 8931 * Detect if this device has Bluetooth co-existence. 8932 */ 8933 if (!rt2x00_rt(rt2x00dev, RT3352) && 8934 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) 8935 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); 8936 8937 /* 8938 * Read frequency offset and RF programming sequence. 8939 */ 8940 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 8941 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 8942 8943 /* 8944 * Store led settings, for correct led behaviour. 8945 */ 8946 #ifdef CONFIG_RT2X00_LIB_LEDS 8947 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 8948 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 8949 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 8950 8951 rt2x00dev->led_mcu_reg = eeprom; 8952 #endif /* CONFIG_RT2X00_LIB_LEDS */ 8953 8954 /* 8955 * Check if support EIRP tx power limit feature. 8956 */ 8957 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 8958 8959 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < 8960 EIRP_MAX_TX_POWER_LIMIT) 8961 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); 8962 8963 /* 8964 * Detect if device uses internal or external PA 8965 */ 8966 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 8967 8968 if (rt2x00_rt(rt2x00dev, RT3352)) { 8969 if (rt2x00_get_field16(eeprom, 8970 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352)) 8971 __set_bit(CAPABILITY_EXTERNAL_PA_TX0, 8972 &rt2x00dev->cap_flags); 8973 if (rt2x00_get_field16(eeprom, 8974 EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352)) 8975 __set_bit(CAPABILITY_EXTERNAL_PA_TX1, 8976 &rt2x00dev->cap_flags); 8977 } 8978 8979 return 0; 8980 } 8981 8982 /* 8983 * RF value list for rt28xx 8984 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) 8985 */ 8986 static const struct rf_channel rf_vals[] = { 8987 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, 8988 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, 8989 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, 8990 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, 8991 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, 8992 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, 8993 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, 8994 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, 8995 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, 8996 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, 8997 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, 8998 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, 8999 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, 9000 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, 9001 9002 /* 802.11 UNI / HyperLan 2 */ 9003 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, 9004 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, 9005 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, 9006 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, 9007 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, 9008 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, 9009 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, 9010 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, 9011 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, 9012 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, 9013 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, 9014 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, 9015 9016 /* 802.11 HyperLan 2 */ 9017 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, 9018 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, 9019 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, 9020 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, 9021 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, 9022 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, 9023 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, 9024 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, 9025 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, 9026 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, 9027 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, 9028 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, 9029 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, 9030 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, 9031 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, 9032 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, 9033 9034 /* 802.11 UNII */ 9035 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, 9036 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, 9037 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, 9038 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, 9039 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, 9040 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, 9041 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, 9042 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, 9043 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, 9044 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, 9045 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, 9046 9047 /* 802.11 Japan */ 9048 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, 9049 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, 9050 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, 9051 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, 9052 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, 9053 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, 9054 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, 9055 }; 9056 9057 /* 9058 * RF value list for rt3xxx 9059 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053) 9060 */ 9061 static const struct rf_channel rf_vals_3x[] = { 9062 {1, 241, 2, 2 }, 9063 {2, 241, 2, 7 }, 9064 {3, 242, 2, 2 }, 9065 {4, 242, 2, 7 }, 9066 {5, 243, 2, 2 }, 9067 {6, 243, 2, 7 }, 9068 {7, 244, 2, 2 }, 9069 {8, 244, 2, 7 }, 9070 {9, 245, 2, 2 }, 9071 {10, 245, 2, 7 }, 9072 {11, 246, 2, 2 }, 9073 {12, 246, 2, 7 }, 9074 {13, 247, 2, 2 }, 9075 {14, 248, 2, 4 }, 9076 9077 /* 802.11 UNI / HyperLan 2 */ 9078 {36, 0x56, 0, 4}, 9079 {38, 0x56, 0, 6}, 9080 {40, 0x56, 0, 8}, 9081 {44, 0x57, 0, 0}, 9082 {46, 0x57, 0, 2}, 9083 {48, 0x57, 0, 4}, 9084 {52, 0x57, 0, 8}, 9085 {54, 0x57, 0, 10}, 9086 {56, 0x58, 0, 0}, 9087 {60, 0x58, 0, 4}, 9088 {62, 0x58, 0, 6}, 9089 {64, 0x58, 0, 8}, 9090 9091 /* 802.11 HyperLan 2 */ 9092 {100, 0x5b, 0, 8}, 9093 {102, 0x5b, 0, 10}, 9094 {104, 0x5c, 0, 0}, 9095 {108, 0x5c, 0, 4}, 9096 {110, 0x5c, 0, 6}, 9097 {112, 0x5c, 0, 8}, 9098 {116, 0x5d, 0, 0}, 9099 {118, 0x5d, 0, 2}, 9100 {120, 0x5d, 0, 4}, 9101 {124, 0x5d, 0, 8}, 9102 {126, 0x5d, 0, 10}, 9103 {128, 0x5e, 0, 0}, 9104 {132, 0x5e, 0, 4}, 9105 {134, 0x5e, 0, 6}, 9106 {136, 0x5e, 0, 8}, 9107 {140, 0x5f, 0, 0}, 9108 9109 /* 802.11 UNII */ 9110 {149, 0x5f, 0, 9}, 9111 {151, 0x5f, 0, 11}, 9112 {153, 0x60, 0, 1}, 9113 {157, 0x60, 0, 5}, 9114 {159, 0x60, 0, 7}, 9115 {161, 0x60, 0, 9}, 9116 {165, 0x61, 0, 1}, 9117 {167, 0x61, 0, 3}, 9118 {169, 0x61, 0, 5}, 9119 {171, 0x61, 0, 7}, 9120 {173, 0x61, 0, 9}, 9121 }; 9122 9123 /* 9124 * RF value list for rt3xxx with Xtal20MHz 9125 * Supports: 2.4 GHz (all) (RF3322) 9126 */ 9127 static const struct rf_channel rf_vals_3x_xtal20[] = { 9128 {1, 0xE2, 2, 0x14}, 9129 {2, 0xE3, 2, 0x14}, 9130 {3, 0xE4, 2, 0x14}, 9131 {4, 0xE5, 2, 0x14}, 9132 {5, 0xE6, 2, 0x14}, 9133 {6, 0xE7, 2, 0x14}, 9134 {7, 0xE8, 2, 0x14}, 9135 {8, 0xE9, 2, 0x14}, 9136 {9, 0xEA, 2, 0x14}, 9137 {10, 0xEB, 2, 0x14}, 9138 {11, 0xEC, 2, 0x14}, 9139 {12, 0xED, 2, 0x14}, 9140 {13, 0xEE, 2, 0x14}, 9141 {14, 0xF0, 2, 0x18}, 9142 }; 9143 9144 static const struct rf_channel rf_vals_5592_xtal20[] = { 9145 /* Channel, N, K, mod, R */ 9146 {1, 482, 4, 10, 3}, 9147 {2, 483, 4, 10, 3}, 9148 {3, 484, 4, 10, 3}, 9149 {4, 485, 4, 10, 3}, 9150 {5, 486, 4, 10, 3}, 9151 {6, 487, 4, 10, 3}, 9152 {7, 488, 4, 10, 3}, 9153 {8, 489, 4, 10, 3}, 9154 {9, 490, 4, 10, 3}, 9155 {10, 491, 4, 10, 3}, 9156 {11, 492, 4, 10, 3}, 9157 {12, 493, 4, 10, 3}, 9158 {13, 494, 4, 10, 3}, 9159 {14, 496, 8, 10, 3}, 9160 {36, 172, 8, 12, 1}, 9161 {38, 173, 0, 12, 1}, 9162 {40, 173, 4, 12, 1}, 9163 {42, 173, 8, 12, 1}, 9164 {44, 174, 0, 12, 1}, 9165 {46, 174, 4, 12, 1}, 9166 {48, 174, 8, 12, 1}, 9167 {50, 175, 0, 12, 1}, 9168 {52, 175, 4, 12, 1}, 9169 {54, 175, 8, 12, 1}, 9170 {56, 176, 0, 12, 1}, 9171 {58, 176, 4, 12, 1}, 9172 {60, 176, 8, 12, 1}, 9173 {62, 177, 0, 12, 1}, 9174 {64, 177, 4, 12, 1}, 9175 {100, 183, 4, 12, 1}, 9176 {102, 183, 8, 12, 1}, 9177 {104, 184, 0, 12, 1}, 9178 {106, 184, 4, 12, 1}, 9179 {108, 184, 8, 12, 1}, 9180 {110, 185, 0, 12, 1}, 9181 {112, 185, 4, 12, 1}, 9182 {114, 185, 8, 12, 1}, 9183 {116, 186, 0, 12, 1}, 9184 {118, 186, 4, 12, 1}, 9185 {120, 186, 8, 12, 1}, 9186 {122, 187, 0, 12, 1}, 9187 {124, 187, 4, 12, 1}, 9188 {126, 187, 8, 12, 1}, 9189 {128, 188, 0, 12, 1}, 9190 {130, 188, 4, 12, 1}, 9191 {132, 188, 8, 12, 1}, 9192 {134, 189, 0, 12, 1}, 9193 {136, 189, 4, 12, 1}, 9194 {138, 189, 8, 12, 1}, 9195 {140, 190, 0, 12, 1}, 9196 {149, 191, 6, 12, 1}, 9197 {151, 191, 10, 12, 1}, 9198 {153, 192, 2, 12, 1}, 9199 {155, 192, 6, 12, 1}, 9200 {157, 192, 10, 12, 1}, 9201 {159, 193, 2, 12, 1}, 9202 {161, 193, 6, 12, 1}, 9203 {165, 194, 2, 12, 1}, 9204 {184, 164, 0, 12, 1}, 9205 {188, 164, 4, 12, 1}, 9206 {192, 165, 8, 12, 1}, 9207 {196, 166, 0, 12, 1}, 9208 }; 9209 9210 static const struct rf_channel rf_vals_5592_xtal40[] = { 9211 /* Channel, N, K, mod, R */ 9212 {1, 241, 2, 10, 3}, 9213 {2, 241, 7, 10, 3}, 9214 {3, 242, 2, 10, 3}, 9215 {4, 242, 7, 10, 3}, 9216 {5, 243, 2, 10, 3}, 9217 {6, 243, 7, 10, 3}, 9218 {7, 244, 2, 10, 3}, 9219 {8, 244, 7, 10, 3}, 9220 {9, 245, 2, 10, 3}, 9221 {10, 245, 7, 10, 3}, 9222 {11, 246, 2, 10, 3}, 9223 {12, 246, 7, 10, 3}, 9224 {13, 247, 2, 10, 3}, 9225 {14, 248, 4, 10, 3}, 9226 {36, 86, 4, 12, 1}, 9227 {38, 86, 6, 12, 1}, 9228 {40, 86, 8, 12, 1}, 9229 {42, 86, 10, 12, 1}, 9230 {44, 87, 0, 12, 1}, 9231 {46, 87, 2, 12, 1}, 9232 {48, 87, 4, 12, 1}, 9233 {50, 87, 6, 12, 1}, 9234 {52, 87, 8, 12, 1}, 9235 {54, 87, 10, 12, 1}, 9236 {56, 88, 0, 12, 1}, 9237 {58, 88, 2, 12, 1}, 9238 {60, 88, 4, 12, 1}, 9239 {62, 88, 6, 12, 1}, 9240 {64, 88, 8, 12, 1}, 9241 {100, 91, 8, 12, 1}, 9242 {102, 91, 10, 12, 1}, 9243 {104, 92, 0, 12, 1}, 9244 {106, 92, 2, 12, 1}, 9245 {108, 92, 4, 12, 1}, 9246 {110, 92, 6, 12, 1}, 9247 {112, 92, 8, 12, 1}, 9248 {114, 92, 10, 12, 1}, 9249 {116, 93, 0, 12, 1}, 9250 {118, 93, 2, 12, 1}, 9251 {120, 93, 4, 12, 1}, 9252 {122, 93, 6, 12, 1}, 9253 {124, 93, 8, 12, 1}, 9254 {126, 93, 10, 12, 1}, 9255 {128, 94, 0, 12, 1}, 9256 {130, 94, 2, 12, 1}, 9257 {132, 94, 4, 12, 1}, 9258 {134, 94, 6, 12, 1}, 9259 {136, 94, 8, 12, 1}, 9260 {138, 94, 10, 12, 1}, 9261 {140, 95, 0, 12, 1}, 9262 {149, 95, 9, 12, 1}, 9263 {151, 95, 11, 12, 1}, 9264 {153, 96, 1, 12, 1}, 9265 {155, 96, 3, 12, 1}, 9266 {157, 96, 5, 12, 1}, 9267 {159, 96, 7, 12, 1}, 9268 {161, 96, 9, 12, 1}, 9269 {165, 97, 1, 12, 1}, 9270 {184, 82, 0, 12, 1}, 9271 {188, 82, 4, 12, 1}, 9272 {192, 82, 8, 12, 1}, 9273 {196, 83, 0, 12, 1}, 9274 }; 9275 9276 static const struct rf_channel rf_vals_7620[] = { 9277 {1, 0x50, 0x99, 0x99, 1}, 9278 {2, 0x50, 0x44, 0x44, 2}, 9279 {3, 0x50, 0xEE, 0xEE, 2}, 9280 {4, 0x50, 0x99, 0x99, 3}, 9281 {5, 0x51, 0x44, 0x44, 0}, 9282 {6, 0x51, 0xEE, 0xEE, 0}, 9283 {7, 0x51, 0x99, 0x99, 1}, 9284 {8, 0x51, 0x44, 0x44, 2}, 9285 {9, 0x51, 0xEE, 0xEE, 2}, 9286 {10, 0x51, 0x99, 0x99, 3}, 9287 {11, 0x52, 0x44, 0x44, 0}, 9288 {12, 0x52, 0xEE, 0xEE, 0}, 9289 {13, 0x52, 0x99, 0x99, 1}, 9290 {14, 0x52, 0x33, 0x33, 3}, 9291 }; 9292 9293 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 9294 { 9295 struct hw_mode_spec *spec = &rt2x00dev->spec; 9296 struct channel_info *info; 9297 char *default_power1; 9298 char *default_power2; 9299 char *default_power3; 9300 unsigned int i, tx_chains, rx_chains; 9301 u32 reg; 9302 9303 /* 9304 * Disable powersaving as default. 9305 */ 9306 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 9307 9308 /* 9309 * Change default retry settings to values corresponding more closely 9310 * to rate[0].count setting of minstrel rate control algorithm. 9311 */ 9312 rt2x00dev->hw->wiphy->retry_short = 2; 9313 rt2x00dev->hw->wiphy->retry_long = 2; 9314 9315 /* 9316 * Initialize all hw fields. 9317 */ 9318 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS); 9319 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION); 9320 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); 9321 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); 9322 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); 9323 9324 /* 9325 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices 9326 * unless we are capable of sending the buffered frames out after the 9327 * DTIM transmission using rt2x00lib_beacondone. This will send out 9328 * multicast and broadcast traffic immediately instead of buffering it 9329 * infinitly and thus dropping it after some time. 9330 */ 9331 if (!rt2x00_is_usb(rt2x00dev)) 9332 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); 9333 9334 /* Set MFP if HW crypto is disabled. */ 9335 if (rt2800_hwcrypt_disabled(rt2x00dev)) 9336 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE); 9337 9338 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 9339 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 9340 rt2800_eeprom_addr(rt2x00dev, 9341 EEPROM_MAC_ADDR_0)); 9342 9343 /* 9344 * As rt2800 has a global fallback table we cannot specify 9345 * more then one tx rate per frame but since the hw will 9346 * try several rates (based on the fallback table) we should 9347 * initialize max_report_rates to the maximum number of rates 9348 * we are going to try. Otherwise mac80211 will truncate our 9349 * reported tx rates and the rc algortihm will end up with 9350 * incorrect data. 9351 */ 9352 rt2x00dev->hw->max_rates = 1; 9353 rt2x00dev->hw->max_report_rates = 7; 9354 rt2x00dev->hw->max_rate_tries = 1; 9355 9356 /* 9357 * Initialize hw_mode information. 9358 */ 9359 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 9360 9361 switch (rt2x00dev->chip.rf) { 9362 case RF2720: 9363 case RF2820: 9364 spec->num_channels = 14; 9365 spec->channels = rf_vals; 9366 break; 9367 9368 case RF2750: 9369 case RF2850: 9370 spec->num_channels = ARRAY_SIZE(rf_vals); 9371 spec->channels = rf_vals; 9372 break; 9373 9374 case RF2020: 9375 case RF3020: 9376 case RF3021: 9377 case RF3022: 9378 case RF3070: 9379 case RF3290: 9380 case RF3320: 9381 case RF3322: 9382 case RF5350: 9383 case RF5360: 9384 case RF5362: 9385 case RF5370: 9386 case RF5372: 9387 case RF5390: 9388 case RF5392: 9389 spec->num_channels = 14; 9390 if (rt2800_clk_is_20mhz(rt2x00dev)) 9391 spec->channels = rf_vals_3x_xtal20; 9392 else 9393 spec->channels = rf_vals_3x; 9394 break; 9395 9396 case RF7620: 9397 spec->num_channels = ARRAY_SIZE(rf_vals_7620); 9398 spec->channels = rf_vals_7620; 9399 break; 9400 9401 case RF3052: 9402 case RF3053: 9403 spec->num_channels = ARRAY_SIZE(rf_vals_3x); 9404 spec->channels = rf_vals_3x; 9405 break; 9406 9407 case RF5592: 9408 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX); 9409 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { 9410 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); 9411 spec->channels = rf_vals_5592_xtal40; 9412 } else { 9413 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20); 9414 spec->channels = rf_vals_5592_xtal20; 9415 } 9416 break; 9417 } 9418 9419 if (WARN_ON_ONCE(!spec->channels)) 9420 return -ENODEV; 9421 9422 spec->supported_bands = SUPPORT_BAND_2GHZ; 9423 if (spec->num_channels > 14) 9424 spec->supported_bands |= SUPPORT_BAND_5GHZ; 9425 9426 /* 9427 * Initialize HT information. 9428 */ 9429 if (!rt2x00_rf(rt2x00dev, RF2020)) 9430 spec->ht.ht_supported = true; 9431 else 9432 spec->ht.ht_supported = false; 9433 9434 spec->ht.cap = 9435 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 9436 IEEE80211_HT_CAP_GRN_FLD | 9437 IEEE80211_HT_CAP_SGI_20 | 9438 IEEE80211_HT_CAP_SGI_40; 9439 9440 tx_chains = rt2x00dev->default_ant.tx_chain_num; 9441 rx_chains = rt2x00dev->default_ant.rx_chain_num; 9442 9443 if (tx_chains >= 2) 9444 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; 9445 9446 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT; 9447 9448 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2; 9449 spec->ht.ampdu_density = 4; 9450 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 9451 if (tx_chains != rx_chains) { 9452 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 9453 spec->ht.mcs.tx_params |= 9454 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; 9455 } 9456 9457 switch (rx_chains) { 9458 case 3: 9459 spec->ht.mcs.rx_mask[2] = 0xff; 9460 case 2: 9461 spec->ht.mcs.rx_mask[1] = 0xff; 9462 case 1: 9463 spec->ht.mcs.rx_mask[0] = 0xff; 9464 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ 9465 break; 9466 } 9467 9468 /* 9469 * Create channel information array 9470 */ 9471 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 9472 if (!info) 9473 return -ENOMEM; 9474 9475 spec->channels_info = info; 9476 9477 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 9478 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 9479 9480 if (rt2x00dev->default_ant.tx_chain_num > 2) 9481 default_power3 = rt2800_eeprom_addr(rt2x00dev, 9482 EEPROM_EXT_TXPOWER_BG3); 9483 else 9484 default_power3 = NULL; 9485 9486 for (i = 0; i < 14; i++) { 9487 info[i].default_power1 = default_power1[i]; 9488 info[i].default_power2 = default_power2[i]; 9489 if (default_power3) 9490 info[i].default_power3 = default_power3[i]; 9491 } 9492 9493 if (spec->num_channels > 14) { 9494 default_power1 = rt2800_eeprom_addr(rt2x00dev, 9495 EEPROM_TXPOWER_A1); 9496 default_power2 = rt2800_eeprom_addr(rt2x00dev, 9497 EEPROM_TXPOWER_A2); 9498 9499 if (rt2x00dev->default_ant.tx_chain_num > 2) 9500 default_power3 = 9501 rt2800_eeprom_addr(rt2x00dev, 9502 EEPROM_EXT_TXPOWER_A3); 9503 else 9504 default_power3 = NULL; 9505 9506 for (i = 14; i < spec->num_channels; i++) { 9507 info[i].default_power1 = default_power1[i - 14]; 9508 info[i].default_power2 = default_power2[i - 14]; 9509 if (default_power3) 9510 info[i].default_power3 = default_power3[i - 14]; 9511 } 9512 } 9513 9514 switch (rt2x00dev->chip.rf) { 9515 case RF2020: 9516 case RF3020: 9517 case RF3021: 9518 case RF3022: 9519 case RF3320: 9520 case RF3052: 9521 case RF3053: 9522 case RF3070: 9523 case RF3290: 9524 case RF5350: 9525 case RF5360: 9526 case RF5362: 9527 case RF5370: 9528 case RF5372: 9529 case RF5390: 9530 case RF5392: 9531 case RF5592: 9532 case RF7620: 9533 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags); 9534 break; 9535 } 9536 9537 return 0; 9538 } 9539 9540 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) 9541 { 9542 u32 reg; 9543 u32 rt; 9544 u32 rev; 9545 9546 if (rt2x00_rt(rt2x00dev, RT3290)) 9547 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290); 9548 else 9549 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 9550 9551 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); 9552 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); 9553 9554 switch (rt) { 9555 case RT2860: 9556 case RT2872: 9557 case RT2883: 9558 case RT3070: 9559 case RT3071: 9560 case RT3090: 9561 case RT3290: 9562 case RT3352: 9563 case RT3390: 9564 case RT3572: 9565 case RT3593: 9566 case RT5350: 9567 case RT5390: 9568 case RT5392: 9569 case RT5592: 9570 break; 9571 default: 9572 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n", 9573 rt, rev); 9574 return -ENODEV; 9575 } 9576 9577 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev)) 9578 rt = RT6352; 9579 9580 rt2x00_set_rt(rt2x00dev, rt, rev); 9581 9582 return 0; 9583 } 9584 9585 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) 9586 { 9587 int retval; 9588 u32 reg; 9589 9590 retval = rt2800_probe_rt(rt2x00dev); 9591 if (retval) 9592 return retval; 9593 9594 /* 9595 * Allocate eeprom data. 9596 */ 9597 retval = rt2800_validate_eeprom(rt2x00dev); 9598 if (retval) 9599 return retval; 9600 9601 retval = rt2800_init_eeprom(rt2x00dev); 9602 if (retval) 9603 return retval; 9604 9605 /* 9606 * Enable rfkill polling by setting GPIO direction of the 9607 * rfkill switch GPIO pin correctly. 9608 */ 9609 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 9610 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); 9611 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 9612 9613 /* 9614 * Initialize hw specifications. 9615 */ 9616 retval = rt2800_probe_hw_mode(rt2x00dev); 9617 if (retval) 9618 return retval; 9619 9620 /* 9621 * Set device capabilities. 9622 */ 9623 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); 9624 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags); 9625 if (!rt2x00_is_usb(rt2x00dev)) 9626 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags); 9627 9628 /* 9629 * Set device requirements. 9630 */ 9631 if (!rt2x00_is_soc(rt2x00dev)) 9632 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); 9633 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags); 9634 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags); 9635 if (!rt2800_hwcrypt_disabled(rt2x00dev)) 9636 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); 9637 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 9638 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags); 9639 if (rt2x00_is_usb(rt2x00dev)) 9640 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); 9641 else { 9642 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); 9643 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags); 9644 } 9645 9646 /* 9647 * Set the rssi offset. 9648 */ 9649 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 9650 9651 return 0; 9652 } 9653 EXPORT_SYMBOL_GPL(rt2800_probe_hw); 9654 9655 /* 9656 * IEEE80211 stack callback functions. 9657 */ 9658 void rt2800_get_key_seq(struct ieee80211_hw *hw, 9659 struct ieee80211_key_conf *key, 9660 struct ieee80211_key_seq *seq) 9661 { 9662 struct rt2x00_dev *rt2x00dev = hw->priv; 9663 struct mac_iveiv_entry iveiv_entry; 9664 u32 offset; 9665 9666 if (key->cipher != WLAN_CIPHER_SUITE_TKIP) 9667 return; 9668 9669 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 9670 rt2800_register_multiread(rt2x00dev, offset, 9671 &iveiv_entry, sizeof(iveiv_entry)); 9672 9673 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2); 9674 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4); 9675 } 9676 EXPORT_SYMBOL_GPL(rt2800_get_key_seq); 9677 9678 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) 9679 { 9680 struct rt2x00_dev *rt2x00dev = hw->priv; 9681 u32 reg; 9682 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); 9683 9684 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 9685 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); 9686 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 9687 9688 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 9689 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); 9690 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 9691 9692 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 9693 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); 9694 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 9695 9696 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 9697 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); 9698 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 9699 9700 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 9701 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); 9702 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 9703 9704 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 9705 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); 9706 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 9707 9708 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 9709 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); 9710 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 9711 9712 return 0; 9713 } 9714 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold); 9715 9716 int rt2800_conf_tx(struct ieee80211_hw *hw, 9717 struct ieee80211_vif *vif, u16 queue_idx, 9718 const struct ieee80211_tx_queue_params *params) 9719 { 9720 struct rt2x00_dev *rt2x00dev = hw->priv; 9721 struct data_queue *queue; 9722 struct rt2x00_field32 field; 9723 int retval; 9724 u32 reg; 9725 u32 offset; 9726 9727 /* 9728 * First pass the configuration through rt2x00lib, that will 9729 * update the queue settings and validate the input. After that 9730 * we are free to update the registers based on the value 9731 * in the queue parameter. 9732 */ 9733 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params); 9734 if (retval) 9735 return retval; 9736 9737 /* 9738 * We only need to perform additional register initialization 9739 * for WMM queues/ 9740 */ 9741 if (queue_idx >= 4) 9742 return 0; 9743 9744 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 9745 9746 /* Update WMM TXOP register */ 9747 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); 9748 field.bit_offset = (queue_idx & 1) * 16; 9749 field.bit_mask = 0xffff << field.bit_offset; 9750 9751 reg = rt2800_register_read(rt2x00dev, offset); 9752 rt2x00_set_field32(®, field, queue->txop); 9753 rt2800_register_write(rt2x00dev, offset, reg); 9754 9755 /* Update WMM registers */ 9756 field.bit_offset = queue_idx * 4; 9757 field.bit_mask = 0xf << field.bit_offset; 9758 9759 reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG); 9760 rt2x00_set_field32(®, field, queue->aifs); 9761 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); 9762 9763 reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG); 9764 rt2x00_set_field32(®, field, queue->cw_min); 9765 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); 9766 9767 reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG); 9768 rt2x00_set_field32(®, field, queue->cw_max); 9769 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); 9770 9771 /* Update EDCA registers */ 9772 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); 9773 9774 reg = rt2800_register_read(rt2x00dev, offset); 9775 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); 9776 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); 9777 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); 9778 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); 9779 rt2800_register_write(rt2x00dev, offset, reg); 9780 9781 return 0; 9782 } 9783 EXPORT_SYMBOL_GPL(rt2800_conf_tx); 9784 9785 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 9786 { 9787 struct rt2x00_dev *rt2x00dev = hw->priv; 9788 u64 tsf; 9789 u32 reg; 9790 9791 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1); 9792 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; 9793 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0); 9794 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); 9795 9796 return tsf; 9797 } 9798 EXPORT_SYMBOL_GPL(rt2800_get_tsf); 9799 9800 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 9801 struct ieee80211_ampdu_params *params) 9802 { 9803 struct ieee80211_sta *sta = params->sta; 9804 enum ieee80211_ampdu_mlme_action action = params->action; 9805 u16 tid = params->tid; 9806 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv; 9807 int ret = 0; 9808 9809 /* 9810 * Don't allow aggregation for stations the hardware isn't aware 9811 * of because tx status reports for frames to an unknown station 9812 * always contain wcid=WCID_END+1 and thus we can't distinguish 9813 * between multiple stations which leads to unwanted situations 9814 * when the hw reorders frames due to aggregation. 9815 */ 9816 if (sta_priv->wcid > WCID_END) 9817 return 1; 9818 9819 switch (action) { 9820 case IEEE80211_AMPDU_RX_START: 9821 case IEEE80211_AMPDU_RX_STOP: 9822 /* 9823 * The hw itself takes care of setting up BlockAck mechanisms. 9824 * So, we only have to allow mac80211 to nagotiate a BlockAck 9825 * agreement. Once that is done, the hw will BlockAck incoming 9826 * AMPDUs without further setup. 9827 */ 9828 break; 9829 case IEEE80211_AMPDU_TX_START: 9830 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 9831 break; 9832 case IEEE80211_AMPDU_TX_STOP_CONT: 9833 case IEEE80211_AMPDU_TX_STOP_FLUSH: 9834 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 9835 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 9836 break; 9837 case IEEE80211_AMPDU_TX_OPERATIONAL: 9838 break; 9839 default: 9840 rt2x00_warn((struct rt2x00_dev *)hw->priv, 9841 "Unknown AMPDU action\n"); 9842 } 9843 9844 return ret; 9845 } 9846 EXPORT_SYMBOL_GPL(rt2800_ampdu_action); 9847 9848 int rt2800_get_survey(struct ieee80211_hw *hw, int idx, 9849 struct survey_info *survey) 9850 { 9851 struct rt2x00_dev *rt2x00dev = hw->priv; 9852 struct ieee80211_conf *conf = &hw->conf; 9853 u32 idle, busy, busy_ext; 9854 9855 if (idx != 0) 9856 return -ENOENT; 9857 9858 survey->channel = conf->chandef.chan; 9859 9860 idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 9861 busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 9862 busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 9863 9864 if (idle || busy) { 9865 survey->filled = SURVEY_INFO_TIME | 9866 SURVEY_INFO_TIME_BUSY | 9867 SURVEY_INFO_TIME_EXT_BUSY; 9868 9869 survey->time = (idle + busy) / 1000; 9870 survey->time_busy = busy / 1000; 9871 survey->time_ext_busy = busy_ext / 1000; 9872 } 9873 9874 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 9875 survey->filled |= SURVEY_INFO_IN_USE; 9876 9877 return 0; 9878 9879 } 9880 EXPORT_SYMBOL_GPL(rt2800_get_survey); 9881 9882 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); 9883 MODULE_VERSION(DRV_VERSION); 9884 MODULE_DESCRIPTION("Ralink RT2800 library"); 9885 MODULE_LICENSE("GPL"); 9886