1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 4 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> 5 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 6 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> 7 8 Based on the original rt2800pci.c and rt2800usb.c. 9 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 10 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 11 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 12 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 13 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 14 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 15 <http://rt2x00.serialmonkey.com> 16 17 */ 18 19 /* 20 Module: rt2800lib 21 Abstract: rt2800 generic device routines. 22 */ 23 24 #include <linux/crc-ccitt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/slab.h> 28 29 #include "rt2x00.h" 30 #include "rt2800lib.h" 31 #include "rt2800.h" 32 33 /* 34 * Register access. 35 * All access to the CSR registers will go through the methods 36 * rt2800_register_read and rt2800_register_write. 37 * BBP and RF register require indirect register access, 38 * and use the CSR registers BBPCSR and RFCSR to achieve this. 39 * These indirect registers work with busy bits, 40 * and we will try maximal REGISTER_BUSY_COUNT times to access 41 * the register while taking a REGISTER_BUSY_DELAY us delay 42 * between each attampt. When the busy bit is still set at that time, 43 * the access attempt is considered to have failed, 44 * and we will print an error. 45 * The _lock versions must be used if you already hold the csr_mutex 46 */ 47 #define WAIT_FOR_BBP(__dev, __reg) \ 48 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) 49 #define WAIT_FOR_RFCSR(__dev, __reg) \ 50 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) 51 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \ 52 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \ 53 (__reg)) 54 #define WAIT_FOR_RF(__dev, __reg) \ 55 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) 56 #define WAIT_FOR_MCU(__dev, __reg) \ 57 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 58 H2M_MAILBOX_CSR_OWNER, (__reg)) 59 60 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) 61 { 62 /* check for rt2872 on SoC */ 63 if (!rt2x00_is_soc(rt2x00dev) || 64 !rt2x00_rt(rt2x00dev, RT2872)) 65 return false; 66 67 /* we know for sure that these rf chipsets are used on rt305x boards */ 68 if (rt2x00_rf(rt2x00dev, RF3020) || 69 rt2x00_rf(rt2x00dev, RF3021) || 70 rt2x00_rf(rt2x00dev, RF3022)) 71 return true; 72 73 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n"); 74 return false; 75 } 76 77 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, 78 const unsigned int word, const u8 value) 79 { 80 u32 reg; 81 82 mutex_lock(&rt2x00dev->csr_mutex); 83 84 /* 85 * Wait until the BBP becomes available, afterwards we 86 * can safely write the new data into the register. 87 */ 88 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 89 reg = 0; 90 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); 91 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 92 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 93 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); 94 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 95 96 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 97 } 98 99 mutex_unlock(&rt2x00dev->csr_mutex); 100 } 101 102 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word) 103 { 104 u32 reg; 105 u8 value; 106 107 mutex_lock(&rt2x00dev->csr_mutex); 108 109 /* 110 * Wait until the BBP becomes available, afterwards we 111 * can safely write the read request into the register. 112 * After the data has been written, we wait until hardware 113 * returns the correct value, if at any time the register 114 * doesn't become available in time, reg will be 0xffffffff 115 * which means we return 0xff to the caller. 116 */ 117 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 118 reg = 0; 119 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 120 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 121 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); 122 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 123 124 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 125 126 WAIT_FOR_BBP(rt2x00dev, ®); 127 } 128 129 value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); 130 131 mutex_unlock(&rt2x00dev->csr_mutex); 132 133 return value; 134 } 135 136 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, 137 const unsigned int word, const u8 value) 138 { 139 u32 reg; 140 141 mutex_lock(&rt2x00dev->csr_mutex); 142 143 /* 144 * Wait until the RFCSR becomes available, afterwards we 145 * can safely write the new data into the register. 146 */ 147 switch (rt2x00dev->chip.rt) { 148 case RT6352: 149 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 150 reg = 0; 151 rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value); 152 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 153 word); 154 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1); 155 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 156 157 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 158 } 159 break; 160 161 default: 162 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 163 reg = 0; 164 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); 165 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 166 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); 167 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 168 169 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 170 } 171 break; 172 } 173 174 mutex_unlock(&rt2x00dev->csr_mutex); 175 } 176 177 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 178 const unsigned int reg, const u8 value) 179 { 180 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value); 181 } 182 183 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev, 184 const unsigned int reg, const u8 value) 185 { 186 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value); 187 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value); 188 } 189 190 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev, 191 const unsigned int reg, const u8 value) 192 { 193 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value); 194 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value); 195 } 196 197 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, 198 const unsigned int word) 199 { 200 u32 reg; 201 u8 value; 202 203 mutex_lock(&rt2x00dev->csr_mutex); 204 205 /* 206 * Wait until the RFCSR becomes available, afterwards we 207 * can safely write the read request into the register. 208 * After the data has been written, we wait until hardware 209 * returns the correct value, if at any time the register 210 * doesn't become available in time, reg will be 0xffffffff 211 * which means we return 0xff to the caller. 212 */ 213 switch (rt2x00dev->chip.rt) { 214 case RT6352: 215 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 216 reg = 0; 217 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 218 word); 219 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0); 220 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 221 222 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 223 224 WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®); 225 } 226 227 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620); 228 break; 229 230 default: 231 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 232 reg = 0; 233 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 234 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); 235 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 236 237 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 238 239 WAIT_FOR_RFCSR(rt2x00dev, ®); 240 } 241 242 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); 243 break; 244 } 245 246 mutex_unlock(&rt2x00dev->csr_mutex); 247 248 return value; 249 } 250 251 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 252 const unsigned int reg) 253 { 254 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6))); 255 } 256 257 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, 258 const unsigned int word, const u32 value) 259 { 260 u32 reg; 261 262 mutex_lock(&rt2x00dev->csr_mutex); 263 264 /* 265 * Wait until the RF becomes available, afterwards we 266 * can safely write the new data into the register. 267 */ 268 if (WAIT_FOR_RF(rt2x00dev, ®)) { 269 reg = 0; 270 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); 271 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); 272 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); 273 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); 274 275 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); 276 rt2x00_rf_write(rt2x00dev, word, value); 277 } 278 279 mutex_unlock(&rt2x00dev->csr_mutex); 280 } 281 282 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { 283 [EEPROM_CHIP_ID] = 0x0000, 284 [EEPROM_VERSION] = 0x0001, 285 [EEPROM_MAC_ADDR_0] = 0x0002, 286 [EEPROM_MAC_ADDR_1] = 0x0003, 287 [EEPROM_MAC_ADDR_2] = 0x0004, 288 [EEPROM_NIC_CONF0] = 0x001a, 289 [EEPROM_NIC_CONF1] = 0x001b, 290 [EEPROM_FREQ] = 0x001d, 291 [EEPROM_LED_AG_CONF] = 0x001e, 292 [EEPROM_LED_ACT_CONF] = 0x001f, 293 [EEPROM_LED_POLARITY] = 0x0020, 294 [EEPROM_NIC_CONF2] = 0x0021, 295 [EEPROM_LNA] = 0x0022, 296 [EEPROM_RSSI_BG] = 0x0023, 297 [EEPROM_RSSI_BG2] = 0x0024, 298 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */ 299 [EEPROM_RSSI_A] = 0x0025, 300 [EEPROM_RSSI_A2] = 0x0026, 301 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */ 302 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027, 303 [EEPROM_TXPOWER_DELTA] = 0x0028, 304 [EEPROM_TXPOWER_BG1] = 0x0029, 305 [EEPROM_TXPOWER_BG2] = 0x0030, 306 [EEPROM_TSSI_BOUND_BG1] = 0x0037, 307 [EEPROM_TSSI_BOUND_BG2] = 0x0038, 308 [EEPROM_TSSI_BOUND_BG3] = 0x0039, 309 [EEPROM_TSSI_BOUND_BG4] = 0x003a, 310 [EEPROM_TSSI_BOUND_BG5] = 0x003b, 311 [EEPROM_TXPOWER_A1] = 0x003c, 312 [EEPROM_TXPOWER_A2] = 0x0053, 313 [EEPROM_TXPOWER_INIT] = 0x0068, 314 [EEPROM_TSSI_BOUND_A1] = 0x006a, 315 [EEPROM_TSSI_BOUND_A2] = 0x006b, 316 [EEPROM_TSSI_BOUND_A3] = 0x006c, 317 [EEPROM_TSSI_BOUND_A4] = 0x006d, 318 [EEPROM_TSSI_BOUND_A5] = 0x006e, 319 [EEPROM_TXPOWER_BYRATE] = 0x006f, 320 [EEPROM_BBP_START] = 0x0078, 321 }; 322 323 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = { 324 [EEPROM_CHIP_ID] = 0x0000, 325 [EEPROM_VERSION] = 0x0001, 326 [EEPROM_MAC_ADDR_0] = 0x0002, 327 [EEPROM_MAC_ADDR_1] = 0x0003, 328 [EEPROM_MAC_ADDR_2] = 0x0004, 329 [EEPROM_NIC_CONF0] = 0x001a, 330 [EEPROM_NIC_CONF1] = 0x001b, 331 [EEPROM_NIC_CONF2] = 0x001c, 332 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020, 333 [EEPROM_FREQ] = 0x0022, 334 [EEPROM_LED_AG_CONF] = 0x0023, 335 [EEPROM_LED_ACT_CONF] = 0x0024, 336 [EEPROM_LED_POLARITY] = 0x0025, 337 [EEPROM_LNA] = 0x0026, 338 [EEPROM_EXT_LNA2] = 0x0027, 339 [EEPROM_RSSI_BG] = 0x0028, 340 [EEPROM_RSSI_BG2] = 0x0029, 341 [EEPROM_RSSI_A] = 0x002a, 342 [EEPROM_RSSI_A2] = 0x002b, 343 [EEPROM_TXPOWER_BG1] = 0x0030, 344 [EEPROM_TXPOWER_BG2] = 0x0037, 345 [EEPROM_EXT_TXPOWER_BG3] = 0x003e, 346 [EEPROM_TSSI_BOUND_BG1] = 0x0045, 347 [EEPROM_TSSI_BOUND_BG2] = 0x0046, 348 [EEPROM_TSSI_BOUND_BG3] = 0x0047, 349 [EEPROM_TSSI_BOUND_BG4] = 0x0048, 350 [EEPROM_TSSI_BOUND_BG5] = 0x0049, 351 [EEPROM_TXPOWER_A1] = 0x004b, 352 [EEPROM_TXPOWER_A2] = 0x0065, 353 [EEPROM_EXT_TXPOWER_A3] = 0x007f, 354 [EEPROM_TSSI_BOUND_A1] = 0x009a, 355 [EEPROM_TSSI_BOUND_A2] = 0x009b, 356 [EEPROM_TSSI_BOUND_A3] = 0x009c, 357 [EEPROM_TSSI_BOUND_A4] = 0x009d, 358 [EEPROM_TSSI_BOUND_A5] = 0x009e, 359 [EEPROM_TXPOWER_BYRATE] = 0x00a0, 360 }; 361 362 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev, 363 const enum rt2800_eeprom_word word) 364 { 365 const unsigned int *map; 366 unsigned int index; 367 368 if (WARN_ONCE(word >= EEPROM_WORD_COUNT, 369 "%s: invalid EEPROM word %d\n", 370 wiphy_name(rt2x00dev->hw->wiphy), word)) 371 return 0; 372 373 if (rt2x00_rt(rt2x00dev, RT3593) || 374 rt2x00_rt(rt2x00dev, RT3883)) 375 map = rt2800_eeprom_map_ext; 376 else 377 map = rt2800_eeprom_map; 378 379 index = map[word]; 380 381 /* Index 0 is valid only for EEPROM_CHIP_ID. 382 * Otherwise it means that the offset of the 383 * given word is not initialized in the map, 384 * or that the field is not usable on the 385 * actual chipset. 386 */ 387 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0, 388 "%s: invalid access of EEPROM word %d\n", 389 wiphy_name(rt2x00dev->hw->wiphy), word); 390 391 return index; 392 } 393 394 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev, 395 const enum rt2800_eeprom_word word) 396 { 397 unsigned int index; 398 399 index = rt2800_eeprom_word_index(rt2x00dev, word); 400 return rt2x00_eeprom_addr(rt2x00dev, index); 401 } 402 403 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, 404 const enum rt2800_eeprom_word word) 405 { 406 unsigned int index; 407 408 index = rt2800_eeprom_word_index(rt2x00dev, word); 409 return rt2x00_eeprom_read(rt2x00dev, index); 410 } 411 412 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, 413 const enum rt2800_eeprom_word word, u16 data) 414 { 415 unsigned int index; 416 417 index = rt2800_eeprom_word_index(rt2x00dev, word); 418 rt2x00_eeprom_write(rt2x00dev, index, data); 419 } 420 421 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, 422 const enum rt2800_eeprom_word array, 423 unsigned int offset) 424 { 425 unsigned int index; 426 427 index = rt2800_eeprom_word_index(rt2x00dev, array); 428 return rt2x00_eeprom_read(rt2x00dev, index + offset); 429 } 430 431 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) 432 { 433 u32 reg; 434 int i, count; 435 436 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 437 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); 438 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); 439 rt2x00_set_field32(®, WLAN_CLK_EN, 0); 440 rt2x00_set_field32(®, WLAN_EN, 1); 441 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 442 443 udelay(REGISTER_BUSY_DELAY); 444 445 count = 0; 446 do { 447 /* 448 * Check PLL_LD & XTAL_RDY. 449 */ 450 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 451 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 452 if (rt2x00_get_field32(reg, PLL_LD) && 453 rt2x00_get_field32(reg, XTAL_RDY)) 454 break; 455 udelay(REGISTER_BUSY_DELAY); 456 } 457 458 if (i >= REGISTER_BUSY_COUNT) { 459 460 if (count >= 10) 461 return -EIO; 462 463 rt2800_register_write(rt2x00dev, 0x58, 0x018); 464 udelay(REGISTER_BUSY_DELAY); 465 rt2800_register_write(rt2x00dev, 0x58, 0x418); 466 udelay(REGISTER_BUSY_DELAY); 467 rt2800_register_write(rt2x00dev, 0x58, 0x618); 468 udelay(REGISTER_BUSY_DELAY); 469 count++; 470 } else { 471 count = 0; 472 } 473 474 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 475 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); 476 rt2x00_set_field32(®, WLAN_CLK_EN, 1); 477 rt2x00_set_field32(®, WLAN_RESET, 1); 478 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 479 udelay(10); 480 rt2x00_set_field32(®, WLAN_RESET, 0); 481 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 482 udelay(10); 483 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff); 484 } while (count != 0); 485 486 return 0; 487 } 488 489 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 490 const u8 command, const u8 token, 491 const u8 arg0, const u8 arg1) 492 { 493 u32 reg; 494 495 /* 496 * SOC devices don't support MCU requests. 497 */ 498 if (rt2x00_is_soc(rt2x00dev)) 499 return; 500 501 mutex_lock(&rt2x00dev->csr_mutex); 502 503 /* 504 * Wait until the MCU becomes available, afterwards we 505 * can safely write the new data into the register. 506 */ 507 if (WAIT_FOR_MCU(rt2x00dev, ®)) { 508 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); 509 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); 510 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); 511 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); 512 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); 513 514 reg = 0; 515 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); 516 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); 517 } 518 519 mutex_unlock(&rt2x00dev->csr_mutex); 520 } 521 EXPORT_SYMBOL_GPL(rt2800_mcu_request); 522 523 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) 524 { 525 unsigned int i = 0; 526 u32 reg; 527 528 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 529 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 530 if (reg && reg != ~0) 531 return 0; 532 msleep(1); 533 } 534 535 rt2x00_err(rt2x00dev, "Unstable hardware\n"); 536 return -EBUSY; 537 } 538 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); 539 540 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 541 { 542 unsigned int i; 543 u32 reg; 544 545 /* 546 * Some devices are really slow to respond here. Wait a whole second 547 * before timing out. 548 */ 549 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 550 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 551 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 552 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 553 return 0; 554 555 msleep(10); 556 } 557 558 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); 559 return -EACCES; 560 } 561 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); 562 563 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) 564 { 565 u32 reg; 566 567 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 568 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 569 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 570 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 571 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 572 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 573 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 574 } 575 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma); 576 577 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev, 578 unsigned short *txwi_size, 579 unsigned short *rxwi_size) 580 { 581 switch (rt2x00dev->chip.rt) { 582 case RT3593: 583 case RT3883: 584 *txwi_size = TXWI_DESC_SIZE_4WORDS; 585 *rxwi_size = RXWI_DESC_SIZE_5WORDS; 586 break; 587 588 case RT5592: 589 case RT6352: 590 *txwi_size = TXWI_DESC_SIZE_5WORDS; 591 *rxwi_size = RXWI_DESC_SIZE_6WORDS; 592 break; 593 594 default: 595 *txwi_size = TXWI_DESC_SIZE_4WORDS; 596 *rxwi_size = RXWI_DESC_SIZE_4WORDS; 597 break; 598 } 599 } 600 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size); 601 602 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) 603 { 604 u16 fw_crc; 605 u16 crc; 606 607 /* 608 * The last 2 bytes in the firmware array are the crc checksum itself, 609 * this means that we should never pass those 2 bytes to the crc 610 * algorithm. 611 */ 612 fw_crc = (data[len - 2] << 8 | data[len - 1]); 613 614 /* 615 * Use the crc ccitt algorithm. 616 * This will return the same value as the legacy driver which 617 * used bit ordering reversion on the both the firmware bytes 618 * before input input as well as on the final output. 619 * Obviously using crc ccitt directly is much more efficient. 620 */ 621 crc = crc_ccitt(~0, data, len - 2); 622 623 /* 624 * There is a small difference between the crc-itu-t + bitrev and 625 * the crc-ccitt crc calculation. In the latter method the 2 bytes 626 * will be swapped, use swab16 to convert the crc to the correct 627 * value. 628 */ 629 crc = swab16(crc); 630 631 return fw_crc == crc; 632 } 633 634 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, 635 const u8 *data, const size_t len) 636 { 637 size_t offset = 0; 638 size_t fw_len; 639 bool multiple; 640 641 /* 642 * PCI(e) & SOC devices require firmware with a length 643 * of 8kb. USB devices require firmware files with a length 644 * of 4kb. Certain USB chipsets however require different firmware, 645 * which Ralink only provides attached to the original firmware 646 * file. Thus for USB devices, firmware files have a length 647 * which is a multiple of 4kb. The firmware for rt3290 chip also 648 * have a length which is a multiple of 4kb. 649 */ 650 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290)) 651 fw_len = 4096; 652 else 653 fw_len = 8192; 654 655 multiple = true; 656 /* 657 * Validate the firmware length 658 */ 659 if (len != fw_len && (!multiple || (len % fw_len) != 0)) 660 return FW_BAD_LENGTH; 661 662 /* 663 * Check if the chipset requires one of the upper parts 664 * of the firmware. 665 */ 666 if (rt2x00_is_usb(rt2x00dev) && 667 !rt2x00_rt(rt2x00dev, RT2860) && 668 !rt2x00_rt(rt2x00dev, RT2872) && 669 !rt2x00_rt(rt2x00dev, RT3070) && 670 ((len / fw_len) == 1)) 671 return FW_BAD_VERSION; 672 673 /* 674 * 8kb firmware files must be checked as if it were 675 * 2 separate firmware files. 676 */ 677 while (offset < len) { 678 if (!rt2800_check_firmware_crc(data + offset, fw_len)) 679 return FW_BAD_CRC; 680 681 offset += fw_len; 682 } 683 684 return FW_OK; 685 } 686 EXPORT_SYMBOL_GPL(rt2800_check_firmware); 687 688 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, 689 const u8 *data, const size_t len) 690 { 691 unsigned int i; 692 u32 reg; 693 int retval; 694 695 if (rt2x00_rt(rt2x00dev, RT3290)) { 696 retval = rt2800_enable_wlan_rt3290(rt2x00dev); 697 if (retval) 698 return -EBUSY; 699 } 700 701 /* 702 * If driver doesn't wake up firmware here, 703 * rt2800_load_firmware will hang forever when interface is up again. 704 */ 705 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 706 707 /* 708 * Wait for stable hardware. 709 */ 710 if (rt2800_wait_csr_ready(rt2x00dev)) 711 return -EBUSY; 712 713 if (rt2x00_is_pci(rt2x00dev)) { 714 if (rt2x00_rt(rt2x00dev, RT3290) || 715 rt2x00_rt(rt2x00dev, RT3572) || 716 rt2x00_rt(rt2x00dev, RT5390) || 717 rt2x00_rt(rt2x00dev, RT5392)) { 718 reg = rt2800_register_read(rt2x00dev, AUX_CTRL); 719 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); 720 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); 721 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); 722 } 723 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 724 } 725 726 rt2800_disable_wpdma(rt2x00dev); 727 728 /* 729 * Write firmware to the device. 730 */ 731 rt2800_drv_write_firmware(rt2x00dev, data, len); 732 733 /* 734 * Wait for device to stabilize. 735 */ 736 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 737 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL); 738 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 739 break; 740 msleep(1); 741 } 742 743 if (i == REGISTER_BUSY_COUNT) { 744 rt2x00_err(rt2x00dev, "PBF system register not ready\n"); 745 return -EBUSY; 746 } 747 748 /* 749 * Disable DMA, will be reenabled later when enabling 750 * the radio. 751 */ 752 rt2800_disable_wpdma(rt2x00dev); 753 754 /* 755 * Initialize firmware. 756 */ 757 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 758 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 759 if (rt2x00_is_usb(rt2x00dev)) { 760 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 761 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 762 } 763 msleep(1); 764 765 return 0; 766 } 767 EXPORT_SYMBOL_GPL(rt2800_load_firmware); 768 769 void rt2800_write_tx_data(struct queue_entry *entry, 770 struct txentry_desc *txdesc) 771 { 772 __le32 *txwi = rt2800_drv_get_txwi(entry); 773 u32 word; 774 int i; 775 776 /* 777 * Initialize TX Info descriptor 778 */ 779 word = rt2x00_desc_read(txwi, 0); 780 rt2x00_set_field32(&word, TXWI_W0_FRAG, 781 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 782 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 783 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); 784 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); 785 rt2x00_set_field32(&word, TXWI_W0_TS, 786 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 787 rt2x00_set_field32(&word, TXWI_W0_AMPDU, 788 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); 789 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, 790 txdesc->u.ht.mpdu_density); 791 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); 792 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); 793 rt2x00_set_field32(&word, TXWI_W0_BW, 794 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); 795 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, 796 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); 797 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); 798 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); 799 rt2x00_desc_write(txwi, 0, word); 800 801 word = rt2x00_desc_read(txwi, 1); 802 rt2x00_set_field32(&word, TXWI_W1_ACK, 803 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 804 rt2x00_set_field32(&word, TXWI_W1_NSEQ, 805 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 806 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); 807 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 808 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 809 txdesc->key_idx : txdesc->u.ht.wcid); 810 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 811 txdesc->length); 812 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); 813 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); 814 rt2x00_desc_write(txwi, 1, word); 815 816 /* 817 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert 818 * the IV from the IVEIV register when TXD_W3_WIV is set to 0. 819 * When TXD_W3_WIV is set to 1 it will use the IV data 820 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 821 * crypto entry in the registers should be used to encrypt the frame. 822 * 823 * Nulify all remaining words as well, we don't know how to program them. 824 */ 825 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++) 826 _rt2x00_desc_write(txwi, i, 0); 827 } 828 EXPORT_SYMBOL_GPL(rt2800_write_tx_data); 829 830 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) 831 { 832 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); 833 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); 834 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); 835 u16 eeprom; 836 u8 offset0; 837 u8 offset1; 838 u8 offset2; 839 840 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 841 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 842 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); 843 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); 844 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 845 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); 846 } else { 847 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 848 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); 849 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); 850 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 851 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); 852 } 853 854 /* 855 * Convert the value from the descriptor into the RSSI value 856 * If the value in the descriptor is 0, it is considered invalid 857 * and the default (extremely low) rssi value is assumed 858 */ 859 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128; 860 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128; 861 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128; 862 863 /* 864 * mac80211 only accepts a single RSSI value. Calculating the 865 * average doesn't deliver a fair answer either since -60:-60 would 866 * be considered equally good as -50:-70 while the second is the one 867 * which gives less energy... 868 */ 869 rssi0 = max(rssi0, rssi1); 870 return (int)max(rssi0, rssi2); 871 } 872 873 void rt2800_process_rxwi(struct queue_entry *entry, 874 struct rxdone_entry_desc *rxdesc) 875 { 876 __le32 *rxwi = (__le32 *) entry->skb->data; 877 u32 word; 878 879 word = rt2x00_desc_read(rxwi, 0); 880 881 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); 882 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); 883 884 word = rt2x00_desc_read(rxwi, 1); 885 886 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) 887 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI; 888 889 if (rt2x00_get_field32(word, RXWI_W1_BW)) 890 rxdesc->bw = RATE_INFO_BW_40; 891 892 /* 893 * Detect RX rate, always use MCS as signal type. 894 */ 895 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; 896 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); 897 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); 898 899 /* 900 * Mask of 0x8 bit to remove the short preamble flag. 901 */ 902 if (rxdesc->rate_mode == RATE_MODE_CCK) 903 rxdesc->signal &= ~0x8; 904 905 word = rt2x00_desc_read(rxwi, 2); 906 907 /* 908 * Convert descriptor AGC value to RSSI value. 909 */ 910 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); 911 /* 912 * Remove RXWI descriptor from start of the buffer. 913 */ 914 skb_pull(entry->skb, entry->queue->winfo_size); 915 } 916 EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 917 918 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc, 919 u32 status, enum nl80211_band band) 920 { 921 u8 flags = 0; 922 u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 923 924 switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) { 925 case RATE_MODE_HT_GREENFIELD: 926 flags |= IEEE80211_TX_RC_GREEN_FIELD; 927 /* fall through */ 928 case RATE_MODE_HT_MIX: 929 flags |= IEEE80211_TX_RC_MCS; 930 break; 931 case RATE_MODE_OFDM: 932 if (band == NL80211_BAND_2GHZ) 933 idx += 4; 934 break; 935 case RATE_MODE_CCK: 936 if (idx >= 8) 937 idx -= 8; 938 break; 939 } 940 941 if (rt2x00_get_field32(status, TX_STA_FIFO_BW)) 942 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 943 944 if (rt2x00_get_field32(status, TX_STA_FIFO_SGI)) 945 flags |= IEEE80211_TX_RC_SHORT_GI; 946 947 skbdesc->tx_rate_idx = idx; 948 skbdesc->tx_rate_flags = flags; 949 } 950 951 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg) 952 { 953 __le32 *txwi; 954 u32 word; 955 int wcid, ack, pid; 956 int tx_wcid, tx_ack, tx_pid, is_agg; 957 958 /* 959 * This frames has returned with an IO error, 960 * so the status report is not intended for this 961 * frame. 962 */ 963 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) 964 return false; 965 966 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID); 967 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED); 968 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE); 969 is_agg = rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE); 970 971 /* 972 * Validate if this TX status report is intended for 973 * this entry by comparing the WCID/ACK/PID fields. 974 */ 975 txwi = rt2800_drv_get_txwi(entry); 976 977 word = rt2x00_desc_read(txwi, 1); 978 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID); 979 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK); 980 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID); 981 982 if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) { 983 rt2x00_dbg(entry->queue->rt2x00dev, 984 "TX status report missed for queue %d entry %d\n", 985 entry->queue->qid, entry->entry_idx); 986 return false; 987 } 988 989 return true; 990 } 991 992 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi, 993 bool match) 994 { 995 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 996 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 997 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 998 struct txdone_entry_desc txdesc; 999 u32 word; 1000 u16 mcs, real_mcs; 1001 int aggr, ampdu, wcid, ack_req; 1002 1003 /* 1004 * Obtain the status about this packet. 1005 */ 1006 txdesc.flags = 0; 1007 word = rt2x00_desc_read(txwi, 0); 1008 1009 mcs = rt2x00_get_field32(word, TXWI_W0_MCS); 1010 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); 1011 1012 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 1013 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); 1014 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID); 1015 ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED); 1016 1017 /* 1018 * If a frame was meant to be sent as a single non-aggregated MPDU 1019 * but ended up in an aggregate the used tx rate doesn't correlate 1020 * with the one specified in the TXWI as the whole aggregate is sent 1021 * with the same rate. 1022 * 1023 * For example: two frames are sent to rt2x00, the first one sets 1024 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 1025 * and requests MCS15. If the hw aggregates both frames into one 1026 * AMDPU the tx status for both frames will contain MCS7 although 1027 * the frame was sent successfully. 1028 * 1029 * Hence, replace the requested rate with the real tx rate to not 1030 * confuse the rate control algortihm by providing clearly wrong 1031 * data. 1032 * 1033 * FIXME: if we do not find matching entry, we tell that frame was 1034 * posted without any retries. We need to find a way to fix that 1035 * and provide retry count. 1036 */ 1037 if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) { 1038 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band); 1039 mcs = real_mcs; 1040 } 1041 1042 if (aggr == 1 || ampdu == 1) 1043 __set_bit(TXDONE_AMPDU, &txdesc.flags); 1044 1045 if (!ack_req) 1046 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags); 1047 1048 /* 1049 * Ralink has a retry mechanism using a global fallback 1050 * table. We setup this fallback table to try the immediate 1051 * lower rate for all rates. In the TX_STA_FIFO, the MCS field 1052 * always contains the MCS used for the last transmission, be 1053 * it successful or not. 1054 */ 1055 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { 1056 /* 1057 * Transmission succeeded. The number of retries is 1058 * mcs - real_mcs 1059 */ 1060 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 1061 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); 1062 } else { 1063 /* 1064 * Transmission failed. The number of retries is 1065 * always 7 in this case (for a total number of 8 1066 * frames sent). 1067 */ 1068 __set_bit(TXDONE_FAILURE, &txdesc.flags); 1069 txdesc.retry = rt2x00dev->long_retry; 1070 } 1071 1072 /* 1073 * the frame was retried at least once 1074 * -> hw used fallback rates 1075 */ 1076 if (txdesc.retry) 1077 __set_bit(TXDONE_FALLBACK, &txdesc.flags); 1078 1079 if (!match) { 1080 /* RCU assures non-null sta will not be freed by mac80211. */ 1081 rcu_read_lock(); 1082 if (likely(wcid >= WCID_START && wcid <= WCID_END)) 1083 skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START]; 1084 else 1085 skbdesc->sta = NULL; 1086 rt2x00lib_txdone_nomatch(entry, &txdesc); 1087 rcu_read_unlock(); 1088 } else { 1089 rt2x00lib_txdone(entry, &txdesc); 1090 } 1091 } 1092 EXPORT_SYMBOL_GPL(rt2800_txdone_entry); 1093 1094 void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota) 1095 { 1096 struct data_queue *queue; 1097 struct queue_entry *entry; 1098 u32 reg; 1099 u8 qid; 1100 bool match; 1101 1102 while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, ®)) { 1103 /* 1104 * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is 1105 * guaranteed to be one of the TX QIDs . 1106 */ 1107 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE); 1108 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid); 1109 1110 if (unlikely(rt2x00queue_empty(queue))) { 1111 rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n", 1112 qid); 1113 break; 1114 } 1115 1116 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1117 1118 if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1119 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) { 1120 rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n", 1121 entry->entry_idx, qid); 1122 break; 1123 } 1124 1125 match = rt2800_txdone_entry_check(entry, reg); 1126 rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match); 1127 } 1128 } 1129 EXPORT_SYMBOL_GPL(rt2800_txdone); 1130 1131 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev, 1132 struct queue_entry *entry) 1133 { 1134 bool ret; 1135 unsigned long tout; 1136 1137 if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1138 return false; 1139 1140 if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags)) 1141 tout = msecs_to_jiffies(50); 1142 else 1143 tout = msecs_to_jiffies(2000); 1144 1145 ret = time_after(jiffies, entry->last_action + tout); 1146 if (unlikely(ret)) 1147 rt2x00_dbg(entry->queue->rt2x00dev, 1148 "TX status timeout for entry %d in queue %d\n", 1149 entry->entry_idx, entry->queue->qid); 1150 return ret; 1151 } 1152 1153 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev) 1154 { 1155 struct data_queue *queue; 1156 struct queue_entry *entry; 1157 1158 tx_queue_for_each(rt2x00dev, queue) { 1159 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1160 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1161 return true; 1162 } 1163 1164 return false; 1165 } 1166 EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout); 1167 1168 /* 1169 * test if there is an entry in any TX queue for which DMA is done 1170 * but the TX status has not been returned yet 1171 */ 1172 bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev) 1173 { 1174 struct data_queue *queue; 1175 1176 tx_queue_for_each(rt2x00dev, queue) { 1177 if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) != 1178 rt2x00queue_get_entry(queue, Q_INDEX_DONE)) 1179 return true; 1180 } 1181 return false; 1182 } 1183 EXPORT_SYMBOL_GPL(rt2800_txstatus_pending); 1184 1185 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev) 1186 { 1187 struct data_queue *queue; 1188 struct queue_entry *entry; 1189 1190 /* 1191 * Process any trailing TX status reports for IO failures, 1192 * we loop until we find the first non-IO error entry. This 1193 * can either be a frame which is free, is being uploaded, 1194 * or has completed the upload but didn't have an entry 1195 * in the TX_STAT_FIFO register yet. 1196 */ 1197 tx_queue_for_each(rt2x00dev, queue) { 1198 while (!rt2x00queue_empty(queue)) { 1199 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1200 1201 if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1202 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1203 break; 1204 1205 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) || 1206 rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1207 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE); 1208 else 1209 break; 1210 } 1211 } 1212 } 1213 EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus); 1214 1215 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev, 1216 unsigned int index) 1217 { 1218 return HW_BEACON_BASE(index); 1219 } 1220 1221 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev, 1222 unsigned int index) 1223 { 1224 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index)); 1225 } 1226 1227 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev) 1228 { 1229 struct data_queue *queue = rt2x00dev->bcn; 1230 struct queue_entry *entry; 1231 int i, bcn_num = 0; 1232 u64 off, reg = 0; 1233 u32 bssid_dw1; 1234 1235 /* 1236 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers. 1237 */ 1238 for (i = 0; i < queue->limit; i++) { 1239 entry = &queue->entries[i]; 1240 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags)) 1241 continue; 1242 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx); 1243 reg |= off << (8 * bcn_num); 1244 bcn_num++; 1245 } 1246 1247 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); 1248 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); 1249 1250 /* 1251 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons. 1252 */ 1253 bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1); 1254 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, 1255 bcn_num > 0 ? bcn_num - 1 : 0); 1256 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1); 1257 } 1258 1259 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) 1260 { 1261 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1262 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1263 unsigned int beacon_base; 1264 unsigned int padding_len; 1265 u32 orig_reg, reg; 1266 const int txwi_desc_size = entry->queue->winfo_size; 1267 1268 /* 1269 * Disable beaconing while we are reloading the beacon data, 1270 * otherwise we might be sending out invalid data. 1271 */ 1272 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1273 orig_reg = reg; 1274 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1275 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1276 1277 /* 1278 * Add space for the TXWI in front of the skb. 1279 */ 1280 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size); 1281 1282 /* 1283 * Register descriptor details in skb frame descriptor. 1284 */ 1285 skbdesc->flags |= SKBDESC_DESC_IN_SKB; 1286 skbdesc->desc = entry->skb->data; 1287 skbdesc->desc_len = txwi_desc_size; 1288 1289 /* 1290 * Add the TXWI for the beacon to the skb. 1291 */ 1292 rt2800_write_tx_data(entry, txdesc); 1293 1294 /* 1295 * Dump beacon to userspace through debugfs. 1296 */ 1297 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); 1298 1299 /* 1300 * Write entire beacon with TXWI and padding to register. 1301 */ 1302 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 1303 if (padding_len && skb_pad(entry->skb, padding_len)) { 1304 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); 1305 /* skb freed by skb_pad() on failure */ 1306 entry->skb = NULL; 1307 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1308 return; 1309 } 1310 1311 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx); 1312 1313 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, 1314 entry->skb->len + padding_len); 1315 __set_bit(ENTRY_BCN_ENABLED, &entry->flags); 1316 1317 /* 1318 * Change global beacons settings. 1319 */ 1320 rt2800_update_beacons_setup(rt2x00dev); 1321 1322 /* 1323 * Restore beaconing state. 1324 */ 1325 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1326 1327 /* 1328 * Clean up beacon skb. 1329 */ 1330 dev_kfree_skb_any(entry->skb); 1331 entry->skb = NULL; 1332 } 1333 EXPORT_SYMBOL_GPL(rt2800_write_beacon); 1334 1335 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, 1336 unsigned int index) 1337 { 1338 int i; 1339 const int txwi_desc_size = rt2x00dev->bcn->winfo_size; 1340 unsigned int beacon_base; 1341 1342 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index); 1343 1344 /* 1345 * For the Beacon base registers we only need to clear 1346 * the whole TXWI which (when set to 0) will invalidate 1347 * the entire beacon. 1348 */ 1349 for (i = 0; i < txwi_desc_size; i += sizeof(__le32)) 1350 rt2800_register_write(rt2x00dev, beacon_base + i, 0); 1351 } 1352 1353 void rt2800_clear_beacon(struct queue_entry *entry) 1354 { 1355 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1356 u32 orig_reg, reg; 1357 1358 /* 1359 * Disable beaconing while we are reloading the beacon data, 1360 * otherwise we might be sending out invalid data. 1361 */ 1362 orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1363 reg = orig_reg; 1364 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1365 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1366 1367 /* 1368 * Clear beacon. 1369 */ 1370 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx); 1371 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags); 1372 1373 /* 1374 * Change global beacons settings. 1375 */ 1376 rt2800_update_beacons_setup(rt2x00dev); 1377 /* 1378 * Restore beaconing state. 1379 */ 1380 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1381 } 1382 EXPORT_SYMBOL_GPL(rt2800_clear_beacon); 1383 1384 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 1385 const struct rt2x00debug rt2800_rt2x00debug = { 1386 .owner = THIS_MODULE, 1387 .csr = { 1388 .read = rt2800_register_read, 1389 .write = rt2800_register_write, 1390 .flags = RT2X00DEBUGFS_OFFSET, 1391 .word_base = CSR_REG_BASE, 1392 .word_size = sizeof(u32), 1393 .word_count = CSR_REG_SIZE / sizeof(u32), 1394 }, 1395 .eeprom = { 1396 /* NOTE: The local EEPROM access functions can't 1397 * be used here, use the generic versions instead. 1398 */ 1399 .read = rt2x00_eeprom_read, 1400 .write = rt2x00_eeprom_write, 1401 .word_base = EEPROM_BASE, 1402 .word_size = sizeof(u16), 1403 .word_count = EEPROM_SIZE / sizeof(u16), 1404 }, 1405 .bbp = { 1406 .read = rt2800_bbp_read, 1407 .write = rt2800_bbp_write, 1408 .word_base = BBP_BASE, 1409 .word_size = sizeof(u8), 1410 .word_count = BBP_SIZE / sizeof(u8), 1411 }, 1412 .rf = { 1413 .read = rt2x00_rf_read, 1414 .write = rt2800_rf_write, 1415 .word_base = RF_BASE, 1416 .word_size = sizeof(u32), 1417 .word_count = RF_SIZE / sizeof(u32), 1418 }, 1419 .rfcsr = { 1420 .read = rt2800_rfcsr_read, 1421 .write = rt2800_rfcsr_write, 1422 .word_base = RFCSR_BASE, 1423 .word_size = sizeof(u8), 1424 .word_count = RFCSR_SIZE / sizeof(u8), 1425 }, 1426 }; 1427 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); 1428 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1429 1430 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) 1431 { 1432 u32 reg; 1433 1434 if (rt2x00_rt(rt2x00dev, RT3290)) { 1435 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 1436 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); 1437 } else { 1438 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 1439 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); 1440 } 1441 } 1442 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 1443 1444 #ifdef CONFIG_RT2X00_LIB_LEDS 1445 static void rt2800_brightness_set(struct led_classdev *led_cdev, 1446 enum led_brightness brightness) 1447 { 1448 struct rt2x00_led *led = 1449 container_of(led_cdev, struct rt2x00_led, led_dev); 1450 unsigned int enabled = brightness != LED_OFF; 1451 unsigned int bg_mode = 1452 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); 1453 unsigned int polarity = 1454 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1455 EEPROM_FREQ_LED_POLARITY); 1456 unsigned int ledmode = 1457 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1458 EEPROM_FREQ_LED_MODE); 1459 u32 reg; 1460 1461 /* Check for SoC (SOC devices don't support MCU requests) */ 1462 if (rt2x00_is_soc(led->rt2x00dev)) { 1463 reg = rt2800_register_read(led->rt2x00dev, LED_CFG); 1464 1465 /* Set LED Polarity */ 1466 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); 1467 1468 /* Set LED Mode */ 1469 if (led->type == LED_TYPE_RADIO) { 1470 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 1471 enabled ? 3 : 0); 1472 } else if (led->type == LED_TYPE_ASSOC) { 1473 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 1474 enabled ? 3 : 0); 1475 } else if (led->type == LED_TYPE_QUALITY) { 1476 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 1477 enabled ? 3 : 0); 1478 } 1479 1480 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 1481 1482 } else { 1483 if (led->type == LED_TYPE_RADIO) { 1484 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1485 enabled ? 0x20 : 0); 1486 } else if (led->type == LED_TYPE_ASSOC) { 1487 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1488 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); 1489 } else if (led->type == LED_TYPE_QUALITY) { 1490 /* 1491 * The brightness is divided into 6 levels (0 - 5), 1492 * The specs tell us the following levels: 1493 * 0, 1 ,3, 7, 15, 31 1494 * to determine the level in a simple way we can simply 1495 * work with bitshifting: 1496 * (1 << level) - 1 1497 */ 1498 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 1499 (1 << brightness / (LED_FULL / 6)) - 1, 1500 polarity); 1501 } 1502 } 1503 } 1504 1505 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, 1506 struct rt2x00_led *led, enum led_type type) 1507 { 1508 led->rt2x00dev = rt2x00dev; 1509 led->type = type; 1510 led->led_dev.brightness_set = rt2800_brightness_set; 1511 led->flags = LED_INITIALIZED; 1512 } 1513 #endif /* CONFIG_RT2X00_LIB_LEDS */ 1514 1515 /* 1516 * Configuration handlers. 1517 */ 1518 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, 1519 const u8 *address, 1520 int wcid) 1521 { 1522 struct mac_wcid_entry wcid_entry; 1523 u32 offset; 1524 1525 offset = MAC_WCID_ENTRY(wcid); 1526 1527 memset(&wcid_entry, 0xff, sizeof(wcid_entry)); 1528 if (address) 1529 memcpy(wcid_entry.mac, address, ETH_ALEN); 1530 1531 rt2800_register_multiwrite(rt2x00dev, offset, 1532 &wcid_entry, sizeof(wcid_entry)); 1533 } 1534 1535 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) 1536 { 1537 u32 offset; 1538 offset = MAC_WCID_ATTR_ENTRY(wcid); 1539 rt2800_register_write(rt2x00dev, offset, 0); 1540 } 1541 1542 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, 1543 int wcid, u32 bssidx) 1544 { 1545 u32 offset = MAC_WCID_ATTR_ENTRY(wcid); 1546 u32 reg; 1547 1548 /* 1549 * The BSS Idx numbers is split in a main value of 3 bits, 1550 * and a extended field for adding one additional bit to the value. 1551 */ 1552 reg = rt2800_register_read(rt2x00dev, offset); 1553 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); 1554 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, 1555 (bssidx & 0x8) >> 3); 1556 rt2800_register_write(rt2x00dev, offset, reg); 1557 } 1558 1559 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, 1560 struct rt2x00lib_crypto *crypto, 1561 struct ieee80211_key_conf *key) 1562 { 1563 struct mac_iveiv_entry iveiv_entry; 1564 u32 offset; 1565 u32 reg; 1566 1567 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); 1568 1569 if (crypto->cmd == SET_KEY) { 1570 reg = rt2800_register_read(rt2x00dev, offset); 1571 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 1572 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 1573 /* 1574 * Both the cipher as the BSS Idx numbers are split in a main 1575 * value of 3 bits, and a extended field for adding one additional 1576 * bit to the value. 1577 */ 1578 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 1579 (crypto->cipher & 0x7)); 1580 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 1581 (crypto->cipher & 0x8) >> 3); 1582 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); 1583 rt2800_register_write(rt2x00dev, offset, reg); 1584 } else { 1585 /* Delete the cipher without touching the bssidx */ 1586 reg = rt2800_register_read(rt2x00dev, offset); 1587 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); 1588 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); 1589 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); 1590 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); 1591 rt2800_register_write(rt2x00dev, offset, reg); 1592 } 1593 1594 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 1595 1596 memset(&iveiv_entry, 0, sizeof(iveiv_entry)); 1597 if ((crypto->cipher == CIPHER_TKIP) || 1598 (crypto->cipher == CIPHER_TKIP_NO_MIC) || 1599 (crypto->cipher == CIPHER_AES)) 1600 iveiv_entry.iv[3] |= 0x20; 1601 iveiv_entry.iv[3] |= key->keyidx << 6; 1602 rt2800_register_multiwrite(rt2x00dev, offset, 1603 &iveiv_entry, sizeof(iveiv_entry)); 1604 } 1605 1606 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, 1607 struct rt2x00lib_crypto *crypto, 1608 struct ieee80211_key_conf *key) 1609 { 1610 struct hw_key_entry key_entry; 1611 struct rt2x00_field32 field; 1612 u32 offset; 1613 u32 reg; 1614 1615 if (crypto->cmd == SET_KEY) { 1616 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; 1617 1618 memcpy(key_entry.key, crypto->key, 1619 sizeof(key_entry.key)); 1620 memcpy(key_entry.tx_mic, crypto->tx_mic, 1621 sizeof(key_entry.tx_mic)); 1622 memcpy(key_entry.rx_mic, crypto->rx_mic, 1623 sizeof(key_entry.rx_mic)); 1624 1625 offset = SHARED_KEY_ENTRY(key->hw_key_idx); 1626 rt2800_register_multiwrite(rt2x00dev, offset, 1627 &key_entry, sizeof(key_entry)); 1628 } 1629 1630 /* 1631 * The cipher types are stored over multiple registers 1632 * starting with SHARED_KEY_MODE_BASE each word will have 1633 * 32 bits and contains the cipher types for 2 bssidx each. 1634 * Using the correct defines correctly will cause overhead, 1635 * so just calculate the correct offset. 1636 */ 1637 field.bit_offset = 4 * (key->hw_key_idx % 8); 1638 field.bit_mask = 0x7 << field.bit_offset; 1639 1640 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); 1641 1642 reg = rt2800_register_read(rt2x00dev, offset); 1643 rt2x00_set_field32(®, field, 1644 (crypto->cmd == SET_KEY) * crypto->cipher); 1645 rt2800_register_write(rt2x00dev, offset, reg); 1646 1647 /* 1648 * Update WCID information 1649 */ 1650 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); 1651 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, 1652 crypto->bssidx); 1653 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1654 1655 return 0; 1656 } 1657 EXPORT_SYMBOL_GPL(rt2800_config_shared_key); 1658 1659 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 1660 struct rt2x00lib_crypto *crypto, 1661 struct ieee80211_key_conf *key) 1662 { 1663 struct hw_key_entry key_entry; 1664 u32 offset; 1665 1666 if (crypto->cmd == SET_KEY) { 1667 /* 1668 * Allow key configuration only for STAs that are 1669 * known by the hw. 1670 */ 1671 if (crypto->wcid > WCID_END) 1672 return -ENOSPC; 1673 key->hw_key_idx = crypto->wcid; 1674 1675 memcpy(key_entry.key, crypto->key, 1676 sizeof(key_entry.key)); 1677 memcpy(key_entry.tx_mic, crypto->tx_mic, 1678 sizeof(key_entry.tx_mic)); 1679 memcpy(key_entry.rx_mic, crypto->rx_mic, 1680 sizeof(key_entry.rx_mic)); 1681 1682 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 1683 rt2800_register_multiwrite(rt2x00dev, offset, 1684 &key_entry, sizeof(key_entry)); 1685 } 1686 1687 /* 1688 * Update WCID information 1689 */ 1690 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1691 1692 return 0; 1693 } 1694 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); 1695 1696 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev) 1697 { 1698 u8 i, max_psdu; 1699 u32 reg; 1700 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1701 1702 for (i = 0; i < 3; i++) 1703 if (drv_data->ampdu_factor_cnt[i] > 0) 1704 break; 1705 1706 max_psdu = min(drv_data->max_psdu, i); 1707 1708 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 1709 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); 1710 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1711 } 1712 1713 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1714 struct ieee80211_sta *sta) 1715 { 1716 struct rt2x00_dev *rt2x00dev = hw->priv; 1717 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1718 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1719 int wcid; 1720 1721 /* 1722 * Limit global maximum TX AMPDU length to smallest value of all 1723 * connected stations. In AP mode this can be suboptimal, but we 1724 * do not have a choice if some connected STA is not capable to 1725 * receive the same amount of data like the others. 1726 */ 1727 if (sta->ht_cap.ht_supported) { 1728 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++; 1729 rt2800_set_max_psdu_len(rt2x00dev); 1730 } 1731 1732 /* 1733 * Search for the first free WCID entry and return the corresponding 1734 * index. 1735 */ 1736 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START; 1737 1738 /* 1739 * Store selected wcid even if it is invalid so that we can 1740 * later decide if the STA is uploaded into the hw. 1741 */ 1742 sta_priv->wcid = wcid; 1743 1744 /* 1745 * No space left in the device, however, we can still communicate 1746 * with the STA -> No error. 1747 */ 1748 if (wcid > WCID_END) 1749 return 0; 1750 1751 __set_bit(wcid - WCID_START, drv_data->sta_ids); 1752 drv_data->wcid_to_sta[wcid - WCID_START] = sta; 1753 1754 /* 1755 * Clean up WCID attributes and write STA address to the device. 1756 */ 1757 rt2800_delete_wcid_attr(rt2x00dev, wcid); 1758 rt2800_config_wcid(rt2x00dev, sta->addr, wcid); 1759 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, 1760 rt2x00lib_get_bssidx(rt2x00dev, vif)); 1761 return 0; 1762 } 1763 EXPORT_SYMBOL_GPL(rt2800_sta_add); 1764 1765 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1766 struct ieee80211_sta *sta) 1767 { 1768 struct rt2x00_dev *rt2x00dev = hw->priv; 1769 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1770 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1771 int wcid = sta_priv->wcid; 1772 1773 if (sta->ht_cap.ht_supported) { 1774 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--; 1775 rt2800_set_max_psdu_len(rt2x00dev); 1776 } 1777 1778 if (wcid > WCID_END) 1779 return 0; 1780 /* 1781 * Remove WCID entry, no need to clean the attributes as they will 1782 * get renewed when the WCID is reused. 1783 */ 1784 rt2800_config_wcid(rt2x00dev, NULL, wcid); 1785 drv_data->wcid_to_sta[wcid - WCID_START] = NULL; 1786 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1787 1788 return 0; 1789 } 1790 EXPORT_SYMBOL_GPL(rt2800_sta_remove); 1791 1792 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, 1793 const unsigned int filter_flags) 1794 { 1795 u32 reg; 1796 1797 /* 1798 * Start configuration steps. 1799 * Note that the version error will always be dropped 1800 * and broadcast frames will always be accepted since 1801 * there is no filter for it at this time. 1802 */ 1803 reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG); 1804 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, 1805 !(filter_flags & FIF_FCSFAIL)); 1806 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, 1807 !(filter_flags & FIF_PLCPFAIL)); 1808 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, 1809 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); 1810 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); 1811 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); 1812 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, 1813 !(filter_flags & FIF_ALLMULTI)); 1814 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); 1815 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); 1816 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, 1817 !(filter_flags & FIF_CONTROL)); 1818 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, 1819 !(filter_flags & FIF_CONTROL)); 1820 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, 1821 !(filter_flags & FIF_CONTROL)); 1822 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, 1823 !(filter_flags & FIF_CONTROL)); 1824 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, 1825 !(filter_flags & FIF_CONTROL)); 1826 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, 1827 !(filter_flags & FIF_PSPOLL)); 1828 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); 1829 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 1830 !(filter_flags & FIF_CONTROL)); 1831 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, 1832 !(filter_flags & FIF_CONTROL)); 1833 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); 1834 } 1835 EXPORT_SYMBOL_GPL(rt2800_config_filter); 1836 1837 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, 1838 struct rt2x00intf_conf *conf, const unsigned int flags) 1839 { 1840 u32 reg; 1841 bool update_bssid = false; 1842 1843 if (flags & CONFIG_UPDATE_TYPE) { 1844 /* 1845 * Enable synchronisation. 1846 */ 1847 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1848 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); 1849 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1850 1851 if (conf->sync == TSF_SYNC_AP_NONE) { 1852 /* 1853 * Tune beacon queue transmit parameters for AP mode 1854 */ 1855 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1856 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); 1857 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); 1858 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1859 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); 1860 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1861 } else { 1862 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1863 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); 1864 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); 1865 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1866 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); 1867 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1868 } 1869 } 1870 1871 if (flags & CONFIG_UPDATE_MAC) { 1872 if (flags & CONFIG_UPDATE_TYPE && 1873 conf->sync == TSF_SYNC_AP_NONE) { 1874 /* 1875 * The BSSID register has to be set to our own mac 1876 * address in AP mode. 1877 */ 1878 memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); 1879 update_bssid = true; 1880 } 1881 1882 if (!is_zero_ether_addr((const u8 *)conf->mac)) { 1883 reg = le32_to_cpu(conf->mac[1]); 1884 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); 1885 conf->mac[1] = cpu_to_le32(reg); 1886 } 1887 1888 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, 1889 conf->mac, sizeof(conf->mac)); 1890 } 1891 1892 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { 1893 if (!is_zero_ether_addr((const u8 *)conf->bssid)) { 1894 reg = le32_to_cpu(conf->bssid[1]); 1895 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); 1896 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); 1897 conf->bssid[1] = cpu_to_le32(reg); 1898 } 1899 1900 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, 1901 conf->bssid, sizeof(conf->bssid)); 1902 } 1903 } 1904 EXPORT_SYMBOL_GPL(rt2800_config_intf); 1905 1906 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, 1907 struct rt2x00lib_erp *erp) 1908 { 1909 bool any_sta_nongf = !!(erp->ht_opmode & 1910 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 1911 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; 1912 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; 1913 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; 1914 u32 reg; 1915 1916 /* default protection rate for HT20: OFDM 24M */ 1917 mm20_rate = gf20_rate = 0x4004; 1918 1919 /* default protection rate for HT40: duplicate OFDM 24M */ 1920 mm40_rate = gf40_rate = 0x4084; 1921 1922 switch (protection) { 1923 case IEEE80211_HT_OP_MODE_PROTECTION_NONE: 1924 /* 1925 * All STAs in this BSS are HT20/40 but there might be 1926 * STAs not supporting greenfield mode. 1927 * => Disable protection for HT transmissions. 1928 */ 1929 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; 1930 1931 break; 1932 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 1933 /* 1934 * All STAs in this BSS are HT20 or HT20/40 but there 1935 * might be STAs not supporting greenfield mode. 1936 * => Protect all HT40 transmissions. 1937 */ 1938 mm20_mode = gf20_mode = 0; 1939 mm40_mode = gf40_mode = 1; 1940 1941 break; 1942 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 1943 /* 1944 * Nonmember protection: 1945 * According to 802.11n we _should_ protect all 1946 * HT transmissions (but we don't have to). 1947 * 1948 * But if cts_protection is enabled we _shall_ protect 1949 * all HT transmissions using a CCK rate. 1950 * 1951 * And if any station is non GF we _shall_ protect 1952 * GF transmissions. 1953 * 1954 * We decide to protect everything 1955 * -> fall through to mixed mode. 1956 */ 1957 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 1958 /* 1959 * Legacy STAs are present 1960 * => Protect all HT transmissions. 1961 */ 1962 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1; 1963 1964 /* 1965 * If erp protection is needed we have to protect HT 1966 * transmissions with CCK 11M long preamble. 1967 */ 1968 if (erp->cts_protection) { 1969 /* don't duplicate RTS/CTS in CCK mode */ 1970 mm20_rate = mm40_rate = 0x0003; 1971 gf20_rate = gf40_rate = 0x0003; 1972 } 1973 break; 1974 } 1975 1976 /* check for STAs not supporting greenfield mode */ 1977 if (any_sta_nongf) 1978 gf20_mode = gf40_mode = 1; 1979 1980 /* Update HT protection config */ 1981 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 1982 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); 1983 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); 1984 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 1985 1986 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 1987 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); 1988 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); 1989 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 1990 1991 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 1992 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); 1993 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); 1994 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 1995 1996 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 1997 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); 1998 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); 1999 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 2000 } 2001 2002 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, 2003 u32 changed) 2004 { 2005 u32 reg; 2006 2007 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 2008 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 2009 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 2010 !!erp->short_preamble); 2011 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 2012 } 2013 2014 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 2015 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 2016 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 2017 erp->cts_protection ? 2 : 0); 2018 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 2019 } 2020 2021 if (changed & BSS_CHANGED_BASIC_RATES) { 2022 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 2023 0xff0 | erp->basic_rates); 2024 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 2025 } 2026 2027 if (changed & BSS_CHANGED_ERP_SLOT) { 2028 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 2029 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 2030 erp->slot_time); 2031 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 2032 2033 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 2034 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); 2035 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 2036 } 2037 2038 if (changed & BSS_CHANGED_BEACON_INT) { 2039 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 2040 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 2041 erp->beacon_int * 16); 2042 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 2043 } 2044 2045 if (changed & BSS_CHANGED_HT) 2046 rt2800_config_ht_opmode(rt2x00dev, erp); 2047 } 2048 EXPORT_SYMBOL_GPL(rt2800_config_erp); 2049 2050 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) 2051 { 2052 u32 reg; 2053 u16 eeprom; 2054 u8 led_ctrl, led_g_mode, led_r_mode; 2055 2056 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 2057 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { 2058 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); 2059 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); 2060 } else { 2061 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); 2062 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); 2063 } 2064 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 2065 2066 reg = rt2800_register_read(rt2x00dev, LED_CFG); 2067 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; 2068 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; 2069 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || 2070 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { 2071 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 2072 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); 2073 if (led_ctrl == 0 || led_ctrl > 0x40) { 2074 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); 2075 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); 2076 rt2800_register_write(rt2x00dev, LED_CFG, reg); 2077 } else { 2078 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, 2079 (led_g_mode << 2) | led_r_mode, 1); 2080 } 2081 } 2082 } 2083 2084 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, 2085 enum antenna ant) 2086 { 2087 u32 reg; 2088 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; 2089 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; 2090 2091 if (rt2x00_is_pci(rt2x00dev)) { 2092 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR); 2093 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); 2094 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); 2095 } else if (rt2x00_is_usb(rt2x00dev)) 2096 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, 2097 eesk_pin, 0); 2098 2099 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2100 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 2101 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); 2102 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2103 } 2104 2105 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 2106 { 2107 u8 r1; 2108 u8 r3; 2109 u16 eeprom; 2110 2111 r1 = rt2800_bbp_read(rt2x00dev, 1); 2112 r3 = rt2800_bbp_read(rt2x00dev, 3); 2113 2114 if (rt2x00_rt(rt2x00dev, RT3572) && 2115 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2116 rt2800_config_3572bt_ant(rt2x00dev); 2117 2118 /* 2119 * Configure the TX antenna. 2120 */ 2121 switch (ant->tx_chain_num) { 2122 case 1: 2123 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 2124 break; 2125 case 2: 2126 if (rt2x00_rt(rt2x00dev, RT3572) && 2127 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2128 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); 2129 else 2130 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2131 break; 2132 case 3: 2133 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2134 break; 2135 } 2136 2137 /* 2138 * Configure the RX antenna. 2139 */ 2140 switch (ant->rx_chain_num) { 2141 case 1: 2142 if (rt2x00_rt(rt2x00dev, RT3070) || 2143 rt2x00_rt(rt2x00dev, RT3090) || 2144 rt2x00_rt(rt2x00dev, RT3352) || 2145 rt2x00_rt(rt2x00dev, RT3390)) { 2146 eeprom = rt2800_eeprom_read(rt2x00dev, 2147 EEPROM_NIC_CONF1); 2148 if (rt2x00_get_field16(eeprom, 2149 EEPROM_NIC_CONF1_ANT_DIVERSITY)) 2150 rt2800_set_ant_diversity(rt2x00dev, 2151 rt2x00dev->default_ant.rx); 2152 } 2153 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 2154 break; 2155 case 2: 2156 if (rt2x00_rt(rt2x00dev, RT3572) && 2157 rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2158 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); 2159 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2160 rt2x00dev->curr_band == NL80211_BAND_5GHZ); 2161 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); 2162 } else { 2163 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); 2164 } 2165 break; 2166 case 3: 2167 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); 2168 break; 2169 } 2170 2171 rt2800_bbp_write(rt2x00dev, 3, r3); 2172 rt2800_bbp_write(rt2x00dev, 1, r1); 2173 2174 if (rt2x00_rt(rt2x00dev, RT3593) || 2175 rt2x00_rt(rt2x00dev, RT3883)) { 2176 if (ant->rx_chain_num == 1) 2177 rt2800_bbp_write(rt2x00dev, 86, 0x00); 2178 else 2179 rt2800_bbp_write(rt2x00dev, 86, 0x46); 2180 } 2181 } 2182 EXPORT_SYMBOL_GPL(rt2800_config_ant); 2183 2184 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, 2185 struct rt2x00lib_conf *libconf) 2186 { 2187 u16 eeprom; 2188 short lna_gain; 2189 2190 if (libconf->rf.channel <= 14) { 2191 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2192 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); 2193 } else if (libconf->rf.channel <= 64) { 2194 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2195 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); 2196 } else if (libconf->rf.channel <= 128) { 2197 if (rt2x00_rt(rt2x00dev, RT3593) || 2198 rt2x00_rt(rt2x00dev, RT3883)) { 2199 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2200 lna_gain = rt2x00_get_field16(eeprom, 2201 EEPROM_EXT_LNA2_A1); 2202 } else { 2203 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 2204 lna_gain = rt2x00_get_field16(eeprom, 2205 EEPROM_RSSI_BG2_LNA_A1); 2206 } 2207 } else { 2208 if (rt2x00_rt(rt2x00dev, RT3593) || 2209 rt2x00_rt(rt2x00dev, RT3883)) { 2210 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2211 lna_gain = rt2x00_get_field16(eeprom, 2212 EEPROM_EXT_LNA2_A2); 2213 } else { 2214 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 2215 lna_gain = rt2x00_get_field16(eeprom, 2216 EEPROM_RSSI_A2_LNA_A2); 2217 } 2218 } 2219 2220 rt2x00dev->lna_gain = lna_gain; 2221 } 2222 2223 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev) 2224 { 2225 return clk_get_rate(rt2x00dev->clk) == 20000000; 2226 } 2227 2228 #define FREQ_OFFSET_BOUND 0x5f 2229 2230 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev) 2231 { 2232 u8 freq_offset, prev_freq_offset; 2233 u8 rfcsr, prev_rfcsr; 2234 2235 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE); 2236 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND); 2237 2238 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 2239 prev_rfcsr = rfcsr; 2240 2241 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset); 2242 if (rfcsr == prev_rfcsr) 2243 return; 2244 2245 if (rt2x00_is_usb(rt2x00dev)) { 2246 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff, 2247 freq_offset, prev_rfcsr); 2248 return; 2249 } 2250 2251 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE); 2252 while (prev_freq_offset != freq_offset) { 2253 if (prev_freq_offset < freq_offset) 2254 prev_freq_offset++; 2255 else 2256 prev_freq_offset--; 2257 2258 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset); 2259 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 2260 2261 usleep_range(1000, 1500); 2262 } 2263 } 2264 2265 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, 2266 struct ieee80211_conf *conf, 2267 struct rf_channel *rf, 2268 struct channel_info *info) 2269 { 2270 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 2271 2272 if (rt2x00dev->default_ant.tx_chain_num == 1) 2273 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); 2274 2275 if (rt2x00dev->default_ant.rx_chain_num == 1) { 2276 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); 2277 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2278 } else if (rt2x00dev->default_ant.rx_chain_num == 2) 2279 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2280 2281 if (rf->channel > 14) { 2282 /* 2283 * When TX power is below 0, we should increase it by 7 to 2284 * make it a positive value (Minimum value is -7). 2285 * However this means that values between 0 and 7 have 2286 * double meaning, and we should set a 7DBm boost flag. 2287 */ 2288 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, 2289 (info->default_power1 >= 0)); 2290 2291 if (info->default_power1 < 0) 2292 info->default_power1 += 7; 2293 2294 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); 2295 2296 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, 2297 (info->default_power2 >= 0)); 2298 2299 if (info->default_power2 < 0) 2300 info->default_power2 += 7; 2301 2302 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); 2303 } else { 2304 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); 2305 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); 2306 } 2307 2308 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); 2309 2310 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2311 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2312 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2313 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2314 2315 udelay(200); 2316 2317 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2318 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2319 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 2320 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2321 2322 udelay(200); 2323 2324 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2325 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2326 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2327 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2328 } 2329 2330 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, 2331 struct ieee80211_conf *conf, 2332 struct rf_channel *rf, 2333 struct channel_info *info) 2334 { 2335 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2336 u8 rfcsr, calib_tx, calib_rx; 2337 2338 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2339 2340 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2341 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3); 2342 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2343 2344 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2345 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2346 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2347 2348 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2349 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); 2350 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2351 2352 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2353 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); 2354 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2355 2356 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2357 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2358 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 2359 rt2x00dev->default_ant.rx_chain_num <= 1); 2360 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 2361 rt2x00dev->default_ant.rx_chain_num <= 2); 2362 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2363 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 2364 rt2x00dev->default_ant.tx_chain_num <= 1); 2365 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 2366 rt2x00dev->default_ant.tx_chain_num <= 2); 2367 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2368 2369 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2370 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2371 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2372 2373 if (rt2x00_rt(rt2x00dev, RT3390)) { 2374 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f; 2375 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f; 2376 } else { 2377 if (conf_is_ht40(conf)) { 2378 calib_tx = drv_data->calibration_bw40; 2379 calib_rx = drv_data->calibration_bw40; 2380 } else { 2381 calib_tx = drv_data->calibration_bw20; 2382 calib_rx = drv_data->calibration_bw20; 2383 } 2384 } 2385 2386 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24); 2387 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx); 2388 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr); 2389 2390 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 2391 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx); 2392 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2393 2394 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2395 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2396 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2397 2398 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2399 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 2400 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2401 2402 usleep_range(1000, 1500); 2403 2404 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 2405 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2406 } 2407 2408 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, 2409 struct ieee80211_conf *conf, 2410 struct rf_channel *rf, 2411 struct channel_info *info) 2412 { 2413 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2414 u8 rfcsr; 2415 u32 reg; 2416 2417 if (rf->channel <= 14) { 2418 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2419 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2420 } else { 2421 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2422 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2423 } 2424 2425 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2426 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 2427 2428 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2429 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2430 if (rf->channel <= 14) 2431 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); 2432 else 2433 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); 2434 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2435 2436 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5); 2437 if (rf->channel <= 14) 2438 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); 2439 else 2440 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); 2441 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); 2442 2443 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2444 if (rf->channel <= 14) { 2445 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); 2446 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2447 info->default_power1); 2448 } else { 2449 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); 2450 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2451 (info->default_power1 & 0x3) | 2452 ((info->default_power1 & 0xC) << 1)); 2453 } 2454 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2455 2456 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2457 if (rf->channel <= 14) { 2458 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); 2459 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2460 info->default_power2); 2461 } else { 2462 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); 2463 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2464 (info->default_power2 & 0x3) | 2465 ((info->default_power2 & 0xC) << 1)); 2466 } 2467 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2468 2469 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2470 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2471 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2472 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2473 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2474 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2475 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2476 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2477 if (rf->channel <= 14) { 2478 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2479 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2480 } 2481 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2482 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2483 } else { 2484 switch (rt2x00dev->default_ant.tx_chain_num) { 2485 case 1: 2486 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2487 /* fall through */ 2488 case 2: 2489 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2490 break; 2491 } 2492 2493 switch (rt2x00dev->default_ant.rx_chain_num) { 2494 case 1: 2495 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2496 /* fall through */ 2497 case 2: 2498 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2499 break; 2500 } 2501 } 2502 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2503 2504 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2505 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2506 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2507 2508 if (conf_is_ht40(conf)) { 2509 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40); 2510 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40); 2511 } else { 2512 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20); 2513 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20); 2514 } 2515 2516 if (rf->channel <= 14) { 2517 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 2518 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 2519 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2520 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 2521 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 2522 rfcsr = 0x4c; 2523 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2524 drv_data->txmixer_gain_24g); 2525 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2526 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2527 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 2528 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 2529 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 2530 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 2531 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 2532 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 2533 } else { 2534 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2535 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1); 2536 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0); 2537 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1); 2538 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0); 2539 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2540 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 2541 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2542 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 2543 rt2800_rfcsr_write(rt2x00dev, 15, 0x43); 2544 rfcsr = 0x7a; 2545 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2546 drv_data->txmixer_gain_5g); 2547 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2548 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2549 if (rf->channel <= 64) { 2550 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7); 2551 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6); 2552 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 2553 } else if (rf->channel <= 128) { 2554 rt2800_rfcsr_write(rt2x00dev, 19, 0x74); 2555 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4); 2556 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2557 } else { 2558 rt2800_rfcsr_write(rt2x00dev, 19, 0x72); 2559 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3); 2560 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2561 } 2562 rt2800_rfcsr_write(rt2x00dev, 26, 0x87); 2563 rt2800_rfcsr_write(rt2x00dev, 27, 0x01); 2564 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); 2565 } 2566 2567 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2568 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 2569 if (rf->channel <= 14) 2570 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 2571 else 2572 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); 2573 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2574 2575 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2576 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2577 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2578 } 2579 2580 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, 2581 struct ieee80211_conf *conf, 2582 struct rf_channel *rf, 2583 struct channel_info *info) 2584 { 2585 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2586 u8 txrx_agc_fc; 2587 u8 txrx_h20m; 2588 u8 rfcsr; 2589 u8 bbp; 2590 const bool txbf_enabled = false; /* TODO */ 2591 2592 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */ 2593 bbp = rt2800_bbp_read(rt2x00dev, 109); 2594 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0); 2595 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0); 2596 rt2800_bbp_write(rt2x00dev, 109, bbp); 2597 2598 bbp = rt2800_bbp_read(rt2x00dev, 110); 2599 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0); 2600 rt2800_bbp_write(rt2x00dev, 110, bbp); 2601 2602 if (rf->channel <= 14) { 2603 /* Restore BBP 25 & 26 for 2.4 GHz */ 2604 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2605 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2606 } else { 2607 /* Hard code BBP 25 & 26 for 5GHz */ 2608 2609 /* Enable IQ Phase correction */ 2610 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2611 /* Setup IQ Phase correction value */ 2612 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2613 } 2614 2615 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2616 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf); 2617 2618 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2619 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3)); 2620 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2621 2622 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2623 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1); 2624 if (rf->channel <= 14) 2625 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1); 2626 else 2627 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2); 2628 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2629 2630 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53); 2631 if (rf->channel <= 14) { 2632 rfcsr = 0; 2633 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2634 info->default_power1 & 0x1f); 2635 } else { 2636 if (rt2x00_is_usb(rt2x00dev)) 2637 rfcsr = 0x40; 2638 2639 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2640 ((info->default_power1 & 0x18) << 1) | 2641 (info->default_power1 & 7)); 2642 } 2643 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr); 2644 2645 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55); 2646 if (rf->channel <= 14) { 2647 rfcsr = 0; 2648 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2649 info->default_power2 & 0x1f); 2650 } else { 2651 if (rt2x00_is_usb(rt2x00dev)) 2652 rfcsr = 0x40; 2653 2654 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2655 ((info->default_power2 & 0x18) << 1) | 2656 (info->default_power2 & 7)); 2657 } 2658 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr); 2659 2660 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54); 2661 if (rf->channel <= 14) { 2662 rfcsr = 0; 2663 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2664 info->default_power3 & 0x1f); 2665 } else { 2666 if (rt2x00_is_usb(rt2x00dev)) 2667 rfcsr = 0x40; 2668 2669 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2670 ((info->default_power3 & 0x18) << 1) | 2671 (info->default_power3 & 7)); 2672 } 2673 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr); 2674 2675 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2676 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2677 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2678 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2679 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2680 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2681 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2682 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2683 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2684 2685 switch (rt2x00dev->default_ant.tx_chain_num) { 2686 case 3: 2687 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2688 /* fallthrough */ 2689 case 2: 2690 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2691 /* fallthrough */ 2692 case 1: 2693 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2694 break; 2695 } 2696 2697 switch (rt2x00dev->default_ant.rx_chain_num) { 2698 case 3: 2699 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2700 /* fallthrough */ 2701 case 2: 2702 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2703 /* fallthrough */ 2704 case 1: 2705 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2706 break; 2707 } 2708 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2709 2710 rt2800_freq_cal_mode1(rt2x00dev); 2711 2712 if (conf_is_ht40(conf)) { 2713 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40, 2714 RFCSR24_TX_AGC_FC); 2715 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40, 2716 RFCSR24_TX_H20M); 2717 } else { 2718 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20, 2719 RFCSR24_TX_AGC_FC); 2720 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20, 2721 RFCSR24_TX_H20M); 2722 } 2723 2724 /* NOTE: the reference driver does not writes the new value 2725 * back to RFCSR 32 2726 */ 2727 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32); 2728 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc); 2729 2730 if (rf->channel <= 14) 2731 rfcsr = 0xa0; 2732 else 2733 rfcsr = 0x80; 2734 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2735 2736 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2737 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m); 2738 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m); 2739 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2740 2741 /* Band selection */ 2742 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 2743 if (rf->channel <= 14) 2744 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 2745 else 2746 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 2747 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 2748 2749 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34); 2750 if (rf->channel <= 14) 2751 rfcsr = 0x3c; 2752 else 2753 rfcsr = 0x20; 2754 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 2755 2756 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2757 if (rf->channel <= 14) 2758 rfcsr = 0x1a; 2759 else 2760 rfcsr = 0x12; 2761 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2762 2763 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2764 if (rf->channel >= 1 && rf->channel <= 14) 2765 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2766 else if (rf->channel >= 36 && rf->channel <= 64) 2767 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2768 else if (rf->channel >= 100 && rf->channel <= 128) 2769 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2770 else 2771 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2772 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2773 2774 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2775 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 2776 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2777 2778 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 2779 2780 if (rf->channel <= 14) { 2781 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 2782 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 2783 } else { 2784 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8); 2785 rt2800_rfcsr_write(rt2x00dev, 13, 0x23); 2786 } 2787 2788 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2789 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1); 2790 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2791 2792 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2793 if (rf->channel <= 14) { 2794 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5); 2795 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3); 2796 } else { 2797 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4); 2798 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2); 2799 } 2800 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2801 2802 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2803 if (rf->channel <= 14) 2804 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3); 2805 else 2806 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2); 2807 2808 if (txbf_enabled) 2809 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1); 2810 2811 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2812 2813 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 2814 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0); 2815 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2816 2817 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 2818 if (rf->channel <= 14) 2819 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b); 2820 else 2821 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f); 2822 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr); 2823 2824 if (rf->channel <= 14) { 2825 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 2826 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 2827 } else { 2828 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 2829 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 2830 } 2831 2832 /* Initiate VCO calibration */ 2833 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2834 if (rf->channel <= 14) { 2835 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2836 } else { 2837 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1); 2838 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1); 2839 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1); 2840 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1); 2841 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1); 2842 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2843 } 2844 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2845 2846 if (rf->channel >= 1 && rf->channel <= 14) { 2847 rfcsr = 0x23; 2848 if (txbf_enabled) 2849 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2850 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2851 2852 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 2853 } else if (rf->channel >= 36 && rf->channel <= 64) { 2854 rfcsr = 0x36; 2855 if (txbf_enabled) 2856 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2857 rt2800_rfcsr_write(rt2x00dev, 39, 0x36); 2858 2859 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb); 2860 } else if (rf->channel >= 100 && rf->channel <= 128) { 2861 rfcsr = 0x32; 2862 if (txbf_enabled) 2863 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2864 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2865 2866 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3); 2867 } else { 2868 rfcsr = 0x30; 2869 if (txbf_enabled) 2870 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2871 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2872 2873 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b); 2874 } 2875 } 2876 2877 static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev, 2878 struct ieee80211_conf *conf, 2879 struct rf_channel *rf, 2880 struct channel_info *info) 2881 { 2882 u8 rfcsr; 2883 u8 bbp; 2884 u8 pwr1, pwr2, pwr3; 2885 2886 const bool txbf_enabled = false; /* TODO */ 2887 2888 /* TODO: add band selection */ 2889 2890 if (rf->channel <= 14) 2891 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 2892 else if (rf->channel < 132) 2893 rt2800_rfcsr_write(rt2x00dev, 6, 0x80); 2894 else 2895 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 2896 2897 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2898 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2899 2900 if (rf->channel <= 14) 2901 rt2800_rfcsr_write(rt2x00dev, 11, 0x46); 2902 else 2903 rt2800_rfcsr_write(rt2x00dev, 11, 0x48); 2904 2905 if (rf->channel <= 14) 2906 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a); 2907 else 2908 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 2909 2910 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 2911 2912 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2913 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2914 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2915 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2916 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2917 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2918 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2919 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2920 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2921 2922 switch (rt2x00dev->default_ant.tx_chain_num) { 2923 case 3: 2924 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2925 /* fallthrough */ 2926 case 2: 2927 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2928 /* fallthrough */ 2929 case 1: 2930 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2931 break; 2932 } 2933 2934 switch (rt2x00dev->default_ant.rx_chain_num) { 2935 case 3: 2936 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2937 /* fallthrough */ 2938 case 2: 2939 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2940 /* fallthrough */ 2941 case 1: 2942 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2943 break; 2944 } 2945 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2946 2947 rt2800_freq_cal_mode1(rt2x00dev); 2948 2949 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2950 if (!conf_is_ht40(conf)) 2951 rfcsr &= ~(0x06); 2952 else 2953 rfcsr |= 0x06; 2954 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2955 2956 if (rf->channel <= 14) 2957 rt2800_rfcsr_write(rt2x00dev, 31, 0xa0); 2958 else 2959 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 2960 2961 if (conf_is_ht40(conf)) 2962 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 2963 else 2964 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8); 2965 2966 if (rf->channel <= 14) 2967 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 2968 else 2969 rt2800_rfcsr_write(rt2x00dev, 34, 0x20); 2970 2971 /* loopback RF_BS */ 2972 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 2973 if (rf->channel <= 14) 2974 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 2975 else 2976 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 2977 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 2978 2979 if (rf->channel <= 14) 2980 rfcsr = 0x23; 2981 else if (rf->channel < 100) 2982 rfcsr = 0x36; 2983 else if (rf->channel < 132) 2984 rfcsr = 0x32; 2985 else 2986 rfcsr = 0x30; 2987 2988 if (txbf_enabled) 2989 rfcsr |= 0x40; 2990 2991 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2992 2993 if (rf->channel <= 14) 2994 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 2995 else 2996 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 2997 2998 if (rf->channel <= 14) 2999 rfcsr = 0xbb; 3000 else if (rf->channel < 100) 3001 rfcsr = 0xeb; 3002 else if (rf->channel < 132) 3003 rfcsr = 0xb3; 3004 else 3005 rfcsr = 0x9b; 3006 rt2800_rfcsr_write(rt2x00dev, 45, rfcsr); 3007 3008 if (rf->channel <= 14) 3009 rfcsr = 0x8e; 3010 else 3011 rfcsr = 0x8a; 3012 3013 if (txbf_enabled) 3014 rfcsr |= 0x20; 3015 3016 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3017 3018 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 3019 3020 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 3021 if (rf->channel <= 14) 3022 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 3023 else 3024 rt2800_rfcsr_write(rt2x00dev, 51, 0x51); 3025 3026 rfcsr = rt2800_rfcsr_read(rt2x00dev, 52); 3027 if (rf->channel <= 14) 3028 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 3029 else 3030 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 3031 3032 if (rf->channel <= 14) { 3033 pwr1 = info->default_power1 & 0x1f; 3034 pwr2 = info->default_power2 & 0x1f; 3035 pwr3 = info->default_power3 & 0x1f; 3036 } else { 3037 pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) | 3038 (info->default_power1 & 0x7); 3039 pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) | 3040 (info->default_power2 & 0x7); 3041 pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) | 3042 (info->default_power3 & 0x7); 3043 } 3044 3045 rt2800_rfcsr_write(rt2x00dev, 53, pwr1); 3046 rt2800_rfcsr_write(rt2x00dev, 54, pwr2); 3047 rt2800_rfcsr_write(rt2x00dev, 55, pwr3); 3048 3049 rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n", 3050 rf->channel, pwr1, pwr2, pwr3); 3051 3052 bbp = (info->default_power1 >> 5) | 3053 ((info->default_power2 & 0xe0) >> 1); 3054 rt2800_bbp_write(rt2x00dev, 109, bbp); 3055 3056 bbp = rt2800_bbp_read(rt2x00dev, 110); 3057 bbp &= 0x0f; 3058 bbp |= (info->default_power3 & 0xe0) >> 1; 3059 rt2800_bbp_write(rt2x00dev, 110, bbp); 3060 3061 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 3062 if (rf->channel <= 14) 3063 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 3064 else 3065 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e); 3066 3067 /* Enable RF tuning */ 3068 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3069 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3070 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3071 3072 udelay(2000); 3073 3074 bbp = rt2800_bbp_read(rt2x00dev, 49); 3075 /* clear update flag */ 3076 rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe); 3077 rt2800_bbp_write(rt2x00dev, 49, bbp); 3078 3079 /* TODO: add calibration for TxBF */ 3080 } 3081 3082 #define POWER_BOUND 0x27 3083 #define POWER_BOUND_5G 0x2b 3084 3085 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev, 3086 struct ieee80211_conf *conf, 3087 struct rf_channel *rf, 3088 struct channel_info *info) 3089 { 3090 u8 rfcsr; 3091 3092 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3093 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3094 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3095 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 3096 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3097 3098 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3099 if (info->default_power1 > POWER_BOUND) 3100 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 3101 else 3102 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3103 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3104 3105 rt2800_freq_cal_mode1(rt2x00dev); 3106 3107 if (rf->channel <= 14) { 3108 if (rf->channel == 6) 3109 rt2800_bbp_write(rt2x00dev, 68, 0x0c); 3110 else 3111 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 3112 3113 if (rf->channel >= 1 && rf->channel <= 6) 3114 rt2800_bbp_write(rt2x00dev, 59, 0x0f); 3115 else if (rf->channel >= 7 && rf->channel <= 11) 3116 rt2800_bbp_write(rt2x00dev, 59, 0x0e); 3117 else if (rf->channel >= 12 && rf->channel <= 14) 3118 rt2800_bbp_write(rt2x00dev, 59, 0x0d); 3119 } 3120 } 3121 3122 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev, 3123 struct ieee80211_conf *conf, 3124 struct rf_channel *rf, 3125 struct channel_info *info) 3126 { 3127 u8 rfcsr; 3128 3129 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3130 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3131 3132 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 3133 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 3134 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 3135 3136 if (info->default_power1 > POWER_BOUND) 3137 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND); 3138 else 3139 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1); 3140 3141 if (info->default_power2 > POWER_BOUND) 3142 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND); 3143 else 3144 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2); 3145 3146 rt2800_freq_cal_mode1(rt2x00dev); 3147 3148 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3149 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3150 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3151 3152 if ( rt2x00dev->default_ant.tx_chain_num == 2 ) 3153 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3154 else 3155 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 3156 3157 if ( rt2x00dev->default_ant.rx_chain_num == 2 ) 3158 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3159 else 3160 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 3161 3162 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3163 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3164 3165 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3166 3167 rt2800_rfcsr_write(rt2x00dev, 31, 80); 3168 } 3169 3170 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 3171 struct ieee80211_conf *conf, 3172 struct rf_channel *rf, 3173 struct channel_info *info) 3174 { 3175 u8 rfcsr; 3176 int idx = rf->channel-1; 3177 3178 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3179 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3180 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3181 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 3182 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3183 3184 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3185 if (info->default_power1 > POWER_BOUND) 3186 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 3187 else 3188 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3189 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3190 3191 if (rt2x00_rt(rt2x00dev, RT5392)) { 3192 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3193 if (info->default_power2 > POWER_BOUND) 3194 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND); 3195 else 3196 rt2x00_set_field8(&rfcsr, RFCSR50_TX, 3197 info->default_power2); 3198 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3199 } 3200 3201 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3202 if (rt2x00_rt(rt2x00dev, RT5392)) { 3203 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3204 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3205 } 3206 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3207 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3208 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3209 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3210 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3211 3212 rt2800_freq_cal_mode1(rt2x00dev); 3213 3214 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 3215 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3216 /* r55/r59 value array of channel 1~14 */ 3217 static const char r55_bt_rev[] = {0x83, 0x83, 3218 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, 3219 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; 3220 static const char r59_bt_rev[] = {0x0e, 0x0e, 3221 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, 3222 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; 3223 3224 rt2800_rfcsr_write(rt2x00dev, 55, 3225 r55_bt_rev[idx]); 3226 rt2800_rfcsr_write(rt2x00dev, 59, 3227 r59_bt_rev[idx]); 3228 } else { 3229 static const char r59_bt[] = {0x8b, 0x8b, 0x8b, 3230 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, 3231 0x88, 0x88, 0x86, 0x85, 0x84}; 3232 3233 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); 3234 } 3235 } else { 3236 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3237 static const char r55_nonbt_rev[] = {0x23, 0x23, 3238 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, 3239 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; 3240 static const char r59_nonbt_rev[] = {0x07, 0x07, 3241 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 3242 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; 3243 3244 rt2800_rfcsr_write(rt2x00dev, 55, 3245 r55_nonbt_rev[idx]); 3246 rt2800_rfcsr_write(rt2x00dev, 59, 3247 r59_nonbt_rev[idx]); 3248 } else if (rt2x00_rt(rt2x00dev, RT5390) || 3249 rt2x00_rt(rt2x00dev, RT5392) || 3250 rt2x00_rt(rt2x00dev, RT6352)) { 3251 static const char r59_non_bt[] = {0x8f, 0x8f, 3252 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, 3253 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; 3254 3255 rt2800_rfcsr_write(rt2x00dev, 59, 3256 r59_non_bt[idx]); 3257 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 3258 static const char r59_non_bt[] = {0x0b, 0x0b, 3259 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a, 3260 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06}; 3261 3262 rt2800_rfcsr_write(rt2x00dev, 59, 3263 r59_non_bt[idx]); 3264 } 3265 } 3266 } 3267 3268 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, 3269 struct ieee80211_conf *conf, 3270 struct rf_channel *rf, 3271 struct channel_info *info) 3272 { 3273 u8 rfcsr, ep_reg; 3274 u32 reg; 3275 int power_bound; 3276 3277 /* TODO */ 3278 const bool is_11b = false; 3279 const bool is_type_ep = false; 3280 3281 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 3282 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3283 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0); 3284 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 3285 3286 /* Order of values on rf_channel entry: N, K, mod, R */ 3287 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff); 3288 3289 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9); 3290 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf); 3291 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8); 3292 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2); 3293 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr); 3294 3295 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3296 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1); 3297 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3); 3298 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3299 3300 if (rf->channel <= 14) { 3301 rt2800_rfcsr_write(rt2x00dev, 10, 0x90); 3302 /* FIXME: RF11 owerwrite ? */ 3303 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A); 3304 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 3305 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3306 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3307 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A); 3308 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 3309 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3310 rt2800_rfcsr_write(rt2x00dev, 36, 0x80); 3311 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 3312 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 3313 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B); 3314 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D); 3315 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B); 3316 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5); 3317 rt2800_rfcsr_write(rt2x00dev, 43, 0x72); 3318 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E); 3319 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2); 3320 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B); 3321 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 3322 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E); 3323 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 3324 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 3325 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1); 3326 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 3327 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 3328 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 3329 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 3330 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 3331 3332 /* TODO RF27 <- tssi */ 3333 3334 rfcsr = rf->channel <= 10 ? 0x07 : 0x06; 3335 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 3336 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr); 3337 3338 if (is_11b) { 3339 /* CCK */ 3340 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8); 3341 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0); 3342 if (is_type_ep) 3343 rt2800_rfcsr_write(rt2x00dev, 55, 0x06); 3344 else 3345 rt2800_rfcsr_write(rt2x00dev, 55, 0x47); 3346 } else { 3347 /* OFDM */ 3348 if (is_type_ep) 3349 rt2800_rfcsr_write(rt2x00dev, 55, 0x03); 3350 else 3351 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 3352 } 3353 3354 power_bound = POWER_BOUND; 3355 ep_reg = 0x2; 3356 } else { 3357 rt2800_rfcsr_write(rt2x00dev, 10, 0x97); 3358 /* FIMXE: RF11 overwrite */ 3359 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 3360 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF); 3361 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3362 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 3363 rt2800_rfcsr_write(rt2x00dev, 37, 0x04); 3364 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 3365 rt2800_rfcsr_write(rt2x00dev, 40, 0x42); 3366 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB); 3367 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7); 3368 rt2800_rfcsr_write(rt2x00dev, 45, 0x41); 3369 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 3370 rt2800_rfcsr_write(rt2x00dev, 57, 0x77); 3371 rt2800_rfcsr_write(rt2x00dev, 60, 0x05); 3372 rt2800_rfcsr_write(rt2x00dev, 61, 0x01); 3373 3374 /* TODO RF27 <- tssi */ 3375 3376 if (rf->channel >= 36 && rf->channel <= 64) { 3377 3378 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E); 3379 rt2800_rfcsr_write(rt2x00dev, 13, 0x22); 3380 rt2800_rfcsr_write(rt2x00dev, 22, 0x60); 3381 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F); 3382 if (rf->channel <= 50) 3383 rt2800_rfcsr_write(rt2x00dev, 24, 0x09); 3384 else if (rf->channel >= 52) 3385 rt2800_rfcsr_write(rt2x00dev, 24, 0x07); 3386 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C); 3387 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B); 3388 rt2800_rfcsr_write(rt2x00dev, 44, 0X40); 3389 rt2800_rfcsr_write(rt2x00dev, 46, 0X00); 3390 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE); 3391 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C); 3392 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8); 3393 if (rf->channel <= 50) { 3394 rt2800_rfcsr_write(rt2x00dev, 55, 0x06), 3395 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3); 3396 } else if (rf->channel >= 52) { 3397 rt2800_rfcsr_write(rt2x00dev, 55, 0x04); 3398 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3399 } 3400 3401 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3402 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F); 3403 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3404 3405 } else if (rf->channel >= 100 && rf->channel <= 165) { 3406 3407 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E); 3408 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3409 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3410 if (rf->channel <= 153) { 3411 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C); 3412 rt2800_rfcsr_write(rt2x00dev, 24, 0x06); 3413 } else if (rf->channel >= 155) { 3414 rt2800_rfcsr_write(rt2x00dev, 23, 0x38); 3415 rt2800_rfcsr_write(rt2x00dev, 24, 0x05); 3416 } 3417 if (rf->channel <= 138) { 3418 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A); 3419 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B); 3420 rt2800_rfcsr_write(rt2x00dev, 44, 0x20); 3421 rt2800_rfcsr_write(rt2x00dev, 46, 0x18); 3422 } else if (rf->channel >= 140) { 3423 rt2800_rfcsr_write(rt2x00dev, 39, 0x18); 3424 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B); 3425 rt2800_rfcsr_write(rt2x00dev, 44, 0x10); 3426 rt2800_rfcsr_write(rt2x00dev, 46, 0X08); 3427 } 3428 if (rf->channel <= 124) 3429 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC); 3430 else if (rf->channel >= 126) 3431 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC); 3432 if (rf->channel <= 138) 3433 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3434 else if (rf->channel >= 140) 3435 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3436 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB); 3437 if (rf->channel <= 138) 3438 rt2800_rfcsr_write(rt2x00dev, 55, 0x01); 3439 else if (rf->channel >= 140) 3440 rt2800_rfcsr_write(rt2x00dev, 55, 0x00); 3441 if (rf->channel <= 128) 3442 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3443 else if (rf->channel >= 130) 3444 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB); 3445 if (rf->channel <= 116) 3446 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D); 3447 else if (rf->channel >= 118) 3448 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3449 if (rf->channel <= 138) 3450 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F); 3451 else if (rf->channel >= 140) 3452 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C); 3453 if (rf->channel <= 116) 3454 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D); 3455 else if (rf->channel >= 118) 3456 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3457 } 3458 3459 power_bound = POWER_BOUND_5G; 3460 ep_reg = 0x3; 3461 } 3462 3463 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3464 if (info->default_power1 > power_bound) 3465 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound); 3466 else 3467 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3468 if (is_type_ep) 3469 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg); 3470 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3471 3472 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3473 if (info->default_power2 > power_bound) 3474 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound); 3475 else 3476 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2); 3477 if (is_type_ep) 3478 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg); 3479 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3480 3481 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3482 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3483 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3484 3485 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 3486 rt2x00dev->default_ant.tx_chain_num >= 1); 3487 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 3488 rt2x00dev->default_ant.tx_chain_num == 2); 3489 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3490 3491 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 3492 rt2x00dev->default_ant.rx_chain_num >= 1); 3493 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 3494 rt2x00dev->default_ant.rx_chain_num == 2); 3495 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3496 3497 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3498 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4); 3499 3500 if (conf_is_ht40(conf)) 3501 rt2800_rfcsr_write(rt2x00dev, 30, 0x16); 3502 else 3503 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 3504 3505 if (!is_11b) { 3506 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3507 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3508 } 3509 3510 /* TODO proper frequency adjustment */ 3511 rt2800_freq_cal_mode1(rt2x00dev); 3512 3513 /* TODO merge with others */ 3514 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3515 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3516 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3517 3518 /* BBP settings */ 3519 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3520 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3521 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3522 3523 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18); 3524 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08); 3525 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38); 3526 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92); 3527 3528 /* GLRT band configuration */ 3529 rt2800_bbp_write(rt2x00dev, 195, 128); 3530 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0); 3531 rt2800_bbp_write(rt2x00dev, 195, 129); 3532 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E); 3533 rt2800_bbp_write(rt2x00dev, 195, 130); 3534 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28); 3535 rt2800_bbp_write(rt2x00dev, 195, 131); 3536 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20); 3537 rt2800_bbp_write(rt2x00dev, 195, 133); 3538 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F); 3539 rt2800_bbp_write(rt2x00dev, 195, 124); 3540 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F); 3541 } 3542 3543 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev, 3544 struct ieee80211_conf *conf, 3545 struct rf_channel *rf, 3546 struct channel_info *info) 3547 { 3548 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 3549 u8 rx_agc_fc, tx_agc_fc; 3550 u8 rfcsr; 3551 3552 /* Frequeny plan setting */ 3553 /* Rdiv setting (set 0x03 if Xtal==20) 3554 * R13[1:0] 3555 */ 3556 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 3557 rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620, 3558 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0); 3559 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 3560 3561 /* N setting 3562 * R20[7:0] in rf->rf1 3563 * R21[0] always 0 3564 */ 3565 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 3566 rfcsr = (rf->rf1 & 0x00ff); 3567 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 3568 3569 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3570 rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0); 3571 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3572 3573 /* K setting (always 0) 3574 * R16[3:0] (RF PLL freq selection) 3575 */ 3576 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3577 rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0); 3578 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3579 3580 /* D setting (always 0) 3581 * R22[2:0] (D=15, R22[2:0]=<111>) 3582 */ 3583 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 3584 rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0); 3585 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 3586 3587 /* Ksd setting 3588 * Ksd: R17<7:0> in rf->rf2 3589 * R18<7:0> in rf->rf3 3590 * R19<1:0> in rf->rf4 3591 */ 3592 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 3593 rfcsr = rf->rf2; 3594 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 3595 3596 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 3597 rfcsr = rf->rf3; 3598 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 3599 3600 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19); 3601 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4); 3602 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr); 3603 3604 /* Default: XO=20MHz , SDM mode */ 3605 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3606 rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80); 3607 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3608 3609 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3610 rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1); 3611 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3612 3613 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3614 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620, 3615 rt2x00dev->default_ant.tx_chain_num != 1); 3616 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3617 3618 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 3619 rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620, 3620 rt2x00dev->default_ant.tx_chain_num != 1); 3621 rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620, 3622 rt2x00dev->default_ant.rx_chain_num != 1); 3623 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 3624 3625 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42); 3626 rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620, 3627 rt2x00dev->default_ant.tx_chain_num != 1); 3628 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 3629 3630 /* RF for DC Cal BW */ 3631 if (conf_is_ht40(conf)) { 3632 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 3633 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 3634 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 3635 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 3636 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 3637 } else { 3638 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20); 3639 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20); 3640 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00); 3641 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20); 3642 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20); 3643 } 3644 3645 if (conf_is_ht40(conf)) { 3646 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08); 3647 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08); 3648 } else { 3649 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28); 3650 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28); 3651 } 3652 3653 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28); 3654 rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40, 3655 conf_is_ht40(conf) && (rf->channel == 11)); 3656 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr); 3657 3658 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) { 3659 if (conf_is_ht40(conf)) { 3660 rx_agc_fc = drv_data->rx_calibration_bw40; 3661 tx_agc_fc = drv_data->tx_calibration_bw40; 3662 } else { 3663 rx_agc_fc = drv_data->rx_calibration_bw20; 3664 tx_agc_fc = drv_data->tx_calibration_bw20; 3665 } 3666 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 3667 rfcsr &= (~0x3F); 3668 rfcsr |= rx_agc_fc; 3669 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr); 3670 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 3671 rfcsr &= (~0x3F); 3672 rfcsr |= rx_agc_fc; 3673 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr); 3674 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6); 3675 rfcsr &= (~0x3F); 3676 rfcsr |= rx_agc_fc; 3677 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr); 3678 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7); 3679 rfcsr &= (~0x3F); 3680 rfcsr |= rx_agc_fc; 3681 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr); 3682 3683 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 3684 rfcsr &= (~0x3F); 3685 rfcsr |= tx_agc_fc; 3686 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr); 3687 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 3688 rfcsr &= (~0x3F); 3689 rfcsr |= tx_agc_fc; 3690 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr); 3691 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58); 3692 rfcsr &= (~0x3F); 3693 rfcsr |= tx_agc_fc; 3694 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr); 3695 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59); 3696 rfcsr &= (~0x3F); 3697 rfcsr |= tx_agc_fc; 3698 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr); 3699 } 3700 } 3701 3702 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev, 3703 struct ieee80211_channel *chan, 3704 int power_level) { 3705 u16 eeprom, target_power, max_power; 3706 u32 mac_sys_ctrl, mac_status; 3707 u32 reg; 3708 u8 bbp; 3709 int i; 3710 3711 /* hardware unit is 0.5dBm, limited to 23.5dBm */ 3712 power_level *= 2; 3713 if (power_level > 0x2f) 3714 power_level = 0x2f; 3715 3716 max_power = chan->max_power * 2; 3717 if (max_power > 0x2f) 3718 max_power = 0x2f; 3719 3720 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0); 3721 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, power_level); 3722 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, power_level); 3723 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, max_power); 3724 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, max_power); 3725 3726 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 3727 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) { 3728 /* init base power by eeprom target power */ 3729 target_power = rt2800_eeprom_read(rt2x00dev, 3730 EEPROM_TXPOWER_INIT); 3731 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power); 3732 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power); 3733 } 3734 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg); 3735 3736 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 3737 rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0); 3738 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 3739 3740 /* Save MAC SYS CTRL registers */ 3741 mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 3742 /* Disable Tx/Rx */ 3743 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 3744 /* Check MAC Tx/Rx idle */ 3745 for (i = 0; i < 10000; i++) { 3746 mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 3747 if (mac_status & 0x3) 3748 usleep_range(50, 200); 3749 else 3750 break; 3751 } 3752 3753 if (i == 10000) 3754 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n"); 3755 3756 if (chan->center_freq > 2457) { 3757 bbp = rt2800_bbp_read(rt2x00dev, 30); 3758 bbp = 0x40; 3759 rt2800_bbp_write(rt2x00dev, 30, bbp); 3760 rt2800_rfcsr_write(rt2x00dev, 39, 0); 3761 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3762 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb); 3763 else 3764 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b); 3765 } else { 3766 bbp = rt2800_bbp_read(rt2x00dev, 30); 3767 bbp = 0x1f; 3768 rt2800_bbp_write(rt2x00dev, 30, bbp); 3769 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 3770 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3771 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb); 3772 else 3773 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); 3774 } 3775 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl); 3776 3777 rt2800_vco_calibration(rt2x00dev); 3778 } 3779 3780 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, 3781 const unsigned int word, 3782 const u8 value) 3783 { 3784 u8 chain, reg; 3785 3786 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) { 3787 reg = rt2800_bbp_read(rt2x00dev, 27); 3788 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); 3789 rt2800_bbp_write(rt2x00dev, 27, reg); 3790 3791 rt2800_bbp_write(rt2x00dev, word, value); 3792 } 3793 } 3794 3795 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel) 3796 { 3797 u8 cal; 3798 3799 /* TX0 IQ Gain */ 3800 rt2800_bbp_write(rt2x00dev, 158, 0x2c); 3801 if (channel <= 14) 3802 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G); 3803 else if (channel >= 36 && channel <= 64) 3804 cal = rt2x00_eeprom_byte(rt2x00dev, 3805 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G); 3806 else if (channel >= 100 && channel <= 138) 3807 cal = rt2x00_eeprom_byte(rt2x00dev, 3808 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G); 3809 else if (channel >= 140 && channel <= 165) 3810 cal = rt2x00_eeprom_byte(rt2x00dev, 3811 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G); 3812 else 3813 cal = 0; 3814 rt2800_bbp_write(rt2x00dev, 159, cal); 3815 3816 /* TX0 IQ Phase */ 3817 rt2800_bbp_write(rt2x00dev, 158, 0x2d); 3818 if (channel <= 14) 3819 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G); 3820 else if (channel >= 36 && channel <= 64) 3821 cal = rt2x00_eeprom_byte(rt2x00dev, 3822 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G); 3823 else if (channel >= 100 && channel <= 138) 3824 cal = rt2x00_eeprom_byte(rt2x00dev, 3825 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G); 3826 else if (channel >= 140 && channel <= 165) 3827 cal = rt2x00_eeprom_byte(rt2x00dev, 3828 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G); 3829 else 3830 cal = 0; 3831 rt2800_bbp_write(rt2x00dev, 159, cal); 3832 3833 /* TX1 IQ Gain */ 3834 rt2800_bbp_write(rt2x00dev, 158, 0x4a); 3835 if (channel <= 14) 3836 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G); 3837 else if (channel >= 36 && channel <= 64) 3838 cal = rt2x00_eeprom_byte(rt2x00dev, 3839 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G); 3840 else if (channel >= 100 && channel <= 138) 3841 cal = rt2x00_eeprom_byte(rt2x00dev, 3842 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G); 3843 else if (channel >= 140 && channel <= 165) 3844 cal = rt2x00_eeprom_byte(rt2x00dev, 3845 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G); 3846 else 3847 cal = 0; 3848 rt2800_bbp_write(rt2x00dev, 159, cal); 3849 3850 /* TX1 IQ Phase */ 3851 rt2800_bbp_write(rt2x00dev, 158, 0x4b); 3852 if (channel <= 14) 3853 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G); 3854 else if (channel >= 36 && channel <= 64) 3855 cal = rt2x00_eeprom_byte(rt2x00dev, 3856 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G); 3857 else if (channel >= 100 && channel <= 138) 3858 cal = rt2x00_eeprom_byte(rt2x00dev, 3859 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G); 3860 else if (channel >= 140 && channel <= 165) 3861 cal = rt2x00_eeprom_byte(rt2x00dev, 3862 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G); 3863 else 3864 cal = 0; 3865 rt2800_bbp_write(rt2x00dev, 159, cal); 3866 3867 /* FIXME: possible RX0, RX1 callibration ? */ 3868 3869 /* RF IQ compensation control */ 3870 rt2800_bbp_write(rt2x00dev, 158, 0x04); 3871 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL); 3872 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3873 3874 /* RF IQ imbalance compensation control */ 3875 rt2800_bbp_write(rt2x00dev, 158, 0x03); 3876 cal = rt2x00_eeprom_byte(rt2x00dev, 3877 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL); 3878 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3879 } 3880 3881 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev, 3882 unsigned int channel, 3883 char txpower) 3884 { 3885 if (rt2x00_rt(rt2x00dev, RT3593) || 3886 rt2x00_rt(rt2x00dev, RT3883)) 3887 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC); 3888 3889 if (channel <= 14) 3890 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER); 3891 3892 if (rt2x00_rt(rt2x00dev, RT3593) || 3893 rt2x00_rt(rt2x00dev, RT3883)) 3894 return clamp_t(char, txpower, MIN_A_TXPOWER_3593, 3895 MAX_A_TXPOWER_3593); 3896 else 3897 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER); 3898 } 3899 3900 static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev, 3901 struct rf_channel *rf) 3902 { 3903 u8 bbp; 3904 3905 bbp = (rf->channel > 14) ? 0x48 : 0x38; 3906 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp); 3907 3908 rt2800_bbp_write(rt2x00dev, 69, 0x12); 3909 3910 if (rf->channel <= 14) { 3911 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 3912 } else { 3913 /* Disable CCK packet detection */ 3914 rt2800_bbp_write(rt2x00dev, 70, 0x00); 3915 } 3916 3917 rt2800_bbp_write(rt2x00dev, 73, 0x10); 3918 3919 if (rf->channel > 14) { 3920 rt2800_bbp_write(rt2x00dev, 62, 0x1d); 3921 rt2800_bbp_write(rt2x00dev, 63, 0x1d); 3922 rt2800_bbp_write(rt2x00dev, 64, 0x1d); 3923 } else { 3924 rt2800_bbp_write(rt2x00dev, 62, 0x2d); 3925 rt2800_bbp_write(rt2x00dev, 63, 0x2d); 3926 rt2800_bbp_write(rt2x00dev, 64, 0x2d); 3927 } 3928 } 3929 3930 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 3931 struct ieee80211_conf *conf, 3932 struct rf_channel *rf, 3933 struct channel_info *info) 3934 { 3935 u32 reg; 3936 u32 tx_pin; 3937 u8 bbp, rfcsr; 3938 3939 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3940 info->default_power1); 3941 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3942 info->default_power2); 3943 if (rt2x00dev->default_ant.tx_chain_num > 2) 3944 info->default_power3 = 3945 rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3946 info->default_power3); 3947 3948 switch (rt2x00dev->chip.rt) { 3949 case RT3883: 3950 rt3883_bbp_adjust(rt2x00dev, rf); 3951 break; 3952 } 3953 3954 switch (rt2x00dev->chip.rf) { 3955 case RF2020: 3956 case RF3020: 3957 case RF3021: 3958 case RF3022: 3959 case RF3320: 3960 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 3961 break; 3962 case RF3052: 3963 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); 3964 break; 3965 case RF3053: 3966 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info); 3967 break; 3968 case RF3290: 3969 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info); 3970 break; 3971 case RF3322: 3972 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); 3973 break; 3974 case RF3853: 3975 rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info); 3976 break; 3977 case RF3070: 3978 case RF5350: 3979 case RF5360: 3980 case RF5362: 3981 case RF5370: 3982 case RF5372: 3983 case RF5390: 3984 case RF5392: 3985 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); 3986 break; 3987 case RF5592: 3988 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info); 3989 break; 3990 case RF7620: 3991 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info); 3992 break; 3993 default: 3994 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 3995 } 3996 3997 if (rt2x00_rf(rt2x00dev, RF3070) || 3998 rt2x00_rf(rt2x00dev, RF3290) || 3999 rt2x00_rf(rt2x00dev, RF3322) || 4000 rt2x00_rf(rt2x00dev, RF5350) || 4001 rt2x00_rf(rt2x00dev, RF5360) || 4002 rt2x00_rf(rt2x00dev, RF5362) || 4003 rt2x00_rf(rt2x00dev, RF5370) || 4004 rt2x00_rf(rt2x00dev, RF5372) || 4005 rt2x00_rf(rt2x00dev, RF5390) || 4006 rt2x00_rf(rt2x00dev, RF5392)) { 4007 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 4008 if (rt2x00_rf(rt2x00dev, RF3322)) { 4009 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M, 4010 conf_is_ht40(conf)); 4011 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M, 4012 conf_is_ht40(conf)); 4013 } else { 4014 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 4015 conf_is_ht40(conf)); 4016 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 4017 conf_is_ht40(conf)); 4018 } 4019 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 4020 4021 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 4022 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 4023 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 4024 } 4025 4026 /* 4027 * Change BBP settings 4028 */ 4029 4030 if (rt2x00_rt(rt2x00dev, RT3352)) { 4031 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4032 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4033 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4034 4035 rt2800_bbp_write(rt2x00dev, 27, 0x0); 4036 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 4037 rt2800_bbp_write(rt2x00dev, 27, 0x20); 4038 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 4039 rt2800_bbp_write(rt2x00dev, 86, 0x38); 4040 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 4041 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 4042 if (rf->channel > 14) { 4043 /* Disable CCK Packet detection on 5GHz */ 4044 rt2800_bbp_write(rt2x00dev, 70, 0x00); 4045 } else { 4046 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4047 } 4048 4049 if (conf_is_ht40(conf)) 4050 rt2800_bbp_write(rt2x00dev, 105, 0x04); 4051 else 4052 rt2800_bbp_write(rt2x00dev, 105, 0x34); 4053 4054 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4055 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4056 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4057 rt2800_bbp_write(rt2x00dev, 77, 0x98); 4058 } else if (rt2x00_rt(rt2x00dev, RT3883)) { 4059 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4060 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4061 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4062 4063 if (rt2x00dev->default_ant.rx_chain_num > 1) 4064 rt2800_bbp_write(rt2x00dev, 86, 0x46); 4065 else 4066 rt2800_bbp_write(rt2x00dev, 86, 0); 4067 } else { 4068 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4069 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4070 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4071 rt2800_bbp_write(rt2x00dev, 86, 0); 4072 } 4073 4074 if (rf->channel <= 14) { 4075 if (!rt2x00_rt(rt2x00dev, RT5390) && 4076 !rt2x00_rt(rt2x00dev, RT5392) && 4077 !rt2x00_rt(rt2x00dev, RT6352)) { 4078 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 4079 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4080 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4081 rt2800_bbp_write(rt2x00dev, 75, 0x46); 4082 } else { 4083 if (rt2x00_rt(rt2x00dev, RT3593)) 4084 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4085 else 4086 rt2800_bbp_write(rt2x00dev, 82, 0x84); 4087 rt2800_bbp_write(rt2x00dev, 75, 0x50); 4088 } 4089 if (rt2x00_rt(rt2x00dev, RT3593) || 4090 rt2x00_rt(rt2x00dev, RT3883)) 4091 rt2800_bbp_write(rt2x00dev, 83, 0x8a); 4092 } 4093 4094 } else { 4095 if (rt2x00_rt(rt2x00dev, RT3572)) 4096 rt2800_bbp_write(rt2x00dev, 82, 0x94); 4097 else if (rt2x00_rt(rt2x00dev, RT3593) || 4098 rt2x00_rt(rt2x00dev, RT3883)) 4099 rt2800_bbp_write(rt2x00dev, 82, 0x82); 4100 else if (!rt2x00_rt(rt2x00dev, RT6352)) 4101 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 4102 4103 if (rt2x00_rt(rt2x00dev, RT3593) || 4104 rt2x00_rt(rt2x00dev, RT3883)) 4105 rt2800_bbp_write(rt2x00dev, 83, 0x9a); 4106 4107 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) 4108 rt2800_bbp_write(rt2x00dev, 75, 0x46); 4109 else 4110 rt2800_bbp_write(rt2x00dev, 75, 0x50); 4111 } 4112 4113 reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG); 4114 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); 4115 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); 4116 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); 4117 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); 4118 4119 if (rt2x00_rt(rt2x00dev, RT3572)) 4120 rt2800_rfcsr_write(rt2x00dev, 8, 0); 4121 4122 if (rt2x00_rt(rt2x00dev, RT6352)) { 4123 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 4124 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); 4125 } else { 4126 tx_pin = 0; 4127 } 4128 4129 switch (rt2x00dev->default_ant.tx_chain_num) { 4130 case 3: 4131 /* Turn on tertiary PAs */ 4132 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 4133 rf->channel > 14); 4134 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 4135 rf->channel <= 14); 4136 /* fall-through */ 4137 case 2: 4138 /* Turn on secondary PAs */ 4139 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 4140 rf->channel > 14); 4141 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 4142 rf->channel <= 14); 4143 /* fall-through */ 4144 case 1: 4145 /* Turn on primary PAs */ 4146 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 4147 rf->channel > 14); 4148 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) 4149 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 4150 else 4151 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 4152 rf->channel <= 14); 4153 break; 4154 } 4155 4156 switch (rt2x00dev->default_ant.rx_chain_num) { 4157 case 3: 4158 /* Turn on tertiary LNAs */ 4159 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 4160 rf->channel > 14); 4161 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 4162 rf->channel <= 14); 4163 /* fall-through */ 4164 case 2: 4165 /* Turn on secondary LNAs */ 4166 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 4167 rf->channel > 14); 4168 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 4169 rf->channel <= 14); 4170 /* fall-through */ 4171 case 1: 4172 /* Turn on primary LNAs */ 4173 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 4174 rf->channel > 14); 4175 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 4176 rf->channel <= 14); 4177 break; 4178 } 4179 4180 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); 4181 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); 4182 4183 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 4184 4185 if (rt2x00_rt(rt2x00dev, RT3572)) { 4186 rt2800_rfcsr_write(rt2x00dev, 8, 0x80); 4187 4188 /* AGC init */ 4189 if (rf->channel <= 14) 4190 reg = 0x1c + (2 * rt2x00dev->lna_gain); 4191 else 4192 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 4193 4194 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4195 } 4196 4197 if (rt2x00_rt(rt2x00dev, RT3593)) { 4198 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 4199 4200 /* Band selection */ 4201 if (rt2x00_is_usb(rt2x00dev) || 4202 rt2x00_is_pcie(rt2x00dev)) { 4203 /* GPIO #8 controls all paths */ 4204 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); 4205 if (rf->channel <= 14) 4206 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); 4207 else 4208 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); 4209 } 4210 4211 /* LNA PE control. */ 4212 if (rt2x00_is_usb(rt2x00dev)) { 4213 /* GPIO #4 controls PE0 and PE1, 4214 * GPIO #7 controls PE2 4215 */ 4216 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 4217 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 4218 4219 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 4220 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 4221 } else if (rt2x00_is_pcie(rt2x00dev)) { 4222 /* GPIO #4 controls PE0, PE1 and PE2 */ 4223 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 4224 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 4225 } 4226 4227 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 4228 4229 /* AGC init */ 4230 if (rf->channel <= 14) 4231 reg = 0x1c + 2 * rt2x00dev->lna_gain; 4232 else 4233 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 4234 4235 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4236 4237 usleep_range(1000, 1500); 4238 } 4239 4240 if (rt2x00_rt(rt2x00dev, RT3883)) { 4241 if (!conf_is_ht40(conf)) 4242 rt2800_bbp_write(rt2x00dev, 105, 0x34); 4243 else 4244 rt2800_bbp_write(rt2x00dev, 105, 0x04); 4245 4246 /* AGC init */ 4247 if (rf->channel <= 14) 4248 reg = 0x2e + rt2x00dev->lna_gain; 4249 else 4250 reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3); 4251 4252 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4253 4254 usleep_range(1000, 1500); 4255 } 4256 4257 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) { 4258 reg = 0x10; 4259 if (!conf_is_ht40(conf)) { 4260 if (rt2x00_rt(rt2x00dev, RT6352) && 4261 rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 4262 reg |= 0x5; 4263 } else { 4264 reg |= 0xa; 4265 } 4266 } 4267 rt2800_bbp_write(rt2x00dev, 195, 141); 4268 rt2800_bbp_write(rt2x00dev, 196, reg); 4269 4270 /* AGC init. 4271 * Despite the vendor driver using different values here for 4272 * RT6352 chip, we use 0x1c for now. This may have to be changed 4273 * once TSSI got implemented. 4274 */ 4275 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain; 4276 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4277 4278 rt2800_iq_calibrate(rt2x00dev, rf->channel); 4279 } 4280 4281 bbp = rt2800_bbp_read(rt2x00dev, 4); 4282 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 4283 rt2800_bbp_write(rt2x00dev, 4, bbp); 4284 4285 bbp = rt2800_bbp_read(rt2x00dev, 3); 4286 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); 4287 rt2800_bbp_write(rt2x00dev, 3, bbp); 4288 4289 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 4290 if (conf_is_ht40(conf)) { 4291 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 4292 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4293 rt2800_bbp_write(rt2x00dev, 73, 0x16); 4294 } else { 4295 rt2800_bbp_write(rt2x00dev, 69, 0x16); 4296 rt2800_bbp_write(rt2x00dev, 70, 0x08); 4297 rt2800_bbp_write(rt2x00dev, 73, 0x11); 4298 } 4299 } 4300 4301 usleep_range(1000, 1500); 4302 4303 /* 4304 * Clear channel statistic counters 4305 */ 4306 reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 4307 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 4308 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 4309 4310 /* 4311 * Clear update flag 4312 */ 4313 if (rt2x00_rt(rt2x00dev, RT3352) || 4314 rt2x00_rt(rt2x00dev, RT5350)) { 4315 bbp = rt2800_bbp_read(rt2x00dev, 49); 4316 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0); 4317 rt2800_bbp_write(rt2x00dev, 49, bbp); 4318 } 4319 } 4320 4321 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) 4322 { 4323 u8 tssi_bounds[9]; 4324 u8 current_tssi; 4325 u16 eeprom; 4326 u8 step; 4327 int i; 4328 4329 /* 4330 * First check if temperature compensation is supported. 4331 */ 4332 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 4333 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC)) 4334 return 0; 4335 4336 /* 4337 * Read TSSI boundaries for temperature compensation from 4338 * the EEPROM. 4339 * 4340 * Array idx 0 1 2 3 4 5 6 7 8 4341 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4 4342 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 4343 */ 4344 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 4345 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1); 4346 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4347 EEPROM_TSSI_BOUND_BG1_MINUS4); 4348 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4349 EEPROM_TSSI_BOUND_BG1_MINUS3); 4350 4351 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2); 4352 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4353 EEPROM_TSSI_BOUND_BG2_MINUS2); 4354 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4355 EEPROM_TSSI_BOUND_BG2_MINUS1); 4356 4357 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3); 4358 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4359 EEPROM_TSSI_BOUND_BG3_REF); 4360 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4361 EEPROM_TSSI_BOUND_BG3_PLUS1); 4362 4363 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4); 4364 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4365 EEPROM_TSSI_BOUND_BG4_PLUS2); 4366 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4367 EEPROM_TSSI_BOUND_BG4_PLUS3); 4368 4369 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5); 4370 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4371 EEPROM_TSSI_BOUND_BG5_PLUS4); 4372 4373 step = rt2x00_get_field16(eeprom, 4374 EEPROM_TSSI_BOUND_BG5_AGC_STEP); 4375 } else { 4376 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1); 4377 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4378 EEPROM_TSSI_BOUND_A1_MINUS4); 4379 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4380 EEPROM_TSSI_BOUND_A1_MINUS3); 4381 4382 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2); 4383 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4384 EEPROM_TSSI_BOUND_A2_MINUS2); 4385 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4386 EEPROM_TSSI_BOUND_A2_MINUS1); 4387 4388 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3); 4389 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4390 EEPROM_TSSI_BOUND_A3_REF); 4391 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4392 EEPROM_TSSI_BOUND_A3_PLUS1); 4393 4394 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4); 4395 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4396 EEPROM_TSSI_BOUND_A4_PLUS2); 4397 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4398 EEPROM_TSSI_BOUND_A4_PLUS3); 4399 4400 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5); 4401 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4402 EEPROM_TSSI_BOUND_A5_PLUS4); 4403 4404 step = rt2x00_get_field16(eeprom, 4405 EEPROM_TSSI_BOUND_A5_AGC_STEP); 4406 } 4407 4408 /* 4409 * Check if temperature compensation is supported. 4410 */ 4411 if (tssi_bounds[4] == 0xff || step == 0xff) 4412 return 0; 4413 4414 /* 4415 * Read current TSSI (BBP 49). 4416 */ 4417 current_tssi = rt2800_bbp_read(rt2x00dev, 49); 4418 4419 /* 4420 * Compare TSSI value (BBP49) with the compensation boundaries 4421 * from the EEPROM and increase or decrease tx power. 4422 */ 4423 for (i = 0; i <= 3; i++) { 4424 if (current_tssi > tssi_bounds[i]) 4425 break; 4426 } 4427 4428 if (i == 4) { 4429 for (i = 8; i >= 5; i--) { 4430 if (current_tssi < tssi_bounds[i]) 4431 break; 4432 } 4433 } 4434 4435 return (i - 4) * step; 4436 } 4437 4438 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, 4439 enum nl80211_band band) 4440 { 4441 u16 eeprom; 4442 u8 comp_en; 4443 u8 comp_type; 4444 int comp_value = 0; 4445 4446 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA); 4447 4448 /* 4449 * HT40 compensation not required. 4450 */ 4451 if (eeprom == 0xffff || 4452 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4453 return 0; 4454 4455 if (band == NL80211_BAND_2GHZ) { 4456 comp_en = rt2x00_get_field16(eeprom, 4457 EEPROM_TXPOWER_DELTA_ENABLE_2G); 4458 if (comp_en) { 4459 comp_type = rt2x00_get_field16(eeprom, 4460 EEPROM_TXPOWER_DELTA_TYPE_2G); 4461 comp_value = rt2x00_get_field16(eeprom, 4462 EEPROM_TXPOWER_DELTA_VALUE_2G); 4463 if (!comp_type) 4464 comp_value = -comp_value; 4465 } 4466 } else { 4467 comp_en = rt2x00_get_field16(eeprom, 4468 EEPROM_TXPOWER_DELTA_ENABLE_5G); 4469 if (comp_en) { 4470 comp_type = rt2x00_get_field16(eeprom, 4471 EEPROM_TXPOWER_DELTA_TYPE_5G); 4472 comp_value = rt2x00_get_field16(eeprom, 4473 EEPROM_TXPOWER_DELTA_VALUE_5G); 4474 if (!comp_type) 4475 comp_value = -comp_value; 4476 } 4477 } 4478 4479 return comp_value; 4480 } 4481 4482 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev, 4483 int power_level, int max_power) 4484 { 4485 int delta; 4486 4487 if (rt2x00_has_cap_power_limit(rt2x00dev)) 4488 return 0; 4489 4490 /* 4491 * XXX: We don't know the maximum transmit power of our hardware since 4492 * the EEPROM doesn't expose it. We only know that we are calibrated 4493 * to 100% tx power. 4494 * 4495 * Hence, we assume the regulatory limit that cfg80211 calulated for 4496 * the current channel is our maximum and if we are requested to lower 4497 * the value we just reduce our tx power accordingly. 4498 */ 4499 delta = power_level - max_power; 4500 return min(delta, 0); 4501 } 4502 4503 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, 4504 enum nl80211_band band, int power_level, 4505 u8 txpower, int delta) 4506 { 4507 u16 eeprom; 4508 u8 criterion; 4509 u8 eirp_txpower; 4510 u8 eirp_txpower_criterion; 4511 u8 reg_limit; 4512 4513 if (rt2x00_rt(rt2x00dev, RT3593)) 4514 return min_t(u8, txpower, 0xc); 4515 4516 if (rt2x00_rt(rt2x00dev, RT3883)) 4517 return min_t(u8, txpower, 0xf); 4518 4519 if (rt2x00_has_cap_power_limit(rt2x00dev)) { 4520 /* 4521 * Check if eirp txpower exceed txpower_limit. 4522 * We use OFDM 6M as criterion and its eirp txpower 4523 * is stored at EEPROM_EIRP_MAX_TX_POWER. 4524 * .11b data rate need add additional 4dbm 4525 * when calculating eirp txpower. 4526 */ 4527 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4528 EEPROM_TXPOWER_BYRATE, 4529 1); 4530 criterion = rt2x00_get_field16(eeprom, 4531 EEPROM_TXPOWER_BYRATE_RATE0); 4532 4533 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 4534 4535 if (band == NL80211_BAND_2GHZ) 4536 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4537 EEPROM_EIRP_MAX_TX_POWER_2GHZ); 4538 else 4539 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4540 EEPROM_EIRP_MAX_TX_POWER_5GHZ); 4541 4542 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) + 4543 (is_rate_b ? 4 : 0) + delta; 4544 4545 reg_limit = (eirp_txpower > power_level) ? 4546 (eirp_txpower - power_level) : 0; 4547 } else 4548 reg_limit = 0; 4549 4550 txpower = max(0, txpower + delta - reg_limit); 4551 return min_t(u8, txpower, 0xc); 4552 } 4553 4554 4555 enum { 4556 TX_PWR_CFG_0_IDX, 4557 TX_PWR_CFG_1_IDX, 4558 TX_PWR_CFG_2_IDX, 4559 TX_PWR_CFG_3_IDX, 4560 TX_PWR_CFG_4_IDX, 4561 TX_PWR_CFG_5_IDX, 4562 TX_PWR_CFG_6_IDX, 4563 TX_PWR_CFG_7_IDX, 4564 TX_PWR_CFG_8_IDX, 4565 TX_PWR_CFG_9_IDX, 4566 TX_PWR_CFG_0_EXT_IDX, 4567 TX_PWR_CFG_1_EXT_IDX, 4568 TX_PWR_CFG_2_EXT_IDX, 4569 TX_PWR_CFG_3_EXT_IDX, 4570 TX_PWR_CFG_4_EXT_IDX, 4571 TX_PWR_CFG_IDX_COUNT, 4572 }; 4573 4574 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, 4575 struct ieee80211_channel *chan, 4576 int power_level) 4577 { 4578 u8 txpower; 4579 u16 eeprom; 4580 u32 regs[TX_PWR_CFG_IDX_COUNT]; 4581 unsigned int offset; 4582 enum nl80211_band band = chan->band; 4583 int delta; 4584 int i; 4585 4586 memset(regs, '\0', sizeof(regs)); 4587 4588 /* TODO: adapt TX power reduction from the rt28xx code */ 4589 4590 /* calculate temperature compensation delta */ 4591 delta = rt2800_get_gain_calibration_delta(rt2x00dev); 4592 4593 if (band == NL80211_BAND_5GHZ) 4594 offset = 16; 4595 else 4596 offset = 0; 4597 4598 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4599 offset += 8; 4600 4601 /* read the next four txpower values */ 4602 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4603 offset); 4604 4605 /* CCK 1MBS,2MBS */ 4606 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4607 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4608 txpower, delta); 4609 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4610 TX_PWR_CFG_0_CCK1_CH0, txpower); 4611 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4612 TX_PWR_CFG_0_CCK1_CH1, txpower); 4613 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4614 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower); 4615 4616 /* CCK 5.5MBS,11MBS */ 4617 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4618 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4619 txpower, delta); 4620 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4621 TX_PWR_CFG_0_CCK5_CH0, txpower); 4622 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4623 TX_PWR_CFG_0_CCK5_CH1, txpower); 4624 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4625 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower); 4626 4627 /* OFDM 6MBS,9MBS */ 4628 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4629 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4630 txpower, delta); 4631 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4632 TX_PWR_CFG_0_OFDM6_CH0, txpower); 4633 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4634 TX_PWR_CFG_0_OFDM6_CH1, txpower); 4635 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4636 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower); 4637 4638 /* OFDM 12MBS,18MBS */ 4639 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4640 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4641 txpower, delta); 4642 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4643 TX_PWR_CFG_0_OFDM12_CH0, txpower); 4644 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4645 TX_PWR_CFG_0_OFDM12_CH1, txpower); 4646 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4647 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower); 4648 4649 /* read the next four txpower values */ 4650 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4651 offset + 1); 4652 4653 /* OFDM 24MBS,36MBS */ 4654 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4655 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4656 txpower, delta); 4657 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4658 TX_PWR_CFG_1_OFDM24_CH0, txpower); 4659 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4660 TX_PWR_CFG_1_OFDM24_CH1, txpower); 4661 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4662 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower); 4663 4664 /* OFDM 48MBS */ 4665 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4666 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4667 txpower, delta); 4668 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4669 TX_PWR_CFG_1_OFDM48_CH0, txpower); 4670 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4671 TX_PWR_CFG_1_OFDM48_CH1, txpower); 4672 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4673 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower); 4674 4675 /* OFDM 54MBS */ 4676 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4677 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4678 txpower, delta); 4679 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4680 TX_PWR_CFG_7_OFDM54_CH0, txpower); 4681 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4682 TX_PWR_CFG_7_OFDM54_CH1, txpower); 4683 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4684 TX_PWR_CFG_7_OFDM54_CH2, txpower); 4685 4686 /* read the next four txpower values */ 4687 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4688 offset + 2); 4689 4690 /* MCS 0,1 */ 4691 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4692 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4693 txpower, delta); 4694 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4695 TX_PWR_CFG_1_MCS0_CH0, txpower); 4696 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4697 TX_PWR_CFG_1_MCS0_CH1, txpower); 4698 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4699 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower); 4700 4701 /* MCS 2,3 */ 4702 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4703 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4704 txpower, delta); 4705 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4706 TX_PWR_CFG_1_MCS2_CH0, txpower); 4707 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4708 TX_PWR_CFG_1_MCS2_CH1, txpower); 4709 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4710 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower); 4711 4712 /* MCS 4,5 */ 4713 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4714 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4715 txpower, delta); 4716 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4717 TX_PWR_CFG_2_MCS4_CH0, txpower); 4718 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4719 TX_PWR_CFG_2_MCS4_CH1, txpower); 4720 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4721 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower); 4722 4723 /* MCS 6 */ 4724 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4725 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4726 txpower, delta); 4727 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4728 TX_PWR_CFG_2_MCS6_CH0, txpower); 4729 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4730 TX_PWR_CFG_2_MCS6_CH1, txpower); 4731 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4732 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower); 4733 4734 /* read the next four txpower values */ 4735 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4736 offset + 3); 4737 4738 /* MCS 7 */ 4739 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4740 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4741 txpower, delta); 4742 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4743 TX_PWR_CFG_7_MCS7_CH0, txpower); 4744 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4745 TX_PWR_CFG_7_MCS7_CH1, txpower); 4746 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4747 TX_PWR_CFG_7_MCS7_CH2, txpower); 4748 4749 /* MCS 8,9 */ 4750 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4751 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4752 txpower, delta); 4753 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4754 TX_PWR_CFG_2_MCS8_CH0, txpower); 4755 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4756 TX_PWR_CFG_2_MCS8_CH1, txpower); 4757 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4758 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower); 4759 4760 /* MCS 10,11 */ 4761 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4762 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4763 txpower, delta); 4764 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4765 TX_PWR_CFG_2_MCS10_CH0, txpower); 4766 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4767 TX_PWR_CFG_2_MCS10_CH1, txpower); 4768 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4769 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower); 4770 4771 /* MCS 12,13 */ 4772 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4773 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4774 txpower, delta); 4775 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4776 TX_PWR_CFG_3_MCS12_CH0, txpower); 4777 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4778 TX_PWR_CFG_3_MCS12_CH1, txpower); 4779 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4780 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower); 4781 4782 /* read the next four txpower values */ 4783 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4784 offset + 4); 4785 4786 /* MCS 14 */ 4787 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4788 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4789 txpower, delta); 4790 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4791 TX_PWR_CFG_3_MCS14_CH0, txpower); 4792 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4793 TX_PWR_CFG_3_MCS14_CH1, txpower); 4794 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4795 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower); 4796 4797 /* MCS 15 */ 4798 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4799 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4800 txpower, delta); 4801 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4802 TX_PWR_CFG_8_MCS15_CH0, txpower); 4803 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4804 TX_PWR_CFG_8_MCS15_CH1, txpower); 4805 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4806 TX_PWR_CFG_8_MCS15_CH2, txpower); 4807 4808 /* MCS 16,17 */ 4809 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4810 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4811 txpower, delta); 4812 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4813 TX_PWR_CFG_5_MCS16_CH0, txpower); 4814 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4815 TX_PWR_CFG_5_MCS16_CH1, txpower); 4816 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4817 TX_PWR_CFG_5_MCS16_CH2, txpower); 4818 4819 /* MCS 18,19 */ 4820 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4821 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4822 txpower, delta); 4823 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4824 TX_PWR_CFG_5_MCS18_CH0, txpower); 4825 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4826 TX_PWR_CFG_5_MCS18_CH1, txpower); 4827 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4828 TX_PWR_CFG_5_MCS18_CH2, txpower); 4829 4830 /* read the next four txpower values */ 4831 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4832 offset + 5); 4833 4834 /* MCS 20,21 */ 4835 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4836 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4837 txpower, delta); 4838 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4839 TX_PWR_CFG_6_MCS20_CH0, txpower); 4840 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4841 TX_PWR_CFG_6_MCS20_CH1, txpower); 4842 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4843 TX_PWR_CFG_6_MCS20_CH2, txpower); 4844 4845 /* MCS 22 */ 4846 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4847 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4848 txpower, delta); 4849 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4850 TX_PWR_CFG_6_MCS22_CH0, txpower); 4851 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4852 TX_PWR_CFG_6_MCS22_CH1, txpower); 4853 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4854 TX_PWR_CFG_6_MCS22_CH2, txpower); 4855 4856 /* MCS 23 */ 4857 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4858 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4859 txpower, delta); 4860 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4861 TX_PWR_CFG_8_MCS23_CH0, txpower); 4862 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4863 TX_PWR_CFG_8_MCS23_CH1, txpower); 4864 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4865 TX_PWR_CFG_8_MCS23_CH2, txpower); 4866 4867 /* read the next four txpower values */ 4868 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4869 offset + 6); 4870 4871 /* STBC, MCS 0,1 */ 4872 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4873 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4874 txpower, delta); 4875 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4876 TX_PWR_CFG_3_STBC0_CH0, txpower); 4877 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4878 TX_PWR_CFG_3_STBC0_CH1, txpower); 4879 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4880 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower); 4881 4882 /* STBC, MCS 2,3 */ 4883 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4884 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4885 txpower, delta); 4886 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4887 TX_PWR_CFG_3_STBC2_CH0, txpower); 4888 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4889 TX_PWR_CFG_3_STBC2_CH1, txpower); 4890 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4891 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower); 4892 4893 /* STBC, MCS 4,5 */ 4894 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4895 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4896 txpower, delta); 4897 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); 4898 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); 4899 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, 4900 txpower); 4901 4902 /* STBC, MCS 6 */ 4903 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4904 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4905 txpower, delta); 4906 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); 4907 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); 4908 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, 4909 txpower); 4910 4911 /* read the next four txpower values */ 4912 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4913 offset + 7); 4914 4915 /* STBC, MCS 7 */ 4916 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4917 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4918 txpower, delta); 4919 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4920 TX_PWR_CFG_9_STBC7_CH0, txpower); 4921 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4922 TX_PWR_CFG_9_STBC7_CH1, txpower); 4923 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4924 TX_PWR_CFG_9_STBC7_CH2, txpower); 4925 4926 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]); 4927 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]); 4928 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]); 4929 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]); 4930 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]); 4931 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]); 4932 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]); 4933 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]); 4934 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]); 4935 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]); 4936 4937 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT, 4938 regs[TX_PWR_CFG_0_EXT_IDX]); 4939 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT, 4940 regs[TX_PWR_CFG_1_EXT_IDX]); 4941 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT, 4942 regs[TX_PWR_CFG_2_EXT_IDX]); 4943 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT, 4944 regs[TX_PWR_CFG_3_EXT_IDX]); 4945 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT, 4946 regs[TX_PWR_CFG_4_EXT_IDX]); 4947 4948 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++) 4949 rt2x00_dbg(rt2x00dev, 4950 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n", 4951 (band == NL80211_BAND_5GHZ) ? '5' : '2', 4952 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ? 4953 '4' : '2', 4954 (i > TX_PWR_CFG_9_IDX) ? 4955 (i - TX_PWR_CFG_9_IDX - 1) : i, 4956 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "", 4957 (unsigned long) regs[i]); 4958 } 4959 4960 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev, 4961 struct ieee80211_channel *chan, 4962 int power_level) 4963 { 4964 u32 reg, pwreg; 4965 u16 eeprom; 4966 u32 data, gdata; 4967 u8 t, i; 4968 enum nl80211_band band = chan->band; 4969 int delta; 4970 4971 /* Warn user if bw_comp is set in EEPROM */ 4972 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 4973 4974 if (delta) 4975 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n", 4976 delta); 4977 4978 /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit 4979 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor 4980 * driver does as well, though it looks kinda wrong. 4981 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe 4982 * the hardware has a problem handling 0x20, and as the code initially 4983 * used a fixed offset between HT20 and HT40 rates they had to work- 4984 * around that issue and most likely just forgot about it later on. 4985 * Maybe we should use rt2800_get_txpower_bw_comp() here as well, 4986 * however, the corresponding EEPROM value is not respected by the 4987 * vendor driver, so maybe this is rather being taken care of the 4988 * TXALC and the driver doesn't need to handle it...? 4989 * Though this is all very awkward, just do as they did, as that's what 4990 * board vendors expected when they populated the EEPROM... 4991 */ 4992 for (i = 0; i < 5; i++) { 4993 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4994 EEPROM_TXPOWER_BYRATE, 4995 i * 2); 4996 4997 data = eeprom; 4998 4999 t = eeprom & 0x3f; 5000 if (t == 32) 5001 t++; 5002 5003 gdata = t; 5004 5005 t = (eeprom & 0x3f00) >> 8; 5006 if (t == 32) 5007 t++; 5008 5009 gdata |= (t << 8); 5010 5011 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5012 EEPROM_TXPOWER_BYRATE, 5013 (i * 2) + 1); 5014 5015 t = eeprom & 0x3f; 5016 if (t == 32) 5017 t++; 5018 5019 gdata |= (t << 16); 5020 5021 t = (eeprom & 0x3f00) >> 8; 5022 if (t == 32) 5023 t++; 5024 5025 gdata |= (t << 24); 5026 data |= (eeprom << 16); 5027 5028 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) { 5029 /* HT20 */ 5030 if (data != 0xffffffff) 5031 rt2800_register_write(rt2x00dev, 5032 TX_PWR_CFG_0 + (i * 4), 5033 data); 5034 } else { 5035 /* HT40 */ 5036 if (gdata != 0xffffffff) 5037 rt2800_register_write(rt2x00dev, 5038 TX_PWR_CFG_0 + (i * 4), 5039 gdata); 5040 } 5041 } 5042 5043 /* Aparently Ralink ran out of space in the BYRATE calibration section 5044 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x 5045 * registers. As recent 2T chips use 8-bit instead of 4-bit values for 5046 * power-offsets more space would be needed. Ralink decided to keep the 5047 * EEPROM layout untouched and rather have some shared values covering 5048 * multiple bitrates. 5049 * Populate the registers not covered by the EEPROM in the same way the 5050 * vendor driver does. 5051 */ 5052 5053 /* For OFDM 54MBS use value from OFDM 48MBS */ 5054 pwreg = 0; 5055 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1); 5056 t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS); 5057 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t); 5058 5059 /* For MCS 7 use value from MCS 6 */ 5060 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2); 5061 t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7); 5062 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t); 5063 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg); 5064 5065 /* For MCS 15 use value from MCS 14 */ 5066 pwreg = 0; 5067 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3); 5068 t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14); 5069 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t); 5070 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg); 5071 5072 /* For STBC MCS 7 use value from STBC MCS 6 */ 5073 pwreg = 0; 5074 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4); 5075 t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6); 5076 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); 5077 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg); 5078 5079 rt2800_config_alc(rt2x00dev, chan, power_level); 5080 5081 /* TODO: temperature compensation code! */ 5082 } 5083 5084 /* 5085 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and 5086 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values, 5087 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power 5088 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm. 5089 * Reference per rate transmit power values are located in the EEPROM at 5090 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to 5091 * current conditions (i.e. band, bandwidth, temperature, user settings). 5092 */ 5093 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, 5094 struct ieee80211_channel *chan, 5095 int power_level) 5096 { 5097 u8 txpower, r1; 5098 u16 eeprom; 5099 u32 reg, offset; 5100 int i, is_rate_b, delta, power_ctrl; 5101 enum nl80211_band band = chan->band; 5102 5103 /* 5104 * Calculate HT40 compensation. For 40MHz we need to add or subtract 5105 * value read from EEPROM (different for 2GHz and for 5GHz). 5106 */ 5107 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 5108 5109 /* 5110 * Calculate temperature compensation. Depends on measurement of current 5111 * TSSI (Transmitter Signal Strength Indication) we know TX power (due 5112 * to temperature or maybe other factors) is smaller or bigger than 5113 * expected. We adjust it, based on TSSI reference and boundaries values 5114 * provided in EEPROM. 5115 */ 5116 switch (rt2x00dev->chip.rt) { 5117 case RT2860: 5118 case RT2872: 5119 case RT2883: 5120 case RT3070: 5121 case RT3071: 5122 case RT3090: 5123 case RT3572: 5124 delta += rt2800_get_gain_calibration_delta(rt2x00dev); 5125 break; 5126 default: 5127 /* TODO: temperature compensation code for other chips. */ 5128 break; 5129 } 5130 5131 /* 5132 * Decrease power according to user settings, on devices with unknown 5133 * maximum tx power. For other devices we take user power_level into 5134 * consideration on rt2800_compensate_txpower(). 5135 */ 5136 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level, 5137 chan->max_power); 5138 5139 /* 5140 * BBP_R1 controls TX power for all rates, it allow to set the following 5141 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively. 5142 * 5143 * TODO: we do not use +6 dBm option to do not increase power beyond 5144 * regulatory limit, however this could be utilized for devices with 5145 * CAPABILITY_POWER_LIMIT. 5146 */ 5147 if (delta <= -12) { 5148 power_ctrl = 2; 5149 delta += 12; 5150 } else if (delta <= -6) { 5151 power_ctrl = 1; 5152 delta += 6; 5153 } else { 5154 power_ctrl = 0; 5155 } 5156 r1 = rt2800_bbp_read(rt2x00dev, 1); 5157 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl); 5158 rt2800_bbp_write(rt2x00dev, 1, r1); 5159 5160 offset = TX_PWR_CFG_0; 5161 5162 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { 5163 /* just to be safe */ 5164 if (offset > TX_PWR_CFG_4) 5165 break; 5166 5167 reg = rt2800_register_read(rt2x00dev, offset); 5168 5169 /* read the next four txpower values */ 5170 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5171 EEPROM_TXPOWER_BYRATE, 5172 i); 5173 5174 is_rate_b = i ? 0 : 1; 5175 /* 5176 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, 5177 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, 5178 * TX_PWR_CFG_4: unknown 5179 */ 5180 txpower = rt2x00_get_field16(eeprom, 5181 EEPROM_TXPOWER_BYRATE_RATE0); 5182 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5183 power_level, txpower, delta); 5184 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); 5185 5186 /* 5187 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, 5188 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, 5189 * TX_PWR_CFG_4: unknown 5190 */ 5191 txpower = rt2x00_get_field16(eeprom, 5192 EEPROM_TXPOWER_BYRATE_RATE1); 5193 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5194 power_level, txpower, delta); 5195 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); 5196 5197 /* 5198 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS, 5199 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, 5200 * TX_PWR_CFG_4: unknown 5201 */ 5202 txpower = rt2x00_get_field16(eeprom, 5203 EEPROM_TXPOWER_BYRATE_RATE2); 5204 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5205 power_level, txpower, delta); 5206 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); 5207 5208 /* 5209 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, 5210 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, 5211 * TX_PWR_CFG_4: unknown 5212 */ 5213 txpower = rt2x00_get_field16(eeprom, 5214 EEPROM_TXPOWER_BYRATE_RATE3); 5215 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5216 power_level, txpower, delta); 5217 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); 5218 5219 /* read the next four txpower values */ 5220 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5221 EEPROM_TXPOWER_BYRATE, 5222 i + 1); 5223 5224 is_rate_b = 0; 5225 /* 5226 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, 5227 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, 5228 * TX_PWR_CFG_4: unknown 5229 */ 5230 txpower = rt2x00_get_field16(eeprom, 5231 EEPROM_TXPOWER_BYRATE_RATE0); 5232 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5233 power_level, txpower, delta); 5234 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); 5235 5236 /* 5237 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, 5238 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, 5239 * TX_PWR_CFG_4: unknown 5240 */ 5241 txpower = rt2x00_get_field16(eeprom, 5242 EEPROM_TXPOWER_BYRATE_RATE1); 5243 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5244 power_level, txpower, delta); 5245 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); 5246 5247 /* 5248 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, 5249 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, 5250 * TX_PWR_CFG_4: unknown 5251 */ 5252 txpower = rt2x00_get_field16(eeprom, 5253 EEPROM_TXPOWER_BYRATE_RATE2); 5254 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5255 power_level, txpower, delta); 5256 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); 5257 5258 /* 5259 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, 5260 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, 5261 * TX_PWR_CFG_4: unknown 5262 */ 5263 txpower = rt2x00_get_field16(eeprom, 5264 EEPROM_TXPOWER_BYRATE_RATE3); 5265 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5266 power_level, txpower, delta); 5267 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); 5268 5269 rt2800_register_write(rt2x00dev, offset, reg); 5270 5271 /* next TX_PWR_CFG register */ 5272 offset += 4; 5273 } 5274 } 5275 5276 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, 5277 struct ieee80211_channel *chan, 5278 int power_level) 5279 { 5280 if (rt2x00_rt(rt2x00dev, RT3593) || 5281 rt2x00_rt(rt2x00dev, RT3883)) 5282 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level); 5283 else if (rt2x00_rt(rt2x00dev, RT6352)) 5284 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level); 5285 else 5286 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level); 5287 } 5288 5289 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) 5290 { 5291 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan, 5292 rt2x00dev->tx_power); 5293 } 5294 EXPORT_SYMBOL_GPL(rt2800_gain_calibration); 5295 5296 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) 5297 { 5298 u32 tx_pin; 5299 u8 rfcsr; 5300 unsigned long min_sleep = 0; 5301 5302 /* 5303 * A voltage-controlled oscillator(VCO) is an electronic oscillator 5304 * designed to be controlled in oscillation frequency by a voltage 5305 * input. Maybe the temperature will affect the frequency of 5306 * oscillation to be shifted. The VCO calibration will be called 5307 * periodically to adjust the frequency to be precision. 5308 */ 5309 5310 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5311 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE; 5312 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5313 5314 switch (rt2x00dev->chip.rf) { 5315 case RF2020: 5316 case RF3020: 5317 case RF3021: 5318 case RF3022: 5319 case RF3320: 5320 case RF3052: 5321 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 5322 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 5323 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 5324 break; 5325 case RF3053: 5326 case RF3070: 5327 case RF3290: 5328 case RF3853: 5329 case RF5350: 5330 case RF5360: 5331 case RF5362: 5332 case RF5370: 5333 case RF5372: 5334 case RF5390: 5335 case RF5392: 5336 case RF5592: 5337 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 5338 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 5339 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 5340 min_sleep = 1000; 5341 break; 5342 case RF7620: 5343 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 5344 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 5345 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4); 5346 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1); 5347 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr); 5348 min_sleep = 2000; 5349 break; 5350 default: 5351 WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration", 5352 rt2x00dev->chip.rf); 5353 return; 5354 } 5355 5356 if (min_sleep > 0) 5357 usleep_range(min_sleep, min_sleep * 2); 5358 5359 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5360 if (rt2x00dev->rf_channel <= 14) { 5361 switch (rt2x00dev->default_ant.tx_chain_num) { 5362 case 3: 5363 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); 5364 /* fall through */ 5365 case 2: 5366 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 5367 /* fall through */ 5368 case 1: 5369 default: 5370 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 5371 break; 5372 } 5373 } else { 5374 switch (rt2x00dev->default_ant.tx_chain_num) { 5375 case 3: 5376 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); 5377 /* fall through */ 5378 case 2: 5379 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 5380 /* fall through */ 5381 case 1: 5382 default: 5383 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); 5384 break; 5385 } 5386 } 5387 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5388 5389 if (rt2x00_rt(rt2x00dev, RT6352)) { 5390 if (rt2x00dev->default_ant.rx_chain_num == 1) { 5391 rt2800_bbp_write(rt2x00dev, 91, 0x07); 5392 rt2800_bbp_write(rt2x00dev, 95, 0x1A); 5393 rt2800_bbp_write(rt2x00dev, 195, 128); 5394 rt2800_bbp_write(rt2x00dev, 196, 0xA0); 5395 rt2800_bbp_write(rt2x00dev, 195, 170); 5396 rt2800_bbp_write(rt2x00dev, 196, 0x12); 5397 rt2800_bbp_write(rt2x00dev, 195, 171); 5398 rt2800_bbp_write(rt2x00dev, 196, 0x10); 5399 } else { 5400 rt2800_bbp_write(rt2x00dev, 91, 0x06); 5401 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 5402 rt2800_bbp_write(rt2x00dev, 195, 128); 5403 rt2800_bbp_write(rt2x00dev, 196, 0xE0); 5404 rt2800_bbp_write(rt2x00dev, 195, 170); 5405 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5406 rt2800_bbp_write(rt2x00dev, 195, 171); 5407 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5408 } 5409 5410 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 5411 rt2800_bbp_write(rt2x00dev, 75, 0x68); 5412 rt2800_bbp_write(rt2x00dev, 76, 0x4C); 5413 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 5414 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 5415 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 5416 } 5417 5418 /* On 11A, We should delay and wait RF/BBP to be stable 5419 * and the appropriate time should be 1000 micro seconds 5420 * 2005/06/05 - On 11G, we also need this delay time. 5421 * Otherwise it's difficult to pass the WHQL. 5422 */ 5423 usleep_range(1000, 1500); 5424 } 5425 } 5426 EXPORT_SYMBOL_GPL(rt2800_vco_calibration); 5427 5428 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, 5429 struct rt2x00lib_conf *libconf) 5430 { 5431 u32 reg; 5432 5433 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 5434 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 5435 libconf->conf->short_frame_max_tx_count); 5436 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 5437 libconf->conf->long_frame_max_tx_count); 5438 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5439 } 5440 5441 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, 5442 struct rt2x00lib_conf *libconf) 5443 { 5444 enum dev_state state = 5445 (libconf->conf->flags & IEEE80211_CONF_PS) ? 5446 STATE_SLEEP : STATE_AWAKE; 5447 u32 reg; 5448 5449 if (state == STATE_SLEEP) { 5450 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); 5451 5452 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5453 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); 5454 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 5455 libconf->conf->listen_interval - 1); 5456 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); 5457 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5458 5459 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5460 } else { 5461 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5462 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 5463 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 5464 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); 5465 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5466 5467 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5468 } 5469 } 5470 5471 void rt2800_config(struct rt2x00_dev *rt2x00dev, 5472 struct rt2x00lib_conf *libconf, 5473 const unsigned int flags) 5474 { 5475 /* Always recalculate LNA gain before changing configuration */ 5476 rt2800_config_lna_gain(rt2x00dev, libconf); 5477 5478 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { 5479 rt2800_config_channel(rt2x00dev, libconf->conf, 5480 &libconf->rf, &libconf->channel); 5481 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5482 libconf->conf->power_level); 5483 } 5484 if (flags & IEEE80211_CONF_CHANGE_POWER) 5485 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5486 libconf->conf->power_level); 5487 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 5488 rt2800_config_retry_limit(rt2x00dev, libconf); 5489 if (flags & IEEE80211_CONF_CHANGE_PS) 5490 rt2800_config_ps(rt2x00dev, libconf); 5491 } 5492 EXPORT_SYMBOL_GPL(rt2800_config); 5493 5494 /* 5495 * Link tuning 5496 */ 5497 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5498 { 5499 u32 reg; 5500 5501 /* 5502 * Update FCS error count from register. 5503 */ 5504 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 5505 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); 5506 } 5507 EXPORT_SYMBOL_GPL(rt2800_link_stats); 5508 5509 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 5510 { 5511 u8 vgc; 5512 5513 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 5514 if (rt2x00_rt(rt2x00dev, RT3070) || 5515 rt2x00_rt(rt2x00dev, RT3071) || 5516 rt2x00_rt(rt2x00dev, RT3090) || 5517 rt2x00_rt(rt2x00dev, RT3290) || 5518 rt2x00_rt(rt2x00dev, RT3390) || 5519 rt2x00_rt(rt2x00dev, RT3572) || 5520 rt2x00_rt(rt2x00dev, RT3593) || 5521 rt2x00_rt(rt2x00dev, RT5390) || 5522 rt2x00_rt(rt2x00dev, RT5392) || 5523 rt2x00_rt(rt2x00dev, RT5592) || 5524 rt2x00_rt(rt2x00dev, RT6352)) 5525 vgc = 0x1c + (2 * rt2x00dev->lna_gain); 5526 else 5527 vgc = 0x2e + rt2x00dev->lna_gain; 5528 } else { /* 5GHZ band */ 5529 if (rt2x00_rt(rt2x00dev, RT3593) || 5530 rt2x00_rt(rt2x00dev, RT3883)) 5531 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3; 5532 else if (rt2x00_rt(rt2x00dev, RT5592)) 5533 vgc = 0x24 + (2 * rt2x00dev->lna_gain); 5534 else { 5535 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 5536 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3; 5537 else 5538 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3; 5539 } 5540 } 5541 5542 return vgc; 5543 } 5544 5545 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, 5546 struct link_qual *qual, u8 vgc_level) 5547 { 5548 if (qual->vgc_level != vgc_level) { 5549 if (rt2x00_rt(rt2x00dev, RT3572) || 5550 rt2x00_rt(rt2x00dev, RT3593) || 5551 rt2x00_rt(rt2x00dev, RT3883)) { 5552 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, 5553 vgc_level); 5554 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5555 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a); 5556 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level); 5557 } else { 5558 rt2800_bbp_write(rt2x00dev, 66, vgc_level); 5559 } 5560 5561 qual->vgc_level = vgc_level; 5562 qual->vgc_level_reg = vgc_level; 5563 } 5564 } 5565 5566 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5567 { 5568 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); 5569 } 5570 EXPORT_SYMBOL_GPL(rt2800_reset_tuner); 5571 5572 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 5573 const u32 count) 5574 { 5575 u8 vgc; 5576 5577 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) 5578 return; 5579 5580 /* When RSSI is better than a certain threshold, increase VGC 5581 * with a chip specific value in order to improve the balance 5582 * between sensibility and noise isolation. 5583 */ 5584 5585 vgc = rt2800_get_default_vgc(rt2x00dev); 5586 5587 switch (rt2x00dev->chip.rt) { 5588 case RT3572: 5589 case RT3593: 5590 if (qual->rssi > -65) { 5591 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) 5592 vgc += 0x20; 5593 else 5594 vgc += 0x10; 5595 } 5596 break; 5597 5598 case RT3883: 5599 if (qual->rssi > -65) 5600 vgc += 0x10; 5601 break; 5602 5603 case RT5592: 5604 if (qual->rssi > -65) 5605 vgc += 0x20; 5606 break; 5607 5608 default: 5609 if (qual->rssi > -80) 5610 vgc += 0x10; 5611 break; 5612 } 5613 5614 rt2800_set_vgc(rt2x00dev, qual, vgc); 5615 } 5616 EXPORT_SYMBOL_GPL(rt2800_link_tuner); 5617 5618 /* 5619 * Initialization functions. 5620 */ 5621 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 5622 { 5623 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5624 u32 reg; 5625 u16 eeprom; 5626 unsigned int i; 5627 int ret; 5628 5629 rt2800_disable_wpdma(rt2x00dev); 5630 5631 ret = rt2800_drv_init_registers(rt2x00dev); 5632 if (ret) 5633 return ret; 5634 5635 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); 5636 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 5637 5638 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 5639 5640 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 5641 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); 5642 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); 5643 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); 5644 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); 5645 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 5646 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 5647 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 5648 5649 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); 5650 5651 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 5652 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); 5653 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 5654 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 5655 5656 if (rt2x00_rt(rt2x00dev, RT3290)) { 5657 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 5658 if (rt2x00_get_field32(reg, WLAN_EN) == 1) { 5659 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); 5660 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 5661 } 5662 5663 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 5664 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { 5665 rt2x00_set_field32(®, LDO0_EN, 1); 5666 rt2x00_set_field32(®, LDO_BGSEL, 3); 5667 rt2800_register_write(rt2x00dev, CMB_CTRL, reg); 5668 } 5669 5670 reg = rt2800_register_read(rt2x00dev, OSC_CTRL); 5671 rt2x00_set_field32(®, OSC_ROSC_EN, 1); 5672 rt2x00_set_field32(®, OSC_CAL_REQ, 1); 5673 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); 5674 rt2800_register_write(rt2x00dev, OSC_CTRL, reg); 5675 5676 reg = rt2800_register_read(rt2x00dev, COEX_CFG0); 5677 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); 5678 rt2800_register_write(rt2x00dev, COEX_CFG0, reg); 5679 5680 reg = rt2800_register_read(rt2x00dev, COEX_CFG2); 5681 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); 5682 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); 5683 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); 5684 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); 5685 rt2800_register_write(rt2x00dev, COEX_CFG2, reg); 5686 5687 reg = rt2800_register_read(rt2x00dev, PLL_CTRL); 5688 rt2x00_set_field32(®, PLL_CONTROL, 1); 5689 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); 5690 } 5691 5692 if (rt2x00_rt(rt2x00dev, RT3071) || 5693 rt2x00_rt(rt2x00dev, RT3090) || 5694 rt2x00_rt(rt2x00dev, RT3290) || 5695 rt2x00_rt(rt2x00dev, RT3390)) { 5696 5697 if (rt2x00_rt(rt2x00dev, RT3290)) 5698 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5699 0x00000404); 5700 else 5701 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5702 0x00000400); 5703 5704 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5705 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 5706 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 5707 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 5708 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5709 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 5710 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5711 0x0000002c); 5712 else 5713 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5714 0x0000000f); 5715 } else { 5716 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5717 } 5718 } else if (rt2x00_rt(rt2x00dev, RT3070)) { 5719 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5720 5721 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 5722 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5723 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); 5724 } else { 5725 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5726 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5727 } 5728 } else if (rt2800_is_305x_soc(rt2x00dev)) { 5729 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5730 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5731 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); 5732 } else if (rt2x00_rt(rt2x00dev, RT3352)) { 5733 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5734 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5735 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5736 } else if (rt2x00_rt(rt2x00dev, RT3572)) { 5737 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5738 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5739 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 5740 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5741 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5742 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) { 5743 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5744 if (rt2x00_get_field16(eeprom, 5745 EEPROM_NIC_CONF1_DAC_TEST)) 5746 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5747 0x0000001f); 5748 else 5749 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5750 0x0000000f); 5751 } else { 5752 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5753 0x00000000); 5754 } 5755 } else if (rt2x00_rt(rt2x00dev, RT3883)) { 5756 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5757 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5758 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000); 5759 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21); 5760 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40); 5761 } else if (rt2x00_rt(rt2x00dev, RT5390) || 5762 rt2x00_rt(rt2x00dev, RT5392) || 5763 rt2x00_rt(rt2x00dev, RT6352)) { 5764 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5765 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5766 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5767 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5768 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5769 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5770 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5771 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 5772 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5773 } else if (rt2x00_rt(rt2x00dev, RT6352)) { 5774 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401); 5775 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000); 5776 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5777 rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002); 5778 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F); 5779 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000); 5780 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0); 5781 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0); 5782 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C); 5783 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C); 5784 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 5785 0x3630363A); 5786 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT, 5787 0x3630363A); 5788 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 5789 rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); 5790 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 5791 } else { 5792 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 5793 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5794 } 5795 5796 reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG); 5797 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); 5798 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); 5799 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); 5800 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); 5801 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); 5802 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); 5803 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); 5804 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); 5805 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); 5806 5807 reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG); 5808 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 5809 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); 5810 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 5811 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 5812 5813 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 5814 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 5815 if (rt2x00_is_usb(rt2x00dev)) { 5816 drv_data->max_psdu = 3; 5817 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || 5818 rt2x00_rt(rt2x00dev, RT2883) || 5819 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) { 5820 drv_data->max_psdu = 2; 5821 } else { 5822 drv_data->max_psdu = 1; 5823 } 5824 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu); 5825 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); 5826 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); 5827 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 5828 5829 reg = rt2800_register_read(rt2x00dev, LED_CFG); 5830 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); 5831 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); 5832 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); 5833 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); 5834 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); 5835 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); 5836 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); 5837 rt2800_register_write(rt2x00dev, LED_CFG, reg); 5838 5839 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 5840 5841 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 5842 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); 5843 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); 5844 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); 5845 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); 5846 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); 5847 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); 5848 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5849 5850 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 5851 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); 5852 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); 5853 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); 5854 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); 5855 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); 5856 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 5857 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 5858 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 5859 5860 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 5861 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); 5862 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); 5863 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); 5864 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 5865 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5866 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5867 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5868 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5869 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5870 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); 5871 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 5872 5873 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 5874 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); 5875 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); 5876 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); 5877 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 5878 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5879 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5880 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5881 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5882 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5883 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); 5884 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 5885 5886 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 5887 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 5888 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); 5889 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); 5890 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5891 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5892 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5893 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5894 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5895 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5896 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); 5897 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 5898 5899 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 5900 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 5901 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); 5902 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); 5903 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5904 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5905 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5906 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 5907 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5908 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 5909 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); 5910 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 5911 5912 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 5913 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 5914 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); 5915 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); 5916 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5917 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5918 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5919 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5920 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5921 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5922 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); 5923 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 5924 5925 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 5926 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 5927 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); 5928 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); 5929 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5930 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5931 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5932 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 5933 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5934 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 5935 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); 5936 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 5937 5938 if (rt2x00_is_usb(rt2x00dev)) { 5939 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); 5940 5941 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 5942 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 5943 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 5944 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 5945 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 5946 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); 5947 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); 5948 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); 5949 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); 5950 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); 5951 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 5952 } 5953 5954 /* 5955 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 5956 * although it is reserved. 5957 */ 5958 reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG); 5959 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); 5960 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); 5961 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); 5962 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); 5963 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); 5964 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); 5965 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); 5966 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); 5967 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); 5968 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); 5969 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); 5970 5971 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; 5972 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); 5973 5974 if (rt2x00_rt(rt2x00dev, RT3883)) { 5975 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008); 5976 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413); 5977 } 5978 5979 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 5980 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); 5981 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, 5982 IEEE80211_MAX_RTS_THRESHOLD); 5983 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1); 5984 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 5985 5986 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 5987 5988 /* 5989 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS 5990 * time should be set to 16. However, the original Ralink driver uses 5991 * 16 for both and indeed using a value of 10 for CCK SIFS results in 5992 * connection problems with 11g + CTS protection. Hence, use the same 5993 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. 5994 */ 5995 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 5996 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); 5997 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); 5998 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); 5999 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); 6000 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); 6001 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 6002 6003 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 6004 6005 /* 6006 * ASIC will keep garbage value after boot, clear encryption keys. 6007 */ 6008 for (i = 0; i < 4; i++) 6009 rt2800_register_write(rt2x00dev, 6010 SHARED_KEY_MODE_ENTRY(i), 0); 6011 6012 for (i = 0; i < 256; i++) { 6013 rt2800_config_wcid(rt2x00dev, NULL, i); 6014 rt2800_delete_wcid_attr(rt2x00dev, i); 6015 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 6016 } 6017 6018 /* 6019 * Clear all beacons 6020 */ 6021 for (i = 0; i < 8; i++) 6022 rt2800_clear_beacon_register(rt2x00dev, i); 6023 6024 if (rt2x00_is_usb(rt2x00dev)) { 6025 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6026 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); 6027 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6028 } else if (rt2x00_is_pcie(rt2x00dev)) { 6029 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6030 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); 6031 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6032 } 6033 6034 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0); 6035 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); 6036 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); 6037 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); 6038 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); 6039 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); 6040 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); 6041 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); 6042 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); 6043 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); 6044 6045 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1); 6046 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); 6047 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); 6048 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); 6049 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); 6050 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); 6051 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); 6052 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); 6053 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); 6054 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); 6055 6056 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0); 6057 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); 6058 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); 6059 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); 6060 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); 6061 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); 6062 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); 6063 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); 6064 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); 6065 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); 6066 6067 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1); 6068 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); 6069 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); 6070 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); 6071 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); 6072 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); 6073 6074 /* 6075 * Do not force the BA window size, we use the TXWI to set it 6076 */ 6077 reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE); 6078 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); 6079 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); 6080 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); 6081 6082 /* 6083 * We must clear the error counters. 6084 * These registers are cleared on read, 6085 * so we may pass a useless variable to store the value. 6086 */ 6087 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 6088 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1); 6089 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2); 6090 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0); 6091 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1); 6092 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2); 6093 6094 /* 6095 * Setup leadtime for pre tbtt interrupt to 6ms 6096 */ 6097 reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG); 6098 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); 6099 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); 6100 6101 /* 6102 * Set up channel statistics timer 6103 */ 6104 reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG); 6105 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); 6106 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); 6107 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); 6108 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); 6109 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); 6110 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); 6111 6112 return 0; 6113 } 6114 6115 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) 6116 { 6117 unsigned int i; 6118 u32 reg; 6119 6120 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 6121 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 6122 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) 6123 return 0; 6124 6125 udelay(REGISTER_BUSY_DELAY); 6126 } 6127 6128 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n"); 6129 return -EACCES; 6130 } 6131 6132 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 6133 { 6134 unsigned int i; 6135 u8 value; 6136 6137 /* 6138 * BBP was enabled after firmware was loaded, 6139 * but we need to reactivate it now. 6140 */ 6141 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 6142 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 6143 msleep(1); 6144 6145 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 6146 value = rt2800_bbp_read(rt2x00dev, 0); 6147 if ((value != 0xff) && (value != 0x00)) 6148 return 0; 6149 udelay(REGISTER_BUSY_DELAY); 6150 } 6151 6152 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 6153 return -EACCES; 6154 } 6155 6156 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev) 6157 { 6158 u8 value; 6159 6160 value = rt2800_bbp_read(rt2x00dev, 4); 6161 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); 6162 rt2800_bbp_write(rt2x00dev, 4, value); 6163 } 6164 6165 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev) 6166 { 6167 rt2800_bbp_write(rt2x00dev, 142, 1); 6168 rt2800_bbp_write(rt2x00dev, 143, 57); 6169 } 6170 6171 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev) 6172 { 6173 static const u8 glrt_table[] = { 6174 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */ 6175 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */ 6176 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */ 6177 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */ 6178 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */ 6179 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */ 6180 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */ 6181 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */ 6182 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */ 6183 }; 6184 int i; 6185 6186 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) { 6187 rt2800_bbp_write(rt2x00dev, 195, 128 + i); 6188 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]); 6189 } 6190 }; 6191 6192 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev) 6193 { 6194 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6195 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6196 rt2800_bbp_write(rt2x00dev, 68, 0x0B); 6197 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6198 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6199 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6200 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6201 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6202 rt2800_bbp_write(rt2x00dev, 83, 0x6A); 6203 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6204 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6205 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6206 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6207 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6208 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6209 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6210 } 6211 6212 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev) 6213 { 6214 u16 eeprom; 6215 u8 value; 6216 6217 value = rt2800_bbp_read(rt2x00dev, 138); 6218 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 6219 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 6220 value |= 0x20; 6221 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 6222 value &= ~0x02; 6223 rt2800_bbp_write(rt2x00dev, 138, value); 6224 } 6225 6226 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev) 6227 { 6228 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6229 6230 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6231 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6232 6233 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6234 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6235 6236 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6237 6238 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 6239 rt2800_bbp_write(rt2x00dev, 80, 0x08); 6240 6241 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6242 6243 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6244 6245 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6246 6247 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6248 6249 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6250 6251 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6252 6253 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6254 6255 rt2800_bbp_write(rt2x00dev, 105, 0x01); 6256 6257 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6258 } 6259 6260 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev) 6261 { 6262 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6263 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6264 6265 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 6266 rt2800_bbp_write(rt2x00dev, 69, 0x16); 6267 rt2800_bbp_write(rt2x00dev, 73, 0x12); 6268 } else { 6269 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6270 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6271 } 6272 6273 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6274 6275 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6276 6277 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6278 6279 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6280 6281 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 6282 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6283 else 6284 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6285 6286 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6287 6288 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6289 6290 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6291 6292 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6293 6294 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6295 6296 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6297 } 6298 6299 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev) 6300 { 6301 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6302 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6303 6304 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6305 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6306 6307 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6308 6309 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6310 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6311 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6312 6313 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6314 6315 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6316 6317 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6318 6319 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6320 6321 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6322 6323 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6324 6325 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 6326 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 6327 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E)) 6328 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6329 else 6330 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6331 6332 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6333 6334 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6335 6336 if (rt2x00_rt(rt2x00dev, RT3071) || 6337 rt2x00_rt(rt2x00dev, RT3090)) 6338 rt2800_disable_unused_dac_adc(rt2x00dev); 6339 } 6340 6341 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev) 6342 { 6343 u8 value; 6344 6345 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6346 6347 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6348 6349 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6350 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6351 6352 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6353 6354 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6355 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6356 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6357 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6358 6359 rt2800_bbp_write(rt2x00dev, 77, 0x58); 6360 6361 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6362 6363 rt2800_bbp_write(rt2x00dev, 74, 0x0b); 6364 rt2800_bbp_write(rt2x00dev, 79, 0x18); 6365 rt2800_bbp_write(rt2x00dev, 80, 0x09); 6366 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6367 6368 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6369 6370 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6371 6372 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6373 6374 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6375 6376 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6377 6378 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6379 6380 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6381 6382 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6383 6384 rt2800_bbp_write(rt2x00dev, 105, 0x1c); 6385 6386 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6387 6388 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6389 6390 rt2800_bbp_write(rt2x00dev, 67, 0x24); 6391 rt2800_bbp_write(rt2x00dev, 143, 0x04); 6392 rt2800_bbp_write(rt2x00dev, 142, 0x99); 6393 rt2800_bbp_write(rt2x00dev, 150, 0x30); 6394 rt2800_bbp_write(rt2x00dev, 151, 0x2e); 6395 rt2800_bbp_write(rt2x00dev, 152, 0x20); 6396 rt2800_bbp_write(rt2x00dev, 153, 0x34); 6397 rt2800_bbp_write(rt2x00dev, 154, 0x40); 6398 rt2800_bbp_write(rt2x00dev, 155, 0x3b); 6399 rt2800_bbp_write(rt2x00dev, 253, 0x04); 6400 6401 value = rt2800_bbp_read(rt2x00dev, 47); 6402 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1); 6403 rt2800_bbp_write(rt2x00dev, 47, value); 6404 6405 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */ 6406 value = rt2800_bbp_read(rt2x00dev, 3); 6407 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1); 6408 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1); 6409 rt2800_bbp_write(rt2x00dev, 3, value); 6410 } 6411 6412 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) 6413 { 6414 rt2800_bbp_write(rt2x00dev, 3, 0x00); 6415 rt2800_bbp_write(rt2x00dev, 4, 0x50); 6416 6417 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6418 6419 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6420 6421 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6422 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6423 6424 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6425 6426 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6427 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6428 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6429 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6430 6431 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6432 6433 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6434 6435 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 6436 rt2800_bbp_write(rt2x00dev, 80, 0x08); 6437 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6438 6439 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6440 6441 if (rt2x00_rt(rt2x00dev, RT5350)) { 6442 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6443 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6444 } else { 6445 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6446 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6447 } 6448 6449 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6450 6451 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6452 6453 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6454 6455 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6456 6457 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6458 6459 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6460 6461 if (rt2x00_rt(rt2x00dev, RT5350)) { 6462 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6463 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6464 } else { 6465 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6466 rt2800_bbp_write(rt2x00dev, 106, 0x05); 6467 } 6468 6469 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6470 6471 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6472 6473 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 6474 /* Set ITxBF timeout to 0x9c40=1000msec */ 6475 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6476 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6477 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6478 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6479 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6480 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6481 /* Reprogram the inband interface to put right values in RXWI */ 6482 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6483 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6484 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6485 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6486 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6487 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6488 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6489 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6490 6491 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6492 6493 if (rt2x00_rt(rt2x00dev, RT5350)) { 6494 /* Antenna Software OFDM */ 6495 rt2800_bbp_write(rt2x00dev, 150, 0x40); 6496 /* Antenna Software CCK */ 6497 rt2800_bbp_write(rt2x00dev, 151, 0x30); 6498 rt2800_bbp_write(rt2x00dev, 152, 0xa3); 6499 /* Clear previously selected antenna */ 6500 rt2800_bbp_write(rt2x00dev, 154, 0); 6501 } 6502 } 6503 6504 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev) 6505 { 6506 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6507 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6508 6509 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6510 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6511 6512 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6513 6514 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6515 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6516 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6517 6518 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6519 6520 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6521 6522 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6523 6524 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6525 6526 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6527 6528 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6529 6530 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E)) 6531 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6532 else 6533 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6534 6535 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6536 6537 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6538 6539 rt2800_disable_unused_dac_adc(rt2x00dev); 6540 } 6541 6542 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev) 6543 { 6544 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6545 6546 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6547 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6548 6549 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6550 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6551 6552 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6553 6554 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6555 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6556 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6557 6558 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6559 6560 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6561 6562 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6563 6564 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6565 6566 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6567 6568 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6569 6570 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6571 6572 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6573 6574 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6575 6576 rt2800_disable_unused_dac_adc(rt2x00dev); 6577 } 6578 6579 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev) 6580 { 6581 rt2800_init_bbp_early(rt2x00dev); 6582 6583 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6584 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6585 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6586 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6587 6588 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6589 6590 /* Enable DC filter */ 6591 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E)) 6592 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6593 } 6594 6595 static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev) 6596 { 6597 rt2800_init_bbp_early(rt2x00dev); 6598 6599 rt2800_bbp_write(rt2x00dev, 4, 0x50); 6600 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6601 6602 rt2800_bbp_write(rt2x00dev, 86, 0x46); 6603 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6604 6605 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6606 6607 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6608 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6609 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6610 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6611 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6612 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6613 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 6614 6615 /* Set ITxBF timeout to 0x9C40=1000msec */ 6616 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6617 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6618 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6619 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6620 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6621 6622 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6623 6624 /* Reprogram the inband interface to put right values in RXWI */ 6625 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6626 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6627 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6628 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6629 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6630 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6631 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6632 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6633 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6634 } 6635 6636 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) 6637 { 6638 int ant, div_mode; 6639 u16 eeprom; 6640 u8 value; 6641 6642 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6643 6644 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6645 6646 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6647 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6648 6649 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6650 6651 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6652 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6653 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6654 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6655 6656 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6657 6658 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6659 6660 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6661 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6662 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6663 6664 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6665 6666 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6667 6668 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6669 6670 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6671 6672 if (rt2x00_rt(rt2x00dev, RT5392)) 6673 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6674 6675 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6676 6677 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6678 6679 if (rt2x00_rt(rt2x00dev, RT5392)) { 6680 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6681 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6682 } 6683 6684 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6685 6686 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6687 6688 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6689 6690 if (rt2x00_rt(rt2x00dev, RT5390)) 6691 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6692 else if (rt2x00_rt(rt2x00dev, RT5392)) 6693 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6694 else 6695 WARN_ON(1); 6696 6697 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6698 6699 if (rt2x00_rt(rt2x00dev, RT5392)) { 6700 rt2800_bbp_write(rt2x00dev, 134, 0xd0); 6701 rt2800_bbp_write(rt2x00dev, 135, 0xf6); 6702 } 6703 6704 rt2800_disable_unused_dac_adc(rt2x00dev); 6705 6706 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6707 div_mode = rt2x00_get_field16(eeprom, 6708 EEPROM_NIC_CONF1_ANT_DIVERSITY); 6709 ant = (div_mode == 3) ? 1 : 0; 6710 6711 /* check if this is a Bluetooth combo card */ 6712 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 6713 u32 reg; 6714 6715 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 6716 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 6717 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); 6718 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); 6719 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); 6720 if (ant == 0) 6721 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); 6722 else if (ant == 1) 6723 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); 6724 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 6725 } 6726 6727 /* These chips have hardware RX antenna diversity */ 6728 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 6729 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 6730 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */ 6731 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */ 6732 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */ 6733 } 6734 6735 value = rt2800_bbp_read(rt2x00dev, 152); 6736 if (ant == 0) 6737 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6738 else 6739 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6740 rt2800_bbp_write(rt2x00dev, 152, value); 6741 6742 rt2800_init_freq_calibration(rt2x00dev); 6743 } 6744 6745 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) 6746 { 6747 int ant, div_mode; 6748 u16 eeprom; 6749 u8 value; 6750 6751 rt2800_init_bbp_early(rt2x00dev); 6752 6753 value = rt2800_bbp_read(rt2x00dev, 105); 6754 rt2x00_set_field8(&value, BBP105_MLD, 6755 rt2x00dev->default_ant.rx_chain_num == 2); 6756 rt2800_bbp_write(rt2x00dev, 105, value); 6757 6758 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6759 6760 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6761 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6762 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6763 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6764 rt2800_bbp_write(rt2x00dev, 69, 0x1A); 6765 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6766 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6767 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6768 rt2800_bbp_write(rt2x00dev, 75, 0x4F); 6769 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6770 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6771 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 6772 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6773 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6774 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6775 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6776 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6777 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6778 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 6779 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6780 /* FIXME BBP105 owerwrite */ 6781 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 6782 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6783 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6784 rt2800_bbp_write(rt2x00dev, 134, 0xD0); 6785 rt2800_bbp_write(rt2x00dev, 135, 0xF6); 6786 rt2800_bbp_write(rt2x00dev, 137, 0x0F); 6787 6788 /* Initialize GLRT (Generalized Likehood Radio Test) */ 6789 rt2800_init_bbp_5592_glrt(rt2x00dev); 6790 6791 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6792 6793 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6794 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); 6795 ant = (div_mode == 3) ? 1 : 0; 6796 value = rt2800_bbp_read(rt2x00dev, 152); 6797 if (ant == 0) { 6798 /* Main antenna */ 6799 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6800 } else { 6801 /* Auxiliary antenna */ 6802 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6803 } 6804 rt2800_bbp_write(rt2x00dev, 152, value); 6805 6806 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) { 6807 value = rt2800_bbp_read(rt2x00dev, 254); 6808 rt2x00_set_field8(&value, BBP254_BIT7, 1); 6809 rt2800_bbp_write(rt2x00dev, 254, value); 6810 } 6811 6812 rt2800_init_freq_calibration(rt2x00dev); 6813 6814 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6815 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 6816 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6817 } 6818 6819 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev, 6820 const u8 reg, const u8 value) 6821 { 6822 rt2800_bbp_write(rt2x00dev, 195, reg); 6823 rt2800_bbp_write(rt2x00dev, 196, value); 6824 } 6825 6826 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev, 6827 const u8 reg, const u8 value) 6828 { 6829 rt2800_bbp_write(rt2x00dev, 158, reg); 6830 rt2800_bbp_write(rt2x00dev, 159, value); 6831 } 6832 6833 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg) 6834 { 6835 rt2800_bbp_write(rt2x00dev, 158, reg); 6836 return rt2800_bbp_read(rt2x00dev, 159); 6837 } 6838 6839 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev) 6840 { 6841 u8 bbp; 6842 6843 /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */ 6844 bbp = rt2800_bbp_read(rt2x00dev, 105); 6845 rt2x00_set_field8(&bbp, BBP105_MLD, 6846 rt2x00dev->default_ant.rx_chain_num == 2); 6847 rt2800_bbp_write(rt2x00dev, 105, bbp); 6848 6849 /* Avoid data loss and CRC errors */ 6850 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6851 6852 /* Fix I/Q swap issue */ 6853 bbp = rt2800_bbp_read(rt2x00dev, 1); 6854 bbp |= 0x04; 6855 rt2800_bbp_write(rt2x00dev, 1, bbp); 6856 6857 /* BBP for G band */ 6858 rt2800_bbp_write(rt2x00dev, 3, 0x08); 6859 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */ 6860 rt2800_bbp_write(rt2x00dev, 6, 0x08); 6861 rt2800_bbp_write(rt2x00dev, 14, 0x09); 6862 rt2800_bbp_write(rt2x00dev, 15, 0xFF); 6863 rt2800_bbp_write(rt2x00dev, 16, 0x01); 6864 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6865 rt2800_bbp_write(rt2x00dev, 21, 0x00); 6866 rt2800_bbp_write(rt2x00dev, 22, 0x00); 6867 rt2800_bbp_write(rt2x00dev, 27, 0x00); 6868 rt2800_bbp_write(rt2x00dev, 28, 0x00); 6869 rt2800_bbp_write(rt2x00dev, 30, 0x00); 6870 rt2800_bbp_write(rt2x00dev, 31, 0x48); 6871 rt2800_bbp_write(rt2x00dev, 47, 0x40); 6872 rt2800_bbp_write(rt2x00dev, 62, 0x00); 6873 rt2800_bbp_write(rt2x00dev, 63, 0x00); 6874 rt2800_bbp_write(rt2x00dev, 64, 0x00); 6875 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6876 rt2800_bbp_write(rt2x00dev, 66, 0x1C); 6877 rt2800_bbp_write(rt2x00dev, 67, 0x20); 6878 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6879 rt2800_bbp_write(rt2x00dev, 69, 0x10); 6880 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6881 rt2800_bbp_write(rt2x00dev, 73, 0x18); 6882 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6883 rt2800_bbp_write(rt2x00dev, 75, 0x60); 6884 rt2800_bbp_write(rt2x00dev, 76, 0x44); 6885 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6886 rt2800_bbp_write(rt2x00dev, 78, 0x1E); 6887 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 6888 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 6889 rt2800_bbp_write(rt2x00dev, 81, 0x3A); 6890 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 6891 rt2800_bbp_write(rt2x00dev, 83, 0x9A); 6892 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 6893 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6894 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6895 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6896 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6897 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 6898 rt2800_bbp_write(rt2x00dev, 96, 0x00); 6899 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 6900 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6901 /* FIXME BBP105 owerwrite */ 6902 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 6903 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6904 rt2800_bbp_write(rt2x00dev, 109, 0x00); 6905 rt2800_bbp_write(rt2x00dev, 134, 0x10); 6906 rt2800_bbp_write(rt2x00dev, 135, 0xA6); 6907 rt2800_bbp_write(rt2x00dev, 137, 0x04); 6908 rt2800_bbp_write(rt2x00dev, 142, 0x30); 6909 rt2800_bbp_write(rt2x00dev, 143, 0xF7); 6910 rt2800_bbp_write(rt2x00dev, 160, 0xEC); 6911 rt2800_bbp_write(rt2x00dev, 161, 0xC4); 6912 rt2800_bbp_write(rt2x00dev, 162, 0x77); 6913 rt2800_bbp_write(rt2x00dev, 163, 0xF9); 6914 rt2800_bbp_write(rt2x00dev, 164, 0x00); 6915 rt2800_bbp_write(rt2x00dev, 165, 0x00); 6916 rt2800_bbp_write(rt2x00dev, 186, 0x00); 6917 rt2800_bbp_write(rt2x00dev, 187, 0x00); 6918 rt2800_bbp_write(rt2x00dev, 188, 0x00); 6919 rt2800_bbp_write(rt2x00dev, 186, 0x00); 6920 rt2800_bbp_write(rt2x00dev, 187, 0x01); 6921 rt2800_bbp_write(rt2x00dev, 188, 0x00); 6922 rt2800_bbp_write(rt2x00dev, 189, 0x00); 6923 6924 rt2800_bbp_write(rt2x00dev, 91, 0x06); 6925 rt2800_bbp_write(rt2x00dev, 92, 0x04); 6926 rt2800_bbp_write(rt2x00dev, 93, 0x54); 6927 rt2800_bbp_write(rt2x00dev, 99, 0x50); 6928 rt2800_bbp_write(rt2x00dev, 148, 0x84); 6929 rt2800_bbp_write(rt2x00dev, 167, 0x80); 6930 rt2800_bbp_write(rt2x00dev, 178, 0xFF); 6931 rt2800_bbp_write(rt2x00dev, 106, 0x13); 6932 6933 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */ 6934 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00); 6935 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14); 6936 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20); 6937 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A); 6938 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16); 6939 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06); 6940 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02); 6941 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07); 6942 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05); 6943 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09); 6944 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20); 6945 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08); 6946 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A); 6947 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00); 6948 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00); 6949 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0); 6950 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F); 6951 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F); 6952 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32); 6953 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08); 6954 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28); 6955 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19); 6956 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A); 6957 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16); 6958 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10); 6959 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10); 6960 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A); 6961 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36); 6962 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C); 6963 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26); 6964 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24); 6965 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42); 6966 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40); 6967 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30); 6968 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29); 6969 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C); 6970 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46); 6971 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D); 6972 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40); 6973 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E); 6974 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38); 6975 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D); 6976 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F); 6977 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C); 6978 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34); 6979 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C); 6980 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F); 6981 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C); 6982 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35); 6983 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E); 6984 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F); 6985 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49); 6986 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41); 6987 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36); 6988 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39); 6989 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30); 6990 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30); 6991 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E); 6992 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D); 6993 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28); 6994 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21); 6995 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C); 6996 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16); 6997 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50); 6998 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A); 6999 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43); 7000 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50); 7001 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10); 7002 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10); 7003 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10); 7004 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10); 7005 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D); 7006 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14); 7007 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32); 7008 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C); 7009 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36); 7010 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C); 7011 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43); 7012 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C); 7013 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E); 7014 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36); 7015 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30); 7016 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E); 7017 7018 /* BBP for G band DCOC function */ 7019 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C); 7020 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00); 7021 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10); 7022 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10); 7023 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10); 7024 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10); 7025 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08); 7026 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40); 7027 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04); 7028 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04); 7029 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08); 7030 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08); 7031 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03); 7032 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03); 7033 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03); 7034 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02); 7035 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40); 7036 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40); 7037 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64); 7038 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64); 7039 7040 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7041 } 7042 7043 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) 7044 { 7045 unsigned int i; 7046 u16 eeprom; 7047 u8 reg_id; 7048 u8 value; 7049 7050 if (rt2800_is_305x_soc(rt2x00dev)) 7051 rt2800_init_bbp_305x_soc(rt2x00dev); 7052 7053 switch (rt2x00dev->chip.rt) { 7054 case RT2860: 7055 case RT2872: 7056 case RT2883: 7057 rt2800_init_bbp_28xx(rt2x00dev); 7058 break; 7059 case RT3070: 7060 case RT3071: 7061 case RT3090: 7062 rt2800_init_bbp_30xx(rt2x00dev); 7063 break; 7064 case RT3290: 7065 rt2800_init_bbp_3290(rt2x00dev); 7066 break; 7067 case RT3352: 7068 case RT5350: 7069 rt2800_init_bbp_3352(rt2x00dev); 7070 break; 7071 case RT3390: 7072 rt2800_init_bbp_3390(rt2x00dev); 7073 break; 7074 case RT3572: 7075 rt2800_init_bbp_3572(rt2x00dev); 7076 break; 7077 case RT3593: 7078 rt2800_init_bbp_3593(rt2x00dev); 7079 return; 7080 case RT3883: 7081 rt2800_init_bbp_3883(rt2x00dev); 7082 return; 7083 case RT5390: 7084 case RT5392: 7085 rt2800_init_bbp_53xx(rt2x00dev); 7086 break; 7087 case RT5592: 7088 rt2800_init_bbp_5592(rt2x00dev); 7089 return; 7090 case RT6352: 7091 rt2800_init_bbp_6352(rt2x00dev); 7092 break; 7093 } 7094 7095 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 7096 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 7097 EEPROM_BBP_START, i); 7098 7099 if (eeprom != 0xffff && eeprom != 0x0000) { 7100 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 7101 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 7102 rt2800_bbp_write(rt2x00dev, reg_id, value); 7103 } 7104 } 7105 } 7106 7107 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev) 7108 { 7109 u32 reg; 7110 7111 reg = rt2800_register_read(rt2x00dev, OPT_14_CSR); 7112 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); 7113 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 7114 } 7115 7116 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, 7117 u8 filter_target) 7118 { 7119 unsigned int i; 7120 u8 bbp; 7121 u8 rfcsr; 7122 u8 passband; 7123 u8 stopband; 7124 u8 overtuned = 0; 7125 u8 rfcsr24 = (bw40) ? 0x27 : 0x07; 7126 7127 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7128 7129 bbp = rt2800_bbp_read(rt2x00dev, 4); 7130 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); 7131 rt2800_bbp_write(rt2x00dev, 4, bbp); 7132 7133 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 7134 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); 7135 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 7136 7137 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 7138 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); 7139 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 7140 7141 /* 7142 * Set power & frequency of passband test tone 7143 */ 7144 rt2800_bbp_write(rt2x00dev, 24, 0); 7145 7146 for (i = 0; i < 100; i++) { 7147 rt2800_bbp_write(rt2x00dev, 25, 0x90); 7148 msleep(1); 7149 7150 passband = rt2800_bbp_read(rt2x00dev, 55); 7151 if (passband) 7152 break; 7153 } 7154 7155 /* 7156 * Set power & frequency of stopband test tone 7157 */ 7158 rt2800_bbp_write(rt2x00dev, 24, 0x06); 7159 7160 for (i = 0; i < 100; i++) { 7161 rt2800_bbp_write(rt2x00dev, 25, 0x90); 7162 msleep(1); 7163 7164 stopband = rt2800_bbp_read(rt2x00dev, 55); 7165 7166 if ((passband - stopband) <= filter_target) { 7167 rfcsr24++; 7168 overtuned += ((passband - stopband) == filter_target); 7169 } else 7170 break; 7171 7172 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7173 } 7174 7175 rfcsr24 -= !!overtuned; 7176 7177 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7178 return rfcsr24; 7179 } 7180 7181 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev, 7182 const unsigned int rf_reg) 7183 { 7184 u8 rfcsr; 7185 7186 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg); 7187 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1); 7188 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 7189 msleep(1); 7190 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0); 7191 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 7192 } 7193 7194 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev) 7195 { 7196 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7197 u8 filter_tgt_bw20; 7198 u8 filter_tgt_bw40; 7199 u8 rfcsr, bbp; 7200 7201 /* 7202 * TODO: sync filter_tgt values with vendor driver 7203 */ 7204 if (rt2x00_rt(rt2x00dev, RT3070)) { 7205 filter_tgt_bw20 = 0x16; 7206 filter_tgt_bw40 = 0x19; 7207 } else { 7208 filter_tgt_bw20 = 0x13; 7209 filter_tgt_bw40 = 0x15; 7210 } 7211 7212 drv_data->calibration_bw20 = 7213 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20); 7214 drv_data->calibration_bw40 = 7215 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40); 7216 7217 /* 7218 * Save BBP 25 & 26 values for later use in channel switching (for 3052) 7219 */ 7220 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 7221 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 7222 7223 /* 7224 * Set back to initial state 7225 */ 7226 rt2800_bbp_write(rt2x00dev, 24, 0); 7227 7228 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 7229 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 7230 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 7231 7232 /* 7233 * Set BBP back to BW20 7234 */ 7235 bbp = rt2800_bbp_read(rt2x00dev, 4); 7236 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 7237 rt2800_bbp_write(rt2x00dev, 4, bbp); 7238 } 7239 7240 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) 7241 { 7242 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7243 u8 min_gain, rfcsr, bbp; 7244 u16 eeprom; 7245 7246 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 7247 7248 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 7249 if (rt2x00_rt(rt2x00dev, RT3070) || 7250 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7251 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 7252 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 7253 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev)) 7254 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 7255 } 7256 7257 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2; 7258 if (drv_data->txmixer_gain_24g >= min_gain) { 7259 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 7260 drv_data->txmixer_gain_24g); 7261 } 7262 7263 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 7264 7265 if (rt2x00_rt(rt2x00dev, RT3090)) { 7266 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 7267 bbp = rt2800_bbp_read(rt2x00dev, 138); 7268 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 7269 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 7270 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); 7271 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 7272 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); 7273 rt2800_bbp_write(rt2x00dev, 138, bbp); 7274 } 7275 7276 if (rt2x00_rt(rt2x00dev, RT3070)) { 7277 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27); 7278 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) 7279 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); 7280 else 7281 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); 7282 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); 7283 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); 7284 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); 7285 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 7286 } else if (rt2x00_rt(rt2x00dev, RT3071) || 7287 rt2x00_rt(rt2x00dev, RT3090) || 7288 rt2x00_rt(rt2x00dev, RT3390)) { 7289 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 7290 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 7291 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 7292 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 7293 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 7294 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 7295 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 7296 7297 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15); 7298 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); 7299 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); 7300 7301 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 7302 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); 7303 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 7304 7305 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 7306 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); 7307 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 7308 } 7309 } 7310 7311 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev) 7312 { 7313 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7314 u8 rfcsr; 7315 u8 tx_gain; 7316 7317 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 7318 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0); 7319 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7320 7321 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 7322 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g, 7323 RFCSR17_TXMIXER_GAIN); 7324 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain); 7325 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 7326 7327 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38); 7328 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); 7329 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); 7330 7331 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39); 7332 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); 7333 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 7334 7335 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 7336 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 7337 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 7338 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 7339 7340 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 7341 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 7342 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 7343 7344 /* TODO: enable stream mode */ 7345 } 7346 7347 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev) 7348 { 7349 u8 reg; 7350 u16 eeprom; 7351 7352 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 7353 reg = rt2800_bbp_read(rt2x00dev, 138); 7354 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 7355 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 7356 rt2x00_set_field8(®, BBP138_RX_ADC1, 0); 7357 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 7358 rt2x00_set_field8(®, BBP138_TX_DAC1, 1); 7359 rt2800_bbp_write(rt2x00dev, 138, reg); 7360 7361 reg = rt2800_rfcsr_read(rt2x00dev, 38); 7362 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); 7363 rt2800_rfcsr_write(rt2x00dev, 38, reg); 7364 7365 reg = rt2800_rfcsr_read(rt2x00dev, 39); 7366 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); 7367 rt2800_rfcsr_write(rt2x00dev, 39, reg); 7368 7369 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7370 7371 reg = rt2800_rfcsr_read(rt2x00dev, 30); 7372 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); 7373 rt2800_rfcsr_write(rt2x00dev, 30, reg); 7374 } 7375 7376 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev) 7377 { 7378 rt2800_rf_init_calibration(rt2x00dev, 30); 7379 7380 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 7381 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 7382 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 7383 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 7384 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7385 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7386 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7387 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 7388 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 7389 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7390 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 7391 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7392 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 7393 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 7394 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7395 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7396 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7397 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7398 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7399 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7400 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7401 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7402 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7403 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 7404 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7405 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 7406 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 7407 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 7408 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 7409 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 7410 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 7411 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 7412 } 7413 7414 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) 7415 { 7416 u8 rfcsr; 7417 u16 eeprom; 7418 u32 reg; 7419 7420 /* XXX vendor driver do this only for 3070 */ 7421 rt2800_rf_init_calibration(rt2x00dev, 30); 7422 7423 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7424 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7425 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7426 rt2800_rfcsr_write(rt2x00dev, 7, 0x60); 7427 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7428 rt2800_rfcsr_write(rt2x00dev, 10, 0x41); 7429 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7430 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 7431 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7432 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7433 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7434 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7435 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7436 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7437 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7438 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7439 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7440 rt2800_rfcsr_write(rt2x00dev, 25, 0x03); 7441 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 7442 7443 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 7444 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7445 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7446 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7447 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7448 } else if (rt2x00_rt(rt2x00dev, RT3071) || 7449 rt2x00_rt(rt2x00dev, RT3090)) { 7450 rt2800_rfcsr_write(rt2x00dev, 31, 0x14); 7451 7452 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7453 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7454 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7455 7456 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7457 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7458 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7459 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { 7460 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 7461 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 7462 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7463 else 7464 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7465 } 7466 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7467 7468 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7469 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7470 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7471 } 7472 7473 rt2800_rx_filter_calibration(rt2x00dev); 7474 7475 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 7476 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7477 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) 7478 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7479 7480 rt2800_led_open_drain_enable(rt2x00dev); 7481 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7482 } 7483 7484 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) 7485 { 7486 u8 rfcsr; 7487 7488 rt2800_rf_init_calibration(rt2x00dev, 2); 7489 7490 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 7491 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7492 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7493 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7494 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 7495 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3); 7496 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7497 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7498 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7499 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7500 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7501 rt2800_rfcsr_write(rt2x00dev, 18, 0x02); 7502 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7503 rt2800_rfcsr_write(rt2x00dev, 25, 0x83); 7504 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7505 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7506 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7507 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7508 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7509 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7510 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7511 rt2800_rfcsr_write(rt2x00dev, 34, 0x05); 7512 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7513 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7514 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7515 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7516 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7517 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7518 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7519 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b); 7520 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7521 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7522 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7523 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7524 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7525 rt2800_rfcsr_write(rt2x00dev, 49, 0x98); 7526 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7527 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7528 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 7529 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7530 rt2800_rfcsr_write(rt2x00dev, 56, 0x02); 7531 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 7532 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 7533 rt2800_rfcsr_write(rt2x00dev, 59, 0x09); 7534 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7535 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); 7536 7537 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29); 7538 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3); 7539 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr); 7540 7541 rt2800_led_open_drain_enable(rt2x00dev); 7542 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7543 } 7544 7545 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) 7546 { 7547 int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0, 7548 &rt2x00dev->cap_flags); 7549 int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1, 7550 &rt2x00dev->cap_flags); 7551 u8 rfcsr; 7552 7553 rt2800_rf_init_calibration(rt2x00dev, 30); 7554 7555 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7556 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7557 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7558 rt2800_rfcsr_write(rt2x00dev, 3, 0x18); 7559 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7560 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7561 rt2800_rfcsr_write(rt2x00dev, 6, 0x33); 7562 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7563 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7564 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7565 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2); 7566 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 7567 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 7568 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 7569 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a); 7570 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7571 rt2800_rfcsr_write(rt2x00dev, 16, 0x01); 7572 rt2800_rfcsr_write(rt2x00dev, 18, 0x45); 7573 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7574 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7575 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7576 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7577 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7578 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7579 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7580 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7581 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7582 rt2800_rfcsr_write(rt2x00dev, 28, 0x03); 7583 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 7584 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7585 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7586 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7587 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7588 rfcsr = 0x01; 7589 if (tx0_ext_pa) 7590 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1); 7591 if (tx1_ext_pa) 7592 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1); 7593 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 7594 rt2800_rfcsr_write(rt2x00dev, 35, 0x03); 7595 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); 7596 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); 7597 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); 7598 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); 7599 rt2800_rfcsr_write(rt2x00dev, 40, 0x33); 7600 rfcsr = 0x52; 7601 if (!tx0_ext_pa) { 7602 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1); 7603 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1); 7604 } 7605 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr); 7606 rfcsr = 0x52; 7607 if (!tx1_ext_pa) { 7608 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1); 7609 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1); 7610 } 7611 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 7612 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); 7613 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); 7614 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); 7615 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd); 7616 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); 7617 rt2800_rfcsr_write(rt2x00dev, 48, 0x14); 7618 rt2800_rfcsr_write(rt2x00dev, 49, 0x00); 7619 rfcsr = 0x2d; 7620 if (tx0_ext_pa) 7621 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1); 7622 if (tx1_ext_pa) 7623 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1); 7624 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7625 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f)); 7626 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00)); 7627 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52)); 7628 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b)); 7629 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f)); 7630 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00)); 7631 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52)); 7632 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b)); 7633 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 7634 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 7635 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 7636 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7637 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7638 7639 rt2800_rx_filter_calibration(rt2x00dev); 7640 rt2800_led_open_drain_enable(rt2x00dev); 7641 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7642 } 7643 7644 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) 7645 { 7646 u32 reg; 7647 7648 rt2800_rf_init_calibration(rt2x00dev, 30); 7649 7650 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 7651 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 7652 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7653 rt2800_rfcsr_write(rt2x00dev, 3, 0x62); 7654 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7655 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); 7656 rt2800_rfcsr_write(rt2x00dev, 6, 0x42); 7657 rt2800_rfcsr_write(rt2x00dev, 7, 0x34); 7658 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 7659 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 7660 rt2800_rfcsr_write(rt2x00dev, 10, 0x61); 7661 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7662 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); 7663 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); 7664 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7665 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7666 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); 7667 rt2800_rfcsr_write(rt2x00dev, 17, 0x94); 7668 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); 7669 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); 7670 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); 7671 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); 7672 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7673 rt2800_rfcsr_write(rt2x00dev, 23, 0x14); 7674 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7675 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 7676 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7677 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7678 rt2800_rfcsr_write(rt2x00dev, 28, 0x41); 7679 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); 7680 rt2800_rfcsr_write(rt2x00dev, 30, 0x20); 7681 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); 7682 7683 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7684 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7685 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7686 7687 rt2800_rx_filter_calibration(rt2x00dev); 7688 7689 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) 7690 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7691 7692 rt2800_led_open_drain_enable(rt2x00dev); 7693 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7694 } 7695 7696 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) 7697 { 7698 u8 rfcsr; 7699 u32 reg; 7700 7701 rt2800_rf_init_calibration(rt2x00dev, 30); 7702 7703 rt2800_rfcsr_write(rt2x00dev, 0, 0x70); 7704 rt2800_rfcsr_write(rt2x00dev, 1, 0x81); 7705 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7706 rt2800_rfcsr_write(rt2x00dev, 3, 0x02); 7707 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); 7708 rt2800_rfcsr_write(rt2x00dev, 5, 0x05); 7709 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); 7710 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 7711 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 7712 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 7713 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 7714 rt2800_rfcsr_write(rt2x00dev, 12, 0x70); 7715 rt2800_rfcsr_write(rt2x00dev, 13, 0x65); 7716 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); 7717 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7718 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); 7719 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 7720 rt2800_rfcsr_write(rt2x00dev, 18, 0xac); 7721 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 7722 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 7723 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); 7724 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7725 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); 7726 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7727 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 7728 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7729 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7730 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7731 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 7732 rt2800_rfcsr_write(rt2x00dev, 30, 0x09); 7733 rt2800_rfcsr_write(rt2x00dev, 31, 0x10); 7734 7735 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7736 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7737 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7738 7739 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7740 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7741 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7742 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7743 msleep(1); 7744 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7745 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7746 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7747 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7748 7749 rt2800_rx_filter_calibration(rt2x00dev); 7750 rt2800_led_open_drain_enable(rt2x00dev); 7751 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7752 } 7753 7754 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev) 7755 { 7756 u8 bbp; 7757 bool txbf_enabled = false; /* FIXME */ 7758 7759 bbp = rt2800_bbp_read(rt2x00dev, 105); 7760 if (rt2x00dev->default_ant.rx_chain_num == 1) 7761 rt2x00_set_field8(&bbp, BBP105_MLD, 0); 7762 else 7763 rt2x00_set_field8(&bbp, BBP105_MLD, 1); 7764 rt2800_bbp_write(rt2x00dev, 105, bbp); 7765 7766 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7767 7768 rt2800_bbp_write(rt2x00dev, 92, 0x02); 7769 rt2800_bbp_write(rt2x00dev, 82, 0x82); 7770 rt2800_bbp_write(rt2x00dev, 106, 0x05); 7771 rt2800_bbp_write(rt2x00dev, 104, 0x92); 7772 rt2800_bbp_write(rt2x00dev, 88, 0x90); 7773 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 7774 rt2800_bbp_write(rt2x00dev, 47, 0x48); 7775 rt2800_bbp_write(rt2x00dev, 120, 0x50); 7776 7777 if (txbf_enabled) 7778 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 7779 else 7780 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 7781 7782 /* SNR mapping */ 7783 rt2800_bbp_write(rt2x00dev, 142, 6); 7784 rt2800_bbp_write(rt2x00dev, 143, 160); 7785 rt2800_bbp_write(rt2x00dev, 142, 7); 7786 rt2800_bbp_write(rt2x00dev, 143, 161); 7787 rt2800_bbp_write(rt2x00dev, 142, 8); 7788 rt2800_bbp_write(rt2x00dev, 143, 162); 7789 7790 /* ADC/DAC control */ 7791 rt2800_bbp_write(rt2x00dev, 31, 0x08); 7792 7793 /* RX AGC energy lower bound in log2 */ 7794 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 7795 7796 /* FIXME: BBP 105 owerwrite? */ 7797 rt2800_bbp_write(rt2x00dev, 105, 0x04); 7798 7799 } 7800 7801 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) 7802 { 7803 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7804 u32 reg; 7805 u8 rfcsr; 7806 7807 /* Disable GPIO #4 and #7 function for LAN PE control */ 7808 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7809 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); 7810 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); 7811 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7812 7813 /* Initialize default register values */ 7814 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 7815 rt2800_rfcsr_write(rt2x00dev, 3, 0x80); 7816 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7817 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 7818 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7819 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7820 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 7821 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 7822 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e); 7823 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 7824 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 7825 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7826 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7827 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7828 rt2800_rfcsr_write(rt2x00dev, 32, 0x78); 7829 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b); 7830 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 7831 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0); 7832 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 7833 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 7834 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3); 7835 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 7836 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 7837 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 7838 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 7839 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 7840 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 7841 rt2800_rfcsr_write(rt2x00dev, 53, 0x18); 7842 rt2800_rfcsr_write(rt2x00dev, 54, 0x18); 7843 rt2800_rfcsr_write(rt2x00dev, 55, 0x18); 7844 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 7845 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 7846 7847 /* Initiate calibration */ 7848 /* TODO: use rt2800_rf_init_calibration ? */ 7849 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 7850 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 7851 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 7852 7853 rt2800_freq_cal_mode1(rt2x00dev); 7854 7855 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 7856 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1); 7857 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 7858 7859 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7860 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7861 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7862 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7863 usleep_range(1000, 1500); 7864 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7865 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7866 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7867 7868 /* Set initial values for RX filter calibration */ 7869 drv_data->calibration_bw20 = 0x1f; 7870 drv_data->calibration_bw40 = 0x2f; 7871 7872 /* Save BBP 25 & 26 values for later use in channel switching */ 7873 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 7874 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 7875 7876 rt2800_led_open_drain_enable(rt2x00dev); 7877 rt2800_normal_mode_setup_3593(rt2x00dev); 7878 7879 rt3593_post_bbp_init(rt2x00dev); 7880 7881 /* TODO: enable stream mode support */ 7882 } 7883 7884 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev) 7885 { 7886 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7887 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7888 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7889 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7890 rt2800_rfcsr_write(rt2x00dev, 4, 0x49); 7891 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7892 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 7893 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7894 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7895 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7896 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7897 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7898 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7899 if (rt2800_clk_is_20mhz(rt2x00dev)) 7900 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f); 7901 else 7902 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7903 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7904 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7905 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0); 7906 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7907 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 7908 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7909 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7910 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7911 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7912 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7913 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7914 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7915 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7916 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7917 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0); 7918 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7919 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7920 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7921 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7922 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 7923 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7924 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7925 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 7926 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7927 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7928 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7929 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7930 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7931 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 7932 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c); 7933 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6); 7934 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7935 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7936 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7937 rt2800_rfcsr_write(rt2x00dev, 49, 0x80); 7938 rt2800_rfcsr_write(rt2x00dev, 50, 0x00); 7939 rt2800_rfcsr_write(rt2x00dev, 51, 0x00); 7940 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7941 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7942 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 7943 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7944 rt2800_rfcsr_write(rt2x00dev, 56, 0x82); 7945 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 7946 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 7947 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b); 7948 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7949 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 7950 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7951 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7952 } 7953 7954 static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev) 7955 { 7956 u8 rfcsr; 7957 7958 /* TODO: get the actual ECO value from the SoC */ 7959 const unsigned int eco = 5; 7960 7961 rt2800_rf_init_calibration(rt2x00dev, 2); 7962 7963 rt2800_rfcsr_write(rt2x00dev, 0, 0xe0); 7964 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 7965 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7966 rt2800_rfcsr_write(rt2x00dev, 3, 0x20); 7967 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7968 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7969 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 7970 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7971 rt2800_rfcsr_write(rt2x00dev, 8, 0x5b); 7972 rt2800_rfcsr_write(rt2x00dev, 9, 0x08); 7973 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 7974 rt2800_rfcsr_write(rt2x00dev, 11, 0x48); 7975 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a); 7976 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 7977 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7978 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7979 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 7980 7981 /* RFCSR 17 will be initialized later based on the 7982 * frequency offset stored in the EEPROM 7983 */ 7984 7985 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 7986 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 7987 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7988 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7989 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7990 rt2800_rfcsr_write(rt2x00dev, 23, 0xc0); 7991 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7992 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 7993 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7994 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7995 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7996 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 7997 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7998 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7999 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8000 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8001 rt2800_rfcsr_write(rt2x00dev, 34, 0x20); 8002 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 8003 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8004 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 8005 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 8006 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 8007 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 8008 rt2800_rfcsr_write(rt2x00dev, 41, 0x00); 8009 rt2800_rfcsr_write(rt2x00dev, 42, 0x00); 8010 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 8011 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 8012 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 8013 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 8014 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8015 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 8016 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 8017 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 8018 rt2800_rfcsr_write(rt2x00dev, 51, 0x51); 8019 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 8020 rt2800_rfcsr_write(rt2x00dev, 53, 0x76); 8021 rt2800_rfcsr_write(rt2x00dev, 54, 0x76); 8022 rt2800_rfcsr_write(rt2x00dev, 55, 0x76); 8023 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 8024 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e); 8025 rt2800_rfcsr_write(rt2x00dev, 58, 0x00); 8026 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 8027 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 8028 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 8029 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8030 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8031 8032 /* TODO: rx filter calibration? */ 8033 8034 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 8035 8036 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 8037 8038 rt2800_bbp_write(rt2x00dev, 105, 0x05); 8039 8040 rt2800_bbp_write(rt2x00dev, 179, 0x02); 8041 rt2800_bbp_write(rt2x00dev, 180, 0x00); 8042 rt2800_bbp_write(rt2x00dev, 182, 0x40); 8043 rt2800_bbp_write(rt2x00dev, 180, 0x01); 8044 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 8045 8046 rt2800_bbp_write(rt2x00dev, 179, 0x00); 8047 8048 rt2800_bbp_write(rt2x00dev, 142, 0x04); 8049 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 8050 rt2800_bbp_write(rt2x00dev, 142, 0x06); 8051 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 8052 rt2800_bbp_write(rt2x00dev, 142, 0x07); 8053 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 8054 rt2800_bbp_write(rt2x00dev, 142, 0x08); 8055 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 8056 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 8057 8058 if (eco == 5) { 8059 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8); 8060 rt2800_rfcsr_write(rt2x00dev, 33, 0x32); 8061 } 8062 8063 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 8064 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0); 8065 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 8066 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 8067 msleep(1); 8068 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0); 8069 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 8070 8071 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 8072 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 8073 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 8074 8075 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 8076 rfcsr |= 0xc0; 8077 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 8078 8079 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 8080 rfcsr |= 0x20; 8081 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 8082 8083 rfcsr = rt2800_rfcsr_read(rt2x00dev, 46); 8084 rfcsr |= 0x20; 8085 rt2800_rfcsr_write(rt2x00dev, 46, rfcsr); 8086 8087 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 8088 rfcsr &= ~0xee; 8089 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 8090 } 8091 8092 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) 8093 { 8094 rt2800_rf_init_calibration(rt2x00dev, 2); 8095 8096 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 8097 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 8098 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 8099 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8100 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8101 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8102 else 8103 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 8104 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8105 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8106 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8107 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8108 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8109 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8110 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8111 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8112 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8113 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8114 8115 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8116 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8117 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8118 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 8119 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8120 if (rt2x00_is_usb(rt2x00dev) && 8121 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8122 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8123 else 8124 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); 8125 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8126 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 8127 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8128 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8129 8130 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8131 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8132 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8133 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8134 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8135 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8136 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8137 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8138 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 8139 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8140 8141 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 8142 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8143 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); 8144 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); 8145 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 8146 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 8147 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8148 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8149 else 8150 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); 8151 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8152 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8153 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 8154 8155 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 8156 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8157 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 8158 else 8159 rt2800_rfcsr_write(rt2x00dev, 53, 0x84); 8160 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 8161 rt2800_rfcsr_write(rt2x00dev, 55, 0x44); 8162 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8163 rt2800_rfcsr_write(rt2x00dev, 56, 0x42); 8164 else 8165 rt2800_rfcsr_write(rt2x00dev, 56, 0x22); 8166 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 8167 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 8168 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f); 8169 8170 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8171 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 8172 if (rt2x00_is_usb(rt2x00dev)) 8173 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 8174 else 8175 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5); 8176 } else { 8177 if (rt2x00_is_usb(rt2x00dev)) 8178 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); 8179 else 8180 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5); 8181 } 8182 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8183 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8184 8185 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8186 8187 rt2800_led_open_drain_enable(rt2x00dev); 8188 } 8189 8190 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) 8191 { 8192 rt2800_rf_init_calibration(rt2x00dev, 2); 8193 8194 rt2800_rfcsr_write(rt2x00dev, 1, 0x17); 8195 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 8196 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8197 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8198 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8199 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8200 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8201 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8202 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8203 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8204 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8205 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8206 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8207 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d); 8208 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8209 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d); 8210 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8211 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b); 8212 rt2800_rfcsr_write(rt2x00dev, 24, 0x44); 8213 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8214 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 8215 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 8216 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8217 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8218 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8219 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8220 rt2800_rfcsr_write(rt2x00dev, 32, 0x20); 8221 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 8222 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8223 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8224 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8225 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8226 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 8227 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8228 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f); 8229 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8230 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 8231 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 8232 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 8233 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 8234 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8235 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c); 8236 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8237 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 8238 rt2800_rfcsr_write(rt2x00dev, 50, 0x94); 8239 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a); 8240 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 8241 rt2800_rfcsr_write(rt2x00dev, 53, 0x44); 8242 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 8243 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 8244 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1); 8245 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 8246 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 8247 rt2800_rfcsr_write(rt2x00dev, 59, 0x07); 8248 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8249 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 8250 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 8251 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 8252 8253 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8254 8255 rt2800_led_open_drain_enable(rt2x00dev); 8256 } 8257 8258 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev) 8259 { 8260 rt2800_rf_init_calibration(rt2x00dev, 30); 8261 8262 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F); 8263 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 8264 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8265 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4); 8266 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8267 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8268 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8269 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8270 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8271 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D); 8272 rt2800_rfcsr_write(rt2x00dev, 20, 0x10); 8273 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D); 8274 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 8275 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8276 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8277 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 8278 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8279 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8280 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C); 8281 rt2800_rfcsr_write(rt2x00dev, 53, 0x22); 8282 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 8283 8284 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 8285 msleep(1); 8286 8287 rt2800_freq_cal_mode1(rt2x00dev); 8288 8289 /* Enable DC filter */ 8290 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 8291 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 8292 8293 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8294 8295 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C)) 8296 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 8297 8298 rt2800_led_open_drain_enable(rt2x00dev); 8299 } 8300 8301 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev, 8302 bool set_bw, bool is_ht40) 8303 { 8304 u8 bbp_val; 8305 8306 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 8307 bbp_val |= 0x1; 8308 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 8309 usleep_range(100, 200); 8310 8311 if (set_bw) { 8312 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 8313 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40); 8314 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 8315 usleep_range(100, 200); 8316 } 8317 8318 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 8319 bbp_val &= (~0x1); 8320 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 8321 usleep_range(100, 200); 8322 } 8323 8324 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal) 8325 { 8326 u8 rf_val; 8327 8328 if (btxcal) 8329 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 8330 else 8331 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02); 8332 8333 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06); 8334 8335 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 8336 rf_val |= 0x80; 8337 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val); 8338 8339 if (btxcal) { 8340 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1); 8341 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20); 8342 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 8343 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 8344 rf_val &= (~0x3F); 8345 rf_val |= 0x3F; 8346 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 8347 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8348 rf_val &= (~0x3F); 8349 rf_val |= 0x3F; 8350 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 8351 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31); 8352 } else { 8353 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1); 8354 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18); 8355 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 8356 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 8357 rf_val &= (~0x3F); 8358 rf_val |= 0x34; 8359 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 8360 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8361 rf_val &= (~0x3F); 8362 rf_val |= 0x34; 8363 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 8364 } 8365 8366 return 0; 8367 } 8368 8369 static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev) 8370 { 8371 unsigned int cnt; 8372 u8 bbp_val; 8373 char cal_val; 8374 8375 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82); 8376 8377 cnt = 0; 8378 do { 8379 usleep_range(500, 2000); 8380 bbp_val = rt2800_bbp_read(rt2x00dev, 159); 8381 if (bbp_val == 0x02 || cnt == 20) 8382 break; 8383 8384 cnt++; 8385 } while (cnt < 20); 8386 8387 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39); 8388 cal_val = bbp_val & 0x7F; 8389 if (cal_val >= 0x40) 8390 cal_val -= 128; 8391 8392 return cal_val; 8393 } 8394 8395 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev, 8396 bool btxcal) 8397 { 8398 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 8399 u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc; 8400 u8 filter_target; 8401 u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02; 8402 u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31; 8403 int loop = 0, is_ht40, cnt; 8404 u8 bbp_val, rf_val; 8405 char cal_r32_init, cal_r32_val, cal_diff; 8406 u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05; 8407 u8 saverfb5r06, saverfb5r07; 8408 u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20; 8409 u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41; 8410 u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46; 8411 u8 saverfb5r58, saverfb5r59; 8412 u8 savebbp159r0, savebbp159r2, savebbpr23; 8413 u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0; 8414 8415 /* Save MAC registers */ 8416 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 8417 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 8418 8419 /* save BBP registers */ 8420 savebbpr23 = rt2800_bbp_read(rt2x00dev, 23); 8421 8422 savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0); 8423 savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2); 8424 8425 /* Save RF registers */ 8426 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 8427 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 8428 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 8429 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8430 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5); 8431 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 8432 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 8433 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 8434 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 8435 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 8436 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 8437 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 8438 8439 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37); 8440 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38); 8441 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39); 8442 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40); 8443 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41); 8444 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42); 8445 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43); 8446 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44); 8447 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45); 8448 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46); 8449 8450 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 8451 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 8452 8453 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 8454 rf_val |= 0x3; 8455 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 8456 8457 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 8458 rf_val |= 0x1; 8459 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val); 8460 8461 cnt = 0; 8462 do { 8463 usleep_range(500, 2000); 8464 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 8465 if (((rf_val & 0x1) == 0x00) || (cnt == 40)) 8466 break; 8467 cnt++; 8468 } while (cnt < 40); 8469 8470 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 8471 rf_val &= (~0x3); 8472 rf_val |= 0x1; 8473 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 8474 8475 /* I-3 */ 8476 bbp_val = rt2800_bbp_read(rt2x00dev, 23); 8477 bbp_val &= (~0x1F); 8478 bbp_val |= 0x10; 8479 rt2800_bbp_write(rt2x00dev, 23, bbp_val); 8480 8481 do { 8482 /* I-4,5,6,7,8,9 */ 8483 if (loop == 0) { 8484 is_ht40 = false; 8485 8486 if (btxcal) 8487 filter_target = tx_filter_target_20m; 8488 else 8489 filter_target = rx_filter_target_20m; 8490 } else { 8491 is_ht40 = true; 8492 8493 if (btxcal) 8494 filter_target = tx_filter_target_40m; 8495 else 8496 filter_target = rx_filter_target_40m; 8497 } 8498 8499 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 8500 rf_val &= (~0x04); 8501 if (loop == 1) 8502 rf_val |= 0x4; 8503 8504 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val); 8505 8506 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40); 8507 8508 rt2800_rf_lp_config(rt2x00dev, btxcal); 8509 if (btxcal) { 8510 tx_agc_fc = 0; 8511 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 8512 rf_val &= (~0x7F); 8513 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 8514 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 8515 rf_val &= (~0x7F); 8516 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 8517 } else { 8518 rx_agc_fc = 0; 8519 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 8520 rf_val &= (~0x7F); 8521 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 8522 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 8523 rf_val &= (~0x7F); 8524 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 8525 } 8526 8527 usleep_range(1000, 2000); 8528 8529 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 8530 bbp_val &= (~0x6); 8531 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 8532 8533 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 8534 8535 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 8536 8537 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 8538 bbp_val |= 0x6; 8539 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 8540 do_cal: 8541 if (btxcal) { 8542 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 8543 rf_val &= (~0x7F); 8544 rf_val |= tx_agc_fc; 8545 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 8546 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 8547 rf_val &= (~0x7F); 8548 rf_val |= tx_agc_fc; 8549 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 8550 } else { 8551 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 8552 rf_val &= (~0x7F); 8553 rf_val |= rx_agc_fc; 8554 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 8555 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 8556 rf_val &= (~0x7F); 8557 rf_val |= rx_agc_fc; 8558 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 8559 } 8560 8561 usleep_range(500, 1000); 8562 8563 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 8564 8565 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 8566 8567 cal_diff = cal_r32_init - cal_r32_val; 8568 8569 if (btxcal) 8570 cmm_agc_fc = tx_agc_fc; 8571 else 8572 cmm_agc_fc = rx_agc_fc; 8573 8574 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) || 8575 ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) { 8576 if (btxcal) 8577 tx_agc_fc = 0; 8578 else 8579 rx_agc_fc = 0; 8580 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) { 8581 if (btxcal) 8582 tx_agc_fc++; 8583 else 8584 rx_agc_fc++; 8585 goto do_cal; 8586 } 8587 8588 if (btxcal) { 8589 if (loop == 0) 8590 drv_data->tx_calibration_bw20 = tx_agc_fc; 8591 else 8592 drv_data->tx_calibration_bw40 = tx_agc_fc; 8593 } else { 8594 if (loop == 0) 8595 drv_data->rx_calibration_bw20 = rx_agc_fc; 8596 else 8597 drv_data->rx_calibration_bw40 = rx_agc_fc; 8598 } 8599 8600 loop++; 8601 } while (loop <= 1); 8602 8603 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00); 8604 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01); 8605 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03); 8606 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04); 8607 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05); 8608 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06); 8609 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07); 8610 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08); 8611 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); 8612 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); 8613 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); 8614 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); 8615 8616 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37); 8617 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38); 8618 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39); 8619 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40); 8620 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41); 8621 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42); 8622 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43); 8623 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44); 8624 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45); 8625 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46); 8626 8627 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58); 8628 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59); 8629 8630 rt2800_bbp_write(rt2x00dev, 23, savebbpr23); 8631 8632 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0); 8633 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2); 8634 8635 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 8636 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 8637 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)); 8638 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 8639 8640 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); 8641 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); 8642 } 8643 8644 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev) 8645 { 8646 /* Initialize RF central register to default value */ 8647 rt2800_rfcsr_write(rt2x00dev, 0, 0x02); 8648 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 8649 rt2800_rfcsr_write(rt2x00dev, 2, 0x33); 8650 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF); 8651 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 8652 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 8653 rt2800_rfcsr_write(rt2x00dev, 6, 0x00); 8654 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8655 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 8656 rt2800_rfcsr_write(rt2x00dev, 9, 0x00); 8657 rt2800_rfcsr_write(rt2x00dev, 10, 0x00); 8658 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 8659 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset); 8660 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 8661 rt2800_rfcsr_write(rt2x00dev, 14, 0x40); 8662 rt2800_rfcsr_write(rt2x00dev, 15, 0x22); 8663 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C); 8664 rt2800_rfcsr_write(rt2x00dev, 17, 0x00); 8665 rt2800_rfcsr_write(rt2x00dev, 18, 0x00); 8666 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8667 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0); 8668 rt2800_rfcsr_write(rt2x00dev, 21, 0x12); 8669 rt2800_rfcsr_write(rt2x00dev, 22, 0x07); 8670 rt2800_rfcsr_write(rt2x00dev, 23, 0x13); 8671 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE); 8672 rt2800_rfcsr_write(rt2x00dev, 25, 0x24); 8673 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A); 8674 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8675 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8676 rt2800_rfcsr_write(rt2x00dev, 29, 0x05); 8677 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 8678 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 8679 rt2800_rfcsr_write(rt2x00dev, 32, 0x00); 8680 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8681 rt2800_rfcsr_write(rt2x00dev, 34, 0x00); 8682 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 8683 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8684 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 8685 rt2800_rfcsr_write(rt2x00dev, 38, 0x00); 8686 rt2800_rfcsr_write(rt2x00dev, 39, 0x00); 8687 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 8688 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0); 8689 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B); 8690 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 8691 8692 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 8693 if (rt2800_clk_is_20mhz(rt2x00dev)) 8694 rt2800_rfcsr_write(rt2x00dev, 13, 0x03); 8695 else 8696 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 8697 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C); 8698 rt2800_rfcsr_write(rt2x00dev, 16, 0x80); 8699 rt2800_rfcsr_write(rt2x00dev, 17, 0x99); 8700 rt2800_rfcsr_write(rt2x00dev, 18, 0x99); 8701 rt2800_rfcsr_write(rt2x00dev, 19, 0x09); 8702 rt2800_rfcsr_write(rt2x00dev, 20, 0x50); 8703 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0); 8704 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 8705 rt2800_rfcsr_write(rt2x00dev, 23, 0x06); 8706 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8707 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 8708 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D); 8709 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8710 rt2800_rfcsr_write(rt2x00dev, 28, 0x61); 8711 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5); 8712 rt2800_rfcsr_write(rt2x00dev, 43, 0x02); 8713 8714 rt2800_rfcsr_write(rt2x00dev, 28, 0x62); 8715 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD); 8716 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 8717 8718 /* Initialize RF channel register to default value */ 8719 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03); 8720 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00); 8721 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00); 8722 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00); 8723 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00); 8724 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08); 8725 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00); 8726 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51); 8727 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53); 8728 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16); 8729 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61); 8730 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 8731 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22); 8732 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D); 8733 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 8734 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13); 8735 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22); 8736 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27); 8737 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02); 8738 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 8739 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01); 8740 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52); 8741 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80); 8742 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3); 8743 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00); 8744 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00); 8745 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00); 8746 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00); 8747 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C); 8748 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B); 8749 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B); 8750 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31); 8751 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D); 8752 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00); 8753 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6); 8754 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55); 8755 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00); 8756 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB); 8757 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3); 8758 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3); 8759 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03); 8760 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00); 8761 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00); 8762 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3); 8763 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3); 8764 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 8765 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07); 8766 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68); 8767 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF); 8768 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C); 8769 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07); 8770 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8); 8771 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85); 8772 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10); 8773 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07); 8774 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A); 8775 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85); 8776 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10); 8777 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C); 8778 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00); 8779 8780 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5); 8781 8782 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47); 8783 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71); 8784 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33); 8785 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E); 8786 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23); 8787 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4); 8788 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02); 8789 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12); 8790 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C); 8791 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB); 8792 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D); 8793 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6); 8794 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08); 8795 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4); 8796 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 8797 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3); 8798 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 8799 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); 8800 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67); 8801 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69); 8802 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF); 8803 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27); 8804 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20); 8805 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 8806 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF); 8807 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C); 8808 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20); 8809 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 8810 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7); 8811 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09); 8812 8813 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51); 8814 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 8815 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 8816 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C); 8817 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64); 8818 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51); 8819 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36); 8820 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 8821 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16); 8822 8823 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C); 8824 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC); 8825 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F); 8826 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); 8827 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 8828 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 8829 8830 /* Initialize RF channel register for DRQFN */ 8831 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 8832 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3); 8833 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5); 8834 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28); 8835 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68); 8836 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7); 8837 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02); 8838 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7); 8839 8840 /* Initialize RF DC calibration register to default value */ 8841 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47); 8842 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00); 8843 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00); 8844 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00); 8845 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00); 8846 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 8847 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 8848 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 8849 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 8850 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00); 8851 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07); 8852 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01); 8853 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07); 8854 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07); 8855 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07); 8856 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20); 8857 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22); 8858 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00); 8859 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00); 8860 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00); 8861 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00); 8862 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1); 8863 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11); 8864 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02); 8865 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41); 8866 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20); 8867 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00); 8868 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7); 8869 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2); 8870 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20); 8871 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49); 8872 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20); 8873 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04); 8874 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1); 8875 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1); 8876 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01); 8877 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00); 8878 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00); 8879 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00); 8880 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00); 8881 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00); 8882 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00); 8883 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E); 8884 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D); 8885 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E); 8886 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D); 8887 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E); 8888 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D); 8889 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00); 8890 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00); 8891 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00); 8892 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00); 8893 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00); 8894 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 8895 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 8896 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A); 8897 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00); 8898 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00); 8899 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00); 8900 8901 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08); 8902 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04); 8903 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20); 8904 8905 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 8906 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C); 8907 8908 rt2800_bw_filter_calibration(rt2x00dev, true); 8909 rt2800_bw_filter_calibration(rt2x00dev, false); 8910 } 8911 8912 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) 8913 { 8914 if (rt2800_is_305x_soc(rt2x00dev)) { 8915 rt2800_init_rfcsr_305x_soc(rt2x00dev); 8916 return; 8917 } 8918 8919 switch (rt2x00dev->chip.rt) { 8920 case RT3070: 8921 case RT3071: 8922 case RT3090: 8923 rt2800_init_rfcsr_30xx(rt2x00dev); 8924 break; 8925 case RT3290: 8926 rt2800_init_rfcsr_3290(rt2x00dev); 8927 break; 8928 case RT3352: 8929 rt2800_init_rfcsr_3352(rt2x00dev); 8930 break; 8931 case RT3390: 8932 rt2800_init_rfcsr_3390(rt2x00dev); 8933 break; 8934 case RT3883: 8935 rt2800_init_rfcsr_3883(rt2x00dev); 8936 break; 8937 case RT3572: 8938 rt2800_init_rfcsr_3572(rt2x00dev); 8939 break; 8940 case RT3593: 8941 rt2800_init_rfcsr_3593(rt2x00dev); 8942 break; 8943 case RT5350: 8944 rt2800_init_rfcsr_5350(rt2x00dev); 8945 break; 8946 case RT5390: 8947 rt2800_init_rfcsr_5390(rt2x00dev); 8948 break; 8949 case RT5392: 8950 rt2800_init_rfcsr_5392(rt2x00dev); 8951 break; 8952 case RT5592: 8953 rt2800_init_rfcsr_5592(rt2x00dev); 8954 break; 8955 case RT6352: 8956 rt2800_init_rfcsr_6352(rt2x00dev); 8957 break; 8958 } 8959 } 8960 8961 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) 8962 { 8963 u32 reg; 8964 u16 word; 8965 8966 /* 8967 * Initialize MAC registers. 8968 */ 8969 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || 8970 rt2800_init_registers(rt2x00dev))) 8971 return -EIO; 8972 8973 /* 8974 * Wait BBP/RF to wake up. 8975 */ 8976 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev))) 8977 return -EIO; 8978 8979 /* 8980 * Send signal during boot time to initialize firmware. 8981 */ 8982 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 8983 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 8984 if (rt2x00_is_usb(rt2x00dev)) 8985 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 8986 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 8987 msleep(1); 8988 8989 /* 8990 * Make sure BBP is up and running. 8991 */ 8992 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev))) 8993 return -EIO; 8994 8995 /* 8996 * Initialize BBP/RF registers. 8997 */ 8998 rt2800_init_bbp(rt2x00dev); 8999 rt2800_init_rfcsr(rt2x00dev); 9000 9001 if (rt2x00_is_usb(rt2x00dev) && 9002 (rt2x00_rt(rt2x00dev, RT3070) || 9003 rt2x00_rt(rt2x00dev, RT3071) || 9004 rt2x00_rt(rt2x00dev, RT3572))) { 9005 udelay(200); 9006 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); 9007 udelay(10); 9008 } 9009 9010 /* 9011 * Enable RX. 9012 */ 9013 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9014 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 9015 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 9016 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 9017 9018 udelay(50); 9019 9020 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 9021 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 9022 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 9023 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 9024 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 9025 9026 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9027 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 9028 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); 9029 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 9030 9031 /* 9032 * Initialize LED control 9033 */ 9034 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF); 9035 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, 9036 word & 0xff, (word >> 8) & 0xff); 9037 9038 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF); 9039 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, 9040 word & 0xff, (word >> 8) & 0xff); 9041 9042 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY); 9043 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, 9044 word & 0xff, (word >> 8) & 0xff); 9045 9046 return 0; 9047 } 9048 EXPORT_SYMBOL_GPL(rt2800_enable_radio); 9049 9050 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) 9051 { 9052 u32 reg; 9053 9054 rt2800_disable_wpdma(rt2x00dev); 9055 9056 /* Wait for DMA, ignore error */ 9057 rt2800_wait_wpdma_ready(rt2x00dev); 9058 9059 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9060 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); 9061 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 9062 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 9063 } 9064 EXPORT_SYMBOL_GPL(rt2800_disable_radio); 9065 9066 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 9067 { 9068 u32 reg; 9069 u16 efuse_ctrl_reg; 9070 9071 if (rt2x00_rt(rt2x00dev, RT3290)) 9072 efuse_ctrl_reg = EFUSE_CTRL_3290; 9073 else 9074 efuse_ctrl_reg = EFUSE_CTRL; 9075 9076 reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg); 9077 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); 9078 } 9079 EXPORT_SYMBOL_GPL(rt2800_efuse_detect); 9080 9081 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) 9082 { 9083 u32 reg; 9084 u16 efuse_ctrl_reg; 9085 u16 efuse_data0_reg; 9086 u16 efuse_data1_reg; 9087 u16 efuse_data2_reg; 9088 u16 efuse_data3_reg; 9089 9090 if (rt2x00_rt(rt2x00dev, RT3290)) { 9091 efuse_ctrl_reg = EFUSE_CTRL_3290; 9092 efuse_data0_reg = EFUSE_DATA0_3290; 9093 efuse_data1_reg = EFUSE_DATA1_3290; 9094 efuse_data2_reg = EFUSE_DATA2_3290; 9095 efuse_data3_reg = EFUSE_DATA3_3290; 9096 } else { 9097 efuse_ctrl_reg = EFUSE_CTRL; 9098 efuse_data0_reg = EFUSE_DATA0; 9099 efuse_data1_reg = EFUSE_DATA1; 9100 efuse_data2_reg = EFUSE_DATA2; 9101 efuse_data3_reg = EFUSE_DATA3; 9102 } 9103 mutex_lock(&rt2x00dev->csr_mutex); 9104 9105 reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg); 9106 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); 9107 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); 9108 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); 9109 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); 9110 9111 /* Wait until the EEPROM has been loaded */ 9112 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); 9113 /* Apparently the data is read from end to start */ 9114 reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg); 9115 /* The returned value is in CPU order, but eeprom is le */ 9116 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); 9117 reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg); 9118 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); 9119 reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg); 9120 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); 9121 reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg); 9122 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); 9123 9124 mutex_unlock(&rt2x00dev->csr_mutex); 9125 } 9126 9127 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 9128 { 9129 unsigned int i; 9130 9131 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) 9132 rt2800_efuse_read(rt2x00dev, i); 9133 9134 return 0; 9135 } 9136 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); 9137 9138 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev) 9139 { 9140 u16 word; 9141 9142 if (rt2x00_rt(rt2x00dev, RT3593) || 9143 rt2x00_rt(rt2x00dev, RT3883)) 9144 return 0; 9145 9146 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG); 9147 if ((word & 0x00ff) != 0x00ff) 9148 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL); 9149 9150 return 0; 9151 } 9152 9153 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev) 9154 { 9155 u16 word; 9156 9157 if (rt2x00_rt(rt2x00dev, RT3593) || 9158 rt2x00_rt(rt2x00dev, RT3883)) 9159 return 0; 9160 9161 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A); 9162 if ((word & 0x00ff) != 0x00ff) 9163 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL); 9164 9165 return 0; 9166 } 9167 9168 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) 9169 { 9170 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 9171 u16 word; 9172 u8 *mac; 9173 u8 default_lna_gain; 9174 int retval; 9175 9176 /* 9177 * Read the EEPROM. 9178 */ 9179 retval = rt2800_read_eeprom(rt2x00dev); 9180 if (retval) 9181 return retval; 9182 9183 /* 9184 * Start validation of the data that has been read. 9185 */ 9186 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 9187 rt2x00lib_set_mac_address(rt2x00dev, mac); 9188 9189 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 9190 if (word == 0xffff) { 9191 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 9192 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); 9193 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); 9194 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 9195 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 9196 } else if (rt2x00_rt(rt2x00dev, RT2860) || 9197 rt2x00_rt(rt2x00dev, RT2872)) { 9198 /* 9199 * There is a max of 2 RX streams for RT28x0 series 9200 */ 9201 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2) 9202 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 9203 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 9204 } 9205 9206 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 9207 if (word == 0xffff) { 9208 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); 9209 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); 9210 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0); 9211 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0); 9212 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0); 9213 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0); 9214 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0); 9215 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0); 9216 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0); 9217 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0); 9218 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0); 9219 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0); 9220 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0); 9221 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); 9222 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); 9223 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); 9224 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 9225 } 9226 9227 word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 9228 if ((word & 0x00ff) == 0x00ff) { 9229 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 9230 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 9231 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); 9232 } 9233 if ((word & 0xff00) == 0xff00) { 9234 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, 9235 LED_MODE_TXRX_ACTIVITY); 9236 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); 9237 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 9238 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); 9239 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); 9240 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); 9241 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word); 9242 } 9243 9244 /* 9245 * During the LNA validation we are going to use 9246 * lna0 as correct value. Note that EEPROM_LNA 9247 * is never validated. 9248 */ 9249 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 9250 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); 9251 9252 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 9253 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) 9254 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); 9255 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) 9256 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); 9257 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); 9258 9259 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev); 9260 9261 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 9262 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) 9263 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); 9264 if (!rt2x00_rt(rt2x00dev, RT3593) && 9265 !rt2x00_rt(rt2x00dev, RT3883)) { 9266 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || 9267 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) 9268 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, 9269 default_lna_gain); 9270 } 9271 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); 9272 9273 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev); 9274 9275 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 9276 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) 9277 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); 9278 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) 9279 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); 9280 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); 9281 9282 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 9283 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) 9284 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); 9285 if (!rt2x00_rt(rt2x00dev, RT3593) && 9286 !rt2x00_rt(rt2x00dev, RT3883)) { 9287 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || 9288 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) 9289 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, 9290 default_lna_gain); 9291 } 9292 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); 9293 9294 if (rt2x00_rt(rt2x00dev, RT3593) || 9295 rt2x00_rt(rt2x00dev, RT3883)) { 9296 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 9297 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 || 9298 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff) 9299 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 9300 default_lna_gain); 9301 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 || 9302 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff) 9303 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 9304 default_lna_gain); 9305 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word); 9306 } 9307 9308 return 0; 9309 } 9310 9311 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) 9312 { 9313 u16 value; 9314 u16 eeprom; 9315 u16 rf; 9316 9317 /* 9318 * Read EEPROM word for configuration. 9319 */ 9320 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 9321 9322 /* 9323 * Identify RF chipset by EEPROM value 9324 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 9325 * RT53xx: defined in "EEPROM_CHIP_ID" field 9326 */ 9327 if (rt2x00_rt(rt2x00dev, RT3290) || 9328 rt2x00_rt(rt2x00dev, RT5390) || 9329 rt2x00_rt(rt2x00dev, RT5392) || 9330 rt2x00_rt(rt2x00dev, RT6352)) 9331 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID); 9332 else if (rt2x00_rt(rt2x00dev, RT3352)) 9333 rf = RF3322; 9334 else if (rt2x00_rt(rt2x00dev, RT3883)) 9335 rf = RF3853; 9336 else if (rt2x00_rt(rt2x00dev, RT5350)) 9337 rf = RF5350; 9338 else 9339 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 9340 9341 switch (rf) { 9342 case RF2820: 9343 case RF2850: 9344 case RF2720: 9345 case RF2750: 9346 case RF3020: 9347 case RF2020: 9348 case RF3021: 9349 case RF3022: 9350 case RF3052: 9351 case RF3053: 9352 case RF3070: 9353 case RF3290: 9354 case RF3320: 9355 case RF3322: 9356 case RF3853: 9357 case RF5350: 9358 case RF5360: 9359 case RF5362: 9360 case RF5370: 9361 case RF5372: 9362 case RF5390: 9363 case RF5392: 9364 case RF5592: 9365 case RF7620: 9366 break; 9367 default: 9368 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n", 9369 rf); 9370 return -ENODEV; 9371 } 9372 9373 rt2x00_set_rf(rt2x00dev, rf); 9374 9375 /* 9376 * Identify default antenna configuration. 9377 */ 9378 rt2x00dev->default_ant.tx_chain_num = 9379 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); 9380 rt2x00dev->default_ant.rx_chain_num = 9381 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); 9382 9383 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 9384 9385 if (rt2x00_rt(rt2x00dev, RT3070) || 9386 rt2x00_rt(rt2x00dev, RT3090) || 9387 rt2x00_rt(rt2x00dev, RT3352) || 9388 rt2x00_rt(rt2x00dev, RT3390)) { 9389 value = rt2x00_get_field16(eeprom, 9390 EEPROM_NIC_CONF1_ANT_DIVERSITY); 9391 switch (value) { 9392 case 0: 9393 case 1: 9394 case 2: 9395 rt2x00dev->default_ant.tx = ANTENNA_A; 9396 rt2x00dev->default_ant.rx = ANTENNA_A; 9397 break; 9398 case 3: 9399 rt2x00dev->default_ant.tx = ANTENNA_A; 9400 rt2x00dev->default_ant.rx = ANTENNA_B; 9401 break; 9402 } 9403 } else { 9404 rt2x00dev->default_ant.tx = ANTENNA_A; 9405 rt2x00dev->default_ant.rx = ANTENNA_A; 9406 } 9407 9408 /* These chips have hardware RX antenna diversity */ 9409 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 9410 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 9411 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */ 9412 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */ 9413 } 9414 9415 /* 9416 * Determine external LNA informations. 9417 */ 9418 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G)) 9419 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); 9420 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G)) 9421 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); 9422 9423 /* 9424 * Detect if this device has an hardware controlled radio. 9425 */ 9426 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO)) 9427 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 9428 9429 /* 9430 * Detect if this device has Bluetooth co-existence. 9431 */ 9432 if (!rt2x00_rt(rt2x00dev, RT3352) && 9433 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) 9434 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); 9435 9436 /* 9437 * Read frequency offset and RF programming sequence. 9438 */ 9439 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 9440 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 9441 9442 /* 9443 * Store led settings, for correct led behaviour. 9444 */ 9445 #ifdef CONFIG_RT2X00_LIB_LEDS 9446 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 9447 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 9448 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 9449 9450 rt2x00dev->led_mcu_reg = eeprom; 9451 #endif /* CONFIG_RT2X00_LIB_LEDS */ 9452 9453 /* 9454 * Check if support EIRP tx power limit feature. 9455 */ 9456 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 9457 9458 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < 9459 EIRP_MAX_TX_POWER_LIMIT) 9460 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); 9461 9462 /* 9463 * Detect if device uses internal or external PA 9464 */ 9465 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 9466 9467 if (rt2x00_rt(rt2x00dev, RT3352)) { 9468 if (rt2x00_get_field16(eeprom, 9469 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352)) 9470 __set_bit(CAPABILITY_EXTERNAL_PA_TX0, 9471 &rt2x00dev->cap_flags); 9472 if (rt2x00_get_field16(eeprom, 9473 EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352)) 9474 __set_bit(CAPABILITY_EXTERNAL_PA_TX1, 9475 &rt2x00dev->cap_flags); 9476 } 9477 9478 return 0; 9479 } 9480 9481 /* 9482 * RF value list for rt28xx 9483 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) 9484 */ 9485 static const struct rf_channel rf_vals[] = { 9486 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, 9487 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, 9488 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, 9489 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, 9490 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, 9491 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, 9492 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, 9493 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, 9494 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, 9495 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, 9496 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, 9497 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, 9498 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, 9499 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, 9500 9501 /* 802.11 UNI / HyperLan 2 */ 9502 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, 9503 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, 9504 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, 9505 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, 9506 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, 9507 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, 9508 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, 9509 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, 9510 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, 9511 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, 9512 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, 9513 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, 9514 9515 /* 802.11 HyperLan 2 */ 9516 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, 9517 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, 9518 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, 9519 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, 9520 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, 9521 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, 9522 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, 9523 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, 9524 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, 9525 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, 9526 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, 9527 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, 9528 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, 9529 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, 9530 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, 9531 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, 9532 9533 /* 802.11 UNII */ 9534 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, 9535 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, 9536 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, 9537 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, 9538 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, 9539 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, 9540 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, 9541 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, 9542 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, 9543 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, 9544 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, 9545 9546 /* 802.11 Japan */ 9547 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, 9548 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, 9549 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, 9550 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, 9551 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, 9552 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, 9553 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, 9554 }; 9555 9556 /* 9557 * RF value list for rt3xxx 9558 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053) 9559 */ 9560 static const struct rf_channel rf_vals_3x[] = { 9561 {1, 241, 2, 2 }, 9562 {2, 241, 2, 7 }, 9563 {3, 242, 2, 2 }, 9564 {4, 242, 2, 7 }, 9565 {5, 243, 2, 2 }, 9566 {6, 243, 2, 7 }, 9567 {7, 244, 2, 2 }, 9568 {8, 244, 2, 7 }, 9569 {9, 245, 2, 2 }, 9570 {10, 245, 2, 7 }, 9571 {11, 246, 2, 2 }, 9572 {12, 246, 2, 7 }, 9573 {13, 247, 2, 2 }, 9574 {14, 248, 2, 4 }, 9575 9576 /* 802.11 UNI / HyperLan 2 */ 9577 {36, 0x56, 0, 4}, 9578 {38, 0x56, 0, 6}, 9579 {40, 0x56, 0, 8}, 9580 {44, 0x57, 0, 0}, 9581 {46, 0x57, 0, 2}, 9582 {48, 0x57, 0, 4}, 9583 {52, 0x57, 0, 8}, 9584 {54, 0x57, 0, 10}, 9585 {56, 0x58, 0, 0}, 9586 {60, 0x58, 0, 4}, 9587 {62, 0x58, 0, 6}, 9588 {64, 0x58, 0, 8}, 9589 9590 /* 802.11 HyperLan 2 */ 9591 {100, 0x5b, 0, 8}, 9592 {102, 0x5b, 0, 10}, 9593 {104, 0x5c, 0, 0}, 9594 {108, 0x5c, 0, 4}, 9595 {110, 0x5c, 0, 6}, 9596 {112, 0x5c, 0, 8}, 9597 {116, 0x5d, 0, 0}, 9598 {118, 0x5d, 0, 2}, 9599 {120, 0x5d, 0, 4}, 9600 {124, 0x5d, 0, 8}, 9601 {126, 0x5d, 0, 10}, 9602 {128, 0x5e, 0, 0}, 9603 {132, 0x5e, 0, 4}, 9604 {134, 0x5e, 0, 6}, 9605 {136, 0x5e, 0, 8}, 9606 {140, 0x5f, 0, 0}, 9607 9608 /* 802.11 UNII */ 9609 {149, 0x5f, 0, 9}, 9610 {151, 0x5f, 0, 11}, 9611 {153, 0x60, 0, 1}, 9612 {157, 0x60, 0, 5}, 9613 {159, 0x60, 0, 7}, 9614 {161, 0x60, 0, 9}, 9615 {165, 0x61, 0, 1}, 9616 {167, 0x61, 0, 3}, 9617 {169, 0x61, 0, 5}, 9618 {171, 0x61, 0, 7}, 9619 {173, 0x61, 0, 9}, 9620 }; 9621 9622 /* 9623 * RF value list for rt3xxx with Xtal20MHz 9624 * Supports: 2.4 GHz (all) (RF3322) 9625 */ 9626 static const struct rf_channel rf_vals_3x_xtal20[] = { 9627 {1, 0xE2, 2, 0x14}, 9628 {2, 0xE3, 2, 0x14}, 9629 {3, 0xE4, 2, 0x14}, 9630 {4, 0xE5, 2, 0x14}, 9631 {5, 0xE6, 2, 0x14}, 9632 {6, 0xE7, 2, 0x14}, 9633 {7, 0xE8, 2, 0x14}, 9634 {8, 0xE9, 2, 0x14}, 9635 {9, 0xEA, 2, 0x14}, 9636 {10, 0xEB, 2, 0x14}, 9637 {11, 0xEC, 2, 0x14}, 9638 {12, 0xED, 2, 0x14}, 9639 {13, 0xEE, 2, 0x14}, 9640 {14, 0xF0, 2, 0x18}, 9641 }; 9642 9643 static const struct rf_channel rf_vals_3853[] = { 9644 {1, 241, 6, 2}, 9645 {2, 241, 6, 7}, 9646 {3, 242, 6, 2}, 9647 {4, 242, 6, 7}, 9648 {5, 243, 6, 2}, 9649 {6, 243, 6, 7}, 9650 {7, 244, 6, 2}, 9651 {8, 244, 6, 7}, 9652 {9, 245, 6, 2}, 9653 {10, 245, 6, 7}, 9654 {11, 246, 6, 2}, 9655 {12, 246, 6, 7}, 9656 {13, 247, 6, 2}, 9657 {14, 248, 6, 4}, 9658 9659 {36, 0x56, 8, 4}, 9660 {38, 0x56, 8, 6}, 9661 {40, 0x56, 8, 8}, 9662 {44, 0x57, 8, 0}, 9663 {46, 0x57, 8, 2}, 9664 {48, 0x57, 8, 4}, 9665 {52, 0x57, 8, 8}, 9666 {54, 0x57, 8, 10}, 9667 {56, 0x58, 8, 0}, 9668 {60, 0x58, 8, 4}, 9669 {62, 0x58, 8, 6}, 9670 {64, 0x58, 8, 8}, 9671 9672 {100, 0x5b, 8, 8}, 9673 {102, 0x5b, 8, 10}, 9674 {104, 0x5c, 8, 0}, 9675 {108, 0x5c, 8, 4}, 9676 {110, 0x5c, 8, 6}, 9677 {112, 0x5c, 8, 8}, 9678 {114, 0x5c, 8, 10}, 9679 {116, 0x5d, 8, 0}, 9680 {118, 0x5d, 8, 2}, 9681 {120, 0x5d, 8, 4}, 9682 {124, 0x5d, 8, 8}, 9683 {126, 0x5d, 8, 10}, 9684 {128, 0x5e, 8, 0}, 9685 {132, 0x5e, 8, 4}, 9686 {134, 0x5e, 8, 6}, 9687 {136, 0x5e, 8, 8}, 9688 {140, 0x5f, 8, 0}, 9689 9690 {149, 0x5f, 8, 9}, 9691 {151, 0x5f, 8, 11}, 9692 {153, 0x60, 8, 1}, 9693 {157, 0x60, 8, 5}, 9694 {159, 0x60, 8, 7}, 9695 {161, 0x60, 8, 9}, 9696 {165, 0x61, 8, 1}, 9697 {167, 0x61, 8, 3}, 9698 {169, 0x61, 8, 5}, 9699 {171, 0x61, 8, 7}, 9700 {173, 0x61, 8, 9}, 9701 }; 9702 9703 static const struct rf_channel rf_vals_5592_xtal20[] = { 9704 /* Channel, N, K, mod, R */ 9705 {1, 482, 4, 10, 3}, 9706 {2, 483, 4, 10, 3}, 9707 {3, 484, 4, 10, 3}, 9708 {4, 485, 4, 10, 3}, 9709 {5, 486, 4, 10, 3}, 9710 {6, 487, 4, 10, 3}, 9711 {7, 488, 4, 10, 3}, 9712 {8, 489, 4, 10, 3}, 9713 {9, 490, 4, 10, 3}, 9714 {10, 491, 4, 10, 3}, 9715 {11, 492, 4, 10, 3}, 9716 {12, 493, 4, 10, 3}, 9717 {13, 494, 4, 10, 3}, 9718 {14, 496, 8, 10, 3}, 9719 {36, 172, 8, 12, 1}, 9720 {38, 173, 0, 12, 1}, 9721 {40, 173, 4, 12, 1}, 9722 {42, 173, 8, 12, 1}, 9723 {44, 174, 0, 12, 1}, 9724 {46, 174, 4, 12, 1}, 9725 {48, 174, 8, 12, 1}, 9726 {50, 175, 0, 12, 1}, 9727 {52, 175, 4, 12, 1}, 9728 {54, 175, 8, 12, 1}, 9729 {56, 176, 0, 12, 1}, 9730 {58, 176, 4, 12, 1}, 9731 {60, 176, 8, 12, 1}, 9732 {62, 177, 0, 12, 1}, 9733 {64, 177, 4, 12, 1}, 9734 {100, 183, 4, 12, 1}, 9735 {102, 183, 8, 12, 1}, 9736 {104, 184, 0, 12, 1}, 9737 {106, 184, 4, 12, 1}, 9738 {108, 184, 8, 12, 1}, 9739 {110, 185, 0, 12, 1}, 9740 {112, 185, 4, 12, 1}, 9741 {114, 185, 8, 12, 1}, 9742 {116, 186, 0, 12, 1}, 9743 {118, 186, 4, 12, 1}, 9744 {120, 186, 8, 12, 1}, 9745 {122, 187, 0, 12, 1}, 9746 {124, 187, 4, 12, 1}, 9747 {126, 187, 8, 12, 1}, 9748 {128, 188, 0, 12, 1}, 9749 {130, 188, 4, 12, 1}, 9750 {132, 188, 8, 12, 1}, 9751 {134, 189, 0, 12, 1}, 9752 {136, 189, 4, 12, 1}, 9753 {138, 189, 8, 12, 1}, 9754 {140, 190, 0, 12, 1}, 9755 {149, 191, 6, 12, 1}, 9756 {151, 191, 10, 12, 1}, 9757 {153, 192, 2, 12, 1}, 9758 {155, 192, 6, 12, 1}, 9759 {157, 192, 10, 12, 1}, 9760 {159, 193, 2, 12, 1}, 9761 {161, 193, 6, 12, 1}, 9762 {165, 194, 2, 12, 1}, 9763 {184, 164, 0, 12, 1}, 9764 {188, 164, 4, 12, 1}, 9765 {192, 165, 8, 12, 1}, 9766 {196, 166, 0, 12, 1}, 9767 }; 9768 9769 static const struct rf_channel rf_vals_5592_xtal40[] = { 9770 /* Channel, N, K, mod, R */ 9771 {1, 241, 2, 10, 3}, 9772 {2, 241, 7, 10, 3}, 9773 {3, 242, 2, 10, 3}, 9774 {4, 242, 7, 10, 3}, 9775 {5, 243, 2, 10, 3}, 9776 {6, 243, 7, 10, 3}, 9777 {7, 244, 2, 10, 3}, 9778 {8, 244, 7, 10, 3}, 9779 {9, 245, 2, 10, 3}, 9780 {10, 245, 7, 10, 3}, 9781 {11, 246, 2, 10, 3}, 9782 {12, 246, 7, 10, 3}, 9783 {13, 247, 2, 10, 3}, 9784 {14, 248, 4, 10, 3}, 9785 {36, 86, 4, 12, 1}, 9786 {38, 86, 6, 12, 1}, 9787 {40, 86, 8, 12, 1}, 9788 {42, 86, 10, 12, 1}, 9789 {44, 87, 0, 12, 1}, 9790 {46, 87, 2, 12, 1}, 9791 {48, 87, 4, 12, 1}, 9792 {50, 87, 6, 12, 1}, 9793 {52, 87, 8, 12, 1}, 9794 {54, 87, 10, 12, 1}, 9795 {56, 88, 0, 12, 1}, 9796 {58, 88, 2, 12, 1}, 9797 {60, 88, 4, 12, 1}, 9798 {62, 88, 6, 12, 1}, 9799 {64, 88, 8, 12, 1}, 9800 {100, 91, 8, 12, 1}, 9801 {102, 91, 10, 12, 1}, 9802 {104, 92, 0, 12, 1}, 9803 {106, 92, 2, 12, 1}, 9804 {108, 92, 4, 12, 1}, 9805 {110, 92, 6, 12, 1}, 9806 {112, 92, 8, 12, 1}, 9807 {114, 92, 10, 12, 1}, 9808 {116, 93, 0, 12, 1}, 9809 {118, 93, 2, 12, 1}, 9810 {120, 93, 4, 12, 1}, 9811 {122, 93, 6, 12, 1}, 9812 {124, 93, 8, 12, 1}, 9813 {126, 93, 10, 12, 1}, 9814 {128, 94, 0, 12, 1}, 9815 {130, 94, 2, 12, 1}, 9816 {132, 94, 4, 12, 1}, 9817 {134, 94, 6, 12, 1}, 9818 {136, 94, 8, 12, 1}, 9819 {138, 94, 10, 12, 1}, 9820 {140, 95, 0, 12, 1}, 9821 {149, 95, 9, 12, 1}, 9822 {151, 95, 11, 12, 1}, 9823 {153, 96, 1, 12, 1}, 9824 {155, 96, 3, 12, 1}, 9825 {157, 96, 5, 12, 1}, 9826 {159, 96, 7, 12, 1}, 9827 {161, 96, 9, 12, 1}, 9828 {165, 97, 1, 12, 1}, 9829 {184, 82, 0, 12, 1}, 9830 {188, 82, 4, 12, 1}, 9831 {192, 82, 8, 12, 1}, 9832 {196, 83, 0, 12, 1}, 9833 }; 9834 9835 static const struct rf_channel rf_vals_7620[] = { 9836 {1, 0x50, 0x99, 0x99, 1}, 9837 {2, 0x50, 0x44, 0x44, 2}, 9838 {3, 0x50, 0xEE, 0xEE, 2}, 9839 {4, 0x50, 0x99, 0x99, 3}, 9840 {5, 0x51, 0x44, 0x44, 0}, 9841 {6, 0x51, 0xEE, 0xEE, 0}, 9842 {7, 0x51, 0x99, 0x99, 1}, 9843 {8, 0x51, 0x44, 0x44, 2}, 9844 {9, 0x51, 0xEE, 0xEE, 2}, 9845 {10, 0x51, 0x99, 0x99, 3}, 9846 {11, 0x52, 0x44, 0x44, 0}, 9847 {12, 0x52, 0xEE, 0xEE, 0}, 9848 {13, 0x52, 0x99, 0x99, 1}, 9849 {14, 0x52, 0x33, 0x33, 3}, 9850 }; 9851 9852 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 9853 { 9854 struct hw_mode_spec *spec = &rt2x00dev->spec; 9855 struct channel_info *info; 9856 char *default_power1; 9857 char *default_power2; 9858 char *default_power3; 9859 unsigned int i, tx_chains, rx_chains; 9860 u32 reg; 9861 9862 /* 9863 * Disable powersaving as default. 9864 */ 9865 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 9866 9867 /* 9868 * Change default retry settings to values corresponding more closely 9869 * to rate[0].count setting of minstrel rate control algorithm. 9870 */ 9871 rt2x00dev->hw->wiphy->retry_short = 2; 9872 rt2x00dev->hw->wiphy->retry_long = 2; 9873 9874 /* 9875 * Initialize all hw fields. 9876 */ 9877 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS); 9878 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION); 9879 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); 9880 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); 9881 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); 9882 9883 /* 9884 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices 9885 * unless we are capable of sending the buffered frames out after the 9886 * DTIM transmission using rt2x00lib_beacondone. This will send out 9887 * multicast and broadcast traffic immediately instead of buffering it 9888 * infinitly and thus dropping it after some time. 9889 */ 9890 if (!rt2x00_is_usb(rt2x00dev)) 9891 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); 9892 9893 /* Set MFP if HW crypto is disabled. */ 9894 if (rt2800_hwcrypt_disabled(rt2x00dev)) 9895 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE); 9896 9897 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 9898 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 9899 rt2800_eeprom_addr(rt2x00dev, 9900 EEPROM_MAC_ADDR_0)); 9901 9902 /* 9903 * As rt2800 has a global fallback table we cannot specify 9904 * more then one tx rate per frame but since the hw will 9905 * try several rates (based on the fallback table) we should 9906 * initialize max_report_rates to the maximum number of rates 9907 * we are going to try. Otherwise mac80211 will truncate our 9908 * reported tx rates and the rc algortihm will end up with 9909 * incorrect data. 9910 */ 9911 rt2x00dev->hw->max_rates = 1; 9912 rt2x00dev->hw->max_report_rates = 7; 9913 rt2x00dev->hw->max_rate_tries = 1; 9914 9915 /* 9916 * Initialize hw_mode information. 9917 */ 9918 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 9919 9920 switch (rt2x00dev->chip.rf) { 9921 case RF2720: 9922 case RF2820: 9923 spec->num_channels = 14; 9924 spec->channels = rf_vals; 9925 break; 9926 9927 case RF2750: 9928 case RF2850: 9929 spec->num_channels = ARRAY_SIZE(rf_vals); 9930 spec->channels = rf_vals; 9931 break; 9932 9933 case RF2020: 9934 case RF3020: 9935 case RF3021: 9936 case RF3022: 9937 case RF3070: 9938 case RF3290: 9939 case RF3320: 9940 case RF3322: 9941 case RF5350: 9942 case RF5360: 9943 case RF5362: 9944 case RF5370: 9945 case RF5372: 9946 case RF5390: 9947 case RF5392: 9948 spec->num_channels = 14; 9949 if (rt2800_clk_is_20mhz(rt2x00dev)) 9950 spec->channels = rf_vals_3x_xtal20; 9951 else 9952 spec->channels = rf_vals_3x; 9953 break; 9954 9955 case RF7620: 9956 spec->num_channels = ARRAY_SIZE(rf_vals_7620); 9957 spec->channels = rf_vals_7620; 9958 break; 9959 9960 case RF3052: 9961 case RF3053: 9962 spec->num_channels = ARRAY_SIZE(rf_vals_3x); 9963 spec->channels = rf_vals_3x; 9964 break; 9965 9966 case RF3853: 9967 spec->num_channels = ARRAY_SIZE(rf_vals_3853); 9968 spec->channels = rf_vals_3853; 9969 break; 9970 9971 case RF5592: 9972 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX); 9973 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { 9974 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); 9975 spec->channels = rf_vals_5592_xtal40; 9976 } else { 9977 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20); 9978 spec->channels = rf_vals_5592_xtal20; 9979 } 9980 break; 9981 } 9982 9983 if (WARN_ON_ONCE(!spec->channels)) 9984 return -ENODEV; 9985 9986 spec->supported_bands = SUPPORT_BAND_2GHZ; 9987 if (spec->num_channels > 14) 9988 spec->supported_bands |= SUPPORT_BAND_5GHZ; 9989 9990 /* 9991 * Initialize HT information. 9992 */ 9993 if (!rt2x00_rf(rt2x00dev, RF2020)) 9994 spec->ht.ht_supported = true; 9995 else 9996 spec->ht.ht_supported = false; 9997 9998 spec->ht.cap = 9999 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 10000 IEEE80211_HT_CAP_GRN_FLD | 10001 IEEE80211_HT_CAP_SGI_20 | 10002 IEEE80211_HT_CAP_SGI_40; 10003 10004 tx_chains = rt2x00dev->default_ant.tx_chain_num; 10005 rx_chains = rt2x00dev->default_ant.rx_chain_num; 10006 10007 if (tx_chains >= 2) 10008 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; 10009 10010 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT; 10011 10012 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2; 10013 spec->ht.ampdu_density = 4; 10014 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 10015 if (tx_chains != rx_chains) { 10016 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 10017 spec->ht.mcs.tx_params |= 10018 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; 10019 } 10020 10021 switch (rx_chains) { 10022 case 3: 10023 spec->ht.mcs.rx_mask[2] = 0xff; 10024 /* fall through */ 10025 case 2: 10026 spec->ht.mcs.rx_mask[1] = 0xff; 10027 /* fall through */ 10028 case 1: 10029 spec->ht.mcs.rx_mask[0] = 0xff; 10030 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ 10031 break; 10032 } 10033 10034 /* 10035 * Create channel information array 10036 */ 10037 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 10038 if (!info) 10039 return -ENOMEM; 10040 10041 spec->channels_info = info; 10042 10043 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 10044 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 10045 10046 if (rt2x00dev->default_ant.tx_chain_num > 2) 10047 default_power3 = rt2800_eeprom_addr(rt2x00dev, 10048 EEPROM_EXT_TXPOWER_BG3); 10049 else 10050 default_power3 = NULL; 10051 10052 for (i = 0; i < 14; i++) { 10053 info[i].default_power1 = default_power1[i]; 10054 info[i].default_power2 = default_power2[i]; 10055 if (default_power3) 10056 info[i].default_power3 = default_power3[i]; 10057 } 10058 10059 if (spec->num_channels > 14) { 10060 default_power1 = rt2800_eeprom_addr(rt2x00dev, 10061 EEPROM_TXPOWER_A1); 10062 default_power2 = rt2800_eeprom_addr(rt2x00dev, 10063 EEPROM_TXPOWER_A2); 10064 10065 if (rt2x00dev->default_ant.tx_chain_num > 2) 10066 default_power3 = 10067 rt2800_eeprom_addr(rt2x00dev, 10068 EEPROM_EXT_TXPOWER_A3); 10069 else 10070 default_power3 = NULL; 10071 10072 for (i = 14; i < spec->num_channels; i++) { 10073 info[i].default_power1 = default_power1[i - 14]; 10074 info[i].default_power2 = default_power2[i - 14]; 10075 if (default_power3) 10076 info[i].default_power3 = default_power3[i - 14]; 10077 } 10078 } 10079 10080 switch (rt2x00dev->chip.rf) { 10081 case RF2020: 10082 case RF3020: 10083 case RF3021: 10084 case RF3022: 10085 case RF3320: 10086 case RF3052: 10087 case RF3053: 10088 case RF3070: 10089 case RF3290: 10090 case RF3853: 10091 case RF5350: 10092 case RF5360: 10093 case RF5362: 10094 case RF5370: 10095 case RF5372: 10096 case RF5390: 10097 case RF5392: 10098 case RF5592: 10099 case RF7620: 10100 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags); 10101 break; 10102 } 10103 10104 return 0; 10105 } 10106 10107 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) 10108 { 10109 u32 reg; 10110 u32 rt; 10111 u32 rev; 10112 10113 if (rt2x00_rt(rt2x00dev, RT3290)) 10114 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290); 10115 else 10116 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 10117 10118 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); 10119 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); 10120 10121 switch (rt) { 10122 case RT2860: 10123 case RT2872: 10124 case RT2883: 10125 case RT3070: 10126 case RT3071: 10127 case RT3090: 10128 case RT3290: 10129 case RT3352: 10130 case RT3390: 10131 case RT3572: 10132 case RT3593: 10133 case RT3883: 10134 case RT5350: 10135 case RT5390: 10136 case RT5392: 10137 case RT5592: 10138 break; 10139 default: 10140 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n", 10141 rt, rev); 10142 return -ENODEV; 10143 } 10144 10145 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev)) 10146 rt = RT6352; 10147 10148 rt2x00_set_rt(rt2x00dev, rt, rev); 10149 10150 return 0; 10151 } 10152 10153 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) 10154 { 10155 int retval; 10156 u32 reg; 10157 10158 retval = rt2800_probe_rt(rt2x00dev); 10159 if (retval) 10160 return retval; 10161 10162 /* 10163 * Allocate eeprom data. 10164 */ 10165 retval = rt2800_validate_eeprom(rt2x00dev); 10166 if (retval) 10167 return retval; 10168 10169 retval = rt2800_init_eeprom(rt2x00dev); 10170 if (retval) 10171 return retval; 10172 10173 /* 10174 * Enable rfkill polling by setting GPIO direction of the 10175 * rfkill switch GPIO pin correctly. 10176 */ 10177 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 10178 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); 10179 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 10180 10181 /* 10182 * Initialize hw specifications. 10183 */ 10184 retval = rt2800_probe_hw_mode(rt2x00dev); 10185 if (retval) 10186 return retval; 10187 10188 /* 10189 * Set device capabilities. 10190 */ 10191 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); 10192 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags); 10193 if (!rt2x00_is_usb(rt2x00dev)) 10194 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags); 10195 10196 /* 10197 * Set device requirements. 10198 */ 10199 if (!rt2x00_is_soc(rt2x00dev)) 10200 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); 10201 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags); 10202 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags); 10203 if (!rt2800_hwcrypt_disabled(rt2x00dev)) 10204 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); 10205 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 10206 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags); 10207 if (rt2x00_is_usb(rt2x00dev)) 10208 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); 10209 else { 10210 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); 10211 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags); 10212 } 10213 10214 /* 10215 * Set the rssi offset. 10216 */ 10217 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 10218 10219 return 0; 10220 } 10221 EXPORT_SYMBOL_GPL(rt2800_probe_hw); 10222 10223 /* 10224 * IEEE80211 stack callback functions. 10225 */ 10226 void rt2800_get_key_seq(struct ieee80211_hw *hw, 10227 struct ieee80211_key_conf *key, 10228 struct ieee80211_key_seq *seq) 10229 { 10230 struct rt2x00_dev *rt2x00dev = hw->priv; 10231 struct mac_iveiv_entry iveiv_entry; 10232 u32 offset; 10233 10234 if (key->cipher != WLAN_CIPHER_SUITE_TKIP) 10235 return; 10236 10237 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 10238 rt2800_register_multiread(rt2x00dev, offset, 10239 &iveiv_entry, sizeof(iveiv_entry)); 10240 10241 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2); 10242 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4); 10243 } 10244 EXPORT_SYMBOL_GPL(rt2800_get_key_seq); 10245 10246 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) 10247 { 10248 struct rt2x00_dev *rt2x00dev = hw->priv; 10249 u32 reg; 10250 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); 10251 10252 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 10253 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); 10254 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 10255 10256 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 10257 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); 10258 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 10259 10260 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 10261 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); 10262 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 10263 10264 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 10265 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); 10266 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 10267 10268 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 10269 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); 10270 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 10271 10272 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 10273 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); 10274 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 10275 10276 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 10277 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); 10278 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 10279 10280 return 0; 10281 } 10282 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold); 10283 10284 int rt2800_conf_tx(struct ieee80211_hw *hw, 10285 struct ieee80211_vif *vif, u16 queue_idx, 10286 const struct ieee80211_tx_queue_params *params) 10287 { 10288 struct rt2x00_dev *rt2x00dev = hw->priv; 10289 struct data_queue *queue; 10290 struct rt2x00_field32 field; 10291 int retval; 10292 u32 reg; 10293 u32 offset; 10294 10295 /* 10296 * First pass the configuration through rt2x00lib, that will 10297 * update the queue settings and validate the input. After that 10298 * we are free to update the registers based on the value 10299 * in the queue parameter. 10300 */ 10301 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params); 10302 if (retval) 10303 return retval; 10304 10305 /* 10306 * We only need to perform additional register initialization 10307 * for WMM queues/ 10308 */ 10309 if (queue_idx >= 4) 10310 return 0; 10311 10312 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 10313 10314 /* Update WMM TXOP register */ 10315 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); 10316 field.bit_offset = (queue_idx & 1) * 16; 10317 field.bit_mask = 0xffff << field.bit_offset; 10318 10319 reg = rt2800_register_read(rt2x00dev, offset); 10320 rt2x00_set_field32(®, field, queue->txop); 10321 rt2800_register_write(rt2x00dev, offset, reg); 10322 10323 /* Update WMM registers */ 10324 field.bit_offset = queue_idx * 4; 10325 field.bit_mask = 0xf << field.bit_offset; 10326 10327 reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG); 10328 rt2x00_set_field32(®, field, queue->aifs); 10329 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); 10330 10331 reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG); 10332 rt2x00_set_field32(®, field, queue->cw_min); 10333 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); 10334 10335 reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG); 10336 rt2x00_set_field32(®, field, queue->cw_max); 10337 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); 10338 10339 /* Update EDCA registers */ 10340 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); 10341 10342 reg = rt2800_register_read(rt2x00dev, offset); 10343 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); 10344 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); 10345 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); 10346 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); 10347 rt2800_register_write(rt2x00dev, offset, reg); 10348 10349 return 0; 10350 } 10351 EXPORT_SYMBOL_GPL(rt2800_conf_tx); 10352 10353 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 10354 { 10355 struct rt2x00_dev *rt2x00dev = hw->priv; 10356 u64 tsf; 10357 u32 reg; 10358 10359 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1); 10360 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; 10361 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0); 10362 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); 10363 10364 return tsf; 10365 } 10366 EXPORT_SYMBOL_GPL(rt2800_get_tsf); 10367 10368 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 10369 struct ieee80211_ampdu_params *params) 10370 { 10371 struct ieee80211_sta *sta = params->sta; 10372 enum ieee80211_ampdu_mlme_action action = params->action; 10373 u16 tid = params->tid; 10374 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv; 10375 int ret = 0; 10376 10377 /* 10378 * Don't allow aggregation for stations the hardware isn't aware 10379 * of because tx status reports for frames to an unknown station 10380 * always contain wcid=WCID_END+1 and thus we can't distinguish 10381 * between multiple stations which leads to unwanted situations 10382 * when the hw reorders frames due to aggregation. 10383 */ 10384 if (sta_priv->wcid > WCID_END) 10385 return 1; 10386 10387 switch (action) { 10388 case IEEE80211_AMPDU_RX_START: 10389 case IEEE80211_AMPDU_RX_STOP: 10390 /* 10391 * The hw itself takes care of setting up BlockAck mechanisms. 10392 * So, we only have to allow mac80211 to nagotiate a BlockAck 10393 * agreement. Once that is done, the hw will BlockAck incoming 10394 * AMPDUs without further setup. 10395 */ 10396 break; 10397 case IEEE80211_AMPDU_TX_START: 10398 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 10399 break; 10400 case IEEE80211_AMPDU_TX_STOP_CONT: 10401 case IEEE80211_AMPDU_TX_STOP_FLUSH: 10402 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 10403 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 10404 break; 10405 case IEEE80211_AMPDU_TX_OPERATIONAL: 10406 break; 10407 default: 10408 rt2x00_warn((struct rt2x00_dev *)hw->priv, 10409 "Unknown AMPDU action\n"); 10410 } 10411 10412 return ret; 10413 } 10414 EXPORT_SYMBOL_GPL(rt2800_ampdu_action); 10415 10416 int rt2800_get_survey(struct ieee80211_hw *hw, int idx, 10417 struct survey_info *survey) 10418 { 10419 struct rt2x00_dev *rt2x00dev = hw->priv; 10420 struct ieee80211_conf *conf = &hw->conf; 10421 u32 idle, busy, busy_ext; 10422 10423 if (idx != 0) 10424 return -ENOENT; 10425 10426 survey->channel = conf->chandef.chan; 10427 10428 idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 10429 busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 10430 busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 10431 10432 if (idle || busy) { 10433 survey->filled = SURVEY_INFO_TIME | 10434 SURVEY_INFO_TIME_BUSY | 10435 SURVEY_INFO_TIME_EXT_BUSY; 10436 10437 survey->time = (idle + busy) / 1000; 10438 survey->time_busy = busy / 1000; 10439 survey->time_ext_busy = busy_ext / 1000; 10440 } 10441 10442 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 10443 survey->filled |= SURVEY_INFO_IN_USE; 10444 10445 return 0; 10446 10447 } 10448 EXPORT_SYMBOL_GPL(rt2800_get_survey); 10449 10450 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); 10451 MODULE_VERSION(DRV_VERSION); 10452 MODULE_DESCRIPTION("Ralink RT2800 library"); 10453 MODULE_LICENSE("GPL"); 10454