1 /*
2 	Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 	Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 	Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 	Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6 
7 	Based on the original rt2800pci.c and rt2800usb.c.
8 	  Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 	  Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 	  Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 	  Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 	  Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 	  Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 	  <http://rt2x00.serialmonkey.com>
15 
16 	This program is free software; you can redistribute it and/or modify
17 	it under the terms of the GNU General Public License as published by
18 	the Free Software Foundation; either version 2 of the License, or
19 	(at your option) any later version.
20 
21 	This program is distributed in the hope that it will be useful,
22 	but WITHOUT ANY WARRANTY; without even the implied warranty of
23 	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 	GNU General Public License for more details.
25 
26 	You should have received a copy of the GNU General Public License
27 	along with this program; if not, see <http://www.gnu.org/licenses/>.
28  */
29 
30 /*
31 	Module: rt2800lib
32 	Abstract: rt2800 generic device routines.
33  */
34 
35 #include <linux/crc-ccitt.h>
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/slab.h>
39 
40 #include "rt2x00.h"
41 #include "rt2800lib.h"
42 #include "rt2800.h"
43 
44 /*
45  * Register access.
46  * All access to the CSR registers will go through the methods
47  * rt2800_register_read and rt2800_register_write.
48  * BBP and RF register require indirect register access,
49  * and use the CSR registers BBPCSR and RFCSR to achieve this.
50  * These indirect registers work with busy bits,
51  * and we will try maximal REGISTER_BUSY_COUNT times to access
52  * the register while taking a REGISTER_BUSY_DELAY us delay
53  * between each attampt. When the busy bit is still set at that time,
54  * the access attempt is considered to have failed,
55  * and we will print an error.
56  * The _lock versions must be used if you already hold the csr_mutex
57  */
58 #define WAIT_FOR_BBP(__dev, __reg) \
59 	rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
60 #define WAIT_FOR_RFCSR(__dev, __reg) \
61 	rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
63 	rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
64 			    (__reg))
65 #define WAIT_FOR_RF(__dev, __reg) \
66 	rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
67 #define WAIT_FOR_MCU(__dev, __reg) \
68 	rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
69 			    H2M_MAILBOX_CSR_OWNER, (__reg))
70 
71 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
72 {
73 	/* check for rt2872 on SoC */
74 	if (!rt2x00_is_soc(rt2x00dev) ||
75 	    !rt2x00_rt(rt2x00dev, RT2872))
76 		return false;
77 
78 	/* we know for sure that these rf chipsets are used on rt305x boards */
79 	if (rt2x00_rf(rt2x00dev, RF3020) ||
80 	    rt2x00_rf(rt2x00dev, RF3021) ||
81 	    rt2x00_rf(rt2x00dev, RF3022))
82 		return true;
83 
84 	rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
85 	return false;
86 }
87 
88 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
89 			     const unsigned int word, const u8 value)
90 {
91 	u32 reg;
92 
93 	mutex_lock(&rt2x00dev->csr_mutex);
94 
95 	/*
96 	 * Wait until the BBP becomes available, afterwards we
97 	 * can safely write the new data into the register.
98 	 */
99 	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
100 		reg = 0;
101 		rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
102 		rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
103 		rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
104 		rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
105 		rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
106 
107 		rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
108 	}
109 
110 	mutex_unlock(&rt2x00dev->csr_mutex);
111 }
112 
113 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word)
114 {
115 	u32 reg;
116 	u8 value;
117 
118 	mutex_lock(&rt2x00dev->csr_mutex);
119 
120 	/*
121 	 * Wait until the BBP becomes available, afterwards we
122 	 * can safely write the read request into the register.
123 	 * After the data has been written, we wait until hardware
124 	 * returns the correct value, if at any time the register
125 	 * doesn't become available in time, reg will be 0xffffffff
126 	 * which means we return 0xff to the caller.
127 	 */
128 	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
129 		reg = 0;
130 		rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
131 		rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
132 		rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
133 		rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
134 
135 		rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
136 
137 		WAIT_FOR_BBP(rt2x00dev, &reg);
138 	}
139 
140 	value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
141 
142 	mutex_unlock(&rt2x00dev->csr_mutex);
143 
144 	return value;
145 }
146 
147 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
148 			       const unsigned int word, const u8 value)
149 {
150 	u32 reg;
151 
152 	mutex_lock(&rt2x00dev->csr_mutex);
153 
154 	/*
155 	 * Wait until the RFCSR becomes available, afterwards we
156 	 * can safely write the new data into the register.
157 	 */
158 	switch (rt2x00dev->chip.rt) {
159 	case RT6352:
160 		if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
161 			reg = 0;
162 			rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
163 			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
164 					   word);
165 			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
166 			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
167 
168 			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
169 		}
170 		break;
171 
172 	default:
173 		if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
174 			reg = 0;
175 			rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
176 			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
177 			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
178 			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
179 
180 			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
181 		}
182 		break;
183 	}
184 
185 	mutex_unlock(&rt2x00dev->csr_mutex);
186 }
187 
188 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
189 				    const unsigned int reg, const u8 value)
190 {
191 	rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
192 }
193 
194 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
195 				       const unsigned int reg, const u8 value)
196 {
197 	rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
198 	rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
199 }
200 
201 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
202 				     const unsigned int reg, const u8 value)
203 {
204 	rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
205 	rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
206 }
207 
208 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
209 			    const unsigned int word)
210 {
211 	u32 reg;
212 	u8 value;
213 
214 	mutex_lock(&rt2x00dev->csr_mutex);
215 
216 	/*
217 	 * Wait until the RFCSR becomes available, afterwards we
218 	 * can safely write the read request into the register.
219 	 * After the data has been written, we wait until hardware
220 	 * returns the correct value, if at any time the register
221 	 * doesn't become available in time, reg will be 0xffffffff
222 	 * which means we return 0xff to the caller.
223 	 */
224 	switch (rt2x00dev->chip.rt) {
225 	case RT6352:
226 		if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
227 			reg = 0;
228 			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
229 					   word);
230 			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
231 			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
232 
233 			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
234 
235 			WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
236 		}
237 
238 		value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
239 		break;
240 
241 	default:
242 		if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
243 			reg = 0;
244 			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
245 			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
246 			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
247 
248 			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
249 
250 			WAIT_FOR_RFCSR(rt2x00dev, &reg);
251 		}
252 
253 		value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
254 		break;
255 	}
256 
257 	mutex_unlock(&rt2x00dev->csr_mutex);
258 
259 	return value;
260 }
261 
262 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
263 				 const unsigned int reg)
264 {
265 	return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)));
266 }
267 
268 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
269 			    const unsigned int word, const u32 value)
270 {
271 	u32 reg;
272 
273 	mutex_lock(&rt2x00dev->csr_mutex);
274 
275 	/*
276 	 * Wait until the RF becomes available, afterwards we
277 	 * can safely write the new data into the register.
278 	 */
279 	if (WAIT_FOR_RF(rt2x00dev, &reg)) {
280 		reg = 0;
281 		rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
282 		rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
283 		rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
284 		rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
285 
286 		rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
287 		rt2x00_rf_write(rt2x00dev, word, value);
288 	}
289 
290 	mutex_unlock(&rt2x00dev->csr_mutex);
291 }
292 
293 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
294 	[EEPROM_CHIP_ID]		= 0x0000,
295 	[EEPROM_VERSION]		= 0x0001,
296 	[EEPROM_MAC_ADDR_0]		= 0x0002,
297 	[EEPROM_MAC_ADDR_1]		= 0x0003,
298 	[EEPROM_MAC_ADDR_2]		= 0x0004,
299 	[EEPROM_NIC_CONF0]		= 0x001a,
300 	[EEPROM_NIC_CONF1]		= 0x001b,
301 	[EEPROM_FREQ]			= 0x001d,
302 	[EEPROM_LED_AG_CONF]		= 0x001e,
303 	[EEPROM_LED_ACT_CONF]		= 0x001f,
304 	[EEPROM_LED_POLARITY]		= 0x0020,
305 	[EEPROM_NIC_CONF2]		= 0x0021,
306 	[EEPROM_LNA]			= 0x0022,
307 	[EEPROM_RSSI_BG]		= 0x0023,
308 	[EEPROM_RSSI_BG2]		= 0x0024,
309 	[EEPROM_TXMIXER_GAIN_BG]	= 0x0024, /* overlaps with RSSI_BG2 */
310 	[EEPROM_RSSI_A]			= 0x0025,
311 	[EEPROM_RSSI_A2]		= 0x0026,
312 	[EEPROM_TXMIXER_GAIN_A]		= 0x0026, /* overlaps with RSSI_A2 */
313 	[EEPROM_EIRP_MAX_TX_POWER]	= 0x0027,
314 	[EEPROM_TXPOWER_DELTA]		= 0x0028,
315 	[EEPROM_TXPOWER_BG1]		= 0x0029,
316 	[EEPROM_TXPOWER_BG2]		= 0x0030,
317 	[EEPROM_TSSI_BOUND_BG1]		= 0x0037,
318 	[EEPROM_TSSI_BOUND_BG2]		= 0x0038,
319 	[EEPROM_TSSI_BOUND_BG3]		= 0x0039,
320 	[EEPROM_TSSI_BOUND_BG4]		= 0x003a,
321 	[EEPROM_TSSI_BOUND_BG5]		= 0x003b,
322 	[EEPROM_TXPOWER_A1]		= 0x003c,
323 	[EEPROM_TXPOWER_A2]		= 0x0053,
324 	[EEPROM_TXPOWER_INIT]		= 0x0068,
325 	[EEPROM_TSSI_BOUND_A1]		= 0x006a,
326 	[EEPROM_TSSI_BOUND_A2]		= 0x006b,
327 	[EEPROM_TSSI_BOUND_A3]		= 0x006c,
328 	[EEPROM_TSSI_BOUND_A4]		= 0x006d,
329 	[EEPROM_TSSI_BOUND_A5]		= 0x006e,
330 	[EEPROM_TXPOWER_BYRATE]		= 0x006f,
331 	[EEPROM_BBP_START]		= 0x0078,
332 };
333 
334 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
335 	[EEPROM_CHIP_ID]		= 0x0000,
336 	[EEPROM_VERSION]		= 0x0001,
337 	[EEPROM_MAC_ADDR_0]		= 0x0002,
338 	[EEPROM_MAC_ADDR_1]		= 0x0003,
339 	[EEPROM_MAC_ADDR_2]		= 0x0004,
340 	[EEPROM_NIC_CONF0]		= 0x001a,
341 	[EEPROM_NIC_CONF1]		= 0x001b,
342 	[EEPROM_NIC_CONF2]		= 0x001c,
343 	[EEPROM_EIRP_MAX_TX_POWER]	= 0x0020,
344 	[EEPROM_FREQ]			= 0x0022,
345 	[EEPROM_LED_AG_CONF]		= 0x0023,
346 	[EEPROM_LED_ACT_CONF]		= 0x0024,
347 	[EEPROM_LED_POLARITY]		= 0x0025,
348 	[EEPROM_LNA]			= 0x0026,
349 	[EEPROM_EXT_LNA2]		= 0x0027,
350 	[EEPROM_RSSI_BG]		= 0x0028,
351 	[EEPROM_RSSI_BG2]		= 0x0029,
352 	[EEPROM_RSSI_A]			= 0x002a,
353 	[EEPROM_RSSI_A2]		= 0x002b,
354 	[EEPROM_TXPOWER_BG1]		= 0x0030,
355 	[EEPROM_TXPOWER_BG2]		= 0x0037,
356 	[EEPROM_EXT_TXPOWER_BG3]	= 0x003e,
357 	[EEPROM_TSSI_BOUND_BG1]		= 0x0045,
358 	[EEPROM_TSSI_BOUND_BG2]		= 0x0046,
359 	[EEPROM_TSSI_BOUND_BG3]		= 0x0047,
360 	[EEPROM_TSSI_BOUND_BG4]		= 0x0048,
361 	[EEPROM_TSSI_BOUND_BG5]		= 0x0049,
362 	[EEPROM_TXPOWER_A1]		= 0x004b,
363 	[EEPROM_TXPOWER_A2]		= 0x0065,
364 	[EEPROM_EXT_TXPOWER_A3]		= 0x007f,
365 	[EEPROM_TSSI_BOUND_A1]		= 0x009a,
366 	[EEPROM_TSSI_BOUND_A2]		= 0x009b,
367 	[EEPROM_TSSI_BOUND_A3]		= 0x009c,
368 	[EEPROM_TSSI_BOUND_A4]		= 0x009d,
369 	[EEPROM_TSSI_BOUND_A5]		= 0x009e,
370 	[EEPROM_TXPOWER_BYRATE]		= 0x00a0,
371 };
372 
373 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
374 					     const enum rt2800_eeprom_word word)
375 {
376 	const unsigned int *map;
377 	unsigned int index;
378 
379 	if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
380 		      "%s: invalid EEPROM word %d\n",
381 		      wiphy_name(rt2x00dev->hw->wiphy), word))
382 		return 0;
383 
384 	if (rt2x00_rt(rt2x00dev, RT3593))
385 		map = rt2800_eeprom_map_ext;
386 	else
387 		map = rt2800_eeprom_map;
388 
389 	index = map[word];
390 
391 	/* Index 0 is valid only for EEPROM_CHIP_ID.
392 	 * Otherwise it means that the offset of the
393 	 * given word is not initialized in the map,
394 	 * or that the field is not usable on the
395 	 * actual chipset.
396 	 */
397 	WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
398 		  "%s: invalid access of EEPROM word %d\n",
399 		  wiphy_name(rt2x00dev->hw->wiphy), word);
400 
401 	return index;
402 }
403 
404 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
405 				const enum rt2800_eeprom_word word)
406 {
407 	unsigned int index;
408 
409 	index = rt2800_eeprom_word_index(rt2x00dev, word);
410 	return rt2x00_eeprom_addr(rt2x00dev, index);
411 }
412 
413 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
414 			      const enum rt2800_eeprom_word word)
415 {
416 	unsigned int index;
417 
418 	index = rt2800_eeprom_word_index(rt2x00dev, word);
419 	return rt2x00_eeprom_read(rt2x00dev, index);
420 }
421 
422 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
423 				const enum rt2800_eeprom_word word, u16 data)
424 {
425 	unsigned int index;
426 
427 	index = rt2800_eeprom_word_index(rt2x00dev, word);
428 	rt2x00_eeprom_write(rt2x00dev, index, data);
429 }
430 
431 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
432 					 const enum rt2800_eeprom_word array,
433 					 unsigned int offset)
434 {
435 	unsigned int index;
436 
437 	index = rt2800_eeprom_word_index(rt2x00dev, array);
438 	return rt2x00_eeprom_read(rt2x00dev, index + offset);
439 }
440 
441 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
442 {
443 	u32 reg;
444 	int i, count;
445 
446 	reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
447 	rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
448 	rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
449 	rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
450 	rt2x00_set_field32(&reg, WLAN_EN, 1);
451 	rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
452 
453 	udelay(REGISTER_BUSY_DELAY);
454 
455 	count = 0;
456 	do {
457 		/*
458 		 * Check PLL_LD & XTAL_RDY.
459 		 */
460 		for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
461 			reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
462 			if (rt2x00_get_field32(reg, PLL_LD) &&
463 			    rt2x00_get_field32(reg, XTAL_RDY))
464 				break;
465 			udelay(REGISTER_BUSY_DELAY);
466 		}
467 
468 		if (i >= REGISTER_BUSY_COUNT) {
469 
470 			if (count >= 10)
471 				return -EIO;
472 
473 			rt2800_register_write(rt2x00dev, 0x58, 0x018);
474 			udelay(REGISTER_BUSY_DELAY);
475 			rt2800_register_write(rt2x00dev, 0x58, 0x418);
476 			udelay(REGISTER_BUSY_DELAY);
477 			rt2800_register_write(rt2x00dev, 0x58, 0x618);
478 			udelay(REGISTER_BUSY_DELAY);
479 			count++;
480 		} else {
481 			count = 0;
482 		}
483 
484 		reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
485 		rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
486 		rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
487 		rt2x00_set_field32(&reg, WLAN_RESET, 1);
488 		rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
489 		udelay(10);
490 		rt2x00_set_field32(&reg, WLAN_RESET, 0);
491 		rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
492 		udelay(10);
493 		rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
494 	} while (count != 0);
495 
496 	return 0;
497 }
498 
499 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
500 			const u8 command, const u8 token,
501 			const u8 arg0, const u8 arg1)
502 {
503 	u32 reg;
504 
505 	/*
506 	 * SOC devices don't support MCU requests.
507 	 */
508 	if (rt2x00_is_soc(rt2x00dev))
509 		return;
510 
511 	mutex_lock(&rt2x00dev->csr_mutex);
512 
513 	/*
514 	 * Wait until the MCU becomes available, afterwards we
515 	 * can safely write the new data into the register.
516 	 */
517 	if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
518 		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
519 		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
520 		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
521 		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
522 		rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
523 
524 		reg = 0;
525 		rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
526 		rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
527 	}
528 
529 	mutex_unlock(&rt2x00dev->csr_mutex);
530 }
531 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
532 
533 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
534 {
535 	unsigned int i = 0;
536 	u32 reg;
537 
538 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
539 		reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
540 		if (reg && reg != ~0)
541 			return 0;
542 		msleep(1);
543 	}
544 
545 	rt2x00_err(rt2x00dev, "Unstable hardware\n");
546 	return -EBUSY;
547 }
548 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
549 
550 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
551 {
552 	unsigned int i;
553 	u32 reg;
554 
555 	/*
556 	 * Some devices are really slow to respond here. Wait a whole second
557 	 * before timing out.
558 	 */
559 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
560 		reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
561 		if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
562 		    !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
563 			return 0;
564 
565 		msleep(10);
566 	}
567 
568 	rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
569 	return -EACCES;
570 }
571 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
572 
573 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
574 {
575 	u32 reg;
576 
577 	reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
578 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
579 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
580 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
581 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
582 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
583 	rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
584 }
585 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
586 
587 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
588 			       unsigned short *txwi_size,
589 			       unsigned short *rxwi_size)
590 {
591 	switch (rt2x00dev->chip.rt) {
592 	case RT3593:
593 		*txwi_size = TXWI_DESC_SIZE_4WORDS;
594 		*rxwi_size = RXWI_DESC_SIZE_5WORDS;
595 		break;
596 
597 	case RT5592:
598 	case RT6352:
599 		*txwi_size = TXWI_DESC_SIZE_5WORDS;
600 		*rxwi_size = RXWI_DESC_SIZE_6WORDS;
601 		break;
602 
603 	default:
604 		*txwi_size = TXWI_DESC_SIZE_4WORDS;
605 		*rxwi_size = RXWI_DESC_SIZE_4WORDS;
606 		break;
607 	}
608 }
609 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
610 
611 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
612 {
613 	u16 fw_crc;
614 	u16 crc;
615 
616 	/*
617 	 * The last 2 bytes in the firmware array are the crc checksum itself,
618 	 * this means that we should never pass those 2 bytes to the crc
619 	 * algorithm.
620 	 */
621 	fw_crc = (data[len - 2] << 8 | data[len - 1]);
622 
623 	/*
624 	 * Use the crc ccitt algorithm.
625 	 * This will return the same value as the legacy driver which
626 	 * used bit ordering reversion on the both the firmware bytes
627 	 * before input input as well as on the final output.
628 	 * Obviously using crc ccitt directly is much more efficient.
629 	 */
630 	crc = crc_ccitt(~0, data, len - 2);
631 
632 	/*
633 	 * There is a small difference between the crc-itu-t + bitrev and
634 	 * the crc-ccitt crc calculation. In the latter method the 2 bytes
635 	 * will be swapped, use swab16 to convert the crc to the correct
636 	 * value.
637 	 */
638 	crc = swab16(crc);
639 
640 	return fw_crc == crc;
641 }
642 
643 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
644 			  const u8 *data, const size_t len)
645 {
646 	size_t offset = 0;
647 	size_t fw_len;
648 	bool multiple;
649 
650 	/*
651 	 * PCI(e) & SOC devices require firmware with a length
652 	 * of 8kb. USB devices require firmware files with a length
653 	 * of 4kb. Certain USB chipsets however require different firmware,
654 	 * which Ralink only provides attached to the original firmware
655 	 * file. Thus for USB devices, firmware files have a length
656 	 * which is a multiple of 4kb. The firmware for rt3290 chip also
657 	 * have a length which is a multiple of 4kb.
658 	 */
659 	if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
660 		fw_len = 4096;
661 	else
662 		fw_len = 8192;
663 
664 	multiple = true;
665 	/*
666 	 * Validate the firmware length
667 	 */
668 	if (len != fw_len && (!multiple || (len % fw_len) != 0))
669 		return FW_BAD_LENGTH;
670 
671 	/*
672 	 * Check if the chipset requires one of the upper parts
673 	 * of the firmware.
674 	 */
675 	if (rt2x00_is_usb(rt2x00dev) &&
676 	    !rt2x00_rt(rt2x00dev, RT2860) &&
677 	    !rt2x00_rt(rt2x00dev, RT2872) &&
678 	    !rt2x00_rt(rt2x00dev, RT3070) &&
679 	    ((len / fw_len) == 1))
680 		return FW_BAD_VERSION;
681 
682 	/*
683 	 * 8kb firmware files must be checked as if it were
684 	 * 2 separate firmware files.
685 	 */
686 	while (offset < len) {
687 		if (!rt2800_check_firmware_crc(data + offset, fw_len))
688 			return FW_BAD_CRC;
689 
690 		offset += fw_len;
691 	}
692 
693 	return FW_OK;
694 }
695 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
696 
697 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
698 			 const u8 *data, const size_t len)
699 {
700 	unsigned int i;
701 	u32 reg;
702 	int retval;
703 
704 	if (rt2x00_rt(rt2x00dev, RT3290)) {
705 		retval = rt2800_enable_wlan_rt3290(rt2x00dev);
706 		if (retval)
707 			return -EBUSY;
708 	}
709 
710 	/*
711 	 * If driver doesn't wake up firmware here,
712 	 * rt2800_load_firmware will hang forever when interface is up again.
713 	 */
714 	rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
715 
716 	/*
717 	 * Wait for stable hardware.
718 	 */
719 	if (rt2800_wait_csr_ready(rt2x00dev))
720 		return -EBUSY;
721 
722 	if (rt2x00_is_pci(rt2x00dev)) {
723 		if (rt2x00_rt(rt2x00dev, RT3290) ||
724 		    rt2x00_rt(rt2x00dev, RT3572) ||
725 		    rt2x00_rt(rt2x00dev, RT5390) ||
726 		    rt2x00_rt(rt2x00dev, RT5392)) {
727 			reg = rt2800_register_read(rt2x00dev, AUX_CTRL);
728 			rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
729 			rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
730 			rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
731 		}
732 		rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
733 	}
734 
735 	rt2800_disable_wpdma(rt2x00dev);
736 
737 	/*
738 	 * Write firmware to the device.
739 	 */
740 	rt2800_drv_write_firmware(rt2x00dev, data, len);
741 
742 	/*
743 	 * Wait for device to stabilize.
744 	 */
745 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
746 		reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL);
747 		if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
748 			break;
749 		msleep(1);
750 	}
751 
752 	if (i == REGISTER_BUSY_COUNT) {
753 		rt2x00_err(rt2x00dev, "PBF system register not ready\n");
754 		return -EBUSY;
755 	}
756 
757 	/*
758 	 * Disable DMA, will be reenabled later when enabling
759 	 * the radio.
760 	 */
761 	rt2800_disable_wpdma(rt2x00dev);
762 
763 	/*
764 	 * Initialize firmware.
765 	 */
766 	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
767 	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
768 	if (rt2x00_is_usb(rt2x00dev)) {
769 		rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
770 		rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
771 	}
772 	msleep(1);
773 
774 	return 0;
775 }
776 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
777 
778 void rt2800_write_tx_data(struct queue_entry *entry,
779 			  struct txentry_desc *txdesc)
780 {
781 	__le32 *txwi = rt2800_drv_get_txwi(entry);
782 	u32 word;
783 	int i;
784 
785 	/*
786 	 * Initialize TX Info descriptor
787 	 */
788 	word = rt2x00_desc_read(txwi, 0);
789 	rt2x00_set_field32(&word, TXWI_W0_FRAG,
790 			   test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
791 	rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
792 			   test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
793 	rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
794 	rt2x00_set_field32(&word, TXWI_W0_TS,
795 			   test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
796 	rt2x00_set_field32(&word, TXWI_W0_AMPDU,
797 			   test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
798 	rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
799 			   txdesc->u.ht.mpdu_density);
800 	rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
801 	rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
802 	rt2x00_set_field32(&word, TXWI_W0_BW,
803 			   test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
804 	rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
805 			   test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
806 	rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
807 	rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
808 	rt2x00_desc_write(txwi, 0, word);
809 
810 	word = rt2x00_desc_read(txwi, 1);
811 	rt2x00_set_field32(&word, TXWI_W1_ACK,
812 			   test_bit(ENTRY_TXD_ACK, &txdesc->flags));
813 	rt2x00_set_field32(&word, TXWI_W1_NSEQ,
814 			   test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
815 	rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
816 	rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
817 			   test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
818 			   txdesc->key_idx : txdesc->u.ht.wcid);
819 	rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
820 			   txdesc->length);
821 	rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
822 	rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
823 	rt2x00_desc_write(txwi, 1, word);
824 
825 	/*
826 	 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
827 	 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
828 	 * When TXD_W3_WIV is set to 1 it will use the IV data
829 	 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
830 	 * crypto entry in the registers should be used to encrypt the frame.
831 	 *
832 	 * Nulify all remaining words as well, we don't know how to program them.
833 	 */
834 	for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
835 		_rt2x00_desc_write(txwi, i, 0);
836 }
837 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
838 
839 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
840 {
841 	s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
842 	s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
843 	s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
844 	u16 eeprom;
845 	u8 offset0;
846 	u8 offset1;
847 	u8 offset2;
848 
849 	if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
850 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
851 		offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
852 		offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
853 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
854 		offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
855 	} else {
856 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
857 		offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
858 		offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
859 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
860 		offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
861 	}
862 
863 	/*
864 	 * Convert the value from the descriptor into the RSSI value
865 	 * If the value in the descriptor is 0, it is considered invalid
866 	 * and the default (extremely low) rssi value is assumed
867 	 */
868 	rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
869 	rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
870 	rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
871 
872 	/*
873 	 * mac80211 only accepts a single RSSI value. Calculating the
874 	 * average doesn't deliver a fair answer either since -60:-60 would
875 	 * be considered equally good as -50:-70 while the second is the one
876 	 * which gives less energy...
877 	 */
878 	rssi0 = max(rssi0, rssi1);
879 	return (int)max(rssi0, rssi2);
880 }
881 
882 void rt2800_process_rxwi(struct queue_entry *entry,
883 			 struct rxdone_entry_desc *rxdesc)
884 {
885 	__le32 *rxwi = (__le32 *) entry->skb->data;
886 	u32 word;
887 
888 	word = rt2x00_desc_read(rxwi, 0);
889 
890 	rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
891 	rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
892 
893 	word = rt2x00_desc_read(rxwi, 1);
894 
895 	if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
896 		rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI;
897 
898 	if (rt2x00_get_field32(word, RXWI_W1_BW))
899 		rxdesc->bw = RATE_INFO_BW_40;
900 
901 	/*
902 	 * Detect RX rate, always use MCS as signal type.
903 	 */
904 	rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
905 	rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
906 	rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
907 
908 	/*
909 	 * Mask of 0x8 bit to remove the short preamble flag.
910 	 */
911 	if (rxdesc->rate_mode == RATE_MODE_CCK)
912 		rxdesc->signal &= ~0x8;
913 
914 	word = rt2x00_desc_read(rxwi, 2);
915 
916 	/*
917 	 * Convert descriptor AGC value to RSSI value.
918 	 */
919 	rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
920 	/*
921 	 * Remove RXWI descriptor from start of the buffer.
922 	 */
923 	skb_pull(entry->skb, entry->queue->winfo_size);
924 }
925 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
926 
927 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc,
928 				    u32 status, enum nl80211_band band)
929 {
930 	u8 flags = 0;
931 	u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
932 
933 	switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) {
934 	case RATE_MODE_HT_GREENFIELD:
935 		flags |= IEEE80211_TX_RC_GREEN_FIELD;
936 		/* fall through */
937 	case RATE_MODE_HT_MIX:
938 		flags |= IEEE80211_TX_RC_MCS;
939 		break;
940 	case RATE_MODE_OFDM:
941 		if (band == NL80211_BAND_2GHZ)
942 			idx += 4;
943 		break;
944 	case RATE_MODE_CCK:
945 		if (idx >= 8)
946 			idx -= 8;
947 		break;
948 	}
949 
950 	if (rt2x00_get_field32(status, TX_STA_FIFO_BW))
951 		flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
952 
953 	if (rt2x00_get_field32(status, TX_STA_FIFO_SGI))
954 		flags |= IEEE80211_TX_RC_SHORT_GI;
955 
956 	skbdesc->tx_rate_idx = idx;
957 	skbdesc->tx_rate_flags = flags;
958 }
959 
960 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi,
961 			 bool match)
962 {
963 	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
964 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
965 	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
966 	struct txdone_entry_desc txdesc;
967 	u32 word;
968 	u16 mcs, real_mcs;
969 	int aggr, ampdu, wcid, ack_req;
970 
971 	/*
972 	 * Obtain the status about this packet.
973 	 */
974 	txdesc.flags = 0;
975 	word = rt2x00_desc_read(txwi, 0);
976 
977 	mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
978 	ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
979 
980 	real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
981 	aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
982 	wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
983 	ack_req	= rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED);
984 
985 	/*
986 	 * If a frame was meant to be sent as a single non-aggregated MPDU
987 	 * but ended up in an aggregate the used tx rate doesn't correlate
988 	 * with the one specified in the TXWI as the whole aggregate is sent
989 	 * with the same rate.
990 	 *
991 	 * For example: two frames are sent to rt2x00, the first one sets
992 	 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
993 	 * and requests MCS15. If the hw aggregates both frames into one
994 	 * AMDPU the tx status for both frames will contain MCS7 although
995 	 * the frame was sent successfully.
996 	 *
997 	 * Hence, replace the requested rate with the real tx rate to not
998 	 * confuse the rate control algortihm by providing clearly wrong
999 	 * data.
1000 	 *
1001 	 * FIXME: if we do not find matching entry, we tell that frame was
1002 	 * posted without any retries. We need to find a way to fix that
1003 	 * and provide retry count.
1004  	 */
1005 	if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) {
1006 		rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
1007 		mcs = real_mcs;
1008 	}
1009 
1010 	if (aggr == 1 || ampdu == 1)
1011 		__set_bit(TXDONE_AMPDU, &txdesc.flags);
1012 
1013 	if (!ack_req)
1014 		__set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags);
1015 
1016 	/*
1017 	 * Ralink has a retry mechanism using a global fallback
1018 	 * table. We setup this fallback table to try the immediate
1019 	 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
1020 	 * always contains the MCS used for the last transmission, be
1021 	 * it successful or not.
1022 	 */
1023 	if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
1024 		/*
1025 		 * Transmission succeeded. The number of retries is
1026 		 * mcs - real_mcs
1027 		 */
1028 		__set_bit(TXDONE_SUCCESS, &txdesc.flags);
1029 		txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
1030 	} else {
1031 		/*
1032 		 * Transmission failed. The number of retries is
1033 		 * always 7 in this case (for a total number of 8
1034 		 * frames sent).
1035 		 */
1036 		__set_bit(TXDONE_FAILURE, &txdesc.flags);
1037 		txdesc.retry = rt2x00dev->long_retry;
1038 	}
1039 
1040 	/*
1041 	 * the frame was retried at least once
1042 	 * -> hw used fallback rates
1043 	 */
1044 	if (txdesc.retry)
1045 		__set_bit(TXDONE_FALLBACK, &txdesc.flags);
1046 
1047 	if (!match) {
1048 		/* RCU assures non-null sta will not be freed by mac80211. */
1049 		rcu_read_lock();
1050 		if (likely(wcid >= WCID_START && wcid <= WCID_END))
1051 			skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START];
1052 		else
1053 			skbdesc->sta = NULL;
1054 		rt2x00lib_txdone_nomatch(entry, &txdesc);
1055 		rcu_read_unlock();
1056 	} else {
1057 		rt2x00lib_txdone(entry, &txdesc);
1058 	}
1059 }
1060 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
1061 
1062 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
1063 					  unsigned int index)
1064 {
1065 	return HW_BEACON_BASE(index);
1066 }
1067 
1068 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
1069 					  unsigned int index)
1070 {
1071 	return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
1072 }
1073 
1074 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
1075 {
1076 	struct data_queue *queue = rt2x00dev->bcn;
1077 	struct queue_entry *entry;
1078 	int i, bcn_num = 0;
1079 	u64 off, reg = 0;
1080 	u32 bssid_dw1;
1081 
1082 	/*
1083 	 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
1084 	 */
1085 	for (i = 0; i < queue->limit; i++) {
1086 		entry = &queue->entries[i];
1087 		if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
1088 			continue;
1089 		off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
1090 		reg |= off << (8 * bcn_num);
1091 		bcn_num++;
1092 	}
1093 
1094 	rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
1095 	rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
1096 
1097 	/*
1098 	 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
1099 	 */
1100 	bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1);
1101 	rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
1102 			   bcn_num > 0 ? bcn_num - 1 : 0);
1103 	rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
1104 }
1105 
1106 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
1107 {
1108 	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1109 	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1110 	unsigned int beacon_base;
1111 	unsigned int padding_len;
1112 	u32 orig_reg, reg;
1113 	const int txwi_desc_size = entry->queue->winfo_size;
1114 
1115 	/*
1116 	 * Disable beaconing while we are reloading the beacon data,
1117 	 * otherwise we might be sending out invalid data.
1118 	 */
1119 	reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1120 	orig_reg = reg;
1121 	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1122 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1123 
1124 	/*
1125 	 * Add space for the TXWI in front of the skb.
1126 	 */
1127 	memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
1128 
1129 	/*
1130 	 * Register descriptor details in skb frame descriptor.
1131 	 */
1132 	skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1133 	skbdesc->desc = entry->skb->data;
1134 	skbdesc->desc_len = txwi_desc_size;
1135 
1136 	/*
1137 	 * Add the TXWI for the beacon to the skb.
1138 	 */
1139 	rt2800_write_tx_data(entry, txdesc);
1140 
1141 	/*
1142 	 * Dump beacon to userspace through debugfs.
1143 	 */
1144 	rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1145 
1146 	/*
1147 	 * Write entire beacon with TXWI and padding to register.
1148 	 */
1149 	padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1150 	if (padding_len && skb_pad(entry->skb, padding_len)) {
1151 		rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1152 		/* skb freed by skb_pad() on failure */
1153 		entry->skb = NULL;
1154 		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1155 		return;
1156 	}
1157 
1158 	beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1159 
1160 	rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1161 				   entry->skb->len + padding_len);
1162 	__set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1163 
1164 	/*
1165 	 * Change global beacons settings.
1166 	 */
1167 	rt2800_update_beacons_setup(rt2x00dev);
1168 
1169 	/*
1170 	 * Restore beaconing state.
1171 	 */
1172 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1173 
1174 	/*
1175 	 * Clean up beacon skb.
1176 	 */
1177 	dev_kfree_skb_any(entry->skb);
1178 	entry->skb = NULL;
1179 }
1180 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1181 
1182 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1183 						unsigned int index)
1184 {
1185 	int i;
1186 	const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1187 	unsigned int beacon_base;
1188 
1189 	beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1190 
1191 	/*
1192 	 * For the Beacon base registers we only need to clear
1193 	 * the whole TXWI which (when set to 0) will invalidate
1194 	 * the entire beacon.
1195 	 */
1196 	for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1197 		rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1198 }
1199 
1200 void rt2800_clear_beacon(struct queue_entry *entry)
1201 {
1202 	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1203 	u32 orig_reg, reg;
1204 
1205 	/*
1206 	 * Disable beaconing while we are reloading the beacon data,
1207 	 * otherwise we might be sending out invalid data.
1208 	 */
1209 	orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1210 	reg = orig_reg;
1211 	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1212 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1213 
1214 	/*
1215 	 * Clear beacon.
1216 	 */
1217 	rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1218 	__clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
1219 
1220 	/*
1221 	 * Change global beacons settings.
1222 	 */
1223 	rt2800_update_beacons_setup(rt2x00dev);
1224 	/*
1225 	 * Restore beaconing state.
1226 	 */
1227 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1228 }
1229 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1230 
1231 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1232 const struct rt2x00debug rt2800_rt2x00debug = {
1233 	.owner	= THIS_MODULE,
1234 	.csr	= {
1235 		.read		= rt2800_register_read,
1236 		.write		= rt2800_register_write,
1237 		.flags		= RT2X00DEBUGFS_OFFSET,
1238 		.word_base	= CSR_REG_BASE,
1239 		.word_size	= sizeof(u32),
1240 		.word_count	= CSR_REG_SIZE / sizeof(u32),
1241 	},
1242 	.eeprom	= {
1243 		/* NOTE: The local EEPROM access functions can't
1244 		 * be used here, use the generic versions instead.
1245 		 */
1246 		.read		= rt2x00_eeprom_read,
1247 		.write		= rt2x00_eeprom_write,
1248 		.word_base	= EEPROM_BASE,
1249 		.word_size	= sizeof(u16),
1250 		.word_count	= EEPROM_SIZE / sizeof(u16),
1251 	},
1252 	.bbp	= {
1253 		.read		= rt2800_bbp_read,
1254 		.write		= rt2800_bbp_write,
1255 		.word_base	= BBP_BASE,
1256 		.word_size	= sizeof(u8),
1257 		.word_count	= BBP_SIZE / sizeof(u8),
1258 	},
1259 	.rf	= {
1260 		.read		= rt2x00_rf_read,
1261 		.write		= rt2800_rf_write,
1262 		.word_base	= RF_BASE,
1263 		.word_size	= sizeof(u32),
1264 		.word_count	= RF_SIZE / sizeof(u32),
1265 	},
1266 	.rfcsr	= {
1267 		.read		= rt2800_rfcsr_read,
1268 		.write		= rt2800_rfcsr_write,
1269 		.word_base	= RFCSR_BASE,
1270 		.word_size	= sizeof(u8),
1271 		.word_count	= RFCSR_SIZE / sizeof(u8),
1272 	},
1273 };
1274 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1275 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1276 
1277 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1278 {
1279 	u32 reg;
1280 
1281 	if (rt2x00_rt(rt2x00dev, RT3290)) {
1282 		reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
1283 		return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1284 	} else {
1285 		reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
1286 		return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1287 	}
1288 }
1289 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1290 
1291 #ifdef CONFIG_RT2X00_LIB_LEDS
1292 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1293 				  enum led_brightness brightness)
1294 {
1295 	struct rt2x00_led *led =
1296 	    container_of(led_cdev, struct rt2x00_led, led_dev);
1297 	unsigned int enabled = brightness != LED_OFF;
1298 	unsigned int bg_mode =
1299 	    (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
1300 	unsigned int polarity =
1301 		rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1302 				   EEPROM_FREQ_LED_POLARITY);
1303 	unsigned int ledmode =
1304 		rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1305 				   EEPROM_FREQ_LED_MODE);
1306 	u32 reg;
1307 
1308 	/* Check for SoC (SOC devices don't support MCU requests) */
1309 	if (rt2x00_is_soc(led->rt2x00dev)) {
1310 		reg = rt2800_register_read(led->rt2x00dev, LED_CFG);
1311 
1312 		/* Set LED Polarity */
1313 		rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1314 
1315 		/* Set LED Mode */
1316 		if (led->type == LED_TYPE_RADIO) {
1317 			rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1318 					   enabled ? 3 : 0);
1319 		} else if (led->type == LED_TYPE_ASSOC) {
1320 			rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1321 					   enabled ? 3 : 0);
1322 		} else if (led->type == LED_TYPE_QUALITY) {
1323 			rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1324 					   enabled ? 3 : 0);
1325 		}
1326 
1327 		rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1328 
1329 	} else {
1330 		if (led->type == LED_TYPE_RADIO) {
1331 			rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1332 					      enabled ? 0x20 : 0);
1333 		} else if (led->type == LED_TYPE_ASSOC) {
1334 			rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1335 					      enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1336 		} else if (led->type == LED_TYPE_QUALITY) {
1337 			/*
1338 			 * The brightness is divided into 6 levels (0 - 5),
1339 			 * The specs tell us the following levels:
1340 			 *	0, 1 ,3, 7, 15, 31
1341 			 * to determine the level in a simple way we can simply
1342 			 * work with bitshifting:
1343 			 *	(1 << level) - 1
1344 			 */
1345 			rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1346 					      (1 << brightness / (LED_FULL / 6)) - 1,
1347 					      polarity);
1348 		}
1349 	}
1350 }
1351 
1352 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1353 		     struct rt2x00_led *led, enum led_type type)
1354 {
1355 	led->rt2x00dev = rt2x00dev;
1356 	led->type = type;
1357 	led->led_dev.brightness_set = rt2800_brightness_set;
1358 	led->flags = LED_INITIALIZED;
1359 }
1360 #endif /* CONFIG_RT2X00_LIB_LEDS */
1361 
1362 /*
1363  * Configuration handlers.
1364  */
1365 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1366 			       const u8 *address,
1367 			       int wcid)
1368 {
1369 	struct mac_wcid_entry wcid_entry;
1370 	u32 offset;
1371 
1372 	offset = MAC_WCID_ENTRY(wcid);
1373 
1374 	memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1375 	if (address)
1376 		memcpy(wcid_entry.mac, address, ETH_ALEN);
1377 
1378 	rt2800_register_multiwrite(rt2x00dev, offset,
1379 				      &wcid_entry, sizeof(wcid_entry));
1380 }
1381 
1382 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1383 {
1384 	u32 offset;
1385 	offset = MAC_WCID_ATTR_ENTRY(wcid);
1386 	rt2800_register_write(rt2x00dev, offset, 0);
1387 }
1388 
1389 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1390 					   int wcid, u32 bssidx)
1391 {
1392 	u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1393 	u32 reg;
1394 
1395 	/*
1396 	 * The BSS Idx numbers is split in a main value of 3 bits,
1397 	 * and a extended field for adding one additional bit to the value.
1398 	 */
1399 	reg = rt2800_register_read(rt2x00dev, offset);
1400 	rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1401 	rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1402 			   (bssidx & 0x8) >> 3);
1403 	rt2800_register_write(rt2x00dev, offset, reg);
1404 }
1405 
1406 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1407 					   struct rt2x00lib_crypto *crypto,
1408 					   struct ieee80211_key_conf *key)
1409 {
1410 	struct mac_iveiv_entry iveiv_entry;
1411 	u32 offset;
1412 	u32 reg;
1413 
1414 	offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1415 
1416 	if (crypto->cmd == SET_KEY) {
1417 		reg = rt2800_register_read(rt2x00dev, offset);
1418 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1419 				   !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1420 		/*
1421 		 * Both the cipher as the BSS Idx numbers are split in a main
1422 		 * value of 3 bits, and a extended field for adding one additional
1423 		 * bit to the value.
1424 		 */
1425 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1426 				   (crypto->cipher & 0x7));
1427 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1428 				   (crypto->cipher & 0x8) >> 3);
1429 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1430 		rt2800_register_write(rt2x00dev, offset, reg);
1431 	} else {
1432 		/* Delete the cipher without touching the bssidx */
1433 		reg = rt2800_register_read(rt2x00dev, offset);
1434 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1435 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1436 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1437 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1438 		rt2800_register_write(rt2x00dev, offset, reg);
1439 	}
1440 
1441 	offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1442 
1443 	memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1444 	if ((crypto->cipher == CIPHER_TKIP) ||
1445 	    (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1446 	    (crypto->cipher == CIPHER_AES))
1447 		iveiv_entry.iv[3] |= 0x20;
1448 	iveiv_entry.iv[3] |= key->keyidx << 6;
1449 	rt2800_register_multiwrite(rt2x00dev, offset,
1450 				      &iveiv_entry, sizeof(iveiv_entry));
1451 }
1452 
1453 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1454 			     struct rt2x00lib_crypto *crypto,
1455 			     struct ieee80211_key_conf *key)
1456 {
1457 	struct hw_key_entry key_entry;
1458 	struct rt2x00_field32 field;
1459 	u32 offset;
1460 	u32 reg;
1461 
1462 	if (crypto->cmd == SET_KEY) {
1463 		key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1464 
1465 		memcpy(key_entry.key, crypto->key,
1466 		       sizeof(key_entry.key));
1467 		memcpy(key_entry.tx_mic, crypto->tx_mic,
1468 		       sizeof(key_entry.tx_mic));
1469 		memcpy(key_entry.rx_mic, crypto->rx_mic,
1470 		       sizeof(key_entry.rx_mic));
1471 
1472 		offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1473 		rt2800_register_multiwrite(rt2x00dev, offset,
1474 					      &key_entry, sizeof(key_entry));
1475 	}
1476 
1477 	/*
1478 	 * The cipher types are stored over multiple registers
1479 	 * starting with SHARED_KEY_MODE_BASE each word will have
1480 	 * 32 bits and contains the cipher types for 2 bssidx each.
1481 	 * Using the correct defines correctly will cause overhead,
1482 	 * so just calculate the correct offset.
1483 	 */
1484 	field.bit_offset = 4 * (key->hw_key_idx % 8);
1485 	field.bit_mask = 0x7 << field.bit_offset;
1486 
1487 	offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1488 
1489 	reg = rt2800_register_read(rt2x00dev, offset);
1490 	rt2x00_set_field32(&reg, field,
1491 			   (crypto->cmd == SET_KEY) * crypto->cipher);
1492 	rt2800_register_write(rt2x00dev, offset, reg);
1493 
1494 	/*
1495 	 * Update WCID information
1496 	 */
1497 	rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1498 	rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1499 				       crypto->bssidx);
1500 	rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1501 
1502 	return 0;
1503 }
1504 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1505 
1506 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1507 			       struct rt2x00lib_crypto *crypto,
1508 			       struct ieee80211_key_conf *key)
1509 {
1510 	struct hw_key_entry key_entry;
1511 	u32 offset;
1512 
1513 	if (crypto->cmd == SET_KEY) {
1514 		/*
1515 		 * Allow key configuration only for STAs that are
1516 		 * known by the hw.
1517 		 */
1518 		if (crypto->wcid > WCID_END)
1519 			return -ENOSPC;
1520 		key->hw_key_idx = crypto->wcid;
1521 
1522 		memcpy(key_entry.key, crypto->key,
1523 		       sizeof(key_entry.key));
1524 		memcpy(key_entry.tx_mic, crypto->tx_mic,
1525 		       sizeof(key_entry.tx_mic));
1526 		memcpy(key_entry.rx_mic, crypto->rx_mic,
1527 		       sizeof(key_entry.rx_mic));
1528 
1529 		offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1530 		rt2800_register_multiwrite(rt2x00dev, offset,
1531 					      &key_entry, sizeof(key_entry));
1532 	}
1533 
1534 	/*
1535 	 * Update WCID information
1536 	 */
1537 	rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1538 
1539 	return 0;
1540 }
1541 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1542 
1543 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
1544 {
1545 	u8 i, max_psdu;
1546 	u32 reg;
1547 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1548 
1549 	for (i = 0; i < 3; i++)
1550 		if (drv_data->ampdu_factor_cnt[i] > 0)
1551 			break;
1552 
1553 	max_psdu = min(drv_data->max_psdu, i);
1554 
1555 	reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
1556 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, max_psdu);
1557 	rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1558 }
1559 
1560 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1561 		   struct ieee80211_sta *sta)
1562 {
1563 	int wcid;
1564 	struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1565 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1566 
1567 	/*
1568 	 * Limit global maximum TX AMPDU length to smallest value of all
1569 	 * connected stations. In AP mode this can be suboptimal, but we
1570 	 * do not have a choice if some connected STA is not capable to
1571 	 * receive the same amount of data like the others.
1572 	 */
1573 	if (sta->ht_cap.ht_supported) {
1574 		drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++;
1575 		rt2800_set_max_psdu_len(rt2x00dev);
1576 	}
1577 
1578 	/*
1579 	 * Search for the first free WCID entry and return the corresponding
1580 	 * index.
1581 	 */
1582 	wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
1583 
1584 	/*
1585 	 * Store selected wcid even if it is invalid so that we can
1586 	 * later decide if the STA is uploaded into the hw.
1587 	 */
1588 	sta_priv->wcid = wcid;
1589 
1590 	/*
1591 	 * No space left in the device, however, we can still communicate
1592 	 * with the STA -> No error.
1593 	 */
1594 	if (wcid > WCID_END)
1595 		return 0;
1596 
1597 	__set_bit(wcid - WCID_START, drv_data->sta_ids);
1598 	drv_data->wcid_to_sta[wcid - WCID_START] = sta;
1599 
1600 	/*
1601 	 * Clean up WCID attributes and write STA address to the device.
1602 	 */
1603 	rt2800_delete_wcid_attr(rt2x00dev, wcid);
1604 	rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1605 	rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1606 				       rt2x00lib_get_bssidx(rt2x00dev, vif));
1607 	return 0;
1608 }
1609 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1610 
1611 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, struct ieee80211_sta *sta)
1612 {
1613 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1614 	struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1615 	int wcid = sta_priv->wcid;
1616 
1617 	if (sta->ht_cap.ht_supported) {
1618 		drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--;
1619 		rt2800_set_max_psdu_len(rt2x00dev);
1620 	}
1621 
1622 	if (wcid > WCID_END)
1623 		return 0;
1624 	/*
1625 	 * Remove WCID entry, no need to clean the attributes as they will
1626 	 * get renewed when the WCID is reused.
1627 	 */
1628 	rt2800_config_wcid(rt2x00dev, NULL, wcid);
1629 	drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1630 	__clear_bit(wcid - WCID_START, drv_data->sta_ids);
1631 
1632 	return 0;
1633 }
1634 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1635 
1636 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1637 			  const unsigned int filter_flags)
1638 {
1639 	u32 reg;
1640 
1641 	/*
1642 	 * Start configuration steps.
1643 	 * Note that the version error will always be dropped
1644 	 * and broadcast frames will always be accepted since
1645 	 * there is no filter for it at this time.
1646 	 */
1647 	reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG);
1648 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1649 			   !(filter_flags & FIF_FCSFAIL));
1650 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1651 			   !(filter_flags & FIF_PLCPFAIL));
1652 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1653 			   !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
1654 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1655 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1656 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1657 			   !(filter_flags & FIF_ALLMULTI));
1658 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1659 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1660 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1661 			   !(filter_flags & FIF_CONTROL));
1662 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1663 			   !(filter_flags & FIF_CONTROL));
1664 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1665 			   !(filter_flags & FIF_CONTROL));
1666 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1667 			   !(filter_flags & FIF_CONTROL));
1668 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1669 			   !(filter_flags & FIF_CONTROL));
1670 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1671 			   !(filter_flags & FIF_PSPOLL));
1672 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1673 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1674 			   !(filter_flags & FIF_CONTROL));
1675 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1676 			   !(filter_flags & FIF_CONTROL));
1677 	rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1678 }
1679 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1680 
1681 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1682 			struct rt2x00intf_conf *conf, const unsigned int flags)
1683 {
1684 	u32 reg;
1685 	bool update_bssid = false;
1686 
1687 	if (flags & CONFIG_UPDATE_TYPE) {
1688 		/*
1689 		 * Enable synchronisation.
1690 		 */
1691 		reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1692 		rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1693 		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1694 
1695 		if (conf->sync == TSF_SYNC_AP_NONE) {
1696 			/*
1697 			 * Tune beacon queue transmit parameters for AP mode
1698 			 */
1699 			reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1700 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1701 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1702 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1703 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1704 			rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1705 		} else {
1706 			reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1707 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1708 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1709 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1710 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1711 			rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1712 		}
1713 	}
1714 
1715 	if (flags & CONFIG_UPDATE_MAC) {
1716 		if (flags & CONFIG_UPDATE_TYPE &&
1717 		    conf->sync == TSF_SYNC_AP_NONE) {
1718 			/*
1719 			 * The BSSID register has to be set to our own mac
1720 			 * address in AP mode.
1721 			 */
1722 			memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1723 			update_bssid = true;
1724 		}
1725 
1726 		if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1727 			reg = le32_to_cpu(conf->mac[1]);
1728 			rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1729 			conf->mac[1] = cpu_to_le32(reg);
1730 		}
1731 
1732 		rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1733 					      conf->mac, sizeof(conf->mac));
1734 	}
1735 
1736 	if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1737 		if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1738 			reg = le32_to_cpu(conf->bssid[1]);
1739 			rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1740 			rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
1741 			conf->bssid[1] = cpu_to_le32(reg);
1742 		}
1743 
1744 		rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1745 					      conf->bssid, sizeof(conf->bssid));
1746 	}
1747 }
1748 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1749 
1750 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1751 				    struct rt2x00lib_erp *erp)
1752 {
1753 	bool any_sta_nongf = !!(erp->ht_opmode &
1754 				IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1755 	u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1756 	u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1757 	u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1758 	u32 reg;
1759 
1760 	/* default protection rate for HT20: OFDM 24M */
1761 	mm20_rate = gf20_rate = 0x4004;
1762 
1763 	/* default protection rate for HT40: duplicate OFDM 24M */
1764 	mm40_rate = gf40_rate = 0x4084;
1765 
1766 	switch (protection) {
1767 	case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1768 		/*
1769 		 * All STAs in this BSS are HT20/40 but there might be
1770 		 * STAs not supporting greenfield mode.
1771 		 * => Disable protection for HT transmissions.
1772 		 */
1773 		mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1774 
1775 		break;
1776 	case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1777 		/*
1778 		 * All STAs in this BSS are HT20 or HT20/40 but there
1779 		 * might be STAs not supporting greenfield mode.
1780 		 * => Protect all HT40 transmissions.
1781 		 */
1782 		mm20_mode = gf20_mode = 0;
1783 		mm40_mode = gf40_mode = 1;
1784 
1785 		break;
1786 	case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1787 		/*
1788 		 * Nonmember protection:
1789 		 * According to 802.11n we _should_ protect all
1790 		 * HT transmissions (but we don't have to).
1791 		 *
1792 		 * But if cts_protection is enabled we _shall_ protect
1793 		 * all HT transmissions using a CCK rate.
1794 		 *
1795 		 * And if any station is non GF we _shall_ protect
1796 		 * GF transmissions.
1797 		 *
1798 		 * We decide to protect everything
1799 		 * -> fall through to mixed mode.
1800 		 */
1801 	case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1802 		/*
1803 		 * Legacy STAs are present
1804 		 * => Protect all HT transmissions.
1805 		 */
1806 		mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1;
1807 
1808 		/*
1809 		 * If erp protection is needed we have to protect HT
1810 		 * transmissions with CCK 11M long preamble.
1811 		 */
1812 		if (erp->cts_protection) {
1813 			/* don't duplicate RTS/CTS in CCK mode */
1814 			mm20_rate = mm40_rate = 0x0003;
1815 			gf20_rate = gf40_rate = 0x0003;
1816 		}
1817 		break;
1818 	}
1819 
1820 	/* check for STAs not supporting greenfield mode */
1821 	if (any_sta_nongf)
1822 		gf20_mode = gf40_mode = 1;
1823 
1824 	/* Update HT protection config */
1825 	reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
1826 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1827 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1828 	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1829 
1830 	reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
1831 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1832 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1833 	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1834 
1835 	reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
1836 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1837 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1838 	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1839 
1840 	reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
1841 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1842 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1843 	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1844 }
1845 
1846 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1847 		       u32 changed)
1848 {
1849 	u32 reg;
1850 
1851 	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1852 		reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
1853 		rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1854 				   !!erp->short_preamble);
1855 		rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1856 	}
1857 
1858 	if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1859 		reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
1860 		rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1861 				   erp->cts_protection ? 2 : 0);
1862 		rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1863 	}
1864 
1865 	if (changed & BSS_CHANGED_BASIC_RATES) {
1866 		rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1867 				      0xff0 | erp->basic_rates);
1868 		rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1869 	}
1870 
1871 	if (changed & BSS_CHANGED_ERP_SLOT) {
1872 		reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
1873 		rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1874 				   erp->slot_time);
1875 		rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1876 
1877 		reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
1878 		rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1879 		rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1880 	}
1881 
1882 	if (changed & BSS_CHANGED_BEACON_INT) {
1883 		reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1884 		rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1885 				   erp->beacon_int * 16);
1886 		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1887 	}
1888 
1889 	if (changed & BSS_CHANGED_HT)
1890 		rt2800_config_ht_opmode(rt2x00dev, erp);
1891 }
1892 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1893 
1894 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1895 {
1896 	u32 reg;
1897 	u16 eeprom;
1898 	u8 led_ctrl, led_g_mode, led_r_mode;
1899 
1900 	reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
1901 	if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
1902 		rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1903 		rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1904 	} else {
1905 		rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1906 		rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1907 	}
1908 	rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1909 
1910 	reg = rt2800_register_read(rt2x00dev, LED_CFG);
1911 	led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1912 	led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1913 	if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1914 	    led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1915 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
1916 		led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1917 		if (led_ctrl == 0 || led_ctrl > 0x40) {
1918 			rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1919 			rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1920 			rt2800_register_write(rt2x00dev, LED_CFG, reg);
1921 		} else {
1922 			rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1923 					   (led_g_mode << 2) | led_r_mode, 1);
1924 		}
1925 	}
1926 }
1927 
1928 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1929 				     enum antenna ant)
1930 {
1931 	u32 reg;
1932 	u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1933 	u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1934 
1935 	if (rt2x00_is_pci(rt2x00dev)) {
1936 		reg = rt2800_register_read(rt2x00dev, E2PROM_CSR);
1937 		rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1938 		rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1939 	} else if (rt2x00_is_usb(rt2x00dev))
1940 		rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1941 				   eesk_pin, 0);
1942 
1943 	reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
1944 	rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1945 	rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1946 	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1947 }
1948 
1949 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1950 {
1951 	u8 r1;
1952 	u8 r3;
1953 	u16 eeprom;
1954 
1955 	r1 = rt2800_bbp_read(rt2x00dev, 1);
1956 	r3 = rt2800_bbp_read(rt2x00dev, 3);
1957 
1958 	if (rt2x00_rt(rt2x00dev, RT3572) &&
1959 	    rt2x00_has_cap_bt_coexist(rt2x00dev))
1960 		rt2800_config_3572bt_ant(rt2x00dev);
1961 
1962 	/*
1963 	 * Configure the TX antenna.
1964 	 */
1965 	switch (ant->tx_chain_num) {
1966 	case 1:
1967 		rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1968 		break;
1969 	case 2:
1970 		if (rt2x00_rt(rt2x00dev, RT3572) &&
1971 		    rt2x00_has_cap_bt_coexist(rt2x00dev))
1972 			rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1973 		else
1974 			rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1975 		break;
1976 	case 3:
1977 		rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1978 		break;
1979 	}
1980 
1981 	/*
1982 	 * Configure the RX antenna.
1983 	 */
1984 	switch (ant->rx_chain_num) {
1985 	case 1:
1986 		if (rt2x00_rt(rt2x00dev, RT3070) ||
1987 		    rt2x00_rt(rt2x00dev, RT3090) ||
1988 		    rt2x00_rt(rt2x00dev, RT3352) ||
1989 		    rt2x00_rt(rt2x00dev, RT3390)) {
1990 			eeprom = rt2800_eeprom_read(rt2x00dev,
1991 						    EEPROM_NIC_CONF1);
1992 			if (rt2x00_get_field16(eeprom,
1993 						EEPROM_NIC_CONF1_ANT_DIVERSITY))
1994 				rt2800_set_ant_diversity(rt2x00dev,
1995 						rt2x00dev->default_ant.rx);
1996 		}
1997 		rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1998 		break;
1999 	case 2:
2000 		if (rt2x00_rt(rt2x00dev, RT3572) &&
2001 		    rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2002 			rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
2003 			rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
2004 				rt2x00dev->curr_band == NL80211_BAND_5GHZ);
2005 			rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
2006 		} else {
2007 			rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
2008 		}
2009 		break;
2010 	case 3:
2011 		rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
2012 		break;
2013 	}
2014 
2015 	rt2800_bbp_write(rt2x00dev, 3, r3);
2016 	rt2800_bbp_write(rt2x00dev, 1, r1);
2017 
2018 	if (rt2x00_rt(rt2x00dev, RT3593)) {
2019 		if (ant->rx_chain_num == 1)
2020 			rt2800_bbp_write(rt2x00dev, 86, 0x00);
2021 		else
2022 			rt2800_bbp_write(rt2x00dev, 86, 0x46);
2023 	}
2024 }
2025 EXPORT_SYMBOL_GPL(rt2800_config_ant);
2026 
2027 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
2028 				   struct rt2x00lib_conf *libconf)
2029 {
2030 	u16 eeprom;
2031 	short lna_gain;
2032 
2033 	if (libconf->rf.channel <= 14) {
2034 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2035 		lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
2036 	} else if (libconf->rf.channel <= 64) {
2037 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2038 		lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
2039 	} else if (libconf->rf.channel <= 128) {
2040 		if (rt2x00_rt(rt2x00dev, RT3593)) {
2041 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2042 			lna_gain = rt2x00_get_field16(eeprom,
2043 						      EEPROM_EXT_LNA2_A1);
2044 		} else {
2045 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
2046 			lna_gain = rt2x00_get_field16(eeprom,
2047 						      EEPROM_RSSI_BG2_LNA_A1);
2048 		}
2049 	} else {
2050 		if (rt2x00_rt(rt2x00dev, RT3593)) {
2051 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2052 			lna_gain = rt2x00_get_field16(eeprom,
2053 						      EEPROM_EXT_LNA2_A2);
2054 		} else {
2055 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
2056 			lna_gain = rt2x00_get_field16(eeprom,
2057 						      EEPROM_RSSI_A2_LNA_A2);
2058 		}
2059 	}
2060 
2061 	rt2x00dev->lna_gain = lna_gain;
2062 }
2063 
2064 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)
2065 {
2066 	return clk_get_rate(rt2x00dev->clk) == 20000000;
2067 }
2068 
2069 #define FREQ_OFFSET_BOUND	0x5f
2070 
2071 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
2072 {
2073 	u8 freq_offset, prev_freq_offset;
2074 	u8 rfcsr, prev_rfcsr;
2075 
2076 	freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2077 	freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
2078 
2079 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
2080 	prev_rfcsr = rfcsr;
2081 
2082 	rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
2083 	if (rfcsr == prev_rfcsr)
2084 		return;
2085 
2086 	if (rt2x00_is_usb(rt2x00dev)) {
2087 		rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
2088 				   freq_offset, prev_rfcsr);
2089 		return;
2090 	}
2091 
2092 	prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
2093 	while (prev_freq_offset != freq_offset) {
2094 		if (prev_freq_offset < freq_offset)
2095 			prev_freq_offset++;
2096 		else
2097 			prev_freq_offset--;
2098 
2099 		rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
2100 		rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2101 
2102 		usleep_range(1000, 1500);
2103 	}
2104 }
2105 
2106 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
2107 					 struct ieee80211_conf *conf,
2108 					 struct rf_channel *rf,
2109 					 struct channel_info *info)
2110 {
2111 	rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
2112 
2113 	if (rt2x00dev->default_ant.tx_chain_num == 1)
2114 		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
2115 
2116 	if (rt2x00dev->default_ant.rx_chain_num == 1) {
2117 		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
2118 		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2119 	} else if (rt2x00dev->default_ant.rx_chain_num == 2)
2120 		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2121 
2122 	if (rf->channel > 14) {
2123 		/*
2124 		 * When TX power is below 0, we should increase it by 7 to
2125 		 * make it a positive value (Minimum value is -7).
2126 		 * However this means that values between 0 and 7 have
2127 		 * double meaning, and we should set a 7DBm boost flag.
2128 		 */
2129 		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
2130 				   (info->default_power1 >= 0));
2131 
2132 		if (info->default_power1 < 0)
2133 			info->default_power1 += 7;
2134 
2135 		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
2136 
2137 		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
2138 				   (info->default_power2 >= 0));
2139 
2140 		if (info->default_power2 < 0)
2141 			info->default_power2 += 7;
2142 
2143 		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
2144 	} else {
2145 		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2146 		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
2147 	}
2148 
2149 	rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2150 
2151 	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2152 	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2153 	rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2154 	rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2155 
2156 	udelay(200);
2157 
2158 	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2159 	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2160 	rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2161 	rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2162 
2163 	udelay(200);
2164 
2165 	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2166 	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2167 	rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2168 	rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2169 }
2170 
2171 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2172 					 struct ieee80211_conf *conf,
2173 					 struct rf_channel *rf,
2174 					 struct channel_info *info)
2175 {
2176 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2177 	u8 rfcsr, calib_tx, calib_rx;
2178 
2179 	rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2180 
2181 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2182 	rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2183 	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2184 
2185 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2186 	rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2187 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2188 
2189 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2190 	rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2191 	rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2192 
2193 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2194 	rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2195 	rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2196 
2197 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2198 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2199 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2200 			  rt2x00dev->default_ant.rx_chain_num <= 1);
2201 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2202 			  rt2x00dev->default_ant.rx_chain_num <= 2);
2203 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2204 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2205 			  rt2x00dev->default_ant.tx_chain_num <= 1);
2206 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2207 			  rt2x00dev->default_ant.tx_chain_num <= 2);
2208 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2209 
2210 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2211 	rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2212 	rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2213 
2214 	if (rt2x00_rt(rt2x00dev, RT3390)) {
2215 		calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2216 		calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2217 	} else {
2218 		if (conf_is_ht40(conf)) {
2219 			calib_tx = drv_data->calibration_bw40;
2220 			calib_rx = drv_data->calibration_bw40;
2221 		} else {
2222 			calib_tx = drv_data->calibration_bw20;
2223 			calib_rx = drv_data->calibration_bw20;
2224 		}
2225 	}
2226 
2227 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 24);
2228 	rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2229 	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2230 
2231 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
2232 	rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2233 	rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2234 
2235 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2236 	rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2237 	rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2238 
2239 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2240 	rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2241 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2242 
2243 	usleep_range(1000, 1500);
2244 
2245 	rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2246 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2247 }
2248 
2249 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2250 					 struct ieee80211_conf *conf,
2251 					 struct rf_channel *rf,
2252 					 struct channel_info *info)
2253 {
2254 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2255 	u8 rfcsr;
2256 	u32 reg;
2257 
2258 	if (rf->channel <= 14) {
2259 		rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2260 		rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2261 	} else {
2262 		rt2800_bbp_write(rt2x00dev, 25, 0x09);
2263 		rt2800_bbp_write(rt2x00dev, 26, 0xff);
2264 	}
2265 
2266 	rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2267 	rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2268 
2269 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2270 	rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2271 	if (rf->channel <= 14)
2272 		rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2273 	else
2274 		rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2275 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2276 
2277 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 5);
2278 	if (rf->channel <= 14)
2279 		rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2280 	else
2281 		rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2282 	rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2283 
2284 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2285 	if (rf->channel <= 14) {
2286 		rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2287 		rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2288 				  info->default_power1);
2289 	} else {
2290 		rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2291 		rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2292 				(info->default_power1 & 0x3) |
2293 				((info->default_power1 & 0xC) << 1));
2294 	}
2295 	rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2296 
2297 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2298 	if (rf->channel <= 14) {
2299 		rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2300 		rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2301 				  info->default_power2);
2302 	} else {
2303 		rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2304 		rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2305 				(info->default_power2 & 0x3) |
2306 				((info->default_power2 & 0xC) << 1));
2307 	}
2308 	rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2309 
2310 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2311 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2312 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2313 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2314 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2315 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2316 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2317 	if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2318 		if (rf->channel <= 14) {
2319 			rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2320 			rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2321 		}
2322 		rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2323 		rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2324 	} else {
2325 		switch (rt2x00dev->default_ant.tx_chain_num) {
2326 		case 1:
2327 			rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2328 		case 2:
2329 			rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2330 			break;
2331 		}
2332 
2333 		switch (rt2x00dev->default_ant.rx_chain_num) {
2334 		case 1:
2335 			rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2336 		case 2:
2337 			rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2338 			break;
2339 		}
2340 	}
2341 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2342 
2343 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2344 	rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2345 	rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2346 
2347 	if (conf_is_ht40(conf)) {
2348 		rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2349 		rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2350 	} else {
2351 		rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2352 		rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2353 	}
2354 
2355 	if (rf->channel <= 14) {
2356 		rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2357 		rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2358 		rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2359 		rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2360 		rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2361 		rfcsr = 0x4c;
2362 		rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2363 				  drv_data->txmixer_gain_24g);
2364 		rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2365 		rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2366 		rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2367 		rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2368 		rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2369 		rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2370 		rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2371 		rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2372 	} else {
2373 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2374 		rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2375 		rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2376 		rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2377 		rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2378 		rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2379 		rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2380 		rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2381 		rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2382 		rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2383 		rfcsr = 0x7a;
2384 		rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2385 				  drv_data->txmixer_gain_5g);
2386 		rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2387 		rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2388 		if (rf->channel <= 64) {
2389 			rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2390 			rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2391 			rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2392 		} else if (rf->channel <= 128) {
2393 			rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2394 			rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2395 			rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2396 		} else {
2397 			rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2398 			rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2399 			rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2400 		}
2401 		rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2402 		rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2403 		rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2404 	}
2405 
2406 	reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2407 	rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2408 	if (rf->channel <= 14)
2409 		rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2410 	else
2411 		rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2412 	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2413 
2414 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2415 	rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2416 	rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2417 }
2418 
2419 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2420 					 struct ieee80211_conf *conf,
2421 					 struct rf_channel *rf,
2422 					 struct channel_info *info)
2423 {
2424 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2425 	u8 txrx_agc_fc;
2426 	u8 txrx_h20m;
2427 	u8 rfcsr;
2428 	u8 bbp;
2429 	const bool txbf_enabled = false; /* TODO */
2430 
2431 	/* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2432 	bbp = rt2800_bbp_read(rt2x00dev, 109);
2433 	rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2434 	rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2435 	rt2800_bbp_write(rt2x00dev, 109, bbp);
2436 
2437 	bbp = rt2800_bbp_read(rt2x00dev, 110);
2438 	rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2439 	rt2800_bbp_write(rt2x00dev, 110, bbp);
2440 
2441 	if (rf->channel <= 14) {
2442 		/* Restore BBP 25 & 26 for 2.4 GHz */
2443 		rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2444 		rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2445 	} else {
2446 		/* Hard code BBP 25 & 26 for 5GHz */
2447 
2448 		/* Enable IQ Phase correction */
2449 		rt2800_bbp_write(rt2x00dev, 25, 0x09);
2450 		/* Setup IQ Phase correction value */
2451 		rt2800_bbp_write(rt2x00dev, 26, 0xff);
2452 	}
2453 
2454 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2455 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2456 
2457 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2458 	rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2459 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2460 
2461 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2462 	rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2463 	if (rf->channel <= 14)
2464 		rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2465 	else
2466 		rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2467 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2468 
2469 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 53);
2470 	if (rf->channel <= 14) {
2471 		rfcsr = 0;
2472 		rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2473 				  info->default_power1 & 0x1f);
2474 	} else {
2475 		if (rt2x00_is_usb(rt2x00dev))
2476 			rfcsr = 0x40;
2477 
2478 		rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2479 				  ((info->default_power1 & 0x18) << 1) |
2480 				  (info->default_power1 & 7));
2481 	}
2482 	rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2483 
2484 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 55);
2485 	if (rf->channel <= 14) {
2486 		rfcsr = 0;
2487 		rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2488 				  info->default_power2 & 0x1f);
2489 	} else {
2490 		if (rt2x00_is_usb(rt2x00dev))
2491 			rfcsr = 0x40;
2492 
2493 		rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2494 				  ((info->default_power2 & 0x18) << 1) |
2495 				  (info->default_power2 & 7));
2496 	}
2497 	rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2498 
2499 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 54);
2500 	if (rf->channel <= 14) {
2501 		rfcsr = 0;
2502 		rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2503 				  info->default_power3 & 0x1f);
2504 	} else {
2505 		if (rt2x00_is_usb(rt2x00dev))
2506 			rfcsr = 0x40;
2507 
2508 		rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2509 				  ((info->default_power3 & 0x18) << 1) |
2510 				  (info->default_power3 & 7));
2511 	}
2512 	rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2513 
2514 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2515 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2516 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2517 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2518 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2519 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2520 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2521 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2522 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2523 
2524 	switch (rt2x00dev->default_ant.tx_chain_num) {
2525 	case 3:
2526 		rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2527 		/* fallthrough */
2528 	case 2:
2529 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2530 		/* fallthrough */
2531 	case 1:
2532 		rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2533 		break;
2534 	}
2535 
2536 	switch (rt2x00dev->default_ant.rx_chain_num) {
2537 	case 3:
2538 		rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2539 		/* fallthrough */
2540 	case 2:
2541 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2542 		/* fallthrough */
2543 	case 1:
2544 		rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2545 		break;
2546 	}
2547 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2548 
2549 	rt2800_freq_cal_mode1(rt2x00dev);
2550 
2551 	if (conf_is_ht40(conf)) {
2552 		txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2553 						RFCSR24_TX_AGC_FC);
2554 		txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2555 					      RFCSR24_TX_H20M);
2556 	} else {
2557 		txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2558 						RFCSR24_TX_AGC_FC);
2559 		txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2560 					      RFCSR24_TX_H20M);
2561 	}
2562 
2563 	/* NOTE: the reference driver does not writes the new value
2564 	 * back to RFCSR 32
2565 	 */
2566 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 32);
2567 	rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2568 
2569 	if (rf->channel <= 14)
2570 		rfcsr = 0xa0;
2571 	else
2572 		rfcsr = 0x80;
2573 	rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2574 
2575 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2576 	rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2577 	rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2578 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2579 
2580 	/* Band selection */
2581 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
2582 	if (rf->channel <= 14)
2583 		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2584 	else
2585 		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2586 	rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2587 
2588 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 34);
2589 	if (rf->channel <= 14)
2590 		rfcsr = 0x3c;
2591 	else
2592 		rfcsr = 0x20;
2593 	rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2594 
2595 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2596 	if (rf->channel <= 14)
2597 		rfcsr = 0x1a;
2598 	else
2599 		rfcsr = 0x12;
2600 	rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2601 
2602 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2603 	if (rf->channel >= 1 && rf->channel <= 14)
2604 		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2605 	else if (rf->channel >= 36 && rf->channel <= 64)
2606 		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2607 	else if (rf->channel >= 100 && rf->channel <= 128)
2608 		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2609 	else
2610 		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2611 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2612 
2613 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2614 	rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2615 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2616 
2617 	rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2618 
2619 	if (rf->channel <= 14) {
2620 		rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2621 		rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2622 	} else {
2623 		rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2624 		rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2625 	}
2626 
2627 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2628 	rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2629 	rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2630 
2631 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2632 	if (rf->channel <= 14) {
2633 		rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2634 		rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2635 	} else {
2636 		rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2637 		rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2638 	}
2639 	rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2640 
2641 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2642 	if (rf->channel <= 14)
2643 		rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2644 	else
2645 		rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2646 
2647 	if (txbf_enabled)
2648 		rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2649 
2650 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2651 
2652 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
2653 	rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2654 	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2655 
2656 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
2657 	if (rf->channel <= 14)
2658 		rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2659 	else
2660 		rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2661 	rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2662 
2663 	if (rf->channel <= 14) {
2664 		rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2665 		rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2666 	} else {
2667 		rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2668 		rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2669 	}
2670 
2671 	/* Initiate VCO calibration */
2672 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2673 	if (rf->channel <= 14) {
2674 		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2675 	} else {
2676 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2677 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2678 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2679 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2680 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2681 		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2682 	}
2683 	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2684 
2685 	if (rf->channel >= 1 && rf->channel <= 14) {
2686 		rfcsr = 0x23;
2687 		if (txbf_enabled)
2688 			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2689 		rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2690 
2691 		rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2692 	} else if (rf->channel >= 36 && rf->channel <= 64) {
2693 		rfcsr = 0x36;
2694 		if (txbf_enabled)
2695 			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2696 		rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2697 
2698 		rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2699 	} else if (rf->channel >= 100 && rf->channel <= 128) {
2700 		rfcsr = 0x32;
2701 		if (txbf_enabled)
2702 			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2703 		rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2704 
2705 		rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2706 	} else {
2707 		rfcsr = 0x30;
2708 		if (txbf_enabled)
2709 			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2710 		rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2711 
2712 		rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2713 	}
2714 }
2715 
2716 #define POWER_BOUND		0x27
2717 #define POWER_BOUND_5G		0x2b
2718 
2719 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2720 					 struct ieee80211_conf *conf,
2721 					 struct rf_channel *rf,
2722 					 struct channel_info *info)
2723 {
2724 	u8 rfcsr;
2725 
2726 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2727 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2728 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2729 	rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2730 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2731 
2732 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2733 	if (info->default_power1 > POWER_BOUND)
2734 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2735 	else
2736 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2737 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2738 
2739 	rt2800_freq_cal_mode1(rt2x00dev);
2740 
2741 	if (rf->channel <= 14) {
2742 		if (rf->channel == 6)
2743 			rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2744 		else
2745 			rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2746 
2747 		if (rf->channel >= 1 && rf->channel <= 6)
2748 			rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2749 		else if (rf->channel >= 7 && rf->channel <= 11)
2750 			rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2751 		else if (rf->channel >= 12 && rf->channel <= 14)
2752 			rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2753 	}
2754 }
2755 
2756 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2757 					 struct ieee80211_conf *conf,
2758 					 struct rf_channel *rf,
2759 					 struct channel_info *info)
2760 {
2761 	u8 rfcsr;
2762 
2763 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2764 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2765 
2766 	rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2767 	rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2768 	rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2769 
2770 	if (info->default_power1 > POWER_BOUND)
2771 		rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2772 	else
2773 		rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2774 
2775 	if (info->default_power2 > POWER_BOUND)
2776 		rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2777 	else
2778 		rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2779 
2780 	rt2800_freq_cal_mode1(rt2x00dev);
2781 
2782 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2783 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2784 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2785 
2786 	if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2787 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2788 	else
2789 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2790 
2791 	if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2792 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2793 	else
2794 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2795 
2796 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2797 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2798 
2799 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2800 
2801 	rt2800_rfcsr_write(rt2x00dev, 31, 80);
2802 }
2803 
2804 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2805 					 struct ieee80211_conf *conf,
2806 					 struct rf_channel *rf,
2807 					 struct channel_info *info)
2808 {
2809 	u8 rfcsr;
2810 
2811 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2812 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2813 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2814 	rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2815 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2816 
2817 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2818 	if (info->default_power1 > POWER_BOUND)
2819 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2820 	else
2821 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2822 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2823 
2824 	if (rt2x00_rt(rt2x00dev, RT5392)) {
2825 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
2826 		if (info->default_power2 > POWER_BOUND)
2827 			rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2828 		else
2829 			rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2830 					  info->default_power2);
2831 		rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2832 	}
2833 
2834 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2835 	if (rt2x00_rt(rt2x00dev, RT5392)) {
2836 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2837 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2838 	}
2839 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2840 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2841 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2842 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2843 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2844 
2845 	rt2800_freq_cal_mode1(rt2x00dev);
2846 
2847 	if (rf->channel <= 14) {
2848 		int idx = rf->channel-1;
2849 
2850 		if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2851 			if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2852 				/* r55/r59 value array of channel 1~14 */
2853 				static const char r55_bt_rev[] = {0x83, 0x83,
2854 					0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2855 					0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2856 				static const char r59_bt_rev[] = {0x0e, 0x0e,
2857 					0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2858 					0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2859 
2860 				rt2800_rfcsr_write(rt2x00dev, 55,
2861 						   r55_bt_rev[idx]);
2862 				rt2800_rfcsr_write(rt2x00dev, 59,
2863 						   r59_bt_rev[idx]);
2864 			} else {
2865 				static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2866 					0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2867 					0x88, 0x88, 0x86, 0x85, 0x84};
2868 
2869 				rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2870 			}
2871 		} else {
2872 			if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2873 				static const char r55_nonbt_rev[] = {0x23, 0x23,
2874 					0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2875 					0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2876 				static const char r59_nonbt_rev[] = {0x07, 0x07,
2877 					0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2878 					0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2879 
2880 				rt2800_rfcsr_write(rt2x00dev, 55,
2881 						   r55_nonbt_rev[idx]);
2882 				rt2800_rfcsr_write(rt2x00dev, 59,
2883 						   r59_nonbt_rev[idx]);
2884 			} else if (rt2x00_rt(rt2x00dev, RT5390) ||
2885 				   rt2x00_rt(rt2x00dev, RT5392) ||
2886 				   rt2x00_rt(rt2x00dev, RT6352)) {
2887 				static const char r59_non_bt[] = {0x8f, 0x8f,
2888 					0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2889 					0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2890 
2891 				rt2800_rfcsr_write(rt2x00dev, 59,
2892 						   r59_non_bt[idx]);
2893 			} else if (rt2x00_rt(rt2x00dev, RT5350)) {
2894 				static const char r59_non_bt[] = {0x0b, 0x0b,
2895 					0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
2896 					0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
2897 
2898 				rt2800_rfcsr_write(rt2x00dev, 59,
2899 						   r59_non_bt[idx]);
2900 			}
2901 		}
2902 	}
2903 }
2904 
2905 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2906 					 struct ieee80211_conf *conf,
2907 					 struct rf_channel *rf,
2908 					 struct channel_info *info)
2909 {
2910 	u8 rfcsr, ep_reg;
2911 	u32 reg;
2912 	int power_bound;
2913 
2914 	/* TODO */
2915 	const bool is_11b = false;
2916 	const bool is_type_ep = false;
2917 
2918 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
2919 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2920 			   (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2921 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2922 
2923 	/* Order of values on rf_channel entry: N, K, mod, R */
2924 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2925 
2926 	rfcsr = rt2800_rfcsr_read(rt2x00dev,  9);
2927 	rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2928 	rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2929 	rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2930 	rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2931 
2932 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2933 	rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2934 	rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2935 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2936 
2937 	if (rf->channel <= 14) {
2938 		rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2939 		/* FIXME: RF11 owerwrite ? */
2940 		rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2941 		rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2942 		rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2943 		rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2944 		rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2945 		rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2946 		rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2947 		rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2948 		rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2949 		rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2950 		rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2951 		rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2952 		rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2953 		rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2954 		rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2955 		rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2956 		rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2957 		rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2958 		rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2959 		rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2960 		rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2961 		rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2962 		rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2963 		rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2964 		rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2965 		rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2966 		rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2967 		rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2968 
2969 		/* TODO RF27 <- tssi */
2970 
2971 		rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2972 		rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2973 		rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2974 
2975 		if (is_11b) {
2976 			/* CCK */
2977 			rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2978 			rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2979 			if (is_type_ep)
2980 				rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2981 			else
2982 				rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2983 		} else {
2984 			/* OFDM */
2985 			if (is_type_ep)
2986 				rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2987 			else
2988 				rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2989 		}
2990 
2991 		power_bound = POWER_BOUND;
2992 		ep_reg = 0x2;
2993 	} else {
2994 		rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2995 		/* FIMXE: RF11 overwrite */
2996 		rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2997 		rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2998 		rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2999 		rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3000 		rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
3001 		rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3002 		rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
3003 		rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
3004 		rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
3005 		rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
3006 		rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
3007 		rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
3008 		rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
3009 		rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
3010 
3011 		/* TODO RF27 <- tssi */
3012 
3013 		if (rf->channel >= 36 && rf->channel <= 64) {
3014 
3015 			rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
3016 			rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
3017 			rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
3018 			rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
3019 			if (rf->channel <= 50)
3020 				rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
3021 			else if (rf->channel >= 52)
3022 				rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
3023 			rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
3024 			rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
3025 			rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
3026 			rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
3027 			rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
3028 			rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
3029 			rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
3030 			if (rf->channel <= 50) {
3031 				rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
3032 				rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
3033 			} else if (rf->channel >= 52) {
3034 				rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
3035 				rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3036 			}
3037 
3038 			rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3039 			rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
3040 			rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3041 
3042 		} else if (rf->channel >= 100 && rf->channel <= 165) {
3043 
3044 			rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
3045 			rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3046 			rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3047 			if (rf->channel <= 153) {
3048 				rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
3049 				rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
3050 			} else if (rf->channel >= 155) {
3051 				rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
3052 				rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
3053 			}
3054 			if (rf->channel <= 138) {
3055 				rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
3056 				rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
3057 				rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
3058 				rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
3059 			} else if (rf->channel >= 140) {
3060 				rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
3061 				rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
3062 				rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
3063 				rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
3064 			}
3065 			if (rf->channel <= 124)
3066 				rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
3067 			else if (rf->channel >= 126)
3068 				rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
3069 			if (rf->channel <= 138)
3070 				rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3071 			else if (rf->channel >= 140)
3072 				rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3073 			rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
3074 			if (rf->channel <= 138)
3075 				rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
3076 			else if (rf->channel >= 140)
3077 				rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
3078 			if (rf->channel <= 128)
3079 				rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3080 			else if (rf->channel >= 130)
3081 				rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
3082 			if (rf->channel <= 116)
3083 				rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
3084 			else if (rf->channel >= 118)
3085 				rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3086 			if (rf->channel <= 138)
3087 				rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
3088 			else if (rf->channel >= 140)
3089 				rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
3090 			if (rf->channel <= 116)
3091 				rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
3092 			else if (rf->channel >= 118)
3093 				rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3094 		}
3095 
3096 		power_bound = POWER_BOUND_5G;
3097 		ep_reg = 0x3;
3098 	}
3099 
3100 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3101 	if (info->default_power1 > power_bound)
3102 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
3103 	else
3104 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3105 	if (is_type_ep)
3106 		rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
3107 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3108 
3109 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3110 	if (info->default_power2 > power_bound)
3111 		rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
3112 	else
3113 		rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
3114 	if (is_type_ep)
3115 		rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
3116 	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3117 
3118 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3119 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3120 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3121 
3122 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
3123 			  rt2x00dev->default_ant.tx_chain_num >= 1);
3124 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
3125 			  rt2x00dev->default_ant.tx_chain_num == 2);
3126 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3127 
3128 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
3129 			  rt2x00dev->default_ant.rx_chain_num >= 1);
3130 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
3131 			  rt2x00dev->default_ant.rx_chain_num == 2);
3132 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3133 
3134 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3135 	rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
3136 
3137 	if (conf_is_ht40(conf))
3138 		rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
3139 	else
3140 		rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3141 
3142 	if (!is_11b) {
3143 		rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3144 		rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3145 	}
3146 
3147 	/* TODO proper frequency adjustment */
3148 	rt2800_freq_cal_mode1(rt2x00dev);
3149 
3150 	/* TODO merge with others */
3151 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3152 	rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3153 	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3154 
3155 	/* BBP settings */
3156 	rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3157 	rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3158 	rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3159 
3160 	rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3161 	rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3162 	rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3163 	rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3164 
3165 	/* GLRT band configuration */
3166 	rt2800_bbp_write(rt2x00dev, 195, 128);
3167 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3168 	rt2800_bbp_write(rt2x00dev, 195, 129);
3169 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3170 	rt2800_bbp_write(rt2x00dev, 195, 130);
3171 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3172 	rt2800_bbp_write(rt2x00dev, 195, 131);
3173 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3174 	rt2800_bbp_write(rt2x00dev, 195, 133);
3175 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3176 	rt2800_bbp_write(rt2x00dev, 195, 124);
3177 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
3178 }
3179 
3180 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
3181 					 struct ieee80211_conf *conf,
3182 					 struct rf_channel *rf,
3183 					 struct channel_info *info)
3184 {
3185 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3186 	u8 rx_agc_fc, tx_agc_fc;
3187 	u8 rfcsr;
3188 
3189 	/* Frequeny plan setting */
3190 	/* Rdiv setting (set 0x03 if Xtal==20)
3191 	 * R13[1:0]
3192 	 */
3193 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
3194 	rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
3195 			  rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
3196 	rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
3197 
3198 	/* N setting
3199 	 * R20[7:0] in rf->rf1
3200 	 * R21[0] always 0
3201 	 */
3202 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
3203 	rfcsr = (rf->rf1 & 0x00ff);
3204 	rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3205 
3206 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3207 	rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
3208 	rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3209 
3210 	/* K setting (always 0)
3211 	 * R16[3:0] (RF PLL freq selection)
3212 	 */
3213 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3214 	rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
3215 	rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3216 
3217 	/* D setting (always 0)
3218 	 * R22[2:0] (D=15, R22[2:0]=<111>)
3219 	 */
3220 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
3221 	rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
3222 	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3223 
3224 	/* Ksd setting
3225 	 * Ksd: R17<7:0> in rf->rf2
3226 	 *      R18<7:0> in rf->rf3
3227 	 *      R19<1:0> in rf->rf4
3228 	 */
3229 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
3230 	rfcsr = rf->rf2;
3231 	rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3232 
3233 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
3234 	rfcsr = rf->rf3;
3235 	rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
3236 
3237 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 19);
3238 	rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
3239 	rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
3240 
3241 	/* Default: XO=20MHz , SDM mode */
3242 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3243 	rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
3244 	rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3245 
3246 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3247 	rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
3248 	rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3249 
3250 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3251 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
3252 			  rt2x00dev->default_ant.tx_chain_num != 1);
3253 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3254 
3255 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
3256 	rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
3257 			  rt2x00dev->default_ant.tx_chain_num != 1);
3258 	rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
3259 			  rt2x00dev->default_ant.rx_chain_num != 1);
3260 	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3261 
3262 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 42);
3263 	rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
3264 			  rt2x00dev->default_ant.tx_chain_num != 1);
3265 	rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
3266 
3267 	/* RF for DC Cal BW */
3268 	if (conf_is_ht40(conf)) {
3269 		rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
3270 		rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
3271 		rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
3272 		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
3273 		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
3274 	} else {
3275 		rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
3276 		rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
3277 		rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
3278 		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
3279 		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
3280 	}
3281 
3282 	if (conf_is_ht40(conf)) {
3283 		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
3284 		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
3285 	} else {
3286 		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
3287 		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
3288 	}
3289 
3290 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
3291 	rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
3292 			  conf_is_ht40(conf) && (rf->channel == 11));
3293 	rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
3294 
3295 	if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
3296 		if (conf_is_ht40(conf)) {
3297 			rx_agc_fc = drv_data->rx_calibration_bw40;
3298 			tx_agc_fc = drv_data->tx_calibration_bw40;
3299 		} else {
3300 			rx_agc_fc = drv_data->rx_calibration_bw20;
3301 			tx_agc_fc = drv_data->tx_calibration_bw20;
3302 		}
3303 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
3304 		rfcsr &= (~0x3F);
3305 		rfcsr |= rx_agc_fc;
3306 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
3307 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
3308 		rfcsr &= (~0x3F);
3309 		rfcsr |= rx_agc_fc;
3310 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
3311 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6);
3312 		rfcsr &= (~0x3F);
3313 		rfcsr |= rx_agc_fc;
3314 		rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
3315 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7);
3316 		rfcsr &= (~0x3F);
3317 		rfcsr |= rx_agc_fc;
3318 		rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
3319 
3320 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
3321 		rfcsr &= (~0x3F);
3322 		rfcsr |= tx_agc_fc;
3323 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
3324 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
3325 		rfcsr &= (~0x3F);
3326 		rfcsr |= tx_agc_fc;
3327 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
3328 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58);
3329 		rfcsr &= (~0x3F);
3330 		rfcsr |= tx_agc_fc;
3331 		rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
3332 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59);
3333 		rfcsr &= (~0x3F);
3334 		rfcsr |= tx_agc_fc;
3335 		rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
3336 	}
3337 }
3338 
3339 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
3340 			      struct ieee80211_channel *chan,
3341 			      int power_level) {
3342 	u16 eeprom, target_power, max_power;
3343 	u32 mac_sys_ctrl, mac_status;
3344 	u32 reg;
3345 	u8 bbp;
3346 	int i;
3347 
3348 	/* hardware unit is 0.5dBm, limited to 23.5dBm */
3349 	power_level *= 2;
3350 	if (power_level > 0x2f)
3351 		power_level = 0x2f;
3352 
3353 	max_power = chan->max_power * 2;
3354 	if (max_power > 0x2f)
3355 		max_power = 0x2f;
3356 
3357 	reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0);
3358 	rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, power_level);
3359 	rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, power_level);
3360 	rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, max_power);
3361 	rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, max_power);
3362 
3363 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
3364 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
3365 		/* init base power by eeprom target power */
3366 		target_power = rt2800_eeprom_read(rt2x00dev,
3367 						  EEPROM_TXPOWER_INIT);
3368 		rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, target_power);
3369 		rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, target_power);
3370 	}
3371 	rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
3372 
3373 	reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
3374 	rt2x00_set_field32(&reg, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
3375 	rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
3376 
3377 	/* Save MAC SYS CTRL registers */
3378 	mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
3379 	/* Disable Tx/Rx */
3380 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
3381 	/* Check MAC Tx/Rx idle */
3382 	for (i = 0; i < 10000; i++) {
3383 		mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
3384 		if (mac_status & 0x3)
3385 			usleep_range(50, 200);
3386 		else
3387 			break;
3388 	}
3389 
3390 	if (i == 10000)
3391 		rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
3392 
3393 	if (chan->center_freq > 2457) {
3394 		bbp = rt2800_bbp_read(rt2x00dev, 30);
3395 		bbp = 0x40;
3396 		rt2800_bbp_write(rt2x00dev, 30, bbp);
3397 		rt2800_rfcsr_write(rt2x00dev, 39, 0);
3398 		if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3399 			rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
3400 		else
3401 			rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
3402 	} else {
3403 		bbp = rt2800_bbp_read(rt2x00dev, 30);
3404 		bbp = 0x1f;
3405 		rt2800_bbp_write(rt2x00dev, 30, bbp);
3406 		rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
3407 		if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3408 			rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
3409 		else
3410 			rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
3411 	}
3412 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
3413 
3414 	rt2800_vco_calibration(rt2x00dev);
3415 }
3416 
3417 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3418 					   const unsigned int word,
3419 					   const u8 value)
3420 {
3421 	u8 chain, reg;
3422 
3423 	for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3424 		reg = rt2800_bbp_read(rt2x00dev, 27);
3425 		rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
3426 		rt2800_bbp_write(rt2x00dev, 27, reg);
3427 
3428 		rt2800_bbp_write(rt2x00dev, word, value);
3429 	}
3430 }
3431 
3432 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3433 {
3434 	u8 cal;
3435 
3436 	/* TX0 IQ Gain */
3437 	rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3438 	if (channel <= 14)
3439 		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3440 	else if (channel >= 36 && channel <= 64)
3441 		cal = rt2x00_eeprom_byte(rt2x00dev,
3442 					 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3443 	else if (channel >= 100 && channel <= 138)
3444 		cal = rt2x00_eeprom_byte(rt2x00dev,
3445 					 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3446 	else if (channel >= 140 && channel <= 165)
3447 		cal = rt2x00_eeprom_byte(rt2x00dev,
3448 					 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3449 	else
3450 		cal = 0;
3451 	rt2800_bbp_write(rt2x00dev, 159, cal);
3452 
3453 	/* TX0 IQ Phase */
3454 	rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3455 	if (channel <= 14)
3456 		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3457 	else if (channel >= 36 && channel <= 64)
3458 		cal = rt2x00_eeprom_byte(rt2x00dev,
3459 					 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3460 	else if (channel >= 100 && channel <= 138)
3461 		cal = rt2x00_eeprom_byte(rt2x00dev,
3462 					 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3463 	else if (channel >= 140 && channel <= 165)
3464 		cal = rt2x00_eeprom_byte(rt2x00dev,
3465 					 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3466 	else
3467 		cal = 0;
3468 	rt2800_bbp_write(rt2x00dev, 159, cal);
3469 
3470 	/* TX1 IQ Gain */
3471 	rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3472 	if (channel <= 14)
3473 		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3474 	else if (channel >= 36 && channel <= 64)
3475 		cal = rt2x00_eeprom_byte(rt2x00dev,
3476 					 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3477 	else if (channel >= 100 && channel <= 138)
3478 		cal = rt2x00_eeprom_byte(rt2x00dev,
3479 					 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3480 	else if (channel >= 140 && channel <= 165)
3481 		cal = rt2x00_eeprom_byte(rt2x00dev,
3482 					 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3483 	else
3484 		cal = 0;
3485 	rt2800_bbp_write(rt2x00dev, 159, cal);
3486 
3487 	/* TX1 IQ Phase */
3488 	rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3489 	if (channel <= 14)
3490 		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3491 	else if (channel >= 36 && channel <= 64)
3492 		cal = rt2x00_eeprom_byte(rt2x00dev,
3493 					 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3494 	else if (channel >= 100 && channel <= 138)
3495 		cal = rt2x00_eeprom_byte(rt2x00dev,
3496 					 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3497 	else if (channel >= 140 && channel <= 165)
3498 		cal = rt2x00_eeprom_byte(rt2x00dev,
3499 					 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3500 	else
3501 		cal = 0;
3502 	rt2800_bbp_write(rt2x00dev, 159, cal);
3503 
3504 	/* FIXME: possible RX0, RX1 callibration ? */
3505 
3506 	/* RF IQ compensation control */
3507 	rt2800_bbp_write(rt2x00dev, 158, 0x04);
3508 	cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3509 	rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3510 
3511 	/* RF IQ imbalance compensation control */
3512 	rt2800_bbp_write(rt2x00dev, 158, 0x03);
3513 	cal = rt2x00_eeprom_byte(rt2x00dev,
3514 				 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3515 	rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3516 }
3517 
3518 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3519 				  unsigned int channel,
3520 				  char txpower)
3521 {
3522 	if (rt2x00_rt(rt2x00dev, RT3593))
3523 		txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3524 
3525 	if (channel <= 14)
3526 		return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3527 
3528 	if (rt2x00_rt(rt2x00dev, RT3593))
3529 		return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3530 			       MAX_A_TXPOWER_3593);
3531 	else
3532 		return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3533 }
3534 
3535 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3536 				  struct ieee80211_conf *conf,
3537 				  struct rf_channel *rf,
3538 				  struct channel_info *info)
3539 {
3540 	u32 reg;
3541 	u32 tx_pin;
3542 	u8 bbp, rfcsr;
3543 
3544 	info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3545 						     info->default_power1);
3546 	info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3547 						     info->default_power2);
3548 	if (rt2x00dev->default_ant.tx_chain_num > 2)
3549 		info->default_power3 =
3550 			rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3551 					      info->default_power3);
3552 
3553 	switch (rt2x00dev->chip.rf) {
3554 	case RF2020:
3555 	case RF3020:
3556 	case RF3021:
3557 	case RF3022:
3558 	case RF3320:
3559 		rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
3560 		break;
3561 	case RF3052:
3562 		rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
3563 		break;
3564 	case RF3053:
3565 		rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3566 		break;
3567 	case RF3290:
3568 		rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3569 		break;
3570 	case RF3322:
3571 		rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3572 		break;
3573 	case RF3070:
3574 	case RF5350:
3575 	case RF5360:
3576 	case RF5362:
3577 	case RF5370:
3578 	case RF5372:
3579 	case RF5390:
3580 	case RF5392:
3581 		rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
3582 		break;
3583 	case RF5592:
3584 		rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3585 		break;
3586 	case RF7620:
3587 		rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
3588 		break;
3589 	default:
3590 		rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
3591 	}
3592 
3593 	if (rt2x00_rf(rt2x00dev, RF3070) ||
3594 	    rt2x00_rf(rt2x00dev, RF3290) ||
3595 	    rt2x00_rf(rt2x00dev, RF3322) ||
3596 	    rt2x00_rf(rt2x00dev, RF5350) ||
3597 	    rt2x00_rf(rt2x00dev, RF5360) ||
3598 	    rt2x00_rf(rt2x00dev, RF5362) ||
3599 	    rt2x00_rf(rt2x00dev, RF5370) ||
3600 	    rt2x00_rf(rt2x00dev, RF5372) ||
3601 	    rt2x00_rf(rt2x00dev, RF5390) ||
3602 	    rt2x00_rf(rt2x00dev, RF5392)) {
3603 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
3604 		if (rt2x00_rf(rt2x00dev, RF3322)) {
3605 			rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M,
3606 					  conf_is_ht40(conf));
3607 			rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M,
3608 					  conf_is_ht40(conf));
3609 		} else {
3610 			rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M,
3611 					  conf_is_ht40(conf));
3612 			rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M,
3613 					  conf_is_ht40(conf));
3614 		}
3615 		rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3616 
3617 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3618 		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3619 		rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3620 	}
3621 
3622 	/*
3623 	 * Change BBP settings
3624 	 */
3625 
3626 	if (rt2x00_rt(rt2x00dev, RT3352)) {
3627 		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3628 		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3629 		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3630 
3631 		rt2800_bbp_write(rt2x00dev, 27, 0x0);
3632 		rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3633 		rt2800_bbp_write(rt2x00dev, 27, 0x20);
3634 		rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3635 		rt2800_bbp_write(rt2x00dev, 86, 0x38);
3636 		rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3637 	} else if (rt2x00_rt(rt2x00dev, RT3593)) {
3638 		if (rf->channel > 14) {
3639 			/* Disable CCK Packet detection on 5GHz */
3640 			rt2800_bbp_write(rt2x00dev, 70, 0x00);
3641 		} else {
3642 			rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3643 		}
3644 
3645 		if (conf_is_ht40(conf))
3646 			rt2800_bbp_write(rt2x00dev, 105, 0x04);
3647 		else
3648 			rt2800_bbp_write(rt2x00dev, 105, 0x34);
3649 
3650 		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3651 		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3652 		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3653 		rt2800_bbp_write(rt2x00dev, 77, 0x98);
3654 	} else {
3655 		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3656 		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3657 		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3658 		rt2800_bbp_write(rt2x00dev, 86, 0);
3659 	}
3660 
3661 	if (rf->channel <= 14) {
3662 		if (!rt2x00_rt(rt2x00dev, RT5390) &&
3663 		    !rt2x00_rt(rt2x00dev, RT5392) &&
3664 		    !rt2x00_rt(rt2x00dev, RT6352)) {
3665 			if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
3666 				rt2800_bbp_write(rt2x00dev, 82, 0x62);
3667 				rt2800_bbp_write(rt2x00dev, 75, 0x46);
3668 			} else {
3669 				if (rt2x00_rt(rt2x00dev, RT3593))
3670 					rt2800_bbp_write(rt2x00dev, 82, 0x62);
3671 				else
3672 					rt2800_bbp_write(rt2x00dev, 82, 0x84);
3673 				rt2800_bbp_write(rt2x00dev, 75, 0x50);
3674 			}
3675 			if (rt2x00_rt(rt2x00dev, RT3593))
3676 				rt2800_bbp_write(rt2x00dev, 83, 0x8a);
3677 		}
3678 
3679 	} else {
3680 		if (rt2x00_rt(rt2x00dev, RT3572))
3681 			rt2800_bbp_write(rt2x00dev, 82, 0x94);
3682 		else if (rt2x00_rt(rt2x00dev, RT3593))
3683 			rt2800_bbp_write(rt2x00dev, 82, 0x82);
3684 		else if (!rt2x00_rt(rt2x00dev, RT6352))
3685 			rt2800_bbp_write(rt2x00dev, 82, 0xf2);
3686 
3687 		if (rt2x00_rt(rt2x00dev, RT3593))
3688 			rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3689 
3690 		if (rt2x00_has_cap_external_lna_a(rt2x00dev))
3691 			rt2800_bbp_write(rt2x00dev, 75, 0x46);
3692 		else
3693 			rt2800_bbp_write(rt2x00dev, 75, 0x50);
3694 	}
3695 
3696 	reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG);
3697 	rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
3698 	rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3699 	rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3700 	rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3701 
3702 	if (rt2x00_rt(rt2x00dev, RT3572))
3703 		rt2800_rfcsr_write(rt2x00dev, 8, 0);
3704 
3705 	if (rt2x00_rt(rt2x00dev, RT6352))
3706 		tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
3707 	else
3708 		tx_pin = 0;
3709 
3710 	switch (rt2x00dev->default_ant.tx_chain_num) {
3711 	case 3:
3712 		/* Turn on tertiary PAs */
3713 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3714 				   rf->channel > 14);
3715 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3716 				   rf->channel <= 14);
3717 		/* fall-through */
3718 	case 2:
3719 		/* Turn on secondary PAs */
3720 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3721 				   rf->channel > 14);
3722 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3723 				   rf->channel <= 14);
3724 		/* fall-through */
3725 	case 1:
3726 		/* Turn on primary PAs */
3727 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3728 				   rf->channel > 14);
3729 		if (rt2x00_has_cap_bt_coexist(rt2x00dev))
3730 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3731 		else
3732 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3733 					   rf->channel <= 14);
3734 		break;
3735 	}
3736 
3737 	switch (rt2x00dev->default_ant.rx_chain_num) {
3738 	case 3:
3739 		/* Turn on tertiary LNAs */
3740 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3741 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3742 		/* fall-through */
3743 	case 2:
3744 		/* Turn on secondary LNAs */
3745 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3746 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
3747 		/* fall-through */
3748 	case 1:
3749 		/* Turn on primary LNAs */
3750 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3751 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3752 		break;
3753 	}
3754 
3755 	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3756 	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
3757 	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); /* mt7620 */
3758 
3759 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3760 
3761 	if (rt2x00_rt(rt2x00dev, RT3572)) {
3762 		rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3763 
3764 		/* AGC init */
3765 		if (rf->channel <= 14)
3766 			reg = 0x1c + (2 * rt2x00dev->lna_gain);
3767 		else
3768 			reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3769 
3770 		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3771 	}
3772 
3773 	if (rt2x00_rt(rt2x00dev, RT3593)) {
3774 		reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
3775 
3776 		/* Band selection */
3777 		if (rt2x00_is_usb(rt2x00dev) ||
3778 		    rt2x00_is_pcie(rt2x00dev)) {
3779 			/* GPIO #8 controls all paths */
3780 			rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3781 			if (rf->channel <= 14)
3782 				rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3783 			else
3784 				rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
3785 		}
3786 
3787 		/* LNA PE control. */
3788 		if (rt2x00_is_usb(rt2x00dev)) {
3789 			/* GPIO #4 controls PE0 and PE1,
3790 			 * GPIO #7 controls PE2
3791 			 */
3792 			rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3793 			rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3794 
3795 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3796 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
3797 		} else if (rt2x00_is_pcie(rt2x00dev)) {
3798 			/* GPIO #4 controls PE0, PE1 and PE2 */
3799 			rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3800 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3801 		}
3802 
3803 		rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3804 
3805 		/* AGC init */
3806 		if (rf->channel <= 14)
3807 			reg = 0x1c + 2 * rt2x00dev->lna_gain;
3808 		else
3809 			reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3810 
3811 		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3812 
3813 		usleep_range(1000, 1500);
3814 	}
3815 
3816 	if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
3817 		reg = 0x10;
3818 		if (!conf_is_ht40(conf)) {
3819 			if (rt2x00_rt(rt2x00dev, RT6352) &&
3820 			    rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
3821 				reg |= 0x5;
3822 			} else {
3823 				reg |= 0xa;
3824 			}
3825 		}
3826 		rt2800_bbp_write(rt2x00dev, 195, 141);
3827 		rt2800_bbp_write(rt2x00dev, 196, reg);
3828 
3829 		/* AGC init */
3830 		if (rt2x00_rt(rt2x00dev, RT6352))
3831 			reg = 0x04;
3832 		else
3833 			reg = rf->channel <= 14 ? 0x1c : 0x24;
3834 
3835 		reg += 2 * rt2x00dev->lna_gain;
3836 		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3837 
3838 		rt2800_iq_calibrate(rt2x00dev, rf->channel);
3839 	}
3840 
3841 	bbp = rt2800_bbp_read(rt2x00dev, 4);
3842 	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3843 	rt2800_bbp_write(rt2x00dev, 4, bbp);
3844 
3845 	bbp = rt2800_bbp_read(rt2x00dev, 3);
3846 	rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
3847 	rt2800_bbp_write(rt2x00dev, 3, bbp);
3848 
3849 	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3850 		if (conf_is_ht40(conf)) {
3851 			rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3852 			rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3853 			rt2800_bbp_write(rt2x00dev, 73, 0x16);
3854 		} else {
3855 			rt2800_bbp_write(rt2x00dev, 69, 0x16);
3856 			rt2800_bbp_write(rt2x00dev, 70, 0x08);
3857 			rt2800_bbp_write(rt2x00dev, 73, 0x11);
3858 		}
3859 	}
3860 
3861 	usleep_range(1000, 1500);
3862 
3863 	/*
3864 	 * Clear channel statistic counters
3865 	 */
3866 	reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
3867 	reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
3868 	reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
3869 
3870 	/*
3871 	 * Clear update flag
3872 	 */
3873 	if (rt2x00_rt(rt2x00dev, RT3352) ||
3874 	    rt2x00_rt(rt2x00dev, RT5350)) {
3875 		bbp = rt2800_bbp_read(rt2x00dev, 49);
3876 		rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3877 		rt2800_bbp_write(rt2x00dev, 49, bbp);
3878 	}
3879 }
3880 
3881 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3882 {
3883 	u8 tssi_bounds[9];
3884 	u8 current_tssi;
3885 	u16 eeprom;
3886 	u8 step;
3887 	int i;
3888 
3889 	/*
3890 	 * First check if temperature compensation is supported.
3891 	 */
3892 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
3893 	if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3894 		return 0;
3895 
3896 	/*
3897 	 * Read TSSI boundaries for temperature compensation from
3898 	 * the EEPROM.
3899 	 *
3900 	 * Array idx               0    1    2    3    4    5    6    7    8
3901 	 * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
3902 	 * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3903 	 */
3904 	if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
3905 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1);
3906 		tssi_bounds[0] = rt2x00_get_field16(eeprom,
3907 					EEPROM_TSSI_BOUND_BG1_MINUS4);
3908 		tssi_bounds[1] = rt2x00_get_field16(eeprom,
3909 					EEPROM_TSSI_BOUND_BG1_MINUS3);
3910 
3911 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2);
3912 		tssi_bounds[2] = rt2x00_get_field16(eeprom,
3913 					EEPROM_TSSI_BOUND_BG2_MINUS2);
3914 		tssi_bounds[3] = rt2x00_get_field16(eeprom,
3915 					EEPROM_TSSI_BOUND_BG2_MINUS1);
3916 
3917 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3);
3918 		tssi_bounds[4] = rt2x00_get_field16(eeprom,
3919 					EEPROM_TSSI_BOUND_BG3_REF);
3920 		tssi_bounds[5] = rt2x00_get_field16(eeprom,
3921 					EEPROM_TSSI_BOUND_BG3_PLUS1);
3922 
3923 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4);
3924 		tssi_bounds[6] = rt2x00_get_field16(eeprom,
3925 					EEPROM_TSSI_BOUND_BG4_PLUS2);
3926 		tssi_bounds[7] = rt2x00_get_field16(eeprom,
3927 					EEPROM_TSSI_BOUND_BG4_PLUS3);
3928 
3929 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5);
3930 		tssi_bounds[8] = rt2x00_get_field16(eeprom,
3931 					EEPROM_TSSI_BOUND_BG5_PLUS4);
3932 
3933 		step = rt2x00_get_field16(eeprom,
3934 					  EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3935 	} else {
3936 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1);
3937 		tssi_bounds[0] = rt2x00_get_field16(eeprom,
3938 					EEPROM_TSSI_BOUND_A1_MINUS4);
3939 		tssi_bounds[1] = rt2x00_get_field16(eeprom,
3940 					EEPROM_TSSI_BOUND_A1_MINUS3);
3941 
3942 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2);
3943 		tssi_bounds[2] = rt2x00_get_field16(eeprom,
3944 					EEPROM_TSSI_BOUND_A2_MINUS2);
3945 		tssi_bounds[3] = rt2x00_get_field16(eeprom,
3946 					EEPROM_TSSI_BOUND_A2_MINUS1);
3947 
3948 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3);
3949 		tssi_bounds[4] = rt2x00_get_field16(eeprom,
3950 					EEPROM_TSSI_BOUND_A3_REF);
3951 		tssi_bounds[5] = rt2x00_get_field16(eeprom,
3952 					EEPROM_TSSI_BOUND_A3_PLUS1);
3953 
3954 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4);
3955 		tssi_bounds[6] = rt2x00_get_field16(eeprom,
3956 					EEPROM_TSSI_BOUND_A4_PLUS2);
3957 		tssi_bounds[7] = rt2x00_get_field16(eeprom,
3958 					EEPROM_TSSI_BOUND_A4_PLUS3);
3959 
3960 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5);
3961 		tssi_bounds[8] = rt2x00_get_field16(eeprom,
3962 					EEPROM_TSSI_BOUND_A5_PLUS4);
3963 
3964 		step = rt2x00_get_field16(eeprom,
3965 					  EEPROM_TSSI_BOUND_A5_AGC_STEP);
3966 	}
3967 
3968 	/*
3969 	 * Check if temperature compensation is supported.
3970 	 */
3971 	if (tssi_bounds[4] == 0xff || step == 0xff)
3972 		return 0;
3973 
3974 	/*
3975 	 * Read current TSSI (BBP 49).
3976 	 */
3977 	current_tssi = rt2800_bbp_read(rt2x00dev, 49);
3978 
3979 	/*
3980 	 * Compare TSSI value (BBP49) with the compensation boundaries
3981 	 * from the EEPROM and increase or decrease tx power.
3982 	 */
3983 	for (i = 0; i <= 3; i++) {
3984 		if (current_tssi > tssi_bounds[i])
3985 			break;
3986 	}
3987 
3988 	if (i == 4) {
3989 		for (i = 8; i >= 5; i--) {
3990 			if (current_tssi < tssi_bounds[i])
3991 				break;
3992 		}
3993 	}
3994 
3995 	return (i - 4) * step;
3996 }
3997 
3998 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3999 				      enum nl80211_band band)
4000 {
4001 	u16 eeprom;
4002 	u8 comp_en;
4003 	u8 comp_type;
4004 	int comp_value = 0;
4005 
4006 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA);
4007 
4008 	/*
4009 	 * HT40 compensation not required.
4010 	 */
4011 	if (eeprom == 0xffff ||
4012 	    !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4013 		return 0;
4014 
4015 	if (band == NL80211_BAND_2GHZ) {
4016 		comp_en = rt2x00_get_field16(eeprom,
4017 				 EEPROM_TXPOWER_DELTA_ENABLE_2G);
4018 		if (comp_en) {
4019 			comp_type = rt2x00_get_field16(eeprom,
4020 					   EEPROM_TXPOWER_DELTA_TYPE_2G);
4021 			comp_value = rt2x00_get_field16(eeprom,
4022 					    EEPROM_TXPOWER_DELTA_VALUE_2G);
4023 			if (!comp_type)
4024 				comp_value = -comp_value;
4025 		}
4026 	} else {
4027 		comp_en = rt2x00_get_field16(eeprom,
4028 				 EEPROM_TXPOWER_DELTA_ENABLE_5G);
4029 		if (comp_en) {
4030 			comp_type = rt2x00_get_field16(eeprom,
4031 					   EEPROM_TXPOWER_DELTA_TYPE_5G);
4032 			comp_value = rt2x00_get_field16(eeprom,
4033 					    EEPROM_TXPOWER_DELTA_VALUE_5G);
4034 			if (!comp_type)
4035 				comp_value = -comp_value;
4036 		}
4037 	}
4038 
4039 	return comp_value;
4040 }
4041 
4042 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
4043 					int power_level, int max_power)
4044 {
4045 	int delta;
4046 
4047 	if (rt2x00_has_cap_power_limit(rt2x00dev))
4048 		return 0;
4049 
4050 	/*
4051 	 * XXX: We don't know the maximum transmit power of our hardware since
4052 	 * the EEPROM doesn't expose it. We only know that we are calibrated
4053 	 * to 100% tx power.
4054 	 *
4055 	 * Hence, we assume the regulatory limit that cfg80211 calulated for
4056 	 * the current channel is our maximum and if we are requested to lower
4057 	 * the value we just reduce our tx power accordingly.
4058 	 */
4059 	delta = power_level - max_power;
4060 	return min(delta, 0);
4061 }
4062 
4063 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
4064 				   enum nl80211_band band, int power_level,
4065 				   u8 txpower, int delta)
4066 {
4067 	u16 eeprom;
4068 	u8 criterion;
4069 	u8 eirp_txpower;
4070 	u8 eirp_txpower_criterion;
4071 	u8 reg_limit;
4072 
4073 	if (rt2x00_rt(rt2x00dev, RT3593))
4074 		return min_t(u8, txpower, 0xc);
4075 
4076 	if (rt2x00_has_cap_power_limit(rt2x00dev)) {
4077 		/*
4078 		 * Check if eirp txpower exceed txpower_limit.
4079 		 * We use OFDM 6M as criterion and its eirp txpower
4080 		 * is stored at EEPROM_EIRP_MAX_TX_POWER.
4081 		 * .11b data rate need add additional 4dbm
4082 		 * when calculating eirp txpower.
4083 		 */
4084 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4085 						       EEPROM_TXPOWER_BYRATE,
4086 						       1);
4087 		criterion = rt2x00_get_field16(eeprom,
4088 					       EEPROM_TXPOWER_BYRATE_RATE0);
4089 
4090 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
4091 
4092 		if (band == NL80211_BAND_2GHZ)
4093 			eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4094 						 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
4095 		else
4096 			eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4097 						 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
4098 
4099 		eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
4100 			       (is_rate_b ? 4 : 0) + delta;
4101 
4102 		reg_limit = (eirp_txpower > power_level) ?
4103 					(eirp_txpower - power_level) : 0;
4104 	} else
4105 		reg_limit = 0;
4106 
4107 	txpower = max(0, txpower + delta - reg_limit);
4108 	return min_t(u8, txpower, 0xc);
4109 }
4110 
4111 
4112 enum {
4113 	TX_PWR_CFG_0_IDX,
4114 	TX_PWR_CFG_1_IDX,
4115 	TX_PWR_CFG_2_IDX,
4116 	TX_PWR_CFG_3_IDX,
4117 	TX_PWR_CFG_4_IDX,
4118 	TX_PWR_CFG_5_IDX,
4119 	TX_PWR_CFG_6_IDX,
4120 	TX_PWR_CFG_7_IDX,
4121 	TX_PWR_CFG_8_IDX,
4122 	TX_PWR_CFG_9_IDX,
4123 	TX_PWR_CFG_0_EXT_IDX,
4124 	TX_PWR_CFG_1_EXT_IDX,
4125 	TX_PWR_CFG_2_EXT_IDX,
4126 	TX_PWR_CFG_3_EXT_IDX,
4127 	TX_PWR_CFG_4_EXT_IDX,
4128 	TX_PWR_CFG_IDX_COUNT,
4129 };
4130 
4131 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
4132 					 struct ieee80211_channel *chan,
4133 					 int power_level)
4134 {
4135 	u8 txpower;
4136 	u16 eeprom;
4137 	u32 regs[TX_PWR_CFG_IDX_COUNT];
4138 	unsigned int offset;
4139 	enum nl80211_band band = chan->band;
4140 	int delta;
4141 	int i;
4142 
4143 	memset(regs, '\0', sizeof(regs));
4144 
4145 	/* TODO: adapt TX power reduction from the rt28xx code */
4146 
4147 	/* calculate temperature compensation delta */
4148 	delta = rt2800_get_gain_calibration_delta(rt2x00dev);
4149 
4150 	if (band == NL80211_BAND_5GHZ)
4151 		offset = 16;
4152 	else
4153 		offset = 0;
4154 
4155 	if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4156 		offset += 8;
4157 
4158 	/* read the next four txpower values */
4159 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4160 					       offset);
4161 
4162 	/* CCK 1MBS,2MBS */
4163 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4164 	txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4165 					    txpower, delta);
4166 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4167 			   TX_PWR_CFG_0_CCK1_CH0, txpower);
4168 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4169 			   TX_PWR_CFG_0_CCK1_CH1, txpower);
4170 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4171 			   TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
4172 
4173 	/* CCK 5.5MBS,11MBS */
4174 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4175 	txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4176 					    txpower, delta);
4177 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4178 			   TX_PWR_CFG_0_CCK5_CH0, txpower);
4179 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4180 			   TX_PWR_CFG_0_CCK5_CH1, txpower);
4181 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4182 			   TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
4183 
4184 	/* OFDM 6MBS,9MBS */
4185 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4186 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4187 					    txpower, delta);
4188 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4189 			   TX_PWR_CFG_0_OFDM6_CH0, txpower);
4190 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4191 			   TX_PWR_CFG_0_OFDM6_CH1, txpower);
4192 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4193 			   TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
4194 
4195 	/* OFDM 12MBS,18MBS */
4196 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4197 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4198 					    txpower, delta);
4199 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4200 			   TX_PWR_CFG_0_OFDM12_CH0, txpower);
4201 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4202 			   TX_PWR_CFG_0_OFDM12_CH1, txpower);
4203 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4204 			   TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
4205 
4206 	/* read the next four txpower values */
4207 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4208 					       offset + 1);
4209 
4210 	/* OFDM 24MBS,36MBS */
4211 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4212 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4213 					    txpower, delta);
4214 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4215 			   TX_PWR_CFG_1_OFDM24_CH0, txpower);
4216 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4217 			   TX_PWR_CFG_1_OFDM24_CH1, txpower);
4218 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4219 			   TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
4220 
4221 	/* OFDM 48MBS */
4222 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4223 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4224 					    txpower, delta);
4225 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4226 			   TX_PWR_CFG_1_OFDM48_CH0, txpower);
4227 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4228 			   TX_PWR_CFG_1_OFDM48_CH1, txpower);
4229 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4230 			   TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
4231 
4232 	/* OFDM 54MBS */
4233 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4234 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4235 					    txpower, delta);
4236 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4237 			   TX_PWR_CFG_7_OFDM54_CH0, txpower);
4238 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4239 			   TX_PWR_CFG_7_OFDM54_CH1, txpower);
4240 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4241 			   TX_PWR_CFG_7_OFDM54_CH2, txpower);
4242 
4243 	/* read the next four txpower values */
4244 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4245 					       offset + 2);
4246 
4247 	/* MCS 0,1 */
4248 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4249 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4250 					    txpower, delta);
4251 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4252 			   TX_PWR_CFG_1_MCS0_CH0, txpower);
4253 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4254 			   TX_PWR_CFG_1_MCS0_CH1, txpower);
4255 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4256 			   TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
4257 
4258 	/* MCS 2,3 */
4259 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4260 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4261 					    txpower, delta);
4262 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4263 			   TX_PWR_CFG_1_MCS2_CH0, txpower);
4264 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4265 			   TX_PWR_CFG_1_MCS2_CH1, txpower);
4266 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4267 			   TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
4268 
4269 	/* MCS 4,5 */
4270 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4271 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4272 					    txpower, delta);
4273 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4274 			   TX_PWR_CFG_2_MCS4_CH0, txpower);
4275 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4276 			   TX_PWR_CFG_2_MCS4_CH1, txpower);
4277 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4278 			   TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
4279 
4280 	/* MCS 6 */
4281 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4282 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4283 					    txpower, delta);
4284 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4285 			   TX_PWR_CFG_2_MCS6_CH0, txpower);
4286 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4287 			   TX_PWR_CFG_2_MCS6_CH1, txpower);
4288 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4289 			   TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
4290 
4291 	/* read the next four txpower values */
4292 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4293 					       offset + 3);
4294 
4295 	/* MCS 7 */
4296 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4297 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4298 					    txpower, delta);
4299 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4300 			   TX_PWR_CFG_7_MCS7_CH0, txpower);
4301 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4302 			   TX_PWR_CFG_7_MCS7_CH1, txpower);
4303 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4304 			   TX_PWR_CFG_7_MCS7_CH2, txpower);
4305 
4306 	/* MCS 8,9 */
4307 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4308 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4309 					    txpower, delta);
4310 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4311 			   TX_PWR_CFG_2_MCS8_CH0, txpower);
4312 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4313 			   TX_PWR_CFG_2_MCS8_CH1, txpower);
4314 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4315 			   TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
4316 
4317 	/* MCS 10,11 */
4318 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4319 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4320 					    txpower, delta);
4321 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4322 			   TX_PWR_CFG_2_MCS10_CH0, txpower);
4323 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4324 			   TX_PWR_CFG_2_MCS10_CH1, txpower);
4325 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4326 			   TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
4327 
4328 	/* MCS 12,13 */
4329 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4330 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4331 					    txpower, delta);
4332 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4333 			   TX_PWR_CFG_3_MCS12_CH0, txpower);
4334 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4335 			   TX_PWR_CFG_3_MCS12_CH1, txpower);
4336 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4337 			   TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
4338 
4339 	/* read the next four txpower values */
4340 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4341 					       offset + 4);
4342 
4343 	/* MCS 14 */
4344 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4345 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4346 					    txpower, delta);
4347 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4348 			   TX_PWR_CFG_3_MCS14_CH0, txpower);
4349 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4350 			   TX_PWR_CFG_3_MCS14_CH1, txpower);
4351 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4352 			   TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
4353 
4354 	/* MCS 15 */
4355 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4356 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4357 					    txpower, delta);
4358 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4359 			   TX_PWR_CFG_8_MCS15_CH0, txpower);
4360 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4361 			   TX_PWR_CFG_8_MCS15_CH1, txpower);
4362 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4363 			   TX_PWR_CFG_8_MCS15_CH2, txpower);
4364 
4365 	/* MCS 16,17 */
4366 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4367 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4368 					    txpower, delta);
4369 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4370 			   TX_PWR_CFG_5_MCS16_CH0, txpower);
4371 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4372 			   TX_PWR_CFG_5_MCS16_CH1, txpower);
4373 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4374 			   TX_PWR_CFG_5_MCS16_CH2, txpower);
4375 
4376 	/* MCS 18,19 */
4377 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4378 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4379 					    txpower, delta);
4380 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4381 			   TX_PWR_CFG_5_MCS18_CH0, txpower);
4382 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4383 			   TX_PWR_CFG_5_MCS18_CH1, txpower);
4384 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4385 			   TX_PWR_CFG_5_MCS18_CH2, txpower);
4386 
4387 	/* read the next four txpower values */
4388 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4389 					       offset + 5);
4390 
4391 	/* MCS 20,21 */
4392 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4393 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4394 					    txpower, delta);
4395 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4396 			   TX_PWR_CFG_6_MCS20_CH0, txpower);
4397 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4398 			   TX_PWR_CFG_6_MCS20_CH1, txpower);
4399 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4400 			   TX_PWR_CFG_6_MCS20_CH2, txpower);
4401 
4402 	/* MCS 22 */
4403 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4404 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4405 					    txpower, delta);
4406 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4407 			   TX_PWR_CFG_6_MCS22_CH0, txpower);
4408 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4409 			   TX_PWR_CFG_6_MCS22_CH1, txpower);
4410 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4411 			   TX_PWR_CFG_6_MCS22_CH2, txpower);
4412 
4413 	/* MCS 23 */
4414 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4415 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4416 					    txpower, delta);
4417 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4418 			   TX_PWR_CFG_8_MCS23_CH0, txpower);
4419 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4420 			   TX_PWR_CFG_8_MCS23_CH1, txpower);
4421 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4422 			   TX_PWR_CFG_8_MCS23_CH2, txpower);
4423 
4424 	/* read the next four txpower values */
4425 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4426 					       offset + 6);
4427 
4428 	/* STBC, MCS 0,1 */
4429 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4430 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4431 					    txpower, delta);
4432 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4433 			   TX_PWR_CFG_3_STBC0_CH0, txpower);
4434 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4435 			   TX_PWR_CFG_3_STBC0_CH1, txpower);
4436 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4437 			   TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
4438 
4439 	/* STBC, MCS 2,3 */
4440 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4441 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4442 					    txpower, delta);
4443 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4444 			   TX_PWR_CFG_3_STBC2_CH0, txpower);
4445 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4446 			   TX_PWR_CFG_3_STBC2_CH1, txpower);
4447 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4448 			   TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
4449 
4450 	/* STBC, MCS 4,5 */
4451 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4452 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4453 					    txpower, delta);
4454 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4455 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4456 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4457 			   txpower);
4458 
4459 	/* STBC, MCS 6 */
4460 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4461 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4462 					    txpower, delta);
4463 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4464 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4465 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4466 			   txpower);
4467 
4468 	/* read the next four txpower values */
4469 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4470 					       offset + 7);
4471 
4472 	/* STBC, MCS 7 */
4473 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4474 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4475 					    txpower, delta);
4476 	rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4477 			   TX_PWR_CFG_9_STBC7_CH0, txpower);
4478 	rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4479 			   TX_PWR_CFG_9_STBC7_CH1, txpower);
4480 	rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4481 			   TX_PWR_CFG_9_STBC7_CH2, txpower);
4482 
4483 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4484 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4485 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4486 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4487 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4488 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4489 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4490 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4491 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4492 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4493 
4494 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4495 			      regs[TX_PWR_CFG_0_EXT_IDX]);
4496 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4497 			      regs[TX_PWR_CFG_1_EXT_IDX]);
4498 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4499 			      regs[TX_PWR_CFG_2_EXT_IDX]);
4500 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4501 			      regs[TX_PWR_CFG_3_EXT_IDX]);
4502 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4503 			      regs[TX_PWR_CFG_4_EXT_IDX]);
4504 
4505 	for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4506 		rt2x00_dbg(rt2x00dev,
4507 			   "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4508 			   (band == NL80211_BAND_5GHZ) ? '5' : '2',
4509 			   (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4510 								'4' : '2',
4511 			   (i > TX_PWR_CFG_9_IDX) ?
4512 					(i - TX_PWR_CFG_9_IDX - 1) : i,
4513 			   (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4514 			   (unsigned long) regs[i]);
4515 }
4516 
4517 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
4518 					 struct ieee80211_channel *chan,
4519 					 int power_level)
4520 {
4521 	u32 reg, pwreg;
4522 	u16 eeprom;
4523 	u32 data, gdata;
4524 	u8 t, i;
4525 	enum nl80211_band band = chan->band;
4526 	int delta;
4527 
4528 	/* Warn user if bw_comp is set in EEPROM */
4529 	delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4530 
4531 	if (delta)
4532 		rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
4533 			    delta);
4534 
4535 	/* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
4536 	 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
4537 	 * driver does as well, though it looks kinda wrong.
4538 	 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
4539 	 * the hardware has a problem handling 0x20, and as the code initially
4540 	 * used a fixed offset between HT20 and HT40 rates they had to work-
4541 	 * around that issue and most likely just forgot about it later on.
4542 	 * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
4543 	 * however, the corresponding EEPROM value is not respected by the
4544 	 * vendor driver, so maybe this is rather being taken care of the
4545 	 * TXALC and the driver doesn't need to handle it...?
4546 	 * Though this is all very awkward, just do as they did, as that's what
4547 	 * board vendors expected when they populated the EEPROM...
4548 	 */
4549 	for (i = 0; i < 5; i++) {
4550 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4551 						       EEPROM_TXPOWER_BYRATE,
4552 						       i * 2);
4553 
4554 		data = eeprom;
4555 
4556 		t = eeprom & 0x3f;
4557 		if (t == 32)
4558 			t++;
4559 
4560 		gdata = t;
4561 
4562 		t = (eeprom & 0x3f00) >> 8;
4563 		if (t == 32)
4564 			t++;
4565 
4566 		gdata |= (t << 8);
4567 
4568 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4569 						       EEPROM_TXPOWER_BYRATE,
4570 						       (i * 2) + 1);
4571 
4572 		t = eeprom & 0x3f;
4573 		if (t == 32)
4574 			t++;
4575 
4576 		gdata |= (t << 16);
4577 
4578 		t = (eeprom & 0x3f00) >> 8;
4579 		if (t == 32)
4580 			t++;
4581 
4582 		gdata |= (t << 24);
4583 		data |= (eeprom << 16);
4584 
4585 		if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
4586 			/* HT20 */
4587 			if (data != 0xffffffff)
4588 				rt2800_register_write(rt2x00dev,
4589 						      TX_PWR_CFG_0 + (i * 4),
4590 						      data);
4591 		} else {
4592 			/* HT40 */
4593 			if (gdata != 0xffffffff)
4594 				rt2800_register_write(rt2x00dev,
4595 						      TX_PWR_CFG_0 + (i * 4),
4596 						      gdata);
4597 		}
4598 	}
4599 
4600 	/* Aparently Ralink ran out of space in the BYRATE calibration section
4601 	 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
4602 	 * registers. As recent 2T chips use 8-bit instead of 4-bit values for
4603 	 * power-offsets more space would be needed. Ralink decided to keep the
4604 	 * EEPROM layout untouched and rather have some shared values covering
4605 	 * multiple bitrates.
4606 	 * Populate the registers not covered by the EEPROM in the same way the
4607 	 * vendor driver does.
4608 	 */
4609 
4610 	/* For OFDM 54MBS use value from OFDM 48MBS */
4611 	pwreg = 0;
4612 	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1);
4613 	t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
4614 	rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
4615 
4616 	/* For MCS 7 use value from MCS 6 */
4617 	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2);
4618 	t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
4619 	rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
4620 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
4621 
4622 	/* For MCS 15 use value from MCS 14 */
4623 	pwreg = 0;
4624 	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3);
4625 	t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
4626 	rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
4627 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
4628 
4629 	/* For STBC MCS 7 use value from STBC MCS 6 */
4630 	pwreg = 0;
4631 	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4);
4632 	t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
4633 	rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
4634 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
4635 
4636 	rt2800_config_alc(rt2x00dev, chan, power_level);
4637 
4638 	/* TODO: temperature compensation code! */
4639 }
4640 
4641 /*
4642  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4643  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4644  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4645  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4646  * Reference per rate transmit power values are located in the EEPROM at
4647  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4648  * current conditions (i.e. band, bandwidth, temperature, user settings).
4649  */
4650 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4651 					 struct ieee80211_channel *chan,
4652 					 int power_level)
4653 {
4654 	u8 txpower, r1;
4655 	u16 eeprom;
4656 	u32 reg, offset;
4657 	int i, is_rate_b, delta, power_ctrl;
4658 	enum nl80211_band band = chan->band;
4659 
4660 	/*
4661 	 * Calculate HT40 compensation. For 40MHz we need to add or subtract
4662 	 * value read from EEPROM (different for 2GHz and for 5GHz).
4663 	 */
4664 	delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4665 
4666 	/*
4667 	 * Calculate temperature compensation. Depends on measurement of current
4668 	 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4669 	 * to temperature or maybe other factors) is smaller or bigger than
4670 	 * expected. We adjust it, based on TSSI reference and boundaries values
4671 	 * provided in EEPROM.
4672 	 */
4673 	switch (rt2x00dev->chip.rt) {
4674 	case RT2860:
4675 	case RT2872:
4676 	case RT2883:
4677 	case RT3070:
4678 	case RT3071:
4679 	case RT3090:
4680 	case RT3572:
4681 		delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4682 		break;
4683 	default:
4684 		/* TODO: temperature compensation code for other chips. */
4685 		break;
4686 	}
4687 
4688 	/*
4689 	 * Decrease power according to user settings, on devices with unknown
4690 	 * maximum tx power. For other devices we take user power_level into
4691 	 * consideration on rt2800_compensate_txpower().
4692 	 */
4693 	delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4694 					      chan->max_power);
4695 
4696 	/*
4697 	 * BBP_R1 controls TX power for all rates, it allow to set the following
4698 	 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4699 	 *
4700 	 * TODO: we do not use +6 dBm option to do not increase power beyond
4701 	 * regulatory limit, however this could be utilized for devices with
4702 	 * CAPABILITY_POWER_LIMIT.
4703 	 */
4704 	if (delta <= -12) {
4705 		power_ctrl = 2;
4706 		delta += 12;
4707 	} else if (delta <= -6) {
4708 		power_ctrl = 1;
4709 		delta += 6;
4710 	} else {
4711 		power_ctrl = 0;
4712 	}
4713 	r1 = rt2800_bbp_read(rt2x00dev, 1);
4714 	rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4715 	rt2800_bbp_write(rt2x00dev, 1, r1);
4716 
4717 	offset = TX_PWR_CFG_0;
4718 
4719 	for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4720 		/* just to be safe */
4721 		if (offset > TX_PWR_CFG_4)
4722 			break;
4723 
4724 		reg = rt2800_register_read(rt2x00dev, offset);
4725 
4726 		/* read the next four txpower values */
4727 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4728 						       EEPROM_TXPOWER_BYRATE,
4729 						       i);
4730 
4731 		is_rate_b = i ? 0 : 1;
4732 		/*
4733 		 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
4734 		 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
4735 		 * TX_PWR_CFG_4: unknown
4736 		 */
4737 		txpower = rt2x00_get_field16(eeprom,
4738 					     EEPROM_TXPOWER_BYRATE_RATE0);
4739 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4740 					     power_level, txpower, delta);
4741 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
4742 
4743 		/*
4744 		 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
4745 		 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
4746 		 * TX_PWR_CFG_4: unknown
4747 		 */
4748 		txpower = rt2x00_get_field16(eeprom,
4749 					     EEPROM_TXPOWER_BYRATE_RATE1);
4750 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4751 					     power_level, txpower, delta);
4752 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
4753 
4754 		/*
4755 		 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
4756 		 * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
4757 		 * TX_PWR_CFG_4: unknown
4758 		 */
4759 		txpower = rt2x00_get_field16(eeprom,
4760 					     EEPROM_TXPOWER_BYRATE_RATE2);
4761 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4762 					     power_level, txpower, delta);
4763 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
4764 
4765 		/*
4766 		 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
4767 		 * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
4768 		 * TX_PWR_CFG_4: unknown
4769 		 */
4770 		txpower = rt2x00_get_field16(eeprom,
4771 					     EEPROM_TXPOWER_BYRATE_RATE3);
4772 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4773 					     power_level, txpower, delta);
4774 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
4775 
4776 		/* read the next four txpower values */
4777 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4778 						       EEPROM_TXPOWER_BYRATE,
4779 						       i + 1);
4780 
4781 		is_rate_b = 0;
4782 		/*
4783 		 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
4784 		 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
4785 		 * TX_PWR_CFG_4: unknown
4786 		 */
4787 		txpower = rt2x00_get_field16(eeprom,
4788 					     EEPROM_TXPOWER_BYRATE_RATE0);
4789 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4790 					     power_level, txpower, delta);
4791 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
4792 
4793 		/*
4794 		 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
4795 		 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
4796 		 * TX_PWR_CFG_4: unknown
4797 		 */
4798 		txpower = rt2x00_get_field16(eeprom,
4799 					     EEPROM_TXPOWER_BYRATE_RATE1);
4800 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4801 					     power_level, txpower, delta);
4802 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
4803 
4804 		/*
4805 		 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
4806 		 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
4807 		 * TX_PWR_CFG_4: unknown
4808 		 */
4809 		txpower = rt2x00_get_field16(eeprom,
4810 					     EEPROM_TXPOWER_BYRATE_RATE2);
4811 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4812 					     power_level, txpower, delta);
4813 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
4814 
4815 		/*
4816 		 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
4817 		 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
4818 		 * TX_PWR_CFG_4: unknown
4819 		 */
4820 		txpower = rt2x00_get_field16(eeprom,
4821 					     EEPROM_TXPOWER_BYRATE_RATE3);
4822 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4823 					     power_level, txpower, delta);
4824 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
4825 
4826 		rt2800_register_write(rt2x00dev, offset, reg);
4827 
4828 		/* next TX_PWR_CFG register */
4829 		offset += 4;
4830 	}
4831 }
4832 
4833 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4834 				  struct ieee80211_channel *chan,
4835 				  int power_level)
4836 {
4837 	if (rt2x00_rt(rt2x00dev, RT3593))
4838 		rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4839 	else if (rt2x00_rt(rt2x00dev, RT6352))
4840 		rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
4841 	else
4842 		rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4843 }
4844 
4845 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4846 {
4847 	rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
4848 			      rt2x00dev->tx_power);
4849 }
4850 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4851 
4852 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4853 {
4854 	u32	tx_pin;
4855 	u8	rfcsr;
4856 	unsigned long min_sleep = 0;
4857 
4858 	/*
4859 	 * A voltage-controlled oscillator(VCO) is an electronic oscillator
4860 	 * designed to be controlled in oscillation frequency by a voltage
4861 	 * input. Maybe the temperature will affect the frequency of
4862 	 * oscillation to be shifted. The VCO calibration will be called
4863 	 * periodically to adjust the frequency to be precision.
4864 	*/
4865 
4866 	tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
4867 	tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4868 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4869 
4870 	switch (rt2x00dev->chip.rf) {
4871 	case RF2020:
4872 	case RF3020:
4873 	case RF3021:
4874 	case RF3022:
4875 	case RF3320:
4876 	case RF3052:
4877 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
4878 		rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4879 		rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4880 		break;
4881 	case RF3053:
4882 	case RF3070:
4883 	case RF3290:
4884 	case RF5350:
4885 	case RF5360:
4886 	case RF5362:
4887 	case RF5370:
4888 	case RF5372:
4889 	case RF5390:
4890 	case RF5392:
4891 	case RF5592:
4892 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
4893 		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4894 		rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4895 		min_sleep = 1000;
4896 		break;
4897 	case RF7620:
4898 		rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
4899 		rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
4900 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 4);
4901 		rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
4902 		rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
4903 		min_sleep = 2000;
4904 		break;
4905 	default:
4906 		WARN_ONCE(1, "Not supported RF chipet %x for VCO recalibration",
4907 			  rt2x00dev->chip.rf);
4908 		return;
4909 	}
4910 
4911 	if (min_sleep > 0)
4912 		usleep_range(min_sleep, min_sleep * 2);
4913 
4914 	tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
4915 	if (rt2x00dev->rf_channel <= 14) {
4916 		switch (rt2x00dev->default_ant.tx_chain_num) {
4917 		case 3:
4918 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4919 			/* fall through */
4920 		case 2:
4921 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4922 			/* fall through */
4923 		case 1:
4924 		default:
4925 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4926 			break;
4927 		}
4928 	} else {
4929 		switch (rt2x00dev->default_ant.tx_chain_num) {
4930 		case 3:
4931 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4932 			/* fall through */
4933 		case 2:
4934 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4935 			/* fall through */
4936 		case 1:
4937 		default:
4938 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4939 			break;
4940 		}
4941 	}
4942 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4943 
4944 	if (rt2x00_rt(rt2x00dev, RT6352)) {
4945 		if (rt2x00dev->default_ant.rx_chain_num == 1) {
4946 			rt2800_bbp_write(rt2x00dev, 91, 0x07);
4947 			rt2800_bbp_write(rt2x00dev, 95, 0x1A);
4948 			rt2800_bbp_write(rt2x00dev, 195, 128);
4949 			rt2800_bbp_write(rt2x00dev, 196, 0xA0);
4950 			rt2800_bbp_write(rt2x00dev, 195, 170);
4951 			rt2800_bbp_write(rt2x00dev, 196, 0x12);
4952 			rt2800_bbp_write(rt2x00dev, 195, 171);
4953 			rt2800_bbp_write(rt2x00dev, 196, 0x10);
4954 		} else {
4955 			rt2800_bbp_write(rt2x00dev, 91, 0x06);
4956 			rt2800_bbp_write(rt2x00dev, 95, 0x9A);
4957 			rt2800_bbp_write(rt2x00dev, 195, 128);
4958 			rt2800_bbp_write(rt2x00dev, 196, 0xE0);
4959 			rt2800_bbp_write(rt2x00dev, 195, 170);
4960 			rt2800_bbp_write(rt2x00dev, 196, 0x30);
4961 			rt2800_bbp_write(rt2x00dev, 195, 171);
4962 			rt2800_bbp_write(rt2x00dev, 196, 0x30);
4963 		}
4964 
4965 		if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4966 			rt2800_bbp_write(rt2x00dev, 75, 0x68);
4967 			rt2800_bbp_write(rt2x00dev, 76, 0x4C);
4968 			rt2800_bbp_write(rt2x00dev, 79, 0x1C);
4969 			rt2800_bbp_write(rt2x00dev, 80, 0x0C);
4970 			rt2800_bbp_write(rt2x00dev, 82, 0xB6);
4971 		}
4972 
4973 		/* On 11A, We should delay and wait RF/BBP to be stable
4974 		 * and the appropriate time should be 1000 micro seconds
4975 		 * 2005/06/05 - On 11G, we also need this delay time.
4976 		 * Otherwise it's difficult to pass the WHQL.
4977 		 */
4978 		usleep_range(1000, 1500);
4979 	}
4980 }
4981 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4982 
4983 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4984 				      struct rt2x00lib_conf *libconf)
4985 {
4986 	u32 reg;
4987 
4988 	reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
4989 	rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4990 			   libconf->conf->short_frame_max_tx_count);
4991 	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4992 			   libconf->conf->long_frame_max_tx_count);
4993 	rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4994 }
4995 
4996 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4997 			     struct rt2x00lib_conf *libconf)
4998 {
4999 	enum dev_state state =
5000 	    (libconf->conf->flags & IEEE80211_CONF_PS) ?
5001 		STATE_SLEEP : STATE_AWAKE;
5002 	u32 reg;
5003 
5004 	if (state == STATE_SLEEP) {
5005 		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
5006 
5007 		reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5008 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
5009 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
5010 				   libconf->conf->listen_interval - 1);
5011 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
5012 		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5013 
5014 		rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5015 	} else {
5016 		reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5017 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
5018 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
5019 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
5020 		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5021 
5022 		rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5023 	}
5024 }
5025 
5026 void rt2800_config(struct rt2x00_dev *rt2x00dev,
5027 		   struct rt2x00lib_conf *libconf,
5028 		   const unsigned int flags)
5029 {
5030 	/* Always recalculate LNA gain before changing configuration */
5031 	rt2800_config_lna_gain(rt2x00dev, libconf);
5032 
5033 	if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
5034 		rt2800_config_channel(rt2x00dev, libconf->conf,
5035 				      &libconf->rf, &libconf->channel);
5036 		rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5037 				      libconf->conf->power_level);
5038 	}
5039 	if (flags & IEEE80211_CONF_CHANGE_POWER)
5040 		rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5041 				      libconf->conf->power_level);
5042 	if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
5043 		rt2800_config_retry_limit(rt2x00dev, libconf);
5044 	if (flags & IEEE80211_CONF_CHANGE_PS)
5045 		rt2800_config_ps(rt2x00dev, libconf);
5046 }
5047 EXPORT_SYMBOL_GPL(rt2800_config);
5048 
5049 /*
5050  * Link tuning
5051  */
5052 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5053 {
5054 	u32 reg;
5055 
5056 	/*
5057 	 * Update FCS error count from register.
5058 	 */
5059 	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5060 	qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
5061 }
5062 EXPORT_SYMBOL_GPL(rt2800_link_stats);
5063 
5064 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
5065 {
5066 	u8 vgc;
5067 
5068 	if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
5069 		if (rt2x00_rt(rt2x00dev, RT3070) ||
5070 		    rt2x00_rt(rt2x00dev, RT3071) ||
5071 		    rt2x00_rt(rt2x00dev, RT3090) ||
5072 		    rt2x00_rt(rt2x00dev, RT3290) ||
5073 		    rt2x00_rt(rt2x00dev, RT3390) ||
5074 		    rt2x00_rt(rt2x00dev, RT3572) ||
5075 		    rt2x00_rt(rt2x00dev, RT3593) ||
5076 		    rt2x00_rt(rt2x00dev, RT5390) ||
5077 		    rt2x00_rt(rt2x00dev, RT5392) ||
5078 		    rt2x00_rt(rt2x00dev, RT5592) ||
5079 		    rt2x00_rt(rt2x00dev, RT6352))
5080 			vgc = 0x1c + (2 * rt2x00dev->lna_gain);
5081 		else
5082 			vgc = 0x2e + rt2x00dev->lna_gain;
5083 	} else { /* 5GHZ band */
5084 		if (rt2x00_rt(rt2x00dev, RT3593))
5085 			vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
5086 		else if (rt2x00_rt(rt2x00dev, RT5592))
5087 			vgc = 0x24 + (2 * rt2x00dev->lna_gain);
5088 		else {
5089 			if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5090 				vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5091 			else
5092 				vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5093 		}
5094 	}
5095 
5096 	return vgc;
5097 }
5098 
5099 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
5100 				  struct link_qual *qual, u8 vgc_level)
5101 {
5102 	if (qual->vgc_level != vgc_level) {
5103 		if (rt2x00_rt(rt2x00dev, RT3572) ||
5104 		    rt2x00_rt(rt2x00dev, RT3593)) {
5105 			rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
5106 						       vgc_level);
5107 		} else if (rt2x00_rt(rt2x00dev, RT5592)) {
5108 			rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
5109 			rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
5110 		} else {
5111 			rt2800_bbp_write(rt2x00dev, 66, vgc_level);
5112 		}
5113 
5114 		qual->vgc_level = vgc_level;
5115 		qual->vgc_level_reg = vgc_level;
5116 	}
5117 }
5118 
5119 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5120 {
5121 	rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
5122 }
5123 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
5124 
5125 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
5126 		       const u32 count)
5127 {
5128 	u8 vgc;
5129 
5130 	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
5131 		return;
5132 
5133 	/* When RSSI is better than a certain threshold, increase VGC
5134 	 * with a chip specific value in order to improve the balance
5135 	 * between sensibility and noise isolation.
5136 	 */
5137 
5138 	vgc = rt2800_get_default_vgc(rt2x00dev);
5139 
5140 	switch (rt2x00dev->chip.rt) {
5141 	case RT3572:
5142 	case RT3593:
5143 		if (qual->rssi > -65) {
5144 			if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
5145 				vgc += 0x20;
5146 			else
5147 				vgc += 0x10;
5148 		}
5149 		break;
5150 
5151 	case RT5592:
5152 		if (qual->rssi > -65)
5153 			vgc += 0x20;
5154 		break;
5155 
5156 	default:
5157 		if (qual->rssi > -80)
5158 			vgc += 0x10;
5159 		break;
5160 	}
5161 
5162 	rt2800_set_vgc(rt2x00dev, qual, vgc);
5163 }
5164 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
5165 
5166 /*
5167  * Initialization functions.
5168  */
5169 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
5170 {
5171 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5172 	u32 reg;
5173 	u16 eeprom;
5174 	unsigned int i;
5175 	int ret;
5176 
5177 	rt2800_disable_wpdma(rt2x00dev);
5178 
5179 	ret = rt2800_drv_init_registers(rt2x00dev);
5180 	if (ret)
5181 		return ret;
5182 
5183 	rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5184 	rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5185 
5186 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5187 
5188 	reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
5189 	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
5190 	rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
5191 	rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
5192 	rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
5193 	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
5194 	rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
5195 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5196 
5197 	rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
5198 
5199 	reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
5200 	rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
5201 	rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
5202 	rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5203 
5204 	if (rt2x00_rt(rt2x00dev, RT3290)) {
5205 		reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
5206 		if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
5207 			rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
5208 			rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
5209 		}
5210 
5211 		reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
5212 		if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
5213 			rt2x00_set_field32(&reg, LDO0_EN, 1);
5214 			rt2x00_set_field32(&reg, LDO_BGSEL, 3);
5215 			rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
5216 		}
5217 
5218 		reg = rt2800_register_read(rt2x00dev, OSC_CTRL);
5219 		rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
5220 		rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
5221 		rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
5222 		rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
5223 
5224 		reg = rt2800_register_read(rt2x00dev, COEX_CFG0);
5225 		rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
5226 		rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
5227 
5228 		reg = rt2800_register_read(rt2x00dev, COEX_CFG2);
5229 		rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
5230 		rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
5231 		rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
5232 		rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
5233 		rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
5234 
5235 		reg = rt2800_register_read(rt2x00dev, PLL_CTRL);
5236 		rt2x00_set_field32(&reg, PLL_CONTROL, 1);
5237 		rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
5238 	}
5239 
5240 	if (rt2x00_rt(rt2x00dev, RT3071) ||
5241 	    rt2x00_rt(rt2x00dev, RT3090) ||
5242 	    rt2x00_rt(rt2x00dev, RT3290) ||
5243 	    rt2x00_rt(rt2x00dev, RT3390)) {
5244 
5245 		if (rt2x00_rt(rt2x00dev, RT3290))
5246 			rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5247 					      0x00000404);
5248 		else
5249 			rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5250 					      0x00000400);
5251 
5252 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5253 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5254 		    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5255 		    rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5256 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5257 			if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
5258 				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5259 						      0x0000002c);
5260 			else
5261 				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5262 						      0x0000000f);
5263 		} else {
5264 			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5265 		}
5266 	} else if (rt2x00_rt(rt2x00dev, RT3070)) {
5267 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5268 
5269 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5270 			rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5271 			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
5272 		} else {
5273 			rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5274 			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5275 		}
5276 	} else if (rt2800_is_305x_soc(rt2x00dev)) {
5277 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5278 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5279 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
5280 	} else if (rt2x00_rt(rt2x00dev, RT3352)) {
5281 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5282 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5283 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5284 	} else if (rt2x00_rt(rt2x00dev, RT3572)) {
5285 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5286 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5287 	} else if (rt2x00_rt(rt2x00dev, RT3593)) {
5288 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5289 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5290 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
5291 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5292 			if (rt2x00_get_field16(eeprom,
5293 					       EEPROM_NIC_CONF1_DAC_TEST))
5294 				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5295 						      0x0000001f);
5296 			else
5297 				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5298 						      0x0000000f);
5299 		} else {
5300 			rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5301 					      0x00000000);
5302 		}
5303 	} else if (rt2x00_rt(rt2x00dev, RT5390) ||
5304 		   rt2x00_rt(rt2x00dev, RT5392) ||
5305 		   rt2x00_rt(rt2x00dev, RT6352)) {
5306 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5307 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5308 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5309 	} else if (rt2x00_rt(rt2x00dev, RT5592)) {
5310 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5311 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5312 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5313 	} else if (rt2x00_rt(rt2x00dev, RT5350)) {
5314 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5315 	} else if (rt2x00_rt(rt2x00dev, RT6352)) {
5316 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
5317 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
5318 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5319 		rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002);
5320 		rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F);
5321 		rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x06060606);
5322 		rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
5323 		rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
5324 		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
5325 		rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
5326 		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
5327 				      0x3630363A);
5328 		rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
5329 				      0x3630363A);
5330 		reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
5331 		rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
5332 		rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
5333 	} else {
5334 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
5335 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5336 	}
5337 
5338 	reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG);
5339 	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
5340 	rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
5341 	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
5342 	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
5343 	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
5344 	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
5345 	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
5346 	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
5347 	rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
5348 
5349 	reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG);
5350 	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
5351 	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
5352 	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
5353 	rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
5354 
5355 	reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
5356 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
5357 	if (rt2x00_is_usb(rt2x00dev)) {
5358 		drv_data->max_psdu = 3;
5359 	} else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
5360 		   rt2x00_rt(rt2x00dev, RT2883) ||
5361 		   rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
5362 		drv_data->max_psdu = 2;
5363 	} else {
5364 		drv_data->max_psdu = 1;
5365 	}
5366 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu);
5367 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 10);
5368 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 10);
5369 	rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
5370 
5371 	reg = rt2800_register_read(rt2x00dev, LED_CFG);
5372 	rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
5373 	rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
5374 	rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
5375 	rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
5376 	rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
5377 	rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
5378 	rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
5379 	rt2800_register_write(rt2x00dev, LED_CFG, reg);
5380 
5381 	rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
5382 
5383 	reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5384 	rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 2);
5385 	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 2);
5386 	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
5387 	rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
5388 	rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
5389 	rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
5390 	rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5391 
5392 	reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
5393 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
5394 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
5395 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 1);
5396 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
5397 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 0);
5398 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
5399 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
5400 	rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
5401 
5402 	reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
5403 	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
5404 	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
5405 	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
5406 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5407 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5408 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5409 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5410 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5411 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5412 	rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
5413 	rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5414 
5415 	reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
5416 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
5417 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
5418 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
5419 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5420 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5421 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5422 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5423 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5424 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5425 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
5426 	rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5427 
5428 	reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
5429 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
5430 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 1);
5431 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
5432 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5433 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5434 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5435 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5436 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5437 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5438 	rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
5439 	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5440 
5441 	reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
5442 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
5443 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 1);
5444 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
5445 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5446 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5447 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5448 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5449 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5450 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5451 	rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
5452 	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5453 
5454 	reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
5455 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
5456 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 1);
5457 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
5458 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5459 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5460 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5461 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5462 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5463 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5464 	rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
5465 	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
5466 
5467 	reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
5468 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
5469 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 1);
5470 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
5471 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5472 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5473 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5474 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5475 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5476 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5477 	rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
5478 	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
5479 
5480 	if (rt2x00_is_usb(rt2x00dev)) {
5481 		rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
5482 
5483 		reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
5484 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
5485 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
5486 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
5487 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
5488 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
5489 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
5490 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
5491 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
5492 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
5493 		rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5494 	}
5495 
5496 	/*
5497 	 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
5498 	 * although it is reserved.
5499 	 */
5500 	reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG);
5501 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
5502 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
5503 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
5504 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
5505 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
5506 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
5507 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
5508 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
5509 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
5510 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
5511 	rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
5512 
5513 	reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
5514 	rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
5515 
5516 	reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
5517 	rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7);
5518 	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
5519 			   IEEE80211_MAX_RTS_THRESHOLD);
5520 	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 1);
5521 	rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
5522 
5523 	rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
5524 
5525 	/*
5526 	 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
5527 	 * time should be set to 16. However, the original Ralink driver uses
5528 	 * 16 for both and indeed using a value of 10 for CCK SIFS results in
5529 	 * connection problems with 11g + CTS protection. Hence, use the same
5530 	 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
5531 	 */
5532 	reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
5533 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
5534 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
5535 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
5536 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
5537 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
5538 	rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
5539 
5540 	rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
5541 
5542 	/*
5543 	 * ASIC will keep garbage value after boot, clear encryption keys.
5544 	 */
5545 	for (i = 0; i < 4; i++)
5546 		rt2800_register_write(rt2x00dev,
5547 					 SHARED_KEY_MODE_ENTRY(i), 0);
5548 
5549 	for (i = 0; i < 256; i++) {
5550 		rt2800_config_wcid(rt2x00dev, NULL, i);
5551 		rt2800_delete_wcid_attr(rt2x00dev, i);
5552 		rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
5553 	}
5554 
5555 	/*
5556 	 * Clear all beacons
5557 	 */
5558 	for (i = 0; i < 8; i++)
5559 		rt2800_clear_beacon_register(rt2x00dev, i);
5560 
5561 	if (rt2x00_is_usb(rt2x00dev)) {
5562 		reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
5563 		rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
5564 		rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
5565 	} else if (rt2x00_is_pcie(rt2x00dev)) {
5566 		reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
5567 		rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
5568 		rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
5569 	}
5570 
5571 	reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
5572 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
5573 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
5574 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
5575 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
5576 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
5577 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
5578 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
5579 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
5580 	rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
5581 
5582 	reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1);
5583 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
5584 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
5585 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
5586 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
5587 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
5588 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
5589 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
5590 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
5591 	rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
5592 
5593 	reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0);
5594 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
5595 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
5596 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
5597 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
5598 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
5599 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
5600 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
5601 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
5602 	rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
5603 
5604 	reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1);
5605 	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
5606 	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
5607 	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
5608 	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
5609 	rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
5610 
5611 	/*
5612 	 * Do not force the BA window size, we use the TXWI to set it
5613 	 */
5614 	reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE);
5615 	rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
5616 	rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
5617 	rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
5618 
5619 	/*
5620 	 * We must clear the error counters.
5621 	 * These registers are cleared on read,
5622 	 * so we may pass a useless variable to store the value.
5623 	 */
5624 	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5625 	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1);
5626 	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2);
5627 	reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0);
5628 	reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1);
5629 	reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2);
5630 
5631 	/*
5632 	 * Setup leadtime for pre tbtt interrupt to 6ms
5633 	 */
5634 	reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG);
5635 	rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
5636 	rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
5637 
5638 	/*
5639 	 * Set up channel statistics timer
5640 	 */
5641 	reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG);
5642 	rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
5643 	rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
5644 	rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
5645 	rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
5646 	rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
5647 	rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
5648 
5649 	return 0;
5650 }
5651 
5652 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
5653 {
5654 	unsigned int i;
5655 	u32 reg;
5656 
5657 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5658 		reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
5659 		if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
5660 			return 0;
5661 
5662 		udelay(REGISTER_BUSY_DELAY);
5663 	}
5664 
5665 	rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
5666 	return -EACCES;
5667 }
5668 
5669 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
5670 {
5671 	unsigned int i;
5672 	u8 value;
5673 
5674 	/*
5675 	 * BBP was enabled after firmware was loaded,
5676 	 * but we need to reactivate it now.
5677 	 */
5678 	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5679 	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5680 	msleep(1);
5681 
5682 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5683 		value = rt2800_bbp_read(rt2x00dev, 0);
5684 		if ((value != 0xff) && (value != 0x00))
5685 			return 0;
5686 		udelay(REGISTER_BUSY_DELAY);
5687 	}
5688 
5689 	rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
5690 	return -EACCES;
5691 }
5692 
5693 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5694 {
5695 	u8 value;
5696 
5697 	value = rt2800_bbp_read(rt2x00dev, 4);
5698 	rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5699 	rt2800_bbp_write(rt2x00dev, 4, value);
5700 }
5701 
5702 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5703 {
5704 	rt2800_bbp_write(rt2x00dev, 142, 1);
5705 	rt2800_bbp_write(rt2x00dev, 143, 57);
5706 }
5707 
5708 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5709 {
5710 	static const u8 glrt_table[] = {
5711 		0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5712 		0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5713 		0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5714 		0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5715 		0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5716 		0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5717 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5718 		0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5719 		0x2E, 0x36, 0x30, 0x6E,					    /* 208 ~ 211 */
5720 	};
5721 	int i;
5722 
5723 	for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5724 		rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5725 		rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5726 	}
5727 };
5728 
5729 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
5730 {
5731 	rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5732 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
5733 	rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5734 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
5735 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5736 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
5737 	rt2800_bbp_write(rt2x00dev, 81, 0x37);
5738 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
5739 	rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5740 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
5741 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
5742 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
5743 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
5744 	rt2800_bbp_write(rt2x00dev, 103, 0x00);
5745 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
5746 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
5747 }
5748 
5749 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5750 {
5751 	u16 eeprom;
5752 	u8 value;
5753 
5754 	value = rt2800_bbp_read(rt2x00dev, 138);
5755 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
5756 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5757 		value |= 0x20;
5758 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5759 		value &= ~0x02;
5760 	rt2800_bbp_write(rt2x00dev, 138, value);
5761 }
5762 
5763 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5764 {
5765 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
5766 
5767 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5768 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
5769 
5770 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
5771 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
5772 
5773 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5774 
5775 	rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5776 	rt2800_bbp_write(rt2x00dev, 80, 0x08);
5777 
5778 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
5779 
5780 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5781 
5782 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
5783 
5784 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
5785 
5786 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
5787 
5788 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
5789 
5790 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5791 
5792 	rt2800_bbp_write(rt2x00dev, 105, 0x01);
5793 
5794 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
5795 }
5796 
5797 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5798 {
5799 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5800 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
5801 
5802 	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5803 		rt2800_bbp_write(rt2x00dev, 69, 0x16);
5804 		rt2800_bbp_write(rt2x00dev, 73, 0x12);
5805 	} else {
5806 		rt2800_bbp_write(rt2x00dev, 69, 0x12);
5807 		rt2800_bbp_write(rt2x00dev, 73, 0x10);
5808 	}
5809 
5810 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5811 
5812 	rt2800_bbp_write(rt2x00dev, 81, 0x37);
5813 
5814 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
5815 
5816 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5817 
5818 	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5819 		rt2800_bbp_write(rt2x00dev, 84, 0x19);
5820 	else
5821 		rt2800_bbp_write(rt2x00dev, 84, 0x99);
5822 
5823 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
5824 
5825 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
5826 
5827 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
5828 
5829 	rt2800_bbp_write(rt2x00dev, 103, 0x00);
5830 
5831 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
5832 
5833 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
5834 }
5835 
5836 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5837 {
5838 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5839 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
5840 
5841 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
5842 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
5843 
5844 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5845 
5846 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
5847 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
5848 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
5849 
5850 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
5851 
5852 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5853 
5854 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
5855 
5856 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
5857 
5858 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
5859 
5860 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
5861 
5862 	if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5863 	    rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5864 	    rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5865 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5866 	else
5867 		rt2800_bbp_write(rt2x00dev, 103, 0x00);
5868 
5869 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
5870 
5871 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
5872 
5873 	if (rt2x00_rt(rt2x00dev, RT3071) ||
5874 	    rt2x00_rt(rt2x00dev, RT3090))
5875 		rt2800_disable_unused_dac_adc(rt2x00dev);
5876 }
5877 
5878 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5879 {
5880 	u8 value;
5881 
5882 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5883 
5884 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
5885 
5886 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5887 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
5888 
5889 	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5890 
5891 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
5892 	rt2800_bbp_write(rt2x00dev, 73, 0x13);
5893 	rt2800_bbp_write(rt2x00dev, 75, 0x46);
5894 	rt2800_bbp_write(rt2x00dev, 76, 0x28);
5895 
5896 	rt2800_bbp_write(rt2x00dev, 77, 0x58);
5897 
5898 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5899 
5900 	rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5901 	rt2800_bbp_write(rt2x00dev, 79, 0x18);
5902 	rt2800_bbp_write(rt2x00dev, 80, 0x09);
5903 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
5904 
5905 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
5906 
5907 	rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5908 
5909 	rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5910 
5911 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
5912 
5913 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
5914 
5915 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
5916 
5917 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5918 
5919 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
5920 
5921 	rt2800_bbp_write(rt2x00dev, 105, 0x1c);
5922 
5923 	rt2800_bbp_write(rt2x00dev, 106, 0x03);
5924 
5925 	rt2800_bbp_write(rt2x00dev, 128, 0x12);
5926 
5927 	rt2800_bbp_write(rt2x00dev, 67, 0x24);
5928 	rt2800_bbp_write(rt2x00dev, 143, 0x04);
5929 	rt2800_bbp_write(rt2x00dev, 142, 0x99);
5930 	rt2800_bbp_write(rt2x00dev, 150, 0x30);
5931 	rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5932 	rt2800_bbp_write(rt2x00dev, 152, 0x20);
5933 	rt2800_bbp_write(rt2x00dev, 153, 0x34);
5934 	rt2800_bbp_write(rt2x00dev, 154, 0x40);
5935 	rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5936 	rt2800_bbp_write(rt2x00dev, 253, 0x04);
5937 
5938 	value = rt2800_bbp_read(rt2x00dev, 47);
5939 	rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5940 	rt2800_bbp_write(rt2x00dev, 47, value);
5941 
5942 	/* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5943 	value = rt2800_bbp_read(rt2x00dev, 3);
5944 	rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5945 	rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5946 	rt2800_bbp_write(rt2x00dev, 3, value);
5947 }
5948 
5949 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5950 {
5951 	rt2800_bbp_write(rt2x00dev, 3, 0x00);
5952 	rt2800_bbp_write(rt2x00dev, 4, 0x50);
5953 
5954 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
5955 
5956 	rt2800_bbp_write(rt2x00dev, 47, 0x48);
5957 
5958 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5959 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
5960 
5961 	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5962 
5963 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
5964 	rt2800_bbp_write(rt2x00dev, 73, 0x13);
5965 	rt2800_bbp_write(rt2x00dev, 75, 0x46);
5966 	rt2800_bbp_write(rt2x00dev, 76, 0x28);
5967 
5968 	rt2800_bbp_write(rt2x00dev, 77, 0x59);
5969 
5970 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5971 
5972 	rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5973 	rt2800_bbp_write(rt2x00dev, 80, 0x08);
5974 	rt2800_bbp_write(rt2x00dev, 81, 0x37);
5975 
5976 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
5977 
5978 	if (rt2x00_rt(rt2x00dev, RT5350)) {
5979 		rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5980 		rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5981 	} else {
5982 		rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5983 		rt2800_bbp_write(rt2x00dev, 84, 0x99);
5984 	}
5985 
5986 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
5987 
5988 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
5989 
5990 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
5991 
5992 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
5993 
5994 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5995 
5996 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
5997 
5998 	if (rt2x00_rt(rt2x00dev, RT5350)) {
5999 		rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6000 		rt2800_bbp_write(rt2x00dev, 106, 0x03);
6001 	} else {
6002 		rt2800_bbp_write(rt2x00dev, 105, 0x34);
6003 		rt2800_bbp_write(rt2x00dev, 106, 0x05);
6004 	}
6005 
6006 	rt2800_bbp_write(rt2x00dev, 120, 0x50);
6007 
6008 	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6009 
6010 	rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6011 	/* Set ITxBF timeout to 0x9c40=1000msec */
6012 	rt2800_bbp_write(rt2x00dev, 179, 0x02);
6013 	rt2800_bbp_write(rt2x00dev, 180, 0x00);
6014 	rt2800_bbp_write(rt2x00dev, 182, 0x40);
6015 	rt2800_bbp_write(rt2x00dev, 180, 0x01);
6016 	rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6017 	rt2800_bbp_write(rt2x00dev, 179, 0x00);
6018 	/* Reprogram the inband interface to put right values in RXWI */
6019 	rt2800_bbp_write(rt2x00dev, 142, 0x04);
6020 	rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6021 	rt2800_bbp_write(rt2x00dev, 142, 0x06);
6022 	rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6023 	rt2800_bbp_write(rt2x00dev, 142, 0x07);
6024 	rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6025 	rt2800_bbp_write(rt2x00dev, 142, 0x08);
6026 	rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6027 
6028 	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6029 
6030 	if (rt2x00_rt(rt2x00dev, RT5350)) {
6031 		/* Antenna Software OFDM */
6032 		rt2800_bbp_write(rt2x00dev, 150, 0x40);
6033 		/* Antenna Software CCK */
6034 		rt2800_bbp_write(rt2x00dev, 151, 0x30);
6035 		rt2800_bbp_write(rt2x00dev, 152, 0xa3);
6036 		/* Clear previously selected antenna */
6037 		rt2800_bbp_write(rt2x00dev, 154, 0);
6038 	}
6039 }
6040 
6041 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
6042 {
6043 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6044 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6045 
6046 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6047 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
6048 
6049 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6050 
6051 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6052 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6053 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6054 
6055 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6056 
6057 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6058 
6059 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
6060 
6061 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6062 
6063 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6064 
6065 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6066 
6067 	if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
6068 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6069 	else
6070 		rt2800_bbp_write(rt2x00dev, 103, 0x00);
6071 
6072 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
6073 
6074 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6075 
6076 	rt2800_disable_unused_dac_adc(rt2x00dev);
6077 }
6078 
6079 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
6080 {
6081 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6082 
6083 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6084 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6085 
6086 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6087 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
6088 
6089 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6090 
6091 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6092 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6093 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6094 
6095 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6096 
6097 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6098 
6099 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
6100 
6101 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6102 
6103 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6104 
6105 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6106 
6107 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6108 
6109 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
6110 
6111 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6112 
6113 	rt2800_disable_unused_dac_adc(rt2x00dev);
6114 }
6115 
6116 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
6117 {
6118 	rt2800_init_bbp_early(rt2x00dev);
6119 
6120 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6121 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6122 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6123 	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6124 
6125 	rt2800_bbp_write(rt2x00dev, 84, 0x19);
6126 
6127 	/* Enable DC filter */
6128 	if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
6129 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6130 }
6131 
6132 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
6133 {
6134 	int ant, div_mode;
6135 	u16 eeprom;
6136 	u8 value;
6137 
6138 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6139 
6140 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6141 
6142 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6143 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6144 
6145 	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6146 
6147 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6148 	rt2800_bbp_write(rt2x00dev, 73, 0x13);
6149 	rt2800_bbp_write(rt2x00dev, 75, 0x46);
6150 	rt2800_bbp_write(rt2x00dev, 76, 0x28);
6151 
6152 	rt2800_bbp_write(rt2x00dev, 77, 0x59);
6153 
6154 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6155 
6156 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6157 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6158 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6159 
6160 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6161 
6162 	rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6163 
6164 	rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6165 
6166 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
6167 
6168 	if (rt2x00_rt(rt2x00dev, RT5392))
6169 		rt2800_bbp_write(rt2x00dev, 88, 0x90);
6170 
6171 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6172 
6173 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6174 
6175 	if (rt2x00_rt(rt2x00dev, RT5392)) {
6176 		rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6177 		rt2800_bbp_write(rt2x00dev, 98, 0x12);
6178 	}
6179 
6180 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6181 
6182 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
6183 
6184 	rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6185 
6186 	if (rt2x00_rt(rt2x00dev, RT5390))
6187 		rt2800_bbp_write(rt2x00dev, 106, 0x03);
6188 	else if (rt2x00_rt(rt2x00dev, RT5392))
6189 		rt2800_bbp_write(rt2x00dev, 106, 0x12);
6190 	else
6191 		WARN_ON(1);
6192 
6193 	rt2800_bbp_write(rt2x00dev, 128, 0x12);
6194 
6195 	if (rt2x00_rt(rt2x00dev, RT5392)) {
6196 		rt2800_bbp_write(rt2x00dev, 134, 0xd0);
6197 		rt2800_bbp_write(rt2x00dev, 135, 0xf6);
6198 	}
6199 
6200 	rt2800_disable_unused_dac_adc(rt2x00dev);
6201 
6202 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6203 	div_mode = rt2x00_get_field16(eeprom,
6204 				      EEPROM_NIC_CONF1_ANT_DIVERSITY);
6205 	ant = (div_mode == 3) ? 1 : 0;
6206 
6207 	/* check if this is a Bluetooth combo card */
6208 	if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
6209 		u32 reg;
6210 
6211 		reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
6212 		rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
6213 		rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
6214 		rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
6215 		rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
6216 		if (ant == 0)
6217 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
6218 		else if (ant == 1)
6219 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
6220 		rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6221 	}
6222 
6223 	/* This chip has hardware antenna diversity*/
6224 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
6225 		rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
6226 		rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
6227 		rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
6228 	}
6229 
6230 	value = rt2800_bbp_read(rt2x00dev, 152);
6231 	if (ant == 0)
6232 		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6233 	else
6234 		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6235 	rt2800_bbp_write(rt2x00dev, 152, value);
6236 
6237 	rt2800_init_freq_calibration(rt2x00dev);
6238 }
6239 
6240 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
6241 {
6242 	int ant, div_mode;
6243 	u16 eeprom;
6244 	u8 value;
6245 
6246 	rt2800_init_bbp_early(rt2x00dev);
6247 
6248 	value = rt2800_bbp_read(rt2x00dev, 105);
6249 	rt2x00_set_field8(&value, BBP105_MLD,
6250 			  rt2x00dev->default_ant.rx_chain_num == 2);
6251 	rt2800_bbp_write(rt2x00dev, 105, value);
6252 
6253 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6254 
6255 	rt2800_bbp_write(rt2x00dev, 20, 0x06);
6256 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6257 	rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6258 	rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6259 	rt2800_bbp_write(rt2x00dev, 69, 0x1A);
6260 	rt2800_bbp_write(rt2x00dev, 70, 0x05);
6261 	rt2800_bbp_write(rt2x00dev, 73, 0x13);
6262 	rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6263 	rt2800_bbp_write(rt2x00dev, 75, 0x4F);
6264 	rt2800_bbp_write(rt2x00dev, 76, 0x28);
6265 	rt2800_bbp_write(rt2x00dev, 77, 0x59);
6266 	rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6267 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
6268 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
6269 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6270 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6271 	rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6272 	rt2800_bbp_write(rt2x00dev, 98, 0x12);
6273 	rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6274 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
6275 	/* FIXME BBP105 owerwrite */
6276 	rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6277 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6278 	rt2800_bbp_write(rt2x00dev, 128, 0x12);
6279 	rt2800_bbp_write(rt2x00dev, 134, 0xD0);
6280 	rt2800_bbp_write(rt2x00dev, 135, 0xF6);
6281 	rt2800_bbp_write(rt2x00dev, 137, 0x0F);
6282 
6283 	/* Initialize GLRT (Generalized Likehood Radio Test) */
6284 	rt2800_init_bbp_5592_glrt(rt2x00dev);
6285 
6286 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6287 
6288 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6289 	div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
6290 	ant = (div_mode == 3) ? 1 : 0;
6291 	value = rt2800_bbp_read(rt2x00dev, 152);
6292 	if (ant == 0) {
6293 		/* Main antenna */
6294 		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6295 	} else {
6296 		/* Auxiliary antenna */
6297 		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6298 	}
6299 	rt2800_bbp_write(rt2x00dev, 152, value);
6300 
6301 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
6302 		value = rt2800_bbp_read(rt2x00dev, 254);
6303 		rt2x00_set_field8(&value, BBP254_BIT7, 1);
6304 		rt2800_bbp_write(rt2x00dev, 254, value);
6305 	}
6306 
6307 	rt2800_init_freq_calibration(rt2x00dev);
6308 
6309 	rt2800_bbp_write(rt2x00dev, 84, 0x19);
6310 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6311 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6312 }
6313 
6314 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
6315 				  const u8 reg, const u8 value)
6316 {
6317 	rt2800_bbp_write(rt2x00dev, 195, reg);
6318 	rt2800_bbp_write(rt2x00dev, 196, value);
6319 }
6320 
6321 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
6322 				  const u8 reg, const u8 value)
6323 {
6324 	rt2800_bbp_write(rt2x00dev, 158, reg);
6325 	rt2800_bbp_write(rt2x00dev, 159, value);
6326 }
6327 
6328 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg)
6329 {
6330 	rt2800_bbp_write(rt2x00dev, 158, reg);
6331 	return rt2800_bbp_read(rt2x00dev, 159);
6332 }
6333 
6334 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
6335 {
6336 	u8 bbp;
6337 
6338 	/* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
6339 	bbp = rt2800_bbp_read(rt2x00dev, 105);
6340 	rt2x00_set_field8(&bbp, BBP105_MLD,
6341 			  rt2x00dev->default_ant.rx_chain_num == 2);
6342 	rt2800_bbp_write(rt2x00dev, 105, bbp);
6343 
6344 	/* Avoid data loss and CRC errors */
6345 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6346 
6347 	/* Fix I/Q swap issue */
6348 	bbp = rt2800_bbp_read(rt2x00dev, 1);
6349 	bbp |= 0x04;
6350 	rt2800_bbp_write(rt2x00dev, 1, bbp);
6351 
6352 	/* BBP for G band */
6353 	rt2800_bbp_write(rt2x00dev, 3, 0x08);
6354 	rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
6355 	rt2800_bbp_write(rt2x00dev, 6, 0x08);
6356 	rt2800_bbp_write(rt2x00dev, 14, 0x09);
6357 	rt2800_bbp_write(rt2x00dev, 15, 0xFF);
6358 	rt2800_bbp_write(rt2x00dev, 16, 0x01);
6359 	rt2800_bbp_write(rt2x00dev, 20, 0x06);
6360 	rt2800_bbp_write(rt2x00dev, 21, 0x00);
6361 	rt2800_bbp_write(rt2x00dev, 22, 0x00);
6362 	rt2800_bbp_write(rt2x00dev, 27, 0x00);
6363 	rt2800_bbp_write(rt2x00dev, 28, 0x00);
6364 	rt2800_bbp_write(rt2x00dev, 30, 0x00);
6365 	rt2800_bbp_write(rt2x00dev, 31, 0x48);
6366 	rt2800_bbp_write(rt2x00dev, 47, 0x40);
6367 	rt2800_bbp_write(rt2x00dev, 62, 0x00);
6368 	rt2800_bbp_write(rt2x00dev, 63, 0x00);
6369 	rt2800_bbp_write(rt2x00dev, 64, 0x00);
6370 	rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6371 	rt2800_bbp_write(rt2x00dev, 66, 0x1C);
6372 	rt2800_bbp_write(rt2x00dev, 67, 0x20);
6373 	rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6374 	rt2800_bbp_write(rt2x00dev, 69, 0x10);
6375 	rt2800_bbp_write(rt2x00dev, 70, 0x05);
6376 	rt2800_bbp_write(rt2x00dev, 73, 0x18);
6377 	rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6378 	rt2800_bbp_write(rt2x00dev, 75, 0x60);
6379 	rt2800_bbp_write(rt2x00dev, 76, 0x44);
6380 	rt2800_bbp_write(rt2x00dev, 77, 0x59);
6381 	rt2800_bbp_write(rt2x00dev, 78, 0x1E);
6382 	rt2800_bbp_write(rt2x00dev, 79, 0x1C);
6383 	rt2800_bbp_write(rt2x00dev, 80, 0x0C);
6384 	rt2800_bbp_write(rt2x00dev, 81, 0x3A);
6385 	rt2800_bbp_write(rt2x00dev, 82, 0xB6);
6386 	rt2800_bbp_write(rt2x00dev, 83, 0x9A);
6387 	rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6388 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
6389 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
6390 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6391 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6392 	rt2800_bbp_write(rt2x00dev, 95, 0x9A);
6393 	rt2800_bbp_write(rt2x00dev, 96, 0x00);
6394 	rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6395 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
6396 	/* FIXME BBP105 owerwrite */
6397 	rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6398 	rt2800_bbp_write(rt2x00dev, 106, 0x12);
6399 	rt2800_bbp_write(rt2x00dev, 109, 0x00);
6400 	rt2800_bbp_write(rt2x00dev, 134, 0x10);
6401 	rt2800_bbp_write(rt2x00dev, 135, 0xA6);
6402 	rt2800_bbp_write(rt2x00dev, 137, 0x04);
6403 	rt2800_bbp_write(rt2x00dev, 142, 0x30);
6404 	rt2800_bbp_write(rt2x00dev, 143, 0xF7);
6405 	rt2800_bbp_write(rt2x00dev, 160, 0xEC);
6406 	rt2800_bbp_write(rt2x00dev, 161, 0xC4);
6407 	rt2800_bbp_write(rt2x00dev, 162, 0x77);
6408 	rt2800_bbp_write(rt2x00dev, 163, 0xF9);
6409 	rt2800_bbp_write(rt2x00dev, 164, 0x00);
6410 	rt2800_bbp_write(rt2x00dev, 165, 0x00);
6411 	rt2800_bbp_write(rt2x00dev, 186, 0x00);
6412 	rt2800_bbp_write(rt2x00dev, 187, 0x00);
6413 	rt2800_bbp_write(rt2x00dev, 188, 0x00);
6414 	rt2800_bbp_write(rt2x00dev, 186, 0x00);
6415 	rt2800_bbp_write(rt2x00dev, 187, 0x01);
6416 	rt2800_bbp_write(rt2x00dev, 188, 0x00);
6417 	rt2800_bbp_write(rt2x00dev, 189, 0x00);
6418 
6419 	rt2800_bbp_write(rt2x00dev, 91, 0x06);
6420 	rt2800_bbp_write(rt2x00dev, 92, 0x04);
6421 	rt2800_bbp_write(rt2x00dev, 93, 0x54);
6422 	rt2800_bbp_write(rt2x00dev, 99, 0x50);
6423 	rt2800_bbp_write(rt2x00dev, 148, 0x84);
6424 	rt2800_bbp_write(rt2x00dev, 167, 0x80);
6425 	rt2800_bbp_write(rt2x00dev, 178, 0xFF);
6426 	rt2800_bbp_write(rt2x00dev, 106, 0x13);
6427 
6428 	/* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
6429 	rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
6430 	rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
6431 	rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
6432 	rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
6433 	rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
6434 	rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
6435 	rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
6436 	rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
6437 	rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
6438 	rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
6439 	rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
6440 	rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
6441 	rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
6442 	rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
6443 	rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
6444 	rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
6445 	rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
6446 	rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
6447 	rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
6448 	rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
6449 	rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
6450 	rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
6451 	rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
6452 	rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
6453 	rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
6454 	rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
6455 	rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
6456 	rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
6457 	rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
6458 	rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
6459 	rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
6460 	rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
6461 	rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
6462 	rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
6463 	rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
6464 	rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
6465 	rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
6466 	rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
6467 	rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
6468 	rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
6469 	rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
6470 	rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
6471 	rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
6472 	rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
6473 	rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
6474 	rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
6475 	rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
6476 	rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
6477 	rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
6478 	rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
6479 	rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
6480 	rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
6481 	rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
6482 	rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
6483 	rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
6484 	rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
6485 	rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
6486 	rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
6487 	rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
6488 	rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
6489 	rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
6490 	rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
6491 	rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
6492 	rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
6493 	rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
6494 	rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
6495 	rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
6496 	rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
6497 	rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
6498 	rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
6499 	rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
6500 	rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
6501 	rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
6502 	rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
6503 	rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
6504 	rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
6505 	rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
6506 	rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
6507 	rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
6508 	rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
6509 	rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
6510 	rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
6511 	rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
6512 
6513 	/* BBP for G band DCOC function */
6514 	rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
6515 	rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
6516 	rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
6517 	rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
6518 	rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
6519 	rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
6520 	rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
6521 	rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
6522 	rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
6523 	rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
6524 	rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
6525 	rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
6526 	rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
6527 	rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
6528 	rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
6529 	rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
6530 	rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
6531 	rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
6532 	rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
6533 	rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
6534 
6535 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6536 }
6537 
6538 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
6539 {
6540 	unsigned int i;
6541 	u16 eeprom;
6542 	u8 reg_id;
6543 	u8 value;
6544 
6545 	if (rt2800_is_305x_soc(rt2x00dev))
6546 		rt2800_init_bbp_305x_soc(rt2x00dev);
6547 
6548 	switch (rt2x00dev->chip.rt) {
6549 	case RT2860:
6550 	case RT2872:
6551 	case RT2883:
6552 		rt2800_init_bbp_28xx(rt2x00dev);
6553 		break;
6554 	case RT3070:
6555 	case RT3071:
6556 	case RT3090:
6557 		rt2800_init_bbp_30xx(rt2x00dev);
6558 		break;
6559 	case RT3290:
6560 		rt2800_init_bbp_3290(rt2x00dev);
6561 		break;
6562 	case RT3352:
6563 	case RT5350:
6564 		rt2800_init_bbp_3352(rt2x00dev);
6565 		break;
6566 	case RT3390:
6567 		rt2800_init_bbp_3390(rt2x00dev);
6568 		break;
6569 	case RT3572:
6570 		rt2800_init_bbp_3572(rt2x00dev);
6571 		break;
6572 	case RT3593:
6573 		rt2800_init_bbp_3593(rt2x00dev);
6574 		return;
6575 	case RT5390:
6576 	case RT5392:
6577 		rt2800_init_bbp_53xx(rt2x00dev);
6578 		break;
6579 	case RT5592:
6580 		rt2800_init_bbp_5592(rt2x00dev);
6581 		return;
6582 	case RT6352:
6583 		rt2800_init_bbp_6352(rt2x00dev);
6584 		break;
6585 	}
6586 
6587 	for (i = 0; i < EEPROM_BBP_SIZE; i++) {
6588 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
6589 						       EEPROM_BBP_START, i);
6590 
6591 		if (eeprom != 0xffff && eeprom != 0x0000) {
6592 			reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
6593 			value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
6594 			rt2800_bbp_write(rt2x00dev, reg_id, value);
6595 		}
6596 	}
6597 }
6598 
6599 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
6600 {
6601 	u32 reg;
6602 
6603 	reg = rt2800_register_read(rt2x00dev, OPT_14_CSR);
6604 	rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
6605 	rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
6606 }
6607 
6608 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
6609 				u8 filter_target)
6610 {
6611 	unsigned int i;
6612 	u8 bbp;
6613 	u8 rfcsr;
6614 	u8 passband;
6615 	u8 stopband;
6616 	u8 overtuned = 0;
6617 	u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
6618 
6619 	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6620 
6621 	bbp = rt2800_bbp_read(rt2x00dev, 4);
6622 	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
6623 	rt2800_bbp_write(rt2x00dev, 4, bbp);
6624 
6625 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
6626 	rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
6627 	rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
6628 
6629 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
6630 	rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
6631 	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
6632 
6633 	/*
6634 	 * Set power & frequency of passband test tone
6635 	 */
6636 	rt2800_bbp_write(rt2x00dev, 24, 0);
6637 
6638 	for (i = 0; i < 100; i++) {
6639 		rt2800_bbp_write(rt2x00dev, 25, 0x90);
6640 		msleep(1);
6641 
6642 		passband = rt2800_bbp_read(rt2x00dev, 55);
6643 		if (passband)
6644 			break;
6645 	}
6646 
6647 	/*
6648 	 * Set power & frequency of stopband test tone
6649 	 */
6650 	rt2800_bbp_write(rt2x00dev, 24, 0x06);
6651 
6652 	for (i = 0; i < 100; i++) {
6653 		rt2800_bbp_write(rt2x00dev, 25, 0x90);
6654 		msleep(1);
6655 
6656 		stopband = rt2800_bbp_read(rt2x00dev, 55);
6657 
6658 		if ((passband - stopband) <= filter_target) {
6659 			rfcsr24++;
6660 			overtuned += ((passband - stopband) == filter_target);
6661 		} else
6662 			break;
6663 
6664 		rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6665 	}
6666 
6667 	rfcsr24 -= !!overtuned;
6668 
6669 	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6670 	return rfcsr24;
6671 }
6672 
6673 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
6674 				       const unsigned int rf_reg)
6675 {
6676 	u8 rfcsr;
6677 
6678 	rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg);
6679 	rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
6680 	rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
6681 	msleep(1);
6682 	rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
6683 	rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
6684 }
6685 
6686 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
6687 {
6688 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6689 	u8 filter_tgt_bw20;
6690 	u8 filter_tgt_bw40;
6691 	u8 rfcsr, bbp;
6692 
6693 	/*
6694 	 * TODO: sync filter_tgt values with vendor driver
6695 	 */
6696 	if (rt2x00_rt(rt2x00dev, RT3070)) {
6697 		filter_tgt_bw20 = 0x16;
6698 		filter_tgt_bw40 = 0x19;
6699 	} else {
6700 		filter_tgt_bw20 = 0x13;
6701 		filter_tgt_bw40 = 0x15;
6702 	}
6703 
6704 	drv_data->calibration_bw20 =
6705 		rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
6706 	drv_data->calibration_bw40 =
6707 		rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
6708 
6709 	/*
6710 	 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
6711 	 */
6712 	drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
6713 	drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
6714 
6715 	/*
6716 	 * Set back to initial state
6717 	 */
6718 	rt2800_bbp_write(rt2x00dev, 24, 0);
6719 
6720 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
6721 	rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
6722 	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
6723 
6724 	/*
6725 	 * Set BBP back to BW20
6726 	 */
6727 	bbp = rt2800_bbp_read(rt2x00dev, 4);
6728 	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
6729 	rt2800_bbp_write(rt2x00dev, 4, bbp);
6730 }
6731 
6732 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
6733 {
6734 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6735 	u8 min_gain, rfcsr, bbp;
6736 	u16 eeprom;
6737 
6738 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
6739 
6740 	rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
6741 	if (rt2x00_rt(rt2x00dev, RT3070) ||
6742 	    rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6743 	    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
6744 	    rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
6745 		if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
6746 			rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
6747 	}
6748 
6749 	min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
6750 	if (drv_data->txmixer_gain_24g >= min_gain) {
6751 		rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
6752 				  drv_data->txmixer_gain_24g);
6753 	}
6754 
6755 	rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
6756 
6757 	if (rt2x00_rt(rt2x00dev, RT3090)) {
6758 		/*  Turn off unused DAC1 and ADC1 to reduce power consumption */
6759 		bbp = rt2800_bbp_read(rt2x00dev, 138);
6760 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
6761 		if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6762 			rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
6763 		if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6764 			rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
6765 		rt2800_bbp_write(rt2x00dev, 138, bbp);
6766 	}
6767 
6768 	if (rt2x00_rt(rt2x00dev, RT3070)) {
6769 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 27);
6770 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
6771 			rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
6772 		else
6773 			rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
6774 		rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
6775 		rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
6776 		rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
6777 		rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
6778 	} else if (rt2x00_rt(rt2x00dev, RT3071) ||
6779 		   rt2x00_rt(rt2x00dev, RT3090) ||
6780 		   rt2x00_rt(rt2x00dev, RT3390)) {
6781 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
6782 		rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
6783 		rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
6784 		rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
6785 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
6786 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
6787 		rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
6788 
6789 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 15);
6790 		rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
6791 		rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
6792 
6793 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
6794 		rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
6795 		rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
6796 
6797 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
6798 		rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
6799 		rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
6800 	}
6801 }
6802 
6803 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
6804 {
6805 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6806 	u8 rfcsr;
6807 	u8 tx_gain;
6808 
6809 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
6810 	rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
6811 	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
6812 
6813 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
6814 	tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
6815 				    RFCSR17_TXMIXER_GAIN);
6816 	rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
6817 	rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
6818 
6819 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 38);
6820 	rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
6821 	rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
6822 
6823 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 39);
6824 	rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
6825 	rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
6826 
6827 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
6828 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
6829 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
6830 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
6831 
6832 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
6833 	rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
6834 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
6835 
6836 	/* TODO: enable stream mode */
6837 }
6838 
6839 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
6840 {
6841 	u8 reg;
6842 	u16 eeprom;
6843 
6844 	/*  Turn off unused DAC1 and ADC1 to reduce power consumption */
6845 	reg = rt2800_bbp_read(rt2x00dev, 138);
6846 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
6847 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6848 		rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
6849 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6850 		rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
6851 	rt2800_bbp_write(rt2x00dev, 138, reg);
6852 
6853 	reg = rt2800_rfcsr_read(rt2x00dev, 38);
6854 	rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
6855 	rt2800_rfcsr_write(rt2x00dev, 38, reg);
6856 
6857 	reg = rt2800_rfcsr_read(rt2x00dev, 39);
6858 	rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
6859 	rt2800_rfcsr_write(rt2x00dev, 39, reg);
6860 
6861 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6862 
6863 	reg = rt2800_rfcsr_read(rt2x00dev, 30);
6864 	rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
6865 	rt2800_rfcsr_write(rt2x00dev, 30, reg);
6866 }
6867 
6868 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
6869 {
6870 	rt2800_rf_init_calibration(rt2x00dev, 30);
6871 
6872 	rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
6873 	rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
6874 	rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
6875 	rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
6876 	rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6877 	rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6878 	rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6879 	rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
6880 	rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
6881 	rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6882 	rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
6883 	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6884 	rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
6885 	rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
6886 	rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6887 	rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6888 	rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6889 	rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6890 	rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6891 	rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6892 	rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6893 	rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6894 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6895 	rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
6896 	rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6897 	rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
6898 	rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
6899 	rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
6900 	rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
6901 	rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
6902 	rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6903 	rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
6904 }
6905 
6906 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
6907 {
6908 	u8 rfcsr;
6909 	u16 eeprom;
6910 	u32 reg;
6911 
6912 	/* XXX vendor driver do this only for 3070 */
6913 	rt2800_rf_init_calibration(rt2x00dev, 30);
6914 
6915 	rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6916 	rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6917 	rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6918 	rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
6919 	rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6920 	rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
6921 	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6922 	rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
6923 	rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6924 	rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6925 	rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6926 	rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6927 	rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6928 	rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6929 	rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6930 	rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6931 	rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6932 	rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
6933 	rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
6934 
6935 	if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
6936 		reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
6937 		rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6938 		rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6939 		rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6940 	} else if (rt2x00_rt(rt2x00dev, RT3071) ||
6941 		   rt2x00_rt(rt2x00dev, RT3090)) {
6942 		rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
6943 
6944 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
6945 		rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6946 		rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6947 
6948 		reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
6949 		rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6950 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6951 		    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
6952 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6953 			if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6954 				rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6955 			else
6956 				rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6957 		}
6958 		rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6959 
6960 		reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
6961 		rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6962 		rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6963 	}
6964 
6965 	rt2800_rx_filter_calibration(rt2x00dev);
6966 
6967 	if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6968 	    rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6969 	    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6970 		rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6971 
6972 	rt2800_led_open_drain_enable(rt2x00dev);
6973 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
6974 }
6975 
6976 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
6977 {
6978 	u8 rfcsr;
6979 
6980 	rt2800_rf_init_calibration(rt2x00dev, 2);
6981 
6982 	rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6983 	rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6984 	rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6985 	rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6986 	rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6987 	rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
6988 	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6989 	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6990 	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6991 	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6992 	rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6993 	rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6994 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6995 	rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6996 	rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6997 	rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6998 	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6999 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7000 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7001 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7002 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7003 	rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
7004 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7005 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7006 	rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7007 	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7008 	rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7009 	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7010 	rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7011 	rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
7012 	rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7013 	rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7014 	rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7015 	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7016 	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7017 	rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
7018 	rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7019 	rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7020 	rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7021 	rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7022 	rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
7023 	rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7024 	rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7025 	rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
7026 	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7027 	rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
7028 
7029 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 29);
7030 	rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
7031 	rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
7032 
7033 	rt2800_led_open_drain_enable(rt2x00dev);
7034 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7035 }
7036 
7037 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
7038 {
7039 	int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0,
7040 				  &rt2x00dev->cap_flags);
7041 	int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1,
7042 				  &rt2x00dev->cap_flags);
7043 	u8 rfcsr;
7044 
7045 	rt2800_rf_init_calibration(rt2x00dev, 30);
7046 
7047 	rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7048 	rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7049 	rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7050 	rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
7051 	rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7052 	rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7053 	rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
7054 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7055 	rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7056 	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7057 	rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
7058 	rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
7059 	rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
7060 	rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
7061 	rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
7062 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7063 	rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
7064 	rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
7065 	rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7066 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7067 	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7068 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7069 	rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7070 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7071 	rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7072 	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7073 	rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7074 	rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
7075 	rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
7076 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7077 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7078 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7079 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7080 	rfcsr = 0x01;
7081 	if (tx0_ext_pa)
7082 		rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1);
7083 	if (tx1_ext_pa)
7084 		rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1);
7085 	rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
7086 	rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
7087 	rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
7088 	rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
7089 	rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
7090 	rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
7091 	rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
7092 	rfcsr = 0x52;
7093 	if (!tx0_ext_pa) {
7094 		rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1);
7095 		rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1);
7096 	}
7097 	rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
7098 	rfcsr = 0x52;
7099 	if (!tx1_ext_pa) {
7100 		rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1);
7101 		rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1);
7102 	}
7103 	rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
7104 	rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
7105 	rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
7106 	rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
7107 	rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
7108 	rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
7109 	rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
7110 	rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
7111 	rfcsr = 0x2d;
7112 	if (tx0_ext_pa)
7113 		rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1);
7114 	if (tx1_ext_pa)
7115 		rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1);
7116 	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7117 	rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f));
7118 	rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00));
7119 	rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52));
7120 	rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b));
7121 	rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f));
7122 	rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00));
7123 	rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52));
7124 	rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b));
7125 	rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
7126 	rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
7127 	rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
7128 	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7129 	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7130 
7131 	rt2800_rx_filter_calibration(rt2x00dev);
7132 	rt2800_led_open_drain_enable(rt2x00dev);
7133 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7134 }
7135 
7136 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
7137 {
7138 	u32 reg;
7139 
7140 	rt2800_rf_init_calibration(rt2x00dev, 30);
7141 
7142 	rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
7143 	rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
7144 	rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7145 	rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
7146 	rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7147 	rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
7148 	rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
7149 	rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
7150 	rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
7151 	rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
7152 	rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
7153 	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7154 	rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
7155 	rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
7156 	rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7157 	rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7158 	rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
7159 	rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
7160 	rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
7161 	rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
7162 	rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
7163 	rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
7164 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7165 	rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
7166 	rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7167 	rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
7168 	rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7169 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7170 	rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
7171 	rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
7172 	rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
7173 	rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
7174 
7175 	reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7176 	rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7177 	rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7178 
7179 	rt2800_rx_filter_calibration(rt2x00dev);
7180 
7181 	if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
7182 		rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7183 
7184 	rt2800_led_open_drain_enable(rt2x00dev);
7185 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7186 }
7187 
7188 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
7189 {
7190 	u8 rfcsr;
7191 	u32 reg;
7192 
7193 	rt2800_rf_init_calibration(rt2x00dev, 30);
7194 
7195 	rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
7196 	rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
7197 	rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7198 	rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
7199 	rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
7200 	rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
7201 	rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
7202 	rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
7203 	rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
7204 	rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
7205 	rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
7206 	rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
7207 	rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
7208 	rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
7209 	rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7210 	rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
7211 	rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
7212 	rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
7213 	rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
7214 	rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
7215 	rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
7216 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7217 	rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
7218 	rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7219 	rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
7220 	rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7221 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7222 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7223 	rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
7224 	rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
7225 	rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
7226 
7227 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7228 	rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7229 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7230 
7231 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7232 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7233 	rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7234 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7235 	msleep(1);
7236 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7237 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7238 	rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7239 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7240 
7241 	rt2800_rx_filter_calibration(rt2x00dev);
7242 	rt2800_led_open_drain_enable(rt2x00dev);
7243 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7244 }
7245 
7246 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
7247 {
7248 	u8 bbp;
7249 	bool txbf_enabled = false; /* FIXME */
7250 
7251 	bbp = rt2800_bbp_read(rt2x00dev, 105);
7252 	if (rt2x00dev->default_ant.rx_chain_num == 1)
7253 		rt2x00_set_field8(&bbp, BBP105_MLD, 0);
7254 	else
7255 		rt2x00_set_field8(&bbp, BBP105_MLD, 1);
7256 	rt2800_bbp_write(rt2x00dev, 105, bbp);
7257 
7258 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7259 
7260 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
7261 	rt2800_bbp_write(rt2x00dev, 82, 0x82);
7262 	rt2800_bbp_write(rt2x00dev, 106, 0x05);
7263 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
7264 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
7265 	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
7266 	rt2800_bbp_write(rt2x00dev, 47, 0x48);
7267 	rt2800_bbp_write(rt2x00dev, 120, 0x50);
7268 
7269 	if (txbf_enabled)
7270 		rt2800_bbp_write(rt2x00dev, 163, 0xbd);
7271 	else
7272 		rt2800_bbp_write(rt2x00dev, 163, 0x9d);
7273 
7274 	/* SNR mapping */
7275 	rt2800_bbp_write(rt2x00dev, 142, 6);
7276 	rt2800_bbp_write(rt2x00dev, 143, 160);
7277 	rt2800_bbp_write(rt2x00dev, 142, 7);
7278 	rt2800_bbp_write(rt2x00dev, 143, 161);
7279 	rt2800_bbp_write(rt2x00dev, 142, 8);
7280 	rt2800_bbp_write(rt2x00dev, 143, 162);
7281 
7282 	/* ADC/DAC control */
7283 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
7284 
7285 	/* RX AGC energy lower bound in log2 */
7286 	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
7287 
7288 	/* FIXME: BBP 105 owerwrite? */
7289 	rt2800_bbp_write(rt2x00dev, 105, 0x04);
7290 
7291 }
7292 
7293 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
7294 {
7295 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7296 	u32 reg;
7297 	u8 rfcsr;
7298 
7299 	/* Disable GPIO #4 and #7 function for LAN PE control */
7300 	reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7301 	rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
7302 	rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
7303 	rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7304 
7305 	/* Initialize default register values */
7306 	rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
7307 	rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
7308 	rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7309 	rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
7310 	rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7311 	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7312 	rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
7313 	rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
7314 	rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
7315 	rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
7316 	rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
7317 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7318 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7319 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7320 	rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
7321 	rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
7322 	rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
7323 	rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
7324 	rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
7325 	rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
7326 	rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
7327 	rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
7328 	rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
7329 	rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
7330 	rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
7331 	rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
7332 	rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
7333 	rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
7334 	rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
7335 	rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
7336 	rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
7337 	rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
7338 
7339 	/* Initiate calibration */
7340 	/* TODO: use rt2800_rf_init_calibration ? */
7341 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
7342 	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
7343 	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
7344 
7345 	rt2800_freq_cal_mode1(rt2x00dev);
7346 
7347 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
7348 	rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
7349 	rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
7350 
7351 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7352 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7353 	rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7354 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7355 	usleep_range(1000, 1500);
7356 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7357 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7358 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7359 
7360 	/* Set initial values for RX filter calibration */
7361 	drv_data->calibration_bw20 = 0x1f;
7362 	drv_data->calibration_bw40 = 0x2f;
7363 
7364 	/* Save BBP 25 & 26 values for later use in channel switching */
7365 	drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7366 	drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7367 
7368 	rt2800_led_open_drain_enable(rt2x00dev);
7369 	rt2800_normal_mode_setup_3593(rt2x00dev);
7370 
7371 	rt3593_post_bbp_init(rt2x00dev);
7372 
7373 	/* TODO: enable stream mode support */
7374 }
7375 
7376 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
7377 {
7378 	rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7379 	rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7380 	rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7381 	rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7382 	rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
7383 	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7384 	rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7385 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7386 	rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7387 	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7388 	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7389 	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7390 	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7391 	if (rt2800_clk_is_20mhz(rt2x00dev))
7392 		rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
7393 	else
7394 		rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7395 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7396 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7397 	rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
7398 	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7399 	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
7400 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7401 	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7402 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7403 	rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7404 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7405 	rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7406 	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7407 	rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7408 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7409 	rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
7410 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7411 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7412 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7413 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7414 	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7415 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7416 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7417 	rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7418 	rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7419 	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7420 	rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7421 	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7422 	rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7423 	rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
7424 	rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
7425 	rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
7426 	rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7427 	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7428 	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7429 	rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
7430 	rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
7431 	rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
7432 	rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7433 	rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7434 	rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
7435 	rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7436 	rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
7437 	rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
7438 	rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
7439 	rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
7440 	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7441 	rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
7442 	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7443 	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7444 }
7445 
7446 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
7447 {
7448 	rt2800_rf_init_calibration(rt2x00dev, 2);
7449 
7450 	rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7451 	rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7452 	rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
7453 	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7454 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7455 		rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7456 	else
7457 		rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7458 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7459 	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7460 	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7461 	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7462 	rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7463 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7464 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7465 	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7466 	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7467 	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
7468 
7469 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7470 	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7471 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7472 	rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7473 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7474 	if (rt2x00_is_usb(rt2x00dev) &&
7475 	    rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7476 		rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7477 	else
7478 		rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
7479 	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7480 	rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7481 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7482 	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7483 
7484 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7485 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7486 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7487 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7488 	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7489 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7490 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7491 	rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7492 	rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7493 	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7494 
7495 	rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7496 	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7497 	rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
7498 	rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
7499 	rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7500 	rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7501 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7502 		rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7503 	else
7504 		rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
7505 	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7506 	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7507 	rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
7508 
7509 	rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7510 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7511 		rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7512 	else
7513 		rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
7514 	rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7515 	rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
7516 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7517 		rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
7518 	else
7519 		rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
7520 	rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7521 	rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7522 	rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
7523 
7524 	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7525 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
7526 		if (rt2x00_is_usb(rt2x00dev))
7527 			rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
7528 		else
7529 			rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
7530 	} else {
7531 		if (rt2x00_is_usb(rt2x00dev))
7532 			rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
7533 		else
7534 			rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
7535 	}
7536 	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7537 	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7538 
7539 	rt2800_normal_mode_setup_5xxx(rt2x00dev);
7540 
7541 	rt2800_led_open_drain_enable(rt2x00dev);
7542 }
7543 
7544 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
7545 {
7546 	rt2800_rf_init_calibration(rt2x00dev, 2);
7547 
7548 	rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
7549 	rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
7550 	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7551 	rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7552 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7553 	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7554 	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7555 	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7556 	rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7557 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7558 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7559 	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7560 	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7561 	rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
7562 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7563 	rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
7564 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7565 	rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
7566 	rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
7567 	rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7568 	rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7569 	rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7570 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7571 	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7572 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7573 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7574 	rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
7575 	rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
7576 	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7577 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7578 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7579 	rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7580 	rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
7581 	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7582 	rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
7583 	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7584 	rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7585 	rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
7586 	rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7587 	rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7588 	rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7589 	rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
7590 	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7591 	rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
7592 	rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
7593 	rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
7594 	rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
7595 	rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
7596 	rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
7597 	rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7598 	rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
7599 	rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
7600 	rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
7601 	rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
7602 	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7603 	rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
7604 	rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
7605 	rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
7606 
7607 	rt2800_normal_mode_setup_5xxx(rt2x00dev);
7608 
7609 	rt2800_led_open_drain_enable(rt2x00dev);
7610 }
7611 
7612 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
7613 {
7614 	rt2800_rf_init_calibration(rt2x00dev, 30);
7615 
7616 	rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
7617 	rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7618 	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7619 	rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
7620 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7621 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7622 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7623 	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7624 	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7625 	rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
7626 	rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
7627 	rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
7628 	rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7629 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7630 	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7631 	rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
7632 	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7633 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7634 	rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
7635 	rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
7636 	rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
7637 
7638 	rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7639 	msleep(1);
7640 
7641 	rt2800_freq_cal_mode1(rt2x00dev);
7642 
7643 	/* Enable DC filter */
7644 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
7645 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
7646 
7647 	rt2800_normal_mode_setup_5xxx(rt2x00dev);
7648 
7649 	if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
7650 		rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7651 
7652 	rt2800_led_open_drain_enable(rt2x00dev);
7653 }
7654 
7655 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
7656 				       bool set_bw, bool is_ht40)
7657 {
7658 	u8 bbp_val;
7659 
7660 	bbp_val = rt2800_bbp_read(rt2x00dev, 21);
7661 	bbp_val |= 0x1;
7662 	rt2800_bbp_write(rt2x00dev, 21, bbp_val);
7663 	usleep_range(100, 200);
7664 
7665 	if (set_bw) {
7666 		bbp_val = rt2800_bbp_read(rt2x00dev, 4);
7667 		rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40);
7668 		rt2800_bbp_write(rt2x00dev, 4, bbp_val);
7669 		usleep_range(100, 200);
7670 	}
7671 
7672 	bbp_val = rt2800_bbp_read(rt2x00dev, 21);
7673 	bbp_val &= (~0x1);
7674 	rt2800_bbp_write(rt2x00dev, 21, bbp_val);
7675 	usleep_range(100, 200);
7676 }
7677 
7678 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
7679 {
7680 	u8 rf_val;
7681 
7682 	if (btxcal)
7683 		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
7684 	else
7685 		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
7686 
7687 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
7688 
7689 	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
7690 	rf_val |= 0x80;
7691 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
7692 
7693 	if (btxcal) {
7694 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
7695 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
7696 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
7697 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
7698 		rf_val &= (~0x3F);
7699 		rf_val |= 0x3F;
7700 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
7701 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
7702 		rf_val &= (~0x3F);
7703 		rf_val |= 0x3F;
7704 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
7705 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
7706 	} else {
7707 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
7708 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
7709 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
7710 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
7711 		rf_val &= (~0x3F);
7712 		rf_val |= 0x34;
7713 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
7714 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
7715 		rf_val &= (~0x3F);
7716 		rf_val |= 0x34;
7717 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
7718 	}
7719 
7720 	return 0;
7721 }
7722 
7723 static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
7724 {
7725 	unsigned int cnt;
7726 	u8 bbp_val;
7727 	char cal_val;
7728 
7729 	rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
7730 
7731 	cnt = 0;
7732 	do {
7733 		usleep_range(500, 2000);
7734 		bbp_val = rt2800_bbp_read(rt2x00dev, 159);
7735 		if (bbp_val == 0x02 || cnt == 20)
7736 			break;
7737 
7738 		cnt++;
7739 	} while (cnt < 20);
7740 
7741 	bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39);
7742 	cal_val = bbp_val & 0x7F;
7743 	if (cal_val >= 0x40)
7744 		cal_val -= 128;
7745 
7746 	return cal_val;
7747 }
7748 
7749 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
7750 					 bool btxcal)
7751 {
7752 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7753 	u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc;
7754 	u8 filter_target;
7755 	u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02;
7756 	u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
7757 	int loop = 0, is_ht40, cnt;
7758 	u8 bbp_val, rf_val;
7759 	char cal_r32_init, cal_r32_val, cal_diff;
7760 	u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
7761 	u8 saverfb5r06, saverfb5r07;
7762 	u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
7763 	u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41;
7764 	u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46;
7765 	u8 saverfb5r58, saverfb5r59;
7766 	u8 savebbp159r0, savebbp159r2, savebbpr23;
7767 	u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0;
7768 
7769 	/* Save MAC registers */
7770 	MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
7771 	MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
7772 
7773 	/* save BBP registers */
7774 	savebbpr23 = rt2800_bbp_read(rt2x00dev, 23);
7775 
7776 	savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0);
7777 	savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2);
7778 
7779 	/* Save RF registers */
7780 	saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
7781 	saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
7782 	saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
7783 	saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
7784 	saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5);
7785 	saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
7786 	saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
7787 	saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
7788 	saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
7789 	saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
7790 	saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
7791 	saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
7792 
7793 	saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37);
7794 	saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38);
7795 	saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39);
7796 	saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40);
7797 	saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41);
7798 	saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42);
7799 	saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43);
7800 	saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44);
7801 	saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45);
7802 	saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46);
7803 
7804 	saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
7805 	saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
7806 
7807 	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
7808 	rf_val |= 0x3;
7809 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
7810 
7811 	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
7812 	rf_val |= 0x1;
7813 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
7814 
7815 	cnt = 0;
7816 	do {
7817 		usleep_range(500, 2000);
7818 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
7819 		if (((rf_val & 0x1) == 0x00) || (cnt == 40))
7820 			break;
7821 		cnt++;
7822 	} while (cnt < 40);
7823 
7824 	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
7825 	rf_val &= (~0x3);
7826 	rf_val |= 0x1;
7827 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
7828 
7829 	/* I-3 */
7830 	bbp_val = rt2800_bbp_read(rt2x00dev, 23);
7831 	bbp_val &= (~0x1F);
7832 	bbp_val |= 0x10;
7833 	rt2800_bbp_write(rt2x00dev, 23, bbp_val);
7834 
7835 	do {
7836 		/* I-4,5,6,7,8,9 */
7837 		if (loop == 0) {
7838 			is_ht40 = false;
7839 
7840 			if (btxcal)
7841 				filter_target = tx_filter_target_20m;
7842 			else
7843 				filter_target = rx_filter_target_20m;
7844 		} else {
7845 			is_ht40 = true;
7846 
7847 			if (btxcal)
7848 				filter_target = tx_filter_target_40m;
7849 			else
7850 				filter_target = rx_filter_target_40m;
7851 		}
7852 
7853 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
7854 		rf_val &= (~0x04);
7855 		if (loop == 1)
7856 			rf_val |= 0x4;
7857 
7858 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
7859 
7860 		rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
7861 
7862 		rt2800_rf_lp_config(rt2x00dev, btxcal);
7863 		if (btxcal) {
7864 			tx_agc_fc = 0;
7865 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
7866 			rf_val &= (~0x7F);
7867 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
7868 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
7869 			rf_val &= (~0x7F);
7870 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
7871 		} else {
7872 			rx_agc_fc = 0;
7873 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
7874 			rf_val &= (~0x7F);
7875 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
7876 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
7877 			rf_val &= (~0x7F);
7878 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
7879 		}
7880 
7881 		usleep_range(1000, 2000);
7882 
7883 		bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
7884 		bbp_val &= (~0x6);
7885 		rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
7886 
7887 		rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
7888 
7889 		cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
7890 
7891 		bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
7892 		bbp_val |= 0x6;
7893 		rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
7894 do_cal:
7895 		if (btxcal) {
7896 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
7897 			rf_val &= (~0x7F);
7898 			rf_val |= tx_agc_fc;
7899 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
7900 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
7901 			rf_val &= (~0x7F);
7902 			rf_val |= tx_agc_fc;
7903 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
7904 		} else {
7905 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
7906 			rf_val &= (~0x7F);
7907 			rf_val |= rx_agc_fc;
7908 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
7909 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
7910 			rf_val &= (~0x7F);
7911 			rf_val |= rx_agc_fc;
7912 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
7913 		}
7914 
7915 		usleep_range(500, 1000);
7916 
7917 		rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
7918 
7919 		cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
7920 
7921 		cal_diff = cal_r32_init - cal_r32_val;
7922 
7923 		if (btxcal)
7924 			cmm_agc_fc = tx_agc_fc;
7925 		else
7926 			cmm_agc_fc = rx_agc_fc;
7927 
7928 		if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) ||
7929 		    ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) {
7930 			if (btxcal)
7931 				tx_agc_fc = 0;
7932 			else
7933 				rx_agc_fc = 0;
7934 		} else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) {
7935 			if (btxcal)
7936 				tx_agc_fc++;
7937 			else
7938 				rx_agc_fc++;
7939 			goto do_cal;
7940 		}
7941 
7942 		if (btxcal) {
7943 			if (loop == 0)
7944 				drv_data->tx_calibration_bw20 = tx_agc_fc;
7945 			else
7946 				drv_data->tx_calibration_bw40 = tx_agc_fc;
7947 		} else {
7948 			if (loop == 0)
7949 				drv_data->rx_calibration_bw20 = rx_agc_fc;
7950 			else
7951 				drv_data->rx_calibration_bw40 = rx_agc_fc;
7952 		}
7953 
7954 		loop++;
7955 	} while (loop <= 1);
7956 
7957 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
7958 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
7959 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
7960 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
7961 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
7962 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
7963 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
7964 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
7965 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
7966 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
7967 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
7968 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
7969 
7970 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
7971 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
7972 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
7973 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
7974 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
7975 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
7976 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
7977 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
7978 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
7979 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
7980 
7981 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
7982 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
7983 
7984 	rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
7985 
7986 	rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
7987 	rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
7988 
7989 	bbp_val = rt2800_bbp_read(rt2x00dev, 4);
7990 	rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH,
7991 			  2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
7992 	rt2800_bbp_write(rt2x00dev, 4, bbp_val);
7993 
7994 	rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
7995 	rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
7996 }
7997 
7998 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
7999 {
8000 	/* Initialize RF central register to default value */
8001 	rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
8002 	rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8003 	rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
8004 	rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
8005 	rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
8006 	rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
8007 	rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
8008 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8009 	rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
8010 	rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
8011 	rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
8012 	rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
8013 	rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
8014 	rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8015 	rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
8016 	rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
8017 	rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
8018 	rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
8019 	rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
8020 	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8021 	rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
8022 	rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
8023 	rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
8024 	rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
8025 	rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
8026 	rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
8027 	rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
8028 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8029 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8030 	rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
8031 	rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
8032 	rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
8033 	rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
8034 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8035 	rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
8036 	rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8037 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8038 	rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8039 	rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
8040 	rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
8041 	rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8042 	rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
8043 	rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
8044 	rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8045 
8046 	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
8047 	if (rt2800_clk_is_20mhz(rt2x00dev))
8048 		rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
8049 	else
8050 		rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8051 	rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
8052 	rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
8053 	rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
8054 	rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
8055 	rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
8056 	rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
8057 	rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
8058 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
8059 	rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
8060 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8061 	rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8062 	rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
8063 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8064 	rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
8065 	rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
8066 	rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
8067 
8068 	rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
8069 	rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
8070 	rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
8071 
8072 	/* Initialize RF channel register to default value */
8073 	rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
8074 	rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
8075 	rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
8076 	rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
8077 	rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
8078 	rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
8079 	rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
8080 	rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
8081 	rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
8082 	rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
8083 	rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
8084 	rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8085 	rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
8086 	rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
8087 	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8088 	rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
8089 	rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
8090 	rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
8091 	rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
8092 	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8093 	rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
8094 	rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
8095 	rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
8096 	rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
8097 	rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
8098 	rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
8099 	rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
8100 	rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
8101 	rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
8102 	rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
8103 	rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
8104 	rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
8105 	rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
8106 	rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
8107 	rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
8108 	rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
8109 	rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
8110 	rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
8111 	rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
8112 	rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
8113 	rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
8114 	rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
8115 	rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
8116 	rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
8117 	rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
8118 	rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8119 	rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
8120 	rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
8121 	rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
8122 	rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
8123 	rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
8124 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
8125 	rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
8126 	rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
8127 	rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
8128 	rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
8129 	rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
8130 	rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
8131 	rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
8132 	rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
8133 
8134 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
8135 
8136 	rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
8137 	rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
8138 	rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
8139 	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
8140 	rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
8141 	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
8142 	rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
8143 	rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
8144 	rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
8145 	rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
8146 	rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
8147 	rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
8148 	rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
8149 	rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
8150 	rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8151 	rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
8152 	rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8153 	rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
8154 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
8155 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
8156 	rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
8157 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
8158 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
8159 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8160 	rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
8161 	rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
8162 	rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
8163 	rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8164 	rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
8165 	rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
8166 
8167 	rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
8168 	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8169 	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8170 	rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
8171 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
8172 	rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
8173 	rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
8174 	rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8175 	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
8176 
8177 	rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
8178 	rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
8179 	rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
8180 	rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
8181 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8182 	rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8183 
8184 	/* Initialize RF channel register for DRQFN */
8185 	rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8186 	rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
8187 	rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
8188 	rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
8189 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
8190 	rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
8191 	rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
8192 	rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
8193 
8194 	/* Initialize RF DC calibration register to default value */
8195 	rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
8196 	rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
8197 	rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
8198 	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
8199 	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
8200 	rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8201 	rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
8202 	rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
8203 	rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
8204 	rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
8205 	rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
8206 	rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
8207 	rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
8208 	rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
8209 	rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
8210 	rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
8211 	rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
8212 	rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
8213 	rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
8214 	rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
8215 	rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
8216 	rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
8217 	rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
8218 	rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
8219 	rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
8220 	rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
8221 	rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
8222 	rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
8223 	rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
8224 	rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
8225 	rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
8226 	rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
8227 	rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
8228 	rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
8229 	rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
8230 	rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
8231 	rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
8232 	rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
8233 	rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
8234 	rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
8235 	rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
8236 	rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
8237 	rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
8238 	rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
8239 	rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
8240 	rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
8241 	rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
8242 	rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
8243 	rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
8244 	rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
8245 	rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
8246 	rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
8247 	rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
8248 	rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
8249 	rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
8250 	rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
8251 	rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
8252 	rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
8253 	rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
8254 
8255 	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
8256 	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
8257 	rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
8258 
8259 	rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8260 	rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
8261 
8262 	rt2800_bw_filter_calibration(rt2x00dev, true);
8263 	rt2800_bw_filter_calibration(rt2x00dev, false);
8264 }
8265 
8266 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
8267 {
8268 	if (rt2800_is_305x_soc(rt2x00dev)) {
8269 		rt2800_init_rfcsr_305x_soc(rt2x00dev);
8270 		return;
8271 	}
8272 
8273 	switch (rt2x00dev->chip.rt) {
8274 	case RT3070:
8275 	case RT3071:
8276 	case RT3090:
8277 		rt2800_init_rfcsr_30xx(rt2x00dev);
8278 		break;
8279 	case RT3290:
8280 		rt2800_init_rfcsr_3290(rt2x00dev);
8281 		break;
8282 	case RT3352:
8283 		rt2800_init_rfcsr_3352(rt2x00dev);
8284 		break;
8285 	case RT3390:
8286 		rt2800_init_rfcsr_3390(rt2x00dev);
8287 		break;
8288 	case RT3572:
8289 		rt2800_init_rfcsr_3572(rt2x00dev);
8290 		break;
8291 	case RT3593:
8292 		rt2800_init_rfcsr_3593(rt2x00dev);
8293 		break;
8294 	case RT5350:
8295 		rt2800_init_rfcsr_5350(rt2x00dev);
8296 		break;
8297 	case RT5390:
8298 		rt2800_init_rfcsr_5390(rt2x00dev);
8299 		break;
8300 	case RT5392:
8301 		rt2800_init_rfcsr_5392(rt2x00dev);
8302 		break;
8303 	case RT5592:
8304 		rt2800_init_rfcsr_5592(rt2x00dev);
8305 		break;
8306 	case RT6352:
8307 		rt2800_init_rfcsr_6352(rt2x00dev);
8308 		break;
8309 	}
8310 }
8311 
8312 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
8313 {
8314 	u32 reg;
8315 	u16 word;
8316 
8317 	/*
8318 	 * Initialize MAC registers.
8319 	 */
8320 	if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
8321 		     rt2800_init_registers(rt2x00dev)))
8322 		return -EIO;
8323 
8324 	/*
8325 	 * Wait BBP/RF to wake up.
8326 	 */
8327 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
8328 		return -EIO;
8329 
8330 	/*
8331 	 * Send signal during boot time to initialize firmware.
8332 	 */
8333 	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
8334 	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8335 	if (rt2x00_is_usb(rt2x00dev))
8336 		rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8337 	rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
8338 	msleep(1);
8339 
8340 	/*
8341 	 * Make sure BBP is up and running.
8342 	 */
8343 	if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
8344 		return -EIO;
8345 
8346 	/*
8347 	 * Initialize BBP/RF registers.
8348 	 */
8349 	rt2800_init_bbp(rt2x00dev);
8350 	rt2800_init_rfcsr(rt2x00dev);
8351 
8352 	if (rt2x00_is_usb(rt2x00dev) &&
8353 	    (rt2x00_rt(rt2x00dev, RT3070) ||
8354 	     rt2x00_rt(rt2x00dev, RT3071) ||
8355 	     rt2x00_rt(rt2x00dev, RT3572))) {
8356 		udelay(200);
8357 		rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
8358 		udelay(10);
8359 	}
8360 
8361 	/*
8362 	 * Enable RX.
8363 	 */
8364 	reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8365 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
8366 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
8367 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
8368 
8369 	udelay(50);
8370 
8371 	reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
8372 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
8373 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
8374 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
8375 	rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
8376 
8377 	reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8378 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
8379 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
8380 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
8381 
8382 	/*
8383 	 * Initialize LED control
8384 	 */
8385 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF);
8386 	rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
8387 			   word & 0xff, (word >> 8) & 0xff);
8388 
8389 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF);
8390 	rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
8391 			   word & 0xff, (word >> 8) & 0xff);
8392 
8393 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY);
8394 	rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
8395 			   word & 0xff, (word >> 8) & 0xff);
8396 
8397 	return 0;
8398 }
8399 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
8400 
8401 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
8402 {
8403 	u32 reg;
8404 
8405 	rt2800_disable_wpdma(rt2x00dev);
8406 
8407 	/* Wait for DMA, ignore error */
8408 	rt2800_wait_wpdma_ready(rt2x00dev);
8409 
8410 	reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8411 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
8412 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
8413 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
8414 }
8415 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
8416 
8417 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
8418 {
8419 	u32 reg;
8420 	u16 efuse_ctrl_reg;
8421 
8422 	if (rt2x00_rt(rt2x00dev, RT3290))
8423 		efuse_ctrl_reg = EFUSE_CTRL_3290;
8424 	else
8425 		efuse_ctrl_reg = EFUSE_CTRL;
8426 
8427 	reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg);
8428 	return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
8429 }
8430 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
8431 
8432 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
8433 {
8434 	u32 reg;
8435 	u16 efuse_ctrl_reg;
8436 	u16 efuse_data0_reg;
8437 	u16 efuse_data1_reg;
8438 	u16 efuse_data2_reg;
8439 	u16 efuse_data3_reg;
8440 
8441 	if (rt2x00_rt(rt2x00dev, RT3290)) {
8442 		efuse_ctrl_reg = EFUSE_CTRL_3290;
8443 		efuse_data0_reg = EFUSE_DATA0_3290;
8444 		efuse_data1_reg = EFUSE_DATA1_3290;
8445 		efuse_data2_reg = EFUSE_DATA2_3290;
8446 		efuse_data3_reg = EFUSE_DATA3_3290;
8447 	} else {
8448 		efuse_ctrl_reg = EFUSE_CTRL;
8449 		efuse_data0_reg = EFUSE_DATA0;
8450 		efuse_data1_reg = EFUSE_DATA1;
8451 		efuse_data2_reg = EFUSE_DATA2;
8452 		efuse_data3_reg = EFUSE_DATA3;
8453 	}
8454 	mutex_lock(&rt2x00dev->csr_mutex);
8455 
8456 	reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg);
8457 	rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
8458 	rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
8459 	rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
8460 	rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
8461 
8462 	/* Wait until the EEPROM has been loaded */
8463 	rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
8464 	/* Apparently the data is read from end to start */
8465 	reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg);
8466 	/* The returned value is in CPU order, but eeprom is le */
8467 	*(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
8468 	reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg);
8469 	*(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
8470 	reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg);
8471 	*(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
8472 	reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg);
8473 	*(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
8474 
8475 	mutex_unlock(&rt2x00dev->csr_mutex);
8476 }
8477 
8478 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
8479 {
8480 	unsigned int i;
8481 
8482 	for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
8483 		rt2800_efuse_read(rt2x00dev, i);
8484 
8485 	return 0;
8486 }
8487 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
8488 
8489 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
8490 {
8491 	u16 word;
8492 
8493 	if (rt2x00_rt(rt2x00dev, RT3593))
8494 		return 0;
8495 
8496 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG);
8497 	if ((word & 0x00ff) != 0x00ff)
8498 		return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
8499 
8500 	return 0;
8501 }
8502 
8503 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
8504 {
8505 	u16 word;
8506 
8507 	if (rt2x00_rt(rt2x00dev, RT3593))
8508 		return 0;
8509 
8510 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A);
8511 	if ((word & 0x00ff) != 0x00ff)
8512 		return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
8513 
8514 	return 0;
8515 }
8516 
8517 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
8518 {
8519 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
8520 	u16 word;
8521 	u8 *mac;
8522 	u8 default_lna_gain;
8523 	int retval;
8524 
8525 	/*
8526 	 * Read the EEPROM.
8527 	 */
8528 	retval = rt2800_read_eeprom(rt2x00dev);
8529 	if (retval)
8530 		return retval;
8531 
8532 	/*
8533 	 * Start validation of the data that has been read.
8534 	 */
8535 	mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
8536 	rt2x00lib_set_mac_address(rt2x00dev, mac);
8537 
8538 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
8539 	if (word == 0xffff) {
8540 		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
8541 		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
8542 		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
8543 		rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
8544 		rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
8545 	} else if (rt2x00_rt(rt2x00dev, RT2860) ||
8546 		   rt2x00_rt(rt2x00dev, RT2872)) {
8547 		/*
8548 		 * There is a max of 2 RX streams for RT28x0 series
8549 		 */
8550 		if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
8551 			rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
8552 		rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
8553 	}
8554 
8555 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
8556 	if (word == 0xffff) {
8557 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
8558 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
8559 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
8560 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
8561 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
8562 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
8563 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
8564 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
8565 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
8566 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
8567 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
8568 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
8569 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
8570 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
8571 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
8572 		rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
8573 		rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
8574 	}
8575 
8576 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
8577 	if ((word & 0x00ff) == 0x00ff) {
8578 		rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
8579 		rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
8580 		rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
8581 	}
8582 	if ((word & 0xff00) == 0xff00) {
8583 		rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
8584 				   LED_MODE_TXRX_ACTIVITY);
8585 		rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
8586 		rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
8587 		rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
8588 		rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
8589 		rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
8590 		rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
8591 	}
8592 
8593 	/*
8594 	 * During the LNA validation we are going to use
8595 	 * lna0 as correct value. Note that EEPROM_LNA
8596 	 * is never validated.
8597 	 */
8598 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
8599 	default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
8600 
8601 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
8602 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
8603 		rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
8604 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
8605 		rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
8606 	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
8607 
8608 	drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
8609 
8610 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
8611 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
8612 		rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
8613 	if (!rt2x00_rt(rt2x00dev, RT3593)) {
8614 		if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
8615 		    rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
8616 			rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
8617 					   default_lna_gain);
8618 	}
8619 	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
8620 
8621 	drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
8622 
8623 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
8624 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
8625 		rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
8626 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
8627 		rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
8628 	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
8629 
8630 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
8631 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
8632 		rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
8633 	if (!rt2x00_rt(rt2x00dev, RT3593)) {
8634 		if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
8635 		    rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
8636 			rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
8637 					   default_lna_gain);
8638 	}
8639 	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
8640 
8641 	if (rt2x00_rt(rt2x00dev, RT3593)) {
8642 		word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
8643 		if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
8644 		    rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
8645 			rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
8646 					   default_lna_gain);
8647 		if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
8648 		    rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
8649 			rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
8650 					   default_lna_gain);
8651 		rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
8652 	}
8653 
8654 	return 0;
8655 }
8656 
8657 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
8658 {
8659 	u16 value;
8660 	u16 eeprom;
8661 	u16 rf;
8662 
8663 	/*
8664 	 * Read EEPROM word for configuration.
8665 	 */
8666 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
8667 
8668 	/*
8669 	 * Identify RF chipset by EEPROM value
8670 	 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
8671 	 * RT53xx: defined in "EEPROM_CHIP_ID" field
8672 	 */
8673 	if (rt2x00_rt(rt2x00dev, RT3290) ||
8674 	    rt2x00_rt(rt2x00dev, RT5390) ||
8675 	    rt2x00_rt(rt2x00dev, RT5392) ||
8676 	    rt2x00_rt(rt2x00dev, RT6352))
8677 		rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID);
8678 	else if (rt2x00_rt(rt2x00dev, RT3352))
8679 		rf = RF3322;
8680 	else if (rt2x00_rt(rt2x00dev, RT5350))
8681 		rf = RF5350;
8682 	else
8683 		rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
8684 
8685 	switch (rf) {
8686 	case RF2820:
8687 	case RF2850:
8688 	case RF2720:
8689 	case RF2750:
8690 	case RF3020:
8691 	case RF2020:
8692 	case RF3021:
8693 	case RF3022:
8694 	case RF3052:
8695 	case RF3053:
8696 	case RF3070:
8697 	case RF3290:
8698 	case RF3320:
8699 	case RF3322:
8700 	case RF5350:
8701 	case RF5360:
8702 	case RF5362:
8703 	case RF5370:
8704 	case RF5372:
8705 	case RF5390:
8706 	case RF5392:
8707 	case RF5592:
8708 	case RF7620:
8709 		break;
8710 	default:
8711 		rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
8712 			   rf);
8713 		return -ENODEV;
8714 	}
8715 
8716 	rt2x00_set_rf(rt2x00dev, rf);
8717 
8718 	/*
8719 	 * Identify default antenna configuration.
8720 	 */
8721 	rt2x00dev->default_ant.tx_chain_num =
8722 	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
8723 	rt2x00dev->default_ant.rx_chain_num =
8724 	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
8725 
8726 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
8727 
8728 	if (rt2x00_rt(rt2x00dev, RT3070) ||
8729 	    rt2x00_rt(rt2x00dev, RT3090) ||
8730 	    rt2x00_rt(rt2x00dev, RT3352) ||
8731 	    rt2x00_rt(rt2x00dev, RT3390)) {
8732 		value = rt2x00_get_field16(eeprom,
8733 				EEPROM_NIC_CONF1_ANT_DIVERSITY);
8734 		switch (value) {
8735 		case 0:
8736 		case 1:
8737 		case 2:
8738 			rt2x00dev->default_ant.tx = ANTENNA_A;
8739 			rt2x00dev->default_ant.rx = ANTENNA_A;
8740 			break;
8741 		case 3:
8742 			rt2x00dev->default_ant.tx = ANTENNA_A;
8743 			rt2x00dev->default_ant.rx = ANTENNA_B;
8744 			break;
8745 		}
8746 	} else {
8747 		rt2x00dev->default_ant.tx = ANTENNA_A;
8748 		rt2x00dev->default_ant.rx = ANTENNA_A;
8749 	}
8750 
8751 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
8752 		rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
8753 		rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
8754 	}
8755 
8756 	/*
8757 	 * Determine external LNA informations.
8758 	 */
8759 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
8760 		__set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
8761 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
8762 		__set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
8763 
8764 	/*
8765 	 * Detect if this device has an hardware controlled radio.
8766 	 */
8767 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
8768 		__set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
8769 
8770 	/*
8771 	 * Detect if this device has Bluetooth co-existence.
8772 	 */
8773 	if (!rt2x00_rt(rt2x00dev, RT3352) &&
8774 	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
8775 		__set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
8776 
8777 	/*
8778 	 * Read frequency offset and RF programming sequence.
8779 	 */
8780 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
8781 	rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
8782 
8783 	/*
8784 	 * Store led settings, for correct led behaviour.
8785 	 */
8786 #ifdef CONFIG_RT2X00_LIB_LEDS
8787 	rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
8788 	rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
8789 	rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
8790 
8791 	rt2x00dev->led_mcu_reg = eeprom;
8792 #endif /* CONFIG_RT2X00_LIB_LEDS */
8793 
8794 	/*
8795 	 * Check if support EIRP tx power limit feature.
8796 	 */
8797 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
8798 
8799 	if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
8800 					EIRP_MAX_TX_POWER_LIMIT)
8801 		__set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
8802 
8803 	/*
8804 	 * Detect if device uses internal or external PA
8805 	 */
8806 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
8807 
8808 	if (rt2x00_rt(rt2x00dev, RT3352)) {
8809 		if (rt2x00_get_field16(eeprom,
8810 		    EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))
8811 		    __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
8812 			      &rt2x00dev->cap_flags);
8813 		if (rt2x00_get_field16(eeprom,
8814 		    EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352))
8815 		    __set_bit(CAPABILITY_EXTERNAL_PA_TX1,
8816 			      &rt2x00dev->cap_flags);
8817 	}
8818 
8819 	return 0;
8820 }
8821 
8822 /*
8823  * RF value list for rt28xx
8824  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
8825  */
8826 static const struct rf_channel rf_vals[] = {
8827 	{ 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
8828 	{ 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
8829 	{ 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
8830 	{ 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
8831 	{ 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
8832 	{ 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
8833 	{ 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
8834 	{ 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
8835 	{ 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
8836 	{ 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
8837 	{ 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
8838 	{ 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
8839 	{ 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
8840 	{ 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
8841 
8842 	/* 802.11 UNI / HyperLan 2 */
8843 	{ 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
8844 	{ 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
8845 	{ 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
8846 	{ 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
8847 	{ 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
8848 	{ 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
8849 	{ 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
8850 	{ 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
8851 	{ 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
8852 	{ 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
8853 	{ 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
8854 	{ 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
8855 
8856 	/* 802.11 HyperLan 2 */
8857 	{ 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
8858 	{ 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
8859 	{ 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
8860 	{ 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
8861 	{ 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
8862 	{ 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
8863 	{ 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
8864 	{ 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
8865 	{ 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
8866 	{ 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
8867 	{ 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
8868 	{ 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
8869 	{ 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
8870 	{ 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
8871 	{ 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
8872 	{ 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
8873 
8874 	/* 802.11 UNII */
8875 	{ 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
8876 	{ 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
8877 	{ 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
8878 	{ 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
8879 	{ 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
8880 	{ 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
8881 	{ 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
8882 	{ 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
8883 	{ 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
8884 	{ 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
8885 	{ 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
8886 
8887 	/* 802.11 Japan */
8888 	{ 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
8889 	{ 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
8890 	{ 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
8891 	{ 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
8892 	{ 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
8893 	{ 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
8894 	{ 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
8895 };
8896 
8897 /*
8898  * RF value list for rt3xxx
8899  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
8900  */
8901 static const struct rf_channel rf_vals_3x[] = {
8902 	{1,  241, 2, 2 },
8903 	{2,  241, 2, 7 },
8904 	{3,  242, 2, 2 },
8905 	{4,  242, 2, 7 },
8906 	{5,  243, 2, 2 },
8907 	{6,  243, 2, 7 },
8908 	{7,  244, 2, 2 },
8909 	{8,  244, 2, 7 },
8910 	{9,  245, 2, 2 },
8911 	{10, 245, 2, 7 },
8912 	{11, 246, 2, 2 },
8913 	{12, 246, 2, 7 },
8914 	{13, 247, 2, 2 },
8915 	{14, 248, 2, 4 },
8916 
8917 	/* 802.11 UNI / HyperLan 2 */
8918 	{36, 0x56, 0, 4},
8919 	{38, 0x56, 0, 6},
8920 	{40, 0x56, 0, 8},
8921 	{44, 0x57, 0, 0},
8922 	{46, 0x57, 0, 2},
8923 	{48, 0x57, 0, 4},
8924 	{52, 0x57, 0, 8},
8925 	{54, 0x57, 0, 10},
8926 	{56, 0x58, 0, 0},
8927 	{60, 0x58, 0, 4},
8928 	{62, 0x58, 0, 6},
8929 	{64, 0x58, 0, 8},
8930 
8931 	/* 802.11 HyperLan 2 */
8932 	{100, 0x5b, 0, 8},
8933 	{102, 0x5b, 0, 10},
8934 	{104, 0x5c, 0, 0},
8935 	{108, 0x5c, 0, 4},
8936 	{110, 0x5c, 0, 6},
8937 	{112, 0x5c, 0, 8},
8938 	{116, 0x5d, 0, 0},
8939 	{118, 0x5d, 0, 2},
8940 	{120, 0x5d, 0, 4},
8941 	{124, 0x5d, 0, 8},
8942 	{126, 0x5d, 0, 10},
8943 	{128, 0x5e, 0, 0},
8944 	{132, 0x5e, 0, 4},
8945 	{134, 0x5e, 0, 6},
8946 	{136, 0x5e, 0, 8},
8947 	{140, 0x5f, 0, 0},
8948 
8949 	/* 802.11 UNII */
8950 	{149, 0x5f, 0, 9},
8951 	{151, 0x5f, 0, 11},
8952 	{153, 0x60, 0, 1},
8953 	{157, 0x60, 0, 5},
8954 	{159, 0x60, 0, 7},
8955 	{161, 0x60, 0, 9},
8956 	{165, 0x61, 0, 1},
8957 	{167, 0x61, 0, 3},
8958 	{169, 0x61, 0, 5},
8959 	{171, 0x61, 0, 7},
8960 	{173, 0x61, 0, 9},
8961 };
8962 
8963 /*
8964  * RF value list for rt3xxx with Xtal20MHz
8965  * Supports: 2.4 GHz (all) (RF3322)
8966  */
8967 static const struct rf_channel rf_vals_3x_xtal20[] = {
8968 	{1,    0xE2,	 2,  0x14},
8969 	{2,    0xE3,	 2,  0x14},
8970 	{3,    0xE4,	 2,  0x14},
8971 	{4,    0xE5,	 2,  0x14},
8972 	{5,    0xE6,	 2,  0x14},
8973 	{6,    0xE7,	 2,  0x14},
8974 	{7,    0xE8,	 2,  0x14},
8975 	{8,    0xE9,	 2,  0x14},
8976 	{9,    0xEA,	 2,  0x14},
8977 	{10,   0xEB,	 2,  0x14},
8978 	{11,   0xEC,	 2,  0x14},
8979 	{12,   0xED,	 2,  0x14},
8980 	{13,   0xEE,	 2,  0x14},
8981 	{14,   0xF0,	 2,  0x18},
8982 };
8983 
8984 static const struct rf_channel rf_vals_5592_xtal20[] = {
8985 	/* Channel, N, K, mod, R */
8986 	{1, 482, 4, 10, 3},
8987 	{2, 483, 4, 10, 3},
8988 	{3, 484, 4, 10, 3},
8989 	{4, 485, 4, 10, 3},
8990 	{5, 486, 4, 10, 3},
8991 	{6, 487, 4, 10, 3},
8992 	{7, 488, 4, 10, 3},
8993 	{8, 489, 4, 10, 3},
8994 	{9, 490, 4, 10, 3},
8995 	{10, 491, 4, 10, 3},
8996 	{11, 492, 4, 10, 3},
8997 	{12, 493, 4, 10, 3},
8998 	{13, 494, 4, 10, 3},
8999 	{14, 496, 8, 10, 3},
9000 	{36, 172, 8, 12, 1},
9001 	{38, 173, 0, 12, 1},
9002 	{40, 173, 4, 12, 1},
9003 	{42, 173, 8, 12, 1},
9004 	{44, 174, 0, 12, 1},
9005 	{46, 174, 4, 12, 1},
9006 	{48, 174, 8, 12, 1},
9007 	{50, 175, 0, 12, 1},
9008 	{52, 175, 4, 12, 1},
9009 	{54, 175, 8, 12, 1},
9010 	{56, 176, 0, 12, 1},
9011 	{58, 176, 4, 12, 1},
9012 	{60, 176, 8, 12, 1},
9013 	{62, 177, 0, 12, 1},
9014 	{64, 177, 4, 12, 1},
9015 	{100, 183, 4, 12, 1},
9016 	{102, 183, 8, 12, 1},
9017 	{104, 184, 0, 12, 1},
9018 	{106, 184, 4, 12, 1},
9019 	{108, 184, 8, 12, 1},
9020 	{110, 185, 0, 12, 1},
9021 	{112, 185, 4, 12, 1},
9022 	{114, 185, 8, 12, 1},
9023 	{116, 186, 0, 12, 1},
9024 	{118, 186, 4, 12, 1},
9025 	{120, 186, 8, 12, 1},
9026 	{122, 187, 0, 12, 1},
9027 	{124, 187, 4, 12, 1},
9028 	{126, 187, 8, 12, 1},
9029 	{128, 188, 0, 12, 1},
9030 	{130, 188, 4, 12, 1},
9031 	{132, 188, 8, 12, 1},
9032 	{134, 189, 0, 12, 1},
9033 	{136, 189, 4, 12, 1},
9034 	{138, 189, 8, 12, 1},
9035 	{140, 190, 0, 12, 1},
9036 	{149, 191, 6, 12, 1},
9037 	{151, 191, 10, 12, 1},
9038 	{153, 192, 2, 12, 1},
9039 	{155, 192, 6, 12, 1},
9040 	{157, 192, 10, 12, 1},
9041 	{159, 193, 2, 12, 1},
9042 	{161, 193, 6, 12, 1},
9043 	{165, 194, 2, 12, 1},
9044 	{184, 164, 0, 12, 1},
9045 	{188, 164, 4, 12, 1},
9046 	{192, 165, 8, 12, 1},
9047 	{196, 166, 0, 12, 1},
9048 };
9049 
9050 static const struct rf_channel rf_vals_5592_xtal40[] = {
9051 	/* Channel, N, K, mod, R */
9052 	{1, 241, 2, 10, 3},
9053 	{2, 241, 7, 10, 3},
9054 	{3, 242, 2, 10, 3},
9055 	{4, 242, 7, 10, 3},
9056 	{5, 243, 2, 10, 3},
9057 	{6, 243, 7, 10, 3},
9058 	{7, 244, 2, 10, 3},
9059 	{8, 244, 7, 10, 3},
9060 	{9, 245, 2, 10, 3},
9061 	{10, 245, 7, 10, 3},
9062 	{11, 246, 2, 10, 3},
9063 	{12, 246, 7, 10, 3},
9064 	{13, 247, 2, 10, 3},
9065 	{14, 248, 4, 10, 3},
9066 	{36, 86, 4, 12, 1},
9067 	{38, 86, 6, 12, 1},
9068 	{40, 86, 8, 12, 1},
9069 	{42, 86, 10, 12, 1},
9070 	{44, 87, 0, 12, 1},
9071 	{46, 87, 2, 12, 1},
9072 	{48, 87, 4, 12, 1},
9073 	{50, 87, 6, 12, 1},
9074 	{52, 87, 8, 12, 1},
9075 	{54, 87, 10, 12, 1},
9076 	{56, 88, 0, 12, 1},
9077 	{58, 88, 2, 12, 1},
9078 	{60, 88, 4, 12, 1},
9079 	{62, 88, 6, 12, 1},
9080 	{64, 88, 8, 12, 1},
9081 	{100, 91, 8, 12, 1},
9082 	{102, 91, 10, 12, 1},
9083 	{104, 92, 0, 12, 1},
9084 	{106, 92, 2, 12, 1},
9085 	{108, 92, 4, 12, 1},
9086 	{110, 92, 6, 12, 1},
9087 	{112, 92, 8, 12, 1},
9088 	{114, 92, 10, 12, 1},
9089 	{116, 93, 0, 12, 1},
9090 	{118, 93, 2, 12, 1},
9091 	{120, 93, 4, 12, 1},
9092 	{122, 93, 6, 12, 1},
9093 	{124, 93, 8, 12, 1},
9094 	{126, 93, 10, 12, 1},
9095 	{128, 94, 0, 12, 1},
9096 	{130, 94, 2, 12, 1},
9097 	{132, 94, 4, 12, 1},
9098 	{134, 94, 6, 12, 1},
9099 	{136, 94, 8, 12, 1},
9100 	{138, 94, 10, 12, 1},
9101 	{140, 95, 0, 12, 1},
9102 	{149, 95, 9, 12, 1},
9103 	{151, 95, 11, 12, 1},
9104 	{153, 96, 1, 12, 1},
9105 	{155, 96, 3, 12, 1},
9106 	{157, 96, 5, 12, 1},
9107 	{159, 96, 7, 12, 1},
9108 	{161, 96, 9, 12, 1},
9109 	{165, 97, 1, 12, 1},
9110 	{184, 82, 0, 12, 1},
9111 	{188, 82, 4, 12, 1},
9112 	{192, 82, 8, 12, 1},
9113 	{196, 83, 0, 12, 1},
9114 };
9115 
9116 static const struct rf_channel rf_vals_7620[] = {
9117 	{1, 0x50, 0x99, 0x99, 1},
9118 	{2, 0x50, 0x44, 0x44, 2},
9119 	{3, 0x50, 0xEE, 0xEE, 2},
9120 	{4, 0x50, 0x99, 0x99, 3},
9121 	{5, 0x51, 0x44, 0x44, 0},
9122 	{6, 0x51, 0xEE, 0xEE, 0},
9123 	{7, 0x51, 0x99, 0x99, 1},
9124 	{8, 0x51, 0x44, 0x44, 2},
9125 	{9, 0x51, 0xEE, 0xEE, 2},
9126 	{10, 0x51, 0x99, 0x99, 3},
9127 	{11, 0x52, 0x44, 0x44, 0},
9128 	{12, 0x52, 0xEE, 0xEE, 0},
9129 	{13, 0x52, 0x99, 0x99, 1},
9130 	{14, 0x52, 0x33, 0x33, 3},
9131 };
9132 
9133 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
9134 {
9135 	struct hw_mode_spec *spec = &rt2x00dev->spec;
9136 	struct channel_info *info;
9137 	char *default_power1;
9138 	char *default_power2;
9139 	char *default_power3;
9140 	unsigned int i, tx_chains, rx_chains;
9141 	u32 reg;
9142 
9143 	/*
9144 	 * Disable powersaving as default.
9145 	 */
9146 	rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
9147 
9148 	/*
9149 	 * Change default retry settings to values corresponding more closely
9150 	 * to rate[0].count setting of minstrel rate control algorithm.
9151 	 */
9152 	rt2x00dev->hw->wiphy->retry_short = 2;
9153 	rt2x00dev->hw->wiphy->retry_long = 2;
9154 
9155 	/*
9156 	 * Initialize all hw fields.
9157 	 */
9158 	ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
9159 	ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
9160 	ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
9161 	ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
9162 	ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
9163 
9164 	/*
9165 	 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
9166 	 * unless we are capable of sending the buffered frames out after the
9167 	 * DTIM transmission using rt2x00lib_beacondone. This will send out
9168 	 * multicast and broadcast traffic immediately instead of buffering it
9169 	 * infinitly and thus dropping it after some time.
9170 	 */
9171 	if (!rt2x00_is_usb(rt2x00dev))
9172 		ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
9173 
9174 	/* Set MFP if HW crypto is disabled. */
9175 	if (rt2800_hwcrypt_disabled(rt2x00dev))
9176 		ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
9177 
9178 	SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
9179 	SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
9180 				rt2800_eeprom_addr(rt2x00dev,
9181 						   EEPROM_MAC_ADDR_0));
9182 
9183 	/*
9184 	 * As rt2800 has a global fallback table we cannot specify
9185 	 * more then one tx rate per frame but since the hw will
9186 	 * try several rates (based on the fallback table) we should
9187 	 * initialize max_report_rates to the maximum number of rates
9188 	 * we are going to try. Otherwise mac80211 will truncate our
9189 	 * reported tx rates and the rc algortihm will end up with
9190 	 * incorrect data.
9191 	 */
9192 	rt2x00dev->hw->max_rates = 1;
9193 	rt2x00dev->hw->max_report_rates = 7;
9194 	rt2x00dev->hw->max_rate_tries = 1;
9195 
9196 	/*
9197 	 * Initialize hw_mode information.
9198 	 */
9199 	spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
9200 
9201 	switch (rt2x00dev->chip.rf) {
9202 	case RF2720:
9203 	case RF2820:
9204 		spec->num_channels = 14;
9205 		spec->channels = rf_vals;
9206 		break;
9207 
9208 	case RF2750:
9209 	case RF2850:
9210 		spec->num_channels = ARRAY_SIZE(rf_vals);
9211 		spec->channels = rf_vals;
9212 		break;
9213 
9214 	case RF2020:
9215 	case RF3020:
9216 	case RF3021:
9217 	case RF3022:
9218 	case RF3070:
9219 	case RF3290:
9220 	case RF3320:
9221 	case RF3322:
9222 	case RF5350:
9223 	case RF5360:
9224 	case RF5362:
9225 	case RF5370:
9226 	case RF5372:
9227 	case RF5390:
9228 	case RF5392:
9229 		spec->num_channels = 14;
9230 		if (rt2800_clk_is_20mhz(rt2x00dev))
9231 			spec->channels = rf_vals_3x_xtal20;
9232 		else
9233 			spec->channels = rf_vals_3x;
9234 		break;
9235 
9236 	case RF7620:
9237 		spec->num_channels = ARRAY_SIZE(rf_vals_7620);
9238 		spec->channels = rf_vals_7620;
9239 		break;
9240 
9241 	case RF3052:
9242 	case RF3053:
9243 		spec->num_channels = ARRAY_SIZE(rf_vals_3x);
9244 		spec->channels = rf_vals_3x;
9245 		break;
9246 
9247 	case RF5592:
9248 		reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX);
9249 		if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
9250 			spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
9251 			spec->channels = rf_vals_5592_xtal40;
9252 		} else {
9253 			spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
9254 			spec->channels = rf_vals_5592_xtal20;
9255 		}
9256 		break;
9257 	}
9258 
9259 	if (WARN_ON_ONCE(!spec->channels))
9260 		return -ENODEV;
9261 
9262 	spec->supported_bands = SUPPORT_BAND_2GHZ;
9263 	if (spec->num_channels > 14)
9264 		spec->supported_bands |= SUPPORT_BAND_5GHZ;
9265 
9266 	/*
9267 	 * Initialize HT information.
9268 	 */
9269 	if (!rt2x00_rf(rt2x00dev, RF2020))
9270 		spec->ht.ht_supported = true;
9271 	else
9272 		spec->ht.ht_supported = false;
9273 
9274 	spec->ht.cap =
9275 	    IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
9276 	    IEEE80211_HT_CAP_GRN_FLD |
9277 	    IEEE80211_HT_CAP_SGI_20 |
9278 	    IEEE80211_HT_CAP_SGI_40;
9279 
9280 	tx_chains = rt2x00dev->default_ant.tx_chain_num;
9281 	rx_chains = rt2x00dev->default_ant.rx_chain_num;
9282 
9283 	if (tx_chains >= 2)
9284 		spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
9285 
9286 	spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT;
9287 
9288 	spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2;
9289 	spec->ht.ampdu_density = 4;
9290 	spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
9291 	if (tx_chains != rx_chains) {
9292 		spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
9293 		spec->ht.mcs.tx_params |=
9294 		    (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
9295 	}
9296 
9297 	switch (rx_chains) {
9298 	case 3:
9299 		spec->ht.mcs.rx_mask[2] = 0xff;
9300 	case 2:
9301 		spec->ht.mcs.rx_mask[1] = 0xff;
9302 	case 1:
9303 		spec->ht.mcs.rx_mask[0] = 0xff;
9304 		spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
9305 		break;
9306 	}
9307 
9308 	/*
9309 	 * Create channel information array
9310 	 */
9311 	info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
9312 	if (!info)
9313 		return -ENOMEM;
9314 
9315 	spec->channels_info = info;
9316 
9317 	default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
9318 	default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
9319 
9320 	if (rt2x00dev->default_ant.tx_chain_num > 2)
9321 		default_power3 = rt2800_eeprom_addr(rt2x00dev,
9322 						    EEPROM_EXT_TXPOWER_BG3);
9323 	else
9324 		default_power3 = NULL;
9325 
9326 	for (i = 0; i < 14; i++) {
9327 		info[i].default_power1 = default_power1[i];
9328 		info[i].default_power2 = default_power2[i];
9329 		if (default_power3)
9330 			info[i].default_power3 = default_power3[i];
9331 	}
9332 
9333 	if (spec->num_channels > 14) {
9334 		default_power1 = rt2800_eeprom_addr(rt2x00dev,
9335 						    EEPROM_TXPOWER_A1);
9336 		default_power2 = rt2800_eeprom_addr(rt2x00dev,
9337 						    EEPROM_TXPOWER_A2);
9338 
9339 		if (rt2x00dev->default_ant.tx_chain_num > 2)
9340 			default_power3 =
9341 				rt2800_eeprom_addr(rt2x00dev,
9342 						   EEPROM_EXT_TXPOWER_A3);
9343 		else
9344 			default_power3 = NULL;
9345 
9346 		for (i = 14; i < spec->num_channels; i++) {
9347 			info[i].default_power1 = default_power1[i - 14];
9348 			info[i].default_power2 = default_power2[i - 14];
9349 			if (default_power3)
9350 				info[i].default_power3 = default_power3[i - 14];
9351 		}
9352 	}
9353 
9354 	switch (rt2x00dev->chip.rf) {
9355 	case RF2020:
9356 	case RF3020:
9357 	case RF3021:
9358 	case RF3022:
9359 	case RF3320:
9360 	case RF3052:
9361 	case RF3053:
9362 	case RF3070:
9363 	case RF3290:
9364 	case RF5350:
9365 	case RF5360:
9366 	case RF5362:
9367 	case RF5370:
9368 	case RF5372:
9369 	case RF5390:
9370 	case RF5392:
9371 	case RF5592:
9372 	case RF7620:
9373 		__set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
9374 		break;
9375 	}
9376 
9377 	return 0;
9378 }
9379 
9380 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
9381 {
9382 	u32 reg;
9383 	u32 rt;
9384 	u32 rev;
9385 
9386 	if (rt2x00_rt(rt2x00dev, RT3290))
9387 		reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290);
9388 	else
9389 		reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
9390 
9391 	rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
9392 	rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
9393 
9394 	switch (rt) {
9395 	case RT2860:
9396 	case RT2872:
9397 	case RT2883:
9398 	case RT3070:
9399 	case RT3071:
9400 	case RT3090:
9401 	case RT3290:
9402 	case RT3352:
9403 	case RT3390:
9404 	case RT3572:
9405 	case RT3593:
9406 	case RT5350:
9407 	case RT5390:
9408 	case RT5392:
9409 	case RT5592:
9410 		break;
9411 	default:
9412 		rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
9413 			   rt, rev);
9414 		return -ENODEV;
9415 	}
9416 
9417 	if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
9418 		rt = RT6352;
9419 
9420 	rt2x00_set_rt(rt2x00dev, rt, rev);
9421 
9422 	return 0;
9423 }
9424 
9425 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
9426 {
9427 	int retval;
9428 	u32 reg;
9429 
9430 	retval = rt2800_probe_rt(rt2x00dev);
9431 	if (retval)
9432 		return retval;
9433 
9434 	/*
9435 	 * Allocate eeprom data.
9436 	 */
9437 	retval = rt2800_validate_eeprom(rt2x00dev);
9438 	if (retval)
9439 		return retval;
9440 
9441 	retval = rt2800_init_eeprom(rt2x00dev);
9442 	if (retval)
9443 		return retval;
9444 
9445 	/*
9446 	 * Enable rfkill polling by setting GPIO direction of the
9447 	 * rfkill switch GPIO pin correctly.
9448 	 */
9449 	reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
9450 	rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
9451 	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
9452 
9453 	/*
9454 	 * Initialize hw specifications.
9455 	 */
9456 	retval = rt2800_probe_hw_mode(rt2x00dev);
9457 	if (retval)
9458 		return retval;
9459 
9460 	/*
9461 	 * Set device capabilities.
9462 	 */
9463 	__set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
9464 	__set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
9465 	if (!rt2x00_is_usb(rt2x00dev))
9466 		__set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
9467 
9468 	/*
9469 	 * Set device requirements.
9470 	 */
9471 	if (!rt2x00_is_soc(rt2x00dev))
9472 		__set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
9473 	__set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
9474 	__set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
9475 	if (!rt2800_hwcrypt_disabled(rt2x00dev))
9476 		__set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
9477 	__set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
9478 	__set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
9479 	if (rt2x00_is_usb(rt2x00dev))
9480 		__set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
9481 	else {
9482 		__set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
9483 		__set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
9484 	}
9485 
9486 	/*
9487 	 * Set the rssi offset.
9488 	 */
9489 	rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
9490 
9491 	return 0;
9492 }
9493 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
9494 
9495 /*
9496  * IEEE80211 stack callback functions.
9497  */
9498 void rt2800_get_key_seq(struct ieee80211_hw *hw,
9499 			struct ieee80211_key_conf *key,
9500 			struct ieee80211_key_seq *seq)
9501 {
9502 	struct rt2x00_dev *rt2x00dev = hw->priv;
9503 	struct mac_iveiv_entry iveiv_entry;
9504 	u32 offset;
9505 
9506 	if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
9507 		return;
9508 
9509 	offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
9510 	rt2800_register_multiread(rt2x00dev, offset,
9511 				      &iveiv_entry, sizeof(iveiv_entry));
9512 
9513 	memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
9514 	memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
9515 }
9516 EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
9517 
9518 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
9519 {
9520 	struct rt2x00_dev *rt2x00dev = hw->priv;
9521 	u32 reg;
9522 	bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
9523 
9524 	reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
9525 	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
9526 	rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
9527 
9528 	reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
9529 	rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
9530 	rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
9531 
9532 	reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
9533 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
9534 	rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
9535 
9536 	reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
9537 	rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
9538 	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
9539 
9540 	reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
9541 	rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
9542 	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
9543 
9544 	reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
9545 	rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
9546 	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
9547 
9548 	reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
9549 	rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
9550 	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
9551 
9552 	return 0;
9553 }
9554 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
9555 
9556 int rt2800_conf_tx(struct ieee80211_hw *hw,
9557 		   struct ieee80211_vif *vif, u16 queue_idx,
9558 		   const struct ieee80211_tx_queue_params *params)
9559 {
9560 	struct rt2x00_dev *rt2x00dev = hw->priv;
9561 	struct data_queue *queue;
9562 	struct rt2x00_field32 field;
9563 	int retval;
9564 	u32 reg;
9565 	u32 offset;
9566 
9567 	/*
9568 	 * First pass the configuration through rt2x00lib, that will
9569 	 * update the queue settings and validate the input. After that
9570 	 * we are free to update the registers based on the value
9571 	 * in the queue parameter.
9572 	 */
9573 	retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
9574 	if (retval)
9575 		return retval;
9576 
9577 	/*
9578 	 * We only need to perform additional register initialization
9579 	 * for WMM queues/
9580 	 */
9581 	if (queue_idx >= 4)
9582 		return 0;
9583 
9584 	queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
9585 
9586 	/* Update WMM TXOP register */
9587 	offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
9588 	field.bit_offset = (queue_idx & 1) * 16;
9589 	field.bit_mask = 0xffff << field.bit_offset;
9590 
9591 	reg = rt2800_register_read(rt2x00dev, offset);
9592 	rt2x00_set_field32(&reg, field, queue->txop);
9593 	rt2800_register_write(rt2x00dev, offset, reg);
9594 
9595 	/* Update WMM registers */
9596 	field.bit_offset = queue_idx * 4;
9597 	field.bit_mask = 0xf << field.bit_offset;
9598 
9599 	reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG);
9600 	rt2x00_set_field32(&reg, field, queue->aifs);
9601 	rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
9602 
9603 	reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG);
9604 	rt2x00_set_field32(&reg, field, queue->cw_min);
9605 	rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
9606 
9607 	reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG);
9608 	rt2x00_set_field32(&reg, field, queue->cw_max);
9609 	rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
9610 
9611 	/* Update EDCA registers */
9612 	offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
9613 
9614 	reg = rt2800_register_read(rt2x00dev, offset);
9615 	rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
9616 	rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
9617 	rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
9618 	rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
9619 	rt2800_register_write(rt2x00dev, offset, reg);
9620 
9621 	return 0;
9622 }
9623 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
9624 
9625 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
9626 {
9627 	struct rt2x00_dev *rt2x00dev = hw->priv;
9628 	u64 tsf;
9629 	u32 reg;
9630 
9631 	reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1);
9632 	tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
9633 	reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0);
9634 	tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
9635 
9636 	return tsf;
9637 }
9638 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
9639 
9640 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
9641 			struct ieee80211_ampdu_params *params)
9642 {
9643 	struct ieee80211_sta *sta = params->sta;
9644 	enum ieee80211_ampdu_mlme_action action = params->action;
9645 	u16 tid = params->tid;
9646 	struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
9647 	int ret = 0;
9648 
9649 	/*
9650 	 * Don't allow aggregation for stations the hardware isn't aware
9651 	 * of because tx status reports for frames to an unknown station
9652 	 * always contain wcid=WCID_END+1 and thus we can't distinguish
9653 	 * between multiple stations which leads to unwanted situations
9654 	 * when the hw reorders frames due to aggregation.
9655 	 */
9656 	if (sta_priv->wcid > WCID_END)
9657 		return 1;
9658 
9659 	switch (action) {
9660 	case IEEE80211_AMPDU_RX_START:
9661 	case IEEE80211_AMPDU_RX_STOP:
9662 		/*
9663 		 * The hw itself takes care of setting up BlockAck mechanisms.
9664 		 * So, we only have to allow mac80211 to nagotiate a BlockAck
9665 		 * agreement. Once that is done, the hw will BlockAck incoming
9666 		 * AMPDUs without further setup.
9667 		 */
9668 		break;
9669 	case IEEE80211_AMPDU_TX_START:
9670 		ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
9671 		break;
9672 	case IEEE80211_AMPDU_TX_STOP_CONT:
9673 	case IEEE80211_AMPDU_TX_STOP_FLUSH:
9674 	case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
9675 		ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
9676 		break;
9677 	case IEEE80211_AMPDU_TX_OPERATIONAL:
9678 		break;
9679 	default:
9680 		rt2x00_warn((struct rt2x00_dev *)hw->priv,
9681 			    "Unknown AMPDU action\n");
9682 	}
9683 
9684 	return ret;
9685 }
9686 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
9687 
9688 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
9689 		      struct survey_info *survey)
9690 {
9691 	struct rt2x00_dev *rt2x00dev = hw->priv;
9692 	struct ieee80211_conf *conf = &hw->conf;
9693 	u32 idle, busy, busy_ext;
9694 
9695 	if (idx != 0)
9696 		return -ENOENT;
9697 
9698 	survey->channel = conf->chandef.chan;
9699 
9700 	idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
9701 	busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
9702 	busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
9703 
9704 	if (idle || busy) {
9705 		survey->filled = SURVEY_INFO_TIME |
9706 				 SURVEY_INFO_TIME_BUSY |
9707 				 SURVEY_INFO_TIME_EXT_BUSY;
9708 
9709 		survey->time = (idle + busy) / 1000;
9710 		survey->time_busy = busy / 1000;
9711 		survey->time_ext_busy = busy_ext / 1000;
9712 	}
9713 
9714 	if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
9715 		survey->filled |= SURVEY_INFO_IN_USE;
9716 
9717 	return 0;
9718 
9719 }
9720 EXPORT_SYMBOL_GPL(rt2800_get_survey);
9721 
9722 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
9723 MODULE_VERSION(DRV_VERSION);
9724 MODULE_DESCRIPTION("Ralink RT2800 library");
9725 MODULE_LICENSE("GPL");
9726