1 /* 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> 6 7 Based on the original rt2800pci.c and rt2800usb.c. 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 14 <http://rt2x00.serialmonkey.com> 15 16 This program is free software; you can redistribute it and/or modify 17 it under the terms of the GNU General Public License as published by 18 the Free Software Foundation; either version 2 of the License, or 19 (at your option) any later version. 20 21 This program is distributed in the hope that it will be useful, 22 but WITHOUT ANY WARRANTY; without even the implied warranty of 23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 GNU General Public License for more details. 25 26 You should have received a copy of the GNU General Public License 27 along with this program; if not, see <http://www.gnu.org/licenses/>. 28 */ 29 30 /* 31 Module: rt2800lib 32 Abstract: rt2800 generic device routines. 33 */ 34 35 #include <linux/crc-ccitt.h> 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/slab.h> 39 40 #include "rt2x00.h" 41 #include "rt2800lib.h" 42 #include "rt2800.h" 43 44 /* 45 * Register access. 46 * All access to the CSR registers will go through the methods 47 * rt2800_register_read and rt2800_register_write. 48 * BBP and RF register require indirect register access, 49 * and use the CSR registers BBPCSR and RFCSR to achieve this. 50 * These indirect registers work with busy bits, 51 * and we will try maximal REGISTER_BUSY_COUNT times to access 52 * the register while taking a REGISTER_BUSY_DELAY us delay 53 * between each attampt. When the busy bit is still set at that time, 54 * the access attempt is considered to have failed, 55 * and we will print an error. 56 * The _lock versions must be used if you already hold the csr_mutex 57 */ 58 #define WAIT_FOR_BBP(__dev, __reg) \ 59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) 60 #define WAIT_FOR_RFCSR(__dev, __reg) \ 61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) 62 #define WAIT_FOR_RF(__dev, __reg) \ 63 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) 64 #define WAIT_FOR_MCU(__dev, __reg) \ 65 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 66 H2M_MAILBOX_CSR_OWNER, (__reg)) 67 68 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) 69 { 70 /* check for rt2872 on SoC */ 71 if (!rt2x00_is_soc(rt2x00dev) || 72 !rt2x00_rt(rt2x00dev, RT2872)) 73 return false; 74 75 /* we know for sure that these rf chipsets are used on rt305x boards */ 76 if (rt2x00_rf(rt2x00dev, RF3020) || 77 rt2x00_rf(rt2x00dev, RF3021) || 78 rt2x00_rf(rt2x00dev, RF3022)) 79 return true; 80 81 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n"); 82 return false; 83 } 84 85 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, 86 const unsigned int word, const u8 value) 87 { 88 u32 reg; 89 90 mutex_lock(&rt2x00dev->csr_mutex); 91 92 /* 93 * Wait until the BBP becomes available, afterwards we 94 * can safely write the new data into the register. 95 */ 96 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 97 reg = 0; 98 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); 99 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 100 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 101 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); 102 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 103 104 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 105 } 106 107 mutex_unlock(&rt2x00dev->csr_mutex); 108 } 109 110 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, 111 const unsigned int word, u8 *value) 112 { 113 u32 reg; 114 115 mutex_lock(&rt2x00dev->csr_mutex); 116 117 /* 118 * Wait until the BBP becomes available, afterwards we 119 * can safely write the read request into the register. 120 * After the data has been written, we wait until hardware 121 * returns the correct value, if at any time the register 122 * doesn't become available in time, reg will be 0xffffffff 123 * which means we return 0xff to the caller. 124 */ 125 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 126 reg = 0; 127 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 128 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 129 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); 130 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 131 132 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 133 134 WAIT_FOR_BBP(rt2x00dev, ®); 135 } 136 137 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); 138 139 mutex_unlock(&rt2x00dev->csr_mutex); 140 } 141 142 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, 143 const unsigned int word, const u8 value) 144 { 145 u32 reg; 146 147 mutex_lock(&rt2x00dev->csr_mutex); 148 149 /* 150 * Wait until the RFCSR becomes available, afterwards we 151 * can safely write the new data into the register. 152 */ 153 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 154 reg = 0; 155 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); 156 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 157 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); 158 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 159 160 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 161 } 162 163 mutex_unlock(&rt2x00dev->csr_mutex); 164 } 165 166 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, 167 const unsigned int word, u8 *value) 168 { 169 u32 reg; 170 171 mutex_lock(&rt2x00dev->csr_mutex); 172 173 /* 174 * Wait until the RFCSR becomes available, afterwards we 175 * can safely write the read request into the register. 176 * After the data has been written, we wait until hardware 177 * returns the correct value, if at any time the register 178 * doesn't become available in time, reg will be 0xffffffff 179 * which means we return 0xff to the caller. 180 */ 181 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 182 reg = 0; 183 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 184 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); 185 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 186 187 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 188 189 WAIT_FOR_RFCSR(rt2x00dev, ®); 190 } 191 192 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); 193 194 mutex_unlock(&rt2x00dev->csr_mutex); 195 } 196 197 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, 198 const unsigned int word, const u32 value) 199 { 200 u32 reg; 201 202 mutex_lock(&rt2x00dev->csr_mutex); 203 204 /* 205 * Wait until the RF becomes available, afterwards we 206 * can safely write the new data into the register. 207 */ 208 if (WAIT_FOR_RF(rt2x00dev, ®)) { 209 reg = 0; 210 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); 211 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); 212 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); 213 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); 214 215 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); 216 rt2x00_rf_write(rt2x00dev, word, value); 217 } 218 219 mutex_unlock(&rt2x00dev->csr_mutex); 220 } 221 222 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { 223 [EEPROM_CHIP_ID] = 0x0000, 224 [EEPROM_VERSION] = 0x0001, 225 [EEPROM_MAC_ADDR_0] = 0x0002, 226 [EEPROM_MAC_ADDR_1] = 0x0003, 227 [EEPROM_MAC_ADDR_2] = 0x0004, 228 [EEPROM_NIC_CONF0] = 0x001a, 229 [EEPROM_NIC_CONF1] = 0x001b, 230 [EEPROM_FREQ] = 0x001d, 231 [EEPROM_LED_AG_CONF] = 0x001e, 232 [EEPROM_LED_ACT_CONF] = 0x001f, 233 [EEPROM_LED_POLARITY] = 0x0020, 234 [EEPROM_NIC_CONF2] = 0x0021, 235 [EEPROM_LNA] = 0x0022, 236 [EEPROM_RSSI_BG] = 0x0023, 237 [EEPROM_RSSI_BG2] = 0x0024, 238 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */ 239 [EEPROM_RSSI_A] = 0x0025, 240 [EEPROM_RSSI_A2] = 0x0026, 241 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */ 242 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027, 243 [EEPROM_TXPOWER_DELTA] = 0x0028, 244 [EEPROM_TXPOWER_BG1] = 0x0029, 245 [EEPROM_TXPOWER_BG2] = 0x0030, 246 [EEPROM_TSSI_BOUND_BG1] = 0x0037, 247 [EEPROM_TSSI_BOUND_BG2] = 0x0038, 248 [EEPROM_TSSI_BOUND_BG3] = 0x0039, 249 [EEPROM_TSSI_BOUND_BG4] = 0x003a, 250 [EEPROM_TSSI_BOUND_BG5] = 0x003b, 251 [EEPROM_TXPOWER_A1] = 0x003c, 252 [EEPROM_TXPOWER_A2] = 0x0053, 253 [EEPROM_TSSI_BOUND_A1] = 0x006a, 254 [EEPROM_TSSI_BOUND_A2] = 0x006b, 255 [EEPROM_TSSI_BOUND_A3] = 0x006c, 256 [EEPROM_TSSI_BOUND_A4] = 0x006d, 257 [EEPROM_TSSI_BOUND_A5] = 0x006e, 258 [EEPROM_TXPOWER_BYRATE] = 0x006f, 259 [EEPROM_BBP_START] = 0x0078, 260 }; 261 262 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = { 263 [EEPROM_CHIP_ID] = 0x0000, 264 [EEPROM_VERSION] = 0x0001, 265 [EEPROM_MAC_ADDR_0] = 0x0002, 266 [EEPROM_MAC_ADDR_1] = 0x0003, 267 [EEPROM_MAC_ADDR_2] = 0x0004, 268 [EEPROM_NIC_CONF0] = 0x001a, 269 [EEPROM_NIC_CONF1] = 0x001b, 270 [EEPROM_NIC_CONF2] = 0x001c, 271 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020, 272 [EEPROM_FREQ] = 0x0022, 273 [EEPROM_LED_AG_CONF] = 0x0023, 274 [EEPROM_LED_ACT_CONF] = 0x0024, 275 [EEPROM_LED_POLARITY] = 0x0025, 276 [EEPROM_LNA] = 0x0026, 277 [EEPROM_EXT_LNA2] = 0x0027, 278 [EEPROM_RSSI_BG] = 0x0028, 279 [EEPROM_RSSI_BG2] = 0x0029, 280 [EEPROM_RSSI_A] = 0x002a, 281 [EEPROM_RSSI_A2] = 0x002b, 282 [EEPROM_TXPOWER_BG1] = 0x0030, 283 [EEPROM_TXPOWER_BG2] = 0x0037, 284 [EEPROM_EXT_TXPOWER_BG3] = 0x003e, 285 [EEPROM_TSSI_BOUND_BG1] = 0x0045, 286 [EEPROM_TSSI_BOUND_BG2] = 0x0046, 287 [EEPROM_TSSI_BOUND_BG3] = 0x0047, 288 [EEPROM_TSSI_BOUND_BG4] = 0x0048, 289 [EEPROM_TSSI_BOUND_BG5] = 0x0049, 290 [EEPROM_TXPOWER_A1] = 0x004b, 291 [EEPROM_TXPOWER_A2] = 0x0065, 292 [EEPROM_EXT_TXPOWER_A3] = 0x007f, 293 [EEPROM_TSSI_BOUND_A1] = 0x009a, 294 [EEPROM_TSSI_BOUND_A2] = 0x009b, 295 [EEPROM_TSSI_BOUND_A3] = 0x009c, 296 [EEPROM_TSSI_BOUND_A4] = 0x009d, 297 [EEPROM_TSSI_BOUND_A5] = 0x009e, 298 [EEPROM_TXPOWER_BYRATE] = 0x00a0, 299 }; 300 301 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev, 302 const enum rt2800_eeprom_word word) 303 { 304 const unsigned int *map; 305 unsigned int index; 306 307 if (WARN_ONCE(word >= EEPROM_WORD_COUNT, 308 "%s: invalid EEPROM word %d\n", 309 wiphy_name(rt2x00dev->hw->wiphy), word)) 310 return 0; 311 312 if (rt2x00_rt(rt2x00dev, RT3593)) 313 map = rt2800_eeprom_map_ext; 314 else 315 map = rt2800_eeprom_map; 316 317 index = map[word]; 318 319 /* Index 0 is valid only for EEPROM_CHIP_ID. 320 * Otherwise it means that the offset of the 321 * given word is not initialized in the map, 322 * or that the field is not usable on the 323 * actual chipset. 324 */ 325 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0, 326 "%s: invalid access of EEPROM word %d\n", 327 wiphy_name(rt2x00dev->hw->wiphy), word); 328 329 return index; 330 } 331 332 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev, 333 const enum rt2800_eeprom_word word) 334 { 335 unsigned int index; 336 337 index = rt2800_eeprom_word_index(rt2x00dev, word); 338 return rt2x00_eeprom_addr(rt2x00dev, index); 339 } 340 341 static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, 342 const enum rt2800_eeprom_word word, u16 *data) 343 { 344 unsigned int index; 345 346 index = rt2800_eeprom_word_index(rt2x00dev, word); 347 rt2x00_eeprom_read(rt2x00dev, index, data); 348 } 349 350 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, 351 const enum rt2800_eeprom_word word, u16 data) 352 { 353 unsigned int index; 354 355 index = rt2800_eeprom_word_index(rt2x00dev, word); 356 rt2x00_eeprom_write(rt2x00dev, index, data); 357 } 358 359 static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, 360 const enum rt2800_eeprom_word array, 361 unsigned int offset, 362 u16 *data) 363 { 364 unsigned int index; 365 366 index = rt2800_eeprom_word_index(rt2x00dev, array); 367 rt2x00_eeprom_read(rt2x00dev, index + offset, data); 368 } 369 370 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) 371 { 372 u32 reg; 373 int i, count; 374 375 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); 376 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); 377 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); 378 rt2x00_set_field32(®, WLAN_CLK_EN, 0); 379 rt2x00_set_field32(®, WLAN_EN, 1); 380 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 381 382 udelay(REGISTER_BUSY_DELAY); 383 384 count = 0; 385 do { 386 /* 387 * Check PLL_LD & XTAL_RDY. 388 */ 389 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 390 rt2800_register_read(rt2x00dev, CMB_CTRL, ®); 391 if (rt2x00_get_field32(reg, PLL_LD) && 392 rt2x00_get_field32(reg, XTAL_RDY)) 393 break; 394 udelay(REGISTER_BUSY_DELAY); 395 } 396 397 if (i >= REGISTER_BUSY_COUNT) { 398 399 if (count >= 10) 400 return -EIO; 401 402 rt2800_register_write(rt2x00dev, 0x58, 0x018); 403 udelay(REGISTER_BUSY_DELAY); 404 rt2800_register_write(rt2x00dev, 0x58, 0x418); 405 udelay(REGISTER_BUSY_DELAY); 406 rt2800_register_write(rt2x00dev, 0x58, 0x618); 407 udelay(REGISTER_BUSY_DELAY); 408 count++; 409 } else { 410 count = 0; 411 } 412 413 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); 414 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); 415 rt2x00_set_field32(®, WLAN_CLK_EN, 1); 416 rt2x00_set_field32(®, WLAN_RESET, 1); 417 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 418 udelay(10); 419 rt2x00_set_field32(®, WLAN_RESET, 0); 420 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 421 udelay(10); 422 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff); 423 } while (count != 0); 424 425 return 0; 426 } 427 428 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 429 const u8 command, const u8 token, 430 const u8 arg0, const u8 arg1) 431 { 432 u32 reg; 433 434 /* 435 * SOC devices don't support MCU requests. 436 */ 437 if (rt2x00_is_soc(rt2x00dev)) 438 return; 439 440 mutex_lock(&rt2x00dev->csr_mutex); 441 442 /* 443 * Wait until the MCU becomes available, afterwards we 444 * can safely write the new data into the register. 445 */ 446 if (WAIT_FOR_MCU(rt2x00dev, ®)) { 447 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); 448 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); 449 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); 450 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); 451 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); 452 453 reg = 0; 454 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); 455 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); 456 } 457 458 mutex_unlock(&rt2x00dev->csr_mutex); 459 } 460 EXPORT_SYMBOL_GPL(rt2800_mcu_request); 461 462 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) 463 { 464 unsigned int i = 0; 465 u32 reg; 466 467 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 468 rt2800_register_read(rt2x00dev, MAC_CSR0, ®); 469 if (reg && reg != ~0) 470 return 0; 471 msleep(1); 472 } 473 474 rt2x00_err(rt2x00dev, "Unstable hardware\n"); 475 return -EBUSY; 476 } 477 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); 478 479 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 480 { 481 unsigned int i; 482 u32 reg; 483 484 /* 485 * Some devices are really slow to respond here. Wait a whole second 486 * before timing out. 487 */ 488 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 489 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); 490 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 491 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 492 return 0; 493 494 msleep(10); 495 } 496 497 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); 498 return -EACCES; 499 } 500 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); 501 502 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) 503 { 504 u32 reg; 505 506 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); 507 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 508 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 509 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 510 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 511 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 512 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 513 } 514 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma); 515 516 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev, 517 unsigned short *txwi_size, 518 unsigned short *rxwi_size) 519 { 520 switch (rt2x00dev->chip.rt) { 521 case RT3593: 522 *txwi_size = TXWI_DESC_SIZE_4WORDS; 523 *rxwi_size = RXWI_DESC_SIZE_5WORDS; 524 break; 525 526 case RT5592: 527 *txwi_size = TXWI_DESC_SIZE_5WORDS; 528 *rxwi_size = RXWI_DESC_SIZE_6WORDS; 529 break; 530 531 default: 532 *txwi_size = TXWI_DESC_SIZE_4WORDS; 533 *rxwi_size = RXWI_DESC_SIZE_4WORDS; 534 break; 535 } 536 } 537 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size); 538 539 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) 540 { 541 u16 fw_crc; 542 u16 crc; 543 544 /* 545 * The last 2 bytes in the firmware array are the crc checksum itself, 546 * this means that we should never pass those 2 bytes to the crc 547 * algorithm. 548 */ 549 fw_crc = (data[len - 2] << 8 | data[len - 1]); 550 551 /* 552 * Use the crc ccitt algorithm. 553 * This will return the same value as the legacy driver which 554 * used bit ordering reversion on the both the firmware bytes 555 * before input input as well as on the final output. 556 * Obviously using crc ccitt directly is much more efficient. 557 */ 558 crc = crc_ccitt(~0, data, len - 2); 559 560 /* 561 * There is a small difference between the crc-itu-t + bitrev and 562 * the crc-ccitt crc calculation. In the latter method the 2 bytes 563 * will be swapped, use swab16 to convert the crc to the correct 564 * value. 565 */ 566 crc = swab16(crc); 567 568 return fw_crc == crc; 569 } 570 571 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, 572 const u8 *data, const size_t len) 573 { 574 size_t offset = 0; 575 size_t fw_len; 576 bool multiple; 577 578 /* 579 * PCI(e) & SOC devices require firmware with a length 580 * of 8kb. USB devices require firmware files with a length 581 * of 4kb. Certain USB chipsets however require different firmware, 582 * which Ralink only provides attached to the original firmware 583 * file. Thus for USB devices, firmware files have a length 584 * which is a multiple of 4kb. The firmware for rt3290 chip also 585 * have a length which is a multiple of 4kb. 586 */ 587 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290)) 588 fw_len = 4096; 589 else 590 fw_len = 8192; 591 592 multiple = true; 593 /* 594 * Validate the firmware length 595 */ 596 if (len != fw_len && (!multiple || (len % fw_len) != 0)) 597 return FW_BAD_LENGTH; 598 599 /* 600 * Check if the chipset requires one of the upper parts 601 * of the firmware. 602 */ 603 if (rt2x00_is_usb(rt2x00dev) && 604 !rt2x00_rt(rt2x00dev, RT2860) && 605 !rt2x00_rt(rt2x00dev, RT2872) && 606 !rt2x00_rt(rt2x00dev, RT3070) && 607 ((len / fw_len) == 1)) 608 return FW_BAD_VERSION; 609 610 /* 611 * 8kb firmware files must be checked as if it were 612 * 2 separate firmware files. 613 */ 614 while (offset < len) { 615 if (!rt2800_check_firmware_crc(data + offset, fw_len)) 616 return FW_BAD_CRC; 617 618 offset += fw_len; 619 } 620 621 return FW_OK; 622 } 623 EXPORT_SYMBOL_GPL(rt2800_check_firmware); 624 625 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, 626 const u8 *data, const size_t len) 627 { 628 unsigned int i; 629 u32 reg; 630 int retval; 631 632 if (rt2x00_rt(rt2x00dev, RT3290)) { 633 retval = rt2800_enable_wlan_rt3290(rt2x00dev); 634 if (retval) 635 return -EBUSY; 636 } 637 638 /* 639 * If driver doesn't wake up firmware here, 640 * rt2800_load_firmware will hang forever when interface is up again. 641 */ 642 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 643 644 /* 645 * Wait for stable hardware. 646 */ 647 if (rt2800_wait_csr_ready(rt2x00dev)) 648 return -EBUSY; 649 650 if (rt2x00_is_pci(rt2x00dev)) { 651 if (rt2x00_rt(rt2x00dev, RT3290) || 652 rt2x00_rt(rt2x00dev, RT3572) || 653 rt2x00_rt(rt2x00dev, RT5390) || 654 rt2x00_rt(rt2x00dev, RT5392)) { 655 rt2800_register_read(rt2x00dev, AUX_CTRL, ®); 656 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); 657 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); 658 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); 659 } 660 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 661 } 662 663 rt2800_disable_wpdma(rt2x00dev); 664 665 /* 666 * Write firmware to the device. 667 */ 668 rt2800_drv_write_firmware(rt2x00dev, data, len); 669 670 /* 671 * Wait for device to stabilize. 672 */ 673 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 674 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®); 675 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 676 break; 677 msleep(1); 678 } 679 680 if (i == REGISTER_BUSY_COUNT) { 681 rt2x00_err(rt2x00dev, "PBF system register not ready\n"); 682 return -EBUSY; 683 } 684 685 /* 686 * Disable DMA, will be reenabled later when enabling 687 * the radio. 688 */ 689 rt2800_disable_wpdma(rt2x00dev); 690 691 /* 692 * Initialize firmware. 693 */ 694 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 695 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 696 if (rt2x00_is_usb(rt2x00dev)) { 697 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 698 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 699 } 700 msleep(1); 701 702 return 0; 703 } 704 EXPORT_SYMBOL_GPL(rt2800_load_firmware); 705 706 void rt2800_write_tx_data(struct queue_entry *entry, 707 struct txentry_desc *txdesc) 708 { 709 __le32 *txwi = rt2800_drv_get_txwi(entry); 710 u32 word; 711 int i; 712 713 /* 714 * Initialize TX Info descriptor 715 */ 716 rt2x00_desc_read(txwi, 0, &word); 717 rt2x00_set_field32(&word, TXWI_W0_FRAG, 718 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 719 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 720 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); 721 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); 722 rt2x00_set_field32(&word, TXWI_W0_TS, 723 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 724 rt2x00_set_field32(&word, TXWI_W0_AMPDU, 725 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); 726 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, 727 txdesc->u.ht.mpdu_density); 728 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); 729 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); 730 rt2x00_set_field32(&word, TXWI_W0_BW, 731 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); 732 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, 733 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); 734 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); 735 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); 736 rt2x00_desc_write(txwi, 0, word); 737 738 rt2x00_desc_read(txwi, 1, &word); 739 rt2x00_set_field32(&word, TXWI_W1_ACK, 740 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 741 rt2x00_set_field32(&word, TXWI_W1_NSEQ, 742 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 743 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); 744 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 745 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 746 txdesc->key_idx : txdesc->u.ht.wcid); 747 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 748 txdesc->length); 749 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); 750 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); 751 rt2x00_desc_write(txwi, 1, word); 752 753 /* 754 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert 755 * the IV from the IVEIV register when TXD_W3_WIV is set to 0. 756 * When TXD_W3_WIV is set to 1 it will use the IV data 757 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 758 * crypto entry in the registers should be used to encrypt the frame. 759 * 760 * Nulify all remaining words as well, we don't know how to program them. 761 */ 762 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++) 763 _rt2x00_desc_write(txwi, i, 0); 764 } 765 EXPORT_SYMBOL_GPL(rt2800_write_tx_data); 766 767 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) 768 { 769 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); 770 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); 771 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); 772 u16 eeprom; 773 u8 offset0; 774 u8 offset1; 775 u8 offset2; 776 777 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 778 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom); 779 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); 780 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); 781 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); 782 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); 783 } else { 784 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom); 785 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); 786 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); 787 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); 788 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); 789 } 790 791 /* 792 * Convert the value from the descriptor into the RSSI value 793 * If the value in the descriptor is 0, it is considered invalid 794 * and the default (extremely low) rssi value is assumed 795 */ 796 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128; 797 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128; 798 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128; 799 800 /* 801 * mac80211 only accepts a single RSSI value. Calculating the 802 * average doesn't deliver a fair answer either since -60:-60 would 803 * be considered equally good as -50:-70 while the second is the one 804 * which gives less energy... 805 */ 806 rssi0 = max(rssi0, rssi1); 807 return (int)max(rssi0, rssi2); 808 } 809 810 void rt2800_process_rxwi(struct queue_entry *entry, 811 struct rxdone_entry_desc *rxdesc) 812 { 813 __le32 *rxwi = (__le32 *) entry->skb->data; 814 u32 word; 815 816 rt2x00_desc_read(rxwi, 0, &word); 817 818 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); 819 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); 820 821 rt2x00_desc_read(rxwi, 1, &word); 822 823 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) 824 rxdesc->flags |= RX_FLAG_SHORT_GI; 825 826 if (rt2x00_get_field32(word, RXWI_W1_BW)) 827 rxdesc->flags |= RX_FLAG_40MHZ; 828 829 /* 830 * Detect RX rate, always use MCS as signal type. 831 */ 832 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; 833 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); 834 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); 835 836 /* 837 * Mask of 0x8 bit to remove the short preamble flag. 838 */ 839 if (rxdesc->rate_mode == RATE_MODE_CCK) 840 rxdesc->signal &= ~0x8; 841 842 rt2x00_desc_read(rxwi, 2, &word); 843 844 /* 845 * Convert descriptor AGC value to RSSI value. 846 */ 847 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); 848 /* 849 * Remove RXWI descriptor from start of the buffer. 850 */ 851 skb_pull(entry->skb, entry->queue->winfo_size); 852 } 853 EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 854 855 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi) 856 { 857 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 858 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 859 struct txdone_entry_desc txdesc; 860 u32 word; 861 u16 mcs, real_mcs; 862 int aggr, ampdu; 863 864 /* 865 * Obtain the status about this packet. 866 */ 867 txdesc.flags = 0; 868 rt2x00_desc_read(txwi, 0, &word); 869 870 mcs = rt2x00_get_field32(word, TXWI_W0_MCS); 871 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); 872 873 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 874 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); 875 876 /* 877 * If a frame was meant to be sent as a single non-aggregated MPDU 878 * but ended up in an aggregate the used tx rate doesn't correlate 879 * with the one specified in the TXWI as the whole aggregate is sent 880 * with the same rate. 881 * 882 * For example: two frames are sent to rt2x00, the first one sets 883 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 884 * and requests MCS15. If the hw aggregates both frames into one 885 * AMDPU the tx status for both frames will contain MCS7 although 886 * the frame was sent successfully. 887 * 888 * Hence, replace the requested rate with the real tx rate to not 889 * confuse the rate control algortihm by providing clearly wrong 890 * data. 891 */ 892 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) { 893 skbdesc->tx_rate_idx = real_mcs; 894 mcs = real_mcs; 895 } 896 897 if (aggr == 1 || ampdu == 1) 898 __set_bit(TXDONE_AMPDU, &txdesc.flags); 899 900 /* 901 * Ralink has a retry mechanism using a global fallback 902 * table. We setup this fallback table to try the immediate 903 * lower rate for all rates. In the TX_STA_FIFO, the MCS field 904 * always contains the MCS used for the last transmission, be 905 * it successful or not. 906 */ 907 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { 908 /* 909 * Transmission succeeded. The number of retries is 910 * mcs - real_mcs 911 */ 912 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 913 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); 914 } else { 915 /* 916 * Transmission failed. The number of retries is 917 * always 7 in this case (for a total number of 8 918 * frames sent). 919 */ 920 __set_bit(TXDONE_FAILURE, &txdesc.flags); 921 txdesc.retry = rt2x00dev->long_retry; 922 } 923 924 /* 925 * the frame was retried at least once 926 * -> hw used fallback rates 927 */ 928 if (txdesc.retry) 929 __set_bit(TXDONE_FALLBACK, &txdesc.flags); 930 931 rt2x00lib_txdone(entry, &txdesc); 932 } 933 EXPORT_SYMBOL_GPL(rt2800_txdone_entry); 934 935 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev, 936 unsigned int index) 937 { 938 return HW_BEACON_BASE(index); 939 } 940 941 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev, 942 unsigned int index) 943 { 944 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index)); 945 } 946 947 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev) 948 { 949 struct data_queue *queue = rt2x00dev->bcn; 950 struct queue_entry *entry; 951 int i, bcn_num = 0; 952 u64 off, reg = 0; 953 u32 bssid_dw1; 954 955 /* 956 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers. 957 */ 958 for (i = 0; i < queue->limit; i++) { 959 entry = &queue->entries[i]; 960 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags)) 961 continue; 962 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx); 963 reg |= off << (8 * bcn_num); 964 bcn_num++; 965 } 966 967 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); 968 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); 969 970 /* 971 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons. 972 */ 973 rt2800_register_read(rt2x00dev, MAC_BSSID_DW1, &bssid_dw1); 974 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, 975 bcn_num > 0 ? bcn_num - 1 : 0); 976 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1); 977 } 978 979 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) 980 { 981 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 982 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 983 unsigned int beacon_base; 984 unsigned int padding_len; 985 u32 orig_reg, reg; 986 const int txwi_desc_size = entry->queue->winfo_size; 987 988 /* 989 * Disable beaconing while we are reloading the beacon data, 990 * otherwise we might be sending out invalid data. 991 */ 992 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); 993 orig_reg = reg; 994 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 995 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 996 997 /* 998 * Add space for the TXWI in front of the skb. 999 */ 1000 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size); 1001 1002 /* 1003 * Register descriptor details in skb frame descriptor. 1004 */ 1005 skbdesc->flags |= SKBDESC_DESC_IN_SKB; 1006 skbdesc->desc = entry->skb->data; 1007 skbdesc->desc_len = txwi_desc_size; 1008 1009 /* 1010 * Add the TXWI for the beacon to the skb. 1011 */ 1012 rt2800_write_tx_data(entry, txdesc); 1013 1014 /* 1015 * Dump beacon to userspace through debugfs. 1016 */ 1017 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); 1018 1019 /* 1020 * Write entire beacon with TXWI and padding to register. 1021 */ 1022 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 1023 if (padding_len && skb_pad(entry->skb, padding_len)) { 1024 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); 1025 /* skb freed by skb_pad() on failure */ 1026 entry->skb = NULL; 1027 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1028 return; 1029 } 1030 1031 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx); 1032 1033 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, 1034 entry->skb->len + padding_len); 1035 __set_bit(ENTRY_BCN_ENABLED, &entry->flags); 1036 1037 /* 1038 * Change global beacons settings. 1039 */ 1040 rt2800_update_beacons_setup(rt2x00dev); 1041 1042 /* 1043 * Restore beaconing state. 1044 */ 1045 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1046 1047 /* 1048 * Clean up beacon skb. 1049 */ 1050 dev_kfree_skb_any(entry->skb); 1051 entry->skb = NULL; 1052 } 1053 EXPORT_SYMBOL_GPL(rt2800_write_beacon); 1054 1055 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, 1056 unsigned int index) 1057 { 1058 int i; 1059 const int txwi_desc_size = rt2x00dev->bcn->winfo_size; 1060 unsigned int beacon_base; 1061 1062 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index); 1063 1064 /* 1065 * For the Beacon base registers we only need to clear 1066 * the whole TXWI which (when set to 0) will invalidate 1067 * the entire beacon. 1068 */ 1069 for (i = 0; i < txwi_desc_size; i += sizeof(__le32)) 1070 rt2800_register_write(rt2x00dev, beacon_base + i, 0); 1071 } 1072 1073 void rt2800_clear_beacon(struct queue_entry *entry) 1074 { 1075 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1076 u32 orig_reg, reg; 1077 1078 /* 1079 * Disable beaconing while we are reloading the beacon data, 1080 * otherwise we might be sending out invalid data. 1081 */ 1082 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &orig_reg); 1083 reg = orig_reg; 1084 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1085 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1086 1087 /* 1088 * Clear beacon. 1089 */ 1090 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx); 1091 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags); 1092 1093 /* 1094 * Change global beacons settings. 1095 */ 1096 rt2800_update_beacons_setup(rt2x00dev); 1097 /* 1098 * Restore beaconing state. 1099 */ 1100 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1101 } 1102 EXPORT_SYMBOL_GPL(rt2800_clear_beacon); 1103 1104 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 1105 const struct rt2x00debug rt2800_rt2x00debug = { 1106 .owner = THIS_MODULE, 1107 .csr = { 1108 .read = rt2800_register_read, 1109 .write = rt2800_register_write, 1110 .flags = RT2X00DEBUGFS_OFFSET, 1111 .word_base = CSR_REG_BASE, 1112 .word_size = sizeof(u32), 1113 .word_count = CSR_REG_SIZE / sizeof(u32), 1114 }, 1115 .eeprom = { 1116 /* NOTE: The local EEPROM access functions can't 1117 * be used here, use the generic versions instead. 1118 */ 1119 .read = rt2x00_eeprom_read, 1120 .write = rt2x00_eeprom_write, 1121 .word_base = EEPROM_BASE, 1122 .word_size = sizeof(u16), 1123 .word_count = EEPROM_SIZE / sizeof(u16), 1124 }, 1125 .bbp = { 1126 .read = rt2800_bbp_read, 1127 .write = rt2800_bbp_write, 1128 .word_base = BBP_BASE, 1129 .word_size = sizeof(u8), 1130 .word_count = BBP_SIZE / sizeof(u8), 1131 }, 1132 .rf = { 1133 .read = rt2x00_rf_read, 1134 .write = rt2800_rf_write, 1135 .word_base = RF_BASE, 1136 .word_size = sizeof(u32), 1137 .word_count = RF_SIZE / sizeof(u32), 1138 }, 1139 .rfcsr = { 1140 .read = rt2800_rfcsr_read, 1141 .write = rt2800_rfcsr_write, 1142 .word_base = RFCSR_BASE, 1143 .word_size = sizeof(u8), 1144 .word_count = RFCSR_SIZE / sizeof(u8), 1145 }, 1146 }; 1147 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); 1148 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1149 1150 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) 1151 { 1152 u32 reg; 1153 1154 if (rt2x00_rt(rt2x00dev, RT3290)) { 1155 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); 1156 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); 1157 } else { 1158 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 1159 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); 1160 } 1161 } 1162 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 1163 1164 #ifdef CONFIG_RT2X00_LIB_LEDS 1165 static void rt2800_brightness_set(struct led_classdev *led_cdev, 1166 enum led_brightness brightness) 1167 { 1168 struct rt2x00_led *led = 1169 container_of(led_cdev, struct rt2x00_led, led_dev); 1170 unsigned int enabled = brightness != LED_OFF; 1171 unsigned int bg_mode = 1172 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); 1173 unsigned int polarity = 1174 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1175 EEPROM_FREQ_LED_POLARITY); 1176 unsigned int ledmode = 1177 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1178 EEPROM_FREQ_LED_MODE); 1179 u32 reg; 1180 1181 /* Check for SoC (SOC devices don't support MCU requests) */ 1182 if (rt2x00_is_soc(led->rt2x00dev)) { 1183 rt2800_register_read(led->rt2x00dev, LED_CFG, ®); 1184 1185 /* Set LED Polarity */ 1186 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); 1187 1188 /* Set LED Mode */ 1189 if (led->type == LED_TYPE_RADIO) { 1190 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 1191 enabled ? 3 : 0); 1192 } else if (led->type == LED_TYPE_ASSOC) { 1193 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 1194 enabled ? 3 : 0); 1195 } else if (led->type == LED_TYPE_QUALITY) { 1196 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 1197 enabled ? 3 : 0); 1198 } 1199 1200 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 1201 1202 } else { 1203 if (led->type == LED_TYPE_RADIO) { 1204 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1205 enabled ? 0x20 : 0); 1206 } else if (led->type == LED_TYPE_ASSOC) { 1207 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1208 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); 1209 } else if (led->type == LED_TYPE_QUALITY) { 1210 /* 1211 * The brightness is divided into 6 levels (0 - 5), 1212 * The specs tell us the following levels: 1213 * 0, 1 ,3, 7, 15, 31 1214 * to determine the level in a simple way we can simply 1215 * work with bitshifting: 1216 * (1 << level) - 1 1217 */ 1218 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 1219 (1 << brightness / (LED_FULL / 6)) - 1, 1220 polarity); 1221 } 1222 } 1223 } 1224 1225 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, 1226 struct rt2x00_led *led, enum led_type type) 1227 { 1228 led->rt2x00dev = rt2x00dev; 1229 led->type = type; 1230 led->led_dev.brightness_set = rt2800_brightness_set; 1231 led->flags = LED_INITIALIZED; 1232 } 1233 #endif /* CONFIG_RT2X00_LIB_LEDS */ 1234 1235 /* 1236 * Configuration handlers. 1237 */ 1238 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, 1239 const u8 *address, 1240 int wcid) 1241 { 1242 struct mac_wcid_entry wcid_entry; 1243 u32 offset; 1244 1245 offset = MAC_WCID_ENTRY(wcid); 1246 1247 memset(&wcid_entry, 0xff, sizeof(wcid_entry)); 1248 if (address) 1249 memcpy(wcid_entry.mac, address, ETH_ALEN); 1250 1251 rt2800_register_multiwrite(rt2x00dev, offset, 1252 &wcid_entry, sizeof(wcid_entry)); 1253 } 1254 1255 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) 1256 { 1257 u32 offset; 1258 offset = MAC_WCID_ATTR_ENTRY(wcid); 1259 rt2800_register_write(rt2x00dev, offset, 0); 1260 } 1261 1262 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, 1263 int wcid, u32 bssidx) 1264 { 1265 u32 offset = MAC_WCID_ATTR_ENTRY(wcid); 1266 u32 reg; 1267 1268 /* 1269 * The BSS Idx numbers is split in a main value of 3 bits, 1270 * and a extended field for adding one additional bit to the value. 1271 */ 1272 rt2800_register_read(rt2x00dev, offset, ®); 1273 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); 1274 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, 1275 (bssidx & 0x8) >> 3); 1276 rt2800_register_write(rt2x00dev, offset, reg); 1277 } 1278 1279 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, 1280 struct rt2x00lib_crypto *crypto, 1281 struct ieee80211_key_conf *key) 1282 { 1283 struct mac_iveiv_entry iveiv_entry; 1284 u32 offset; 1285 u32 reg; 1286 1287 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); 1288 1289 if (crypto->cmd == SET_KEY) { 1290 rt2800_register_read(rt2x00dev, offset, ®); 1291 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 1292 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 1293 /* 1294 * Both the cipher as the BSS Idx numbers are split in a main 1295 * value of 3 bits, and a extended field for adding one additional 1296 * bit to the value. 1297 */ 1298 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 1299 (crypto->cipher & 0x7)); 1300 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 1301 (crypto->cipher & 0x8) >> 3); 1302 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); 1303 rt2800_register_write(rt2x00dev, offset, reg); 1304 } else { 1305 /* Delete the cipher without touching the bssidx */ 1306 rt2800_register_read(rt2x00dev, offset, ®); 1307 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); 1308 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); 1309 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); 1310 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); 1311 rt2800_register_write(rt2x00dev, offset, reg); 1312 } 1313 1314 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 1315 1316 memset(&iveiv_entry, 0, sizeof(iveiv_entry)); 1317 if ((crypto->cipher == CIPHER_TKIP) || 1318 (crypto->cipher == CIPHER_TKIP_NO_MIC) || 1319 (crypto->cipher == CIPHER_AES)) 1320 iveiv_entry.iv[3] |= 0x20; 1321 iveiv_entry.iv[3] |= key->keyidx << 6; 1322 rt2800_register_multiwrite(rt2x00dev, offset, 1323 &iveiv_entry, sizeof(iveiv_entry)); 1324 } 1325 1326 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, 1327 struct rt2x00lib_crypto *crypto, 1328 struct ieee80211_key_conf *key) 1329 { 1330 struct hw_key_entry key_entry; 1331 struct rt2x00_field32 field; 1332 u32 offset; 1333 u32 reg; 1334 1335 if (crypto->cmd == SET_KEY) { 1336 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; 1337 1338 memcpy(key_entry.key, crypto->key, 1339 sizeof(key_entry.key)); 1340 memcpy(key_entry.tx_mic, crypto->tx_mic, 1341 sizeof(key_entry.tx_mic)); 1342 memcpy(key_entry.rx_mic, crypto->rx_mic, 1343 sizeof(key_entry.rx_mic)); 1344 1345 offset = SHARED_KEY_ENTRY(key->hw_key_idx); 1346 rt2800_register_multiwrite(rt2x00dev, offset, 1347 &key_entry, sizeof(key_entry)); 1348 } 1349 1350 /* 1351 * The cipher types are stored over multiple registers 1352 * starting with SHARED_KEY_MODE_BASE each word will have 1353 * 32 bits and contains the cipher types for 2 bssidx each. 1354 * Using the correct defines correctly will cause overhead, 1355 * so just calculate the correct offset. 1356 */ 1357 field.bit_offset = 4 * (key->hw_key_idx % 8); 1358 field.bit_mask = 0x7 << field.bit_offset; 1359 1360 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); 1361 1362 rt2800_register_read(rt2x00dev, offset, ®); 1363 rt2x00_set_field32(®, field, 1364 (crypto->cmd == SET_KEY) * crypto->cipher); 1365 rt2800_register_write(rt2x00dev, offset, reg); 1366 1367 /* 1368 * Update WCID information 1369 */ 1370 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); 1371 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, 1372 crypto->bssidx); 1373 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1374 1375 return 0; 1376 } 1377 EXPORT_SYMBOL_GPL(rt2800_config_shared_key); 1378 1379 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 1380 struct rt2x00lib_crypto *crypto, 1381 struct ieee80211_key_conf *key) 1382 { 1383 struct hw_key_entry key_entry; 1384 u32 offset; 1385 1386 if (crypto->cmd == SET_KEY) { 1387 /* 1388 * Allow key configuration only for STAs that are 1389 * known by the hw. 1390 */ 1391 if (crypto->wcid > WCID_END) 1392 return -ENOSPC; 1393 key->hw_key_idx = crypto->wcid; 1394 1395 memcpy(key_entry.key, crypto->key, 1396 sizeof(key_entry.key)); 1397 memcpy(key_entry.tx_mic, crypto->tx_mic, 1398 sizeof(key_entry.tx_mic)); 1399 memcpy(key_entry.rx_mic, crypto->rx_mic, 1400 sizeof(key_entry.rx_mic)); 1401 1402 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 1403 rt2800_register_multiwrite(rt2x00dev, offset, 1404 &key_entry, sizeof(key_entry)); 1405 } 1406 1407 /* 1408 * Update WCID information 1409 */ 1410 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1411 1412 return 0; 1413 } 1414 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); 1415 1416 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev) 1417 { 1418 u8 i, max_psdu; 1419 u32 reg; 1420 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1421 1422 for (i = 0; i < 3; i++) 1423 if (drv_data->ampdu_factor_cnt[i] > 0) 1424 break; 1425 1426 max_psdu = min(drv_data->max_psdu, i); 1427 1428 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®); 1429 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); 1430 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1431 } 1432 1433 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif, 1434 struct ieee80211_sta *sta) 1435 { 1436 int wcid; 1437 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1438 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1439 1440 /* 1441 * Limit global maximum TX AMPDU length to smallest value of all 1442 * connected stations. In AP mode this can be suboptimal, but we 1443 * do not have a choice if some connected STA is not capable to 1444 * receive the same amount of data like the others. 1445 */ 1446 if (sta->ht_cap.ht_supported) { 1447 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++; 1448 rt2800_set_max_psdu_len(rt2x00dev); 1449 } 1450 1451 /* 1452 * Search for the first free WCID entry and return the corresponding 1453 * index. 1454 */ 1455 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START; 1456 1457 /* 1458 * Store selected wcid even if it is invalid so that we can 1459 * later decide if the STA is uploaded into the hw. 1460 */ 1461 sta_priv->wcid = wcid; 1462 1463 /* 1464 * No space left in the device, however, we can still communicate 1465 * with the STA -> No error. 1466 */ 1467 if (wcid > WCID_END) 1468 return 0; 1469 1470 __set_bit(wcid - WCID_START, drv_data->sta_ids); 1471 1472 /* 1473 * Clean up WCID attributes and write STA address to the device. 1474 */ 1475 rt2800_delete_wcid_attr(rt2x00dev, wcid); 1476 rt2800_config_wcid(rt2x00dev, sta->addr, wcid); 1477 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, 1478 rt2x00lib_get_bssidx(rt2x00dev, vif)); 1479 return 0; 1480 } 1481 EXPORT_SYMBOL_GPL(rt2800_sta_add); 1482 1483 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, struct ieee80211_sta *sta) 1484 { 1485 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1486 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1487 int wcid = sta_priv->wcid; 1488 1489 if (sta->ht_cap.ht_supported) { 1490 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--; 1491 rt2800_set_max_psdu_len(rt2x00dev); 1492 } 1493 1494 if (wcid > WCID_END) 1495 return 0; 1496 /* 1497 * Remove WCID entry, no need to clean the attributes as they will 1498 * get renewed when the WCID is reused. 1499 */ 1500 rt2800_config_wcid(rt2x00dev, NULL, wcid); 1501 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1502 1503 return 0; 1504 } 1505 EXPORT_SYMBOL_GPL(rt2800_sta_remove); 1506 1507 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, 1508 const unsigned int filter_flags) 1509 { 1510 u32 reg; 1511 1512 /* 1513 * Start configuration steps. 1514 * Note that the version error will always be dropped 1515 * and broadcast frames will always be accepted since 1516 * there is no filter for it at this time. 1517 */ 1518 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®); 1519 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, 1520 !(filter_flags & FIF_FCSFAIL)); 1521 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, 1522 !(filter_flags & FIF_PLCPFAIL)); 1523 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, 1524 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); 1525 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); 1526 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); 1527 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, 1528 !(filter_flags & FIF_ALLMULTI)); 1529 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); 1530 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); 1531 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, 1532 !(filter_flags & FIF_CONTROL)); 1533 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, 1534 !(filter_flags & FIF_CONTROL)); 1535 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, 1536 !(filter_flags & FIF_CONTROL)); 1537 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, 1538 !(filter_flags & FIF_CONTROL)); 1539 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, 1540 !(filter_flags & FIF_CONTROL)); 1541 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, 1542 !(filter_flags & FIF_PSPOLL)); 1543 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); 1544 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 1545 !(filter_flags & FIF_CONTROL)); 1546 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, 1547 !(filter_flags & FIF_CONTROL)); 1548 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); 1549 } 1550 EXPORT_SYMBOL_GPL(rt2800_config_filter); 1551 1552 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, 1553 struct rt2x00intf_conf *conf, const unsigned int flags) 1554 { 1555 u32 reg; 1556 bool update_bssid = false; 1557 1558 if (flags & CONFIG_UPDATE_TYPE) { 1559 /* 1560 * Enable synchronisation. 1561 */ 1562 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); 1563 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); 1564 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1565 1566 if (conf->sync == TSF_SYNC_AP_NONE) { 1567 /* 1568 * Tune beacon queue transmit parameters for AP mode 1569 */ 1570 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); 1571 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); 1572 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); 1573 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1574 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); 1575 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1576 } else { 1577 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); 1578 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); 1579 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); 1580 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1581 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); 1582 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1583 } 1584 } 1585 1586 if (flags & CONFIG_UPDATE_MAC) { 1587 if (flags & CONFIG_UPDATE_TYPE && 1588 conf->sync == TSF_SYNC_AP_NONE) { 1589 /* 1590 * The BSSID register has to be set to our own mac 1591 * address in AP mode. 1592 */ 1593 memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); 1594 update_bssid = true; 1595 } 1596 1597 if (!is_zero_ether_addr((const u8 *)conf->mac)) { 1598 reg = le32_to_cpu(conf->mac[1]); 1599 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); 1600 conf->mac[1] = cpu_to_le32(reg); 1601 } 1602 1603 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, 1604 conf->mac, sizeof(conf->mac)); 1605 } 1606 1607 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { 1608 if (!is_zero_ether_addr((const u8 *)conf->bssid)) { 1609 reg = le32_to_cpu(conf->bssid[1]); 1610 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); 1611 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); 1612 conf->bssid[1] = cpu_to_le32(reg); 1613 } 1614 1615 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, 1616 conf->bssid, sizeof(conf->bssid)); 1617 } 1618 } 1619 EXPORT_SYMBOL_GPL(rt2800_config_intf); 1620 1621 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, 1622 struct rt2x00lib_erp *erp) 1623 { 1624 bool any_sta_nongf = !!(erp->ht_opmode & 1625 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 1626 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; 1627 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; 1628 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; 1629 u32 reg; 1630 1631 /* default protection rate for HT20: OFDM 24M */ 1632 mm20_rate = gf20_rate = 0x4004; 1633 1634 /* default protection rate for HT40: duplicate OFDM 24M */ 1635 mm40_rate = gf40_rate = 0x4084; 1636 1637 switch (protection) { 1638 case IEEE80211_HT_OP_MODE_PROTECTION_NONE: 1639 /* 1640 * All STAs in this BSS are HT20/40 but there might be 1641 * STAs not supporting greenfield mode. 1642 * => Disable protection for HT transmissions. 1643 */ 1644 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; 1645 1646 break; 1647 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 1648 /* 1649 * All STAs in this BSS are HT20 or HT20/40 but there 1650 * might be STAs not supporting greenfield mode. 1651 * => Protect all HT40 transmissions. 1652 */ 1653 mm20_mode = gf20_mode = 0; 1654 mm40_mode = gf40_mode = 1; 1655 1656 break; 1657 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 1658 /* 1659 * Nonmember protection: 1660 * According to 802.11n we _should_ protect all 1661 * HT transmissions (but we don't have to). 1662 * 1663 * But if cts_protection is enabled we _shall_ protect 1664 * all HT transmissions using a CCK rate. 1665 * 1666 * And if any station is non GF we _shall_ protect 1667 * GF transmissions. 1668 * 1669 * We decide to protect everything 1670 * -> fall through to mixed mode. 1671 */ 1672 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 1673 /* 1674 * Legacy STAs are present 1675 * => Protect all HT transmissions. 1676 */ 1677 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1; 1678 1679 /* 1680 * If erp protection is needed we have to protect HT 1681 * transmissions with CCK 11M long preamble. 1682 */ 1683 if (erp->cts_protection) { 1684 /* don't duplicate RTS/CTS in CCK mode */ 1685 mm20_rate = mm40_rate = 0x0003; 1686 gf20_rate = gf40_rate = 0x0003; 1687 } 1688 break; 1689 } 1690 1691 /* check for STAs not supporting greenfield mode */ 1692 if (any_sta_nongf) 1693 gf20_mode = gf40_mode = 1; 1694 1695 /* Update HT protection config */ 1696 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); 1697 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); 1698 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); 1699 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 1700 1701 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); 1702 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); 1703 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); 1704 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 1705 1706 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); 1707 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); 1708 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); 1709 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 1710 1711 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); 1712 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); 1713 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); 1714 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 1715 } 1716 1717 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, 1718 u32 changed) 1719 { 1720 u32 reg; 1721 1722 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 1723 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); 1724 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 1725 !!erp->short_preamble); 1726 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 1727 } 1728 1729 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 1730 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); 1731 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 1732 erp->cts_protection ? 2 : 0); 1733 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 1734 } 1735 1736 if (changed & BSS_CHANGED_BASIC_RATES) { 1737 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 1738 0xff0 | erp->basic_rates); 1739 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 1740 } 1741 1742 if (changed & BSS_CHANGED_ERP_SLOT) { 1743 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); 1744 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 1745 erp->slot_time); 1746 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 1747 1748 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); 1749 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); 1750 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 1751 } 1752 1753 if (changed & BSS_CHANGED_BEACON_INT) { 1754 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); 1755 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1756 erp->beacon_int * 16); 1757 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1758 } 1759 1760 if (changed & BSS_CHANGED_HT) 1761 rt2800_config_ht_opmode(rt2x00dev, erp); 1762 } 1763 EXPORT_SYMBOL_GPL(rt2800_config_erp); 1764 1765 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) 1766 { 1767 u32 reg; 1768 u16 eeprom; 1769 u8 led_ctrl, led_g_mode, led_r_mode; 1770 1771 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); 1772 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { 1773 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); 1774 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); 1775 } else { 1776 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); 1777 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); 1778 } 1779 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 1780 1781 rt2800_register_read(rt2x00dev, LED_CFG, ®); 1782 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; 1783 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; 1784 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || 1785 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { 1786 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); 1787 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); 1788 if (led_ctrl == 0 || led_ctrl > 0x40) { 1789 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); 1790 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); 1791 rt2800_register_write(rt2x00dev, LED_CFG, reg); 1792 } else { 1793 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, 1794 (led_g_mode << 2) | led_r_mode, 1); 1795 } 1796 } 1797 } 1798 1799 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, 1800 enum antenna ant) 1801 { 1802 u32 reg; 1803 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; 1804 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; 1805 1806 if (rt2x00_is_pci(rt2x00dev)) { 1807 rt2800_register_read(rt2x00dev, E2PROM_CSR, ®); 1808 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); 1809 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); 1810 } else if (rt2x00_is_usb(rt2x00dev)) 1811 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, 1812 eesk_pin, 0); 1813 1814 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 1815 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 1816 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); 1817 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 1818 } 1819 1820 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 1821 { 1822 u8 r1; 1823 u8 r3; 1824 u16 eeprom; 1825 1826 rt2800_bbp_read(rt2x00dev, 1, &r1); 1827 rt2800_bbp_read(rt2x00dev, 3, &r3); 1828 1829 if (rt2x00_rt(rt2x00dev, RT3572) && 1830 rt2x00_has_cap_bt_coexist(rt2x00dev)) 1831 rt2800_config_3572bt_ant(rt2x00dev); 1832 1833 /* 1834 * Configure the TX antenna. 1835 */ 1836 switch (ant->tx_chain_num) { 1837 case 1: 1838 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 1839 break; 1840 case 2: 1841 if (rt2x00_rt(rt2x00dev, RT3572) && 1842 rt2x00_has_cap_bt_coexist(rt2x00dev)) 1843 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); 1844 else 1845 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 1846 break; 1847 case 3: 1848 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 1849 break; 1850 } 1851 1852 /* 1853 * Configure the RX antenna. 1854 */ 1855 switch (ant->rx_chain_num) { 1856 case 1: 1857 if (rt2x00_rt(rt2x00dev, RT3070) || 1858 rt2x00_rt(rt2x00dev, RT3090) || 1859 rt2x00_rt(rt2x00dev, RT3352) || 1860 rt2x00_rt(rt2x00dev, RT3390)) { 1861 rt2800_eeprom_read(rt2x00dev, 1862 EEPROM_NIC_CONF1, &eeprom); 1863 if (rt2x00_get_field16(eeprom, 1864 EEPROM_NIC_CONF1_ANT_DIVERSITY)) 1865 rt2800_set_ant_diversity(rt2x00dev, 1866 rt2x00dev->default_ant.rx); 1867 } 1868 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 1869 break; 1870 case 2: 1871 if (rt2x00_rt(rt2x00dev, RT3572) && 1872 rt2x00_has_cap_bt_coexist(rt2x00dev)) { 1873 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); 1874 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1875 rt2x00dev->curr_band == NL80211_BAND_5GHZ); 1876 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); 1877 } else { 1878 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); 1879 } 1880 break; 1881 case 3: 1882 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); 1883 break; 1884 } 1885 1886 rt2800_bbp_write(rt2x00dev, 3, r3); 1887 rt2800_bbp_write(rt2x00dev, 1, r1); 1888 1889 if (rt2x00_rt(rt2x00dev, RT3593)) { 1890 if (ant->rx_chain_num == 1) 1891 rt2800_bbp_write(rt2x00dev, 86, 0x00); 1892 else 1893 rt2800_bbp_write(rt2x00dev, 86, 0x46); 1894 } 1895 } 1896 EXPORT_SYMBOL_GPL(rt2800_config_ant); 1897 1898 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, 1899 struct rt2x00lib_conf *libconf) 1900 { 1901 u16 eeprom; 1902 short lna_gain; 1903 1904 if (libconf->rf.channel <= 14) { 1905 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); 1906 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); 1907 } else if (libconf->rf.channel <= 64) { 1908 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); 1909 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); 1910 } else if (libconf->rf.channel <= 128) { 1911 if (rt2x00_rt(rt2x00dev, RT3593)) { 1912 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom); 1913 lna_gain = rt2x00_get_field16(eeprom, 1914 EEPROM_EXT_LNA2_A1); 1915 } else { 1916 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); 1917 lna_gain = rt2x00_get_field16(eeprom, 1918 EEPROM_RSSI_BG2_LNA_A1); 1919 } 1920 } else { 1921 if (rt2x00_rt(rt2x00dev, RT3593)) { 1922 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom); 1923 lna_gain = rt2x00_get_field16(eeprom, 1924 EEPROM_EXT_LNA2_A2); 1925 } else { 1926 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); 1927 lna_gain = rt2x00_get_field16(eeprom, 1928 EEPROM_RSSI_A2_LNA_A2); 1929 } 1930 } 1931 1932 rt2x00dev->lna_gain = lna_gain; 1933 } 1934 1935 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev) 1936 { 1937 return clk_get_rate(rt2x00dev->clk) == 20000000; 1938 } 1939 1940 #define FREQ_OFFSET_BOUND 0x5f 1941 1942 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev) 1943 { 1944 u8 freq_offset, prev_freq_offset; 1945 u8 rfcsr, prev_rfcsr; 1946 1947 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE); 1948 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND); 1949 1950 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); 1951 prev_rfcsr = rfcsr; 1952 1953 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset); 1954 if (rfcsr == prev_rfcsr) 1955 return; 1956 1957 if (rt2x00_is_usb(rt2x00dev)) { 1958 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff, 1959 freq_offset, prev_rfcsr); 1960 return; 1961 } 1962 1963 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE); 1964 while (prev_freq_offset != freq_offset) { 1965 if (prev_freq_offset < freq_offset) 1966 prev_freq_offset++; 1967 else 1968 prev_freq_offset--; 1969 1970 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset); 1971 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 1972 1973 usleep_range(1000, 1500); 1974 } 1975 } 1976 1977 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, 1978 struct ieee80211_conf *conf, 1979 struct rf_channel *rf, 1980 struct channel_info *info) 1981 { 1982 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 1983 1984 if (rt2x00dev->default_ant.tx_chain_num == 1) 1985 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); 1986 1987 if (rt2x00dev->default_ant.rx_chain_num == 1) { 1988 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); 1989 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 1990 } else if (rt2x00dev->default_ant.rx_chain_num == 2) 1991 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 1992 1993 if (rf->channel > 14) { 1994 /* 1995 * When TX power is below 0, we should increase it by 7 to 1996 * make it a positive value (Minimum value is -7). 1997 * However this means that values between 0 and 7 have 1998 * double meaning, and we should set a 7DBm boost flag. 1999 */ 2000 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, 2001 (info->default_power1 >= 0)); 2002 2003 if (info->default_power1 < 0) 2004 info->default_power1 += 7; 2005 2006 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); 2007 2008 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, 2009 (info->default_power2 >= 0)); 2010 2011 if (info->default_power2 < 0) 2012 info->default_power2 += 7; 2013 2014 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); 2015 } else { 2016 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); 2017 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); 2018 } 2019 2020 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); 2021 2022 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2023 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2024 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2025 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2026 2027 udelay(200); 2028 2029 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2030 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2031 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 2032 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2033 2034 udelay(200); 2035 2036 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2037 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2038 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2039 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2040 } 2041 2042 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, 2043 struct ieee80211_conf *conf, 2044 struct rf_channel *rf, 2045 struct channel_info *info) 2046 { 2047 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2048 u8 rfcsr, calib_tx, calib_rx; 2049 2050 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2051 2052 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); 2053 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3); 2054 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2055 2056 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 2057 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2058 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2059 2060 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); 2061 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); 2062 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2063 2064 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); 2065 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); 2066 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2067 2068 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2069 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2070 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 2071 rt2x00dev->default_ant.rx_chain_num <= 1); 2072 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 2073 rt2x00dev->default_ant.rx_chain_num <= 2); 2074 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2075 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 2076 rt2x00dev->default_ant.tx_chain_num <= 1); 2077 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 2078 rt2x00dev->default_ant.tx_chain_num <= 2); 2079 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2080 2081 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); 2082 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2083 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2084 2085 if (rt2x00_rt(rt2x00dev, RT3390)) { 2086 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f; 2087 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f; 2088 } else { 2089 if (conf_is_ht40(conf)) { 2090 calib_tx = drv_data->calibration_bw40; 2091 calib_rx = drv_data->calibration_bw40; 2092 } else { 2093 calib_tx = drv_data->calibration_bw20; 2094 calib_rx = drv_data->calibration_bw20; 2095 } 2096 } 2097 2098 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr); 2099 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx); 2100 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr); 2101 2102 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr); 2103 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx); 2104 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2105 2106 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); 2107 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2108 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2109 2110 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 2111 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 2112 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2113 2114 usleep_range(1000, 1500); 2115 2116 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 2117 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2118 } 2119 2120 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, 2121 struct ieee80211_conf *conf, 2122 struct rf_channel *rf, 2123 struct channel_info *info) 2124 { 2125 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2126 u8 rfcsr; 2127 u32 reg; 2128 2129 if (rf->channel <= 14) { 2130 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2131 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2132 } else { 2133 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2134 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2135 } 2136 2137 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2138 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 2139 2140 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 2141 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2142 if (rf->channel <= 14) 2143 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); 2144 else 2145 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); 2146 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2147 2148 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr); 2149 if (rf->channel <= 14) 2150 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); 2151 else 2152 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); 2153 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); 2154 2155 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); 2156 if (rf->channel <= 14) { 2157 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); 2158 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2159 info->default_power1); 2160 } else { 2161 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); 2162 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2163 (info->default_power1 & 0x3) | 2164 ((info->default_power1 & 0xC) << 1)); 2165 } 2166 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2167 2168 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); 2169 if (rf->channel <= 14) { 2170 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); 2171 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2172 info->default_power2); 2173 } else { 2174 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); 2175 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2176 (info->default_power2 & 0x3) | 2177 ((info->default_power2 & 0xC) << 1)); 2178 } 2179 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2180 2181 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2182 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2183 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2184 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2185 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2186 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2187 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2188 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2189 if (rf->channel <= 14) { 2190 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2191 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2192 } 2193 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2194 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2195 } else { 2196 switch (rt2x00dev->default_ant.tx_chain_num) { 2197 case 1: 2198 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2199 case 2: 2200 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2201 break; 2202 } 2203 2204 switch (rt2x00dev->default_ant.rx_chain_num) { 2205 case 1: 2206 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2207 case 2: 2208 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2209 break; 2210 } 2211 } 2212 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2213 2214 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); 2215 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2216 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2217 2218 if (conf_is_ht40(conf)) { 2219 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40); 2220 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40); 2221 } else { 2222 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20); 2223 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20); 2224 } 2225 2226 if (rf->channel <= 14) { 2227 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 2228 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 2229 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2230 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 2231 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 2232 rfcsr = 0x4c; 2233 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2234 drv_data->txmixer_gain_24g); 2235 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2236 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2237 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 2238 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 2239 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 2240 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 2241 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 2242 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 2243 } else { 2244 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); 2245 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1); 2246 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0); 2247 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1); 2248 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0); 2249 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2250 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 2251 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2252 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 2253 rt2800_rfcsr_write(rt2x00dev, 15, 0x43); 2254 rfcsr = 0x7a; 2255 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2256 drv_data->txmixer_gain_5g); 2257 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2258 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2259 if (rf->channel <= 64) { 2260 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7); 2261 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6); 2262 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 2263 } else if (rf->channel <= 128) { 2264 rt2800_rfcsr_write(rt2x00dev, 19, 0x74); 2265 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4); 2266 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2267 } else { 2268 rt2800_rfcsr_write(rt2x00dev, 19, 0x72); 2269 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3); 2270 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2271 } 2272 rt2800_rfcsr_write(rt2x00dev, 26, 0x87); 2273 rt2800_rfcsr_write(rt2x00dev, 27, 0x01); 2274 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); 2275 } 2276 2277 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 2278 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 2279 if (rf->channel <= 14) 2280 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 2281 else 2282 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); 2283 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2284 2285 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); 2286 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2287 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2288 } 2289 2290 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, 2291 struct ieee80211_conf *conf, 2292 struct rf_channel *rf, 2293 struct channel_info *info) 2294 { 2295 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2296 u8 txrx_agc_fc; 2297 u8 txrx_h20m; 2298 u8 rfcsr; 2299 u8 bbp; 2300 const bool txbf_enabled = false; /* TODO */ 2301 2302 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */ 2303 rt2800_bbp_read(rt2x00dev, 109, &bbp); 2304 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0); 2305 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0); 2306 rt2800_bbp_write(rt2x00dev, 109, bbp); 2307 2308 rt2800_bbp_read(rt2x00dev, 110, &bbp); 2309 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0); 2310 rt2800_bbp_write(rt2x00dev, 110, bbp); 2311 2312 if (rf->channel <= 14) { 2313 /* Restore BBP 25 & 26 for 2.4 GHz */ 2314 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2315 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2316 } else { 2317 /* Hard code BBP 25 & 26 for 5GHz */ 2318 2319 /* Enable IQ Phase correction */ 2320 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2321 /* Setup IQ Phase correction value */ 2322 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2323 } 2324 2325 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2326 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf); 2327 2328 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); 2329 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3)); 2330 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2331 2332 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); 2333 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1); 2334 if (rf->channel <= 14) 2335 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1); 2336 else 2337 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2); 2338 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2339 2340 rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr); 2341 if (rf->channel <= 14) { 2342 rfcsr = 0; 2343 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2344 info->default_power1 & 0x1f); 2345 } else { 2346 if (rt2x00_is_usb(rt2x00dev)) 2347 rfcsr = 0x40; 2348 2349 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2350 ((info->default_power1 & 0x18) << 1) | 2351 (info->default_power1 & 7)); 2352 } 2353 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr); 2354 2355 rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr); 2356 if (rf->channel <= 14) { 2357 rfcsr = 0; 2358 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2359 info->default_power2 & 0x1f); 2360 } else { 2361 if (rt2x00_is_usb(rt2x00dev)) 2362 rfcsr = 0x40; 2363 2364 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2365 ((info->default_power2 & 0x18) << 1) | 2366 (info->default_power2 & 7)); 2367 } 2368 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr); 2369 2370 rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr); 2371 if (rf->channel <= 14) { 2372 rfcsr = 0; 2373 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2374 info->default_power3 & 0x1f); 2375 } else { 2376 if (rt2x00_is_usb(rt2x00dev)) 2377 rfcsr = 0x40; 2378 2379 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2380 ((info->default_power3 & 0x18) << 1) | 2381 (info->default_power3 & 7)); 2382 } 2383 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr); 2384 2385 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2386 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2387 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2388 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2389 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2390 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2391 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2392 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2393 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2394 2395 switch (rt2x00dev->default_ant.tx_chain_num) { 2396 case 3: 2397 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2398 /* fallthrough */ 2399 case 2: 2400 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2401 /* fallthrough */ 2402 case 1: 2403 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2404 break; 2405 } 2406 2407 switch (rt2x00dev->default_ant.rx_chain_num) { 2408 case 3: 2409 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2410 /* fallthrough */ 2411 case 2: 2412 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2413 /* fallthrough */ 2414 case 1: 2415 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2416 break; 2417 } 2418 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2419 2420 rt2800_freq_cal_mode1(rt2x00dev); 2421 2422 if (conf_is_ht40(conf)) { 2423 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40, 2424 RFCSR24_TX_AGC_FC); 2425 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40, 2426 RFCSR24_TX_H20M); 2427 } else { 2428 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20, 2429 RFCSR24_TX_AGC_FC); 2430 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20, 2431 RFCSR24_TX_H20M); 2432 } 2433 2434 /* NOTE: the reference driver does not writes the new value 2435 * back to RFCSR 32 2436 */ 2437 rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr); 2438 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc); 2439 2440 if (rf->channel <= 14) 2441 rfcsr = 0xa0; 2442 else 2443 rfcsr = 0x80; 2444 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2445 2446 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 2447 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m); 2448 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m); 2449 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2450 2451 /* Band selection */ 2452 rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr); 2453 if (rf->channel <= 14) 2454 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 2455 else 2456 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 2457 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 2458 2459 rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr); 2460 if (rf->channel <= 14) 2461 rfcsr = 0x3c; 2462 else 2463 rfcsr = 0x20; 2464 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 2465 2466 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); 2467 if (rf->channel <= 14) 2468 rfcsr = 0x1a; 2469 else 2470 rfcsr = 0x12; 2471 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2472 2473 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 2474 if (rf->channel >= 1 && rf->channel <= 14) 2475 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2476 else if (rf->channel >= 36 && rf->channel <= 64) 2477 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2478 else if (rf->channel >= 100 && rf->channel <= 128) 2479 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2480 else 2481 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2482 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2483 2484 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 2485 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 2486 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2487 2488 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 2489 2490 if (rf->channel <= 14) { 2491 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 2492 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 2493 } else { 2494 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8); 2495 rt2800_rfcsr_write(rt2x00dev, 13, 0x23); 2496 } 2497 2498 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr); 2499 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1); 2500 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2501 2502 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr); 2503 if (rf->channel <= 14) { 2504 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5); 2505 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3); 2506 } else { 2507 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4); 2508 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2); 2509 } 2510 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2511 2512 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); 2513 if (rf->channel <= 14) 2514 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3); 2515 else 2516 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2); 2517 2518 if (txbf_enabled) 2519 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1); 2520 2521 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2522 2523 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); 2524 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0); 2525 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2526 2527 rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr); 2528 if (rf->channel <= 14) 2529 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b); 2530 else 2531 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f); 2532 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr); 2533 2534 if (rf->channel <= 14) { 2535 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 2536 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 2537 } else { 2538 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 2539 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 2540 } 2541 2542 /* Initiate VCO calibration */ 2543 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); 2544 if (rf->channel <= 14) { 2545 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2546 } else { 2547 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1); 2548 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1); 2549 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1); 2550 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1); 2551 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1); 2552 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2553 } 2554 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2555 2556 if (rf->channel >= 1 && rf->channel <= 14) { 2557 rfcsr = 0x23; 2558 if (txbf_enabled) 2559 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2560 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2561 2562 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 2563 } else if (rf->channel >= 36 && rf->channel <= 64) { 2564 rfcsr = 0x36; 2565 if (txbf_enabled) 2566 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2567 rt2800_rfcsr_write(rt2x00dev, 39, 0x36); 2568 2569 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb); 2570 } else if (rf->channel >= 100 && rf->channel <= 128) { 2571 rfcsr = 0x32; 2572 if (txbf_enabled) 2573 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2574 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2575 2576 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3); 2577 } else { 2578 rfcsr = 0x30; 2579 if (txbf_enabled) 2580 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2581 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2582 2583 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b); 2584 } 2585 } 2586 2587 #define POWER_BOUND 0x27 2588 #define POWER_BOUND_5G 0x2b 2589 2590 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev, 2591 struct ieee80211_conf *conf, 2592 struct rf_channel *rf, 2593 struct channel_info *info) 2594 { 2595 u8 rfcsr; 2596 2597 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2598 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2599 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); 2600 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 2601 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2602 2603 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); 2604 if (info->default_power1 > POWER_BOUND) 2605 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 2606 else 2607 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2608 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2609 2610 rt2800_freq_cal_mode1(rt2x00dev); 2611 2612 if (rf->channel <= 14) { 2613 if (rf->channel == 6) 2614 rt2800_bbp_write(rt2x00dev, 68, 0x0c); 2615 else 2616 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 2617 2618 if (rf->channel >= 1 && rf->channel <= 6) 2619 rt2800_bbp_write(rt2x00dev, 59, 0x0f); 2620 else if (rf->channel >= 7 && rf->channel <= 11) 2621 rt2800_bbp_write(rt2x00dev, 59, 0x0e); 2622 else if (rf->channel >= 12 && rf->channel <= 14) 2623 rt2800_bbp_write(rt2x00dev, 59, 0x0d); 2624 } 2625 } 2626 2627 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev, 2628 struct ieee80211_conf *conf, 2629 struct rf_channel *rf, 2630 struct channel_info *info) 2631 { 2632 u8 rfcsr; 2633 2634 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2635 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2636 2637 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 2638 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 2639 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 2640 2641 if (info->default_power1 > POWER_BOUND) 2642 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND); 2643 else 2644 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1); 2645 2646 if (info->default_power2 > POWER_BOUND) 2647 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND); 2648 else 2649 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2); 2650 2651 rt2800_freq_cal_mode1(rt2x00dev); 2652 2653 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2654 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2655 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2656 2657 if ( rt2x00dev->default_ant.tx_chain_num == 2 ) 2658 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2659 else 2660 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2661 2662 if ( rt2x00dev->default_ant.rx_chain_num == 2 ) 2663 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2664 else 2665 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2666 2667 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2668 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2669 2670 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2671 2672 rt2800_rfcsr_write(rt2x00dev, 31, 80); 2673 } 2674 2675 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 2676 struct ieee80211_conf *conf, 2677 struct rf_channel *rf, 2678 struct channel_info *info) 2679 { 2680 u8 rfcsr; 2681 2682 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2683 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2684 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); 2685 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 2686 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2687 2688 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); 2689 if (info->default_power1 > POWER_BOUND) 2690 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 2691 else 2692 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2693 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2694 2695 if (rt2x00_rt(rt2x00dev, RT5392)) { 2696 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); 2697 if (info->default_power2 > POWER_BOUND) 2698 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND); 2699 else 2700 rt2x00_set_field8(&rfcsr, RFCSR50_TX, 2701 info->default_power2); 2702 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2703 } 2704 2705 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2706 if (rt2x00_rt(rt2x00dev, RT5392)) { 2707 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2708 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2709 } 2710 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2711 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2712 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2713 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2714 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2715 2716 rt2800_freq_cal_mode1(rt2x00dev); 2717 2718 if (rf->channel <= 14) { 2719 int idx = rf->channel-1; 2720 2721 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2722 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 2723 /* r55/r59 value array of channel 1~14 */ 2724 static const char r55_bt_rev[] = {0x83, 0x83, 2725 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, 2726 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; 2727 static const char r59_bt_rev[] = {0x0e, 0x0e, 2728 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, 2729 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; 2730 2731 rt2800_rfcsr_write(rt2x00dev, 55, 2732 r55_bt_rev[idx]); 2733 rt2800_rfcsr_write(rt2x00dev, 59, 2734 r59_bt_rev[idx]); 2735 } else { 2736 static const char r59_bt[] = {0x8b, 0x8b, 0x8b, 2737 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, 2738 0x88, 0x88, 0x86, 0x85, 0x84}; 2739 2740 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); 2741 } 2742 } else { 2743 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 2744 static const char r55_nonbt_rev[] = {0x23, 0x23, 2745 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, 2746 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; 2747 static const char r59_nonbt_rev[] = {0x07, 0x07, 2748 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 2749 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; 2750 2751 rt2800_rfcsr_write(rt2x00dev, 55, 2752 r55_nonbt_rev[idx]); 2753 rt2800_rfcsr_write(rt2x00dev, 59, 2754 r59_nonbt_rev[idx]); 2755 } else if (rt2x00_rt(rt2x00dev, RT5390) || 2756 rt2x00_rt(rt2x00dev, RT5392)) { 2757 static const char r59_non_bt[] = {0x8f, 0x8f, 2758 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, 2759 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; 2760 2761 rt2800_rfcsr_write(rt2x00dev, 59, 2762 r59_non_bt[idx]); 2763 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 2764 static const char r59_non_bt[] = {0x0b, 0x0b, 2765 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a, 2766 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06}; 2767 2768 rt2800_rfcsr_write(rt2x00dev, 59, 2769 r59_non_bt[idx]); 2770 } 2771 } 2772 } 2773 } 2774 2775 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, 2776 struct ieee80211_conf *conf, 2777 struct rf_channel *rf, 2778 struct channel_info *info) 2779 { 2780 u8 rfcsr, ep_reg; 2781 u32 reg; 2782 int power_bound; 2783 2784 /* TODO */ 2785 const bool is_11b = false; 2786 const bool is_type_ep = false; 2787 2788 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 2789 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 2790 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0); 2791 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 2792 2793 /* Order of values on rf_channel entry: N, K, mod, R */ 2794 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff); 2795 2796 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr); 2797 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf); 2798 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8); 2799 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2); 2800 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr); 2801 2802 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); 2803 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1); 2804 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3); 2805 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2806 2807 if (rf->channel <= 14) { 2808 rt2800_rfcsr_write(rt2x00dev, 10, 0x90); 2809 /* FIXME: RF11 owerwrite ? */ 2810 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A); 2811 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 2812 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 2813 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 2814 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A); 2815 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 2816 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 2817 rt2800_rfcsr_write(rt2x00dev, 36, 0x80); 2818 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 2819 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 2820 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B); 2821 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D); 2822 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B); 2823 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5); 2824 rt2800_rfcsr_write(rt2x00dev, 43, 0x72); 2825 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E); 2826 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2); 2827 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B); 2828 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 2829 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E); 2830 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 2831 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 2832 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1); 2833 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 2834 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 2835 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 2836 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 2837 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 2838 2839 /* TODO RF27 <- tssi */ 2840 2841 rfcsr = rf->channel <= 10 ? 0x07 : 0x06; 2842 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2843 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr); 2844 2845 if (is_11b) { 2846 /* CCK */ 2847 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8); 2848 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0); 2849 if (is_type_ep) 2850 rt2800_rfcsr_write(rt2x00dev, 55, 0x06); 2851 else 2852 rt2800_rfcsr_write(rt2x00dev, 55, 0x47); 2853 } else { 2854 /* OFDM */ 2855 if (is_type_ep) 2856 rt2800_rfcsr_write(rt2x00dev, 55, 0x03); 2857 else 2858 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 2859 } 2860 2861 power_bound = POWER_BOUND; 2862 ep_reg = 0x2; 2863 } else { 2864 rt2800_rfcsr_write(rt2x00dev, 10, 0x97); 2865 /* FIMXE: RF11 overwrite */ 2866 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 2867 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF); 2868 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 2869 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 2870 rt2800_rfcsr_write(rt2x00dev, 37, 0x04); 2871 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 2872 rt2800_rfcsr_write(rt2x00dev, 40, 0x42); 2873 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB); 2874 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7); 2875 rt2800_rfcsr_write(rt2x00dev, 45, 0x41); 2876 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 2877 rt2800_rfcsr_write(rt2x00dev, 57, 0x77); 2878 rt2800_rfcsr_write(rt2x00dev, 60, 0x05); 2879 rt2800_rfcsr_write(rt2x00dev, 61, 0x01); 2880 2881 /* TODO RF27 <- tssi */ 2882 2883 if (rf->channel >= 36 && rf->channel <= 64) { 2884 2885 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E); 2886 rt2800_rfcsr_write(rt2x00dev, 13, 0x22); 2887 rt2800_rfcsr_write(rt2x00dev, 22, 0x60); 2888 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F); 2889 if (rf->channel <= 50) 2890 rt2800_rfcsr_write(rt2x00dev, 24, 0x09); 2891 else if (rf->channel >= 52) 2892 rt2800_rfcsr_write(rt2x00dev, 24, 0x07); 2893 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C); 2894 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B); 2895 rt2800_rfcsr_write(rt2x00dev, 44, 0X40); 2896 rt2800_rfcsr_write(rt2x00dev, 46, 0X00); 2897 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE); 2898 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C); 2899 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8); 2900 if (rf->channel <= 50) { 2901 rt2800_rfcsr_write(rt2x00dev, 55, 0x06), 2902 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3); 2903 } else if (rf->channel >= 52) { 2904 rt2800_rfcsr_write(rt2x00dev, 55, 0x04); 2905 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 2906 } 2907 2908 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 2909 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F); 2910 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 2911 2912 } else if (rf->channel >= 100 && rf->channel <= 165) { 2913 2914 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E); 2915 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 2916 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 2917 if (rf->channel <= 153) { 2918 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C); 2919 rt2800_rfcsr_write(rt2x00dev, 24, 0x06); 2920 } else if (rf->channel >= 155) { 2921 rt2800_rfcsr_write(rt2x00dev, 23, 0x38); 2922 rt2800_rfcsr_write(rt2x00dev, 24, 0x05); 2923 } 2924 if (rf->channel <= 138) { 2925 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A); 2926 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B); 2927 rt2800_rfcsr_write(rt2x00dev, 44, 0x20); 2928 rt2800_rfcsr_write(rt2x00dev, 46, 0x18); 2929 } else if (rf->channel >= 140) { 2930 rt2800_rfcsr_write(rt2x00dev, 39, 0x18); 2931 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B); 2932 rt2800_rfcsr_write(rt2x00dev, 44, 0x10); 2933 rt2800_rfcsr_write(rt2x00dev, 46, 0X08); 2934 } 2935 if (rf->channel <= 124) 2936 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC); 2937 else if (rf->channel >= 126) 2938 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC); 2939 if (rf->channel <= 138) 2940 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 2941 else if (rf->channel >= 140) 2942 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 2943 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB); 2944 if (rf->channel <= 138) 2945 rt2800_rfcsr_write(rt2x00dev, 55, 0x01); 2946 else if (rf->channel >= 140) 2947 rt2800_rfcsr_write(rt2x00dev, 55, 0x00); 2948 if (rf->channel <= 128) 2949 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 2950 else if (rf->channel >= 130) 2951 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB); 2952 if (rf->channel <= 116) 2953 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D); 2954 else if (rf->channel >= 118) 2955 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 2956 if (rf->channel <= 138) 2957 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F); 2958 else if (rf->channel >= 140) 2959 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C); 2960 if (rf->channel <= 116) 2961 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D); 2962 else if (rf->channel >= 118) 2963 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 2964 } 2965 2966 power_bound = POWER_BOUND_5G; 2967 ep_reg = 0x3; 2968 } 2969 2970 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); 2971 if (info->default_power1 > power_bound) 2972 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound); 2973 else 2974 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2975 if (is_type_ep) 2976 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg); 2977 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2978 2979 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); 2980 if (info->default_power2 > power_bound) 2981 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound); 2982 else 2983 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2); 2984 if (is_type_ep) 2985 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg); 2986 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2987 2988 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2989 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2990 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2991 2992 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 2993 rt2x00dev->default_ant.tx_chain_num >= 1); 2994 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 2995 rt2x00dev->default_ant.tx_chain_num == 2); 2996 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2997 2998 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 2999 rt2x00dev->default_ant.rx_chain_num >= 1); 3000 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 3001 rt2x00dev->default_ant.rx_chain_num == 2); 3002 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3003 3004 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3005 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4); 3006 3007 if (conf_is_ht40(conf)) 3008 rt2800_rfcsr_write(rt2x00dev, 30, 0x16); 3009 else 3010 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 3011 3012 if (!is_11b) { 3013 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3014 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3015 } 3016 3017 /* TODO proper frequency adjustment */ 3018 rt2800_freq_cal_mode1(rt2x00dev); 3019 3020 /* TODO merge with others */ 3021 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); 3022 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3023 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3024 3025 /* BBP settings */ 3026 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3027 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3028 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3029 3030 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18); 3031 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08); 3032 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38); 3033 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92); 3034 3035 /* GLRT band configuration */ 3036 rt2800_bbp_write(rt2x00dev, 195, 128); 3037 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0); 3038 rt2800_bbp_write(rt2x00dev, 195, 129); 3039 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E); 3040 rt2800_bbp_write(rt2x00dev, 195, 130); 3041 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28); 3042 rt2800_bbp_write(rt2x00dev, 195, 131); 3043 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20); 3044 rt2800_bbp_write(rt2x00dev, 195, 133); 3045 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F); 3046 rt2800_bbp_write(rt2x00dev, 195, 124); 3047 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F); 3048 } 3049 3050 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, 3051 const unsigned int word, 3052 const u8 value) 3053 { 3054 u8 chain, reg; 3055 3056 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) { 3057 rt2800_bbp_read(rt2x00dev, 27, ®); 3058 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); 3059 rt2800_bbp_write(rt2x00dev, 27, reg); 3060 3061 rt2800_bbp_write(rt2x00dev, word, value); 3062 } 3063 } 3064 3065 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel) 3066 { 3067 u8 cal; 3068 3069 /* TX0 IQ Gain */ 3070 rt2800_bbp_write(rt2x00dev, 158, 0x2c); 3071 if (channel <= 14) 3072 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G); 3073 else if (channel >= 36 && channel <= 64) 3074 cal = rt2x00_eeprom_byte(rt2x00dev, 3075 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G); 3076 else if (channel >= 100 && channel <= 138) 3077 cal = rt2x00_eeprom_byte(rt2x00dev, 3078 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G); 3079 else if (channel >= 140 && channel <= 165) 3080 cal = rt2x00_eeprom_byte(rt2x00dev, 3081 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G); 3082 else 3083 cal = 0; 3084 rt2800_bbp_write(rt2x00dev, 159, cal); 3085 3086 /* TX0 IQ Phase */ 3087 rt2800_bbp_write(rt2x00dev, 158, 0x2d); 3088 if (channel <= 14) 3089 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G); 3090 else if (channel >= 36 && channel <= 64) 3091 cal = rt2x00_eeprom_byte(rt2x00dev, 3092 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G); 3093 else if (channel >= 100 && channel <= 138) 3094 cal = rt2x00_eeprom_byte(rt2x00dev, 3095 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G); 3096 else if (channel >= 140 && channel <= 165) 3097 cal = rt2x00_eeprom_byte(rt2x00dev, 3098 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G); 3099 else 3100 cal = 0; 3101 rt2800_bbp_write(rt2x00dev, 159, cal); 3102 3103 /* TX1 IQ Gain */ 3104 rt2800_bbp_write(rt2x00dev, 158, 0x4a); 3105 if (channel <= 14) 3106 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G); 3107 else if (channel >= 36 && channel <= 64) 3108 cal = rt2x00_eeprom_byte(rt2x00dev, 3109 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G); 3110 else if (channel >= 100 && channel <= 138) 3111 cal = rt2x00_eeprom_byte(rt2x00dev, 3112 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G); 3113 else if (channel >= 140 && channel <= 165) 3114 cal = rt2x00_eeprom_byte(rt2x00dev, 3115 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G); 3116 else 3117 cal = 0; 3118 rt2800_bbp_write(rt2x00dev, 159, cal); 3119 3120 /* TX1 IQ Phase */ 3121 rt2800_bbp_write(rt2x00dev, 158, 0x4b); 3122 if (channel <= 14) 3123 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G); 3124 else if (channel >= 36 && channel <= 64) 3125 cal = rt2x00_eeprom_byte(rt2x00dev, 3126 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G); 3127 else if (channel >= 100 && channel <= 138) 3128 cal = rt2x00_eeprom_byte(rt2x00dev, 3129 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G); 3130 else if (channel >= 140 && channel <= 165) 3131 cal = rt2x00_eeprom_byte(rt2x00dev, 3132 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G); 3133 else 3134 cal = 0; 3135 rt2800_bbp_write(rt2x00dev, 159, cal); 3136 3137 /* FIXME: possible RX0, RX1 callibration ? */ 3138 3139 /* RF IQ compensation control */ 3140 rt2800_bbp_write(rt2x00dev, 158, 0x04); 3141 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL); 3142 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3143 3144 /* RF IQ imbalance compensation control */ 3145 rt2800_bbp_write(rt2x00dev, 158, 0x03); 3146 cal = rt2x00_eeprom_byte(rt2x00dev, 3147 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL); 3148 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3149 } 3150 3151 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev, 3152 unsigned int channel, 3153 char txpower) 3154 { 3155 if (rt2x00_rt(rt2x00dev, RT3593)) 3156 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC); 3157 3158 if (channel <= 14) 3159 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER); 3160 3161 if (rt2x00_rt(rt2x00dev, RT3593)) 3162 return clamp_t(char, txpower, MIN_A_TXPOWER_3593, 3163 MAX_A_TXPOWER_3593); 3164 else 3165 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER); 3166 } 3167 3168 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 3169 struct ieee80211_conf *conf, 3170 struct rf_channel *rf, 3171 struct channel_info *info) 3172 { 3173 u32 reg; 3174 unsigned int tx_pin; 3175 u8 bbp, rfcsr; 3176 3177 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3178 info->default_power1); 3179 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3180 info->default_power2); 3181 if (rt2x00dev->default_ant.tx_chain_num > 2) 3182 info->default_power3 = 3183 rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3184 info->default_power3); 3185 3186 switch (rt2x00dev->chip.rf) { 3187 case RF2020: 3188 case RF3020: 3189 case RF3021: 3190 case RF3022: 3191 case RF3320: 3192 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 3193 break; 3194 case RF3052: 3195 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); 3196 break; 3197 case RF3053: 3198 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info); 3199 break; 3200 case RF3290: 3201 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info); 3202 break; 3203 case RF3322: 3204 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); 3205 break; 3206 case RF3070: 3207 case RF5350: 3208 case RF5360: 3209 case RF5362: 3210 case RF5370: 3211 case RF5372: 3212 case RF5390: 3213 case RF5392: 3214 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); 3215 break; 3216 case RF5592: 3217 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info); 3218 break; 3219 default: 3220 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 3221 } 3222 3223 if (rt2x00_rf(rt2x00dev, RF3070) || 3224 rt2x00_rf(rt2x00dev, RF3290) || 3225 rt2x00_rf(rt2x00dev, RF3322) || 3226 rt2x00_rf(rt2x00dev, RF5350) || 3227 rt2x00_rf(rt2x00dev, RF5360) || 3228 rt2x00_rf(rt2x00dev, RF5362) || 3229 rt2x00_rf(rt2x00dev, RF5370) || 3230 rt2x00_rf(rt2x00dev, RF5372) || 3231 rt2x00_rf(rt2x00dev, RF5390) || 3232 rt2x00_rf(rt2x00dev, RF5392)) { 3233 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 3234 if (rt2x00_rf(rt2x00dev, RF3322)) { 3235 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M, 3236 conf_is_ht40(conf)); 3237 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M, 3238 conf_is_ht40(conf)); 3239 } else { 3240 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 3241 conf_is_ht40(conf)); 3242 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 3243 conf_is_ht40(conf)); 3244 } 3245 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 3246 3247 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); 3248 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3249 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3250 } 3251 3252 /* 3253 * Change BBP settings 3254 */ 3255 3256 if (rt2x00_rt(rt2x00dev, RT3352)) { 3257 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3258 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3259 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3260 3261 rt2800_bbp_write(rt2x00dev, 27, 0x0); 3262 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 3263 rt2800_bbp_write(rt2x00dev, 27, 0x20); 3264 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 3265 rt2800_bbp_write(rt2x00dev, 86, 0x38); 3266 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 3267 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 3268 if (rf->channel > 14) { 3269 /* Disable CCK Packet detection on 5GHz */ 3270 rt2800_bbp_write(rt2x00dev, 70, 0x00); 3271 } else { 3272 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 3273 } 3274 3275 if (conf_is_ht40(conf)) 3276 rt2800_bbp_write(rt2x00dev, 105, 0x04); 3277 else 3278 rt2800_bbp_write(rt2x00dev, 105, 0x34); 3279 3280 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3281 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3282 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3283 rt2800_bbp_write(rt2x00dev, 77, 0x98); 3284 } else { 3285 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3286 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3287 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3288 rt2800_bbp_write(rt2x00dev, 86, 0); 3289 } 3290 3291 if (rf->channel <= 14) { 3292 if (!rt2x00_rt(rt2x00dev, RT5390) && 3293 !rt2x00_rt(rt2x00dev, RT5392)) { 3294 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 3295 rt2800_bbp_write(rt2x00dev, 82, 0x62); 3296 rt2800_bbp_write(rt2x00dev, 75, 0x46); 3297 } else { 3298 if (rt2x00_rt(rt2x00dev, RT3593)) 3299 rt2800_bbp_write(rt2x00dev, 82, 0x62); 3300 else 3301 rt2800_bbp_write(rt2x00dev, 82, 0x84); 3302 rt2800_bbp_write(rt2x00dev, 75, 0x50); 3303 } 3304 if (rt2x00_rt(rt2x00dev, RT3593)) 3305 rt2800_bbp_write(rt2x00dev, 83, 0x8a); 3306 } 3307 3308 } else { 3309 if (rt2x00_rt(rt2x00dev, RT3572)) 3310 rt2800_bbp_write(rt2x00dev, 82, 0x94); 3311 else if (rt2x00_rt(rt2x00dev, RT3593)) 3312 rt2800_bbp_write(rt2x00dev, 82, 0x82); 3313 else 3314 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 3315 3316 if (rt2x00_rt(rt2x00dev, RT3593)) 3317 rt2800_bbp_write(rt2x00dev, 83, 0x9a); 3318 3319 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) 3320 rt2800_bbp_write(rt2x00dev, 75, 0x46); 3321 else 3322 rt2800_bbp_write(rt2x00dev, 75, 0x50); 3323 } 3324 3325 rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®); 3326 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); 3327 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); 3328 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); 3329 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); 3330 3331 if (rt2x00_rt(rt2x00dev, RT3572)) 3332 rt2800_rfcsr_write(rt2x00dev, 8, 0); 3333 3334 tx_pin = 0; 3335 3336 switch (rt2x00dev->default_ant.tx_chain_num) { 3337 case 3: 3338 /* Turn on tertiary PAs */ 3339 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 3340 rf->channel > 14); 3341 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 3342 rf->channel <= 14); 3343 /* fall-through */ 3344 case 2: 3345 /* Turn on secondary PAs */ 3346 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 3347 rf->channel > 14); 3348 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 3349 rf->channel <= 14); 3350 /* fall-through */ 3351 case 1: 3352 /* Turn on primary PAs */ 3353 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 3354 rf->channel > 14); 3355 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) 3356 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 3357 else 3358 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 3359 rf->channel <= 14); 3360 break; 3361 } 3362 3363 switch (rt2x00dev->default_ant.rx_chain_num) { 3364 case 3: 3365 /* Turn on tertiary LNAs */ 3366 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1); 3367 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1); 3368 /* fall-through */ 3369 case 2: 3370 /* Turn on secondary LNAs */ 3371 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); 3372 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); 3373 /* fall-through */ 3374 case 1: 3375 /* Turn on primary LNAs */ 3376 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); 3377 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); 3378 break; 3379 } 3380 3381 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); 3382 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); 3383 3384 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 3385 3386 if (rt2x00_rt(rt2x00dev, RT3572)) { 3387 rt2800_rfcsr_write(rt2x00dev, 8, 0x80); 3388 3389 /* AGC init */ 3390 if (rf->channel <= 14) 3391 reg = 0x1c + (2 * rt2x00dev->lna_gain); 3392 else 3393 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 3394 3395 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3396 } 3397 3398 if (rt2x00_rt(rt2x00dev, RT3593)) { 3399 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 3400 3401 /* Band selection */ 3402 if (rt2x00_is_usb(rt2x00dev) || 3403 rt2x00_is_pcie(rt2x00dev)) { 3404 /* GPIO #8 controls all paths */ 3405 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); 3406 if (rf->channel <= 14) 3407 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); 3408 else 3409 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); 3410 } 3411 3412 /* LNA PE control. */ 3413 if (rt2x00_is_usb(rt2x00dev)) { 3414 /* GPIO #4 controls PE0 and PE1, 3415 * GPIO #7 controls PE2 3416 */ 3417 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 3418 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 3419 3420 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 3421 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 3422 } else if (rt2x00_is_pcie(rt2x00dev)) { 3423 /* GPIO #4 controls PE0, PE1 and PE2 */ 3424 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 3425 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 3426 } 3427 3428 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 3429 3430 /* AGC init */ 3431 if (rf->channel <= 14) 3432 reg = 0x1c + 2 * rt2x00dev->lna_gain; 3433 else 3434 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 3435 3436 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3437 3438 usleep_range(1000, 1500); 3439 } 3440 3441 if (rt2x00_rt(rt2x00dev, RT5592)) { 3442 rt2800_bbp_write(rt2x00dev, 195, 141); 3443 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a); 3444 3445 /* AGC init */ 3446 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain; 3447 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3448 3449 rt2800_iq_calibrate(rt2x00dev, rf->channel); 3450 } 3451 3452 rt2800_bbp_read(rt2x00dev, 4, &bbp); 3453 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 3454 rt2800_bbp_write(rt2x00dev, 4, bbp); 3455 3456 rt2800_bbp_read(rt2x00dev, 3, &bbp); 3457 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); 3458 rt2800_bbp_write(rt2x00dev, 3, bbp); 3459 3460 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 3461 if (conf_is_ht40(conf)) { 3462 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 3463 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 3464 rt2800_bbp_write(rt2x00dev, 73, 0x16); 3465 } else { 3466 rt2800_bbp_write(rt2x00dev, 69, 0x16); 3467 rt2800_bbp_write(rt2x00dev, 70, 0x08); 3468 rt2800_bbp_write(rt2x00dev, 73, 0x11); 3469 } 3470 } 3471 3472 usleep_range(1000, 1500); 3473 3474 /* 3475 * Clear channel statistic counters 3476 */ 3477 rt2800_register_read(rt2x00dev, CH_IDLE_STA, ®); 3478 rt2800_register_read(rt2x00dev, CH_BUSY_STA, ®); 3479 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, ®); 3480 3481 /* 3482 * Clear update flag 3483 */ 3484 if (rt2x00_rt(rt2x00dev, RT3352) || 3485 rt2x00_rt(rt2x00dev, RT5350)) { 3486 rt2800_bbp_read(rt2x00dev, 49, &bbp); 3487 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0); 3488 rt2800_bbp_write(rt2x00dev, 49, bbp); 3489 } 3490 } 3491 3492 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) 3493 { 3494 u8 tssi_bounds[9]; 3495 u8 current_tssi; 3496 u16 eeprom; 3497 u8 step; 3498 int i; 3499 3500 /* 3501 * First check if temperature compensation is supported. 3502 */ 3503 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); 3504 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC)) 3505 return 0; 3506 3507 /* 3508 * Read TSSI boundaries for temperature compensation from 3509 * the EEPROM. 3510 * 3511 * Array idx 0 1 2 3 4 5 6 7 8 3512 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4 3513 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 3514 */ 3515 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 3516 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom); 3517 tssi_bounds[0] = rt2x00_get_field16(eeprom, 3518 EEPROM_TSSI_BOUND_BG1_MINUS4); 3519 tssi_bounds[1] = rt2x00_get_field16(eeprom, 3520 EEPROM_TSSI_BOUND_BG1_MINUS3); 3521 3522 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom); 3523 tssi_bounds[2] = rt2x00_get_field16(eeprom, 3524 EEPROM_TSSI_BOUND_BG2_MINUS2); 3525 tssi_bounds[3] = rt2x00_get_field16(eeprom, 3526 EEPROM_TSSI_BOUND_BG2_MINUS1); 3527 3528 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom); 3529 tssi_bounds[4] = rt2x00_get_field16(eeprom, 3530 EEPROM_TSSI_BOUND_BG3_REF); 3531 tssi_bounds[5] = rt2x00_get_field16(eeprom, 3532 EEPROM_TSSI_BOUND_BG3_PLUS1); 3533 3534 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom); 3535 tssi_bounds[6] = rt2x00_get_field16(eeprom, 3536 EEPROM_TSSI_BOUND_BG4_PLUS2); 3537 tssi_bounds[7] = rt2x00_get_field16(eeprom, 3538 EEPROM_TSSI_BOUND_BG4_PLUS3); 3539 3540 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom); 3541 tssi_bounds[8] = rt2x00_get_field16(eeprom, 3542 EEPROM_TSSI_BOUND_BG5_PLUS4); 3543 3544 step = rt2x00_get_field16(eeprom, 3545 EEPROM_TSSI_BOUND_BG5_AGC_STEP); 3546 } else { 3547 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom); 3548 tssi_bounds[0] = rt2x00_get_field16(eeprom, 3549 EEPROM_TSSI_BOUND_A1_MINUS4); 3550 tssi_bounds[1] = rt2x00_get_field16(eeprom, 3551 EEPROM_TSSI_BOUND_A1_MINUS3); 3552 3553 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom); 3554 tssi_bounds[2] = rt2x00_get_field16(eeprom, 3555 EEPROM_TSSI_BOUND_A2_MINUS2); 3556 tssi_bounds[3] = rt2x00_get_field16(eeprom, 3557 EEPROM_TSSI_BOUND_A2_MINUS1); 3558 3559 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom); 3560 tssi_bounds[4] = rt2x00_get_field16(eeprom, 3561 EEPROM_TSSI_BOUND_A3_REF); 3562 tssi_bounds[5] = rt2x00_get_field16(eeprom, 3563 EEPROM_TSSI_BOUND_A3_PLUS1); 3564 3565 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom); 3566 tssi_bounds[6] = rt2x00_get_field16(eeprom, 3567 EEPROM_TSSI_BOUND_A4_PLUS2); 3568 tssi_bounds[7] = rt2x00_get_field16(eeprom, 3569 EEPROM_TSSI_BOUND_A4_PLUS3); 3570 3571 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom); 3572 tssi_bounds[8] = rt2x00_get_field16(eeprom, 3573 EEPROM_TSSI_BOUND_A5_PLUS4); 3574 3575 step = rt2x00_get_field16(eeprom, 3576 EEPROM_TSSI_BOUND_A5_AGC_STEP); 3577 } 3578 3579 /* 3580 * Check if temperature compensation is supported. 3581 */ 3582 if (tssi_bounds[4] == 0xff || step == 0xff) 3583 return 0; 3584 3585 /* 3586 * Read current TSSI (BBP 49). 3587 */ 3588 rt2800_bbp_read(rt2x00dev, 49, ¤t_tssi); 3589 3590 /* 3591 * Compare TSSI value (BBP49) with the compensation boundaries 3592 * from the EEPROM and increase or decrease tx power. 3593 */ 3594 for (i = 0; i <= 3; i++) { 3595 if (current_tssi > tssi_bounds[i]) 3596 break; 3597 } 3598 3599 if (i == 4) { 3600 for (i = 8; i >= 5; i--) { 3601 if (current_tssi < tssi_bounds[i]) 3602 break; 3603 } 3604 } 3605 3606 return (i - 4) * step; 3607 } 3608 3609 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, 3610 enum nl80211_band band) 3611 { 3612 u16 eeprom; 3613 u8 comp_en; 3614 u8 comp_type; 3615 int comp_value = 0; 3616 3617 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom); 3618 3619 /* 3620 * HT40 compensation not required. 3621 */ 3622 if (eeprom == 0xffff || 3623 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 3624 return 0; 3625 3626 if (band == NL80211_BAND_2GHZ) { 3627 comp_en = rt2x00_get_field16(eeprom, 3628 EEPROM_TXPOWER_DELTA_ENABLE_2G); 3629 if (comp_en) { 3630 comp_type = rt2x00_get_field16(eeprom, 3631 EEPROM_TXPOWER_DELTA_TYPE_2G); 3632 comp_value = rt2x00_get_field16(eeprom, 3633 EEPROM_TXPOWER_DELTA_VALUE_2G); 3634 if (!comp_type) 3635 comp_value = -comp_value; 3636 } 3637 } else { 3638 comp_en = rt2x00_get_field16(eeprom, 3639 EEPROM_TXPOWER_DELTA_ENABLE_5G); 3640 if (comp_en) { 3641 comp_type = rt2x00_get_field16(eeprom, 3642 EEPROM_TXPOWER_DELTA_TYPE_5G); 3643 comp_value = rt2x00_get_field16(eeprom, 3644 EEPROM_TXPOWER_DELTA_VALUE_5G); 3645 if (!comp_type) 3646 comp_value = -comp_value; 3647 } 3648 } 3649 3650 return comp_value; 3651 } 3652 3653 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev, 3654 int power_level, int max_power) 3655 { 3656 int delta; 3657 3658 if (rt2x00_has_cap_power_limit(rt2x00dev)) 3659 return 0; 3660 3661 /* 3662 * XXX: We don't know the maximum transmit power of our hardware since 3663 * the EEPROM doesn't expose it. We only know that we are calibrated 3664 * to 100% tx power. 3665 * 3666 * Hence, we assume the regulatory limit that cfg80211 calulated for 3667 * the current channel is our maximum and if we are requested to lower 3668 * the value we just reduce our tx power accordingly. 3669 */ 3670 delta = power_level - max_power; 3671 return min(delta, 0); 3672 } 3673 3674 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, 3675 enum nl80211_band band, int power_level, 3676 u8 txpower, int delta) 3677 { 3678 u16 eeprom; 3679 u8 criterion; 3680 u8 eirp_txpower; 3681 u8 eirp_txpower_criterion; 3682 u8 reg_limit; 3683 3684 if (rt2x00_rt(rt2x00dev, RT3593)) 3685 return min_t(u8, txpower, 0xc); 3686 3687 if (rt2x00_has_cap_power_limit(rt2x00dev)) { 3688 /* 3689 * Check if eirp txpower exceed txpower_limit. 3690 * We use OFDM 6M as criterion and its eirp txpower 3691 * is stored at EEPROM_EIRP_MAX_TX_POWER. 3692 * .11b data rate need add additional 4dbm 3693 * when calculating eirp txpower. 3694 */ 3695 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3696 1, &eeprom); 3697 criterion = rt2x00_get_field16(eeprom, 3698 EEPROM_TXPOWER_BYRATE_RATE0); 3699 3700 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, 3701 &eeprom); 3702 3703 if (band == NL80211_BAND_2GHZ) 3704 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 3705 EEPROM_EIRP_MAX_TX_POWER_2GHZ); 3706 else 3707 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 3708 EEPROM_EIRP_MAX_TX_POWER_5GHZ); 3709 3710 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) + 3711 (is_rate_b ? 4 : 0) + delta; 3712 3713 reg_limit = (eirp_txpower > power_level) ? 3714 (eirp_txpower - power_level) : 0; 3715 } else 3716 reg_limit = 0; 3717 3718 txpower = max(0, txpower + delta - reg_limit); 3719 return min_t(u8, txpower, 0xc); 3720 } 3721 3722 3723 enum { 3724 TX_PWR_CFG_0_IDX, 3725 TX_PWR_CFG_1_IDX, 3726 TX_PWR_CFG_2_IDX, 3727 TX_PWR_CFG_3_IDX, 3728 TX_PWR_CFG_4_IDX, 3729 TX_PWR_CFG_5_IDX, 3730 TX_PWR_CFG_6_IDX, 3731 TX_PWR_CFG_7_IDX, 3732 TX_PWR_CFG_8_IDX, 3733 TX_PWR_CFG_9_IDX, 3734 TX_PWR_CFG_0_EXT_IDX, 3735 TX_PWR_CFG_1_EXT_IDX, 3736 TX_PWR_CFG_2_EXT_IDX, 3737 TX_PWR_CFG_3_EXT_IDX, 3738 TX_PWR_CFG_4_EXT_IDX, 3739 TX_PWR_CFG_IDX_COUNT, 3740 }; 3741 3742 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, 3743 struct ieee80211_channel *chan, 3744 int power_level) 3745 { 3746 u8 txpower; 3747 u16 eeprom; 3748 u32 regs[TX_PWR_CFG_IDX_COUNT]; 3749 unsigned int offset; 3750 enum nl80211_band band = chan->band; 3751 int delta; 3752 int i; 3753 3754 memset(regs, '\0', sizeof(regs)); 3755 3756 /* TODO: adapt TX power reduction from the rt28xx code */ 3757 3758 /* calculate temperature compensation delta */ 3759 delta = rt2800_get_gain_calibration_delta(rt2x00dev); 3760 3761 if (band == NL80211_BAND_5GHZ) 3762 offset = 16; 3763 else 3764 offset = 0; 3765 3766 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 3767 offset += 8; 3768 3769 /* read the next four txpower values */ 3770 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3771 offset, &eeprom); 3772 3773 /* CCK 1MBS,2MBS */ 3774 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 3775 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 3776 txpower, delta); 3777 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3778 TX_PWR_CFG_0_CCK1_CH0, txpower); 3779 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3780 TX_PWR_CFG_0_CCK1_CH1, txpower); 3781 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 3782 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower); 3783 3784 /* CCK 5.5MBS,11MBS */ 3785 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 3786 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 3787 txpower, delta); 3788 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3789 TX_PWR_CFG_0_CCK5_CH0, txpower); 3790 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3791 TX_PWR_CFG_0_CCK5_CH1, txpower); 3792 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 3793 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower); 3794 3795 /* OFDM 6MBS,9MBS */ 3796 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 3797 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3798 txpower, delta); 3799 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3800 TX_PWR_CFG_0_OFDM6_CH0, txpower); 3801 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3802 TX_PWR_CFG_0_OFDM6_CH1, txpower); 3803 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 3804 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower); 3805 3806 /* OFDM 12MBS,18MBS */ 3807 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 3808 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3809 txpower, delta); 3810 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3811 TX_PWR_CFG_0_OFDM12_CH0, txpower); 3812 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3813 TX_PWR_CFG_0_OFDM12_CH1, txpower); 3814 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 3815 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower); 3816 3817 /* read the next four txpower values */ 3818 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3819 offset + 1, &eeprom); 3820 3821 /* OFDM 24MBS,36MBS */ 3822 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 3823 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3824 txpower, delta); 3825 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3826 TX_PWR_CFG_1_OFDM24_CH0, txpower); 3827 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3828 TX_PWR_CFG_1_OFDM24_CH1, txpower); 3829 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 3830 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower); 3831 3832 /* OFDM 48MBS */ 3833 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 3834 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3835 txpower, delta); 3836 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3837 TX_PWR_CFG_1_OFDM48_CH0, txpower); 3838 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3839 TX_PWR_CFG_1_OFDM48_CH1, txpower); 3840 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 3841 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower); 3842 3843 /* OFDM 54MBS */ 3844 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 3845 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3846 txpower, delta); 3847 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3848 TX_PWR_CFG_7_OFDM54_CH0, txpower); 3849 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3850 TX_PWR_CFG_7_OFDM54_CH1, txpower); 3851 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3852 TX_PWR_CFG_7_OFDM54_CH2, txpower); 3853 3854 /* read the next four txpower values */ 3855 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3856 offset + 2, &eeprom); 3857 3858 /* MCS 0,1 */ 3859 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 3860 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3861 txpower, delta); 3862 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3863 TX_PWR_CFG_1_MCS0_CH0, txpower); 3864 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3865 TX_PWR_CFG_1_MCS0_CH1, txpower); 3866 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 3867 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower); 3868 3869 /* MCS 2,3 */ 3870 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 3871 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3872 txpower, delta); 3873 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3874 TX_PWR_CFG_1_MCS2_CH0, txpower); 3875 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3876 TX_PWR_CFG_1_MCS2_CH1, txpower); 3877 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 3878 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower); 3879 3880 /* MCS 4,5 */ 3881 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 3882 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3883 txpower, delta); 3884 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3885 TX_PWR_CFG_2_MCS4_CH0, txpower); 3886 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3887 TX_PWR_CFG_2_MCS4_CH1, txpower); 3888 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 3889 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower); 3890 3891 /* MCS 6 */ 3892 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 3893 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3894 txpower, delta); 3895 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3896 TX_PWR_CFG_2_MCS6_CH0, txpower); 3897 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3898 TX_PWR_CFG_2_MCS6_CH1, txpower); 3899 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 3900 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower); 3901 3902 /* read the next four txpower values */ 3903 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3904 offset + 3, &eeprom); 3905 3906 /* MCS 7 */ 3907 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 3908 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3909 txpower, delta); 3910 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3911 TX_PWR_CFG_7_MCS7_CH0, txpower); 3912 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3913 TX_PWR_CFG_7_MCS7_CH1, txpower); 3914 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3915 TX_PWR_CFG_7_MCS7_CH2, txpower); 3916 3917 /* MCS 8,9 */ 3918 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 3919 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3920 txpower, delta); 3921 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3922 TX_PWR_CFG_2_MCS8_CH0, txpower); 3923 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3924 TX_PWR_CFG_2_MCS8_CH1, txpower); 3925 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 3926 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower); 3927 3928 /* MCS 10,11 */ 3929 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 3930 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3931 txpower, delta); 3932 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3933 TX_PWR_CFG_2_MCS10_CH0, txpower); 3934 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3935 TX_PWR_CFG_2_MCS10_CH1, txpower); 3936 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 3937 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower); 3938 3939 /* MCS 12,13 */ 3940 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 3941 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3942 txpower, delta); 3943 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 3944 TX_PWR_CFG_3_MCS12_CH0, txpower); 3945 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 3946 TX_PWR_CFG_3_MCS12_CH1, txpower); 3947 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 3948 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower); 3949 3950 /* read the next four txpower values */ 3951 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3952 offset + 4, &eeprom); 3953 3954 /* MCS 14 */ 3955 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 3956 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3957 txpower, delta); 3958 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 3959 TX_PWR_CFG_3_MCS14_CH0, txpower); 3960 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 3961 TX_PWR_CFG_3_MCS14_CH1, txpower); 3962 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 3963 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower); 3964 3965 /* MCS 15 */ 3966 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 3967 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3968 txpower, delta); 3969 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 3970 TX_PWR_CFG_8_MCS15_CH0, txpower); 3971 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 3972 TX_PWR_CFG_8_MCS15_CH1, txpower); 3973 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 3974 TX_PWR_CFG_8_MCS15_CH2, txpower); 3975 3976 /* MCS 16,17 */ 3977 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 3978 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3979 txpower, delta); 3980 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3981 TX_PWR_CFG_5_MCS16_CH0, txpower); 3982 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3983 TX_PWR_CFG_5_MCS16_CH1, txpower); 3984 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3985 TX_PWR_CFG_5_MCS16_CH2, txpower); 3986 3987 /* MCS 18,19 */ 3988 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 3989 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3990 txpower, delta); 3991 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3992 TX_PWR_CFG_5_MCS18_CH0, txpower); 3993 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3994 TX_PWR_CFG_5_MCS18_CH1, txpower); 3995 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3996 TX_PWR_CFG_5_MCS18_CH2, txpower); 3997 3998 /* read the next four txpower values */ 3999 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4000 offset + 5, &eeprom); 4001 4002 /* MCS 20,21 */ 4003 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4004 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4005 txpower, delta); 4006 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4007 TX_PWR_CFG_6_MCS20_CH0, txpower); 4008 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4009 TX_PWR_CFG_6_MCS20_CH1, txpower); 4010 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4011 TX_PWR_CFG_6_MCS20_CH2, txpower); 4012 4013 /* MCS 22 */ 4014 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4015 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4016 txpower, delta); 4017 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4018 TX_PWR_CFG_6_MCS22_CH0, txpower); 4019 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4020 TX_PWR_CFG_6_MCS22_CH1, txpower); 4021 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4022 TX_PWR_CFG_6_MCS22_CH2, txpower); 4023 4024 /* MCS 23 */ 4025 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4026 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4027 txpower, delta); 4028 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4029 TX_PWR_CFG_8_MCS23_CH0, txpower); 4030 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4031 TX_PWR_CFG_8_MCS23_CH1, txpower); 4032 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4033 TX_PWR_CFG_8_MCS23_CH2, txpower); 4034 4035 /* read the next four txpower values */ 4036 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4037 offset + 6, &eeprom); 4038 4039 /* STBC, MCS 0,1 */ 4040 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4041 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4042 txpower, delta); 4043 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4044 TX_PWR_CFG_3_STBC0_CH0, txpower); 4045 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4046 TX_PWR_CFG_3_STBC0_CH1, txpower); 4047 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4048 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower); 4049 4050 /* STBC, MCS 2,3 */ 4051 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4052 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4053 txpower, delta); 4054 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4055 TX_PWR_CFG_3_STBC2_CH0, txpower); 4056 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4057 TX_PWR_CFG_3_STBC2_CH1, txpower); 4058 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4059 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower); 4060 4061 /* STBC, MCS 4,5 */ 4062 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4063 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4064 txpower, delta); 4065 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); 4066 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); 4067 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, 4068 txpower); 4069 4070 /* STBC, MCS 6 */ 4071 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4072 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4073 txpower, delta); 4074 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); 4075 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); 4076 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, 4077 txpower); 4078 4079 /* read the next four txpower values */ 4080 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4081 offset + 7, &eeprom); 4082 4083 /* STBC, MCS 7 */ 4084 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4085 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4086 txpower, delta); 4087 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4088 TX_PWR_CFG_9_STBC7_CH0, txpower); 4089 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4090 TX_PWR_CFG_9_STBC7_CH1, txpower); 4091 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4092 TX_PWR_CFG_9_STBC7_CH2, txpower); 4093 4094 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]); 4095 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]); 4096 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]); 4097 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]); 4098 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]); 4099 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]); 4100 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]); 4101 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]); 4102 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]); 4103 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]); 4104 4105 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT, 4106 regs[TX_PWR_CFG_0_EXT_IDX]); 4107 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT, 4108 regs[TX_PWR_CFG_1_EXT_IDX]); 4109 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT, 4110 regs[TX_PWR_CFG_2_EXT_IDX]); 4111 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT, 4112 regs[TX_PWR_CFG_3_EXT_IDX]); 4113 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT, 4114 regs[TX_PWR_CFG_4_EXT_IDX]); 4115 4116 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++) 4117 rt2x00_dbg(rt2x00dev, 4118 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n", 4119 (band == NL80211_BAND_5GHZ) ? '5' : '2', 4120 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ? 4121 '4' : '2', 4122 (i > TX_PWR_CFG_9_IDX) ? 4123 (i - TX_PWR_CFG_9_IDX - 1) : i, 4124 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "", 4125 (unsigned long) regs[i]); 4126 } 4127 4128 /* 4129 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and 4130 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values, 4131 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power 4132 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm. 4133 * Reference per rate transmit power values are located in the EEPROM at 4134 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to 4135 * current conditions (i.e. band, bandwidth, temperature, user settings). 4136 */ 4137 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, 4138 struct ieee80211_channel *chan, 4139 int power_level) 4140 { 4141 u8 txpower, r1; 4142 u16 eeprom; 4143 u32 reg, offset; 4144 int i, is_rate_b, delta, power_ctrl; 4145 enum nl80211_band band = chan->band; 4146 4147 /* 4148 * Calculate HT40 compensation. For 40MHz we need to add or subtract 4149 * value read from EEPROM (different for 2GHz and for 5GHz). 4150 */ 4151 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 4152 4153 /* 4154 * Calculate temperature compensation. Depends on measurement of current 4155 * TSSI (Transmitter Signal Strength Indication) we know TX power (due 4156 * to temperature or maybe other factors) is smaller or bigger than 4157 * expected. We adjust it, based on TSSI reference and boundaries values 4158 * provided in EEPROM. 4159 */ 4160 switch (rt2x00dev->chip.rt) { 4161 case RT2860: 4162 case RT2872: 4163 case RT2883: 4164 case RT3070: 4165 case RT3071: 4166 case RT3090: 4167 case RT3572: 4168 delta += rt2800_get_gain_calibration_delta(rt2x00dev); 4169 break; 4170 default: 4171 /* TODO: temperature compensation code for other chips. */ 4172 break; 4173 } 4174 4175 /* 4176 * Decrease power according to user settings, on devices with unknown 4177 * maximum tx power. For other devices we take user power_level into 4178 * consideration on rt2800_compensate_txpower(). 4179 */ 4180 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level, 4181 chan->max_power); 4182 4183 /* 4184 * BBP_R1 controls TX power for all rates, it allow to set the following 4185 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively. 4186 * 4187 * TODO: we do not use +6 dBm option to do not increase power beyond 4188 * regulatory limit, however this could be utilized for devices with 4189 * CAPABILITY_POWER_LIMIT. 4190 */ 4191 if (delta <= -12) { 4192 power_ctrl = 2; 4193 delta += 12; 4194 } else if (delta <= -6) { 4195 power_ctrl = 1; 4196 delta += 6; 4197 } else { 4198 power_ctrl = 0; 4199 } 4200 rt2800_bbp_read(rt2x00dev, 1, &r1); 4201 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl); 4202 rt2800_bbp_write(rt2x00dev, 1, r1); 4203 4204 offset = TX_PWR_CFG_0; 4205 4206 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { 4207 /* just to be safe */ 4208 if (offset > TX_PWR_CFG_4) 4209 break; 4210 4211 rt2800_register_read(rt2x00dev, offset, ®); 4212 4213 /* read the next four txpower values */ 4214 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4215 i, &eeprom); 4216 4217 is_rate_b = i ? 0 : 1; 4218 /* 4219 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, 4220 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, 4221 * TX_PWR_CFG_4: unknown 4222 */ 4223 txpower = rt2x00_get_field16(eeprom, 4224 EEPROM_TXPOWER_BYRATE_RATE0); 4225 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4226 power_level, txpower, delta); 4227 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); 4228 4229 /* 4230 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, 4231 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, 4232 * TX_PWR_CFG_4: unknown 4233 */ 4234 txpower = rt2x00_get_field16(eeprom, 4235 EEPROM_TXPOWER_BYRATE_RATE1); 4236 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4237 power_level, txpower, delta); 4238 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); 4239 4240 /* 4241 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS, 4242 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, 4243 * TX_PWR_CFG_4: unknown 4244 */ 4245 txpower = rt2x00_get_field16(eeprom, 4246 EEPROM_TXPOWER_BYRATE_RATE2); 4247 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4248 power_level, txpower, delta); 4249 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); 4250 4251 /* 4252 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, 4253 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, 4254 * TX_PWR_CFG_4: unknown 4255 */ 4256 txpower = rt2x00_get_field16(eeprom, 4257 EEPROM_TXPOWER_BYRATE_RATE3); 4258 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4259 power_level, txpower, delta); 4260 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); 4261 4262 /* read the next four txpower values */ 4263 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4264 i + 1, &eeprom); 4265 4266 is_rate_b = 0; 4267 /* 4268 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, 4269 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, 4270 * TX_PWR_CFG_4: unknown 4271 */ 4272 txpower = rt2x00_get_field16(eeprom, 4273 EEPROM_TXPOWER_BYRATE_RATE0); 4274 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4275 power_level, txpower, delta); 4276 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); 4277 4278 /* 4279 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, 4280 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, 4281 * TX_PWR_CFG_4: unknown 4282 */ 4283 txpower = rt2x00_get_field16(eeprom, 4284 EEPROM_TXPOWER_BYRATE_RATE1); 4285 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4286 power_level, txpower, delta); 4287 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); 4288 4289 /* 4290 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, 4291 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, 4292 * TX_PWR_CFG_4: unknown 4293 */ 4294 txpower = rt2x00_get_field16(eeprom, 4295 EEPROM_TXPOWER_BYRATE_RATE2); 4296 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4297 power_level, txpower, delta); 4298 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); 4299 4300 /* 4301 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, 4302 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, 4303 * TX_PWR_CFG_4: unknown 4304 */ 4305 txpower = rt2x00_get_field16(eeprom, 4306 EEPROM_TXPOWER_BYRATE_RATE3); 4307 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4308 power_level, txpower, delta); 4309 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); 4310 4311 rt2800_register_write(rt2x00dev, offset, reg); 4312 4313 /* next TX_PWR_CFG register */ 4314 offset += 4; 4315 } 4316 } 4317 4318 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, 4319 struct ieee80211_channel *chan, 4320 int power_level) 4321 { 4322 if (rt2x00_rt(rt2x00dev, RT3593)) 4323 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level); 4324 else 4325 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level); 4326 } 4327 4328 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) 4329 { 4330 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan, 4331 rt2x00dev->tx_power); 4332 } 4333 EXPORT_SYMBOL_GPL(rt2800_gain_calibration); 4334 4335 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) 4336 { 4337 u32 tx_pin; 4338 u8 rfcsr; 4339 4340 /* 4341 * A voltage-controlled oscillator(VCO) is an electronic oscillator 4342 * designed to be controlled in oscillation frequency by a voltage 4343 * input. Maybe the temperature will affect the frequency of 4344 * oscillation to be shifted. The VCO calibration will be called 4345 * periodically to adjust the frequency to be precision. 4346 */ 4347 4348 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin); 4349 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE; 4350 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 4351 4352 switch (rt2x00dev->chip.rf) { 4353 case RF2020: 4354 case RF3020: 4355 case RF3021: 4356 case RF3022: 4357 case RF3320: 4358 case RF3052: 4359 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); 4360 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 4361 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 4362 break; 4363 case RF3053: 4364 case RF3070: 4365 case RF3290: 4366 case RF5350: 4367 case RF5360: 4368 case RF5362: 4369 case RF5370: 4370 case RF5372: 4371 case RF5390: 4372 case RF5392: 4373 case RF5592: 4374 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); 4375 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 4376 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 4377 break; 4378 default: 4379 WARN_ONCE(1, "Not supported RF chipet %x for VCO recalibration", 4380 rt2x00dev->chip.rf); 4381 return; 4382 } 4383 4384 usleep_range(1000, 1500); 4385 4386 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin); 4387 if (rt2x00dev->rf_channel <= 14) { 4388 switch (rt2x00dev->default_ant.tx_chain_num) { 4389 case 3: 4390 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); 4391 /* fall through */ 4392 case 2: 4393 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 4394 /* fall through */ 4395 case 1: 4396 default: 4397 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 4398 break; 4399 } 4400 } else { 4401 switch (rt2x00dev->default_ant.tx_chain_num) { 4402 case 3: 4403 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); 4404 /* fall through */ 4405 case 2: 4406 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 4407 /* fall through */ 4408 case 1: 4409 default: 4410 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); 4411 break; 4412 } 4413 } 4414 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 4415 4416 } 4417 EXPORT_SYMBOL_GPL(rt2800_vco_calibration); 4418 4419 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, 4420 struct rt2x00lib_conf *libconf) 4421 { 4422 u32 reg; 4423 4424 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); 4425 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 4426 libconf->conf->short_frame_max_tx_count); 4427 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 4428 libconf->conf->long_frame_max_tx_count); 4429 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 4430 } 4431 4432 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, 4433 struct rt2x00lib_conf *libconf) 4434 { 4435 enum dev_state state = 4436 (libconf->conf->flags & IEEE80211_CONF_PS) ? 4437 STATE_SLEEP : STATE_AWAKE; 4438 u32 reg; 4439 4440 if (state == STATE_SLEEP) { 4441 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); 4442 4443 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); 4444 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); 4445 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 4446 libconf->conf->listen_interval - 1); 4447 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); 4448 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 4449 4450 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 4451 } else { 4452 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); 4453 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 4454 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 4455 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); 4456 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 4457 4458 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 4459 } 4460 } 4461 4462 void rt2800_config(struct rt2x00_dev *rt2x00dev, 4463 struct rt2x00lib_conf *libconf, 4464 const unsigned int flags) 4465 { 4466 /* Always recalculate LNA gain before changing configuration */ 4467 rt2800_config_lna_gain(rt2x00dev, libconf); 4468 4469 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { 4470 rt2800_config_channel(rt2x00dev, libconf->conf, 4471 &libconf->rf, &libconf->channel); 4472 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 4473 libconf->conf->power_level); 4474 } 4475 if (flags & IEEE80211_CONF_CHANGE_POWER) 4476 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 4477 libconf->conf->power_level); 4478 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 4479 rt2800_config_retry_limit(rt2x00dev, libconf); 4480 if (flags & IEEE80211_CONF_CHANGE_PS) 4481 rt2800_config_ps(rt2x00dev, libconf); 4482 } 4483 EXPORT_SYMBOL_GPL(rt2800_config); 4484 4485 /* 4486 * Link tuning 4487 */ 4488 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 4489 { 4490 u32 reg; 4491 4492 /* 4493 * Update FCS error count from register. 4494 */ 4495 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); 4496 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); 4497 } 4498 EXPORT_SYMBOL_GPL(rt2800_link_stats); 4499 4500 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 4501 { 4502 u8 vgc; 4503 4504 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 4505 if (rt2x00_rt(rt2x00dev, RT3070) || 4506 rt2x00_rt(rt2x00dev, RT3071) || 4507 rt2x00_rt(rt2x00dev, RT3090) || 4508 rt2x00_rt(rt2x00dev, RT3290) || 4509 rt2x00_rt(rt2x00dev, RT3390) || 4510 rt2x00_rt(rt2x00dev, RT3572) || 4511 rt2x00_rt(rt2x00dev, RT3593) || 4512 rt2x00_rt(rt2x00dev, RT5390) || 4513 rt2x00_rt(rt2x00dev, RT5392) || 4514 rt2x00_rt(rt2x00dev, RT5592)) 4515 vgc = 0x1c + (2 * rt2x00dev->lna_gain); 4516 else 4517 vgc = 0x2e + rt2x00dev->lna_gain; 4518 } else { /* 5GHZ band */ 4519 if (rt2x00_rt(rt2x00dev, RT3593)) 4520 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3; 4521 else if (rt2x00_rt(rt2x00dev, RT5592)) 4522 vgc = 0x24 + (2 * rt2x00dev->lna_gain); 4523 else { 4524 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4525 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3; 4526 else 4527 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3; 4528 } 4529 } 4530 4531 return vgc; 4532 } 4533 4534 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, 4535 struct link_qual *qual, u8 vgc_level) 4536 { 4537 if (qual->vgc_level != vgc_level) { 4538 if (rt2x00_rt(rt2x00dev, RT3572) || 4539 rt2x00_rt(rt2x00dev, RT3593)) { 4540 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, 4541 vgc_level); 4542 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 4543 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a); 4544 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level); 4545 } else { 4546 rt2800_bbp_write(rt2x00dev, 66, vgc_level); 4547 } 4548 4549 qual->vgc_level = vgc_level; 4550 qual->vgc_level_reg = vgc_level; 4551 } 4552 } 4553 4554 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 4555 { 4556 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); 4557 } 4558 EXPORT_SYMBOL_GPL(rt2800_reset_tuner); 4559 4560 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 4561 const u32 count) 4562 { 4563 u8 vgc; 4564 4565 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) 4566 return; 4567 4568 /* When RSSI is better than a certain threshold, increase VGC 4569 * with a chip specific value in order to improve the balance 4570 * between sensibility and noise isolation. 4571 */ 4572 4573 vgc = rt2800_get_default_vgc(rt2x00dev); 4574 4575 switch (rt2x00dev->chip.rt) { 4576 case RT3572: 4577 case RT3593: 4578 if (qual->rssi > -65) { 4579 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) 4580 vgc += 0x20; 4581 else 4582 vgc += 0x10; 4583 } 4584 break; 4585 4586 case RT5592: 4587 if (qual->rssi > -65) 4588 vgc += 0x20; 4589 break; 4590 4591 default: 4592 if (qual->rssi > -80) 4593 vgc += 0x10; 4594 break; 4595 } 4596 4597 rt2800_set_vgc(rt2x00dev, qual, vgc); 4598 } 4599 EXPORT_SYMBOL_GPL(rt2800_link_tuner); 4600 4601 /* 4602 * Initialization functions. 4603 */ 4604 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 4605 { 4606 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 4607 u32 reg; 4608 u16 eeprom; 4609 unsigned int i; 4610 int ret; 4611 4612 rt2800_disable_wpdma(rt2x00dev); 4613 4614 ret = rt2800_drv_init_registers(rt2x00dev); 4615 if (ret) 4616 return ret; 4617 4618 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); 4619 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 4620 4621 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 4622 4623 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); 4624 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); 4625 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); 4626 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); 4627 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); 4628 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 4629 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 4630 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 4631 4632 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); 4633 4634 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); 4635 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); 4636 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 4637 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 4638 4639 if (rt2x00_rt(rt2x00dev, RT3290)) { 4640 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); 4641 if (rt2x00_get_field32(reg, WLAN_EN) == 1) { 4642 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); 4643 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 4644 } 4645 4646 rt2800_register_read(rt2x00dev, CMB_CTRL, ®); 4647 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { 4648 rt2x00_set_field32(®, LDO0_EN, 1); 4649 rt2x00_set_field32(®, LDO_BGSEL, 3); 4650 rt2800_register_write(rt2x00dev, CMB_CTRL, reg); 4651 } 4652 4653 rt2800_register_read(rt2x00dev, OSC_CTRL, ®); 4654 rt2x00_set_field32(®, OSC_ROSC_EN, 1); 4655 rt2x00_set_field32(®, OSC_CAL_REQ, 1); 4656 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); 4657 rt2800_register_write(rt2x00dev, OSC_CTRL, reg); 4658 4659 rt2800_register_read(rt2x00dev, COEX_CFG0, ®); 4660 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); 4661 rt2800_register_write(rt2x00dev, COEX_CFG0, reg); 4662 4663 rt2800_register_read(rt2x00dev, COEX_CFG2, ®); 4664 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); 4665 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); 4666 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); 4667 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); 4668 rt2800_register_write(rt2x00dev, COEX_CFG2, reg); 4669 4670 rt2800_register_read(rt2x00dev, PLL_CTRL, ®); 4671 rt2x00_set_field32(®, PLL_CONTROL, 1); 4672 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); 4673 } 4674 4675 if (rt2x00_rt(rt2x00dev, RT3071) || 4676 rt2x00_rt(rt2x00dev, RT3090) || 4677 rt2x00_rt(rt2x00dev, RT3290) || 4678 rt2x00_rt(rt2x00dev, RT3390)) { 4679 4680 if (rt2x00_rt(rt2x00dev, RT3290)) 4681 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 4682 0x00000404); 4683 else 4684 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 4685 0x00000400); 4686 4687 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 4688 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 4689 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 4690 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 4691 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, 4692 &eeprom); 4693 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 4694 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 4695 0x0000002c); 4696 else 4697 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 4698 0x0000000f); 4699 } else { 4700 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 4701 } 4702 } else if (rt2x00_rt(rt2x00dev, RT3070)) { 4703 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 4704 4705 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 4706 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 4707 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); 4708 } else { 4709 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 4710 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 4711 } 4712 } else if (rt2800_is_305x_soc(rt2x00dev)) { 4713 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 4714 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 4715 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); 4716 } else if (rt2x00_rt(rt2x00dev, RT3352)) { 4717 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 4718 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 4719 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 4720 } else if (rt2x00_rt(rt2x00dev, RT3572)) { 4721 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 4722 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 4723 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 4724 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 4725 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 4726 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) { 4727 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, 4728 &eeprom); 4729 if (rt2x00_get_field16(eeprom, 4730 EEPROM_NIC_CONF1_DAC_TEST)) 4731 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 4732 0x0000001f); 4733 else 4734 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 4735 0x0000000f); 4736 } else { 4737 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 4738 0x00000000); 4739 } 4740 } else if (rt2x00_rt(rt2x00dev, RT5390) || 4741 rt2x00_rt(rt2x00dev, RT5392)) { 4742 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 4743 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 4744 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 4745 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 4746 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 4747 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 4748 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 4749 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 4750 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 4751 } else { 4752 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 4753 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 4754 } 4755 4756 rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®); 4757 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); 4758 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); 4759 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); 4760 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); 4761 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); 4762 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); 4763 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); 4764 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); 4765 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); 4766 4767 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®); 4768 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 4769 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); 4770 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 4771 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 4772 4773 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®); 4774 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 4775 if (rt2x00_is_usb(rt2x00dev)) { 4776 drv_data->max_psdu = 3; 4777 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || 4778 rt2x00_rt(rt2x00dev, RT2883) || 4779 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) { 4780 drv_data->max_psdu = 2; 4781 } else { 4782 drv_data->max_psdu = 1; 4783 } 4784 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu); 4785 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); 4786 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); 4787 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 4788 4789 rt2800_register_read(rt2x00dev, LED_CFG, ®); 4790 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); 4791 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); 4792 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); 4793 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); 4794 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); 4795 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); 4796 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); 4797 rt2800_register_write(rt2x00dev, LED_CFG, reg); 4798 4799 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 4800 4801 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); 4802 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); 4803 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); 4804 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); 4805 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); 4806 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); 4807 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); 4808 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 4809 4810 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); 4811 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); 4812 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); 4813 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); 4814 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); 4815 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); 4816 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 4817 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 4818 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 4819 4820 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); 4821 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); 4822 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); 4823 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); 4824 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 4825 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4826 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4827 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); 4828 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4829 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); 4830 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); 4831 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 4832 4833 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); 4834 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); 4835 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); 4836 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); 4837 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 4838 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4839 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4840 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); 4841 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4842 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); 4843 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); 4844 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 4845 4846 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); 4847 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 4848 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); 4849 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); 4850 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 4851 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4852 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4853 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 4854 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4855 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 4856 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); 4857 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 4858 4859 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); 4860 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 4861 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); 4862 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); 4863 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 4864 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4865 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4866 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 4867 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4868 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 4869 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); 4870 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 4871 4872 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); 4873 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 4874 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); 4875 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); 4876 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 4877 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4878 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4879 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 4880 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4881 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 4882 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); 4883 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 4884 4885 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); 4886 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 4887 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); 4888 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); 4889 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 4890 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4891 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4892 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 4893 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4894 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 4895 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); 4896 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 4897 4898 if (rt2x00_is_usb(rt2x00dev)) { 4899 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); 4900 4901 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); 4902 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 4903 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 4904 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 4905 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 4906 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); 4907 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); 4908 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); 4909 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); 4910 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); 4911 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 4912 } 4913 4914 /* 4915 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 4916 * although it is reserved. 4917 */ 4918 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, ®); 4919 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); 4920 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); 4921 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); 4922 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); 4923 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); 4924 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); 4925 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); 4926 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); 4927 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); 4928 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); 4929 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); 4930 4931 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; 4932 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); 4933 4934 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); 4935 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); 4936 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, 4937 IEEE80211_MAX_RTS_THRESHOLD); 4938 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1); 4939 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 4940 4941 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 4942 4943 /* 4944 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS 4945 * time should be set to 16. However, the original Ralink driver uses 4946 * 16 for both and indeed using a value of 10 for CCK SIFS results in 4947 * connection problems with 11g + CTS protection. Hence, use the same 4948 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. 4949 */ 4950 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); 4951 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); 4952 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); 4953 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); 4954 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); 4955 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); 4956 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 4957 4958 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 4959 4960 /* 4961 * ASIC will keep garbage value after boot, clear encryption keys. 4962 */ 4963 for (i = 0; i < 4; i++) 4964 rt2800_register_write(rt2x00dev, 4965 SHARED_KEY_MODE_ENTRY(i), 0); 4966 4967 for (i = 0; i < 256; i++) { 4968 rt2800_config_wcid(rt2x00dev, NULL, i); 4969 rt2800_delete_wcid_attr(rt2x00dev, i); 4970 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 4971 } 4972 4973 /* 4974 * Clear all beacons 4975 */ 4976 for (i = 0; i < 8; i++) 4977 rt2800_clear_beacon_register(rt2x00dev, i); 4978 4979 if (rt2x00_is_usb(rt2x00dev)) { 4980 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); 4981 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); 4982 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 4983 } else if (rt2x00_is_pcie(rt2x00dev)) { 4984 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); 4985 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); 4986 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 4987 } 4988 4989 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®); 4990 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); 4991 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); 4992 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); 4993 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); 4994 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); 4995 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); 4996 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); 4997 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); 4998 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); 4999 5000 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®); 5001 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); 5002 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); 5003 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); 5004 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); 5005 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); 5006 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); 5007 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); 5008 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); 5009 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); 5010 5011 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®); 5012 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); 5013 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); 5014 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); 5015 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); 5016 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); 5017 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); 5018 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); 5019 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); 5020 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); 5021 5022 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®); 5023 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); 5024 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); 5025 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); 5026 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); 5027 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); 5028 5029 /* 5030 * Do not force the BA window size, we use the TXWI to set it 5031 */ 5032 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, ®); 5033 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); 5034 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); 5035 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); 5036 5037 /* 5038 * We must clear the error counters. 5039 * These registers are cleared on read, 5040 * so we may pass a useless variable to store the value. 5041 */ 5042 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); 5043 rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®); 5044 rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®); 5045 rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®); 5046 rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®); 5047 rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®); 5048 5049 /* 5050 * Setup leadtime for pre tbtt interrupt to 6ms 5051 */ 5052 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, ®); 5053 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); 5054 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); 5055 5056 /* 5057 * Set up channel statistics timer 5058 */ 5059 rt2800_register_read(rt2x00dev, CH_TIME_CFG, ®); 5060 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); 5061 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); 5062 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); 5063 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); 5064 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); 5065 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); 5066 5067 return 0; 5068 } 5069 5070 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) 5071 { 5072 unsigned int i; 5073 u32 reg; 5074 5075 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 5076 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®); 5077 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) 5078 return 0; 5079 5080 udelay(REGISTER_BUSY_DELAY); 5081 } 5082 5083 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n"); 5084 return -EACCES; 5085 } 5086 5087 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 5088 { 5089 unsigned int i; 5090 u8 value; 5091 5092 /* 5093 * BBP was enabled after firmware was loaded, 5094 * but we need to reactivate it now. 5095 */ 5096 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 5097 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 5098 msleep(1); 5099 5100 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 5101 rt2800_bbp_read(rt2x00dev, 0, &value); 5102 if ((value != 0xff) && (value != 0x00)) 5103 return 0; 5104 udelay(REGISTER_BUSY_DELAY); 5105 } 5106 5107 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 5108 return -EACCES; 5109 } 5110 5111 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev) 5112 { 5113 u8 value; 5114 5115 rt2800_bbp_read(rt2x00dev, 4, &value); 5116 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); 5117 rt2800_bbp_write(rt2x00dev, 4, value); 5118 } 5119 5120 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev) 5121 { 5122 rt2800_bbp_write(rt2x00dev, 142, 1); 5123 rt2800_bbp_write(rt2x00dev, 143, 57); 5124 } 5125 5126 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev) 5127 { 5128 const u8 glrt_table[] = { 5129 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */ 5130 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */ 5131 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */ 5132 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */ 5133 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */ 5134 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */ 5135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */ 5136 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */ 5137 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */ 5138 }; 5139 int i; 5140 5141 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) { 5142 rt2800_bbp_write(rt2x00dev, 195, 128 + i); 5143 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]); 5144 } 5145 }; 5146 5147 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev) 5148 { 5149 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 5150 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5151 rt2800_bbp_write(rt2x00dev, 68, 0x0B); 5152 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5153 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5154 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5155 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5156 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5157 rt2800_bbp_write(rt2x00dev, 83, 0x6A); 5158 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5159 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5160 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5161 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5162 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5163 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5164 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5165 } 5166 5167 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev) 5168 { 5169 u16 eeprom; 5170 u8 value; 5171 5172 rt2800_bbp_read(rt2x00dev, 138, &value); 5173 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 5174 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 5175 value |= 0x20; 5176 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 5177 value &= ~0x02; 5178 rt2800_bbp_write(rt2x00dev, 138, value); 5179 } 5180 5181 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev) 5182 { 5183 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5184 5185 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5186 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5187 5188 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5189 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5190 5191 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5192 5193 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 5194 rt2800_bbp_write(rt2x00dev, 80, 0x08); 5195 5196 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5197 5198 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5199 5200 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5201 5202 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5203 5204 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5205 5206 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5207 5208 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5209 5210 rt2800_bbp_write(rt2x00dev, 105, 0x01); 5211 5212 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5213 } 5214 5215 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev) 5216 { 5217 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5218 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5219 5220 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 5221 rt2800_bbp_write(rt2x00dev, 69, 0x16); 5222 rt2800_bbp_write(rt2x00dev, 73, 0x12); 5223 } else { 5224 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5225 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5226 } 5227 5228 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5229 5230 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5231 5232 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5233 5234 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5235 5236 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 5237 rt2800_bbp_write(rt2x00dev, 84, 0x19); 5238 else 5239 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5240 5241 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5242 5243 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5244 5245 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5246 5247 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5248 5249 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5250 5251 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5252 } 5253 5254 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev) 5255 { 5256 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5257 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5258 5259 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5260 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5261 5262 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5263 5264 rt2800_bbp_write(rt2x00dev, 79, 0x13); 5265 rt2800_bbp_write(rt2x00dev, 80, 0x05); 5266 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5267 5268 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5269 5270 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5271 5272 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5273 5274 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5275 5276 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5277 5278 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5279 5280 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 5281 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 5282 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E)) 5283 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5284 else 5285 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5286 5287 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5288 5289 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5290 5291 if (rt2x00_rt(rt2x00dev, RT3071) || 5292 rt2x00_rt(rt2x00dev, RT3090)) 5293 rt2800_disable_unused_dac_adc(rt2x00dev); 5294 } 5295 5296 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev) 5297 { 5298 u8 value; 5299 5300 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 5301 5302 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5303 5304 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5305 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5306 5307 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 5308 5309 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5310 rt2800_bbp_write(rt2x00dev, 73, 0x13); 5311 rt2800_bbp_write(rt2x00dev, 75, 0x46); 5312 rt2800_bbp_write(rt2x00dev, 76, 0x28); 5313 5314 rt2800_bbp_write(rt2x00dev, 77, 0x58); 5315 5316 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5317 5318 rt2800_bbp_write(rt2x00dev, 74, 0x0b); 5319 rt2800_bbp_write(rt2x00dev, 79, 0x18); 5320 rt2800_bbp_write(rt2x00dev, 80, 0x09); 5321 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5322 5323 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5324 5325 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 5326 5327 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 5328 5329 rt2800_bbp_write(rt2x00dev, 86, 0x38); 5330 5331 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5332 5333 rt2800_bbp_write(rt2x00dev, 92, 0x02); 5334 5335 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5336 5337 rt2800_bbp_write(rt2x00dev, 104, 0x92); 5338 5339 rt2800_bbp_write(rt2x00dev, 105, 0x1c); 5340 5341 rt2800_bbp_write(rt2x00dev, 106, 0x03); 5342 5343 rt2800_bbp_write(rt2x00dev, 128, 0x12); 5344 5345 rt2800_bbp_write(rt2x00dev, 67, 0x24); 5346 rt2800_bbp_write(rt2x00dev, 143, 0x04); 5347 rt2800_bbp_write(rt2x00dev, 142, 0x99); 5348 rt2800_bbp_write(rt2x00dev, 150, 0x30); 5349 rt2800_bbp_write(rt2x00dev, 151, 0x2e); 5350 rt2800_bbp_write(rt2x00dev, 152, 0x20); 5351 rt2800_bbp_write(rt2x00dev, 153, 0x34); 5352 rt2800_bbp_write(rt2x00dev, 154, 0x40); 5353 rt2800_bbp_write(rt2x00dev, 155, 0x3b); 5354 rt2800_bbp_write(rt2x00dev, 253, 0x04); 5355 5356 rt2800_bbp_read(rt2x00dev, 47, &value); 5357 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1); 5358 rt2800_bbp_write(rt2x00dev, 47, value); 5359 5360 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */ 5361 rt2800_bbp_read(rt2x00dev, 3, &value); 5362 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1); 5363 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1); 5364 rt2800_bbp_write(rt2x00dev, 3, value); 5365 } 5366 5367 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) 5368 { 5369 rt2800_bbp_write(rt2x00dev, 3, 0x00); 5370 rt2800_bbp_write(rt2x00dev, 4, 0x50); 5371 5372 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5373 5374 rt2800_bbp_write(rt2x00dev, 47, 0x48); 5375 5376 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5377 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5378 5379 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 5380 5381 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5382 rt2800_bbp_write(rt2x00dev, 73, 0x13); 5383 rt2800_bbp_write(rt2x00dev, 75, 0x46); 5384 rt2800_bbp_write(rt2x00dev, 76, 0x28); 5385 5386 rt2800_bbp_write(rt2x00dev, 77, 0x59); 5387 5388 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5389 5390 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 5391 rt2800_bbp_write(rt2x00dev, 80, 0x08); 5392 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5393 5394 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5395 5396 if (rt2x00_rt(rt2x00dev, RT5350)) { 5397 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 5398 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 5399 } else { 5400 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5401 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5402 } 5403 5404 rt2800_bbp_write(rt2x00dev, 86, 0x38); 5405 5406 rt2800_bbp_write(rt2x00dev, 88, 0x90); 5407 5408 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5409 5410 rt2800_bbp_write(rt2x00dev, 92, 0x02); 5411 5412 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5413 5414 rt2800_bbp_write(rt2x00dev, 104, 0x92); 5415 5416 if (rt2x00_rt(rt2x00dev, RT5350)) { 5417 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 5418 rt2800_bbp_write(rt2x00dev, 106, 0x03); 5419 } else { 5420 rt2800_bbp_write(rt2x00dev, 105, 0x34); 5421 rt2800_bbp_write(rt2x00dev, 106, 0x05); 5422 } 5423 5424 rt2800_bbp_write(rt2x00dev, 120, 0x50); 5425 5426 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 5427 5428 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 5429 /* Set ITxBF timeout to 0x9c40=1000msec */ 5430 rt2800_bbp_write(rt2x00dev, 179, 0x02); 5431 rt2800_bbp_write(rt2x00dev, 180, 0x00); 5432 rt2800_bbp_write(rt2x00dev, 182, 0x40); 5433 rt2800_bbp_write(rt2x00dev, 180, 0x01); 5434 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 5435 rt2800_bbp_write(rt2x00dev, 179, 0x00); 5436 /* Reprogram the inband interface to put right values in RXWI */ 5437 rt2800_bbp_write(rt2x00dev, 142, 0x04); 5438 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 5439 rt2800_bbp_write(rt2x00dev, 142, 0x06); 5440 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 5441 rt2800_bbp_write(rt2x00dev, 142, 0x07); 5442 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 5443 rt2800_bbp_write(rt2x00dev, 142, 0x08); 5444 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 5445 5446 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 5447 5448 if (rt2x00_rt(rt2x00dev, RT5350)) { 5449 /* Antenna Software OFDM */ 5450 rt2800_bbp_write(rt2x00dev, 150, 0x40); 5451 /* Antenna Software CCK */ 5452 rt2800_bbp_write(rt2x00dev, 151, 0x30); 5453 rt2800_bbp_write(rt2x00dev, 152, 0xa3); 5454 /* Clear previously selected antenna */ 5455 rt2800_bbp_write(rt2x00dev, 154, 0); 5456 } 5457 } 5458 5459 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev) 5460 { 5461 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5462 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5463 5464 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5465 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5466 5467 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5468 5469 rt2800_bbp_write(rt2x00dev, 79, 0x13); 5470 rt2800_bbp_write(rt2x00dev, 80, 0x05); 5471 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5472 5473 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5474 5475 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5476 5477 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5478 5479 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5480 5481 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5482 5483 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5484 5485 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E)) 5486 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5487 else 5488 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5489 5490 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5491 5492 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5493 5494 rt2800_disable_unused_dac_adc(rt2x00dev); 5495 } 5496 5497 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev) 5498 { 5499 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5500 5501 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5502 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5503 5504 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5505 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5506 5507 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5508 5509 rt2800_bbp_write(rt2x00dev, 79, 0x13); 5510 rt2800_bbp_write(rt2x00dev, 80, 0x05); 5511 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5512 5513 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5514 5515 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5516 5517 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5518 5519 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5520 5521 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5522 5523 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5524 5525 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5526 5527 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5528 5529 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5530 5531 rt2800_disable_unused_dac_adc(rt2x00dev); 5532 } 5533 5534 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev) 5535 { 5536 rt2800_init_bbp_early(rt2x00dev); 5537 5538 rt2800_bbp_write(rt2x00dev, 79, 0x13); 5539 rt2800_bbp_write(rt2x00dev, 80, 0x05); 5540 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5541 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 5542 5543 rt2800_bbp_write(rt2x00dev, 84, 0x19); 5544 5545 /* Enable DC filter */ 5546 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E)) 5547 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5548 } 5549 5550 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) 5551 { 5552 int ant, div_mode; 5553 u16 eeprom; 5554 u8 value; 5555 5556 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 5557 5558 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5559 5560 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5561 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5562 5563 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 5564 5565 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5566 rt2800_bbp_write(rt2x00dev, 73, 0x13); 5567 rt2800_bbp_write(rt2x00dev, 75, 0x46); 5568 rt2800_bbp_write(rt2x00dev, 76, 0x28); 5569 5570 rt2800_bbp_write(rt2x00dev, 77, 0x59); 5571 5572 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5573 5574 rt2800_bbp_write(rt2x00dev, 79, 0x13); 5575 rt2800_bbp_write(rt2x00dev, 80, 0x05); 5576 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5577 5578 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5579 5580 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 5581 5582 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 5583 5584 rt2800_bbp_write(rt2x00dev, 86, 0x38); 5585 5586 if (rt2x00_rt(rt2x00dev, RT5392)) 5587 rt2800_bbp_write(rt2x00dev, 88, 0x90); 5588 5589 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5590 5591 rt2800_bbp_write(rt2x00dev, 92, 0x02); 5592 5593 if (rt2x00_rt(rt2x00dev, RT5392)) { 5594 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 5595 rt2800_bbp_write(rt2x00dev, 98, 0x12); 5596 } 5597 5598 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5599 5600 rt2800_bbp_write(rt2x00dev, 104, 0x92); 5601 5602 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 5603 5604 if (rt2x00_rt(rt2x00dev, RT5390)) 5605 rt2800_bbp_write(rt2x00dev, 106, 0x03); 5606 else if (rt2x00_rt(rt2x00dev, RT5392)) 5607 rt2800_bbp_write(rt2x00dev, 106, 0x12); 5608 else 5609 WARN_ON(1); 5610 5611 rt2800_bbp_write(rt2x00dev, 128, 0x12); 5612 5613 if (rt2x00_rt(rt2x00dev, RT5392)) { 5614 rt2800_bbp_write(rt2x00dev, 134, 0xd0); 5615 rt2800_bbp_write(rt2x00dev, 135, 0xf6); 5616 } 5617 5618 rt2800_disable_unused_dac_adc(rt2x00dev); 5619 5620 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); 5621 div_mode = rt2x00_get_field16(eeprom, 5622 EEPROM_NIC_CONF1_ANT_DIVERSITY); 5623 ant = (div_mode == 3) ? 1 : 0; 5624 5625 /* check if this is a Bluetooth combo card */ 5626 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 5627 u32 reg; 5628 5629 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 5630 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 5631 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); 5632 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); 5633 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); 5634 if (ant == 0) 5635 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); 5636 else if (ant == 1) 5637 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); 5638 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 5639 } 5640 5641 /* This chip has hardware antenna diversity*/ 5642 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) { 5643 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */ 5644 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */ 5645 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */ 5646 } 5647 5648 rt2800_bbp_read(rt2x00dev, 152, &value); 5649 if (ant == 0) 5650 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 5651 else 5652 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 5653 rt2800_bbp_write(rt2x00dev, 152, value); 5654 5655 rt2800_init_freq_calibration(rt2x00dev); 5656 } 5657 5658 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) 5659 { 5660 int ant, div_mode; 5661 u16 eeprom; 5662 u8 value; 5663 5664 rt2800_init_bbp_early(rt2x00dev); 5665 5666 rt2800_bbp_read(rt2x00dev, 105, &value); 5667 rt2x00_set_field8(&value, BBP105_MLD, 5668 rt2x00dev->default_ant.rx_chain_num == 2); 5669 rt2800_bbp_write(rt2x00dev, 105, value); 5670 5671 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 5672 5673 rt2800_bbp_write(rt2x00dev, 20, 0x06); 5674 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5675 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 5676 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 5677 rt2800_bbp_write(rt2x00dev, 69, 0x1A); 5678 rt2800_bbp_write(rt2x00dev, 70, 0x05); 5679 rt2800_bbp_write(rt2x00dev, 73, 0x13); 5680 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 5681 rt2800_bbp_write(rt2x00dev, 75, 0x4F); 5682 rt2800_bbp_write(rt2x00dev, 76, 0x28); 5683 rt2800_bbp_write(rt2x00dev, 77, 0x59); 5684 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 5685 rt2800_bbp_write(rt2x00dev, 86, 0x38); 5686 rt2800_bbp_write(rt2x00dev, 88, 0x90); 5687 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5688 rt2800_bbp_write(rt2x00dev, 92, 0x02); 5689 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 5690 rt2800_bbp_write(rt2x00dev, 98, 0x12); 5691 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 5692 rt2800_bbp_write(rt2x00dev, 104, 0x92); 5693 /* FIXME BBP105 owerwrite */ 5694 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 5695 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5696 rt2800_bbp_write(rt2x00dev, 128, 0x12); 5697 rt2800_bbp_write(rt2x00dev, 134, 0xD0); 5698 rt2800_bbp_write(rt2x00dev, 135, 0xF6); 5699 rt2800_bbp_write(rt2x00dev, 137, 0x0F); 5700 5701 /* Initialize GLRT (Generalized Likehood Radio Test) */ 5702 rt2800_init_bbp_5592_glrt(rt2x00dev); 5703 5704 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 5705 5706 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); 5707 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); 5708 ant = (div_mode == 3) ? 1 : 0; 5709 rt2800_bbp_read(rt2x00dev, 152, &value); 5710 if (ant == 0) { 5711 /* Main antenna */ 5712 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 5713 } else { 5714 /* Auxiliary antenna */ 5715 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 5716 } 5717 rt2800_bbp_write(rt2x00dev, 152, value); 5718 5719 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) { 5720 rt2800_bbp_read(rt2x00dev, 254, &value); 5721 rt2x00_set_field8(&value, BBP254_BIT7, 1); 5722 rt2800_bbp_write(rt2x00dev, 254, value); 5723 } 5724 5725 rt2800_init_freq_calibration(rt2x00dev); 5726 5727 rt2800_bbp_write(rt2x00dev, 84, 0x19); 5728 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 5729 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5730 } 5731 5732 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) 5733 { 5734 unsigned int i; 5735 u16 eeprom; 5736 u8 reg_id; 5737 u8 value; 5738 5739 if (rt2800_is_305x_soc(rt2x00dev)) 5740 rt2800_init_bbp_305x_soc(rt2x00dev); 5741 5742 switch (rt2x00dev->chip.rt) { 5743 case RT2860: 5744 case RT2872: 5745 case RT2883: 5746 rt2800_init_bbp_28xx(rt2x00dev); 5747 break; 5748 case RT3070: 5749 case RT3071: 5750 case RT3090: 5751 rt2800_init_bbp_30xx(rt2x00dev); 5752 break; 5753 case RT3290: 5754 rt2800_init_bbp_3290(rt2x00dev); 5755 break; 5756 case RT3352: 5757 case RT5350: 5758 rt2800_init_bbp_3352(rt2x00dev); 5759 break; 5760 case RT3390: 5761 rt2800_init_bbp_3390(rt2x00dev); 5762 break; 5763 case RT3572: 5764 rt2800_init_bbp_3572(rt2x00dev); 5765 break; 5766 case RT3593: 5767 rt2800_init_bbp_3593(rt2x00dev); 5768 return; 5769 case RT5390: 5770 case RT5392: 5771 rt2800_init_bbp_53xx(rt2x00dev); 5772 break; 5773 case RT5592: 5774 rt2800_init_bbp_5592(rt2x00dev); 5775 return; 5776 } 5777 5778 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 5779 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i, 5780 &eeprom); 5781 5782 if (eeprom != 0xffff && eeprom != 0x0000) { 5783 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 5784 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 5785 rt2800_bbp_write(rt2x00dev, reg_id, value); 5786 } 5787 } 5788 } 5789 5790 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev) 5791 { 5792 u32 reg; 5793 5794 rt2800_register_read(rt2x00dev, OPT_14_CSR, ®); 5795 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); 5796 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 5797 } 5798 5799 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, 5800 u8 filter_target) 5801 { 5802 unsigned int i; 5803 u8 bbp; 5804 u8 rfcsr; 5805 u8 passband; 5806 u8 stopband; 5807 u8 overtuned = 0; 5808 u8 rfcsr24 = (bw40) ? 0x27 : 0x07; 5809 5810 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 5811 5812 rt2800_bbp_read(rt2x00dev, 4, &bbp); 5813 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); 5814 rt2800_bbp_write(rt2x00dev, 4, bbp); 5815 5816 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr); 5817 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); 5818 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 5819 5820 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); 5821 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); 5822 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 5823 5824 /* 5825 * Set power & frequency of passband test tone 5826 */ 5827 rt2800_bbp_write(rt2x00dev, 24, 0); 5828 5829 for (i = 0; i < 100; i++) { 5830 rt2800_bbp_write(rt2x00dev, 25, 0x90); 5831 msleep(1); 5832 5833 rt2800_bbp_read(rt2x00dev, 55, &passband); 5834 if (passband) 5835 break; 5836 } 5837 5838 /* 5839 * Set power & frequency of stopband test tone 5840 */ 5841 rt2800_bbp_write(rt2x00dev, 24, 0x06); 5842 5843 for (i = 0; i < 100; i++) { 5844 rt2800_bbp_write(rt2x00dev, 25, 0x90); 5845 msleep(1); 5846 5847 rt2800_bbp_read(rt2x00dev, 55, &stopband); 5848 5849 if ((passband - stopband) <= filter_target) { 5850 rfcsr24++; 5851 overtuned += ((passband - stopband) == filter_target); 5852 } else 5853 break; 5854 5855 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 5856 } 5857 5858 rfcsr24 -= !!overtuned; 5859 5860 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 5861 return rfcsr24; 5862 } 5863 5864 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev, 5865 const unsigned int rf_reg) 5866 { 5867 u8 rfcsr; 5868 5869 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr); 5870 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1); 5871 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 5872 msleep(1); 5873 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0); 5874 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 5875 } 5876 5877 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev) 5878 { 5879 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5880 u8 filter_tgt_bw20; 5881 u8 filter_tgt_bw40; 5882 u8 rfcsr, bbp; 5883 5884 /* 5885 * TODO: sync filter_tgt values with vendor driver 5886 */ 5887 if (rt2x00_rt(rt2x00dev, RT3070)) { 5888 filter_tgt_bw20 = 0x16; 5889 filter_tgt_bw40 = 0x19; 5890 } else { 5891 filter_tgt_bw20 = 0x13; 5892 filter_tgt_bw40 = 0x15; 5893 } 5894 5895 drv_data->calibration_bw20 = 5896 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20); 5897 drv_data->calibration_bw40 = 5898 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40); 5899 5900 /* 5901 * Save BBP 25 & 26 values for later use in channel switching (for 3052) 5902 */ 5903 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25); 5904 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26); 5905 5906 /* 5907 * Set back to initial state 5908 */ 5909 rt2800_bbp_write(rt2x00dev, 24, 0); 5910 5911 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); 5912 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 5913 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 5914 5915 /* 5916 * Set BBP back to BW20 5917 */ 5918 rt2800_bbp_read(rt2x00dev, 4, &bbp); 5919 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 5920 rt2800_bbp_write(rt2x00dev, 4, bbp); 5921 } 5922 5923 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) 5924 { 5925 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5926 u8 min_gain, rfcsr, bbp; 5927 u16 eeprom; 5928 5929 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); 5930 5931 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 5932 if (rt2x00_rt(rt2x00dev, RT3070) || 5933 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 5934 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 5935 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 5936 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev)) 5937 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 5938 } 5939 5940 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2; 5941 if (drv_data->txmixer_gain_24g >= min_gain) { 5942 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 5943 drv_data->txmixer_gain_24g); 5944 } 5945 5946 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 5947 5948 if (rt2x00_rt(rt2x00dev, RT3090)) { 5949 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 5950 rt2800_bbp_read(rt2x00dev, 138, &bbp); 5951 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 5952 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 5953 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); 5954 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 5955 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); 5956 rt2800_bbp_write(rt2x00dev, 138, bbp); 5957 } 5958 5959 if (rt2x00_rt(rt2x00dev, RT3070)) { 5960 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr); 5961 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) 5962 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); 5963 else 5964 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); 5965 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); 5966 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); 5967 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); 5968 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 5969 } else if (rt2x00_rt(rt2x00dev, RT3071) || 5970 rt2x00_rt(rt2x00dev, RT3090) || 5971 rt2x00_rt(rt2x00dev, RT3390)) { 5972 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 5973 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 5974 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 5975 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 5976 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 5977 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 5978 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 5979 5980 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr); 5981 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); 5982 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); 5983 5984 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr); 5985 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); 5986 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 5987 5988 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr); 5989 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); 5990 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 5991 } 5992 } 5993 5994 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev) 5995 { 5996 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5997 u8 rfcsr; 5998 u8 tx_gain; 5999 6000 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); 6001 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0); 6002 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 6003 6004 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr); 6005 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g, 6006 RFCSR17_TXMIXER_GAIN); 6007 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain); 6008 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 6009 6010 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr); 6011 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); 6012 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); 6013 6014 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr); 6015 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); 6016 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 6017 6018 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 6019 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 6020 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 6021 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 6022 6023 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 6024 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 6025 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 6026 6027 /* TODO: enable stream mode */ 6028 } 6029 6030 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev) 6031 { 6032 u8 reg; 6033 u16 eeprom; 6034 6035 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 6036 rt2800_bbp_read(rt2x00dev, 138, ®); 6037 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 6038 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 6039 rt2x00_set_field8(®, BBP138_RX_ADC1, 0); 6040 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 6041 rt2x00_set_field8(®, BBP138_TX_DAC1, 1); 6042 rt2800_bbp_write(rt2x00dev, 138, reg); 6043 6044 rt2800_rfcsr_read(rt2x00dev, 38, ®); 6045 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); 6046 rt2800_rfcsr_write(rt2x00dev, 38, reg); 6047 6048 rt2800_rfcsr_read(rt2x00dev, 39, ®); 6049 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); 6050 rt2800_rfcsr_write(rt2x00dev, 39, reg); 6051 6052 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6053 6054 rt2800_rfcsr_read(rt2x00dev, 30, ®); 6055 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); 6056 rt2800_rfcsr_write(rt2x00dev, 30, reg); 6057 } 6058 6059 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev) 6060 { 6061 rt2800_rf_init_calibration(rt2x00dev, 30); 6062 6063 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 6064 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 6065 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 6066 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 6067 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 6068 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 6069 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 6070 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 6071 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 6072 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 6073 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 6074 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 6075 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 6076 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 6077 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 6078 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 6079 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 6080 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 6081 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 6082 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 6083 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 6084 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 6085 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 6086 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 6087 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 6088 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 6089 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 6090 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 6091 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 6092 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 6093 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 6094 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 6095 } 6096 6097 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) 6098 { 6099 u8 rfcsr; 6100 u16 eeprom; 6101 u32 reg; 6102 6103 /* XXX vendor driver do this only for 3070 */ 6104 rt2800_rf_init_calibration(rt2x00dev, 30); 6105 6106 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 6107 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 6108 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 6109 rt2800_rfcsr_write(rt2x00dev, 7, 0x60); 6110 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 6111 rt2800_rfcsr_write(rt2x00dev, 10, 0x41); 6112 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 6113 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 6114 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 6115 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 6116 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 6117 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 6118 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 6119 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 6120 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 6121 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 6122 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 6123 rt2800_rfcsr_write(rt2x00dev, 25, 0x03); 6124 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 6125 6126 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 6127 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6128 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 6129 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 6130 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6131 } else if (rt2x00_rt(rt2x00dev, RT3071) || 6132 rt2x00_rt(rt2x00dev, RT3090)) { 6133 rt2800_rfcsr_write(rt2x00dev, 31, 0x14); 6134 6135 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 6136 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 6137 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 6138 6139 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6140 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 6141 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 6142 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { 6143 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, 6144 &eeprom); 6145 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 6146 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 6147 else 6148 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 6149 } 6150 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6151 6152 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); 6153 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 6154 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 6155 } 6156 6157 rt2800_rx_filter_calibration(rt2x00dev); 6158 6159 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 6160 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 6161 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) 6162 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 6163 6164 rt2800_led_open_drain_enable(rt2x00dev); 6165 rt2800_normal_mode_setup_3xxx(rt2x00dev); 6166 } 6167 6168 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) 6169 { 6170 u8 rfcsr; 6171 6172 rt2800_rf_init_calibration(rt2x00dev, 2); 6173 6174 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 6175 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 6176 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 6177 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 6178 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 6179 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3); 6180 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 6181 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 6182 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 6183 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 6184 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 6185 rt2800_rfcsr_write(rt2x00dev, 18, 0x02); 6186 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 6187 rt2800_rfcsr_write(rt2x00dev, 25, 0x83); 6188 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 6189 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 6190 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 6191 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 6192 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 6193 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 6194 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 6195 rt2800_rfcsr_write(rt2x00dev, 34, 0x05); 6196 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 6197 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 6198 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 6199 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 6200 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 6201 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 6202 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 6203 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b); 6204 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 6205 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 6206 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 6207 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 6208 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 6209 rt2800_rfcsr_write(rt2x00dev, 49, 0x98); 6210 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 6211 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 6212 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 6213 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 6214 rt2800_rfcsr_write(rt2x00dev, 56, 0x02); 6215 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 6216 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 6217 rt2800_rfcsr_write(rt2x00dev, 59, 0x09); 6218 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 6219 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); 6220 6221 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr); 6222 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3); 6223 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr); 6224 6225 rt2800_led_open_drain_enable(rt2x00dev); 6226 rt2800_normal_mode_setup_3xxx(rt2x00dev); 6227 } 6228 6229 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) 6230 { 6231 int tx0_int_pa = test_bit(CAPABILITY_INTERNAL_PA_TX0, 6232 &rt2x00dev->cap_flags); 6233 int tx1_int_pa = test_bit(CAPABILITY_INTERNAL_PA_TX1, 6234 &rt2x00dev->cap_flags); 6235 u8 rfcsr; 6236 6237 rt2800_rf_init_calibration(rt2x00dev, 30); 6238 6239 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 6240 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 6241 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 6242 rt2800_rfcsr_write(rt2x00dev, 3, 0x18); 6243 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 6244 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 6245 rt2800_rfcsr_write(rt2x00dev, 6, 0x33); 6246 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 6247 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 6248 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 6249 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2); 6250 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 6251 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 6252 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 6253 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a); 6254 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 6255 rt2800_rfcsr_write(rt2x00dev, 16, 0x01); 6256 rt2800_rfcsr_write(rt2x00dev, 18, 0x45); 6257 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 6258 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 6259 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 6260 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 6261 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 6262 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 6263 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 6264 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 6265 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 6266 rt2800_rfcsr_write(rt2x00dev, 28, 0x03); 6267 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 6268 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 6269 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 6270 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 6271 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 6272 rfcsr = 0x01; 6273 if (!tx0_int_pa) 6274 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1); 6275 if (!tx1_int_pa) 6276 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1); 6277 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 6278 rt2800_rfcsr_write(rt2x00dev, 35, 0x03); 6279 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); 6280 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); 6281 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); 6282 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); 6283 rt2800_rfcsr_write(rt2x00dev, 40, 0x33); 6284 rfcsr = 0x52; 6285 if (tx0_int_pa) { 6286 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1); 6287 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1); 6288 } 6289 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr); 6290 rfcsr = 0x52; 6291 if (tx1_int_pa) { 6292 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1); 6293 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1); 6294 } 6295 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 6296 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); 6297 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); 6298 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); 6299 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd); 6300 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); 6301 rt2800_rfcsr_write(rt2x00dev, 48, 0x14); 6302 rt2800_rfcsr_write(rt2x00dev, 49, 0x00); 6303 rfcsr = 0x2d; 6304 if (!tx0_int_pa) 6305 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1); 6306 if (!tx1_int_pa) 6307 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1); 6308 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 6309 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_int_pa ? 0x7f : 0x52)); 6310 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_int_pa ? 0x00 : 0xc0)); 6311 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_int_pa ? 0x52 : 0xd2)); 6312 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_int_pa ? 0x1b : 0xc0)); 6313 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_int_pa ? 0x7f : 0x52)); 6314 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_int_pa ? 0x00 : 0xc0)); 6315 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_int_pa ? 0x52 : 0x49)); 6316 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_int_pa ? 0x1b : 0xc0)); 6317 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 6318 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 6319 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 6320 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 6321 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 6322 6323 rt2800_rx_filter_calibration(rt2x00dev); 6324 rt2800_led_open_drain_enable(rt2x00dev); 6325 rt2800_normal_mode_setup_3xxx(rt2x00dev); 6326 } 6327 6328 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) 6329 { 6330 u32 reg; 6331 6332 rt2800_rf_init_calibration(rt2x00dev, 30); 6333 6334 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 6335 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 6336 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 6337 rt2800_rfcsr_write(rt2x00dev, 3, 0x62); 6338 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 6339 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); 6340 rt2800_rfcsr_write(rt2x00dev, 6, 0x42); 6341 rt2800_rfcsr_write(rt2x00dev, 7, 0x34); 6342 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 6343 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 6344 rt2800_rfcsr_write(rt2x00dev, 10, 0x61); 6345 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 6346 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); 6347 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); 6348 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 6349 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 6350 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); 6351 rt2800_rfcsr_write(rt2x00dev, 17, 0x94); 6352 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); 6353 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); 6354 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); 6355 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); 6356 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 6357 rt2800_rfcsr_write(rt2x00dev, 23, 0x14); 6358 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 6359 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 6360 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 6361 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 6362 rt2800_rfcsr_write(rt2x00dev, 28, 0x41); 6363 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); 6364 rt2800_rfcsr_write(rt2x00dev, 30, 0x20); 6365 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); 6366 6367 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); 6368 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 6369 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 6370 6371 rt2800_rx_filter_calibration(rt2x00dev); 6372 6373 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) 6374 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 6375 6376 rt2800_led_open_drain_enable(rt2x00dev); 6377 rt2800_normal_mode_setup_3xxx(rt2x00dev); 6378 } 6379 6380 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) 6381 { 6382 u8 rfcsr; 6383 u32 reg; 6384 6385 rt2800_rf_init_calibration(rt2x00dev, 30); 6386 6387 rt2800_rfcsr_write(rt2x00dev, 0, 0x70); 6388 rt2800_rfcsr_write(rt2x00dev, 1, 0x81); 6389 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 6390 rt2800_rfcsr_write(rt2x00dev, 3, 0x02); 6391 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); 6392 rt2800_rfcsr_write(rt2x00dev, 5, 0x05); 6393 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); 6394 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 6395 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 6396 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 6397 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 6398 rt2800_rfcsr_write(rt2x00dev, 12, 0x70); 6399 rt2800_rfcsr_write(rt2x00dev, 13, 0x65); 6400 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); 6401 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 6402 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); 6403 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 6404 rt2800_rfcsr_write(rt2x00dev, 18, 0xac); 6405 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 6406 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 6407 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); 6408 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 6409 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); 6410 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 6411 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 6412 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 6413 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 6414 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 6415 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 6416 rt2800_rfcsr_write(rt2x00dev, 30, 0x09); 6417 rt2800_rfcsr_write(rt2x00dev, 31, 0x10); 6418 6419 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 6420 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 6421 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 6422 6423 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6424 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 6425 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 6426 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6427 msleep(1); 6428 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6429 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 6430 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 6431 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6432 6433 rt2800_rx_filter_calibration(rt2x00dev); 6434 rt2800_led_open_drain_enable(rt2x00dev); 6435 rt2800_normal_mode_setup_3xxx(rt2x00dev); 6436 } 6437 6438 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev) 6439 { 6440 u8 bbp; 6441 bool txbf_enabled = false; /* FIXME */ 6442 6443 rt2800_bbp_read(rt2x00dev, 105, &bbp); 6444 if (rt2x00dev->default_ant.rx_chain_num == 1) 6445 rt2x00_set_field8(&bbp, BBP105_MLD, 0); 6446 else 6447 rt2x00_set_field8(&bbp, BBP105_MLD, 1); 6448 rt2800_bbp_write(rt2x00dev, 105, bbp); 6449 6450 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6451 6452 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6453 rt2800_bbp_write(rt2x00dev, 82, 0x82); 6454 rt2800_bbp_write(rt2x00dev, 106, 0x05); 6455 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6456 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6457 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6458 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6459 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6460 6461 if (txbf_enabled) 6462 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 6463 else 6464 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 6465 6466 /* SNR mapping */ 6467 rt2800_bbp_write(rt2x00dev, 142, 6); 6468 rt2800_bbp_write(rt2x00dev, 143, 160); 6469 rt2800_bbp_write(rt2x00dev, 142, 7); 6470 rt2800_bbp_write(rt2x00dev, 143, 161); 6471 rt2800_bbp_write(rt2x00dev, 142, 8); 6472 rt2800_bbp_write(rt2x00dev, 143, 162); 6473 6474 /* ADC/DAC control */ 6475 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6476 6477 /* RX AGC energy lower bound in log2 */ 6478 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6479 6480 /* FIXME: BBP 105 owerwrite? */ 6481 rt2800_bbp_write(rt2x00dev, 105, 0x04); 6482 6483 } 6484 6485 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) 6486 { 6487 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 6488 u32 reg; 6489 u8 rfcsr; 6490 6491 /* Disable GPIO #4 and #7 function for LAN PE control */ 6492 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); 6493 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); 6494 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); 6495 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 6496 6497 /* Initialize default register values */ 6498 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 6499 rt2800_rfcsr_write(rt2x00dev, 3, 0x80); 6500 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 6501 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 6502 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 6503 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 6504 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 6505 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 6506 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e); 6507 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 6508 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 6509 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 6510 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 6511 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 6512 rt2800_rfcsr_write(rt2x00dev, 32, 0x78); 6513 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b); 6514 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 6515 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0); 6516 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 6517 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 6518 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3); 6519 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 6520 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 6521 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 6522 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 6523 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 6524 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 6525 rt2800_rfcsr_write(rt2x00dev, 53, 0x18); 6526 rt2800_rfcsr_write(rt2x00dev, 54, 0x18); 6527 rt2800_rfcsr_write(rt2x00dev, 55, 0x18); 6528 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 6529 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 6530 6531 /* Initiate calibration */ 6532 /* TODO: use rt2800_rf_init_calibration ? */ 6533 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr); 6534 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 6535 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 6536 6537 rt2800_freq_cal_mode1(rt2x00dev); 6538 6539 rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr); 6540 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1); 6541 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 6542 6543 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6544 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 6545 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 6546 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6547 usleep_range(1000, 1500); 6548 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6549 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 6550 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6551 6552 /* Set initial values for RX filter calibration */ 6553 drv_data->calibration_bw20 = 0x1f; 6554 drv_data->calibration_bw40 = 0x2f; 6555 6556 /* Save BBP 25 & 26 values for later use in channel switching */ 6557 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25); 6558 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26); 6559 6560 rt2800_led_open_drain_enable(rt2x00dev); 6561 rt2800_normal_mode_setup_3593(rt2x00dev); 6562 6563 rt3593_post_bbp_init(rt2x00dev); 6564 6565 /* TODO: enable stream mode support */ 6566 } 6567 6568 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev) 6569 { 6570 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 6571 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 6572 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 6573 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 6574 rt2800_rfcsr_write(rt2x00dev, 4, 0x49); 6575 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 6576 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 6577 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 6578 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 6579 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 6580 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 6581 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 6582 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 6583 if (rt2800_clk_is_20mhz(rt2x00dev)) 6584 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f); 6585 else 6586 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 6587 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 6588 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 6589 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0); 6590 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 6591 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 6592 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 6593 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 6594 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 6595 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 6596 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 6597 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 6598 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 6599 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 6600 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 6601 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0); 6602 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 6603 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 6604 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 6605 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 6606 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 6607 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 6608 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 6609 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 6610 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 6611 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 6612 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 6613 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 6614 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 6615 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 6616 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c); 6617 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6); 6618 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 6619 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 6620 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 6621 rt2800_rfcsr_write(rt2x00dev, 49, 0x80); 6622 rt2800_rfcsr_write(rt2x00dev, 50, 0x00); 6623 rt2800_rfcsr_write(rt2x00dev, 51, 0x00); 6624 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 6625 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 6626 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 6627 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 6628 rt2800_rfcsr_write(rt2x00dev, 56, 0x82); 6629 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 6630 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 6631 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b); 6632 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 6633 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 6634 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 6635 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 6636 } 6637 6638 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) 6639 { 6640 rt2800_rf_init_calibration(rt2x00dev, 2); 6641 6642 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 6643 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 6644 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 6645 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 6646 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 6647 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 6648 else 6649 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 6650 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 6651 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 6652 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 6653 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 6654 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 6655 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 6656 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 6657 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 6658 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 6659 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 6660 6661 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 6662 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 6663 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 6664 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 6665 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 6666 if (rt2x00_is_usb(rt2x00dev) && 6667 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 6668 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 6669 else 6670 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); 6671 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 6672 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 6673 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 6674 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 6675 6676 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 6677 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 6678 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 6679 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 6680 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 6681 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 6682 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 6683 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 6684 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 6685 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 6686 6687 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 6688 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 6689 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); 6690 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); 6691 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 6692 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 6693 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 6694 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 6695 else 6696 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); 6697 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 6698 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 6699 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 6700 6701 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 6702 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 6703 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 6704 else 6705 rt2800_rfcsr_write(rt2x00dev, 53, 0x84); 6706 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 6707 rt2800_rfcsr_write(rt2x00dev, 55, 0x44); 6708 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 6709 rt2800_rfcsr_write(rt2x00dev, 56, 0x42); 6710 else 6711 rt2800_rfcsr_write(rt2x00dev, 56, 0x22); 6712 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 6713 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 6714 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f); 6715 6716 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 6717 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 6718 if (rt2x00_is_usb(rt2x00dev)) 6719 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 6720 else 6721 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5); 6722 } else { 6723 if (rt2x00_is_usb(rt2x00dev)) 6724 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); 6725 else 6726 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5); 6727 } 6728 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 6729 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 6730 6731 rt2800_normal_mode_setup_5xxx(rt2x00dev); 6732 6733 rt2800_led_open_drain_enable(rt2x00dev); 6734 } 6735 6736 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) 6737 { 6738 rt2800_rf_init_calibration(rt2x00dev, 2); 6739 6740 rt2800_rfcsr_write(rt2x00dev, 1, 0x17); 6741 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 6742 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 6743 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 6744 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 6745 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 6746 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 6747 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 6748 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 6749 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 6750 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 6751 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 6752 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 6753 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d); 6754 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 6755 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d); 6756 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 6757 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b); 6758 rt2800_rfcsr_write(rt2x00dev, 24, 0x44); 6759 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 6760 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 6761 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 6762 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 6763 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 6764 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 6765 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 6766 rt2800_rfcsr_write(rt2x00dev, 32, 0x20); 6767 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 6768 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 6769 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 6770 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 6771 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 6772 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 6773 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 6774 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f); 6775 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 6776 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 6777 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 6778 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 6779 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 6780 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 6781 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c); 6782 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 6783 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 6784 rt2800_rfcsr_write(rt2x00dev, 50, 0x94); 6785 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a); 6786 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 6787 rt2800_rfcsr_write(rt2x00dev, 53, 0x44); 6788 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 6789 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 6790 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1); 6791 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 6792 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 6793 rt2800_rfcsr_write(rt2x00dev, 59, 0x07); 6794 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 6795 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 6796 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 6797 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 6798 6799 rt2800_normal_mode_setup_5xxx(rt2x00dev); 6800 6801 rt2800_led_open_drain_enable(rt2x00dev); 6802 } 6803 6804 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev) 6805 { 6806 rt2800_rf_init_calibration(rt2x00dev, 30); 6807 6808 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F); 6809 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 6810 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 6811 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4); 6812 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 6813 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 6814 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 6815 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 6816 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 6817 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D); 6818 rt2800_rfcsr_write(rt2x00dev, 20, 0x10); 6819 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D); 6820 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 6821 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 6822 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 6823 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 6824 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 6825 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 6826 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C); 6827 rt2800_rfcsr_write(rt2x00dev, 53, 0x22); 6828 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 6829 6830 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 6831 msleep(1); 6832 6833 rt2800_freq_cal_mode1(rt2x00dev); 6834 6835 /* Enable DC filter */ 6836 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 6837 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6838 6839 rt2800_normal_mode_setup_5xxx(rt2x00dev); 6840 6841 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C)) 6842 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 6843 6844 rt2800_led_open_drain_enable(rt2x00dev); 6845 } 6846 6847 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) 6848 { 6849 if (rt2800_is_305x_soc(rt2x00dev)) { 6850 rt2800_init_rfcsr_305x_soc(rt2x00dev); 6851 return; 6852 } 6853 6854 switch (rt2x00dev->chip.rt) { 6855 case RT3070: 6856 case RT3071: 6857 case RT3090: 6858 rt2800_init_rfcsr_30xx(rt2x00dev); 6859 break; 6860 case RT3290: 6861 rt2800_init_rfcsr_3290(rt2x00dev); 6862 break; 6863 case RT3352: 6864 rt2800_init_rfcsr_3352(rt2x00dev); 6865 break; 6866 case RT3390: 6867 rt2800_init_rfcsr_3390(rt2x00dev); 6868 break; 6869 case RT3572: 6870 rt2800_init_rfcsr_3572(rt2x00dev); 6871 break; 6872 case RT3593: 6873 rt2800_init_rfcsr_3593(rt2x00dev); 6874 break; 6875 case RT5350: 6876 rt2800_init_rfcsr_5350(rt2x00dev); 6877 break; 6878 case RT5390: 6879 rt2800_init_rfcsr_5390(rt2x00dev); 6880 break; 6881 case RT5392: 6882 rt2800_init_rfcsr_5392(rt2x00dev); 6883 break; 6884 case RT5592: 6885 rt2800_init_rfcsr_5592(rt2x00dev); 6886 break; 6887 } 6888 } 6889 6890 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) 6891 { 6892 u32 reg; 6893 u16 word; 6894 6895 /* 6896 * Initialize MAC registers. 6897 */ 6898 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || 6899 rt2800_init_registers(rt2x00dev))) 6900 return -EIO; 6901 6902 /* 6903 * Wait BBP/RF to wake up. 6904 */ 6905 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev))) 6906 return -EIO; 6907 6908 /* 6909 * Send signal during boot time to initialize firmware. 6910 */ 6911 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 6912 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 6913 if (rt2x00_is_usb(rt2x00dev)) 6914 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 6915 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 6916 msleep(1); 6917 6918 /* 6919 * Make sure BBP is up and running. 6920 */ 6921 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev))) 6922 return -EIO; 6923 6924 /* 6925 * Initialize BBP/RF registers. 6926 */ 6927 rt2800_init_bbp(rt2x00dev); 6928 rt2800_init_rfcsr(rt2x00dev); 6929 6930 if (rt2x00_is_usb(rt2x00dev) && 6931 (rt2x00_rt(rt2x00dev, RT3070) || 6932 rt2x00_rt(rt2x00dev, RT3071) || 6933 rt2x00_rt(rt2x00dev, RT3572))) { 6934 udelay(200); 6935 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); 6936 udelay(10); 6937 } 6938 6939 /* 6940 * Enable RX. 6941 */ 6942 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); 6943 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 6944 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 6945 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 6946 6947 udelay(50); 6948 6949 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); 6950 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 6951 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 6952 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 6953 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 6954 6955 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); 6956 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 6957 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); 6958 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 6959 6960 /* 6961 * Initialize LED control 6962 */ 6963 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word); 6964 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, 6965 word & 0xff, (word >> 8) & 0xff); 6966 6967 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word); 6968 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, 6969 word & 0xff, (word >> 8) & 0xff); 6970 6971 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word); 6972 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, 6973 word & 0xff, (word >> 8) & 0xff); 6974 6975 return 0; 6976 } 6977 EXPORT_SYMBOL_GPL(rt2800_enable_radio); 6978 6979 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) 6980 { 6981 u32 reg; 6982 6983 rt2800_disable_wpdma(rt2x00dev); 6984 6985 /* Wait for DMA, ignore error */ 6986 rt2800_wait_wpdma_ready(rt2x00dev); 6987 6988 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); 6989 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); 6990 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 6991 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 6992 } 6993 EXPORT_SYMBOL_GPL(rt2800_disable_radio); 6994 6995 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 6996 { 6997 u32 reg; 6998 u16 efuse_ctrl_reg; 6999 7000 if (rt2x00_rt(rt2x00dev, RT3290)) 7001 efuse_ctrl_reg = EFUSE_CTRL_3290; 7002 else 7003 efuse_ctrl_reg = EFUSE_CTRL; 7004 7005 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, ®); 7006 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); 7007 } 7008 EXPORT_SYMBOL_GPL(rt2800_efuse_detect); 7009 7010 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) 7011 { 7012 u32 reg; 7013 u16 efuse_ctrl_reg; 7014 u16 efuse_data0_reg; 7015 u16 efuse_data1_reg; 7016 u16 efuse_data2_reg; 7017 u16 efuse_data3_reg; 7018 7019 if (rt2x00_rt(rt2x00dev, RT3290)) { 7020 efuse_ctrl_reg = EFUSE_CTRL_3290; 7021 efuse_data0_reg = EFUSE_DATA0_3290; 7022 efuse_data1_reg = EFUSE_DATA1_3290; 7023 efuse_data2_reg = EFUSE_DATA2_3290; 7024 efuse_data3_reg = EFUSE_DATA3_3290; 7025 } else { 7026 efuse_ctrl_reg = EFUSE_CTRL; 7027 efuse_data0_reg = EFUSE_DATA0; 7028 efuse_data1_reg = EFUSE_DATA1; 7029 efuse_data2_reg = EFUSE_DATA2; 7030 efuse_data3_reg = EFUSE_DATA3; 7031 } 7032 mutex_lock(&rt2x00dev->csr_mutex); 7033 7034 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, ®); 7035 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); 7036 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); 7037 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); 7038 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); 7039 7040 /* Wait until the EEPROM has been loaded */ 7041 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); 7042 /* Apparently the data is read from end to start */ 7043 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, ®); 7044 /* The returned value is in CPU order, but eeprom is le */ 7045 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); 7046 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, ®); 7047 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); 7048 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, ®); 7049 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); 7050 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, ®); 7051 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); 7052 7053 mutex_unlock(&rt2x00dev->csr_mutex); 7054 } 7055 7056 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 7057 { 7058 unsigned int i; 7059 7060 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) 7061 rt2800_efuse_read(rt2x00dev, i); 7062 7063 return 0; 7064 } 7065 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); 7066 7067 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev) 7068 { 7069 u16 word; 7070 7071 if (rt2x00_rt(rt2x00dev, RT3593)) 7072 return 0; 7073 7074 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word); 7075 if ((word & 0x00ff) != 0x00ff) 7076 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL); 7077 7078 return 0; 7079 } 7080 7081 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev) 7082 { 7083 u16 word; 7084 7085 if (rt2x00_rt(rt2x00dev, RT3593)) 7086 return 0; 7087 7088 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word); 7089 if ((word & 0x00ff) != 0x00ff) 7090 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL); 7091 7092 return 0; 7093 } 7094 7095 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) 7096 { 7097 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7098 u16 word; 7099 u8 *mac; 7100 u8 default_lna_gain; 7101 int retval; 7102 7103 /* 7104 * Read the EEPROM. 7105 */ 7106 retval = rt2800_read_eeprom(rt2x00dev); 7107 if (retval) 7108 return retval; 7109 7110 /* 7111 * Start validation of the data that has been read. 7112 */ 7113 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 7114 rt2x00lib_set_mac_address(rt2x00dev, mac); 7115 7116 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word); 7117 if (word == 0xffff) { 7118 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 7119 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); 7120 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); 7121 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 7122 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 7123 } else if (rt2x00_rt(rt2x00dev, RT2860) || 7124 rt2x00_rt(rt2x00dev, RT2872)) { 7125 /* 7126 * There is a max of 2 RX streams for RT28x0 series 7127 */ 7128 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2) 7129 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 7130 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 7131 } 7132 7133 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word); 7134 if (word == 0xffff) { 7135 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); 7136 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); 7137 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0); 7138 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0); 7139 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0); 7140 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0); 7141 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0); 7142 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0); 7143 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0); 7144 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0); 7145 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0); 7146 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0); 7147 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0); 7148 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); 7149 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); 7150 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); 7151 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 7152 } 7153 7154 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); 7155 if ((word & 0x00ff) == 0x00ff) { 7156 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 7157 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 7158 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); 7159 } 7160 if ((word & 0xff00) == 0xff00) { 7161 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, 7162 LED_MODE_TXRX_ACTIVITY); 7163 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); 7164 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 7165 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); 7166 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); 7167 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); 7168 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word); 7169 } 7170 7171 /* 7172 * During the LNA validation we are going to use 7173 * lna0 as correct value. Note that EEPROM_LNA 7174 * is never validated. 7175 */ 7176 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word); 7177 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); 7178 7179 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word); 7180 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) 7181 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); 7182 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) 7183 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); 7184 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); 7185 7186 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev); 7187 7188 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word); 7189 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) 7190 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); 7191 if (!rt2x00_rt(rt2x00dev, RT3593)) { 7192 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || 7193 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) 7194 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, 7195 default_lna_gain); 7196 } 7197 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); 7198 7199 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev); 7200 7201 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word); 7202 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) 7203 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); 7204 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) 7205 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); 7206 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); 7207 7208 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word); 7209 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) 7210 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); 7211 if (!rt2x00_rt(rt2x00dev, RT3593)) { 7212 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || 7213 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) 7214 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, 7215 default_lna_gain); 7216 } 7217 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); 7218 7219 if (rt2x00_rt(rt2x00dev, RT3593)) { 7220 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word); 7221 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 || 7222 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff) 7223 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 7224 default_lna_gain); 7225 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 || 7226 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff) 7227 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 7228 default_lna_gain); 7229 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word); 7230 } 7231 7232 return 0; 7233 } 7234 7235 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) 7236 { 7237 u16 value; 7238 u16 eeprom; 7239 u16 rf; 7240 7241 /* 7242 * Read EEPROM word for configuration. 7243 */ 7244 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 7245 7246 /* 7247 * Identify RF chipset by EEPROM value 7248 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 7249 * RT53xx: defined in "EEPROM_CHIP_ID" field 7250 */ 7251 if (rt2x00_rt(rt2x00dev, RT3290) || 7252 rt2x00_rt(rt2x00dev, RT5390) || 7253 rt2x00_rt(rt2x00dev, RT5392)) 7254 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf); 7255 else if (rt2x00_rt(rt2x00dev, RT3352)) 7256 rf = RF3322; 7257 else if (rt2x00_rt(rt2x00dev, RT5350)) 7258 rf = RF5350; 7259 else 7260 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 7261 7262 switch (rf) { 7263 case RF2820: 7264 case RF2850: 7265 case RF2720: 7266 case RF2750: 7267 case RF3020: 7268 case RF2020: 7269 case RF3021: 7270 case RF3022: 7271 case RF3052: 7272 case RF3053: 7273 case RF3070: 7274 case RF3290: 7275 case RF3320: 7276 case RF3322: 7277 case RF5350: 7278 case RF5360: 7279 case RF5362: 7280 case RF5370: 7281 case RF5372: 7282 case RF5390: 7283 case RF5392: 7284 case RF5592: 7285 break; 7286 default: 7287 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n", 7288 rf); 7289 return -ENODEV; 7290 } 7291 7292 rt2x00_set_rf(rt2x00dev, rf); 7293 7294 /* 7295 * Identify default antenna configuration. 7296 */ 7297 rt2x00dev->default_ant.tx_chain_num = 7298 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); 7299 rt2x00dev->default_ant.rx_chain_num = 7300 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); 7301 7302 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); 7303 7304 if (rt2x00_rt(rt2x00dev, RT3070) || 7305 rt2x00_rt(rt2x00dev, RT3090) || 7306 rt2x00_rt(rt2x00dev, RT3352) || 7307 rt2x00_rt(rt2x00dev, RT3390)) { 7308 value = rt2x00_get_field16(eeprom, 7309 EEPROM_NIC_CONF1_ANT_DIVERSITY); 7310 switch (value) { 7311 case 0: 7312 case 1: 7313 case 2: 7314 rt2x00dev->default_ant.tx = ANTENNA_A; 7315 rt2x00dev->default_ant.rx = ANTENNA_A; 7316 break; 7317 case 3: 7318 rt2x00dev->default_ant.tx = ANTENNA_A; 7319 rt2x00dev->default_ant.rx = ANTENNA_B; 7320 break; 7321 } 7322 } else { 7323 rt2x00dev->default_ant.tx = ANTENNA_A; 7324 rt2x00dev->default_ant.rx = ANTENNA_A; 7325 } 7326 7327 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) { 7328 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */ 7329 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */ 7330 } 7331 7332 /* 7333 * Determine external LNA informations. 7334 */ 7335 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G)) 7336 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); 7337 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G)) 7338 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); 7339 7340 /* 7341 * Detect if this device has an hardware controlled radio. 7342 */ 7343 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO)) 7344 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 7345 7346 /* 7347 * Detect if this device has Bluetooth co-existence. 7348 */ 7349 if (!rt2x00_rt(rt2x00dev, RT3352) && 7350 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) 7351 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); 7352 7353 /* 7354 * Read frequency offset and RF programming sequence. 7355 */ 7356 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); 7357 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 7358 7359 /* 7360 * Store led settings, for correct led behaviour. 7361 */ 7362 #ifdef CONFIG_RT2X00_LIB_LEDS 7363 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 7364 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 7365 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 7366 7367 rt2x00dev->led_mcu_reg = eeprom; 7368 #endif /* CONFIG_RT2X00_LIB_LEDS */ 7369 7370 /* 7371 * Check if support EIRP tx power limit feature. 7372 */ 7373 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom); 7374 7375 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < 7376 EIRP_MAX_TX_POWER_LIMIT) 7377 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); 7378 7379 /* 7380 * Detect if device uses internal or external PA 7381 */ 7382 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); 7383 7384 if (rt2x00_rt(rt2x00dev, RT3352)) { 7385 if (!rt2x00_get_field16(eeprom, 7386 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352)) 7387 __set_bit(CAPABILITY_INTERNAL_PA_TX0, 7388 &rt2x00dev->cap_flags); 7389 if (!rt2x00_get_field16(eeprom, 7390 EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352)) 7391 __set_bit(CAPABILITY_INTERNAL_PA_TX1, 7392 &rt2x00dev->cap_flags); 7393 } 7394 7395 return 0; 7396 } 7397 7398 /* 7399 * RF value list for rt28xx 7400 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) 7401 */ 7402 static const struct rf_channel rf_vals[] = { 7403 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, 7404 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, 7405 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, 7406 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, 7407 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, 7408 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, 7409 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, 7410 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, 7411 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, 7412 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, 7413 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, 7414 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, 7415 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, 7416 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, 7417 7418 /* 802.11 UNI / HyperLan 2 */ 7419 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, 7420 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, 7421 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, 7422 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, 7423 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, 7424 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, 7425 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, 7426 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, 7427 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, 7428 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, 7429 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, 7430 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, 7431 7432 /* 802.11 HyperLan 2 */ 7433 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, 7434 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, 7435 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, 7436 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, 7437 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, 7438 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, 7439 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, 7440 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, 7441 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, 7442 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, 7443 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, 7444 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, 7445 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, 7446 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, 7447 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, 7448 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, 7449 7450 /* 802.11 UNII */ 7451 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, 7452 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, 7453 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, 7454 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, 7455 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, 7456 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, 7457 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, 7458 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, 7459 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, 7460 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, 7461 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, 7462 7463 /* 802.11 Japan */ 7464 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, 7465 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, 7466 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, 7467 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, 7468 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, 7469 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, 7470 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, 7471 }; 7472 7473 /* 7474 * RF value list for rt3xxx 7475 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053) 7476 */ 7477 static const struct rf_channel rf_vals_3x[] = { 7478 {1, 241, 2, 2 }, 7479 {2, 241, 2, 7 }, 7480 {3, 242, 2, 2 }, 7481 {4, 242, 2, 7 }, 7482 {5, 243, 2, 2 }, 7483 {6, 243, 2, 7 }, 7484 {7, 244, 2, 2 }, 7485 {8, 244, 2, 7 }, 7486 {9, 245, 2, 2 }, 7487 {10, 245, 2, 7 }, 7488 {11, 246, 2, 2 }, 7489 {12, 246, 2, 7 }, 7490 {13, 247, 2, 2 }, 7491 {14, 248, 2, 4 }, 7492 7493 /* 802.11 UNI / HyperLan 2 */ 7494 {36, 0x56, 0, 4}, 7495 {38, 0x56, 0, 6}, 7496 {40, 0x56, 0, 8}, 7497 {44, 0x57, 0, 0}, 7498 {46, 0x57, 0, 2}, 7499 {48, 0x57, 0, 4}, 7500 {52, 0x57, 0, 8}, 7501 {54, 0x57, 0, 10}, 7502 {56, 0x58, 0, 0}, 7503 {60, 0x58, 0, 4}, 7504 {62, 0x58, 0, 6}, 7505 {64, 0x58, 0, 8}, 7506 7507 /* 802.11 HyperLan 2 */ 7508 {100, 0x5b, 0, 8}, 7509 {102, 0x5b, 0, 10}, 7510 {104, 0x5c, 0, 0}, 7511 {108, 0x5c, 0, 4}, 7512 {110, 0x5c, 0, 6}, 7513 {112, 0x5c, 0, 8}, 7514 {116, 0x5d, 0, 0}, 7515 {118, 0x5d, 0, 2}, 7516 {120, 0x5d, 0, 4}, 7517 {124, 0x5d, 0, 8}, 7518 {126, 0x5d, 0, 10}, 7519 {128, 0x5e, 0, 0}, 7520 {132, 0x5e, 0, 4}, 7521 {134, 0x5e, 0, 6}, 7522 {136, 0x5e, 0, 8}, 7523 {140, 0x5f, 0, 0}, 7524 7525 /* 802.11 UNII */ 7526 {149, 0x5f, 0, 9}, 7527 {151, 0x5f, 0, 11}, 7528 {153, 0x60, 0, 1}, 7529 {157, 0x60, 0, 5}, 7530 {159, 0x60, 0, 7}, 7531 {161, 0x60, 0, 9}, 7532 {165, 0x61, 0, 1}, 7533 {167, 0x61, 0, 3}, 7534 {169, 0x61, 0, 5}, 7535 {171, 0x61, 0, 7}, 7536 {173, 0x61, 0, 9}, 7537 }; 7538 7539 /* 7540 * RF value list for rt3xxx with Xtal20MHz 7541 * Supports: 2.4 GHz (all) (RF3322) 7542 */ 7543 static const struct rf_channel rf_vals_3x_xtal20[] = { 7544 {1, 0xE2, 2, 0x14}, 7545 {2, 0xE3, 2, 0x14}, 7546 {3, 0xE4, 2, 0x14}, 7547 {4, 0xE5, 2, 0x14}, 7548 {5, 0xE6, 2, 0x14}, 7549 {6, 0xE7, 2, 0x14}, 7550 {7, 0xE8, 2, 0x14}, 7551 {8, 0xE9, 2, 0x14}, 7552 {9, 0xEA, 2, 0x14}, 7553 {10, 0xEB, 2, 0x14}, 7554 {11, 0xEC, 2, 0x14}, 7555 {12, 0xED, 2, 0x14}, 7556 {13, 0xEE, 2, 0x14}, 7557 {14, 0xF0, 2, 0x18}, 7558 }; 7559 7560 static const struct rf_channel rf_vals_5592_xtal20[] = { 7561 /* Channel, N, K, mod, R */ 7562 {1, 482, 4, 10, 3}, 7563 {2, 483, 4, 10, 3}, 7564 {3, 484, 4, 10, 3}, 7565 {4, 485, 4, 10, 3}, 7566 {5, 486, 4, 10, 3}, 7567 {6, 487, 4, 10, 3}, 7568 {7, 488, 4, 10, 3}, 7569 {8, 489, 4, 10, 3}, 7570 {9, 490, 4, 10, 3}, 7571 {10, 491, 4, 10, 3}, 7572 {11, 492, 4, 10, 3}, 7573 {12, 493, 4, 10, 3}, 7574 {13, 494, 4, 10, 3}, 7575 {14, 496, 8, 10, 3}, 7576 {36, 172, 8, 12, 1}, 7577 {38, 173, 0, 12, 1}, 7578 {40, 173, 4, 12, 1}, 7579 {42, 173, 8, 12, 1}, 7580 {44, 174, 0, 12, 1}, 7581 {46, 174, 4, 12, 1}, 7582 {48, 174, 8, 12, 1}, 7583 {50, 175, 0, 12, 1}, 7584 {52, 175, 4, 12, 1}, 7585 {54, 175, 8, 12, 1}, 7586 {56, 176, 0, 12, 1}, 7587 {58, 176, 4, 12, 1}, 7588 {60, 176, 8, 12, 1}, 7589 {62, 177, 0, 12, 1}, 7590 {64, 177, 4, 12, 1}, 7591 {100, 183, 4, 12, 1}, 7592 {102, 183, 8, 12, 1}, 7593 {104, 184, 0, 12, 1}, 7594 {106, 184, 4, 12, 1}, 7595 {108, 184, 8, 12, 1}, 7596 {110, 185, 0, 12, 1}, 7597 {112, 185, 4, 12, 1}, 7598 {114, 185, 8, 12, 1}, 7599 {116, 186, 0, 12, 1}, 7600 {118, 186, 4, 12, 1}, 7601 {120, 186, 8, 12, 1}, 7602 {122, 187, 0, 12, 1}, 7603 {124, 187, 4, 12, 1}, 7604 {126, 187, 8, 12, 1}, 7605 {128, 188, 0, 12, 1}, 7606 {130, 188, 4, 12, 1}, 7607 {132, 188, 8, 12, 1}, 7608 {134, 189, 0, 12, 1}, 7609 {136, 189, 4, 12, 1}, 7610 {138, 189, 8, 12, 1}, 7611 {140, 190, 0, 12, 1}, 7612 {149, 191, 6, 12, 1}, 7613 {151, 191, 10, 12, 1}, 7614 {153, 192, 2, 12, 1}, 7615 {155, 192, 6, 12, 1}, 7616 {157, 192, 10, 12, 1}, 7617 {159, 193, 2, 12, 1}, 7618 {161, 193, 6, 12, 1}, 7619 {165, 194, 2, 12, 1}, 7620 {184, 164, 0, 12, 1}, 7621 {188, 164, 4, 12, 1}, 7622 {192, 165, 8, 12, 1}, 7623 {196, 166, 0, 12, 1}, 7624 }; 7625 7626 static const struct rf_channel rf_vals_5592_xtal40[] = { 7627 /* Channel, N, K, mod, R */ 7628 {1, 241, 2, 10, 3}, 7629 {2, 241, 7, 10, 3}, 7630 {3, 242, 2, 10, 3}, 7631 {4, 242, 7, 10, 3}, 7632 {5, 243, 2, 10, 3}, 7633 {6, 243, 7, 10, 3}, 7634 {7, 244, 2, 10, 3}, 7635 {8, 244, 7, 10, 3}, 7636 {9, 245, 2, 10, 3}, 7637 {10, 245, 7, 10, 3}, 7638 {11, 246, 2, 10, 3}, 7639 {12, 246, 7, 10, 3}, 7640 {13, 247, 2, 10, 3}, 7641 {14, 248, 4, 10, 3}, 7642 {36, 86, 4, 12, 1}, 7643 {38, 86, 6, 12, 1}, 7644 {40, 86, 8, 12, 1}, 7645 {42, 86, 10, 12, 1}, 7646 {44, 87, 0, 12, 1}, 7647 {46, 87, 2, 12, 1}, 7648 {48, 87, 4, 12, 1}, 7649 {50, 87, 6, 12, 1}, 7650 {52, 87, 8, 12, 1}, 7651 {54, 87, 10, 12, 1}, 7652 {56, 88, 0, 12, 1}, 7653 {58, 88, 2, 12, 1}, 7654 {60, 88, 4, 12, 1}, 7655 {62, 88, 6, 12, 1}, 7656 {64, 88, 8, 12, 1}, 7657 {100, 91, 8, 12, 1}, 7658 {102, 91, 10, 12, 1}, 7659 {104, 92, 0, 12, 1}, 7660 {106, 92, 2, 12, 1}, 7661 {108, 92, 4, 12, 1}, 7662 {110, 92, 6, 12, 1}, 7663 {112, 92, 8, 12, 1}, 7664 {114, 92, 10, 12, 1}, 7665 {116, 93, 0, 12, 1}, 7666 {118, 93, 2, 12, 1}, 7667 {120, 93, 4, 12, 1}, 7668 {122, 93, 6, 12, 1}, 7669 {124, 93, 8, 12, 1}, 7670 {126, 93, 10, 12, 1}, 7671 {128, 94, 0, 12, 1}, 7672 {130, 94, 2, 12, 1}, 7673 {132, 94, 4, 12, 1}, 7674 {134, 94, 6, 12, 1}, 7675 {136, 94, 8, 12, 1}, 7676 {138, 94, 10, 12, 1}, 7677 {140, 95, 0, 12, 1}, 7678 {149, 95, 9, 12, 1}, 7679 {151, 95, 11, 12, 1}, 7680 {153, 96, 1, 12, 1}, 7681 {155, 96, 3, 12, 1}, 7682 {157, 96, 5, 12, 1}, 7683 {159, 96, 7, 12, 1}, 7684 {161, 96, 9, 12, 1}, 7685 {165, 97, 1, 12, 1}, 7686 {184, 82, 0, 12, 1}, 7687 {188, 82, 4, 12, 1}, 7688 {192, 82, 8, 12, 1}, 7689 {196, 83, 0, 12, 1}, 7690 }; 7691 7692 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 7693 { 7694 struct hw_mode_spec *spec = &rt2x00dev->spec; 7695 struct channel_info *info; 7696 char *default_power1; 7697 char *default_power2; 7698 char *default_power3; 7699 unsigned int i, tx_chains, rx_chains; 7700 u32 reg; 7701 7702 /* 7703 * Disable powersaving as default. 7704 */ 7705 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 7706 7707 /* 7708 * Change default retry settings to values corresponding more closely 7709 * to rate[0].count setting of minstrel rate control algorithm. 7710 */ 7711 rt2x00dev->hw->wiphy->retry_short = 2; 7712 rt2x00dev->hw->wiphy->retry_long = 2; 7713 7714 /* 7715 * Initialize all hw fields. 7716 */ 7717 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS); 7718 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION); 7719 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); 7720 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); 7721 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); 7722 7723 /* 7724 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices 7725 * unless we are capable of sending the buffered frames out after the 7726 * DTIM transmission using rt2x00lib_beacondone. This will send out 7727 * multicast and broadcast traffic immediately instead of buffering it 7728 * infinitly and thus dropping it after some time. 7729 */ 7730 if (!rt2x00_is_usb(rt2x00dev)) 7731 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); 7732 7733 /* Set MFP if HW crypto is disabled. */ 7734 if (rt2800_hwcrypt_disabled(rt2x00dev)) 7735 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE); 7736 7737 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 7738 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 7739 rt2800_eeprom_addr(rt2x00dev, 7740 EEPROM_MAC_ADDR_0)); 7741 7742 /* 7743 * As rt2800 has a global fallback table we cannot specify 7744 * more then one tx rate per frame but since the hw will 7745 * try several rates (based on the fallback table) we should 7746 * initialize max_report_rates to the maximum number of rates 7747 * we are going to try. Otherwise mac80211 will truncate our 7748 * reported tx rates and the rc algortihm will end up with 7749 * incorrect data. 7750 */ 7751 rt2x00dev->hw->max_rates = 1; 7752 rt2x00dev->hw->max_report_rates = 7; 7753 rt2x00dev->hw->max_rate_tries = 1; 7754 7755 /* 7756 * Initialize hw_mode information. 7757 */ 7758 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 7759 7760 switch (rt2x00dev->chip.rf) { 7761 case RF2720: 7762 case RF2820: 7763 spec->num_channels = 14; 7764 spec->channels = rf_vals; 7765 break; 7766 7767 case RF2750: 7768 case RF2850: 7769 spec->num_channels = ARRAY_SIZE(rf_vals); 7770 spec->channels = rf_vals; 7771 break; 7772 7773 case RF2020: 7774 case RF3020: 7775 case RF3021: 7776 case RF3022: 7777 case RF3070: 7778 case RF3290: 7779 case RF3320: 7780 case RF3322: 7781 case RF5350: 7782 case RF5360: 7783 case RF5362: 7784 case RF5370: 7785 case RF5372: 7786 case RF5390: 7787 case RF5392: 7788 spec->num_channels = 14; 7789 if (rt2800_clk_is_20mhz(rt2x00dev)) 7790 spec->channels = rf_vals_3x_xtal20; 7791 else 7792 spec->channels = rf_vals_3x; 7793 break; 7794 7795 case RF3052: 7796 case RF3053: 7797 spec->num_channels = ARRAY_SIZE(rf_vals_3x); 7798 spec->channels = rf_vals_3x; 7799 break; 7800 7801 case RF5592: 7802 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, ®); 7803 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { 7804 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); 7805 spec->channels = rf_vals_5592_xtal40; 7806 } else { 7807 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20); 7808 spec->channels = rf_vals_5592_xtal20; 7809 } 7810 break; 7811 } 7812 7813 if (WARN_ON_ONCE(!spec->channels)) 7814 return -ENODEV; 7815 7816 spec->supported_bands = SUPPORT_BAND_2GHZ; 7817 if (spec->num_channels > 14) 7818 spec->supported_bands |= SUPPORT_BAND_5GHZ; 7819 7820 /* 7821 * Initialize HT information. 7822 */ 7823 if (!rt2x00_rf(rt2x00dev, RF2020)) 7824 spec->ht.ht_supported = true; 7825 else 7826 spec->ht.ht_supported = false; 7827 7828 spec->ht.cap = 7829 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 7830 IEEE80211_HT_CAP_GRN_FLD | 7831 IEEE80211_HT_CAP_SGI_20 | 7832 IEEE80211_HT_CAP_SGI_40; 7833 7834 tx_chains = rt2x00dev->default_ant.tx_chain_num; 7835 rx_chains = rt2x00dev->default_ant.rx_chain_num; 7836 7837 if (tx_chains >= 2) 7838 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; 7839 7840 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT; 7841 7842 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2; 7843 spec->ht.ampdu_density = 4; 7844 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 7845 if (tx_chains != rx_chains) { 7846 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 7847 spec->ht.mcs.tx_params |= 7848 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; 7849 } 7850 7851 switch (rx_chains) { 7852 case 3: 7853 spec->ht.mcs.rx_mask[2] = 0xff; 7854 case 2: 7855 spec->ht.mcs.rx_mask[1] = 0xff; 7856 case 1: 7857 spec->ht.mcs.rx_mask[0] = 0xff; 7858 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ 7859 break; 7860 } 7861 7862 /* 7863 * Create channel information array 7864 */ 7865 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 7866 if (!info) 7867 return -ENOMEM; 7868 7869 spec->channels_info = info; 7870 7871 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 7872 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 7873 7874 if (rt2x00dev->default_ant.tx_chain_num > 2) 7875 default_power3 = rt2800_eeprom_addr(rt2x00dev, 7876 EEPROM_EXT_TXPOWER_BG3); 7877 else 7878 default_power3 = NULL; 7879 7880 for (i = 0; i < 14; i++) { 7881 info[i].default_power1 = default_power1[i]; 7882 info[i].default_power2 = default_power2[i]; 7883 if (default_power3) 7884 info[i].default_power3 = default_power3[i]; 7885 } 7886 7887 if (spec->num_channels > 14) { 7888 default_power1 = rt2800_eeprom_addr(rt2x00dev, 7889 EEPROM_TXPOWER_A1); 7890 default_power2 = rt2800_eeprom_addr(rt2x00dev, 7891 EEPROM_TXPOWER_A2); 7892 7893 if (rt2x00dev->default_ant.tx_chain_num > 2) 7894 default_power3 = 7895 rt2800_eeprom_addr(rt2x00dev, 7896 EEPROM_EXT_TXPOWER_A3); 7897 else 7898 default_power3 = NULL; 7899 7900 for (i = 14; i < spec->num_channels; i++) { 7901 info[i].default_power1 = default_power1[i - 14]; 7902 info[i].default_power2 = default_power2[i - 14]; 7903 if (default_power3) 7904 info[i].default_power3 = default_power3[i - 14]; 7905 } 7906 } 7907 7908 switch (rt2x00dev->chip.rf) { 7909 case RF2020: 7910 case RF3020: 7911 case RF3021: 7912 case RF3022: 7913 case RF3320: 7914 case RF3052: 7915 case RF3053: 7916 case RF3070: 7917 case RF3290: 7918 case RF5350: 7919 case RF5360: 7920 case RF5362: 7921 case RF5370: 7922 case RF5372: 7923 case RF5390: 7924 case RF5392: 7925 case RF5592: 7926 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags); 7927 break; 7928 } 7929 7930 return 0; 7931 } 7932 7933 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) 7934 { 7935 u32 reg; 7936 u32 rt; 7937 u32 rev; 7938 7939 if (rt2x00_rt(rt2x00dev, RT3290)) 7940 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, ®); 7941 else 7942 rt2800_register_read(rt2x00dev, MAC_CSR0, ®); 7943 7944 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); 7945 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); 7946 7947 switch (rt) { 7948 case RT2860: 7949 case RT2872: 7950 case RT2883: 7951 case RT3070: 7952 case RT3071: 7953 case RT3090: 7954 case RT3290: 7955 case RT3352: 7956 case RT3390: 7957 case RT3572: 7958 case RT3593: 7959 case RT5350: 7960 case RT5390: 7961 case RT5392: 7962 case RT5592: 7963 break; 7964 default: 7965 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n", 7966 rt, rev); 7967 return -ENODEV; 7968 } 7969 7970 rt2x00_set_rt(rt2x00dev, rt, rev); 7971 7972 return 0; 7973 } 7974 7975 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) 7976 { 7977 int retval; 7978 u32 reg; 7979 7980 retval = rt2800_probe_rt(rt2x00dev); 7981 if (retval) 7982 return retval; 7983 7984 /* 7985 * Allocate eeprom data. 7986 */ 7987 retval = rt2800_validate_eeprom(rt2x00dev); 7988 if (retval) 7989 return retval; 7990 7991 retval = rt2800_init_eeprom(rt2x00dev); 7992 if (retval) 7993 return retval; 7994 7995 /* 7996 * Enable rfkill polling by setting GPIO direction of the 7997 * rfkill switch GPIO pin correctly. 7998 */ 7999 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 8000 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); 8001 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 8002 8003 /* 8004 * Initialize hw specifications. 8005 */ 8006 retval = rt2800_probe_hw_mode(rt2x00dev); 8007 if (retval) 8008 return retval; 8009 8010 /* 8011 * Set device capabilities. 8012 */ 8013 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); 8014 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags); 8015 if (!rt2x00_is_usb(rt2x00dev)) 8016 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags); 8017 8018 /* 8019 * Set device requirements. 8020 */ 8021 if (!rt2x00_is_soc(rt2x00dev)) 8022 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); 8023 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags); 8024 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags); 8025 if (!rt2800_hwcrypt_disabled(rt2x00dev)) 8026 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); 8027 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 8028 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags); 8029 if (rt2x00_is_usb(rt2x00dev)) 8030 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); 8031 else { 8032 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); 8033 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags); 8034 } 8035 8036 /* 8037 * Set the rssi offset. 8038 */ 8039 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 8040 8041 return 0; 8042 } 8043 EXPORT_SYMBOL_GPL(rt2800_probe_hw); 8044 8045 /* 8046 * IEEE80211 stack callback functions. 8047 */ 8048 void rt2800_get_key_seq(struct ieee80211_hw *hw, 8049 struct ieee80211_key_conf *key, 8050 struct ieee80211_key_seq *seq) 8051 { 8052 struct rt2x00_dev *rt2x00dev = hw->priv; 8053 struct mac_iveiv_entry iveiv_entry; 8054 u32 offset; 8055 8056 if (key->cipher != WLAN_CIPHER_SUITE_TKIP) 8057 return; 8058 8059 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 8060 rt2800_register_multiread(rt2x00dev, offset, 8061 &iveiv_entry, sizeof(iveiv_entry)); 8062 8063 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2); 8064 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4); 8065 } 8066 EXPORT_SYMBOL_GPL(rt2800_get_key_seq); 8067 8068 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) 8069 { 8070 struct rt2x00_dev *rt2x00dev = hw->priv; 8071 u32 reg; 8072 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); 8073 8074 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); 8075 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); 8076 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 8077 8078 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); 8079 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); 8080 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 8081 8082 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); 8083 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); 8084 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 8085 8086 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); 8087 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); 8088 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 8089 8090 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); 8091 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); 8092 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 8093 8094 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); 8095 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); 8096 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 8097 8098 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); 8099 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); 8100 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 8101 8102 return 0; 8103 } 8104 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold); 8105 8106 int rt2800_conf_tx(struct ieee80211_hw *hw, 8107 struct ieee80211_vif *vif, u16 queue_idx, 8108 const struct ieee80211_tx_queue_params *params) 8109 { 8110 struct rt2x00_dev *rt2x00dev = hw->priv; 8111 struct data_queue *queue; 8112 struct rt2x00_field32 field; 8113 int retval; 8114 u32 reg; 8115 u32 offset; 8116 8117 /* 8118 * First pass the configuration through rt2x00lib, that will 8119 * update the queue settings and validate the input. After that 8120 * we are free to update the registers based on the value 8121 * in the queue parameter. 8122 */ 8123 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params); 8124 if (retval) 8125 return retval; 8126 8127 /* 8128 * We only need to perform additional register initialization 8129 * for WMM queues/ 8130 */ 8131 if (queue_idx >= 4) 8132 return 0; 8133 8134 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 8135 8136 /* Update WMM TXOP register */ 8137 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); 8138 field.bit_offset = (queue_idx & 1) * 16; 8139 field.bit_mask = 0xffff << field.bit_offset; 8140 8141 rt2800_register_read(rt2x00dev, offset, ®); 8142 rt2x00_set_field32(®, field, queue->txop); 8143 rt2800_register_write(rt2x00dev, offset, reg); 8144 8145 /* Update WMM registers */ 8146 field.bit_offset = queue_idx * 4; 8147 field.bit_mask = 0xf << field.bit_offset; 8148 8149 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®); 8150 rt2x00_set_field32(®, field, queue->aifs); 8151 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); 8152 8153 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®); 8154 rt2x00_set_field32(®, field, queue->cw_min); 8155 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); 8156 8157 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®); 8158 rt2x00_set_field32(®, field, queue->cw_max); 8159 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); 8160 8161 /* Update EDCA registers */ 8162 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); 8163 8164 rt2800_register_read(rt2x00dev, offset, ®); 8165 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); 8166 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); 8167 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); 8168 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); 8169 rt2800_register_write(rt2x00dev, offset, reg); 8170 8171 return 0; 8172 } 8173 EXPORT_SYMBOL_GPL(rt2800_conf_tx); 8174 8175 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 8176 { 8177 struct rt2x00_dev *rt2x00dev = hw->priv; 8178 u64 tsf; 8179 u32 reg; 8180 8181 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®); 8182 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; 8183 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®); 8184 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); 8185 8186 return tsf; 8187 } 8188 EXPORT_SYMBOL_GPL(rt2800_get_tsf); 8189 8190 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 8191 struct ieee80211_ampdu_params *params) 8192 { 8193 struct ieee80211_sta *sta = params->sta; 8194 enum ieee80211_ampdu_mlme_action action = params->action; 8195 u16 tid = params->tid; 8196 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv; 8197 int ret = 0; 8198 8199 /* 8200 * Don't allow aggregation for stations the hardware isn't aware 8201 * of because tx status reports for frames to an unknown station 8202 * always contain wcid=WCID_END+1 and thus we can't distinguish 8203 * between multiple stations which leads to unwanted situations 8204 * when the hw reorders frames due to aggregation. 8205 */ 8206 if (sta_priv->wcid > WCID_END) 8207 return 1; 8208 8209 switch (action) { 8210 case IEEE80211_AMPDU_RX_START: 8211 case IEEE80211_AMPDU_RX_STOP: 8212 /* 8213 * The hw itself takes care of setting up BlockAck mechanisms. 8214 * So, we only have to allow mac80211 to nagotiate a BlockAck 8215 * agreement. Once that is done, the hw will BlockAck incoming 8216 * AMPDUs without further setup. 8217 */ 8218 break; 8219 case IEEE80211_AMPDU_TX_START: 8220 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 8221 break; 8222 case IEEE80211_AMPDU_TX_STOP_CONT: 8223 case IEEE80211_AMPDU_TX_STOP_FLUSH: 8224 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 8225 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 8226 break; 8227 case IEEE80211_AMPDU_TX_OPERATIONAL: 8228 break; 8229 default: 8230 rt2x00_warn((struct rt2x00_dev *)hw->priv, 8231 "Unknown AMPDU action\n"); 8232 } 8233 8234 return ret; 8235 } 8236 EXPORT_SYMBOL_GPL(rt2800_ampdu_action); 8237 8238 int rt2800_get_survey(struct ieee80211_hw *hw, int idx, 8239 struct survey_info *survey) 8240 { 8241 struct rt2x00_dev *rt2x00dev = hw->priv; 8242 struct ieee80211_conf *conf = &hw->conf; 8243 u32 idle, busy, busy_ext; 8244 8245 if (idx != 0) 8246 return -ENOENT; 8247 8248 survey->channel = conf->chandef.chan; 8249 8250 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle); 8251 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy); 8252 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext); 8253 8254 if (idle || busy) { 8255 survey->filled = SURVEY_INFO_TIME | 8256 SURVEY_INFO_TIME_BUSY | 8257 SURVEY_INFO_TIME_EXT_BUSY; 8258 8259 survey->time = (idle + busy) / 1000; 8260 survey->time_busy = busy / 1000; 8261 survey->time_ext_busy = busy_ext / 1000; 8262 } 8263 8264 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 8265 survey->filled |= SURVEY_INFO_IN_USE; 8266 8267 return 0; 8268 8269 } 8270 EXPORT_SYMBOL_GPL(rt2800_get_survey); 8271 8272 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); 8273 MODULE_VERSION(DRV_VERSION); 8274 MODULE_DESCRIPTION("Ralink RT2800 library"); 8275 MODULE_LICENSE("GPL"); 8276