1 /* 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> 6 7 Based on the original rt2800pci.c and rt2800usb.c. 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 14 <http://rt2x00.serialmonkey.com> 15 16 This program is free software; you can redistribute it and/or modify 17 it under the terms of the GNU General Public License as published by 18 the Free Software Foundation; either version 2 of the License, or 19 (at your option) any later version. 20 21 This program is distributed in the hope that it will be useful, 22 but WITHOUT ANY WARRANTY; without even the implied warranty of 23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 GNU General Public License for more details. 25 26 You should have received a copy of the GNU General Public License 27 along with this program; if not, see <http://www.gnu.org/licenses/>. 28 */ 29 30 /* 31 Module: rt2800lib 32 Abstract: rt2800 generic device routines. 33 */ 34 35 #include <linux/crc-ccitt.h> 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/slab.h> 39 40 #include "rt2x00.h" 41 #include "rt2800lib.h" 42 #include "rt2800.h" 43 44 /* 45 * Register access. 46 * All access to the CSR registers will go through the methods 47 * rt2800_register_read and rt2800_register_write. 48 * BBP and RF register require indirect register access, 49 * and use the CSR registers BBPCSR and RFCSR to achieve this. 50 * These indirect registers work with busy bits, 51 * and we will try maximal REGISTER_BUSY_COUNT times to access 52 * the register while taking a REGISTER_BUSY_DELAY us delay 53 * between each attampt. When the busy bit is still set at that time, 54 * the access attempt is considered to have failed, 55 * and we will print an error. 56 * The _lock versions must be used if you already hold the csr_mutex 57 */ 58 #define WAIT_FOR_BBP(__dev, __reg) \ 59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) 60 #define WAIT_FOR_RFCSR(__dev, __reg) \ 61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) 62 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \ 63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \ 64 (__reg)) 65 #define WAIT_FOR_RF(__dev, __reg) \ 66 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) 67 #define WAIT_FOR_MCU(__dev, __reg) \ 68 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 69 H2M_MAILBOX_CSR_OWNER, (__reg)) 70 71 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) 72 { 73 /* check for rt2872 on SoC */ 74 if (!rt2x00_is_soc(rt2x00dev) || 75 !rt2x00_rt(rt2x00dev, RT2872)) 76 return false; 77 78 /* we know for sure that these rf chipsets are used on rt305x boards */ 79 if (rt2x00_rf(rt2x00dev, RF3020) || 80 rt2x00_rf(rt2x00dev, RF3021) || 81 rt2x00_rf(rt2x00dev, RF3022)) 82 return true; 83 84 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n"); 85 return false; 86 } 87 88 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, 89 const unsigned int word, const u8 value) 90 { 91 u32 reg; 92 93 mutex_lock(&rt2x00dev->csr_mutex); 94 95 /* 96 * Wait until the BBP becomes available, afterwards we 97 * can safely write the new data into the register. 98 */ 99 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 100 reg = 0; 101 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); 102 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 103 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 104 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); 105 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 106 107 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 108 } 109 110 mutex_unlock(&rt2x00dev->csr_mutex); 111 } 112 113 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word) 114 { 115 u32 reg; 116 u8 value; 117 118 mutex_lock(&rt2x00dev->csr_mutex); 119 120 /* 121 * Wait until the BBP becomes available, afterwards we 122 * can safely write the read request into the register. 123 * After the data has been written, we wait until hardware 124 * returns the correct value, if at any time the register 125 * doesn't become available in time, reg will be 0xffffffff 126 * which means we return 0xff to the caller. 127 */ 128 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 129 reg = 0; 130 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 131 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 132 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); 133 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 134 135 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 136 137 WAIT_FOR_BBP(rt2x00dev, ®); 138 } 139 140 value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); 141 142 mutex_unlock(&rt2x00dev->csr_mutex); 143 144 return value; 145 } 146 147 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, 148 const unsigned int word, const u8 value) 149 { 150 u32 reg; 151 152 mutex_lock(&rt2x00dev->csr_mutex); 153 154 /* 155 * Wait until the RFCSR becomes available, afterwards we 156 * can safely write the new data into the register. 157 */ 158 switch (rt2x00dev->chip.rt) { 159 case RT6352: 160 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 161 reg = 0; 162 rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value); 163 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 164 word); 165 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1); 166 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 167 168 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 169 } 170 break; 171 172 default: 173 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 174 reg = 0; 175 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); 176 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 177 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); 178 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 179 180 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 181 } 182 break; 183 } 184 185 mutex_unlock(&rt2x00dev->csr_mutex); 186 } 187 188 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 189 const unsigned int reg, const u8 value) 190 { 191 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value); 192 } 193 194 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev, 195 const unsigned int reg, const u8 value) 196 { 197 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value); 198 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value); 199 } 200 201 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev, 202 const unsigned int reg, const u8 value) 203 { 204 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value); 205 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value); 206 } 207 208 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, 209 const unsigned int word) 210 { 211 u32 reg; 212 u8 value; 213 214 mutex_lock(&rt2x00dev->csr_mutex); 215 216 /* 217 * Wait until the RFCSR becomes available, afterwards we 218 * can safely write the read request into the register. 219 * After the data has been written, we wait until hardware 220 * returns the correct value, if at any time the register 221 * doesn't become available in time, reg will be 0xffffffff 222 * which means we return 0xff to the caller. 223 */ 224 switch (rt2x00dev->chip.rt) { 225 case RT6352: 226 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 227 reg = 0; 228 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 229 word); 230 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0); 231 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 232 233 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 234 235 WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®); 236 } 237 238 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620); 239 break; 240 241 default: 242 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 243 reg = 0; 244 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 245 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); 246 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 247 248 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 249 250 WAIT_FOR_RFCSR(rt2x00dev, ®); 251 } 252 253 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); 254 break; 255 } 256 257 mutex_unlock(&rt2x00dev->csr_mutex); 258 259 return value; 260 } 261 262 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 263 const unsigned int reg) 264 { 265 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6))); 266 } 267 268 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, 269 const unsigned int word, const u32 value) 270 { 271 u32 reg; 272 273 mutex_lock(&rt2x00dev->csr_mutex); 274 275 /* 276 * Wait until the RF becomes available, afterwards we 277 * can safely write the new data into the register. 278 */ 279 if (WAIT_FOR_RF(rt2x00dev, ®)) { 280 reg = 0; 281 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); 282 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); 283 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); 284 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); 285 286 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); 287 rt2x00_rf_write(rt2x00dev, word, value); 288 } 289 290 mutex_unlock(&rt2x00dev->csr_mutex); 291 } 292 293 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { 294 [EEPROM_CHIP_ID] = 0x0000, 295 [EEPROM_VERSION] = 0x0001, 296 [EEPROM_MAC_ADDR_0] = 0x0002, 297 [EEPROM_MAC_ADDR_1] = 0x0003, 298 [EEPROM_MAC_ADDR_2] = 0x0004, 299 [EEPROM_NIC_CONF0] = 0x001a, 300 [EEPROM_NIC_CONF1] = 0x001b, 301 [EEPROM_FREQ] = 0x001d, 302 [EEPROM_LED_AG_CONF] = 0x001e, 303 [EEPROM_LED_ACT_CONF] = 0x001f, 304 [EEPROM_LED_POLARITY] = 0x0020, 305 [EEPROM_NIC_CONF2] = 0x0021, 306 [EEPROM_LNA] = 0x0022, 307 [EEPROM_RSSI_BG] = 0x0023, 308 [EEPROM_RSSI_BG2] = 0x0024, 309 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */ 310 [EEPROM_RSSI_A] = 0x0025, 311 [EEPROM_RSSI_A2] = 0x0026, 312 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */ 313 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027, 314 [EEPROM_TXPOWER_DELTA] = 0x0028, 315 [EEPROM_TXPOWER_BG1] = 0x0029, 316 [EEPROM_TXPOWER_BG2] = 0x0030, 317 [EEPROM_TSSI_BOUND_BG1] = 0x0037, 318 [EEPROM_TSSI_BOUND_BG2] = 0x0038, 319 [EEPROM_TSSI_BOUND_BG3] = 0x0039, 320 [EEPROM_TSSI_BOUND_BG4] = 0x003a, 321 [EEPROM_TSSI_BOUND_BG5] = 0x003b, 322 [EEPROM_TXPOWER_A1] = 0x003c, 323 [EEPROM_TXPOWER_A2] = 0x0053, 324 [EEPROM_TXPOWER_INIT] = 0x0068, 325 [EEPROM_TSSI_BOUND_A1] = 0x006a, 326 [EEPROM_TSSI_BOUND_A2] = 0x006b, 327 [EEPROM_TSSI_BOUND_A3] = 0x006c, 328 [EEPROM_TSSI_BOUND_A4] = 0x006d, 329 [EEPROM_TSSI_BOUND_A5] = 0x006e, 330 [EEPROM_TXPOWER_BYRATE] = 0x006f, 331 [EEPROM_BBP_START] = 0x0078, 332 }; 333 334 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = { 335 [EEPROM_CHIP_ID] = 0x0000, 336 [EEPROM_VERSION] = 0x0001, 337 [EEPROM_MAC_ADDR_0] = 0x0002, 338 [EEPROM_MAC_ADDR_1] = 0x0003, 339 [EEPROM_MAC_ADDR_2] = 0x0004, 340 [EEPROM_NIC_CONF0] = 0x001a, 341 [EEPROM_NIC_CONF1] = 0x001b, 342 [EEPROM_NIC_CONF2] = 0x001c, 343 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020, 344 [EEPROM_FREQ] = 0x0022, 345 [EEPROM_LED_AG_CONF] = 0x0023, 346 [EEPROM_LED_ACT_CONF] = 0x0024, 347 [EEPROM_LED_POLARITY] = 0x0025, 348 [EEPROM_LNA] = 0x0026, 349 [EEPROM_EXT_LNA2] = 0x0027, 350 [EEPROM_RSSI_BG] = 0x0028, 351 [EEPROM_RSSI_BG2] = 0x0029, 352 [EEPROM_RSSI_A] = 0x002a, 353 [EEPROM_RSSI_A2] = 0x002b, 354 [EEPROM_TXPOWER_BG1] = 0x0030, 355 [EEPROM_TXPOWER_BG2] = 0x0037, 356 [EEPROM_EXT_TXPOWER_BG3] = 0x003e, 357 [EEPROM_TSSI_BOUND_BG1] = 0x0045, 358 [EEPROM_TSSI_BOUND_BG2] = 0x0046, 359 [EEPROM_TSSI_BOUND_BG3] = 0x0047, 360 [EEPROM_TSSI_BOUND_BG4] = 0x0048, 361 [EEPROM_TSSI_BOUND_BG5] = 0x0049, 362 [EEPROM_TXPOWER_A1] = 0x004b, 363 [EEPROM_TXPOWER_A2] = 0x0065, 364 [EEPROM_EXT_TXPOWER_A3] = 0x007f, 365 [EEPROM_TSSI_BOUND_A1] = 0x009a, 366 [EEPROM_TSSI_BOUND_A2] = 0x009b, 367 [EEPROM_TSSI_BOUND_A3] = 0x009c, 368 [EEPROM_TSSI_BOUND_A4] = 0x009d, 369 [EEPROM_TSSI_BOUND_A5] = 0x009e, 370 [EEPROM_TXPOWER_BYRATE] = 0x00a0, 371 }; 372 373 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev, 374 const enum rt2800_eeprom_word word) 375 { 376 const unsigned int *map; 377 unsigned int index; 378 379 if (WARN_ONCE(word >= EEPROM_WORD_COUNT, 380 "%s: invalid EEPROM word %d\n", 381 wiphy_name(rt2x00dev->hw->wiphy), word)) 382 return 0; 383 384 if (rt2x00_rt(rt2x00dev, RT3593)) 385 map = rt2800_eeprom_map_ext; 386 else 387 map = rt2800_eeprom_map; 388 389 index = map[word]; 390 391 /* Index 0 is valid only for EEPROM_CHIP_ID. 392 * Otherwise it means that the offset of the 393 * given word is not initialized in the map, 394 * or that the field is not usable on the 395 * actual chipset. 396 */ 397 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0, 398 "%s: invalid access of EEPROM word %d\n", 399 wiphy_name(rt2x00dev->hw->wiphy), word); 400 401 return index; 402 } 403 404 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev, 405 const enum rt2800_eeprom_word word) 406 { 407 unsigned int index; 408 409 index = rt2800_eeprom_word_index(rt2x00dev, word); 410 return rt2x00_eeprom_addr(rt2x00dev, index); 411 } 412 413 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, 414 const enum rt2800_eeprom_word word) 415 { 416 unsigned int index; 417 418 index = rt2800_eeprom_word_index(rt2x00dev, word); 419 return rt2x00_eeprom_read(rt2x00dev, index); 420 } 421 422 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, 423 const enum rt2800_eeprom_word word, u16 data) 424 { 425 unsigned int index; 426 427 index = rt2800_eeprom_word_index(rt2x00dev, word); 428 rt2x00_eeprom_write(rt2x00dev, index, data); 429 } 430 431 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, 432 const enum rt2800_eeprom_word array, 433 unsigned int offset) 434 { 435 unsigned int index; 436 437 index = rt2800_eeprom_word_index(rt2x00dev, array); 438 return rt2x00_eeprom_read(rt2x00dev, index + offset); 439 } 440 441 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) 442 { 443 u32 reg; 444 int i, count; 445 446 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 447 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); 448 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); 449 rt2x00_set_field32(®, WLAN_CLK_EN, 0); 450 rt2x00_set_field32(®, WLAN_EN, 1); 451 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 452 453 udelay(REGISTER_BUSY_DELAY); 454 455 count = 0; 456 do { 457 /* 458 * Check PLL_LD & XTAL_RDY. 459 */ 460 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 461 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 462 if (rt2x00_get_field32(reg, PLL_LD) && 463 rt2x00_get_field32(reg, XTAL_RDY)) 464 break; 465 udelay(REGISTER_BUSY_DELAY); 466 } 467 468 if (i >= REGISTER_BUSY_COUNT) { 469 470 if (count >= 10) 471 return -EIO; 472 473 rt2800_register_write(rt2x00dev, 0x58, 0x018); 474 udelay(REGISTER_BUSY_DELAY); 475 rt2800_register_write(rt2x00dev, 0x58, 0x418); 476 udelay(REGISTER_BUSY_DELAY); 477 rt2800_register_write(rt2x00dev, 0x58, 0x618); 478 udelay(REGISTER_BUSY_DELAY); 479 count++; 480 } else { 481 count = 0; 482 } 483 484 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 485 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); 486 rt2x00_set_field32(®, WLAN_CLK_EN, 1); 487 rt2x00_set_field32(®, WLAN_RESET, 1); 488 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 489 udelay(10); 490 rt2x00_set_field32(®, WLAN_RESET, 0); 491 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 492 udelay(10); 493 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff); 494 } while (count != 0); 495 496 return 0; 497 } 498 499 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 500 const u8 command, const u8 token, 501 const u8 arg0, const u8 arg1) 502 { 503 u32 reg; 504 505 /* 506 * SOC devices don't support MCU requests. 507 */ 508 if (rt2x00_is_soc(rt2x00dev)) 509 return; 510 511 mutex_lock(&rt2x00dev->csr_mutex); 512 513 /* 514 * Wait until the MCU becomes available, afterwards we 515 * can safely write the new data into the register. 516 */ 517 if (WAIT_FOR_MCU(rt2x00dev, ®)) { 518 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); 519 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); 520 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); 521 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); 522 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); 523 524 reg = 0; 525 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); 526 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); 527 } 528 529 mutex_unlock(&rt2x00dev->csr_mutex); 530 } 531 EXPORT_SYMBOL_GPL(rt2800_mcu_request); 532 533 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) 534 { 535 unsigned int i = 0; 536 u32 reg; 537 538 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 539 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 540 if (reg && reg != ~0) 541 return 0; 542 msleep(1); 543 } 544 545 rt2x00_err(rt2x00dev, "Unstable hardware\n"); 546 return -EBUSY; 547 } 548 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); 549 550 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 551 { 552 unsigned int i; 553 u32 reg; 554 555 /* 556 * Some devices are really slow to respond here. Wait a whole second 557 * before timing out. 558 */ 559 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 560 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 561 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 562 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 563 return 0; 564 565 msleep(10); 566 } 567 568 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); 569 return -EACCES; 570 } 571 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); 572 573 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) 574 { 575 u32 reg; 576 577 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 578 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 579 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 580 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 581 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 582 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 583 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 584 } 585 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma); 586 587 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev, 588 unsigned short *txwi_size, 589 unsigned short *rxwi_size) 590 { 591 switch (rt2x00dev->chip.rt) { 592 case RT3593: 593 *txwi_size = TXWI_DESC_SIZE_4WORDS; 594 *rxwi_size = RXWI_DESC_SIZE_5WORDS; 595 break; 596 597 case RT5592: 598 case RT6352: 599 *txwi_size = TXWI_DESC_SIZE_5WORDS; 600 *rxwi_size = RXWI_DESC_SIZE_6WORDS; 601 break; 602 603 default: 604 *txwi_size = TXWI_DESC_SIZE_4WORDS; 605 *rxwi_size = RXWI_DESC_SIZE_4WORDS; 606 break; 607 } 608 } 609 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size); 610 611 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) 612 { 613 u16 fw_crc; 614 u16 crc; 615 616 /* 617 * The last 2 bytes in the firmware array are the crc checksum itself, 618 * this means that we should never pass those 2 bytes to the crc 619 * algorithm. 620 */ 621 fw_crc = (data[len - 2] << 8 | data[len - 1]); 622 623 /* 624 * Use the crc ccitt algorithm. 625 * This will return the same value as the legacy driver which 626 * used bit ordering reversion on the both the firmware bytes 627 * before input input as well as on the final output. 628 * Obviously using crc ccitt directly is much more efficient. 629 */ 630 crc = crc_ccitt(~0, data, len - 2); 631 632 /* 633 * There is a small difference between the crc-itu-t + bitrev and 634 * the crc-ccitt crc calculation. In the latter method the 2 bytes 635 * will be swapped, use swab16 to convert the crc to the correct 636 * value. 637 */ 638 crc = swab16(crc); 639 640 return fw_crc == crc; 641 } 642 643 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, 644 const u8 *data, const size_t len) 645 { 646 size_t offset = 0; 647 size_t fw_len; 648 bool multiple; 649 650 /* 651 * PCI(e) & SOC devices require firmware with a length 652 * of 8kb. USB devices require firmware files with a length 653 * of 4kb. Certain USB chipsets however require different firmware, 654 * which Ralink only provides attached to the original firmware 655 * file. Thus for USB devices, firmware files have a length 656 * which is a multiple of 4kb. The firmware for rt3290 chip also 657 * have a length which is a multiple of 4kb. 658 */ 659 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290)) 660 fw_len = 4096; 661 else 662 fw_len = 8192; 663 664 multiple = true; 665 /* 666 * Validate the firmware length 667 */ 668 if (len != fw_len && (!multiple || (len % fw_len) != 0)) 669 return FW_BAD_LENGTH; 670 671 /* 672 * Check if the chipset requires one of the upper parts 673 * of the firmware. 674 */ 675 if (rt2x00_is_usb(rt2x00dev) && 676 !rt2x00_rt(rt2x00dev, RT2860) && 677 !rt2x00_rt(rt2x00dev, RT2872) && 678 !rt2x00_rt(rt2x00dev, RT3070) && 679 ((len / fw_len) == 1)) 680 return FW_BAD_VERSION; 681 682 /* 683 * 8kb firmware files must be checked as if it were 684 * 2 separate firmware files. 685 */ 686 while (offset < len) { 687 if (!rt2800_check_firmware_crc(data + offset, fw_len)) 688 return FW_BAD_CRC; 689 690 offset += fw_len; 691 } 692 693 return FW_OK; 694 } 695 EXPORT_SYMBOL_GPL(rt2800_check_firmware); 696 697 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, 698 const u8 *data, const size_t len) 699 { 700 unsigned int i; 701 u32 reg; 702 int retval; 703 704 if (rt2x00_rt(rt2x00dev, RT3290)) { 705 retval = rt2800_enable_wlan_rt3290(rt2x00dev); 706 if (retval) 707 return -EBUSY; 708 } 709 710 /* 711 * If driver doesn't wake up firmware here, 712 * rt2800_load_firmware will hang forever when interface is up again. 713 */ 714 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 715 716 /* 717 * Wait for stable hardware. 718 */ 719 if (rt2800_wait_csr_ready(rt2x00dev)) 720 return -EBUSY; 721 722 if (rt2x00_is_pci(rt2x00dev)) { 723 if (rt2x00_rt(rt2x00dev, RT3290) || 724 rt2x00_rt(rt2x00dev, RT3572) || 725 rt2x00_rt(rt2x00dev, RT5390) || 726 rt2x00_rt(rt2x00dev, RT5392)) { 727 reg = rt2800_register_read(rt2x00dev, AUX_CTRL); 728 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); 729 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); 730 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); 731 } 732 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 733 } 734 735 rt2800_disable_wpdma(rt2x00dev); 736 737 /* 738 * Write firmware to the device. 739 */ 740 rt2800_drv_write_firmware(rt2x00dev, data, len); 741 742 /* 743 * Wait for device to stabilize. 744 */ 745 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 746 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL); 747 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 748 break; 749 msleep(1); 750 } 751 752 if (i == REGISTER_BUSY_COUNT) { 753 rt2x00_err(rt2x00dev, "PBF system register not ready\n"); 754 return -EBUSY; 755 } 756 757 /* 758 * Disable DMA, will be reenabled later when enabling 759 * the radio. 760 */ 761 rt2800_disable_wpdma(rt2x00dev); 762 763 /* 764 * Initialize firmware. 765 */ 766 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 767 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 768 if (rt2x00_is_usb(rt2x00dev)) { 769 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 770 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 771 } 772 msleep(1); 773 774 return 0; 775 } 776 EXPORT_SYMBOL_GPL(rt2800_load_firmware); 777 778 void rt2800_write_tx_data(struct queue_entry *entry, 779 struct txentry_desc *txdesc) 780 { 781 __le32 *txwi = rt2800_drv_get_txwi(entry); 782 u32 word; 783 int i; 784 785 /* 786 * Initialize TX Info descriptor 787 */ 788 word = rt2x00_desc_read(txwi, 0); 789 rt2x00_set_field32(&word, TXWI_W0_FRAG, 790 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 791 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 792 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); 793 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); 794 rt2x00_set_field32(&word, TXWI_W0_TS, 795 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 796 rt2x00_set_field32(&word, TXWI_W0_AMPDU, 797 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); 798 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, 799 txdesc->u.ht.mpdu_density); 800 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); 801 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); 802 rt2x00_set_field32(&word, TXWI_W0_BW, 803 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); 804 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, 805 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); 806 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); 807 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); 808 rt2x00_desc_write(txwi, 0, word); 809 810 word = rt2x00_desc_read(txwi, 1); 811 rt2x00_set_field32(&word, TXWI_W1_ACK, 812 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 813 rt2x00_set_field32(&word, TXWI_W1_NSEQ, 814 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 815 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); 816 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 817 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 818 txdesc->key_idx : txdesc->u.ht.wcid); 819 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 820 txdesc->length); 821 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); 822 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); 823 rt2x00_desc_write(txwi, 1, word); 824 825 /* 826 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert 827 * the IV from the IVEIV register when TXD_W3_WIV is set to 0. 828 * When TXD_W3_WIV is set to 1 it will use the IV data 829 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 830 * crypto entry in the registers should be used to encrypt the frame. 831 * 832 * Nulify all remaining words as well, we don't know how to program them. 833 */ 834 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++) 835 _rt2x00_desc_write(txwi, i, 0); 836 } 837 EXPORT_SYMBOL_GPL(rt2800_write_tx_data); 838 839 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) 840 { 841 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); 842 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); 843 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); 844 u16 eeprom; 845 u8 offset0; 846 u8 offset1; 847 u8 offset2; 848 849 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 850 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 851 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); 852 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); 853 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 854 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); 855 } else { 856 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 857 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); 858 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); 859 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 860 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); 861 } 862 863 /* 864 * Convert the value from the descriptor into the RSSI value 865 * If the value in the descriptor is 0, it is considered invalid 866 * and the default (extremely low) rssi value is assumed 867 */ 868 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128; 869 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128; 870 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128; 871 872 /* 873 * mac80211 only accepts a single RSSI value. Calculating the 874 * average doesn't deliver a fair answer either since -60:-60 would 875 * be considered equally good as -50:-70 while the second is the one 876 * which gives less energy... 877 */ 878 rssi0 = max(rssi0, rssi1); 879 return (int)max(rssi0, rssi2); 880 } 881 882 void rt2800_process_rxwi(struct queue_entry *entry, 883 struct rxdone_entry_desc *rxdesc) 884 { 885 __le32 *rxwi = (__le32 *) entry->skb->data; 886 u32 word; 887 888 word = rt2x00_desc_read(rxwi, 0); 889 890 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); 891 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); 892 893 word = rt2x00_desc_read(rxwi, 1); 894 895 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) 896 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI; 897 898 if (rt2x00_get_field32(word, RXWI_W1_BW)) 899 rxdesc->bw = RATE_INFO_BW_40; 900 901 /* 902 * Detect RX rate, always use MCS as signal type. 903 */ 904 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; 905 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); 906 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); 907 908 /* 909 * Mask of 0x8 bit to remove the short preamble flag. 910 */ 911 if (rxdesc->rate_mode == RATE_MODE_CCK) 912 rxdesc->signal &= ~0x8; 913 914 word = rt2x00_desc_read(rxwi, 2); 915 916 /* 917 * Convert descriptor AGC value to RSSI value. 918 */ 919 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); 920 /* 921 * Remove RXWI descriptor from start of the buffer. 922 */ 923 skb_pull(entry->skb, entry->queue->winfo_size); 924 } 925 EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 926 927 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc, 928 u32 status, enum nl80211_band band) 929 { 930 u8 flags = 0; 931 u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 932 933 switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) { 934 case RATE_MODE_HT_GREENFIELD: 935 flags |= IEEE80211_TX_RC_GREEN_FIELD; 936 /* fall through */ 937 case RATE_MODE_HT_MIX: 938 flags |= IEEE80211_TX_RC_MCS; 939 break; 940 case RATE_MODE_OFDM: 941 if (band == NL80211_BAND_2GHZ) 942 idx += 4; 943 break; 944 case RATE_MODE_CCK: 945 if (idx >= 8) 946 idx -= 8; 947 break; 948 } 949 950 if (rt2x00_get_field32(status, TX_STA_FIFO_BW)) 951 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 952 953 if (rt2x00_get_field32(status, TX_STA_FIFO_SGI)) 954 flags |= IEEE80211_TX_RC_SHORT_GI; 955 956 skbdesc->tx_rate_idx = idx; 957 skbdesc->tx_rate_flags = flags; 958 } 959 960 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg) 961 { 962 __le32 *txwi; 963 u32 word; 964 int wcid, ack, pid; 965 int tx_wcid, tx_ack, tx_pid, is_agg; 966 967 /* 968 * This frames has returned with an IO error, 969 * so the status report is not intended for this 970 * frame. 971 */ 972 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) 973 return false; 974 975 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID); 976 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED); 977 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE); 978 is_agg = rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE); 979 980 /* 981 * Validate if this TX status report is intended for 982 * this entry by comparing the WCID/ACK/PID fields. 983 */ 984 txwi = rt2800_drv_get_txwi(entry); 985 986 word = rt2x00_desc_read(txwi, 1); 987 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID); 988 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK); 989 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID); 990 991 if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) { 992 rt2x00_dbg(entry->queue->rt2x00dev, 993 "TX status report missed for queue %d entry %d\n", 994 entry->queue->qid, entry->entry_idx); 995 return false; 996 } 997 998 return true; 999 } 1000 1001 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi, 1002 bool match) 1003 { 1004 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1005 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1006 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1007 struct txdone_entry_desc txdesc; 1008 u32 word; 1009 u16 mcs, real_mcs; 1010 int aggr, ampdu, wcid, ack_req; 1011 1012 /* 1013 * Obtain the status about this packet. 1014 */ 1015 txdesc.flags = 0; 1016 word = rt2x00_desc_read(txwi, 0); 1017 1018 mcs = rt2x00_get_field32(word, TXWI_W0_MCS); 1019 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); 1020 1021 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 1022 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); 1023 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID); 1024 ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED); 1025 1026 /* 1027 * If a frame was meant to be sent as a single non-aggregated MPDU 1028 * but ended up in an aggregate the used tx rate doesn't correlate 1029 * with the one specified in the TXWI as the whole aggregate is sent 1030 * with the same rate. 1031 * 1032 * For example: two frames are sent to rt2x00, the first one sets 1033 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 1034 * and requests MCS15. If the hw aggregates both frames into one 1035 * AMDPU the tx status for both frames will contain MCS7 although 1036 * the frame was sent successfully. 1037 * 1038 * Hence, replace the requested rate with the real tx rate to not 1039 * confuse the rate control algortihm by providing clearly wrong 1040 * data. 1041 * 1042 * FIXME: if we do not find matching entry, we tell that frame was 1043 * posted without any retries. We need to find a way to fix that 1044 * and provide retry count. 1045 */ 1046 if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) { 1047 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band); 1048 mcs = real_mcs; 1049 } 1050 1051 if (aggr == 1 || ampdu == 1) 1052 __set_bit(TXDONE_AMPDU, &txdesc.flags); 1053 1054 if (!ack_req) 1055 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags); 1056 1057 /* 1058 * Ralink has a retry mechanism using a global fallback 1059 * table. We setup this fallback table to try the immediate 1060 * lower rate for all rates. In the TX_STA_FIFO, the MCS field 1061 * always contains the MCS used for the last transmission, be 1062 * it successful or not. 1063 */ 1064 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { 1065 /* 1066 * Transmission succeeded. The number of retries is 1067 * mcs - real_mcs 1068 */ 1069 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 1070 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); 1071 } else { 1072 /* 1073 * Transmission failed. The number of retries is 1074 * always 7 in this case (for a total number of 8 1075 * frames sent). 1076 */ 1077 __set_bit(TXDONE_FAILURE, &txdesc.flags); 1078 txdesc.retry = rt2x00dev->long_retry; 1079 } 1080 1081 /* 1082 * the frame was retried at least once 1083 * -> hw used fallback rates 1084 */ 1085 if (txdesc.retry) 1086 __set_bit(TXDONE_FALLBACK, &txdesc.flags); 1087 1088 if (!match) { 1089 /* RCU assures non-null sta will not be freed by mac80211. */ 1090 rcu_read_lock(); 1091 if (likely(wcid >= WCID_START && wcid <= WCID_END)) 1092 skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START]; 1093 else 1094 skbdesc->sta = NULL; 1095 rt2x00lib_txdone_nomatch(entry, &txdesc); 1096 rcu_read_unlock(); 1097 } else { 1098 rt2x00lib_txdone(entry, &txdesc); 1099 } 1100 } 1101 EXPORT_SYMBOL_GPL(rt2800_txdone_entry); 1102 1103 void rt2800_txdone(struct rt2x00_dev *rt2x00dev) 1104 { 1105 struct data_queue *queue; 1106 struct queue_entry *entry; 1107 u32 reg; 1108 u8 qid; 1109 bool match; 1110 1111 while (kfifo_get(&rt2x00dev->txstatus_fifo, ®)) { 1112 /* 1113 * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is 1114 * guaranteed to be one of the TX QIDs . 1115 */ 1116 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE); 1117 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid); 1118 1119 if (unlikely(rt2x00queue_empty(queue))) { 1120 rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n", 1121 qid); 1122 break; 1123 } 1124 1125 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1126 1127 if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1128 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) { 1129 rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n", 1130 entry->entry_idx, qid); 1131 break; 1132 } 1133 1134 match = rt2800_txdone_entry_check(entry, reg); 1135 rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match); 1136 } 1137 } 1138 EXPORT_SYMBOL_GPL(rt2800_txdone); 1139 1140 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev, 1141 struct queue_entry *entry) 1142 { 1143 bool ret; 1144 unsigned long tout; 1145 1146 if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1147 return false; 1148 1149 if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags)) 1150 tout = msecs_to_jiffies(50); 1151 else 1152 tout = msecs_to_jiffies(2000); 1153 1154 ret = time_after(jiffies, entry->last_action + tout); 1155 if (unlikely(ret)) 1156 rt2x00_dbg(entry->queue->rt2x00dev, 1157 "TX status timeout for entry %d in queue %d\n", 1158 entry->entry_idx, entry->queue->qid); 1159 return ret; 1160 } 1161 1162 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev) 1163 { 1164 struct data_queue *queue; 1165 struct queue_entry *entry; 1166 1167 if (!test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags)) { 1168 unsigned long tout = msecs_to_jiffies(1000); 1169 1170 if (time_before(jiffies, rt2x00dev->last_nostatus_check + tout)) 1171 return false; 1172 } 1173 1174 rt2x00dev->last_nostatus_check = jiffies; 1175 1176 tx_queue_for_each(rt2x00dev, queue) { 1177 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1178 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1179 return true; 1180 } 1181 1182 return false; 1183 } 1184 EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout); 1185 1186 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev) 1187 { 1188 struct data_queue *queue; 1189 struct queue_entry *entry; 1190 1191 /* 1192 * Process any trailing TX status reports for IO failures, 1193 * we loop until we find the first non-IO error entry. This 1194 * can either be a frame which is free, is being uploaded, 1195 * or has completed the upload but didn't have an entry 1196 * in the TX_STAT_FIFO register yet. 1197 */ 1198 tx_queue_for_each(rt2x00dev, queue) { 1199 while (!rt2x00queue_empty(queue)) { 1200 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1201 1202 if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1203 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1204 break; 1205 1206 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) || 1207 rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1208 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE); 1209 else 1210 break; 1211 } 1212 } 1213 } 1214 EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus); 1215 1216 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev, 1217 unsigned int index) 1218 { 1219 return HW_BEACON_BASE(index); 1220 } 1221 1222 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev, 1223 unsigned int index) 1224 { 1225 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index)); 1226 } 1227 1228 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev) 1229 { 1230 struct data_queue *queue = rt2x00dev->bcn; 1231 struct queue_entry *entry; 1232 int i, bcn_num = 0; 1233 u64 off, reg = 0; 1234 u32 bssid_dw1; 1235 1236 /* 1237 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers. 1238 */ 1239 for (i = 0; i < queue->limit; i++) { 1240 entry = &queue->entries[i]; 1241 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags)) 1242 continue; 1243 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx); 1244 reg |= off << (8 * bcn_num); 1245 bcn_num++; 1246 } 1247 1248 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); 1249 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); 1250 1251 /* 1252 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons. 1253 */ 1254 bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1); 1255 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, 1256 bcn_num > 0 ? bcn_num - 1 : 0); 1257 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1); 1258 } 1259 1260 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) 1261 { 1262 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1263 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1264 unsigned int beacon_base; 1265 unsigned int padding_len; 1266 u32 orig_reg, reg; 1267 const int txwi_desc_size = entry->queue->winfo_size; 1268 1269 /* 1270 * Disable beaconing while we are reloading the beacon data, 1271 * otherwise we might be sending out invalid data. 1272 */ 1273 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1274 orig_reg = reg; 1275 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1276 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1277 1278 /* 1279 * Add space for the TXWI in front of the skb. 1280 */ 1281 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size); 1282 1283 /* 1284 * Register descriptor details in skb frame descriptor. 1285 */ 1286 skbdesc->flags |= SKBDESC_DESC_IN_SKB; 1287 skbdesc->desc = entry->skb->data; 1288 skbdesc->desc_len = txwi_desc_size; 1289 1290 /* 1291 * Add the TXWI for the beacon to the skb. 1292 */ 1293 rt2800_write_tx_data(entry, txdesc); 1294 1295 /* 1296 * Dump beacon to userspace through debugfs. 1297 */ 1298 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); 1299 1300 /* 1301 * Write entire beacon with TXWI and padding to register. 1302 */ 1303 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 1304 if (padding_len && skb_pad(entry->skb, padding_len)) { 1305 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); 1306 /* skb freed by skb_pad() on failure */ 1307 entry->skb = NULL; 1308 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1309 return; 1310 } 1311 1312 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx); 1313 1314 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, 1315 entry->skb->len + padding_len); 1316 __set_bit(ENTRY_BCN_ENABLED, &entry->flags); 1317 1318 /* 1319 * Change global beacons settings. 1320 */ 1321 rt2800_update_beacons_setup(rt2x00dev); 1322 1323 /* 1324 * Restore beaconing state. 1325 */ 1326 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1327 1328 /* 1329 * Clean up beacon skb. 1330 */ 1331 dev_kfree_skb_any(entry->skb); 1332 entry->skb = NULL; 1333 } 1334 EXPORT_SYMBOL_GPL(rt2800_write_beacon); 1335 1336 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, 1337 unsigned int index) 1338 { 1339 int i; 1340 const int txwi_desc_size = rt2x00dev->bcn->winfo_size; 1341 unsigned int beacon_base; 1342 1343 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index); 1344 1345 /* 1346 * For the Beacon base registers we only need to clear 1347 * the whole TXWI which (when set to 0) will invalidate 1348 * the entire beacon. 1349 */ 1350 for (i = 0; i < txwi_desc_size; i += sizeof(__le32)) 1351 rt2800_register_write(rt2x00dev, beacon_base + i, 0); 1352 } 1353 1354 void rt2800_clear_beacon(struct queue_entry *entry) 1355 { 1356 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1357 u32 orig_reg, reg; 1358 1359 /* 1360 * Disable beaconing while we are reloading the beacon data, 1361 * otherwise we might be sending out invalid data. 1362 */ 1363 orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1364 reg = orig_reg; 1365 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1366 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1367 1368 /* 1369 * Clear beacon. 1370 */ 1371 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx); 1372 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags); 1373 1374 /* 1375 * Change global beacons settings. 1376 */ 1377 rt2800_update_beacons_setup(rt2x00dev); 1378 /* 1379 * Restore beaconing state. 1380 */ 1381 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1382 } 1383 EXPORT_SYMBOL_GPL(rt2800_clear_beacon); 1384 1385 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 1386 const struct rt2x00debug rt2800_rt2x00debug = { 1387 .owner = THIS_MODULE, 1388 .csr = { 1389 .read = rt2800_register_read, 1390 .write = rt2800_register_write, 1391 .flags = RT2X00DEBUGFS_OFFSET, 1392 .word_base = CSR_REG_BASE, 1393 .word_size = sizeof(u32), 1394 .word_count = CSR_REG_SIZE / sizeof(u32), 1395 }, 1396 .eeprom = { 1397 /* NOTE: The local EEPROM access functions can't 1398 * be used here, use the generic versions instead. 1399 */ 1400 .read = rt2x00_eeprom_read, 1401 .write = rt2x00_eeprom_write, 1402 .word_base = EEPROM_BASE, 1403 .word_size = sizeof(u16), 1404 .word_count = EEPROM_SIZE / sizeof(u16), 1405 }, 1406 .bbp = { 1407 .read = rt2800_bbp_read, 1408 .write = rt2800_bbp_write, 1409 .word_base = BBP_BASE, 1410 .word_size = sizeof(u8), 1411 .word_count = BBP_SIZE / sizeof(u8), 1412 }, 1413 .rf = { 1414 .read = rt2x00_rf_read, 1415 .write = rt2800_rf_write, 1416 .word_base = RF_BASE, 1417 .word_size = sizeof(u32), 1418 .word_count = RF_SIZE / sizeof(u32), 1419 }, 1420 .rfcsr = { 1421 .read = rt2800_rfcsr_read, 1422 .write = rt2800_rfcsr_write, 1423 .word_base = RFCSR_BASE, 1424 .word_size = sizeof(u8), 1425 .word_count = RFCSR_SIZE / sizeof(u8), 1426 }, 1427 }; 1428 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); 1429 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1430 1431 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) 1432 { 1433 u32 reg; 1434 1435 if (rt2x00_rt(rt2x00dev, RT3290)) { 1436 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 1437 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); 1438 } else { 1439 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 1440 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); 1441 } 1442 } 1443 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 1444 1445 #ifdef CONFIG_RT2X00_LIB_LEDS 1446 static void rt2800_brightness_set(struct led_classdev *led_cdev, 1447 enum led_brightness brightness) 1448 { 1449 struct rt2x00_led *led = 1450 container_of(led_cdev, struct rt2x00_led, led_dev); 1451 unsigned int enabled = brightness != LED_OFF; 1452 unsigned int bg_mode = 1453 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); 1454 unsigned int polarity = 1455 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1456 EEPROM_FREQ_LED_POLARITY); 1457 unsigned int ledmode = 1458 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1459 EEPROM_FREQ_LED_MODE); 1460 u32 reg; 1461 1462 /* Check for SoC (SOC devices don't support MCU requests) */ 1463 if (rt2x00_is_soc(led->rt2x00dev)) { 1464 reg = rt2800_register_read(led->rt2x00dev, LED_CFG); 1465 1466 /* Set LED Polarity */ 1467 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); 1468 1469 /* Set LED Mode */ 1470 if (led->type == LED_TYPE_RADIO) { 1471 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 1472 enabled ? 3 : 0); 1473 } else if (led->type == LED_TYPE_ASSOC) { 1474 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 1475 enabled ? 3 : 0); 1476 } else if (led->type == LED_TYPE_QUALITY) { 1477 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 1478 enabled ? 3 : 0); 1479 } 1480 1481 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 1482 1483 } else { 1484 if (led->type == LED_TYPE_RADIO) { 1485 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1486 enabled ? 0x20 : 0); 1487 } else if (led->type == LED_TYPE_ASSOC) { 1488 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1489 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); 1490 } else if (led->type == LED_TYPE_QUALITY) { 1491 /* 1492 * The brightness is divided into 6 levels (0 - 5), 1493 * The specs tell us the following levels: 1494 * 0, 1 ,3, 7, 15, 31 1495 * to determine the level in a simple way we can simply 1496 * work with bitshifting: 1497 * (1 << level) - 1 1498 */ 1499 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 1500 (1 << brightness / (LED_FULL / 6)) - 1, 1501 polarity); 1502 } 1503 } 1504 } 1505 1506 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, 1507 struct rt2x00_led *led, enum led_type type) 1508 { 1509 led->rt2x00dev = rt2x00dev; 1510 led->type = type; 1511 led->led_dev.brightness_set = rt2800_brightness_set; 1512 led->flags = LED_INITIALIZED; 1513 } 1514 #endif /* CONFIG_RT2X00_LIB_LEDS */ 1515 1516 /* 1517 * Configuration handlers. 1518 */ 1519 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, 1520 const u8 *address, 1521 int wcid) 1522 { 1523 struct mac_wcid_entry wcid_entry; 1524 u32 offset; 1525 1526 offset = MAC_WCID_ENTRY(wcid); 1527 1528 memset(&wcid_entry, 0xff, sizeof(wcid_entry)); 1529 if (address) 1530 memcpy(wcid_entry.mac, address, ETH_ALEN); 1531 1532 rt2800_register_multiwrite(rt2x00dev, offset, 1533 &wcid_entry, sizeof(wcid_entry)); 1534 } 1535 1536 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) 1537 { 1538 u32 offset; 1539 offset = MAC_WCID_ATTR_ENTRY(wcid); 1540 rt2800_register_write(rt2x00dev, offset, 0); 1541 } 1542 1543 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, 1544 int wcid, u32 bssidx) 1545 { 1546 u32 offset = MAC_WCID_ATTR_ENTRY(wcid); 1547 u32 reg; 1548 1549 /* 1550 * The BSS Idx numbers is split in a main value of 3 bits, 1551 * and a extended field for adding one additional bit to the value. 1552 */ 1553 reg = rt2800_register_read(rt2x00dev, offset); 1554 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); 1555 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, 1556 (bssidx & 0x8) >> 3); 1557 rt2800_register_write(rt2x00dev, offset, reg); 1558 } 1559 1560 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, 1561 struct rt2x00lib_crypto *crypto, 1562 struct ieee80211_key_conf *key) 1563 { 1564 struct mac_iveiv_entry iveiv_entry; 1565 u32 offset; 1566 u32 reg; 1567 1568 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); 1569 1570 if (crypto->cmd == SET_KEY) { 1571 reg = rt2800_register_read(rt2x00dev, offset); 1572 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 1573 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 1574 /* 1575 * Both the cipher as the BSS Idx numbers are split in a main 1576 * value of 3 bits, and a extended field for adding one additional 1577 * bit to the value. 1578 */ 1579 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 1580 (crypto->cipher & 0x7)); 1581 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 1582 (crypto->cipher & 0x8) >> 3); 1583 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); 1584 rt2800_register_write(rt2x00dev, offset, reg); 1585 } else { 1586 /* Delete the cipher without touching the bssidx */ 1587 reg = rt2800_register_read(rt2x00dev, offset); 1588 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); 1589 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); 1590 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); 1591 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); 1592 rt2800_register_write(rt2x00dev, offset, reg); 1593 } 1594 1595 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 1596 1597 memset(&iveiv_entry, 0, sizeof(iveiv_entry)); 1598 if ((crypto->cipher == CIPHER_TKIP) || 1599 (crypto->cipher == CIPHER_TKIP_NO_MIC) || 1600 (crypto->cipher == CIPHER_AES)) 1601 iveiv_entry.iv[3] |= 0x20; 1602 iveiv_entry.iv[3] |= key->keyidx << 6; 1603 rt2800_register_multiwrite(rt2x00dev, offset, 1604 &iveiv_entry, sizeof(iveiv_entry)); 1605 } 1606 1607 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, 1608 struct rt2x00lib_crypto *crypto, 1609 struct ieee80211_key_conf *key) 1610 { 1611 struct hw_key_entry key_entry; 1612 struct rt2x00_field32 field; 1613 u32 offset; 1614 u32 reg; 1615 1616 if (crypto->cmd == SET_KEY) { 1617 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; 1618 1619 memcpy(key_entry.key, crypto->key, 1620 sizeof(key_entry.key)); 1621 memcpy(key_entry.tx_mic, crypto->tx_mic, 1622 sizeof(key_entry.tx_mic)); 1623 memcpy(key_entry.rx_mic, crypto->rx_mic, 1624 sizeof(key_entry.rx_mic)); 1625 1626 offset = SHARED_KEY_ENTRY(key->hw_key_idx); 1627 rt2800_register_multiwrite(rt2x00dev, offset, 1628 &key_entry, sizeof(key_entry)); 1629 } 1630 1631 /* 1632 * The cipher types are stored over multiple registers 1633 * starting with SHARED_KEY_MODE_BASE each word will have 1634 * 32 bits and contains the cipher types for 2 bssidx each. 1635 * Using the correct defines correctly will cause overhead, 1636 * so just calculate the correct offset. 1637 */ 1638 field.bit_offset = 4 * (key->hw_key_idx % 8); 1639 field.bit_mask = 0x7 << field.bit_offset; 1640 1641 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); 1642 1643 reg = rt2800_register_read(rt2x00dev, offset); 1644 rt2x00_set_field32(®, field, 1645 (crypto->cmd == SET_KEY) * crypto->cipher); 1646 rt2800_register_write(rt2x00dev, offset, reg); 1647 1648 /* 1649 * Update WCID information 1650 */ 1651 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); 1652 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, 1653 crypto->bssidx); 1654 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1655 1656 return 0; 1657 } 1658 EXPORT_SYMBOL_GPL(rt2800_config_shared_key); 1659 1660 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 1661 struct rt2x00lib_crypto *crypto, 1662 struct ieee80211_key_conf *key) 1663 { 1664 struct hw_key_entry key_entry; 1665 u32 offset; 1666 1667 if (crypto->cmd == SET_KEY) { 1668 /* 1669 * Allow key configuration only for STAs that are 1670 * known by the hw. 1671 */ 1672 if (crypto->wcid > WCID_END) 1673 return -ENOSPC; 1674 key->hw_key_idx = crypto->wcid; 1675 1676 memcpy(key_entry.key, crypto->key, 1677 sizeof(key_entry.key)); 1678 memcpy(key_entry.tx_mic, crypto->tx_mic, 1679 sizeof(key_entry.tx_mic)); 1680 memcpy(key_entry.rx_mic, crypto->rx_mic, 1681 sizeof(key_entry.rx_mic)); 1682 1683 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 1684 rt2800_register_multiwrite(rt2x00dev, offset, 1685 &key_entry, sizeof(key_entry)); 1686 } 1687 1688 /* 1689 * Update WCID information 1690 */ 1691 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1692 1693 return 0; 1694 } 1695 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); 1696 1697 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev) 1698 { 1699 u8 i, max_psdu; 1700 u32 reg; 1701 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1702 1703 for (i = 0; i < 3; i++) 1704 if (drv_data->ampdu_factor_cnt[i] > 0) 1705 break; 1706 1707 max_psdu = min(drv_data->max_psdu, i); 1708 1709 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 1710 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); 1711 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1712 } 1713 1714 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1715 struct ieee80211_sta *sta) 1716 { 1717 struct rt2x00_dev *rt2x00dev = hw->priv; 1718 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1719 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1720 int wcid; 1721 1722 /* 1723 * Limit global maximum TX AMPDU length to smallest value of all 1724 * connected stations. In AP mode this can be suboptimal, but we 1725 * do not have a choice if some connected STA is not capable to 1726 * receive the same amount of data like the others. 1727 */ 1728 if (sta->ht_cap.ht_supported) { 1729 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++; 1730 rt2800_set_max_psdu_len(rt2x00dev); 1731 } 1732 1733 /* 1734 * Search for the first free WCID entry and return the corresponding 1735 * index. 1736 */ 1737 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START; 1738 1739 /* 1740 * Store selected wcid even if it is invalid so that we can 1741 * later decide if the STA is uploaded into the hw. 1742 */ 1743 sta_priv->wcid = wcid; 1744 1745 /* 1746 * No space left in the device, however, we can still communicate 1747 * with the STA -> No error. 1748 */ 1749 if (wcid > WCID_END) 1750 return 0; 1751 1752 __set_bit(wcid - WCID_START, drv_data->sta_ids); 1753 drv_data->wcid_to_sta[wcid - WCID_START] = sta; 1754 1755 /* 1756 * Clean up WCID attributes and write STA address to the device. 1757 */ 1758 rt2800_delete_wcid_attr(rt2x00dev, wcid); 1759 rt2800_config_wcid(rt2x00dev, sta->addr, wcid); 1760 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, 1761 rt2x00lib_get_bssidx(rt2x00dev, vif)); 1762 return 0; 1763 } 1764 EXPORT_SYMBOL_GPL(rt2800_sta_add); 1765 1766 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1767 struct ieee80211_sta *sta) 1768 { 1769 struct rt2x00_dev *rt2x00dev = hw->priv; 1770 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1771 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1772 int wcid = sta_priv->wcid; 1773 1774 if (sta->ht_cap.ht_supported) { 1775 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--; 1776 rt2800_set_max_psdu_len(rt2x00dev); 1777 } 1778 1779 if (wcid > WCID_END) 1780 return 0; 1781 /* 1782 * Remove WCID entry, no need to clean the attributes as they will 1783 * get renewed when the WCID is reused. 1784 */ 1785 rt2800_config_wcid(rt2x00dev, NULL, wcid); 1786 drv_data->wcid_to_sta[wcid - WCID_START] = NULL; 1787 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1788 1789 return 0; 1790 } 1791 EXPORT_SYMBOL_GPL(rt2800_sta_remove); 1792 1793 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, 1794 const unsigned int filter_flags) 1795 { 1796 u32 reg; 1797 1798 /* 1799 * Start configuration steps. 1800 * Note that the version error will always be dropped 1801 * and broadcast frames will always be accepted since 1802 * there is no filter for it at this time. 1803 */ 1804 reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG); 1805 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, 1806 !(filter_flags & FIF_FCSFAIL)); 1807 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, 1808 !(filter_flags & FIF_PLCPFAIL)); 1809 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, 1810 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); 1811 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); 1812 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); 1813 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, 1814 !(filter_flags & FIF_ALLMULTI)); 1815 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); 1816 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); 1817 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, 1818 !(filter_flags & FIF_CONTROL)); 1819 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, 1820 !(filter_flags & FIF_CONTROL)); 1821 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, 1822 !(filter_flags & FIF_CONTROL)); 1823 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, 1824 !(filter_flags & FIF_CONTROL)); 1825 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, 1826 !(filter_flags & FIF_CONTROL)); 1827 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, 1828 !(filter_flags & FIF_PSPOLL)); 1829 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); 1830 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 1831 !(filter_flags & FIF_CONTROL)); 1832 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, 1833 !(filter_flags & FIF_CONTROL)); 1834 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); 1835 } 1836 EXPORT_SYMBOL_GPL(rt2800_config_filter); 1837 1838 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, 1839 struct rt2x00intf_conf *conf, const unsigned int flags) 1840 { 1841 u32 reg; 1842 bool update_bssid = false; 1843 1844 if (flags & CONFIG_UPDATE_TYPE) { 1845 /* 1846 * Enable synchronisation. 1847 */ 1848 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1849 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); 1850 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1851 1852 if (conf->sync == TSF_SYNC_AP_NONE) { 1853 /* 1854 * Tune beacon queue transmit parameters for AP mode 1855 */ 1856 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1857 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); 1858 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); 1859 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1860 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); 1861 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1862 } else { 1863 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1864 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); 1865 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); 1866 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1867 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); 1868 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1869 } 1870 } 1871 1872 if (flags & CONFIG_UPDATE_MAC) { 1873 if (flags & CONFIG_UPDATE_TYPE && 1874 conf->sync == TSF_SYNC_AP_NONE) { 1875 /* 1876 * The BSSID register has to be set to our own mac 1877 * address in AP mode. 1878 */ 1879 memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); 1880 update_bssid = true; 1881 } 1882 1883 if (!is_zero_ether_addr((const u8 *)conf->mac)) { 1884 reg = le32_to_cpu(conf->mac[1]); 1885 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); 1886 conf->mac[1] = cpu_to_le32(reg); 1887 } 1888 1889 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, 1890 conf->mac, sizeof(conf->mac)); 1891 } 1892 1893 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { 1894 if (!is_zero_ether_addr((const u8 *)conf->bssid)) { 1895 reg = le32_to_cpu(conf->bssid[1]); 1896 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); 1897 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); 1898 conf->bssid[1] = cpu_to_le32(reg); 1899 } 1900 1901 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, 1902 conf->bssid, sizeof(conf->bssid)); 1903 } 1904 } 1905 EXPORT_SYMBOL_GPL(rt2800_config_intf); 1906 1907 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, 1908 struct rt2x00lib_erp *erp) 1909 { 1910 bool any_sta_nongf = !!(erp->ht_opmode & 1911 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 1912 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; 1913 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; 1914 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; 1915 u32 reg; 1916 1917 /* default protection rate for HT20: OFDM 24M */ 1918 mm20_rate = gf20_rate = 0x4004; 1919 1920 /* default protection rate for HT40: duplicate OFDM 24M */ 1921 mm40_rate = gf40_rate = 0x4084; 1922 1923 switch (protection) { 1924 case IEEE80211_HT_OP_MODE_PROTECTION_NONE: 1925 /* 1926 * All STAs in this BSS are HT20/40 but there might be 1927 * STAs not supporting greenfield mode. 1928 * => Disable protection for HT transmissions. 1929 */ 1930 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; 1931 1932 break; 1933 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 1934 /* 1935 * All STAs in this BSS are HT20 or HT20/40 but there 1936 * might be STAs not supporting greenfield mode. 1937 * => Protect all HT40 transmissions. 1938 */ 1939 mm20_mode = gf20_mode = 0; 1940 mm40_mode = gf40_mode = 1; 1941 1942 break; 1943 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 1944 /* 1945 * Nonmember protection: 1946 * According to 802.11n we _should_ protect all 1947 * HT transmissions (but we don't have to). 1948 * 1949 * But if cts_protection is enabled we _shall_ protect 1950 * all HT transmissions using a CCK rate. 1951 * 1952 * And if any station is non GF we _shall_ protect 1953 * GF transmissions. 1954 * 1955 * We decide to protect everything 1956 * -> fall through to mixed mode. 1957 */ 1958 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 1959 /* 1960 * Legacy STAs are present 1961 * => Protect all HT transmissions. 1962 */ 1963 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1; 1964 1965 /* 1966 * If erp protection is needed we have to protect HT 1967 * transmissions with CCK 11M long preamble. 1968 */ 1969 if (erp->cts_protection) { 1970 /* don't duplicate RTS/CTS in CCK mode */ 1971 mm20_rate = mm40_rate = 0x0003; 1972 gf20_rate = gf40_rate = 0x0003; 1973 } 1974 break; 1975 } 1976 1977 /* check for STAs not supporting greenfield mode */ 1978 if (any_sta_nongf) 1979 gf20_mode = gf40_mode = 1; 1980 1981 /* Update HT protection config */ 1982 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 1983 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); 1984 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); 1985 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 1986 1987 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 1988 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); 1989 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); 1990 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 1991 1992 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 1993 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); 1994 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); 1995 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 1996 1997 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 1998 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); 1999 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); 2000 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 2001 } 2002 2003 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, 2004 u32 changed) 2005 { 2006 u32 reg; 2007 2008 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 2009 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 2010 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 2011 !!erp->short_preamble); 2012 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 2013 } 2014 2015 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 2016 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 2017 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 2018 erp->cts_protection ? 2 : 0); 2019 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 2020 } 2021 2022 if (changed & BSS_CHANGED_BASIC_RATES) { 2023 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 2024 0xff0 | erp->basic_rates); 2025 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 2026 } 2027 2028 if (changed & BSS_CHANGED_ERP_SLOT) { 2029 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 2030 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 2031 erp->slot_time); 2032 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 2033 2034 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 2035 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); 2036 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 2037 } 2038 2039 if (changed & BSS_CHANGED_BEACON_INT) { 2040 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 2041 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 2042 erp->beacon_int * 16); 2043 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 2044 } 2045 2046 if (changed & BSS_CHANGED_HT) 2047 rt2800_config_ht_opmode(rt2x00dev, erp); 2048 } 2049 EXPORT_SYMBOL_GPL(rt2800_config_erp); 2050 2051 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) 2052 { 2053 u32 reg; 2054 u16 eeprom; 2055 u8 led_ctrl, led_g_mode, led_r_mode; 2056 2057 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 2058 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { 2059 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); 2060 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); 2061 } else { 2062 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); 2063 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); 2064 } 2065 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 2066 2067 reg = rt2800_register_read(rt2x00dev, LED_CFG); 2068 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; 2069 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; 2070 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || 2071 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { 2072 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 2073 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); 2074 if (led_ctrl == 0 || led_ctrl > 0x40) { 2075 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); 2076 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); 2077 rt2800_register_write(rt2x00dev, LED_CFG, reg); 2078 } else { 2079 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, 2080 (led_g_mode << 2) | led_r_mode, 1); 2081 } 2082 } 2083 } 2084 2085 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, 2086 enum antenna ant) 2087 { 2088 u32 reg; 2089 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; 2090 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; 2091 2092 if (rt2x00_is_pci(rt2x00dev)) { 2093 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR); 2094 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); 2095 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); 2096 } else if (rt2x00_is_usb(rt2x00dev)) 2097 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, 2098 eesk_pin, 0); 2099 2100 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2101 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 2102 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); 2103 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2104 } 2105 2106 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 2107 { 2108 u8 r1; 2109 u8 r3; 2110 u16 eeprom; 2111 2112 r1 = rt2800_bbp_read(rt2x00dev, 1); 2113 r3 = rt2800_bbp_read(rt2x00dev, 3); 2114 2115 if (rt2x00_rt(rt2x00dev, RT3572) && 2116 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2117 rt2800_config_3572bt_ant(rt2x00dev); 2118 2119 /* 2120 * Configure the TX antenna. 2121 */ 2122 switch (ant->tx_chain_num) { 2123 case 1: 2124 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 2125 break; 2126 case 2: 2127 if (rt2x00_rt(rt2x00dev, RT3572) && 2128 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2129 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); 2130 else 2131 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2132 break; 2133 case 3: 2134 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2135 break; 2136 } 2137 2138 /* 2139 * Configure the RX antenna. 2140 */ 2141 switch (ant->rx_chain_num) { 2142 case 1: 2143 if (rt2x00_rt(rt2x00dev, RT3070) || 2144 rt2x00_rt(rt2x00dev, RT3090) || 2145 rt2x00_rt(rt2x00dev, RT3352) || 2146 rt2x00_rt(rt2x00dev, RT3390)) { 2147 eeprom = rt2800_eeprom_read(rt2x00dev, 2148 EEPROM_NIC_CONF1); 2149 if (rt2x00_get_field16(eeprom, 2150 EEPROM_NIC_CONF1_ANT_DIVERSITY)) 2151 rt2800_set_ant_diversity(rt2x00dev, 2152 rt2x00dev->default_ant.rx); 2153 } 2154 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 2155 break; 2156 case 2: 2157 if (rt2x00_rt(rt2x00dev, RT3572) && 2158 rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2159 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); 2160 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2161 rt2x00dev->curr_band == NL80211_BAND_5GHZ); 2162 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); 2163 } else { 2164 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); 2165 } 2166 break; 2167 case 3: 2168 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); 2169 break; 2170 } 2171 2172 rt2800_bbp_write(rt2x00dev, 3, r3); 2173 rt2800_bbp_write(rt2x00dev, 1, r1); 2174 2175 if (rt2x00_rt(rt2x00dev, RT3593)) { 2176 if (ant->rx_chain_num == 1) 2177 rt2800_bbp_write(rt2x00dev, 86, 0x00); 2178 else 2179 rt2800_bbp_write(rt2x00dev, 86, 0x46); 2180 } 2181 } 2182 EXPORT_SYMBOL_GPL(rt2800_config_ant); 2183 2184 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, 2185 struct rt2x00lib_conf *libconf) 2186 { 2187 u16 eeprom; 2188 short lna_gain; 2189 2190 if (libconf->rf.channel <= 14) { 2191 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2192 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); 2193 } else if (libconf->rf.channel <= 64) { 2194 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2195 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); 2196 } else if (libconf->rf.channel <= 128) { 2197 if (rt2x00_rt(rt2x00dev, RT3593)) { 2198 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2199 lna_gain = rt2x00_get_field16(eeprom, 2200 EEPROM_EXT_LNA2_A1); 2201 } else { 2202 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 2203 lna_gain = rt2x00_get_field16(eeprom, 2204 EEPROM_RSSI_BG2_LNA_A1); 2205 } 2206 } else { 2207 if (rt2x00_rt(rt2x00dev, RT3593)) { 2208 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2209 lna_gain = rt2x00_get_field16(eeprom, 2210 EEPROM_EXT_LNA2_A2); 2211 } else { 2212 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 2213 lna_gain = rt2x00_get_field16(eeprom, 2214 EEPROM_RSSI_A2_LNA_A2); 2215 } 2216 } 2217 2218 rt2x00dev->lna_gain = lna_gain; 2219 } 2220 2221 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev) 2222 { 2223 return clk_get_rate(rt2x00dev->clk) == 20000000; 2224 } 2225 2226 #define FREQ_OFFSET_BOUND 0x5f 2227 2228 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev) 2229 { 2230 u8 freq_offset, prev_freq_offset; 2231 u8 rfcsr, prev_rfcsr; 2232 2233 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE); 2234 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND); 2235 2236 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 2237 prev_rfcsr = rfcsr; 2238 2239 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset); 2240 if (rfcsr == prev_rfcsr) 2241 return; 2242 2243 if (rt2x00_is_usb(rt2x00dev)) { 2244 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff, 2245 freq_offset, prev_rfcsr); 2246 return; 2247 } 2248 2249 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE); 2250 while (prev_freq_offset != freq_offset) { 2251 if (prev_freq_offset < freq_offset) 2252 prev_freq_offset++; 2253 else 2254 prev_freq_offset--; 2255 2256 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset); 2257 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 2258 2259 usleep_range(1000, 1500); 2260 } 2261 } 2262 2263 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, 2264 struct ieee80211_conf *conf, 2265 struct rf_channel *rf, 2266 struct channel_info *info) 2267 { 2268 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 2269 2270 if (rt2x00dev->default_ant.tx_chain_num == 1) 2271 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); 2272 2273 if (rt2x00dev->default_ant.rx_chain_num == 1) { 2274 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); 2275 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2276 } else if (rt2x00dev->default_ant.rx_chain_num == 2) 2277 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2278 2279 if (rf->channel > 14) { 2280 /* 2281 * When TX power is below 0, we should increase it by 7 to 2282 * make it a positive value (Minimum value is -7). 2283 * However this means that values between 0 and 7 have 2284 * double meaning, and we should set a 7DBm boost flag. 2285 */ 2286 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, 2287 (info->default_power1 >= 0)); 2288 2289 if (info->default_power1 < 0) 2290 info->default_power1 += 7; 2291 2292 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); 2293 2294 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, 2295 (info->default_power2 >= 0)); 2296 2297 if (info->default_power2 < 0) 2298 info->default_power2 += 7; 2299 2300 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); 2301 } else { 2302 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); 2303 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); 2304 } 2305 2306 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); 2307 2308 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2309 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2310 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2311 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2312 2313 udelay(200); 2314 2315 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2316 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2317 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 2318 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2319 2320 udelay(200); 2321 2322 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2323 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2324 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2325 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2326 } 2327 2328 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, 2329 struct ieee80211_conf *conf, 2330 struct rf_channel *rf, 2331 struct channel_info *info) 2332 { 2333 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2334 u8 rfcsr, calib_tx, calib_rx; 2335 2336 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2337 2338 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2339 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3); 2340 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2341 2342 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2343 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2344 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2345 2346 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2347 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); 2348 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2349 2350 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2351 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); 2352 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2353 2354 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2355 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2356 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 2357 rt2x00dev->default_ant.rx_chain_num <= 1); 2358 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 2359 rt2x00dev->default_ant.rx_chain_num <= 2); 2360 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2361 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 2362 rt2x00dev->default_ant.tx_chain_num <= 1); 2363 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 2364 rt2x00dev->default_ant.tx_chain_num <= 2); 2365 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2366 2367 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2368 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2369 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2370 2371 if (rt2x00_rt(rt2x00dev, RT3390)) { 2372 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f; 2373 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f; 2374 } else { 2375 if (conf_is_ht40(conf)) { 2376 calib_tx = drv_data->calibration_bw40; 2377 calib_rx = drv_data->calibration_bw40; 2378 } else { 2379 calib_tx = drv_data->calibration_bw20; 2380 calib_rx = drv_data->calibration_bw20; 2381 } 2382 } 2383 2384 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24); 2385 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx); 2386 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr); 2387 2388 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 2389 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx); 2390 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2391 2392 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2393 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2394 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2395 2396 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2397 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 2398 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2399 2400 usleep_range(1000, 1500); 2401 2402 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 2403 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2404 } 2405 2406 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, 2407 struct ieee80211_conf *conf, 2408 struct rf_channel *rf, 2409 struct channel_info *info) 2410 { 2411 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2412 u8 rfcsr; 2413 u32 reg; 2414 2415 if (rf->channel <= 14) { 2416 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2417 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2418 } else { 2419 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2420 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2421 } 2422 2423 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2424 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 2425 2426 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2427 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2428 if (rf->channel <= 14) 2429 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); 2430 else 2431 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); 2432 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2433 2434 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5); 2435 if (rf->channel <= 14) 2436 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); 2437 else 2438 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); 2439 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); 2440 2441 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2442 if (rf->channel <= 14) { 2443 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); 2444 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2445 info->default_power1); 2446 } else { 2447 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); 2448 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2449 (info->default_power1 & 0x3) | 2450 ((info->default_power1 & 0xC) << 1)); 2451 } 2452 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2453 2454 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2455 if (rf->channel <= 14) { 2456 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); 2457 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2458 info->default_power2); 2459 } else { 2460 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); 2461 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2462 (info->default_power2 & 0x3) | 2463 ((info->default_power2 & 0xC) << 1)); 2464 } 2465 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2466 2467 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2468 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2469 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2470 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2471 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2472 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2473 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2474 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2475 if (rf->channel <= 14) { 2476 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2477 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2478 } 2479 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2480 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2481 } else { 2482 switch (rt2x00dev->default_ant.tx_chain_num) { 2483 case 1: 2484 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2485 /* fall through */ 2486 case 2: 2487 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2488 break; 2489 } 2490 2491 switch (rt2x00dev->default_ant.rx_chain_num) { 2492 case 1: 2493 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2494 /* fall through */ 2495 case 2: 2496 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2497 break; 2498 } 2499 } 2500 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2501 2502 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2503 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2504 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2505 2506 if (conf_is_ht40(conf)) { 2507 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40); 2508 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40); 2509 } else { 2510 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20); 2511 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20); 2512 } 2513 2514 if (rf->channel <= 14) { 2515 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 2516 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 2517 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2518 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 2519 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 2520 rfcsr = 0x4c; 2521 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2522 drv_data->txmixer_gain_24g); 2523 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2524 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2525 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 2526 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 2527 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 2528 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 2529 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 2530 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 2531 } else { 2532 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2533 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1); 2534 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0); 2535 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1); 2536 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0); 2537 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2538 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 2539 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2540 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 2541 rt2800_rfcsr_write(rt2x00dev, 15, 0x43); 2542 rfcsr = 0x7a; 2543 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2544 drv_data->txmixer_gain_5g); 2545 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2546 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2547 if (rf->channel <= 64) { 2548 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7); 2549 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6); 2550 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 2551 } else if (rf->channel <= 128) { 2552 rt2800_rfcsr_write(rt2x00dev, 19, 0x74); 2553 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4); 2554 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2555 } else { 2556 rt2800_rfcsr_write(rt2x00dev, 19, 0x72); 2557 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3); 2558 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2559 } 2560 rt2800_rfcsr_write(rt2x00dev, 26, 0x87); 2561 rt2800_rfcsr_write(rt2x00dev, 27, 0x01); 2562 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); 2563 } 2564 2565 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2566 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 2567 if (rf->channel <= 14) 2568 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 2569 else 2570 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); 2571 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2572 2573 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2574 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2575 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2576 } 2577 2578 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, 2579 struct ieee80211_conf *conf, 2580 struct rf_channel *rf, 2581 struct channel_info *info) 2582 { 2583 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2584 u8 txrx_agc_fc; 2585 u8 txrx_h20m; 2586 u8 rfcsr; 2587 u8 bbp; 2588 const bool txbf_enabled = false; /* TODO */ 2589 2590 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */ 2591 bbp = rt2800_bbp_read(rt2x00dev, 109); 2592 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0); 2593 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0); 2594 rt2800_bbp_write(rt2x00dev, 109, bbp); 2595 2596 bbp = rt2800_bbp_read(rt2x00dev, 110); 2597 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0); 2598 rt2800_bbp_write(rt2x00dev, 110, bbp); 2599 2600 if (rf->channel <= 14) { 2601 /* Restore BBP 25 & 26 for 2.4 GHz */ 2602 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2603 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2604 } else { 2605 /* Hard code BBP 25 & 26 for 5GHz */ 2606 2607 /* Enable IQ Phase correction */ 2608 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2609 /* Setup IQ Phase correction value */ 2610 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2611 } 2612 2613 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2614 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf); 2615 2616 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2617 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3)); 2618 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2619 2620 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2621 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1); 2622 if (rf->channel <= 14) 2623 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1); 2624 else 2625 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2); 2626 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2627 2628 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53); 2629 if (rf->channel <= 14) { 2630 rfcsr = 0; 2631 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2632 info->default_power1 & 0x1f); 2633 } else { 2634 if (rt2x00_is_usb(rt2x00dev)) 2635 rfcsr = 0x40; 2636 2637 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2638 ((info->default_power1 & 0x18) << 1) | 2639 (info->default_power1 & 7)); 2640 } 2641 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr); 2642 2643 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55); 2644 if (rf->channel <= 14) { 2645 rfcsr = 0; 2646 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2647 info->default_power2 & 0x1f); 2648 } else { 2649 if (rt2x00_is_usb(rt2x00dev)) 2650 rfcsr = 0x40; 2651 2652 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2653 ((info->default_power2 & 0x18) << 1) | 2654 (info->default_power2 & 7)); 2655 } 2656 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr); 2657 2658 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54); 2659 if (rf->channel <= 14) { 2660 rfcsr = 0; 2661 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2662 info->default_power3 & 0x1f); 2663 } else { 2664 if (rt2x00_is_usb(rt2x00dev)) 2665 rfcsr = 0x40; 2666 2667 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2668 ((info->default_power3 & 0x18) << 1) | 2669 (info->default_power3 & 7)); 2670 } 2671 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr); 2672 2673 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2674 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2675 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2676 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2677 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2678 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2679 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2680 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2681 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2682 2683 switch (rt2x00dev->default_ant.tx_chain_num) { 2684 case 3: 2685 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2686 /* fallthrough */ 2687 case 2: 2688 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2689 /* fallthrough */ 2690 case 1: 2691 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2692 break; 2693 } 2694 2695 switch (rt2x00dev->default_ant.rx_chain_num) { 2696 case 3: 2697 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2698 /* fallthrough */ 2699 case 2: 2700 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2701 /* fallthrough */ 2702 case 1: 2703 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2704 break; 2705 } 2706 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2707 2708 rt2800_freq_cal_mode1(rt2x00dev); 2709 2710 if (conf_is_ht40(conf)) { 2711 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40, 2712 RFCSR24_TX_AGC_FC); 2713 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40, 2714 RFCSR24_TX_H20M); 2715 } else { 2716 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20, 2717 RFCSR24_TX_AGC_FC); 2718 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20, 2719 RFCSR24_TX_H20M); 2720 } 2721 2722 /* NOTE: the reference driver does not writes the new value 2723 * back to RFCSR 32 2724 */ 2725 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32); 2726 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc); 2727 2728 if (rf->channel <= 14) 2729 rfcsr = 0xa0; 2730 else 2731 rfcsr = 0x80; 2732 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2733 2734 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2735 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m); 2736 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m); 2737 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2738 2739 /* Band selection */ 2740 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 2741 if (rf->channel <= 14) 2742 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 2743 else 2744 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 2745 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 2746 2747 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34); 2748 if (rf->channel <= 14) 2749 rfcsr = 0x3c; 2750 else 2751 rfcsr = 0x20; 2752 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 2753 2754 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2755 if (rf->channel <= 14) 2756 rfcsr = 0x1a; 2757 else 2758 rfcsr = 0x12; 2759 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2760 2761 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2762 if (rf->channel >= 1 && rf->channel <= 14) 2763 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2764 else if (rf->channel >= 36 && rf->channel <= 64) 2765 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2766 else if (rf->channel >= 100 && rf->channel <= 128) 2767 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2768 else 2769 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2770 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2771 2772 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2773 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 2774 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2775 2776 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 2777 2778 if (rf->channel <= 14) { 2779 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 2780 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 2781 } else { 2782 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8); 2783 rt2800_rfcsr_write(rt2x00dev, 13, 0x23); 2784 } 2785 2786 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2787 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1); 2788 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2789 2790 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2791 if (rf->channel <= 14) { 2792 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5); 2793 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3); 2794 } else { 2795 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4); 2796 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2); 2797 } 2798 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2799 2800 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2801 if (rf->channel <= 14) 2802 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3); 2803 else 2804 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2); 2805 2806 if (txbf_enabled) 2807 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1); 2808 2809 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2810 2811 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 2812 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0); 2813 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2814 2815 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 2816 if (rf->channel <= 14) 2817 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b); 2818 else 2819 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f); 2820 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr); 2821 2822 if (rf->channel <= 14) { 2823 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 2824 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 2825 } else { 2826 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 2827 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 2828 } 2829 2830 /* Initiate VCO calibration */ 2831 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2832 if (rf->channel <= 14) { 2833 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2834 } else { 2835 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1); 2836 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1); 2837 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1); 2838 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1); 2839 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1); 2840 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2841 } 2842 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2843 2844 if (rf->channel >= 1 && rf->channel <= 14) { 2845 rfcsr = 0x23; 2846 if (txbf_enabled) 2847 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2848 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2849 2850 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 2851 } else if (rf->channel >= 36 && rf->channel <= 64) { 2852 rfcsr = 0x36; 2853 if (txbf_enabled) 2854 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2855 rt2800_rfcsr_write(rt2x00dev, 39, 0x36); 2856 2857 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb); 2858 } else if (rf->channel >= 100 && rf->channel <= 128) { 2859 rfcsr = 0x32; 2860 if (txbf_enabled) 2861 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2862 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2863 2864 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3); 2865 } else { 2866 rfcsr = 0x30; 2867 if (txbf_enabled) 2868 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2869 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2870 2871 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b); 2872 } 2873 } 2874 2875 #define POWER_BOUND 0x27 2876 #define POWER_BOUND_5G 0x2b 2877 2878 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev, 2879 struct ieee80211_conf *conf, 2880 struct rf_channel *rf, 2881 struct channel_info *info) 2882 { 2883 u8 rfcsr; 2884 2885 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2886 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2887 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2888 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 2889 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2890 2891 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2892 if (info->default_power1 > POWER_BOUND) 2893 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 2894 else 2895 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2896 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2897 2898 rt2800_freq_cal_mode1(rt2x00dev); 2899 2900 if (rf->channel <= 14) { 2901 if (rf->channel == 6) 2902 rt2800_bbp_write(rt2x00dev, 68, 0x0c); 2903 else 2904 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 2905 2906 if (rf->channel >= 1 && rf->channel <= 6) 2907 rt2800_bbp_write(rt2x00dev, 59, 0x0f); 2908 else if (rf->channel >= 7 && rf->channel <= 11) 2909 rt2800_bbp_write(rt2x00dev, 59, 0x0e); 2910 else if (rf->channel >= 12 && rf->channel <= 14) 2911 rt2800_bbp_write(rt2x00dev, 59, 0x0d); 2912 } 2913 } 2914 2915 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev, 2916 struct ieee80211_conf *conf, 2917 struct rf_channel *rf, 2918 struct channel_info *info) 2919 { 2920 u8 rfcsr; 2921 2922 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2923 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2924 2925 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 2926 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 2927 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 2928 2929 if (info->default_power1 > POWER_BOUND) 2930 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND); 2931 else 2932 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1); 2933 2934 if (info->default_power2 > POWER_BOUND) 2935 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND); 2936 else 2937 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2); 2938 2939 rt2800_freq_cal_mode1(rt2x00dev); 2940 2941 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2942 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2943 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2944 2945 if ( rt2x00dev->default_ant.tx_chain_num == 2 ) 2946 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2947 else 2948 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2949 2950 if ( rt2x00dev->default_ant.rx_chain_num == 2 ) 2951 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2952 else 2953 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2954 2955 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2956 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2957 2958 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2959 2960 rt2800_rfcsr_write(rt2x00dev, 31, 80); 2961 } 2962 2963 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 2964 struct ieee80211_conf *conf, 2965 struct rf_channel *rf, 2966 struct channel_info *info) 2967 { 2968 u8 rfcsr; 2969 2970 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2971 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2972 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2973 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 2974 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2975 2976 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2977 if (info->default_power1 > POWER_BOUND) 2978 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 2979 else 2980 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2981 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2982 2983 if (rt2x00_rt(rt2x00dev, RT5392)) { 2984 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 2985 if (info->default_power2 > POWER_BOUND) 2986 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND); 2987 else 2988 rt2x00_set_field8(&rfcsr, RFCSR50_TX, 2989 info->default_power2); 2990 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2991 } 2992 2993 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2994 if (rt2x00_rt(rt2x00dev, RT5392)) { 2995 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2996 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2997 } 2998 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2999 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3000 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3001 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3002 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3003 3004 rt2800_freq_cal_mode1(rt2x00dev); 3005 3006 if (rf->channel <= 14) { 3007 int idx = rf->channel-1; 3008 3009 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 3010 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3011 /* r55/r59 value array of channel 1~14 */ 3012 static const char r55_bt_rev[] = {0x83, 0x83, 3013 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, 3014 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; 3015 static const char r59_bt_rev[] = {0x0e, 0x0e, 3016 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, 3017 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; 3018 3019 rt2800_rfcsr_write(rt2x00dev, 55, 3020 r55_bt_rev[idx]); 3021 rt2800_rfcsr_write(rt2x00dev, 59, 3022 r59_bt_rev[idx]); 3023 } else { 3024 static const char r59_bt[] = {0x8b, 0x8b, 0x8b, 3025 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, 3026 0x88, 0x88, 0x86, 0x85, 0x84}; 3027 3028 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); 3029 } 3030 } else { 3031 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3032 static const char r55_nonbt_rev[] = {0x23, 0x23, 3033 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, 3034 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; 3035 static const char r59_nonbt_rev[] = {0x07, 0x07, 3036 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 3037 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; 3038 3039 rt2800_rfcsr_write(rt2x00dev, 55, 3040 r55_nonbt_rev[idx]); 3041 rt2800_rfcsr_write(rt2x00dev, 59, 3042 r59_nonbt_rev[idx]); 3043 } else if (rt2x00_rt(rt2x00dev, RT5390) || 3044 rt2x00_rt(rt2x00dev, RT5392) || 3045 rt2x00_rt(rt2x00dev, RT6352)) { 3046 static const char r59_non_bt[] = {0x8f, 0x8f, 3047 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, 3048 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; 3049 3050 rt2800_rfcsr_write(rt2x00dev, 59, 3051 r59_non_bt[idx]); 3052 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 3053 static const char r59_non_bt[] = {0x0b, 0x0b, 3054 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a, 3055 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06}; 3056 3057 rt2800_rfcsr_write(rt2x00dev, 59, 3058 r59_non_bt[idx]); 3059 } 3060 } 3061 } 3062 } 3063 3064 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, 3065 struct ieee80211_conf *conf, 3066 struct rf_channel *rf, 3067 struct channel_info *info) 3068 { 3069 u8 rfcsr, ep_reg; 3070 u32 reg; 3071 int power_bound; 3072 3073 /* TODO */ 3074 const bool is_11b = false; 3075 const bool is_type_ep = false; 3076 3077 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 3078 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3079 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0); 3080 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 3081 3082 /* Order of values on rf_channel entry: N, K, mod, R */ 3083 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff); 3084 3085 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9); 3086 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf); 3087 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8); 3088 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2); 3089 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr); 3090 3091 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3092 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1); 3093 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3); 3094 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3095 3096 if (rf->channel <= 14) { 3097 rt2800_rfcsr_write(rt2x00dev, 10, 0x90); 3098 /* FIXME: RF11 owerwrite ? */ 3099 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A); 3100 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 3101 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3102 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3103 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A); 3104 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 3105 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3106 rt2800_rfcsr_write(rt2x00dev, 36, 0x80); 3107 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 3108 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 3109 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B); 3110 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D); 3111 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B); 3112 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5); 3113 rt2800_rfcsr_write(rt2x00dev, 43, 0x72); 3114 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E); 3115 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2); 3116 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B); 3117 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 3118 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E); 3119 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 3120 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 3121 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1); 3122 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 3123 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 3124 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 3125 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 3126 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 3127 3128 /* TODO RF27 <- tssi */ 3129 3130 rfcsr = rf->channel <= 10 ? 0x07 : 0x06; 3131 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 3132 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr); 3133 3134 if (is_11b) { 3135 /* CCK */ 3136 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8); 3137 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0); 3138 if (is_type_ep) 3139 rt2800_rfcsr_write(rt2x00dev, 55, 0x06); 3140 else 3141 rt2800_rfcsr_write(rt2x00dev, 55, 0x47); 3142 } else { 3143 /* OFDM */ 3144 if (is_type_ep) 3145 rt2800_rfcsr_write(rt2x00dev, 55, 0x03); 3146 else 3147 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 3148 } 3149 3150 power_bound = POWER_BOUND; 3151 ep_reg = 0x2; 3152 } else { 3153 rt2800_rfcsr_write(rt2x00dev, 10, 0x97); 3154 /* FIMXE: RF11 overwrite */ 3155 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 3156 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF); 3157 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3158 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 3159 rt2800_rfcsr_write(rt2x00dev, 37, 0x04); 3160 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 3161 rt2800_rfcsr_write(rt2x00dev, 40, 0x42); 3162 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB); 3163 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7); 3164 rt2800_rfcsr_write(rt2x00dev, 45, 0x41); 3165 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 3166 rt2800_rfcsr_write(rt2x00dev, 57, 0x77); 3167 rt2800_rfcsr_write(rt2x00dev, 60, 0x05); 3168 rt2800_rfcsr_write(rt2x00dev, 61, 0x01); 3169 3170 /* TODO RF27 <- tssi */ 3171 3172 if (rf->channel >= 36 && rf->channel <= 64) { 3173 3174 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E); 3175 rt2800_rfcsr_write(rt2x00dev, 13, 0x22); 3176 rt2800_rfcsr_write(rt2x00dev, 22, 0x60); 3177 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F); 3178 if (rf->channel <= 50) 3179 rt2800_rfcsr_write(rt2x00dev, 24, 0x09); 3180 else if (rf->channel >= 52) 3181 rt2800_rfcsr_write(rt2x00dev, 24, 0x07); 3182 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C); 3183 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B); 3184 rt2800_rfcsr_write(rt2x00dev, 44, 0X40); 3185 rt2800_rfcsr_write(rt2x00dev, 46, 0X00); 3186 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE); 3187 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C); 3188 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8); 3189 if (rf->channel <= 50) { 3190 rt2800_rfcsr_write(rt2x00dev, 55, 0x06), 3191 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3); 3192 } else if (rf->channel >= 52) { 3193 rt2800_rfcsr_write(rt2x00dev, 55, 0x04); 3194 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3195 } 3196 3197 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3198 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F); 3199 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3200 3201 } else if (rf->channel >= 100 && rf->channel <= 165) { 3202 3203 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E); 3204 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3205 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3206 if (rf->channel <= 153) { 3207 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C); 3208 rt2800_rfcsr_write(rt2x00dev, 24, 0x06); 3209 } else if (rf->channel >= 155) { 3210 rt2800_rfcsr_write(rt2x00dev, 23, 0x38); 3211 rt2800_rfcsr_write(rt2x00dev, 24, 0x05); 3212 } 3213 if (rf->channel <= 138) { 3214 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A); 3215 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B); 3216 rt2800_rfcsr_write(rt2x00dev, 44, 0x20); 3217 rt2800_rfcsr_write(rt2x00dev, 46, 0x18); 3218 } else if (rf->channel >= 140) { 3219 rt2800_rfcsr_write(rt2x00dev, 39, 0x18); 3220 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B); 3221 rt2800_rfcsr_write(rt2x00dev, 44, 0x10); 3222 rt2800_rfcsr_write(rt2x00dev, 46, 0X08); 3223 } 3224 if (rf->channel <= 124) 3225 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC); 3226 else if (rf->channel >= 126) 3227 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC); 3228 if (rf->channel <= 138) 3229 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3230 else if (rf->channel >= 140) 3231 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3232 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB); 3233 if (rf->channel <= 138) 3234 rt2800_rfcsr_write(rt2x00dev, 55, 0x01); 3235 else if (rf->channel >= 140) 3236 rt2800_rfcsr_write(rt2x00dev, 55, 0x00); 3237 if (rf->channel <= 128) 3238 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3239 else if (rf->channel >= 130) 3240 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB); 3241 if (rf->channel <= 116) 3242 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D); 3243 else if (rf->channel >= 118) 3244 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3245 if (rf->channel <= 138) 3246 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F); 3247 else if (rf->channel >= 140) 3248 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C); 3249 if (rf->channel <= 116) 3250 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D); 3251 else if (rf->channel >= 118) 3252 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3253 } 3254 3255 power_bound = POWER_BOUND_5G; 3256 ep_reg = 0x3; 3257 } 3258 3259 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3260 if (info->default_power1 > power_bound) 3261 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound); 3262 else 3263 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3264 if (is_type_ep) 3265 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg); 3266 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3267 3268 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3269 if (info->default_power2 > power_bound) 3270 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound); 3271 else 3272 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2); 3273 if (is_type_ep) 3274 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg); 3275 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3276 3277 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3278 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3279 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3280 3281 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 3282 rt2x00dev->default_ant.tx_chain_num >= 1); 3283 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 3284 rt2x00dev->default_ant.tx_chain_num == 2); 3285 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3286 3287 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 3288 rt2x00dev->default_ant.rx_chain_num >= 1); 3289 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 3290 rt2x00dev->default_ant.rx_chain_num == 2); 3291 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3292 3293 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3294 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4); 3295 3296 if (conf_is_ht40(conf)) 3297 rt2800_rfcsr_write(rt2x00dev, 30, 0x16); 3298 else 3299 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 3300 3301 if (!is_11b) { 3302 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3303 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3304 } 3305 3306 /* TODO proper frequency adjustment */ 3307 rt2800_freq_cal_mode1(rt2x00dev); 3308 3309 /* TODO merge with others */ 3310 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3311 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3312 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3313 3314 /* BBP settings */ 3315 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3316 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3317 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3318 3319 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18); 3320 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08); 3321 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38); 3322 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92); 3323 3324 /* GLRT band configuration */ 3325 rt2800_bbp_write(rt2x00dev, 195, 128); 3326 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0); 3327 rt2800_bbp_write(rt2x00dev, 195, 129); 3328 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E); 3329 rt2800_bbp_write(rt2x00dev, 195, 130); 3330 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28); 3331 rt2800_bbp_write(rt2x00dev, 195, 131); 3332 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20); 3333 rt2800_bbp_write(rt2x00dev, 195, 133); 3334 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F); 3335 rt2800_bbp_write(rt2x00dev, 195, 124); 3336 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F); 3337 } 3338 3339 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev, 3340 struct ieee80211_conf *conf, 3341 struct rf_channel *rf, 3342 struct channel_info *info) 3343 { 3344 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 3345 u8 rx_agc_fc, tx_agc_fc; 3346 u8 rfcsr; 3347 3348 /* Frequeny plan setting */ 3349 /* Rdiv setting (set 0x03 if Xtal==20) 3350 * R13[1:0] 3351 */ 3352 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 3353 rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620, 3354 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0); 3355 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 3356 3357 /* N setting 3358 * R20[7:0] in rf->rf1 3359 * R21[0] always 0 3360 */ 3361 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 3362 rfcsr = (rf->rf1 & 0x00ff); 3363 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 3364 3365 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3366 rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0); 3367 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3368 3369 /* K setting (always 0) 3370 * R16[3:0] (RF PLL freq selection) 3371 */ 3372 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3373 rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0); 3374 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3375 3376 /* D setting (always 0) 3377 * R22[2:0] (D=15, R22[2:0]=<111>) 3378 */ 3379 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 3380 rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0); 3381 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 3382 3383 /* Ksd setting 3384 * Ksd: R17<7:0> in rf->rf2 3385 * R18<7:0> in rf->rf3 3386 * R19<1:0> in rf->rf4 3387 */ 3388 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 3389 rfcsr = rf->rf2; 3390 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 3391 3392 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 3393 rfcsr = rf->rf3; 3394 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 3395 3396 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19); 3397 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4); 3398 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr); 3399 3400 /* Default: XO=20MHz , SDM mode */ 3401 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3402 rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80); 3403 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3404 3405 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3406 rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1); 3407 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3408 3409 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3410 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620, 3411 rt2x00dev->default_ant.tx_chain_num != 1); 3412 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3413 3414 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 3415 rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620, 3416 rt2x00dev->default_ant.tx_chain_num != 1); 3417 rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620, 3418 rt2x00dev->default_ant.rx_chain_num != 1); 3419 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 3420 3421 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42); 3422 rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620, 3423 rt2x00dev->default_ant.tx_chain_num != 1); 3424 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 3425 3426 /* RF for DC Cal BW */ 3427 if (conf_is_ht40(conf)) { 3428 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 3429 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 3430 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 3431 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 3432 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 3433 } else { 3434 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20); 3435 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20); 3436 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00); 3437 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20); 3438 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20); 3439 } 3440 3441 if (conf_is_ht40(conf)) { 3442 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08); 3443 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08); 3444 } else { 3445 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28); 3446 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28); 3447 } 3448 3449 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28); 3450 rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40, 3451 conf_is_ht40(conf) && (rf->channel == 11)); 3452 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr); 3453 3454 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) { 3455 if (conf_is_ht40(conf)) { 3456 rx_agc_fc = drv_data->rx_calibration_bw40; 3457 tx_agc_fc = drv_data->tx_calibration_bw40; 3458 } else { 3459 rx_agc_fc = drv_data->rx_calibration_bw20; 3460 tx_agc_fc = drv_data->tx_calibration_bw20; 3461 } 3462 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 3463 rfcsr &= (~0x3F); 3464 rfcsr |= rx_agc_fc; 3465 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr); 3466 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 3467 rfcsr &= (~0x3F); 3468 rfcsr |= rx_agc_fc; 3469 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr); 3470 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6); 3471 rfcsr &= (~0x3F); 3472 rfcsr |= rx_agc_fc; 3473 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr); 3474 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7); 3475 rfcsr &= (~0x3F); 3476 rfcsr |= rx_agc_fc; 3477 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr); 3478 3479 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 3480 rfcsr &= (~0x3F); 3481 rfcsr |= tx_agc_fc; 3482 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr); 3483 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 3484 rfcsr &= (~0x3F); 3485 rfcsr |= tx_agc_fc; 3486 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr); 3487 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58); 3488 rfcsr &= (~0x3F); 3489 rfcsr |= tx_agc_fc; 3490 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr); 3491 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59); 3492 rfcsr &= (~0x3F); 3493 rfcsr |= tx_agc_fc; 3494 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr); 3495 } 3496 } 3497 3498 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev, 3499 struct ieee80211_channel *chan, 3500 int power_level) { 3501 u16 eeprom, target_power, max_power; 3502 u32 mac_sys_ctrl, mac_status; 3503 u32 reg; 3504 u8 bbp; 3505 int i; 3506 3507 /* hardware unit is 0.5dBm, limited to 23.5dBm */ 3508 power_level *= 2; 3509 if (power_level > 0x2f) 3510 power_level = 0x2f; 3511 3512 max_power = chan->max_power * 2; 3513 if (max_power > 0x2f) 3514 max_power = 0x2f; 3515 3516 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0); 3517 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, power_level); 3518 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, power_level); 3519 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, max_power); 3520 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, max_power); 3521 3522 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 3523 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) { 3524 /* init base power by eeprom target power */ 3525 target_power = rt2800_eeprom_read(rt2x00dev, 3526 EEPROM_TXPOWER_INIT); 3527 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power); 3528 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power); 3529 } 3530 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg); 3531 3532 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 3533 rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0); 3534 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 3535 3536 /* Save MAC SYS CTRL registers */ 3537 mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 3538 /* Disable Tx/Rx */ 3539 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 3540 /* Check MAC Tx/Rx idle */ 3541 for (i = 0; i < 10000; i++) { 3542 mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 3543 if (mac_status & 0x3) 3544 usleep_range(50, 200); 3545 else 3546 break; 3547 } 3548 3549 if (i == 10000) 3550 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n"); 3551 3552 if (chan->center_freq > 2457) { 3553 bbp = rt2800_bbp_read(rt2x00dev, 30); 3554 bbp = 0x40; 3555 rt2800_bbp_write(rt2x00dev, 30, bbp); 3556 rt2800_rfcsr_write(rt2x00dev, 39, 0); 3557 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3558 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb); 3559 else 3560 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b); 3561 } else { 3562 bbp = rt2800_bbp_read(rt2x00dev, 30); 3563 bbp = 0x1f; 3564 rt2800_bbp_write(rt2x00dev, 30, bbp); 3565 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 3566 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3567 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb); 3568 else 3569 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); 3570 } 3571 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl); 3572 3573 rt2800_vco_calibration(rt2x00dev); 3574 } 3575 3576 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, 3577 const unsigned int word, 3578 const u8 value) 3579 { 3580 u8 chain, reg; 3581 3582 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) { 3583 reg = rt2800_bbp_read(rt2x00dev, 27); 3584 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); 3585 rt2800_bbp_write(rt2x00dev, 27, reg); 3586 3587 rt2800_bbp_write(rt2x00dev, word, value); 3588 } 3589 } 3590 3591 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel) 3592 { 3593 u8 cal; 3594 3595 /* TX0 IQ Gain */ 3596 rt2800_bbp_write(rt2x00dev, 158, 0x2c); 3597 if (channel <= 14) 3598 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G); 3599 else if (channel >= 36 && channel <= 64) 3600 cal = rt2x00_eeprom_byte(rt2x00dev, 3601 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G); 3602 else if (channel >= 100 && channel <= 138) 3603 cal = rt2x00_eeprom_byte(rt2x00dev, 3604 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G); 3605 else if (channel >= 140 && channel <= 165) 3606 cal = rt2x00_eeprom_byte(rt2x00dev, 3607 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G); 3608 else 3609 cal = 0; 3610 rt2800_bbp_write(rt2x00dev, 159, cal); 3611 3612 /* TX0 IQ Phase */ 3613 rt2800_bbp_write(rt2x00dev, 158, 0x2d); 3614 if (channel <= 14) 3615 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G); 3616 else if (channel >= 36 && channel <= 64) 3617 cal = rt2x00_eeprom_byte(rt2x00dev, 3618 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G); 3619 else if (channel >= 100 && channel <= 138) 3620 cal = rt2x00_eeprom_byte(rt2x00dev, 3621 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G); 3622 else if (channel >= 140 && channel <= 165) 3623 cal = rt2x00_eeprom_byte(rt2x00dev, 3624 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G); 3625 else 3626 cal = 0; 3627 rt2800_bbp_write(rt2x00dev, 159, cal); 3628 3629 /* TX1 IQ Gain */ 3630 rt2800_bbp_write(rt2x00dev, 158, 0x4a); 3631 if (channel <= 14) 3632 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G); 3633 else if (channel >= 36 && channel <= 64) 3634 cal = rt2x00_eeprom_byte(rt2x00dev, 3635 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G); 3636 else if (channel >= 100 && channel <= 138) 3637 cal = rt2x00_eeprom_byte(rt2x00dev, 3638 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G); 3639 else if (channel >= 140 && channel <= 165) 3640 cal = rt2x00_eeprom_byte(rt2x00dev, 3641 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G); 3642 else 3643 cal = 0; 3644 rt2800_bbp_write(rt2x00dev, 159, cal); 3645 3646 /* TX1 IQ Phase */ 3647 rt2800_bbp_write(rt2x00dev, 158, 0x4b); 3648 if (channel <= 14) 3649 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G); 3650 else if (channel >= 36 && channel <= 64) 3651 cal = rt2x00_eeprom_byte(rt2x00dev, 3652 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G); 3653 else if (channel >= 100 && channel <= 138) 3654 cal = rt2x00_eeprom_byte(rt2x00dev, 3655 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G); 3656 else if (channel >= 140 && channel <= 165) 3657 cal = rt2x00_eeprom_byte(rt2x00dev, 3658 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G); 3659 else 3660 cal = 0; 3661 rt2800_bbp_write(rt2x00dev, 159, cal); 3662 3663 /* FIXME: possible RX0, RX1 callibration ? */ 3664 3665 /* RF IQ compensation control */ 3666 rt2800_bbp_write(rt2x00dev, 158, 0x04); 3667 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL); 3668 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3669 3670 /* RF IQ imbalance compensation control */ 3671 rt2800_bbp_write(rt2x00dev, 158, 0x03); 3672 cal = rt2x00_eeprom_byte(rt2x00dev, 3673 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL); 3674 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3675 } 3676 3677 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev, 3678 unsigned int channel, 3679 char txpower) 3680 { 3681 if (rt2x00_rt(rt2x00dev, RT3593)) 3682 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC); 3683 3684 if (channel <= 14) 3685 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER); 3686 3687 if (rt2x00_rt(rt2x00dev, RT3593)) 3688 return clamp_t(char, txpower, MIN_A_TXPOWER_3593, 3689 MAX_A_TXPOWER_3593); 3690 else 3691 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER); 3692 } 3693 3694 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 3695 struct ieee80211_conf *conf, 3696 struct rf_channel *rf, 3697 struct channel_info *info) 3698 { 3699 u32 reg; 3700 u32 tx_pin; 3701 u8 bbp, rfcsr; 3702 3703 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3704 info->default_power1); 3705 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3706 info->default_power2); 3707 if (rt2x00dev->default_ant.tx_chain_num > 2) 3708 info->default_power3 = 3709 rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3710 info->default_power3); 3711 3712 switch (rt2x00dev->chip.rf) { 3713 case RF2020: 3714 case RF3020: 3715 case RF3021: 3716 case RF3022: 3717 case RF3320: 3718 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 3719 break; 3720 case RF3052: 3721 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); 3722 break; 3723 case RF3053: 3724 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info); 3725 break; 3726 case RF3290: 3727 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info); 3728 break; 3729 case RF3322: 3730 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); 3731 break; 3732 case RF3070: 3733 case RF5350: 3734 case RF5360: 3735 case RF5362: 3736 case RF5370: 3737 case RF5372: 3738 case RF5390: 3739 case RF5392: 3740 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); 3741 break; 3742 case RF5592: 3743 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info); 3744 break; 3745 case RF7620: 3746 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info); 3747 break; 3748 default: 3749 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 3750 } 3751 3752 if (rt2x00_rf(rt2x00dev, RF3070) || 3753 rt2x00_rf(rt2x00dev, RF3290) || 3754 rt2x00_rf(rt2x00dev, RF3322) || 3755 rt2x00_rf(rt2x00dev, RF5350) || 3756 rt2x00_rf(rt2x00dev, RF5360) || 3757 rt2x00_rf(rt2x00dev, RF5362) || 3758 rt2x00_rf(rt2x00dev, RF5370) || 3759 rt2x00_rf(rt2x00dev, RF5372) || 3760 rt2x00_rf(rt2x00dev, RF5390) || 3761 rt2x00_rf(rt2x00dev, RF5392)) { 3762 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 3763 if (rt2x00_rf(rt2x00dev, RF3322)) { 3764 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M, 3765 conf_is_ht40(conf)); 3766 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M, 3767 conf_is_ht40(conf)); 3768 } else { 3769 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 3770 conf_is_ht40(conf)); 3771 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 3772 conf_is_ht40(conf)); 3773 } 3774 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 3775 3776 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3777 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3778 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3779 } 3780 3781 /* 3782 * Change BBP settings 3783 */ 3784 3785 if (rt2x00_rt(rt2x00dev, RT3352)) { 3786 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3787 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3788 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3789 3790 rt2800_bbp_write(rt2x00dev, 27, 0x0); 3791 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 3792 rt2800_bbp_write(rt2x00dev, 27, 0x20); 3793 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 3794 rt2800_bbp_write(rt2x00dev, 86, 0x38); 3795 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 3796 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 3797 if (rf->channel > 14) { 3798 /* Disable CCK Packet detection on 5GHz */ 3799 rt2800_bbp_write(rt2x00dev, 70, 0x00); 3800 } else { 3801 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 3802 } 3803 3804 if (conf_is_ht40(conf)) 3805 rt2800_bbp_write(rt2x00dev, 105, 0x04); 3806 else 3807 rt2800_bbp_write(rt2x00dev, 105, 0x34); 3808 3809 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3810 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3811 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3812 rt2800_bbp_write(rt2x00dev, 77, 0x98); 3813 } else { 3814 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3815 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3816 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3817 rt2800_bbp_write(rt2x00dev, 86, 0); 3818 } 3819 3820 if (rf->channel <= 14) { 3821 if (!rt2x00_rt(rt2x00dev, RT5390) && 3822 !rt2x00_rt(rt2x00dev, RT5392) && 3823 !rt2x00_rt(rt2x00dev, RT6352)) { 3824 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 3825 rt2800_bbp_write(rt2x00dev, 82, 0x62); 3826 rt2800_bbp_write(rt2x00dev, 75, 0x46); 3827 } else { 3828 if (rt2x00_rt(rt2x00dev, RT3593)) 3829 rt2800_bbp_write(rt2x00dev, 82, 0x62); 3830 else 3831 rt2800_bbp_write(rt2x00dev, 82, 0x84); 3832 rt2800_bbp_write(rt2x00dev, 75, 0x50); 3833 } 3834 if (rt2x00_rt(rt2x00dev, RT3593)) 3835 rt2800_bbp_write(rt2x00dev, 83, 0x8a); 3836 } 3837 3838 } else { 3839 if (rt2x00_rt(rt2x00dev, RT3572)) 3840 rt2800_bbp_write(rt2x00dev, 82, 0x94); 3841 else if (rt2x00_rt(rt2x00dev, RT3593)) 3842 rt2800_bbp_write(rt2x00dev, 82, 0x82); 3843 else if (!rt2x00_rt(rt2x00dev, RT6352)) 3844 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 3845 3846 if (rt2x00_rt(rt2x00dev, RT3593)) 3847 rt2800_bbp_write(rt2x00dev, 83, 0x9a); 3848 3849 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) 3850 rt2800_bbp_write(rt2x00dev, 75, 0x46); 3851 else 3852 rt2800_bbp_write(rt2x00dev, 75, 0x50); 3853 } 3854 3855 reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG); 3856 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); 3857 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); 3858 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); 3859 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); 3860 3861 if (rt2x00_rt(rt2x00dev, RT3572)) 3862 rt2800_rfcsr_write(rt2x00dev, 8, 0); 3863 3864 if (rt2x00_rt(rt2x00dev, RT6352)) 3865 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 3866 else 3867 tx_pin = 0; 3868 3869 switch (rt2x00dev->default_ant.tx_chain_num) { 3870 case 3: 3871 /* Turn on tertiary PAs */ 3872 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 3873 rf->channel > 14); 3874 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 3875 rf->channel <= 14); 3876 /* fall-through */ 3877 case 2: 3878 /* Turn on secondary PAs */ 3879 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 3880 rf->channel > 14); 3881 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 3882 rf->channel <= 14); 3883 /* fall-through */ 3884 case 1: 3885 /* Turn on primary PAs */ 3886 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 3887 rf->channel > 14); 3888 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) 3889 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 3890 else 3891 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 3892 rf->channel <= 14); 3893 break; 3894 } 3895 3896 switch (rt2x00dev->default_ant.rx_chain_num) { 3897 case 3: 3898 /* Turn on tertiary LNAs */ 3899 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1); 3900 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1); 3901 /* fall-through */ 3902 case 2: 3903 /* Turn on secondary LNAs */ 3904 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); 3905 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); 3906 /* fall-through */ 3907 case 1: 3908 /* Turn on primary LNAs */ 3909 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); 3910 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); 3911 break; 3912 } 3913 3914 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); 3915 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); 3916 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); /* mt7620 */ 3917 3918 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 3919 3920 if (rt2x00_rt(rt2x00dev, RT3572)) { 3921 rt2800_rfcsr_write(rt2x00dev, 8, 0x80); 3922 3923 /* AGC init */ 3924 if (rf->channel <= 14) 3925 reg = 0x1c + (2 * rt2x00dev->lna_gain); 3926 else 3927 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 3928 3929 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3930 } 3931 3932 if (rt2x00_rt(rt2x00dev, RT3593)) { 3933 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 3934 3935 /* Band selection */ 3936 if (rt2x00_is_usb(rt2x00dev) || 3937 rt2x00_is_pcie(rt2x00dev)) { 3938 /* GPIO #8 controls all paths */ 3939 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); 3940 if (rf->channel <= 14) 3941 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); 3942 else 3943 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); 3944 } 3945 3946 /* LNA PE control. */ 3947 if (rt2x00_is_usb(rt2x00dev)) { 3948 /* GPIO #4 controls PE0 and PE1, 3949 * GPIO #7 controls PE2 3950 */ 3951 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 3952 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 3953 3954 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 3955 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 3956 } else if (rt2x00_is_pcie(rt2x00dev)) { 3957 /* GPIO #4 controls PE0, PE1 and PE2 */ 3958 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 3959 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 3960 } 3961 3962 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 3963 3964 /* AGC init */ 3965 if (rf->channel <= 14) 3966 reg = 0x1c + 2 * rt2x00dev->lna_gain; 3967 else 3968 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 3969 3970 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3971 3972 usleep_range(1000, 1500); 3973 } 3974 3975 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) { 3976 reg = 0x10; 3977 if (!conf_is_ht40(conf)) { 3978 if (rt2x00_rt(rt2x00dev, RT6352) && 3979 rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 3980 reg |= 0x5; 3981 } else { 3982 reg |= 0xa; 3983 } 3984 } 3985 rt2800_bbp_write(rt2x00dev, 195, 141); 3986 rt2800_bbp_write(rt2x00dev, 196, reg); 3987 3988 /* AGC init */ 3989 if (rt2x00_rt(rt2x00dev, RT6352)) 3990 reg = 0x04; 3991 else 3992 reg = rf->channel <= 14 ? 0x1c : 0x24; 3993 3994 reg += 2 * rt2x00dev->lna_gain; 3995 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3996 3997 rt2800_iq_calibrate(rt2x00dev, rf->channel); 3998 } 3999 4000 bbp = rt2800_bbp_read(rt2x00dev, 4); 4001 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 4002 rt2800_bbp_write(rt2x00dev, 4, bbp); 4003 4004 bbp = rt2800_bbp_read(rt2x00dev, 3); 4005 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); 4006 rt2800_bbp_write(rt2x00dev, 3, bbp); 4007 4008 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 4009 if (conf_is_ht40(conf)) { 4010 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 4011 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4012 rt2800_bbp_write(rt2x00dev, 73, 0x16); 4013 } else { 4014 rt2800_bbp_write(rt2x00dev, 69, 0x16); 4015 rt2800_bbp_write(rt2x00dev, 70, 0x08); 4016 rt2800_bbp_write(rt2x00dev, 73, 0x11); 4017 } 4018 } 4019 4020 usleep_range(1000, 1500); 4021 4022 /* 4023 * Clear channel statistic counters 4024 */ 4025 reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 4026 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 4027 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 4028 4029 /* 4030 * Clear update flag 4031 */ 4032 if (rt2x00_rt(rt2x00dev, RT3352) || 4033 rt2x00_rt(rt2x00dev, RT5350)) { 4034 bbp = rt2800_bbp_read(rt2x00dev, 49); 4035 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0); 4036 rt2800_bbp_write(rt2x00dev, 49, bbp); 4037 } 4038 } 4039 4040 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) 4041 { 4042 u8 tssi_bounds[9]; 4043 u8 current_tssi; 4044 u16 eeprom; 4045 u8 step; 4046 int i; 4047 4048 /* 4049 * First check if temperature compensation is supported. 4050 */ 4051 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 4052 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC)) 4053 return 0; 4054 4055 /* 4056 * Read TSSI boundaries for temperature compensation from 4057 * the EEPROM. 4058 * 4059 * Array idx 0 1 2 3 4 5 6 7 8 4060 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4 4061 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 4062 */ 4063 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 4064 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1); 4065 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4066 EEPROM_TSSI_BOUND_BG1_MINUS4); 4067 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4068 EEPROM_TSSI_BOUND_BG1_MINUS3); 4069 4070 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2); 4071 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4072 EEPROM_TSSI_BOUND_BG2_MINUS2); 4073 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4074 EEPROM_TSSI_BOUND_BG2_MINUS1); 4075 4076 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3); 4077 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4078 EEPROM_TSSI_BOUND_BG3_REF); 4079 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4080 EEPROM_TSSI_BOUND_BG3_PLUS1); 4081 4082 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4); 4083 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4084 EEPROM_TSSI_BOUND_BG4_PLUS2); 4085 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4086 EEPROM_TSSI_BOUND_BG4_PLUS3); 4087 4088 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5); 4089 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4090 EEPROM_TSSI_BOUND_BG5_PLUS4); 4091 4092 step = rt2x00_get_field16(eeprom, 4093 EEPROM_TSSI_BOUND_BG5_AGC_STEP); 4094 } else { 4095 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1); 4096 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4097 EEPROM_TSSI_BOUND_A1_MINUS4); 4098 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4099 EEPROM_TSSI_BOUND_A1_MINUS3); 4100 4101 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2); 4102 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4103 EEPROM_TSSI_BOUND_A2_MINUS2); 4104 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4105 EEPROM_TSSI_BOUND_A2_MINUS1); 4106 4107 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3); 4108 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4109 EEPROM_TSSI_BOUND_A3_REF); 4110 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4111 EEPROM_TSSI_BOUND_A3_PLUS1); 4112 4113 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4); 4114 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4115 EEPROM_TSSI_BOUND_A4_PLUS2); 4116 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4117 EEPROM_TSSI_BOUND_A4_PLUS3); 4118 4119 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5); 4120 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4121 EEPROM_TSSI_BOUND_A5_PLUS4); 4122 4123 step = rt2x00_get_field16(eeprom, 4124 EEPROM_TSSI_BOUND_A5_AGC_STEP); 4125 } 4126 4127 /* 4128 * Check if temperature compensation is supported. 4129 */ 4130 if (tssi_bounds[4] == 0xff || step == 0xff) 4131 return 0; 4132 4133 /* 4134 * Read current TSSI (BBP 49). 4135 */ 4136 current_tssi = rt2800_bbp_read(rt2x00dev, 49); 4137 4138 /* 4139 * Compare TSSI value (BBP49) with the compensation boundaries 4140 * from the EEPROM and increase or decrease tx power. 4141 */ 4142 for (i = 0; i <= 3; i++) { 4143 if (current_tssi > tssi_bounds[i]) 4144 break; 4145 } 4146 4147 if (i == 4) { 4148 for (i = 8; i >= 5; i--) { 4149 if (current_tssi < tssi_bounds[i]) 4150 break; 4151 } 4152 } 4153 4154 return (i - 4) * step; 4155 } 4156 4157 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, 4158 enum nl80211_band band) 4159 { 4160 u16 eeprom; 4161 u8 comp_en; 4162 u8 comp_type; 4163 int comp_value = 0; 4164 4165 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA); 4166 4167 /* 4168 * HT40 compensation not required. 4169 */ 4170 if (eeprom == 0xffff || 4171 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4172 return 0; 4173 4174 if (band == NL80211_BAND_2GHZ) { 4175 comp_en = rt2x00_get_field16(eeprom, 4176 EEPROM_TXPOWER_DELTA_ENABLE_2G); 4177 if (comp_en) { 4178 comp_type = rt2x00_get_field16(eeprom, 4179 EEPROM_TXPOWER_DELTA_TYPE_2G); 4180 comp_value = rt2x00_get_field16(eeprom, 4181 EEPROM_TXPOWER_DELTA_VALUE_2G); 4182 if (!comp_type) 4183 comp_value = -comp_value; 4184 } 4185 } else { 4186 comp_en = rt2x00_get_field16(eeprom, 4187 EEPROM_TXPOWER_DELTA_ENABLE_5G); 4188 if (comp_en) { 4189 comp_type = rt2x00_get_field16(eeprom, 4190 EEPROM_TXPOWER_DELTA_TYPE_5G); 4191 comp_value = rt2x00_get_field16(eeprom, 4192 EEPROM_TXPOWER_DELTA_VALUE_5G); 4193 if (!comp_type) 4194 comp_value = -comp_value; 4195 } 4196 } 4197 4198 return comp_value; 4199 } 4200 4201 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev, 4202 int power_level, int max_power) 4203 { 4204 int delta; 4205 4206 if (rt2x00_has_cap_power_limit(rt2x00dev)) 4207 return 0; 4208 4209 /* 4210 * XXX: We don't know the maximum transmit power of our hardware since 4211 * the EEPROM doesn't expose it. We only know that we are calibrated 4212 * to 100% tx power. 4213 * 4214 * Hence, we assume the regulatory limit that cfg80211 calulated for 4215 * the current channel is our maximum and if we are requested to lower 4216 * the value we just reduce our tx power accordingly. 4217 */ 4218 delta = power_level - max_power; 4219 return min(delta, 0); 4220 } 4221 4222 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, 4223 enum nl80211_band band, int power_level, 4224 u8 txpower, int delta) 4225 { 4226 u16 eeprom; 4227 u8 criterion; 4228 u8 eirp_txpower; 4229 u8 eirp_txpower_criterion; 4230 u8 reg_limit; 4231 4232 if (rt2x00_rt(rt2x00dev, RT3593)) 4233 return min_t(u8, txpower, 0xc); 4234 4235 if (rt2x00_has_cap_power_limit(rt2x00dev)) { 4236 /* 4237 * Check if eirp txpower exceed txpower_limit. 4238 * We use OFDM 6M as criterion and its eirp txpower 4239 * is stored at EEPROM_EIRP_MAX_TX_POWER. 4240 * .11b data rate need add additional 4dbm 4241 * when calculating eirp txpower. 4242 */ 4243 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4244 EEPROM_TXPOWER_BYRATE, 4245 1); 4246 criterion = rt2x00_get_field16(eeprom, 4247 EEPROM_TXPOWER_BYRATE_RATE0); 4248 4249 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 4250 4251 if (band == NL80211_BAND_2GHZ) 4252 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4253 EEPROM_EIRP_MAX_TX_POWER_2GHZ); 4254 else 4255 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4256 EEPROM_EIRP_MAX_TX_POWER_5GHZ); 4257 4258 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) + 4259 (is_rate_b ? 4 : 0) + delta; 4260 4261 reg_limit = (eirp_txpower > power_level) ? 4262 (eirp_txpower - power_level) : 0; 4263 } else 4264 reg_limit = 0; 4265 4266 txpower = max(0, txpower + delta - reg_limit); 4267 return min_t(u8, txpower, 0xc); 4268 } 4269 4270 4271 enum { 4272 TX_PWR_CFG_0_IDX, 4273 TX_PWR_CFG_1_IDX, 4274 TX_PWR_CFG_2_IDX, 4275 TX_PWR_CFG_3_IDX, 4276 TX_PWR_CFG_4_IDX, 4277 TX_PWR_CFG_5_IDX, 4278 TX_PWR_CFG_6_IDX, 4279 TX_PWR_CFG_7_IDX, 4280 TX_PWR_CFG_8_IDX, 4281 TX_PWR_CFG_9_IDX, 4282 TX_PWR_CFG_0_EXT_IDX, 4283 TX_PWR_CFG_1_EXT_IDX, 4284 TX_PWR_CFG_2_EXT_IDX, 4285 TX_PWR_CFG_3_EXT_IDX, 4286 TX_PWR_CFG_4_EXT_IDX, 4287 TX_PWR_CFG_IDX_COUNT, 4288 }; 4289 4290 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, 4291 struct ieee80211_channel *chan, 4292 int power_level) 4293 { 4294 u8 txpower; 4295 u16 eeprom; 4296 u32 regs[TX_PWR_CFG_IDX_COUNT]; 4297 unsigned int offset; 4298 enum nl80211_band band = chan->band; 4299 int delta; 4300 int i; 4301 4302 memset(regs, '\0', sizeof(regs)); 4303 4304 /* TODO: adapt TX power reduction from the rt28xx code */ 4305 4306 /* calculate temperature compensation delta */ 4307 delta = rt2800_get_gain_calibration_delta(rt2x00dev); 4308 4309 if (band == NL80211_BAND_5GHZ) 4310 offset = 16; 4311 else 4312 offset = 0; 4313 4314 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4315 offset += 8; 4316 4317 /* read the next four txpower values */ 4318 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4319 offset); 4320 4321 /* CCK 1MBS,2MBS */ 4322 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4323 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4324 txpower, delta); 4325 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4326 TX_PWR_CFG_0_CCK1_CH0, txpower); 4327 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4328 TX_PWR_CFG_0_CCK1_CH1, txpower); 4329 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4330 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower); 4331 4332 /* CCK 5.5MBS,11MBS */ 4333 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4334 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4335 txpower, delta); 4336 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4337 TX_PWR_CFG_0_CCK5_CH0, txpower); 4338 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4339 TX_PWR_CFG_0_CCK5_CH1, txpower); 4340 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4341 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower); 4342 4343 /* OFDM 6MBS,9MBS */ 4344 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4345 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4346 txpower, delta); 4347 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4348 TX_PWR_CFG_0_OFDM6_CH0, txpower); 4349 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4350 TX_PWR_CFG_0_OFDM6_CH1, txpower); 4351 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4352 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower); 4353 4354 /* OFDM 12MBS,18MBS */ 4355 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4356 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4357 txpower, delta); 4358 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4359 TX_PWR_CFG_0_OFDM12_CH0, txpower); 4360 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4361 TX_PWR_CFG_0_OFDM12_CH1, txpower); 4362 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4363 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower); 4364 4365 /* read the next four txpower values */ 4366 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4367 offset + 1); 4368 4369 /* OFDM 24MBS,36MBS */ 4370 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4371 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4372 txpower, delta); 4373 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4374 TX_PWR_CFG_1_OFDM24_CH0, txpower); 4375 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4376 TX_PWR_CFG_1_OFDM24_CH1, txpower); 4377 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4378 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower); 4379 4380 /* OFDM 48MBS */ 4381 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4382 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4383 txpower, delta); 4384 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4385 TX_PWR_CFG_1_OFDM48_CH0, txpower); 4386 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4387 TX_PWR_CFG_1_OFDM48_CH1, txpower); 4388 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4389 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower); 4390 4391 /* OFDM 54MBS */ 4392 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4393 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4394 txpower, delta); 4395 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4396 TX_PWR_CFG_7_OFDM54_CH0, txpower); 4397 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4398 TX_PWR_CFG_7_OFDM54_CH1, txpower); 4399 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4400 TX_PWR_CFG_7_OFDM54_CH2, txpower); 4401 4402 /* read the next four txpower values */ 4403 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4404 offset + 2); 4405 4406 /* MCS 0,1 */ 4407 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4408 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4409 txpower, delta); 4410 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4411 TX_PWR_CFG_1_MCS0_CH0, txpower); 4412 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4413 TX_PWR_CFG_1_MCS0_CH1, txpower); 4414 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4415 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower); 4416 4417 /* MCS 2,3 */ 4418 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4419 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4420 txpower, delta); 4421 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4422 TX_PWR_CFG_1_MCS2_CH0, txpower); 4423 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4424 TX_PWR_CFG_1_MCS2_CH1, txpower); 4425 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4426 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower); 4427 4428 /* MCS 4,5 */ 4429 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4430 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4431 txpower, delta); 4432 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4433 TX_PWR_CFG_2_MCS4_CH0, txpower); 4434 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4435 TX_PWR_CFG_2_MCS4_CH1, txpower); 4436 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4437 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower); 4438 4439 /* MCS 6 */ 4440 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4441 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4442 txpower, delta); 4443 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4444 TX_PWR_CFG_2_MCS6_CH0, txpower); 4445 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4446 TX_PWR_CFG_2_MCS6_CH1, txpower); 4447 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4448 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower); 4449 4450 /* read the next four txpower values */ 4451 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4452 offset + 3); 4453 4454 /* MCS 7 */ 4455 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4456 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4457 txpower, delta); 4458 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4459 TX_PWR_CFG_7_MCS7_CH0, txpower); 4460 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4461 TX_PWR_CFG_7_MCS7_CH1, txpower); 4462 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4463 TX_PWR_CFG_7_MCS7_CH2, txpower); 4464 4465 /* MCS 8,9 */ 4466 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4467 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4468 txpower, delta); 4469 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4470 TX_PWR_CFG_2_MCS8_CH0, txpower); 4471 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4472 TX_PWR_CFG_2_MCS8_CH1, txpower); 4473 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4474 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower); 4475 4476 /* MCS 10,11 */ 4477 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4478 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4479 txpower, delta); 4480 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4481 TX_PWR_CFG_2_MCS10_CH0, txpower); 4482 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4483 TX_PWR_CFG_2_MCS10_CH1, txpower); 4484 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4485 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower); 4486 4487 /* MCS 12,13 */ 4488 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4489 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4490 txpower, delta); 4491 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4492 TX_PWR_CFG_3_MCS12_CH0, txpower); 4493 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4494 TX_PWR_CFG_3_MCS12_CH1, txpower); 4495 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4496 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower); 4497 4498 /* read the next four txpower values */ 4499 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4500 offset + 4); 4501 4502 /* MCS 14 */ 4503 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4504 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4505 txpower, delta); 4506 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4507 TX_PWR_CFG_3_MCS14_CH0, txpower); 4508 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4509 TX_PWR_CFG_3_MCS14_CH1, txpower); 4510 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4511 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower); 4512 4513 /* MCS 15 */ 4514 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4515 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4516 txpower, delta); 4517 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4518 TX_PWR_CFG_8_MCS15_CH0, txpower); 4519 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4520 TX_PWR_CFG_8_MCS15_CH1, txpower); 4521 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4522 TX_PWR_CFG_8_MCS15_CH2, txpower); 4523 4524 /* MCS 16,17 */ 4525 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4526 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4527 txpower, delta); 4528 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4529 TX_PWR_CFG_5_MCS16_CH0, txpower); 4530 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4531 TX_PWR_CFG_5_MCS16_CH1, txpower); 4532 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4533 TX_PWR_CFG_5_MCS16_CH2, txpower); 4534 4535 /* MCS 18,19 */ 4536 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4537 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4538 txpower, delta); 4539 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4540 TX_PWR_CFG_5_MCS18_CH0, txpower); 4541 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4542 TX_PWR_CFG_5_MCS18_CH1, txpower); 4543 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4544 TX_PWR_CFG_5_MCS18_CH2, txpower); 4545 4546 /* read the next four txpower values */ 4547 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4548 offset + 5); 4549 4550 /* MCS 20,21 */ 4551 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4552 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4553 txpower, delta); 4554 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4555 TX_PWR_CFG_6_MCS20_CH0, txpower); 4556 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4557 TX_PWR_CFG_6_MCS20_CH1, txpower); 4558 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4559 TX_PWR_CFG_6_MCS20_CH2, txpower); 4560 4561 /* MCS 22 */ 4562 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4563 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4564 txpower, delta); 4565 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4566 TX_PWR_CFG_6_MCS22_CH0, txpower); 4567 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4568 TX_PWR_CFG_6_MCS22_CH1, txpower); 4569 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4570 TX_PWR_CFG_6_MCS22_CH2, txpower); 4571 4572 /* MCS 23 */ 4573 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4574 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4575 txpower, delta); 4576 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4577 TX_PWR_CFG_8_MCS23_CH0, txpower); 4578 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4579 TX_PWR_CFG_8_MCS23_CH1, txpower); 4580 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4581 TX_PWR_CFG_8_MCS23_CH2, txpower); 4582 4583 /* read the next four txpower values */ 4584 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4585 offset + 6); 4586 4587 /* STBC, MCS 0,1 */ 4588 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4589 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4590 txpower, delta); 4591 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4592 TX_PWR_CFG_3_STBC0_CH0, txpower); 4593 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4594 TX_PWR_CFG_3_STBC0_CH1, txpower); 4595 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4596 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower); 4597 4598 /* STBC, MCS 2,3 */ 4599 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4600 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4601 txpower, delta); 4602 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4603 TX_PWR_CFG_3_STBC2_CH0, txpower); 4604 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4605 TX_PWR_CFG_3_STBC2_CH1, txpower); 4606 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4607 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower); 4608 4609 /* STBC, MCS 4,5 */ 4610 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4611 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4612 txpower, delta); 4613 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); 4614 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); 4615 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, 4616 txpower); 4617 4618 /* STBC, MCS 6 */ 4619 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4620 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4621 txpower, delta); 4622 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); 4623 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); 4624 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, 4625 txpower); 4626 4627 /* read the next four txpower values */ 4628 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4629 offset + 7); 4630 4631 /* STBC, MCS 7 */ 4632 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4633 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4634 txpower, delta); 4635 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4636 TX_PWR_CFG_9_STBC7_CH0, txpower); 4637 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4638 TX_PWR_CFG_9_STBC7_CH1, txpower); 4639 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4640 TX_PWR_CFG_9_STBC7_CH2, txpower); 4641 4642 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]); 4643 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]); 4644 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]); 4645 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]); 4646 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]); 4647 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]); 4648 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]); 4649 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]); 4650 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]); 4651 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]); 4652 4653 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT, 4654 regs[TX_PWR_CFG_0_EXT_IDX]); 4655 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT, 4656 regs[TX_PWR_CFG_1_EXT_IDX]); 4657 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT, 4658 regs[TX_PWR_CFG_2_EXT_IDX]); 4659 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT, 4660 regs[TX_PWR_CFG_3_EXT_IDX]); 4661 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT, 4662 regs[TX_PWR_CFG_4_EXT_IDX]); 4663 4664 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++) 4665 rt2x00_dbg(rt2x00dev, 4666 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n", 4667 (band == NL80211_BAND_5GHZ) ? '5' : '2', 4668 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ? 4669 '4' : '2', 4670 (i > TX_PWR_CFG_9_IDX) ? 4671 (i - TX_PWR_CFG_9_IDX - 1) : i, 4672 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "", 4673 (unsigned long) regs[i]); 4674 } 4675 4676 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev, 4677 struct ieee80211_channel *chan, 4678 int power_level) 4679 { 4680 u32 reg, pwreg; 4681 u16 eeprom; 4682 u32 data, gdata; 4683 u8 t, i; 4684 enum nl80211_band band = chan->band; 4685 int delta; 4686 4687 /* Warn user if bw_comp is set in EEPROM */ 4688 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 4689 4690 if (delta) 4691 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n", 4692 delta); 4693 4694 /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit 4695 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor 4696 * driver does as well, though it looks kinda wrong. 4697 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe 4698 * the hardware has a problem handling 0x20, and as the code initially 4699 * used a fixed offset between HT20 and HT40 rates they had to work- 4700 * around that issue and most likely just forgot about it later on. 4701 * Maybe we should use rt2800_get_txpower_bw_comp() here as well, 4702 * however, the corresponding EEPROM value is not respected by the 4703 * vendor driver, so maybe this is rather being taken care of the 4704 * TXALC and the driver doesn't need to handle it...? 4705 * Though this is all very awkward, just do as they did, as that's what 4706 * board vendors expected when they populated the EEPROM... 4707 */ 4708 for (i = 0; i < 5; i++) { 4709 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4710 EEPROM_TXPOWER_BYRATE, 4711 i * 2); 4712 4713 data = eeprom; 4714 4715 t = eeprom & 0x3f; 4716 if (t == 32) 4717 t++; 4718 4719 gdata = t; 4720 4721 t = (eeprom & 0x3f00) >> 8; 4722 if (t == 32) 4723 t++; 4724 4725 gdata |= (t << 8); 4726 4727 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4728 EEPROM_TXPOWER_BYRATE, 4729 (i * 2) + 1); 4730 4731 t = eeprom & 0x3f; 4732 if (t == 32) 4733 t++; 4734 4735 gdata |= (t << 16); 4736 4737 t = (eeprom & 0x3f00) >> 8; 4738 if (t == 32) 4739 t++; 4740 4741 gdata |= (t << 24); 4742 data |= (eeprom << 16); 4743 4744 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) { 4745 /* HT20 */ 4746 if (data != 0xffffffff) 4747 rt2800_register_write(rt2x00dev, 4748 TX_PWR_CFG_0 + (i * 4), 4749 data); 4750 } else { 4751 /* HT40 */ 4752 if (gdata != 0xffffffff) 4753 rt2800_register_write(rt2x00dev, 4754 TX_PWR_CFG_0 + (i * 4), 4755 gdata); 4756 } 4757 } 4758 4759 /* Aparently Ralink ran out of space in the BYRATE calibration section 4760 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x 4761 * registers. As recent 2T chips use 8-bit instead of 4-bit values for 4762 * power-offsets more space would be needed. Ralink decided to keep the 4763 * EEPROM layout untouched and rather have some shared values covering 4764 * multiple bitrates. 4765 * Populate the registers not covered by the EEPROM in the same way the 4766 * vendor driver does. 4767 */ 4768 4769 /* For OFDM 54MBS use value from OFDM 48MBS */ 4770 pwreg = 0; 4771 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1); 4772 t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS); 4773 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t); 4774 4775 /* For MCS 7 use value from MCS 6 */ 4776 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2); 4777 t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7); 4778 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t); 4779 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg); 4780 4781 /* For MCS 15 use value from MCS 14 */ 4782 pwreg = 0; 4783 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3); 4784 t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14); 4785 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t); 4786 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg); 4787 4788 /* For STBC MCS 7 use value from STBC MCS 6 */ 4789 pwreg = 0; 4790 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4); 4791 t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6); 4792 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); 4793 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg); 4794 4795 rt2800_config_alc(rt2x00dev, chan, power_level); 4796 4797 /* TODO: temperature compensation code! */ 4798 } 4799 4800 /* 4801 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and 4802 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values, 4803 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power 4804 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm. 4805 * Reference per rate transmit power values are located in the EEPROM at 4806 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to 4807 * current conditions (i.e. band, bandwidth, temperature, user settings). 4808 */ 4809 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, 4810 struct ieee80211_channel *chan, 4811 int power_level) 4812 { 4813 u8 txpower, r1; 4814 u16 eeprom; 4815 u32 reg, offset; 4816 int i, is_rate_b, delta, power_ctrl; 4817 enum nl80211_band band = chan->band; 4818 4819 /* 4820 * Calculate HT40 compensation. For 40MHz we need to add or subtract 4821 * value read from EEPROM (different for 2GHz and for 5GHz). 4822 */ 4823 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 4824 4825 /* 4826 * Calculate temperature compensation. Depends on measurement of current 4827 * TSSI (Transmitter Signal Strength Indication) we know TX power (due 4828 * to temperature or maybe other factors) is smaller or bigger than 4829 * expected. We adjust it, based on TSSI reference and boundaries values 4830 * provided in EEPROM. 4831 */ 4832 switch (rt2x00dev->chip.rt) { 4833 case RT2860: 4834 case RT2872: 4835 case RT2883: 4836 case RT3070: 4837 case RT3071: 4838 case RT3090: 4839 case RT3572: 4840 delta += rt2800_get_gain_calibration_delta(rt2x00dev); 4841 break; 4842 default: 4843 /* TODO: temperature compensation code for other chips. */ 4844 break; 4845 } 4846 4847 /* 4848 * Decrease power according to user settings, on devices with unknown 4849 * maximum tx power. For other devices we take user power_level into 4850 * consideration on rt2800_compensate_txpower(). 4851 */ 4852 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level, 4853 chan->max_power); 4854 4855 /* 4856 * BBP_R1 controls TX power for all rates, it allow to set the following 4857 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively. 4858 * 4859 * TODO: we do not use +6 dBm option to do not increase power beyond 4860 * regulatory limit, however this could be utilized for devices with 4861 * CAPABILITY_POWER_LIMIT. 4862 */ 4863 if (delta <= -12) { 4864 power_ctrl = 2; 4865 delta += 12; 4866 } else if (delta <= -6) { 4867 power_ctrl = 1; 4868 delta += 6; 4869 } else { 4870 power_ctrl = 0; 4871 } 4872 r1 = rt2800_bbp_read(rt2x00dev, 1); 4873 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl); 4874 rt2800_bbp_write(rt2x00dev, 1, r1); 4875 4876 offset = TX_PWR_CFG_0; 4877 4878 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { 4879 /* just to be safe */ 4880 if (offset > TX_PWR_CFG_4) 4881 break; 4882 4883 reg = rt2800_register_read(rt2x00dev, offset); 4884 4885 /* read the next four txpower values */ 4886 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4887 EEPROM_TXPOWER_BYRATE, 4888 i); 4889 4890 is_rate_b = i ? 0 : 1; 4891 /* 4892 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, 4893 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, 4894 * TX_PWR_CFG_4: unknown 4895 */ 4896 txpower = rt2x00_get_field16(eeprom, 4897 EEPROM_TXPOWER_BYRATE_RATE0); 4898 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4899 power_level, txpower, delta); 4900 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); 4901 4902 /* 4903 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, 4904 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, 4905 * TX_PWR_CFG_4: unknown 4906 */ 4907 txpower = rt2x00_get_field16(eeprom, 4908 EEPROM_TXPOWER_BYRATE_RATE1); 4909 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4910 power_level, txpower, delta); 4911 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); 4912 4913 /* 4914 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS, 4915 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, 4916 * TX_PWR_CFG_4: unknown 4917 */ 4918 txpower = rt2x00_get_field16(eeprom, 4919 EEPROM_TXPOWER_BYRATE_RATE2); 4920 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4921 power_level, txpower, delta); 4922 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); 4923 4924 /* 4925 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, 4926 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, 4927 * TX_PWR_CFG_4: unknown 4928 */ 4929 txpower = rt2x00_get_field16(eeprom, 4930 EEPROM_TXPOWER_BYRATE_RATE3); 4931 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4932 power_level, txpower, delta); 4933 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); 4934 4935 /* read the next four txpower values */ 4936 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4937 EEPROM_TXPOWER_BYRATE, 4938 i + 1); 4939 4940 is_rate_b = 0; 4941 /* 4942 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, 4943 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, 4944 * TX_PWR_CFG_4: unknown 4945 */ 4946 txpower = rt2x00_get_field16(eeprom, 4947 EEPROM_TXPOWER_BYRATE_RATE0); 4948 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4949 power_level, txpower, delta); 4950 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); 4951 4952 /* 4953 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, 4954 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, 4955 * TX_PWR_CFG_4: unknown 4956 */ 4957 txpower = rt2x00_get_field16(eeprom, 4958 EEPROM_TXPOWER_BYRATE_RATE1); 4959 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4960 power_level, txpower, delta); 4961 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); 4962 4963 /* 4964 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, 4965 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, 4966 * TX_PWR_CFG_4: unknown 4967 */ 4968 txpower = rt2x00_get_field16(eeprom, 4969 EEPROM_TXPOWER_BYRATE_RATE2); 4970 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4971 power_level, txpower, delta); 4972 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); 4973 4974 /* 4975 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, 4976 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, 4977 * TX_PWR_CFG_4: unknown 4978 */ 4979 txpower = rt2x00_get_field16(eeprom, 4980 EEPROM_TXPOWER_BYRATE_RATE3); 4981 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4982 power_level, txpower, delta); 4983 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); 4984 4985 rt2800_register_write(rt2x00dev, offset, reg); 4986 4987 /* next TX_PWR_CFG register */ 4988 offset += 4; 4989 } 4990 } 4991 4992 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, 4993 struct ieee80211_channel *chan, 4994 int power_level) 4995 { 4996 if (rt2x00_rt(rt2x00dev, RT3593)) 4997 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level); 4998 else if (rt2x00_rt(rt2x00dev, RT6352)) 4999 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level); 5000 else 5001 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level); 5002 } 5003 5004 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) 5005 { 5006 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan, 5007 rt2x00dev->tx_power); 5008 } 5009 EXPORT_SYMBOL_GPL(rt2800_gain_calibration); 5010 5011 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) 5012 { 5013 u32 tx_pin; 5014 u8 rfcsr; 5015 unsigned long min_sleep = 0; 5016 5017 /* 5018 * A voltage-controlled oscillator(VCO) is an electronic oscillator 5019 * designed to be controlled in oscillation frequency by a voltage 5020 * input. Maybe the temperature will affect the frequency of 5021 * oscillation to be shifted. The VCO calibration will be called 5022 * periodically to adjust the frequency to be precision. 5023 */ 5024 5025 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5026 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE; 5027 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5028 5029 switch (rt2x00dev->chip.rf) { 5030 case RF2020: 5031 case RF3020: 5032 case RF3021: 5033 case RF3022: 5034 case RF3320: 5035 case RF3052: 5036 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 5037 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 5038 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 5039 break; 5040 case RF3053: 5041 case RF3070: 5042 case RF3290: 5043 case RF5350: 5044 case RF5360: 5045 case RF5362: 5046 case RF5370: 5047 case RF5372: 5048 case RF5390: 5049 case RF5392: 5050 case RF5592: 5051 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 5052 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 5053 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 5054 min_sleep = 1000; 5055 break; 5056 case RF7620: 5057 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 5058 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 5059 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4); 5060 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1); 5061 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr); 5062 min_sleep = 2000; 5063 break; 5064 default: 5065 WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration", 5066 rt2x00dev->chip.rf); 5067 return; 5068 } 5069 5070 if (min_sleep > 0) 5071 usleep_range(min_sleep, min_sleep * 2); 5072 5073 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5074 if (rt2x00dev->rf_channel <= 14) { 5075 switch (rt2x00dev->default_ant.tx_chain_num) { 5076 case 3: 5077 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); 5078 /* fall through */ 5079 case 2: 5080 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 5081 /* fall through */ 5082 case 1: 5083 default: 5084 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 5085 break; 5086 } 5087 } else { 5088 switch (rt2x00dev->default_ant.tx_chain_num) { 5089 case 3: 5090 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); 5091 /* fall through */ 5092 case 2: 5093 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 5094 /* fall through */ 5095 case 1: 5096 default: 5097 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); 5098 break; 5099 } 5100 } 5101 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5102 5103 if (rt2x00_rt(rt2x00dev, RT6352)) { 5104 if (rt2x00dev->default_ant.rx_chain_num == 1) { 5105 rt2800_bbp_write(rt2x00dev, 91, 0x07); 5106 rt2800_bbp_write(rt2x00dev, 95, 0x1A); 5107 rt2800_bbp_write(rt2x00dev, 195, 128); 5108 rt2800_bbp_write(rt2x00dev, 196, 0xA0); 5109 rt2800_bbp_write(rt2x00dev, 195, 170); 5110 rt2800_bbp_write(rt2x00dev, 196, 0x12); 5111 rt2800_bbp_write(rt2x00dev, 195, 171); 5112 rt2800_bbp_write(rt2x00dev, 196, 0x10); 5113 } else { 5114 rt2800_bbp_write(rt2x00dev, 91, 0x06); 5115 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 5116 rt2800_bbp_write(rt2x00dev, 195, 128); 5117 rt2800_bbp_write(rt2x00dev, 196, 0xE0); 5118 rt2800_bbp_write(rt2x00dev, 195, 170); 5119 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5120 rt2800_bbp_write(rt2x00dev, 195, 171); 5121 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5122 } 5123 5124 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 5125 rt2800_bbp_write(rt2x00dev, 75, 0x68); 5126 rt2800_bbp_write(rt2x00dev, 76, 0x4C); 5127 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 5128 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 5129 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 5130 } 5131 5132 /* On 11A, We should delay and wait RF/BBP to be stable 5133 * and the appropriate time should be 1000 micro seconds 5134 * 2005/06/05 - On 11G, we also need this delay time. 5135 * Otherwise it's difficult to pass the WHQL. 5136 */ 5137 usleep_range(1000, 1500); 5138 } 5139 } 5140 EXPORT_SYMBOL_GPL(rt2800_vco_calibration); 5141 5142 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, 5143 struct rt2x00lib_conf *libconf) 5144 { 5145 u32 reg; 5146 5147 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 5148 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 5149 libconf->conf->short_frame_max_tx_count); 5150 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 5151 libconf->conf->long_frame_max_tx_count); 5152 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5153 } 5154 5155 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, 5156 struct rt2x00lib_conf *libconf) 5157 { 5158 enum dev_state state = 5159 (libconf->conf->flags & IEEE80211_CONF_PS) ? 5160 STATE_SLEEP : STATE_AWAKE; 5161 u32 reg; 5162 5163 if (state == STATE_SLEEP) { 5164 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); 5165 5166 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5167 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); 5168 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 5169 libconf->conf->listen_interval - 1); 5170 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); 5171 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5172 5173 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5174 } else { 5175 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5176 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 5177 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 5178 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); 5179 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5180 5181 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5182 } 5183 } 5184 5185 void rt2800_config(struct rt2x00_dev *rt2x00dev, 5186 struct rt2x00lib_conf *libconf, 5187 const unsigned int flags) 5188 { 5189 /* Always recalculate LNA gain before changing configuration */ 5190 rt2800_config_lna_gain(rt2x00dev, libconf); 5191 5192 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { 5193 rt2800_config_channel(rt2x00dev, libconf->conf, 5194 &libconf->rf, &libconf->channel); 5195 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5196 libconf->conf->power_level); 5197 } 5198 if (flags & IEEE80211_CONF_CHANGE_POWER) 5199 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5200 libconf->conf->power_level); 5201 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 5202 rt2800_config_retry_limit(rt2x00dev, libconf); 5203 if (flags & IEEE80211_CONF_CHANGE_PS) 5204 rt2800_config_ps(rt2x00dev, libconf); 5205 } 5206 EXPORT_SYMBOL_GPL(rt2800_config); 5207 5208 /* 5209 * Link tuning 5210 */ 5211 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5212 { 5213 u32 reg; 5214 5215 /* 5216 * Update FCS error count from register. 5217 */ 5218 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 5219 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); 5220 } 5221 EXPORT_SYMBOL_GPL(rt2800_link_stats); 5222 5223 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 5224 { 5225 u8 vgc; 5226 5227 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 5228 if (rt2x00_rt(rt2x00dev, RT3070) || 5229 rt2x00_rt(rt2x00dev, RT3071) || 5230 rt2x00_rt(rt2x00dev, RT3090) || 5231 rt2x00_rt(rt2x00dev, RT3290) || 5232 rt2x00_rt(rt2x00dev, RT3390) || 5233 rt2x00_rt(rt2x00dev, RT3572) || 5234 rt2x00_rt(rt2x00dev, RT3593) || 5235 rt2x00_rt(rt2x00dev, RT5390) || 5236 rt2x00_rt(rt2x00dev, RT5392) || 5237 rt2x00_rt(rt2x00dev, RT5592) || 5238 rt2x00_rt(rt2x00dev, RT6352)) 5239 vgc = 0x1c + (2 * rt2x00dev->lna_gain); 5240 else 5241 vgc = 0x2e + rt2x00dev->lna_gain; 5242 } else { /* 5GHZ band */ 5243 if (rt2x00_rt(rt2x00dev, RT3593)) 5244 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3; 5245 else if (rt2x00_rt(rt2x00dev, RT5592)) 5246 vgc = 0x24 + (2 * rt2x00dev->lna_gain); 5247 else { 5248 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 5249 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3; 5250 else 5251 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3; 5252 } 5253 } 5254 5255 return vgc; 5256 } 5257 5258 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, 5259 struct link_qual *qual, u8 vgc_level) 5260 { 5261 if (qual->vgc_level != vgc_level) { 5262 if (rt2x00_rt(rt2x00dev, RT3572) || 5263 rt2x00_rt(rt2x00dev, RT3593)) { 5264 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, 5265 vgc_level); 5266 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5267 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a); 5268 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level); 5269 } else { 5270 rt2800_bbp_write(rt2x00dev, 66, vgc_level); 5271 } 5272 5273 qual->vgc_level = vgc_level; 5274 qual->vgc_level_reg = vgc_level; 5275 } 5276 } 5277 5278 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5279 { 5280 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); 5281 } 5282 EXPORT_SYMBOL_GPL(rt2800_reset_tuner); 5283 5284 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 5285 const u32 count) 5286 { 5287 u8 vgc; 5288 5289 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) 5290 return; 5291 5292 /* When RSSI is better than a certain threshold, increase VGC 5293 * with a chip specific value in order to improve the balance 5294 * between sensibility and noise isolation. 5295 */ 5296 5297 vgc = rt2800_get_default_vgc(rt2x00dev); 5298 5299 switch (rt2x00dev->chip.rt) { 5300 case RT3572: 5301 case RT3593: 5302 if (qual->rssi > -65) { 5303 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) 5304 vgc += 0x20; 5305 else 5306 vgc += 0x10; 5307 } 5308 break; 5309 5310 case RT5592: 5311 if (qual->rssi > -65) 5312 vgc += 0x20; 5313 break; 5314 5315 default: 5316 if (qual->rssi > -80) 5317 vgc += 0x10; 5318 break; 5319 } 5320 5321 rt2800_set_vgc(rt2x00dev, qual, vgc); 5322 } 5323 EXPORT_SYMBOL_GPL(rt2800_link_tuner); 5324 5325 /* 5326 * Initialization functions. 5327 */ 5328 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 5329 { 5330 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5331 u32 reg; 5332 u16 eeprom; 5333 unsigned int i; 5334 int ret; 5335 5336 rt2800_disable_wpdma(rt2x00dev); 5337 5338 ret = rt2800_drv_init_registers(rt2x00dev); 5339 if (ret) 5340 return ret; 5341 5342 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); 5343 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 5344 5345 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 5346 5347 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 5348 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); 5349 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); 5350 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); 5351 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); 5352 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 5353 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 5354 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 5355 5356 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); 5357 5358 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 5359 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); 5360 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 5361 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 5362 5363 if (rt2x00_rt(rt2x00dev, RT3290)) { 5364 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 5365 if (rt2x00_get_field32(reg, WLAN_EN) == 1) { 5366 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); 5367 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 5368 } 5369 5370 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 5371 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { 5372 rt2x00_set_field32(®, LDO0_EN, 1); 5373 rt2x00_set_field32(®, LDO_BGSEL, 3); 5374 rt2800_register_write(rt2x00dev, CMB_CTRL, reg); 5375 } 5376 5377 reg = rt2800_register_read(rt2x00dev, OSC_CTRL); 5378 rt2x00_set_field32(®, OSC_ROSC_EN, 1); 5379 rt2x00_set_field32(®, OSC_CAL_REQ, 1); 5380 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); 5381 rt2800_register_write(rt2x00dev, OSC_CTRL, reg); 5382 5383 reg = rt2800_register_read(rt2x00dev, COEX_CFG0); 5384 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); 5385 rt2800_register_write(rt2x00dev, COEX_CFG0, reg); 5386 5387 reg = rt2800_register_read(rt2x00dev, COEX_CFG2); 5388 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); 5389 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); 5390 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); 5391 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); 5392 rt2800_register_write(rt2x00dev, COEX_CFG2, reg); 5393 5394 reg = rt2800_register_read(rt2x00dev, PLL_CTRL); 5395 rt2x00_set_field32(®, PLL_CONTROL, 1); 5396 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); 5397 } 5398 5399 if (rt2x00_rt(rt2x00dev, RT3071) || 5400 rt2x00_rt(rt2x00dev, RT3090) || 5401 rt2x00_rt(rt2x00dev, RT3290) || 5402 rt2x00_rt(rt2x00dev, RT3390)) { 5403 5404 if (rt2x00_rt(rt2x00dev, RT3290)) 5405 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5406 0x00000404); 5407 else 5408 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5409 0x00000400); 5410 5411 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5412 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 5413 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 5414 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 5415 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5416 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 5417 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5418 0x0000002c); 5419 else 5420 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5421 0x0000000f); 5422 } else { 5423 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5424 } 5425 } else if (rt2x00_rt(rt2x00dev, RT3070)) { 5426 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5427 5428 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 5429 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5430 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); 5431 } else { 5432 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5433 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5434 } 5435 } else if (rt2800_is_305x_soc(rt2x00dev)) { 5436 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5437 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5438 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); 5439 } else if (rt2x00_rt(rt2x00dev, RT3352)) { 5440 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5441 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5442 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5443 } else if (rt2x00_rt(rt2x00dev, RT3572)) { 5444 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5445 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5446 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 5447 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5448 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5449 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) { 5450 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5451 if (rt2x00_get_field16(eeprom, 5452 EEPROM_NIC_CONF1_DAC_TEST)) 5453 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5454 0x0000001f); 5455 else 5456 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5457 0x0000000f); 5458 } else { 5459 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5460 0x00000000); 5461 } 5462 } else if (rt2x00_rt(rt2x00dev, RT5390) || 5463 rt2x00_rt(rt2x00dev, RT5392) || 5464 rt2x00_rt(rt2x00dev, RT6352)) { 5465 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5466 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5467 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5468 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5469 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5470 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5471 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5472 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 5473 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5474 } else if (rt2x00_rt(rt2x00dev, RT6352)) { 5475 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401); 5476 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000); 5477 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5478 rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002); 5479 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F); 5480 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x06060606); 5481 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0); 5482 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0); 5483 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C); 5484 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C); 5485 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 5486 0x3630363A); 5487 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT, 5488 0x3630363A); 5489 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 5490 rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); 5491 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 5492 } else { 5493 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 5494 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5495 } 5496 5497 reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG); 5498 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); 5499 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); 5500 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); 5501 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); 5502 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); 5503 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); 5504 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); 5505 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); 5506 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); 5507 5508 reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG); 5509 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 5510 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); 5511 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 5512 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 5513 5514 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 5515 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 5516 if (rt2x00_is_usb(rt2x00dev)) { 5517 drv_data->max_psdu = 3; 5518 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || 5519 rt2x00_rt(rt2x00dev, RT2883) || 5520 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) { 5521 drv_data->max_psdu = 2; 5522 } else { 5523 drv_data->max_psdu = 1; 5524 } 5525 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu); 5526 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); 5527 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); 5528 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 5529 5530 reg = rt2800_register_read(rt2x00dev, LED_CFG); 5531 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); 5532 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); 5533 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); 5534 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); 5535 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); 5536 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); 5537 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); 5538 rt2800_register_write(rt2x00dev, LED_CFG, reg); 5539 5540 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 5541 5542 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 5543 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); 5544 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); 5545 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); 5546 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); 5547 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); 5548 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); 5549 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5550 5551 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 5552 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); 5553 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); 5554 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); 5555 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); 5556 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); 5557 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 5558 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 5559 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 5560 5561 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 5562 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); 5563 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); 5564 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); 5565 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 5566 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5567 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5568 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5569 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5570 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5571 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); 5572 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 5573 5574 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 5575 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); 5576 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); 5577 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); 5578 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 5579 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5580 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5581 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5582 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5583 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5584 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); 5585 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 5586 5587 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 5588 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 5589 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); 5590 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); 5591 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5592 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5593 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5594 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5595 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5596 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5597 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); 5598 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 5599 5600 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 5601 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 5602 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); 5603 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); 5604 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5605 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5606 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5607 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 5608 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5609 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 5610 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); 5611 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 5612 5613 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 5614 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 5615 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); 5616 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); 5617 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5618 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5619 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5620 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5621 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5622 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5623 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); 5624 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 5625 5626 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 5627 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 5628 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); 5629 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); 5630 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5631 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5632 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5633 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 5634 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5635 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 5636 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); 5637 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 5638 5639 if (rt2x00_is_usb(rt2x00dev)) { 5640 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); 5641 5642 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 5643 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 5644 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 5645 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 5646 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 5647 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); 5648 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); 5649 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); 5650 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); 5651 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); 5652 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 5653 } 5654 5655 /* 5656 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 5657 * although it is reserved. 5658 */ 5659 reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG); 5660 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); 5661 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); 5662 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); 5663 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); 5664 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); 5665 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); 5666 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); 5667 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); 5668 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); 5669 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); 5670 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); 5671 5672 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; 5673 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); 5674 5675 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 5676 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); 5677 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, 5678 IEEE80211_MAX_RTS_THRESHOLD); 5679 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1); 5680 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 5681 5682 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 5683 5684 /* 5685 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS 5686 * time should be set to 16. However, the original Ralink driver uses 5687 * 16 for both and indeed using a value of 10 for CCK SIFS results in 5688 * connection problems with 11g + CTS protection. Hence, use the same 5689 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. 5690 */ 5691 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 5692 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); 5693 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); 5694 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); 5695 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); 5696 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); 5697 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 5698 5699 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 5700 5701 /* 5702 * ASIC will keep garbage value after boot, clear encryption keys. 5703 */ 5704 for (i = 0; i < 4; i++) 5705 rt2800_register_write(rt2x00dev, 5706 SHARED_KEY_MODE_ENTRY(i), 0); 5707 5708 for (i = 0; i < 256; i++) { 5709 rt2800_config_wcid(rt2x00dev, NULL, i); 5710 rt2800_delete_wcid_attr(rt2x00dev, i); 5711 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 5712 } 5713 5714 /* 5715 * Clear all beacons 5716 */ 5717 for (i = 0; i < 8; i++) 5718 rt2800_clear_beacon_register(rt2x00dev, i); 5719 5720 if (rt2x00_is_usb(rt2x00dev)) { 5721 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 5722 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); 5723 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 5724 } else if (rt2x00_is_pcie(rt2x00dev)) { 5725 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 5726 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); 5727 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 5728 } 5729 5730 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0); 5731 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); 5732 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); 5733 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); 5734 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); 5735 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); 5736 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); 5737 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); 5738 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); 5739 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); 5740 5741 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1); 5742 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); 5743 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); 5744 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); 5745 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); 5746 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); 5747 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); 5748 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); 5749 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); 5750 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); 5751 5752 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0); 5753 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); 5754 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); 5755 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); 5756 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); 5757 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); 5758 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); 5759 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); 5760 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); 5761 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); 5762 5763 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1); 5764 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); 5765 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); 5766 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); 5767 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); 5768 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); 5769 5770 /* 5771 * Do not force the BA window size, we use the TXWI to set it 5772 */ 5773 reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE); 5774 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); 5775 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); 5776 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); 5777 5778 /* 5779 * We must clear the error counters. 5780 * These registers are cleared on read, 5781 * so we may pass a useless variable to store the value. 5782 */ 5783 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 5784 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1); 5785 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2); 5786 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0); 5787 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1); 5788 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2); 5789 5790 /* 5791 * Setup leadtime for pre tbtt interrupt to 6ms 5792 */ 5793 reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG); 5794 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); 5795 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); 5796 5797 /* 5798 * Set up channel statistics timer 5799 */ 5800 reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG); 5801 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); 5802 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); 5803 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); 5804 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); 5805 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); 5806 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); 5807 5808 return 0; 5809 } 5810 5811 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) 5812 { 5813 unsigned int i; 5814 u32 reg; 5815 5816 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 5817 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 5818 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) 5819 return 0; 5820 5821 udelay(REGISTER_BUSY_DELAY); 5822 } 5823 5824 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n"); 5825 return -EACCES; 5826 } 5827 5828 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 5829 { 5830 unsigned int i; 5831 u8 value; 5832 5833 /* 5834 * BBP was enabled after firmware was loaded, 5835 * but we need to reactivate it now. 5836 */ 5837 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 5838 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 5839 msleep(1); 5840 5841 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 5842 value = rt2800_bbp_read(rt2x00dev, 0); 5843 if ((value != 0xff) && (value != 0x00)) 5844 return 0; 5845 udelay(REGISTER_BUSY_DELAY); 5846 } 5847 5848 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 5849 return -EACCES; 5850 } 5851 5852 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev) 5853 { 5854 u8 value; 5855 5856 value = rt2800_bbp_read(rt2x00dev, 4); 5857 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); 5858 rt2800_bbp_write(rt2x00dev, 4, value); 5859 } 5860 5861 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev) 5862 { 5863 rt2800_bbp_write(rt2x00dev, 142, 1); 5864 rt2800_bbp_write(rt2x00dev, 143, 57); 5865 } 5866 5867 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev) 5868 { 5869 static const u8 glrt_table[] = { 5870 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */ 5871 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */ 5872 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */ 5873 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */ 5874 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */ 5875 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */ 5876 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */ 5877 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */ 5878 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */ 5879 }; 5880 int i; 5881 5882 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) { 5883 rt2800_bbp_write(rt2x00dev, 195, 128 + i); 5884 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]); 5885 } 5886 }; 5887 5888 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev) 5889 { 5890 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 5891 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5892 rt2800_bbp_write(rt2x00dev, 68, 0x0B); 5893 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5894 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5895 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5896 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5897 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5898 rt2800_bbp_write(rt2x00dev, 83, 0x6A); 5899 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5900 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5901 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5902 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5903 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5904 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5905 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5906 } 5907 5908 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev) 5909 { 5910 u16 eeprom; 5911 u8 value; 5912 5913 value = rt2800_bbp_read(rt2x00dev, 138); 5914 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 5915 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 5916 value |= 0x20; 5917 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 5918 value &= ~0x02; 5919 rt2800_bbp_write(rt2x00dev, 138, value); 5920 } 5921 5922 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev) 5923 { 5924 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5925 5926 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5927 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5928 5929 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5930 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5931 5932 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5933 5934 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 5935 rt2800_bbp_write(rt2x00dev, 80, 0x08); 5936 5937 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5938 5939 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5940 5941 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5942 5943 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5944 5945 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5946 5947 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5948 5949 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5950 5951 rt2800_bbp_write(rt2x00dev, 105, 0x01); 5952 5953 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5954 } 5955 5956 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev) 5957 { 5958 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5959 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5960 5961 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 5962 rt2800_bbp_write(rt2x00dev, 69, 0x16); 5963 rt2800_bbp_write(rt2x00dev, 73, 0x12); 5964 } else { 5965 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5966 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5967 } 5968 5969 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5970 5971 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5972 5973 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5974 5975 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5976 5977 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 5978 rt2800_bbp_write(rt2x00dev, 84, 0x19); 5979 else 5980 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5981 5982 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5983 5984 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5985 5986 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5987 5988 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5989 5990 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5991 5992 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5993 } 5994 5995 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev) 5996 { 5997 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5998 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5999 6000 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6001 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6002 6003 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6004 6005 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6006 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6007 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6008 6009 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6010 6011 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6012 6013 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6014 6015 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6016 6017 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6018 6019 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6020 6021 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 6022 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 6023 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E)) 6024 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6025 else 6026 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6027 6028 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6029 6030 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6031 6032 if (rt2x00_rt(rt2x00dev, RT3071) || 6033 rt2x00_rt(rt2x00dev, RT3090)) 6034 rt2800_disable_unused_dac_adc(rt2x00dev); 6035 } 6036 6037 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev) 6038 { 6039 u8 value; 6040 6041 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6042 6043 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6044 6045 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6046 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6047 6048 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6049 6050 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6051 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6052 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6053 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6054 6055 rt2800_bbp_write(rt2x00dev, 77, 0x58); 6056 6057 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6058 6059 rt2800_bbp_write(rt2x00dev, 74, 0x0b); 6060 rt2800_bbp_write(rt2x00dev, 79, 0x18); 6061 rt2800_bbp_write(rt2x00dev, 80, 0x09); 6062 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6063 6064 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6065 6066 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6067 6068 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6069 6070 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6071 6072 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6073 6074 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6075 6076 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6077 6078 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6079 6080 rt2800_bbp_write(rt2x00dev, 105, 0x1c); 6081 6082 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6083 6084 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6085 6086 rt2800_bbp_write(rt2x00dev, 67, 0x24); 6087 rt2800_bbp_write(rt2x00dev, 143, 0x04); 6088 rt2800_bbp_write(rt2x00dev, 142, 0x99); 6089 rt2800_bbp_write(rt2x00dev, 150, 0x30); 6090 rt2800_bbp_write(rt2x00dev, 151, 0x2e); 6091 rt2800_bbp_write(rt2x00dev, 152, 0x20); 6092 rt2800_bbp_write(rt2x00dev, 153, 0x34); 6093 rt2800_bbp_write(rt2x00dev, 154, 0x40); 6094 rt2800_bbp_write(rt2x00dev, 155, 0x3b); 6095 rt2800_bbp_write(rt2x00dev, 253, 0x04); 6096 6097 value = rt2800_bbp_read(rt2x00dev, 47); 6098 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1); 6099 rt2800_bbp_write(rt2x00dev, 47, value); 6100 6101 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */ 6102 value = rt2800_bbp_read(rt2x00dev, 3); 6103 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1); 6104 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1); 6105 rt2800_bbp_write(rt2x00dev, 3, value); 6106 } 6107 6108 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) 6109 { 6110 rt2800_bbp_write(rt2x00dev, 3, 0x00); 6111 rt2800_bbp_write(rt2x00dev, 4, 0x50); 6112 6113 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6114 6115 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6116 6117 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6118 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6119 6120 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6121 6122 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6123 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6124 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6125 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6126 6127 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6128 6129 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6130 6131 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 6132 rt2800_bbp_write(rt2x00dev, 80, 0x08); 6133 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6134 6135 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6136 6137 if (rt2x00_rt(rt2x00dev, RT5350)) { 6138 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6139 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6140 } else { 6141 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6142 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6143 } 6144 6145 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6146 6147 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6148 6149 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6150 6151 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6152 6153 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6154 6155 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6156 6157 if (rt2x00_rt(rt2x00dev, RT5350)) { 6158 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6159 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6160 } else { 6161 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6162 rt2800_bbp_write(rt2x00dev, 106, 0x05); 6163 } 6164 6165 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6166 6167 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6168 6169 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 6170 /* Set ITxBF timeout to 0x9c40=1000msec */ 6171 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6172 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6173 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6174 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6175 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6176 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6177 /* Reprogram the inband interface to put right values in RXWI */ 6178 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6179 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6180 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6181 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6182 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6183 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6184 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6185 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6186 6187 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6188 6189 if (rt2x00_rt(rt2x00dev, RT5350)) { 6190 /* Antenna Software OFDM */ 6191 rt2800_bbp_write(rt2x00dev, 150, 0x40); 6192 /* Antenna Software CCK */ 6193 rt2800_bbp_write(rt2x00dev, 151, 0x30); 6194 rt2800_bbp_write(rt2x00dev, 152, 0xa3); 6195 /* Clear previously selected antenna */ 6196 rt2800_bbp_write(rt2x00dev, 154, 0); 6197 } 6198 } 6199 6200 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev) 6201 { 6202 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6203 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6204 6205 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6206 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6207 6208 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6209 6210 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6211 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6212 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6213 6214 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6215 6216 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6217 6218 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6219 6220 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6221 6222 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6223 6224 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6225 6226 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E)) 6227 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6228 else 6229 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6230 6231 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6232 6233 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6234 6235 rt2800_disable_unused_dac_adc(rt2x00dev); 6236 } 6237 6238 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev) 6239 { 6240 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6241 6242 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6243 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6244 6245 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6246 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6247 6248 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6249 6250 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6251 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6252 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6253 6254 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6255 6256 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6257 6258 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6259 6260 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6261 6262 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6263 6264 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6265 6266 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6267 6268 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6269 6270 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6271 6272 rt2800_disable_unused_dac_adc(rt2x00dev); 6273 } 6274 6275 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev) 6276 { 6277 rt2800_init_bbp_early(rt2x00dev); 6278 6279 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6280 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6281 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6282 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6283 6284 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6285 6286 /* Enable DC filter */ 6287 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E)) 6288 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6289 } 6290 6291 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) 6292 { 6293 int ant, div_mode; 6294 u16 eeprom; 6295 u8 value; 6296 6297 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6298 6299 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6300 6301 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6302 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6303 6304 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6305 6306 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6307 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6308 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6309 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6310 6311 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6312 6313 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6314 6315 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6316 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6317 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6318 6319 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6320 6321 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6322 6323 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6324 6325 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6326 6327 if (rt2x00_rt(rt2x00dev, RT5392)) 6328 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6329 6330 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6331 6332 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6333 6334 if (rt2x00_rt(rt2x00dev, RT5392)) { 6335 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6336 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6337 } 6338 6339 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6340 6341 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6342 6343 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6344 6345 if (rt2x00_rt(rt2x00dev, RT5390)) 6346 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6347 else if (rt2x00_rt(rt2x00dev, RT5392)) 6348 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6349 else 6350 WARN_ON(1); 6351 6352 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6353 6354 if (rt2x00_rt(rt2x00dev, RT5392)) { 6355 rt2800_bbp_write(rt2x00dev, 134, 0xd0); 6356 rt2800_bbp_write(rt2x00dev, 135, 0xf6); 6357 } 6358 6359 rt2800_disable_unused_dac_adc(rt2x00dev); 6360 6361 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6362 div_mode = rt2x00_get_field16(eeprom, 6363 EEPROM_NIC_CONF1_ANT_DIVERSITY); 6364 ant = (div_mode == 3) ? 1 : 0; 6365 6366 /* check if this is a Bluetooth combo card */ 6367 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 6368 u32 reg; 6369 6370 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 6371 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 6372 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); 6373 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); 6374 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); 6375 if (ant == 0) 6376 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); 6377 else if (ant == 1) 6378 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); 6379 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 6380 } 6381 6382 /* These chips have hardware RX antenna diversity */ 6383 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 6384 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 6385 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */ 6386 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */ 6387 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */ 6388 } 6389 6390 value = rt2800_bbp_read(rt2x00dev, 152); 6391 if (ant == 0) 6392 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6393 else 6394 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6395 rt2800_bbp_write(rt2x00dev, 152, value); 6396 6397 rt2800_init_freq_calibration(rt2x00dev); 6398 } 6399 6400 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) 6401 { 6402 int ant, div_mode; 6403 u16 eeprom; 6404 u8 value; 6405 6406 rt2800_init_bbp_early(rt2x00dev); 6407 6408 value = rt2800_bbp_read(rt2x00dev, 105); 6409 rt2x00_set_field8(&value, BBP105_MLD, 6410 rt2x00dev->default_ant.rx_chain_num == 2); 6411 rt2800_bbp_write(rt2x00dev, 105, value); 6412 6413 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6414 6415 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6416 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6417 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6418 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6419 rt2800_bbp_write(rt2x00dev, 69, 0x1A); 6420 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6421 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6422 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6423 rt2800_bbp_write(rt2x00dev, 75, 0x4F); 6424 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6425 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6426 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 6427 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6428 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6429 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6430 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6431 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6432 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6433 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 6434 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6435 /* FIXME BBP105 owerwrite */ 6436 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 6437 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6438 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6439 rt2800_bbp_write(rt2x00dev, 134, 0xD0); 6440 rt2800_bbp_write(rt2x00dev, 135, 0xF6); 6441 rt2800_bbp_write(rt2x00dev, 137, 0x0F); 6442 6443 /* Initialize GLRT (Generalized Likehood Radio Test) */ 6444 rt2800_init_bbp_5592_glrt(rt2x00dev); 6445 6446 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6447 6448 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6449 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); 6450 ant = (div_mode == 3) ? 1 : 0; 6451 value = rt2800_bbp_read(rt2x00dev, 152); 6452 if (ant == 0) { 6453 /* Main antenna */ 6454 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6455 } else { 6456 /* Auxiliary antenna */ 6457 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6458 } 6459 rt2800_bbp_write(rt2x00dev, 152, value); 6460 6461 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) { 6462 value = rt2800_bbp_read(rt2x00dev, 254); 6463 rt2x00_set_field8(&value, BBP254_BIT7, 1); 6464 rt2800_bbp_write(rt2x00dev, 254, value); 6465 } 6466 6467 rt2800_init_freq_calibration(rt2x00dev); 6468 6469 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6470 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 6471 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6472 } 6473 6474 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev, 6475 const u8 reg, const u8 value) 6476 { 6477 rt2800_bbp_write(rt2x00dev, 195, reg); 6478 rt2800_bbp_write(rt2x00dev, 196, value); 6479 } 6480 6481 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev, 6482 const u8 reg, const u8 value) 6483 { 6484 rt2800_bbp_write(rt2x00dev, 158, reg); 6485 rt2800_bbp_write(rt2x00dev, 159, value); 6486 } 6487 6488 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg) 6489 { 6490 rt2800_bbp_write(rt2x00dev, 158, reg); 6491 return rt2800_bbp_read(rt2x00dev, 159); 6492 } 6493 6494 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev) 6495 { 6496 u8 bbp; 6497 6498 /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */ 6499 bbp = rt2800_bbp_read(rt2x00dev, 105); 6500 rt2x00_set_field8(&bbp, BBP105_MLD, 6501 rt2x00dev->default_ant.rx_chain_num == 2); 6502 rt2800_bbp_write(rt2x00dev, 105, bbp); 6503 6504 /* Avoid data loss and CRC errors */ 6505 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6506 6507 /* Fix I/Q swap issue */ 6508 bbp = rt2800_bbp_read(rt2x00dev, 1); 6509 bbp |= 0x04; 6510 rt2800_bbp_write(rt2x00dev, 1, bbp); 6511 6512 /* BBP for G band */ 6513 rt2800_bbp_write(rt2x00dev, 3, 0x08); 6514 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */ 6515 rt2800_bbp_write(rt2x00dev, 6, 0x08); 6516 rt2800_bbp_write(rt2x00dev, 14, 0x09); 6517 rt2800_bbp_write(rt2x00dev, 15, 0xFF); 6518 rt2800_bbp_write(rt2x00dev, 16, 0x01); 6519 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6520 rt2800_bbp_write(rt2x00dev, 21, 0x00); 6521 rt2800_bbp_write(rt2x00dev, 22, 0x00); 6522 rt2800_bbp_write(rt2x00dev, 27, 0x00); 6523 rt2800_bbp_write(rt2x00dev, 28, 0x00); 6524 rt2800_bbp_write(rt2x00dev, 30, 0x00); 6525 rt2800_bbp_write(rt2x00dev, 31, 0x48); 6526 rt2800_bbp_write(rt2x00dev, 47, 0x40); 6527 rt2800_bbp_write(rt2x00dev, 62, 0x00); 6528 rt2800_bbp_write(rt2x00dev, 63, 0x00); 6529 rt2800_bbp_write(rt2x00dev, 64, 0x00); 6530 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6531 rt2800_bbp_write(rt2x00dev, 66, 0x1C); 6532 rt2800_bbp_write(rt2x00dev, 67, 0x20); 6533 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6534 rt2800_bbp_write(rt2x00dev, 69, 0x10); 6535 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6536 rt2800_bbp_write(rt2x00dev, 73, 0x18); 6537 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6538 rt2800_bbp_write(rt2x00dev, 75, 0x60); 6539 rt2800_bbp_write(rt2x00dev, 76, 0x44); 6540 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6541 rt2800_bbp_write(rt2x00dev, 78, 0x1E); 6542 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 6543 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 6544 rt2800_bbp_write(rt2x00dev, 81, 0x3A); 6545 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 6546 rt2800_bbp_write(rt2x00dev, 83, 0x9A); 6547 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 6548 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6549 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6550 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6551 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6552 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 6553 rt2800_bbp_write(rt2x00dev, 96, 0x00); 6554 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 6555 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6556 /* FIXME BBP105 owerwrite */ 6557 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 6558 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6559 rt2800_bbp_write(rt2x00dev, 109, 0x00); 6560 rt2800_bbp_write(rt2x00dev, 134, 0x10); 6561 rt2800_bbp_write(rt2x00dev, 135, 0xA6); 6562 rt2800_bbp_write(rt2x00dev, 137, 0x04); 6563 rt2800_bbp_write(rt2x00dev, 142, 0x30); 6564 rt2800_bbp_write(rt2x00dev, 143, 0xF7); 6565 rt2800_bbp_write(rt2x00dev, 160, 0xEC); 6566 rt2800_bbp_write(rt2x00dev, 161, 0xC4); 6567 rt2800_bbp_write(rt2x00dev, 162, 0x77); 6568 rt2800_bbp_write(rt2x00dev, 163, 0xF9); 6569 rt2800_bbp_write(rt2x00dev, 164, 0x00); 6570 rt2800_bbp_write(rt2x00dev, 165, 0x00); 6571 rt2800_bbp_write(rt2x00dev, 186, 0x00); 6572 rt2800_bbp_write(rt2x00dev, 187, 0x00); 6573 rt2800_bbp_write(rt2x00dev, 188, 0x00); 6574 rt2800_bbp_write(rt2x00dev, 186, 0x00); 6575 rt2800_bbp_write(rt2x00dev, 187, 0x01); 6576 rt2800_bbp_write(rt2x00dev, 188, 0x00); 6577 rt2800_bbp_write(rt2x00dev, 189, 0x00); 6578 6579 rt2800_bbp_write(rt2x00dev, 91, 0x06); 6580 rt2800_bbp_write(rt2x00dev, 92, 0x04); 6581 rt2800_bbp_write(rt2x00dev, 93, 0x54); 6582 rt2800_bbp_write(rt2x00dev, 99, 0x50); 6583 rt2800_bbp_write(rt2x00dev, 148, 0x84); 6584 rt2800_bbp_write(rt2x00dev, 167, 0x80); 6585 rt2800_bbp_write(rt2x00dev, 178, 0xFF); 6586 rt2800_bbp_write(rt2x00dev, 106, 0x13); 6587 6588 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */ 6589 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00); 6590 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14); 6591 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20); 6592 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A); 6593 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16); 6594 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06); 6595 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02); 6596 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07); 6597 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05); 6598 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09); 6599 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20); 6600 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08); 6601 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A); 6602 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00); 6603 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00); 6604 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0); 6605 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F); 6606 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F); 6607 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32); 6608 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08); 6609 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28); 6610 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19); 6611 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A); 6612 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16); 6613 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10); 6614 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10); 6615 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A); 6616 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36); 6617 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C); 6618 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26); 6619 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24); 6620 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42); 6621 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40); 6622 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30); 6623 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29); 6624 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C); 6625 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46); 6626 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D); 6627 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40); 6628 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E); 6629 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38); 6630 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D); 6631 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F); 6632 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C); 6633 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34); 6634 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C); 6635 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F); 6636 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C); 6637 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35); 6638 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E); 6639 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F); 6640 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49); 6641 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41); 6642 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36); 6643 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39); 6644 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30); 6645 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30); 6646 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E); 6647 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D); 6648 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28); 6649 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21); 6650 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C); 6651 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16); 6652 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50); 6653 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A); 6654 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43); 6655 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50); 6656 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10); 6657 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10); 6658 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10); 6659 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10); 6660 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D); 6661 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14); 6662 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32); 6663 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C); 6664 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36); 6665 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C); 6666 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43); 6667 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C); 6668 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E); 6669 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36); 6670 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30); 6671 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E); 6672 6673 /* BBP for G band DCOC function */ 6674 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C); 6675 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00); 6676 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10); 6677 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10); 6678 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10); 6679 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10); 6680 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08); 6681 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40); 6682 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04); 6683 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04); 6684 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08); 6685 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08); 6686 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03); 6687 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03); 6688 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03); 6689 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02); 6690 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40); 6691 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40); 6692 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64); 6693 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64); 6694 6695 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6696 } 6697 6698 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) 6699 { 6700 unsigned int i; 6701 u16 eeprom; 6702 u8 reg_id; 6703 u8 value; 6704 6705 if (rt2800_is_305x_soc(rt2x00dev)) 6706 rt2800_init_bbp_305x_soc(rt2x00dev); 6707 6708 switch (rt2x00dev->chip.rt) { 6709 case RT2860: 6710 case RT2872: 6711 case RT2883: 6712 rt2800_init_bbp_28xx(rt2x00dev); 6713 break; 6714 case RT3070: 6715 case RT3071: 6716 case RT3090: 6717 rt2800_init_bbp_30xx(rt2x00dev); 6718 break; 6719 case RT3290: 6720 rt2800_init_bbp_3290(rt2x00dev); 6721 break; 6722 case RT3352: 6723 case RT5350: 6724 rt2800_init_bbp_3352(rt2x00dev); 6725 break; 6726 case RT3390: 6727 rt2800_init_bbp_3390(rt2x00dev); 6728 break; 6729 case RT3572: 6730 rt2800_init_bbp_3572(rt2x00dev); 6731 break; 6732 case RT3593: 6733 rt2800_init_bbp_3593(rt2x00dev); 6734 return; 6735 case RT5390: 6736 case RT5392: 6737 rt2800_init_bbp_53xx(rt2x00dev); 6738 break; 6739 case RT5592: 6740 rt2800_init_bbp_5592(rt2x00dev); 6741 return; 6742 case RT6352: 6743 rt2800_init_bbp_6352(rt2x00dev); 6744 break; 6745 } 6746 6747 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 6748 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 6749 EEPROM_BBP_START, i); 6750 6751 if (eeprom != 0xffff && eeprom != 0x0000) { 6752 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 6753 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 6754 rt2800_bbp_write(rt2x00dev, reg_id, value); 6755 } 6756 } 6757 } 6758 6759 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev) 6760 { 6761 u32 reg; 6762 6763 reg = rt2800_register_read(rt2x00dev, OPT_14_CSR); 6764 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); 6765 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 6766 } 6767 6768 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, 6769 u8 filter_target) 6770 { 6771 unsigned int i; 6772 u8 bbp; 6773 u8 rfcsr; 6774 u8 passband; 6775 u8 stopband; 6776 u8 overtuned = 0; 6777 u8 rfcsr24 = (bw40) ? 0x27 : 0x07; 6778 6779 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 6780 6781 bbp = rt2800_bbp_read(rt2x00dev, 4); 6782 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); 6783 rt2800_bbp_write(rt2x00dev, 4, bbp); 6784 6785 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 6786 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); 6787 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 6788 6789 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 6790 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); 6791 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 6792 6793 /* 6794 * Set power & frequency of passband test tone 6795 */ 6796 rt2800_bbp_write(rt2x00dev, 24, 0); 6797 6798 for (i = 0; i < 100; i++) { 6799 rt2800_bbp_write(rt2x00dev, 25, 0x90); 6800 msleep(1); 6801 6802 passband = rt2800_bbp_read(rt2x00dev, 55); 6803 if (passband) 6804 break; 6805 } 6806 6807 /* 6808 * Set power & frequency of stopband test tone 6809 */ 6810 rt2800_bbp_write(rt2x00dev, 24, 0x06); 6811 6812 for (i = 0; i < 100; i++) { 6813 rt2800_bbp_write(rt2x00dev, 25, 0x90); 6814 msleep(1); 6815 6816 stopband = rt2800_bbp_read(rt2x00dev, 55); 6817 6818 if ((passband - stopband) <= filter_target) { 6819 rfcsr24++; 6820 overtuned += ((passband - stopband) == filter_target); 6821 } else 6822 break; 6823 6824 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 6825 } 6826 6827 rfcsr24 -= !!overtuned; 6828 6829 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 6830 return rfcsr24; 6831 } 6832 6833 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev, 6834 const unsigned int rf_reg) 6835 { 6836 u8 rfcsr; 6837 6838 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg); 6839 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1); 6840 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 6841 msleep(1); 6842 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0); 6843 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 6844 } 6845 6846 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev) 6847 { 6848 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 6849 u8 filter_tgt_bw20; 6850 u8 filter_tgt_bw40; 6851 u8 rfcsr, bbp; 6852 6853 /* 6854 * TODO: sync filter_tgt values with vendor driver 6855 */ 6856 if (rt2x00_rt(rt2x00dev, RT3070)) { 6857 filter_tgt_bw20 = 0x16; 6858 filter_tgt_bw40 = 0x19; 6859 } else { 6860 filter_tgt_bw20 = 0x13; 6861 filter_tgt_bw40 = 0x15; 6862 } 6863 6864 drv_data->calibration_bw20 = 6865 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20); 6866 drv_data->calibration_bw40 = 6867 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40); 6868 6869 /* 6870 * Save BBP 25 & 26 values for later use in channel switching (for 3052) 6871 */ 6872 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 6873 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 6874 6875 /* 6876 * Set back to initial state 6877 */ 6878 rt2800_bbp_write(rt2x00dev, 24, 0); 6879 6880 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 6881 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 6882 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 6883 6884 /* 6885 * Set BBP back to BW20 6886 */ 6887 bbp = rt2800_bbp_read(rt2x00dev, 4); 6888 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 6889 rt2800_bbp_write(rt2x00dev, 4, bbp); 6890 } 6891 6892 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) 6893 { 6894 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 6895 u8 min_gain, rfcsr, bbp; 6896 u16 eeprom; 6897 6898 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 6899 6900 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 6901 if (rt2x00_rt(rt2x00dev, RT3070) || 6902 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 6903 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 6904 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 6905 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev)) 6906 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 6907 } 6908 6909 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2; 6910 if (drv_data->txmixer_gain_24g >= min_gain) { 6911 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 6912 drv_data->txmixer_gain_24g); 6913 } 6914 6915 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 6916 6917 if (rt2x00_rt(rt2x00dev, RT3090)) { 6918 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 6919 bbp = rt2800_bbp_read(rt2x00dev, 138); 6920 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 6921 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 6922 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); 6923 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 6924 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); 6925 rt2800_bbp_write(rt2x00dev, 138, bbp); 6926 } 6927 6928 if (rt2x00_rt(rt2x00dev, RT3070)) { 6929 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27); 6930 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) 6931 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); 6932 else 6933 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); 6934 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); 6935 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); 6936 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); 6937 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 6938 } else if (rt2x00_rt(rt2x00dev, RT3071) || 6939 rt2x00_rt(rt2x00dev, RT3090) || 6940 rt2x00_rt(rt2x00dev, RT3390)) { 6941 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 6942 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 6943 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 6944 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 6945 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 6946 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 6947 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 6948 6949 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15); 6950 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); 6951 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); 6952 6953 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 6954 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); 6955 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 6956 6957 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 6958 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); 6959 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 6960 } 6961 } 6962 6963 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev) 6964 { 6965 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 6966 u8 rfcsr; 6967 u8 tx_gain; 6968 6969 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 6970 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0); 6971 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 6972 6973 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 6974 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g, 6975 RFCSR17_TXMIXER_GAIN); 6976 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain); 6977 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 6978 6979 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38); 6980 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); 6981 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); 6982 6983 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39); 6984 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); 6985 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 6986 6987 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 6988 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 6989 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 6990 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 6991 6992 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 6993 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 6994 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 6995 6996 /* TODO: enable stream mode */ 6997 } 6998 6999 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev) 7000 { 7001 u8 reg; 7002 u16 eeprom; 7003 7004 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 7005 reg = rt2800_bbp_read(rt2x00dev, 138); 7006 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 7007 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 7008 rt2x00_set_field8(®, BBP138_RX_ADC1, 0); 7009 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 7010 rt2x00_set_field8(®, BBP138_TX_DAC1, 1); 7011 rt2800_bbp_write(rt2x00dev, 138, reg); 7012 7013 reg = rt2800_rfcsr_read(rt2x00dev, 38); 7014 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); 7015 rt2800_rfcsr_write(rt2x00dev, 38, reg); 7016 7017 reg = rt2800_rfcsr_read(rt2x00dev, 39); 7018 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); 7019 rt2800_rfcsr_write(rt2x00dev, 39, reg); 7020 7021 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7022 7023 reg = rt2800_rfcsr_read(rt2x00dev, 30); 7024 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); 7025 rt2800_rfcsr_write(rt2x00dev, 30, reg); 7026 } 7027 7028 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev) 7029 { 7030 rt2800_rf_init_calibration(rt2x00dev, 30); 7031 7032 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 7033 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 7034 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 7035 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 7036 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7037 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7038 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7039 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 7040 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 7041 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7042 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 7043 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7044 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 7045 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 7046 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7047 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7048 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7049 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7050 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7051 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7052 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7053 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7054 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7055 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 7056 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7057 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 7058 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 7059 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 7060 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 7061 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 7062 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 7063 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 7064 } 7065 7066 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) 7067 { 7068 u8 rfcsr; 7069 u16 eeprom; 7070 u32 reg; 7071 7072 /* XXX vendor driver do this only for 3070 */ 7073 rt2800_rf_init_calibration(rt2x00dev, 30); 7074 7075 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7076 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7077 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7078 rt2800_rfcsr_write(rt2x00dev, 7, 0x60); 7079 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7080 rt2800_rfcsr_write(rt2x00dev, 10, 0x41); 7081 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7082 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 7083 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7084 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7085 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7086 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7087 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7088 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7089 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7090 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7091 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7092 rt2800_rfcsr_write(rt2x00dev, 25, 0x03); 7093 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 7094 7095 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 7096 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7097 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7098 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7099 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7100 } else if (rt2x00_rt(rt2x00dev, RT3071) || 7101 rt2x00_rt(rt2x00dev, RT3090)) { 7102 rt2800_rfcsr_write(rt2x00dev, 31, 0x14); 7103 7104 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7105 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7106 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7107 7108 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7109 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7110 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7111 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { 7112 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 7113 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 7114 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7115 else 7116 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7117 } 7118 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7119 7120 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7121 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7122 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7123 } 7124 7125 rt2800_rx_filter_calibration(rt2x00dev); 7126 7127 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 7128 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7129 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) 7130 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7131 7132 rt2800_led_open_drain_enable(rt2x00dev); 7133 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7134 } 7135 7136 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) 7137 { 7138 u8 rfcsr; 7139 7140 rt2800_rf_init_calibration(rt2x00dev, 2); 7141 7142 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 7143 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7144 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7145 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7146 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 7147 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3); 7148 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7149 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7150 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7151 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7152 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7153 rt2800_rfcsr_write(rt2x00dev, 18, 0x02); 7154 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7155 rt2800_rfcsr_write(rt2x00dev, 25, 0x83); 7156 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7157 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7158 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7159 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7160 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7161 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7162 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7163 rt2800_rfcsr_write(rt2x00dev, 34, 0x05); 7164 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7165 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7166 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7167 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7168 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7169 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7170 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7171 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b); 7172 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7173 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7174 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7175 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7176 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7177 rt2800_rfcsr_write(rt2x00dev, 49, 0x98); 7178 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7179 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7180 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 7181 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7182 rt2800_rfcsr_write(rt2x00dev, 56, 0x02); 7183 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 7184 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 7185 rt2800_rfcsr_write(rt2x00dev, 59, 0x09); 7186 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7187 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); 7188 7189 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29); 7190 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3); 7191 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr); 7192 7193 rt2800_led_open_drain_enable(rt2x00dev); 7194 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7195 } 7196 7197 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) 7198 { 7199 int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0, 7200 &rt2x00dev->cap_flags); 7201 int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1, 7202 &rt2x00dev->cap_flags); 7203 u8 rfcsr; 7204 7205 rt2800_rf_init_calibration(rt2x00dev, 30); 7206 7207 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7208 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7209 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7210 rt2800_rfcsr_write(rt2x00dev, 3, 0x18); 7211 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7212 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7213 rt2800_rfcsr_write(rt2x00dev, 6, 0x33); 7214 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7215 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7216 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7217 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2); 7218 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 7219 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 7220 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 7221 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a); 7222 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7223 rt2800_rfcsr_write(rt2x00dev, 16, 0x01); 7224 rt2800_rfcsr_write(rt2x00dev, 18, 0x45); 7225 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7226 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7227 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7228 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7229 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7230 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7231 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7232 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7233 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7234 rt2800_rfcsr_write(rt2x00dev, 28, 0x03); 7235 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 7236 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7237 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7238 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7239 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7240 rfcsr = 0x01; 7241 if (tx0_ext_pa) 7242 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1); 7243 if (tx1_ext_pa) 7244 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1); 7245 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 7246 rt2800_rfcsr_write(rt2x00dev, 35, 0x03); 7247 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); 7248 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); 7249 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); 7250 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); 7251 rt2800_rfcsr_write(rt2x00dev, 40, 0x33); 7252 rfcsr = 0x52; 7253 if (!tx0_ext_pa) { 7254 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1); 7255 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1); 7256 } 7257 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr); 7258 rfcsr = 0x52; 7259 if (!tx1_ext_pa) { 7260 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1); 7261 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1); 7262 } 7263 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 7264 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); 7265 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); 7266 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); 7267 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd); 7268 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); 7269 rt2800_rfcsr_write(rt2x00dev, 48, 0x14); 7270 rt2800_rfcsr_write(rt2x00dev, 49, 0x00); 7271 rfcsr = 0x2d; 7272 if (tx0_ext_pa) 7273 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1); 7274 if (tx1_ext_pa) 7275 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1); 7276 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7277 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f)); 7278 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00)); 7279 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52)); 7280 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b)); 7281 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f)); 7282 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00)); 7283 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52)); 7284 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b)); 7285 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 7286 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 7287 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 7288 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7289 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7290 7291 rt2800_rx_filter_calibration(rt2x00dev); 7292 rt2800_led_open_drain_enable(rt2x00dev); 7293 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7294 } 7295 7296 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) 7297 { 7298 u32 reg; 7299 7300 rt2800_rf_init_calibration(rt2x00dev, 30); 7301 7302 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 7303 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 7304 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7305 rt2800_rfcsr_write(rt2x00dev, 3, 0x62); 7306 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7307 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); 7308 rt2800_rfcsr_write(rt2x00dev, 6, 0x42); 7309 rt2800_rfcsr_write(rt2x00dev, 7, 0x34); 7310 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 7311 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 7312 rt2800_rfcsr_write(rt2x00dev, 10, 0x61); 7313 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7314 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); 7315 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); 7316 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7317 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7318 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); 7319 rt2800_rfcsr_write(rt2x00dev, 17, 0x94); 7320 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); 7321 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); 7322 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); 7323 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); 7324 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7325 rt2800_rfcsr_write(rt2x00dev, 23, 0x14); 7326 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7327 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 7328 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7329 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7330 rt2800_rfcsr_write(rt2x00dev, 28, 0x41); 7331 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); 7332 rt2800_rfcsr_write(rt2x00dev, 30, 0x20); 7333 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); 7334 7335 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7336 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7337 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7338 7339 rt2800_rx_filter_calibration(rt2x00dev); 7340 7341 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) 7342 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7343 7344 rt2800_led_open_drain_enable(rt2x00dev); 7345 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7346 } 7347 7348 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) 7349 { 7350 u8 rfcsr; 7351 u32 reg; 7352 7353 rt2800_rf_init_calibration(rt2x00dev, 30); 7354 7355 rt2800_rfcsr_write(rt2x00dev, 0, 0x70); 7356 rt2800_rfcsr_write(rt2x00dev, 1, 0x81); 7357 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7358 rt2800_rfcsr_write(rt2x00dev, 3, 0x02); 7359 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); 7360 rt2800_rfcsr_write(rt2x00dev, 5, 0x05); 7361 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); 7362 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 7363 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 7364 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 7365 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 7366 rt2800_rfcsr_write(rt2x00dev, 12, 0x70); 7367 rt2800_rfcsr_write(rt2x00dev, 13, 0x65); 7368 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); 7369 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7370 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); 7371 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 7372 rt2800_rfcsr_write(rt2x00dev, 18, 0xac); 7373 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 7374 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 7375 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); 7376 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7377 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); 7378 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7379 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 7380 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7381 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7382 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7383 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 7384 rt2800_rfcsr_write(rt2x00dev, 30, 0x09); 7385 rt2800_rfcsr_write(rt2x00dev, 31, 0x10); 7386 7387 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7388 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7389 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7390 7391 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7392 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7393 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7394 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7395 msleep(1); 7396 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7397 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7398 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7399 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7400 7401 rt2800_rx_filter_calibration(rt2x00dev); 7402 rt2800_led_open_drain_enable(rt2x00dev); 7403 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7404 } 7405 7406 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev) 7407 { 7408 u8 bbp; 7409 bool txbf_enabled = false; /* FIXME */ 7410 7411 bbp = rt2800_bbp_read(rt2x00dev, 105); 7412 if (rt2x00dev->default_ant.rx_chain_num == 1) 7413 rt2x00_set_field8(&bbp, BBP105_MLD, 0); 7414 else 7415 rt2x00_set_field8(&bbp, BBP105_MLD, 1); 7416 rt2800_bbp_write(rt2x00dev, 105, bbp); 7417 7418 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7419 7420 rt2800_bbp_write(rt2x00dev, 92, 0x02); 7421 rt2800_bbp_write(rt2x00dev, 82, 0x82); 7422 rt2800_bbp_write(rt2x00dev, 106, 0x05); 7423 rt2800_bbp_write(rt2x00dev, 104, 0x92); 7424 rt2800_bbp_write(rt2x00dev, 88, 0x90); 7425 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 7426 rt2800_bbp_write(rt2x00dev, 47, 0x48); 7427 rt2800_bbp_write(rt2x00dev, 120, 0x50); 7428 7429 if (txbf_enabled) 7430 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 7431 else 7432 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 7433 7434 /* SNR mapping */ 7435 rt2800_bbp_write(rt2x00dev, 142, 6); 7436 rt2800_bbp_write(rt2x00dev, 143, 160); 7437 rt2800_bbp_write(rt2x00dev, 142, 7); 7438 rt2800_bbp_write(rt2x00dev, 143, 161); 7439 rt2800_bbp_write(rt2x00dev, 142, 8); 7440 rt2800_bbp_write(rt2x00dev, 143, 162); 7441 7442 /* ADC/DAC control */ 7443 rt2800_bbp_write(rt2x00dev, 31, 0x08); 7444 7445 /* RX AGC energy lower bound in log2 */ 7446 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 7447 7448 /* FIXME: BBP 105 owerwrite? */ 7449 rt2800_bbp_write(rt2x00dev, 105, 0x04); 7450 7451 } 7452 7453 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) 7454 { 7455 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7456 u32 reg; 7457 u8 rfcsr; 7458 7459 /* Disable GPIO #4 and #7 function for LAN PE control */ 7460 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7461 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); 7462 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); 7463 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7464 7465 /* Initialize default register values */ 7466 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 7467 rt2800_rfcsr_write(rt2x00dev, 3, 0x80); 7468 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7469 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 7470 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7471 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7472 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 7473 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 7474 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e); 7475 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 7476 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 7477 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7478 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7479 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7480 rt2800_rfcsr_write(rt2x00dev, 32, 0x78); 7481 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b); 7482 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 7483 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0); 7484 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 7485 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 7486 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3); 7487 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 7488 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 7489 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 7490 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 7491 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 7492 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 7493 rt2800_rfcsr_write(rt2x00dev, 53, 0x18); 7494 rt2800_rfcsr_write(rt2x00dev, 54, 0x18); 7495 rt2800_rfcsr_write(rt2x00dev, 55, 0x18); 7496 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 7497 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 7498 7499 /* Initiate calibration */ 7500 /* TODO: use rt2800_rf_init_calibration ? */ 7501 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 7502 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 7503 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 7504 7505 rt2800_freq_cal_mode1(rt2x00dev); 7506 7507 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 7508 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1); 7509 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 7510 7511 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7512 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7513 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7514 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7515 usleep_range(1000, 1500); 7516 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7517 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7518 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7519 7520 /* Set initial values for RX filter calibration */ 7521 drv_data->calibration_bw20 = 0x1f; 7522 drv_data->calibration_bw40 = 0x2f; 7523 7524 /* Save BBP 25 & 26 values for later use in channel switching */ 7525 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 7526 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 7527 7528 rt2800_led_open_drain_enable(rt2x00dev); 7529 rt2800_normal_mode_setup_3593(rt2x00dev); 7530 7531 rt3593_post_bbp_init(rt2x00dev); 7532 7533 /* TODO: enable stream mode support */ 7534 } 7535 7536 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev) 7537 { 7538 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7539 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7540 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7541 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7542 rt2800_rfcsr_write(rt2x00dev, 4, 0x49); 7543 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7544 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 7545 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7546 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7547 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7548 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7549 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7550 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7551 if (rt2800_clk_is_20mhz(rt2x00dev)) 7552 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f); 7553 else 7554 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7555 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7556 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7557 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0); 7558 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7559 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 7560 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7561 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7562 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7563 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7564 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7565 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7566 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7567 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7568 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7569 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0); 7570 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7571 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7572 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7573 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7574 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 7575 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7576 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7577 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 7578 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7579 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7580 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7581 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7582 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7583 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 7584 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c); 7585 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6); 7586 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7587 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7588 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7589 rt2800_rfcsr_write(rt2x00dev, 49, 0x80); 7590 rt2800_rfcsr_write(rt2x00dev, 50, 0x00); 7591 rt2800_rfcsr_write(rt2x00dev, 51, 0x00); 7592 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7593 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7594 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 7595 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7596 rt2800_rfcsr_write(rt2x00dev, 56, 0x82); 7597 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 7598 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 7599 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b); 7600 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7601 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 7602 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7603 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7604 } 7605 7606 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) 7607 { 7608 rt2800_rf_init_calibration(rt2x00dev, 2); 7609 7610 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 7611 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7612 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 7613 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7614 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7615 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 7616 else 7617 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 7618 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7619 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7620 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7621 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7622 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7623 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7624 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7625 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 7626 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7627 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 7628 7629 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7630 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7631 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7632 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7633 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7634 if (rt2x00_is_usb(rt2x00dev) && 7635 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7636 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7637 else 7638 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); 7639 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7640 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7641 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7642 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7643 7644 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7645 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7646 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7647 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7648 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 7649 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7650 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7651 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 7652 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7653 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7654 7655 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7656 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7657 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); 7658 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); 7659 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7660 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7661 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7662 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7663 else 7664 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); 7665 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7666 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7667 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 7668 7669 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7670 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7671 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7672 else 7673 rt2800_rfcsr_write(rt2x00dev, 53, 0x84); 7674 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 7675 rt2800_rfcsr_write(rt2x00dev, 55, 0x44); 7676 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7677 rt2800_rfcsr_write(rt2x00dev, 56, 0x42); 7678 else 7679 rt2800_rfcsr_write(rt2x00dev, 56, 0x22); 7680 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 7681 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 7682 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f); 7683 7684 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7685 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 7686 if (rt2x00_is_usb(rt2x00dev)) 7687 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 7688 else 7689 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5); 7690 } else { 7691 if (rt2x00_is_usb(rt2x00dev)) 7692 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); 7693 else 7694 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5); 7695 } 7696 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7697 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7698 7699 rt2800_normal_mode_setup_5xxx(rt2x00dev); 7700 7701 rt2800_led_open_drain_enable(rt2x00dev); 7702 } 7703 7704 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) 7705 { 7706 rt2800_rf_init_calibration(rt2x00dev, 2); 7707 7708 rt2800_rfcsr_write(rt2x00dev, 1, 0x17); 7709 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 7710 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7711 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 7712 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7713 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7714 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7715 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7716 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7717 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7718 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7719 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 7720 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7721 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d); 7722 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7723 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d); 7724 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7725 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b); 7726 rt2800_rfcsr_write(rt2x00dev, 24, 0x44); 7727 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7728 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7729 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7730 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7731 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7732 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7733 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7734 rt2800_rfcsr_write(rt2x00dev, 32, 0x20); 7735 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 7736 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 7737 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7738 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7739 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 7740 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 7741 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7742 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f); 7743 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7744 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7745 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 7746 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7747 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7748 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7749 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c); 7750 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7751 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 7752 rt2800_rfcsr_write(rt2x00dev, 50, 0x94); 7753 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a); 7754 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 7755 rt2800_rfcsr_write(rt2x00dev, 53, 0x44); 7756 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 7757 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7758 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1); 7759 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 7760 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 7761 rt2800_rfcsr_write(rt2x00dev, 59, 0x07); 7762 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7763 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 7764 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 7765 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 7766 7767 rt2800_normal_mode_setup_5xxx(rt2x00dev); 7768 7769 rt2800_led_open_drain_enable(rt2x00dev); 7770 } 7771 7772 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev) 7773 { 7774 rt2800_rf_init_calibration(rt2x00dev, 30); 7775 7776 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F); 7777 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7778 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7779 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4); 7780 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7781 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7782 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7783 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 7784 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7785 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D); 7786 rt2800_rfcsr_write(rt2x00dev, 20, 0x10); 7787 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D); 7788 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7789 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7790 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7791 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 7792 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 7793 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7794 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C); 7795 rt2800_rfcsr_write(rt2x00dev, 53, 0x22); 7796 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 7797 7798 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7799 msleep(1); 7800 7801 rt2800_freq_cal_mode1(rt2x00dev); 7802 7803 /* Enable DC filter */ 7804 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 7805 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 7806 7807 rt2800_normal_mode_setup_5xxx(rt2x00dev); 7808 7809 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C)) 7810 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7811 7812 rt2800_led_open_drain_enable(rt2x00dev); 7813 } 7814 7815 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev, 7816 bool set_bw, bool is_ht40) 7817 { 7818 u8 bbp_val; 7819 7820 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 7821 bbp_val |= 0x1; 7822 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 7823 usleep_range(100, 200); 7824 7825 if (set_bw) { 7826 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 7827 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40); 7828 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 7829 usleep_range(100, 200); 7830 } 7831 7832 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 7833 bbp_val &= (~0x1); 7834 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 7835 usleep_range(100, 200); 7836 } 7837 7838 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal) 7839 { 7840 u8 rf_val; 7841 7842 if (btxcal) 7843 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 7844 else 7845 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02); 7846 7847 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06); 7848 7849 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 7850 rf_val |= 0x80; 7851 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val); 7852 7853 if (btxcal) { 7854 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1); 7855 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20); 7856 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 7857 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 7858 rf_val &= (~0x3F); 7859 rf_val |= 0x3F; 7860 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 7861 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 7862 rf_val &= (~0x3F); 7863 rf_val |= 0x3F; 7864 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 7865 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31); 7866 } else { 7867 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1); 7868 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18); 7869 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 7870 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 7871 rf_val &= (~0x3F); 7872 rf_val |= 0x34; 7873 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 7874 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 7875 rf_val &= (~0x3F); 7876 rf_val |= 0x34; 7877 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 7878 } 7879 7880 return 0; 7881 } 7882 7883 static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev) 7884 { 7885 unsigned int cnt; 7886 u8 bbp_val; 7887 char cal_val; 7888 7889 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82); 7890 7891 cnt = 0; 7892 do { 7893 usleep_range(500, 2000); 7894 bbp_val = rt2800_bbp_read(rt2x00dev, 159); 7895 if (bbp_val == 0x02 || cnt == 20) 7896 break; 7897 7898 cnt++; 7899 } while (cnt < 20); 7900 7901 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39); 7902 cal_val = bbp_val & 0x7F; 7903 if (cal_val >= 0x40) 7904 cal_val -= 128; 7905 7906 return cal_val; 7907 } 7908 7909 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev, 7910 bool btxcal) 7911 { 7912 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7913 u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc; 7914 u8 filter_target; 7915 u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02; 7916 u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31; 7917 int loop = 0, is_ht40, cnt; 7918 u8 bbp_val, rf_val; 7919 char cal_r32_init, cal_r32_val, cal_diff; 7920 u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05; 7921 u8 saverfb5r06, saverfb5r07; 7922 u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20; 7923 u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41; 7924 u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46; 7925 u8 saverfb5r58, saverfb5r59; 7926 u8 savebbp159r0, savebbp159r2, savebbpr23; 7927 u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0; 7928 7929 /* Save MAC registers */ 7930 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 7931 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 7932 7933 /* save BBP registers */ 7934 savebbpr23 = rt2800_bbp_read(rt2x00dev, 23); 7935 7936 savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0); 7937 savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2); 7938 7939 /* Save RF registers */ 7940 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 7941 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 7942 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 7943 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 7944 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5); 7945 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 7946 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 7947 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 7948 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 7949 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 7950 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 7951 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 7952 7953 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37); 7954 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38); 7955 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39); 7956 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40); 7957 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41); 7958 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42); 7959 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43); 7960 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44); 7961 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45); 7962 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46); 7963 7964 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 7965 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 7966 7967 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 7968 rf_val |= 0x3; 7969 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 7970 7971 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 7972 rf_val |= 0x1; 7973 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val); 7974 7975 cnt = 0; 7976 do { 7977 usleep_range(500, 2000); 7978 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 7979 if (((rf_val & 0x1) == 0x00) || (cnt == 40)) 7980 break; 7981 cnt++; 7982 } while (cnt < 40); 7983 7984 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 7985 rf_val &= (~0x3); 7986 rf_val |= 0x1; 7987 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 7988 7989 /* I-3 */ 7990 bbp_val = rt2800_bbp_read(rt2x00dev, 23); 7991 bbp_val &= (~0x1F); 7992 bbp_val |= 0x10; 7993 rt2800_bbp_write(rt2x00dev, 23, bbp_val); 7994 7995 do { 7996 /* I-4,5,6,7,8,9 */ 7997 if (loop == 0) { 7998 is_ht40 = false; 7999 8000 if (btxcal) 8001 filter_target = tx_filter_target_20m; 8002 else 8003 filter_target = rx_filter_target_20m; 8004 } else { 8005 is_ht40 = true; 8006 8007 if (btxcal) 8008 filter_target = tx_filter_target_40m; 8009 else 8010 filter_target = rx_filter_target_40m; 8011 } 8012 8013 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 8014 rf_val &= (~0x04); 8015 if (loop == 1) 8016 rf_val |= 0x4; 8017 8018 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val); 8019 8020 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40); 8021 8022 rt2800_rf_lp_config(rt2x00dev, btxcal); 8023 if (btxcal) { 8024 tx_agc_fc = 0; 8025 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 8026 rf_val &= (~0x7F); 8027 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 8028 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 8029 rf_val &= (~0x7F); 8030 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 8031 } else { 8032 rx_agc_fc = 0; 8033 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 8034 rf_val &= (~0x7F); 8035 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 8036 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 8037 rf_val &= (~0x7F); 8038 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 8039 } 8040 8041 usleep_range(1000, 2000); 8042 8043 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 8044 bbp_val &= (~0x6); 8045 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 8046 8047 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 8048 8049 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 8050 8051 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 8052 bbp_val |= 0x6; 8053 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 8054 do_cal: 8055 if (btxcal) { 8056 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 8057 rf_val &= (~0x7F); 8058 rf_val |= tx_agc_fc; 8059 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 8060 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 8061 rf_val &= (~0x7F); 8062 rf_val |= tx_agc_fc; 8063 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 8064 } else { 8065 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 8066 rf_val &= (~0x7F); 8067 rf_val |= rx_agc_fc; 8068 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 8069 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 8070 rf_val &= (~0x7F); 8071 rf_val |= rx_agc_fc; 8072 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 8073 } 8074 8075 usleep_range(500, 1000); 8076 8077 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 8078 8079 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 8080 8081 cal_diff = cal_r32_init - cal_r32_val; 8082 8083 if (btxcal) 8084 cmm_agc_fc = tx_agc_fc; 8085 else 8086 cmm_agc_fc = rx_agc_fc; 8087 8088 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) || 8089 ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) { 8090 if (btxcal) 8091 tx_agc_fc = 0; 8092 else 8093 rx_agc_fc = 0; 8094 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) { 8095 if (btxcal) 8096 tx_agc_fc++; 8097 else 8098 rx_agc_fc++; 8099 goto do_cal; 8100 } 8101 8102 if (btxcal) { 8103 if (loop == 0) 8104 drv_data->tx_calibration_bw20 = tx_agc_fc; 8105 else 8106 drv_data->tx_calibration_bw40 = tx_agc_fc; 8107 } else { 8108 if (loop == 0) 8109 drv_data->rx_calibration_bw20 = rx_agc_fc; 8110 else 8111 drv_data->rx_calibration_bw40 = rx_agc_fc; 8112 } 8113 8114 loop++; 8115 } while (loop <= 1); 8116 8117 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00); 8118 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01); 8119 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03); 8120 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04); 8121 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05); 8122 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06); 8123 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07); 8124 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08); 8125 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); 8126 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); 8127 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); 8128 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); 8129 8130 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37); 8131 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38); 8132 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39); 8133 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40); 8134 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41); 8135 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42); 8136 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43); 8137 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44); 8138 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45); 8139 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46); 8140 8141 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58); 8142 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59); 8143 8144 rt2800_bbp_write(rt2x00dev, 23, savebbpr23); 8145 8146 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0); 8147 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2); 8148 8149 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 8150 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 8151 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)); 8152 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 8153 8154 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); 8155 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); 8156 } 8157 8158 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev) 8159 { 8160 /* Initialize RF central register to default value */ 8161 rt2800_rfcsr_write(rt2x00dev, 0, 0x02); 8162 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 8163 rt2800_rfcsr_write(rt2x00dev, 2, 0x33); 8164 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF); 8165 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 8166 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 8167 rt2800_rfcsr_write(rt2x00dev, 6, 0x00); 8168 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8169 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 8170 rt2800_rfcsr_write(rt2x00dev, 9, 0x00); 8171 rt2800_rfcsr_write(rt2x00dev, 10, 0x00); 8172 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 8173 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset); 8174 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 8175 rt2800_rfcsr_write(rt2x00dev, 14, 0x40); 8176 rt2800_rfcsr_write(rt2x00dev, 15, 0x22); 8177 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C); 8178 rt2800_rfcsr_write(rt2x00dev, 17, 0x00); 8179 rt2800_rfcsr_write(rt2x00dev, 18, 0x00); 8180 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8181 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0); 8182 rt2800_rfcsr_write(rt2x00dev, 21, 0x12); 8183 rt2800_rfcsr_write(rt2x00dev, 22, 0x07); 8184 rt2800_rfcsr_write(rt2x00dev, 23, 0x13); 8185 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE); 8186 rt2800_rfcsr_write(rt2x00dev, 25, 0x24); 8187 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A); 8188 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8189 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8190 rt2800_rfcsr_write(rt2x00dev, 29, 0x05); 8191 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 8192 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 8193 rt2800_rfcsr_write(rt2x00dev, 32, 0x00); 8194 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8195 rt2800_rfcsr_write(rt2x00dev, 34, 0x00); 8196 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 8197 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8198 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 8199 rt2800_rfcsr_write(rt2x00dev, 38, 0x00); 8200 rt2800_rfcsr_write(rt2x00dev, 39, 0x00); 8201 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 8202 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0); 8203 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B); 8204 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 8205 8206 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 8207 if (rt2800_clk_is_20mhz(rt2x00dev)) 8208 rt2800_rfcsr_write(rt2x00dev, 13, 0x03); 8209 else 8210 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 8211 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C); 8212 rt2800_rfcsr_write(rt2x00dev, 16, 0x80); 8213 rt2800_rfcsr_write(rt2x00dev, 17, 0x99); 8214 rt2800_rfcsr_write(rt2x00dev, 18, 0x99); 8215 rt2800_rfcsr_write(rt2x00dev, 19, 0x09); 8216 rt2800_rfcsr_write(rt2x00dev, 20, 0x50); 8217 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0); 8218 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 8219 rt2800_rfcsr_write(rt2x00dev, 23, 0x06); 8220 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8221 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 8222 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D); 8223 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8224 rt2800_rfcsr_write(rt2x00dev, 28, 0x61); 8225 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5); 8226 rt2800_rfcsr_write(rt2x00dev, 43, 0x02); 8227 8228 rt2800_rfcsr_write(rt2x00dev, 28, 0x62); 8229 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD); 8230 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 8231 8232 /* Initialize RF channel register to default value */ 8233 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03); 8234 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00); 8235 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00); 8236 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00); 8237 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00); 8238 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08); 8239 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00); 8240 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51); 8241 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53); 8242 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16); 8243 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61); 8244 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 8245 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22); 8246 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D); 8247 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 8248 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13); 8249 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22); 8250 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27); 8251 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02); 8252 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 8253 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01); 8254 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52); 8255 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80); 8256 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3); 8257 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00); 8258 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00); 8259 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00); 8260 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00); 8261 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C); 8262 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B); 8263 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B); 8264 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31); 8265 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D); 8266 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00); 8267 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6); 8268 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55); 8269 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00); 8270 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB); 8271 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3); 8272 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3); 8273 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03); 8274 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00); 8275 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00); 8276 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3); 8277 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3); 8278 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 8279 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07); 8280 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68); 8281 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF); 8282 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C); 8283 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07); 8284 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8); 8285 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85); 8286 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10); 8287 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07); 8288 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A); 8289 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85); 8290 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10); 8291 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C); 8292 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00); 8293 8294 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5); 8295 8296 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47); 8297 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71); 8298 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33); 8299 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E); 8300 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23); 8301 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4); 8302 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02); 8303 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12); 8304 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C); 8305 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB); 8306 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D); 8307 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6); 8308 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08); 8309 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4); 8310 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 8311 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3); 8312 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 8313 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); 8314 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67); 8315 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69); 8316 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF); 8317 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27); 8318 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20); 8319 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 8320 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF); 8321 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C); 8322 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20); 8323 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 8324 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7); 8325 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09); 8326 8327 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51); 8328 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 8329 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 8330 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C); 8331 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64); 8332 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51); 8333 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36); 8334 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 8335 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16); 8336 8337 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C); 8338 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC); 8339 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F); 8340 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); 8341 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 8342 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 8343 8344 /* Initialize RF channel register for DRQFN */ 8345 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 8346 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3); 8347 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5); 8348 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28); 8349 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68); 8350 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7); 8351 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02); 8352 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7); 8353 8354 /* Initialize RF DC calibration register to default value */ 8355 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47); 8356 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00); 8357 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00); 8358 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00); 8359 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00); 8360 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 8361 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 8362 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 8363 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 8364 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00); 8365 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07); 8366 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01); 8367 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07); 8368 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07); 8369 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07); 8370 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20); 8371 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22); 8372 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00); 8373 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00); 8374 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00); 8375 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00); 8376 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1); 8377 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11); 8378 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02); 8379 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41); 8380 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20); 8381 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00); 8382 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7); 8383 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2); 8384 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20); 8385 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49); 8386 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20); 8387 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04); 8388 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1); 8389 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1); 8390 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01); 8391 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00); 8392 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00); 8393 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00); 8394 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00); 8395 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00); 8396 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00); 8397 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E); 8398 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D); 8399 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E); 8400 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D); 8401 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E); 8402 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D); 8403 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00); 8404 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00); 8405 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00); 8406 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00); 8407 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00); 8408 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 8409 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 8410 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A); 8411 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00); 8412 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00); 8413 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00); 8414 8415 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08); 8416 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04); 8417 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20); 8418 8419 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 8420 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C); 8421 8422 rt2800_bw_filter_calibration(rt2x00dev, true); 8423 rt2800_bw_filter_calibration(rt2x00dev, false); 8424 } 8425 8426 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) 8427 { 8428 if (rt2800_is_305x_soc(rt2x00dev)) { 8429 rt2800_init_rfcsr_305x_soc(rt2x00dev); 8430 return; 8431 } 8432 8433 switch (rt2x00dev->chip.rt) { 8434 case RT3070: 8435 case RT3071: 8436 case RT3090: 8437 rt2800_init_rfcsr_30xx(rt2x00dev); 8438 break; 8439 case RT3290: 8440 rt2800_init_rfcsr_3290(rt2x00dev); 8441 break; 8442 case RT3352: 8443 rt2800_init_rfcsr_3352(rt2x00dev); 8444 break; 8445 case RT3390: 8446 rt2800_init_rfcsr_3390(rt2x00dev); 8447 break; 8448 case RT3572: 8449 rt2800_init_rfcsr_3572(rt2x00dev); 8450 break; 8451 case RT3593: 8452 rt2800_init_rfcsr_3593(rt2x00dev); 8453 break; 8454 case RT5350: 8455 rt2800_init_rfcsr_5350(rt2x00dev); 8456 break; 8457 case RT5390: 8458 rt2800_init_rfcsr_5390(rt2x00dev); 8459 break; 8460 case RT5392: 8461 rt2800_init_rfcsr_5392(rt2x00dev); 8462 break; 8463 case RT5592: 8464 rt2800_init_rfcsr_5592(rt2x00dev); 8465 break; 8466 case RT6352: 8467 rt2800_init_rfcsr_6352(rt2x00dev); 8468 break; 8469 } 8470 } 8471 8472 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) 8473 { 8474 u32 reg; 8475 u16 word; 8476 8477 /* 8478 * Initialize MAC registers. 8479 */ 8480 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || 8481 rt2800_init_registers(rt2x00dev))) 8482 return -EIO; 8483 8484 /* 8485 * Wait BBP/RF to wake up. 8486 */ 8487 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev))) 8488 return -EIO; 8489 8490 /* 8491 * Send signal during boot time to initialize firmware. 8492 */ 8493 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 8494 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 8495 if (rt2x00_is_usb(rt2x00dev)) 8496 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 8497 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 8498 msleep(1); 8499 8500 /* 8501 * Make sure BBP is up and running. 8502 */ 8503 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev))) 8504 return -EIO; 8505 8506 /* 8507 * Initialize BBP/RF registers. 8508 */ 8509 rt2800_init_bbp(rt2x00dev); 8510 rt2800_init_rfcsr(rt2x00dev); 8511 8512 if (rt2x00_is_usb(rt2x00dev) && 8513 (rt2x00_rt(rt2x00dev, RT3070) || 8514 rt2x00_rt(rt2x00dev, RT3071) || 8515 rt2x00_rt(rt2x00dev, RT3572))) { 8516 udelay(200); 8517 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); 8518 udelay(10); 8519 } 8520 8521 /* 8522 * Enable RX. 8523 */ 8524 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8525 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 8526 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 8527 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 8528 8529 udelay(50); 8530 8531 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 8532 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 8533 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 8534 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 8535 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 8536 8537 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8538 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 8539 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); 8540 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 8541 8542 /* 8543 * Initialize LED control 8544 */ 8545 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF); 8546 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, 8547 word & 0xff, (word >> 8) & 0xff); 8548 8549 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF); 8550 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, 8551 word & 0xff, (word >> 8) & 0xff); 8552 8553 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY); 8554 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, 8555 word & 0xff, (word >> 8) & 0xff); 8556 8557 return 0; 8558 } 8559 EXPORT_SYMBOL_GPL(rt2800_enable_radio); 8560 8561 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) 8562 { 8563 u32 reg; 8564 8565 rt2800_disable_wpdma(rt2x00dev); 8566 8567 /* Wait for DMA, ignore error */ 8568 rt2800_wait_wpdma_ready(rt2x00dev); 8569 8570 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8571 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); 8572 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 8573 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 8574 } 8575 EXPORT_SYMBOL_GPL(rt2800_disable_radio); 8576 8577 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 8578 { 8579 u32 reg; 8580 u16 efuse_ctrl_reg; 8581 8582 if (rt2x00_rt(rt2x00dev, RT3290)) 8583 efuse_ctrl_reg = EFUSE_CTRL_3290; 8584 else 8585 efuse_ctrl_reg = EFUSE_CTRL; 8586 8587 reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg); 8588 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); 8589 } 8590 EXPORT_SYMBOL_GPL(rt2800_efuse_detect); 8591 8592 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) 8593 { 8594 u32 reg; 8595 u16 efuse_ctrl_reg; 8596 u16 efuse_data0_reg; 8597 u16 efuse_data1_reg; 8598 u16 efuse_data2_reg; 8599 u16 efuse_data3_reg; 8600 8601 if (rt2x00_rt(rt2x00dev, RT3290)) { 8602 efuse_ctrl_reg = EFUSE_CTRL_3290; 8603 efuse_data0_reg = EFUSE_DATA0_3290; 8604 efuse_data1_reg = EFUSE_DATA1_3290; 8605 efuse_data2_reg = EFUSE_DATA2_3290; 8606 efuse_data3_reg = EFUSE_DATA3_3290; 8607 } else { 8608 efuse_ctrl_reg = EFUSE_CTRL; 8609 efuse_data0_reg = EFUSE_DATA0; 8610 efuse_data1_reg = EFUSE_DATA1; 8611 efuse_data2_reg = EFUSE_DATA2; 8612 efuse_data3_reg = EFUSE_DATA3; 8613 } 8614 mutex_lock(&rt2x00dev->csr_mutex); 8615 8616 reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg); 8617 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); 8618 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); 8619 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); 8620 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); 8621 8622 /* Wait until the EEPROM has been loaded */ 8623 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); 8624 /* Apparently the data is read from end to start */ 8625 reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg); 8626 /* The returned value is in CPU order, but eeprom is le */ 8627 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); 8628 reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg); 8629 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); 8630 reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg); 8631 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); 8632 reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg); 8633 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); 8634 8635 mutex_unlock(&rt2x00dev->csr_mutex); 8636 } 8637 8638 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 8639 { 8640 unsigned int i; 8641 8642 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) 8643 rt2800_efuse_read(rt2x00dev, i); 8644 8645 return 0; 8646 } 8647 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); 8648 8649 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev) 8650 { 8651 u16 word; 8652 8653 if (rt2x00_rt(rt2x00dev, RT3593)) 8654 return 0; 8655 8656 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG); 8657 if ((word & 0x00ff) != 0x00ff) 8658 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL); 8659 8660 return 0; 8661 } 8662 8663 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev) 8664 { 8665 u16 word; 8666 8667 if (rt2x00_rt(rt2x00dev, RT3593)) 8668 return 0; 8669 8670 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A); 8671 if ((word & 0x00ff) != 0x00ff) 8672 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL); 8673 8674 return 0; 8675 } 8676 8677 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) 8678 { 8679 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 8680 u16 word; 8681 u8 *mac; 8682 u8 default_lna_gain; 8683 int retval; 8684 8685 /* 8686 * Read the EEPROM. 8687 */ 8688 retval = rt2800_read_eeprom(rt2x00dev); 8689 if (retval) 8690 return retval; 8691 8692 /* 8693 * Start validation of the data that has been read. 8694 */ 8695 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 8696 rt2x00lib_set_mac_address(rt2x00dev, mac); 8697 8698 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 8699 if (word == 0xffff) { 8700 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 8701 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); 8702 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); 8703 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 8704 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 8705 } else if (rt2x00_rt(rt2x00dev, RT2860) || 8706 rt2x00_rt(rt2x00dev, RT2872)) { 8707 /* 8708 * There is a max of 2 RX streams for RT28x0 series 8709 */ 8710 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2) 8711 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 8712 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 8713 } 8714 8715 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 8716 if (word == 0xffff) { 8717 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); 8718 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); 8719 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0); 8720 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0); 8721 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0); 8722 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0); 8723 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0); 8724 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0); 8725 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0); 8726 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0); 8727 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0); 8728 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0); 8729 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0); 8730 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); 8731 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); 8732 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); 8733 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 8734 } 8735 8736 word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 8737 if ((word & 0x00ff) == 0x00ff) { 8738 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 8739 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 8740 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); 8741 } 8742 if ((word & 0xff00) == 0xff00) { 8743 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, 8744 LED_MODE_TXRX_ACTIVITY); 8745 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); 8746 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 8747 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); 8748 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); 8749 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); 8750 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word); 8751 } 8752 8753 /* 8754 * During the LNA validation we are going to use 8755 * lna0 as correct value. Note that EEPROM_LNA 8756 * is never validated. 8757 */ 8758 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 8759 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); 8760 8761 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 8762 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) 8763 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); 8764 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) 8765 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); 8766 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); 8767 8768 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev); 8769 8770 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 8771 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) 8772 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); 8773 if (!rt2x00_rt(rt2x00dev, RT3593)) { 8774 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || 8775 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) 8776 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, 8777 default_lna_gain); 8778 } 8779 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); 8780 8781 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev); 8782 8783 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 8784 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) 8785 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); 8786 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) 8787 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); 8788 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); 8789 8790 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 8791 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) 8792 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); 8793 if (!rt2x00_rt(rt2x00dev, RT3593)) { 8794 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || 8795 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) 8796 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, 8797 default_lna_gain); 8798 } 8799 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); 8800 8801 if (rt2x00_rt(rt2x00dev, RT3593)) { 8802 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 8803 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 || 8804 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff) 8805 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 8806 default_lna_gain); 8807 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 || 8808 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff) 8809 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 8810 default_lna_gain); 8811 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word); 8812 } 8813 8814 return 0; 8815 } 8816 8817 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) 8818 { 8819 u16 value; 8820 u16 eeprom; 8821 u16 rf; 8822 8823 /* 8824 * Read EEPROM word for configuration. 8825 */ 8826 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 8827 8828 /* 8829 * Identify RF chipset by EEPROM value 8830 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 8831 * RT53xx: defined in "EEPROM_CHIP_ID" field 8832 */ 8833 if (rt2x00_rt(rt2x00dev, RT3290) || 8834 rt2x00_rt(rt2x00dev, RT5390) || 8835 rt2x00_rt(rt2x00dev, RT5392) || 8836 rt2x00_rt(rt2x00dev, RT6352)) 8837 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID); 8838 else if (rt2x00_rt(rt2x00dev, RT3352)) 8839 rf = RF3322; 8840 else if (rt2x00_rt(rt2x00dev, RT5350)) 8841 rf = RF5350; 8842 else 8843 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 8844 8845 switch (rf) { 8846 case RF2820: 8847 case RF2850: 8848 case RF2720: 8849 case RF2750: 8850 case RF3020: 8851 case RF2020: 8852 case RF3021: 8853 case RF3022: 8854 case RF3052: 8855 case RF3053: 8856 case RF3070: 8857 case RF3290: 8858 case RF3320: 8859 case RF3322: 8860 case RF5350: 8861 case RF5360: 8862 case RF5362: 8863 case RF5370: 8864 case RF5372: 8865 case RF5390: 8866 case RF5392: 8867 case RF5592: 8868 case RF7620: 8869 break; 8870 default: 8871 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n", 8872 rf); 8873 return -ENODEV; 8874 } 8875 8876 rt2x00_set_rf(rt2x00dev, rf); 8877 8878 /* 8879 * Identify default antenna configuration. 8880 */ 8881 rt2x00dev->default_ant.tx_chain_num = 8882 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); 8883 rt2x00dev->default_ant.rx_chain_num = 8884 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); 8885 8886 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 8887 8888 if (rt2x00_rt(rt2x00dev, RT3070) || 8889 rt2x00_rt(rt2x00dev, RT3090) || 8890 rt2x00_rt(rt2x00dev, RT3352) || 8891 rt2x00_rt(rt2x00dev, RT3390)) { 8892 value = rt2x00_get_field16(eeprom, 8893 EEPROM_NIC_CONF1_ANT_DIVERSITY); 8894 switch (value) { 8895 case 0: 8896 case 1: 8897 case 2: 8898 rt2x00dev->default_ant.tx = ANTENNA_A; 8899 rt2x00dev->default_ant.rx = ANTENNA_A; 8900 break; 8901 case 3: 8902 rt2x00dev->default_ant.tx = ANTENNA_A; 8903 rt2x00dev->default_ant.rx = ANTENNA_B; 8904 break; 8905 } 8906 } else { 8907 rt2x00dev->default_ant.tx = ANTENNA_A; 8908 rt2x00dev->default_ant.rx = ANTENNA_A; 8909 } 8910 8911 /* These chips have hardware RX antenna diversity */ 8912 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 8913 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 8914 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */ 8915 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */ 8916 } 8917 8918 /* 8919 * Determine external LNA informations. 8920 */ 8921 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G)) 8922 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); 8923 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G)) 8924 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); 8925 8926 /* 8927 * Detect if this device has an hardware controlled radio. 8928 */ 8929 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO)) 8930 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 8931 8932 /* 8933 * Detect if this device has Bluetooth co-existence. 8934 */ 8935 if (!rt2x00_rt(rt2x00dev, RT3352) && 8936 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) 8937 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); 8938 8939 /* 8940 * Read frequency offset and RF programming sequence. 8941 */ 8942 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 8943 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 8944 8945 /* 8946 * Store led settings, for correct led behaviour. 8947 */ 8948 #ifdef CONFIG_RT2X00_LIB_LEDS 8949 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 8950 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 8951 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 8952 8953 rt2x00dev->led_mcu_reg = eeprom; 8954 #endif /* CONFIG_RT2X00_LIB_LEDS */ 8955 8956 /* 8957 * Check if support EIRP tx power limit feature. 8958 */ 8959 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 8960 8961 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < 8962 EIRP_MAX_TX_POWER_LIMIT) 8963 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); 8964 8965 /* 8966 * Detect if device uses internal or external PA 8967 */ 8968 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 8969 8970 if (rt2x00_rt(rt2x00dev, RT3352)) { 8971 if (rt2x00_get_field16(eeprom, 8972 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352)) 8973 __set_bit(CAPABILITY_EXTERNAL_PA_TX0, 8974 &rt2x00dev->cap_flags); 8975 if (rt2x00_get_field16(eeprom, 8976 EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352)) 8977 __set_bit(CAPABILITY_EXTERNAL_PA_TX1, 8978 &rt2x00dev->cap_flags); 8979 } 8980 8981 return 0; 8982 } 8983 8984 /* 8985 * RF value list for rt28xx 8986 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) 8987 */ 8988 static const struct rf_channel rf_vals[] = { 8989 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, 8990 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, 8991 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, 8992 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, 8993 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, 8994 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, 8995 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, 8996 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, 8997 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, 8998 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, 8999 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, 9000 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, 9001 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, 9002 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, 9003 9004 /* 802.11 UNI / HyperLan 2 */ 9005 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, 9006 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, 9007 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, 9008 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, 9009 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, 9010 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, 9011 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, 9012 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, 9013 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, 9014 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, 9015 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, 9016 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, 9017 9018 /* 802.11 HyperLan 2 */ 9019 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, 9020 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, 9021 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, 9022 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, 9023 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, 9024 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, 9025 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, 9026 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, 9027 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, 9028 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, 9029 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, 9030 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, 9031 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, 9032 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, 9033 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, 9034 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, 9035 9036 /* 802.11 UNII */ 9037 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, 9038 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, 9039 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, 9040 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, 9041 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, 9042 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, 9043 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, 9044 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, 9045 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, 9046 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, 9047 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, 9048 9049 /* 802.11 Japan */ 9050 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, 9051 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, 9052 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, 9053 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, 9054 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, 9055 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, 9056 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, 9057 }; 9058 9059 /* 9060 * RF value list for rt3xxx 9061 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053) 9062 */ 9063 static const struct rf_channel rf_vals_3x[] = { 9064 {1, 241, 2, 2 }, 9065 {2, 241, 2, 7 }, 9066 {3, 242, 2, 2 }, 9067 {4, 242, 2, 7 }, 9068 {5, 243, 2, 2 }, 9069 {6, 243, 2, 7 }, 9070 {7, 244, 2, 2 }, 9071 {8, 244, 2, 7 }, 9072 {9, 245, 2, 2 }, 9073 {10, 245, 2, 7 }, 9074 {11, 246, 2, 2 }, 9075 {12, 246, 2, 7 }, 9076 {13, 247, 2, 2 }, 9077 {14, 248, 2, 4 }, 9078 9079 /* 802.11 UNI / HyperLan 2 */ 9080 {36, 0x56, 0, 4}, 9081 {38, 0x56, 0, 6}, 9082 {40, 0x56, 0, 8}, 9083 {44, 0x57, 0, 0}, 9084 {46, 0x57, 0, 2}, 9085 {48, 0x57, 0, 4}, 9086 {52, 0x57, 0, 8}, 9087 {54, 0x57, 0, 10}, 9088 {56, 0x58, 0, 0}, 9089 {60, 0x58, 0, 4}, 9090 {62, 0x58, 0, 6}, 9091 {64, 0x58, 0, 8}, 9092 9093 /* 802.11 HyperLan 2 */ 9094 {100, 0x5b, 0, 8}, 9095 {102, 0x5b, 0, 10}, 9096 {104, 0x5c, 0, 0}, 9097 {108, 0x5c, 0, 4}, 9098 {110, 0x5c, 0, 6}, 9099 {112, 0x5c, 0, 8}, 9100 {116, 0x5d, 0, 0}, 9101 {118, 0x5d, 0, 2}, 9102 {120, 0x5d, 0, 4}, 9103 {124, 0x5d, 0, 8}, 9104 {126, 0x5d, 0, 10}, 9105 {128, 0x5e, 0, 0}, 9106 {132, 0x5e, 0, 4}, 9107 {134, 0x5e, 0, 6}, 9108 {136, 0x5e, 0, 8}, 9109 {140, 0x5f, 0, 0}, 9110 9111 /* 802.11 UNII */ 9112 {149, 0x5f, 0, 9}, 9113 {151, 0x5f, 0, 11}, 9114 {153, 0x60, 0, 1}, 9115 {157, 0x60, 0, 5}, 9116 {159, 0x60, 0, 7}, 9117 {161, 0x60, 0, 9}, 9118 {165, 0x61, 0, 1}, 9119 {167, 0x61, 0, 3}, 9120 {169, 0x61, 0, 5}, 9121 {171, 0x61, 0, 7}, 9122 {173, 0x61, 0, 9}, 9123 }; 9124 9125 /* 9126 * RF value list for rt3xxx with Xtal20MHz 9127 * Supports: 2.4 GHz (all) (RF3322) 9128 */ 9129 static const struct rf_channel rf_vals_3x_xtal20[] = { 9130 {1, 0xE2, 2, 0x14}, 9131 {2, 0xE3, 2, 0x14}, 9132 {3, 0xE4, 2, 0x14}, 9133 {4, 0xE5, 2, 0x14}, 9134 {5, 0xE6, 2, 0x14}, 9135 {6, 0xE7, 2, 0x14}, 9136 {7, 0xE8, 2, 0x14}, 9137 {8, 0xE9, 2, 0x14}, 9138 {9, 0xEA, 2, 0x14}, 9139 {10, 0xEB, 2, 0x14}, 9140 {11, 0xEC, 2, 0x14}, 9141 {12, 0xED, 2, 0x14}, 9142 {13, 0xEE, 2, 0x14}, 9143 {14, 0xF0, 2, 0x18}, 9144 }; 9145 9146 static const struct rf_channel rf_vals_5592_xtal20[] = { 9147 /* Channel, N, K, mod, R */ 9148 {1, 482, 4, 10, 3}, 9149 {2, 483, 4, 10, 3}, 9150 {3, 484, 4, 10, 3}, 9151 {4, 485, 4, 10, 3}, 9152 {5, 486, 4, 10, 3}, 9153 {6, 487, 4, 10, 3}, 9154 {7, 488, 4, 10, 3}, 9155 {8, 489, 4, 10, 3}, 9156 {9, 490, 4, 10, 3}, 9157 {10, 491, 4, 10, 3}, 9158 {11, 492, 4, 10, 3}, 9159 {12, 493, 4, 10, 3}, 9160 {13, 494, 4, 10, 3}, 9161 {14, 496, 8, 10, 3}, 9162 {36, 172, 8, 12, 1}, 9163 {38, 173, 0, 12, 1}, 9164 {40, 173, 4, 12, 1}, 9165 {42, 173, 8, 12, 1}, 9166 {44, 174, 0, 12, 1}, 9167 {46, 174, 4, 12, 1}, 9168 {48, 174, 8, 12, 1}, 9169 {50, 175, 0, 12, 1}, 9170 {52, 175, 4, 12, 1}, 9171 {54, 175, 8, 12, 1}, 9172 {56, 176, 0, 12, 1}, 9173 {58, 176, 4, 12, 1}, 9174 {60, 176, 8, 12, 1}, 9175 {62, 177, 0, 12, 1}, 9176 {64, 177, 4, 12, 1}, 9177 {100, 183, 4, 12, 1}, 9178 {102, 183, 8, 12, 1}, 9179 {104, 184, 0, 12, 1}, 9180 {106, 184, 4, 12, 1}, 9181 {108, 184, 8, 12, 1}, 9182 {110, 185, 0, 12, 1}, 9183 {112, 185, 4, 12, 1}, 9184 {114, 185, 8, 12, 1}, 9185 {116, 186, 0, 12, 1}, 9186 {118, 186, 4, 12, 1}, 9187 {120, 186, 8, 12, 1}, 9188 {122, 187, 0, 12, 1}, 9189 {124, 187, 4, 12, 1}, 9190 {126, 187, 8, 12, 1}, 9191 {128, 188, 0, 12, 1}, 9192 {130, 188, 4, 12, 1}, 9193 {132, 188, 8, 12, 1}, 9194 {134, 189, 0, 12, 1}, 9195 {136, 189, 4, 12, 1}, 9196 {138, 189, 8, 12, 1}, 9197 {140, 190, 0, 12, 1}, 9198 {149, 191, 6, 12, 1}, 9199 {151, 191, 10, 12, 1}, 9200 {153, 192, 2, 12, 1}, 9201 {155, 192, 6, 12, 1}, 9202 {157, 192, 10, 12, 1}, 9203 {159, 193, 2, 12, 1}, 9204 {161, 193, 6, 12, 1}, 9205 {165, 194, 2, 12, 1}, 9206 {184, 164, 0, 12, 1}, 9207 {188, 164, 4, 12, 1}, 9208 {192, 165, 8, 12, 1}, 9209 {196, 166, 0, 12, 1}, 9210 }; 9211 9212 static const struct rf_channel rf_vals_5592_xtal40[] = { 9213 /* Channel, N, K, mod, R */ 9214 {1, 241, 2, 10, 3}, 9215 {2, 241, 7, 10, 3}, 9216 {3, 242, 2, 10, 3}, 9217 {4, 242, 7, 10, 3}, 9218 {5, 243, 2, 10, 3}, 9219 {6, 243, 7, 10, 3}, 9220 {7, 244, 2, 10, 3}, 9221 {8, 244, 7, 10, 3}, 9222 {9, 245, 2, 10, 3}, 9223 {10, 245, 7, 10, 3}, 9224 {11, 246, 2, 10, 3}, 9225 {12, 246, 7, 10, 3}, 9226 {13, 247, 2, 10, 3}, 9227 {14, 248, 4, 10, 3}, 9228 {36, 86, 4, 12, 1}, 9229 {38, 86, 6, 12, 1}, 9230 {40, 86, 8, 12, 1}, 9231 {42, 86, 10, 12, 1}, 9232 {44, 87, 0, 12, 1}, 9233 {46, 87, 2, 12, 1}, 9234 {48, 87, 4, 12, 1}, 9235 {50, 87, 6, 12, 1}, 9236 {52, 87, 8, 12, 1}, 9237 {54, 87, 10, 12, 1}, 9238 {56, 88, 0, 12, 1}, 9239 {58, 88, 2, 12, 1}, 9240 {60, 88, 4, 12, 1}, 9241 {62, 88, 6, 12, 1}, 9242 {64, 88, 8, 12, 1}, 9243 {100, 91, 8, 12, 1}, 9244 {102, 91, 10, 12, 1}, 9245 {104, 92, 0, 12, 1}, 9246 {106, 92, 2, 12, 1}, 9247 {108, 92, 4, 12, 1}, 9248 {110, 92, 6, 12, 1}, 9249 {112, 92, 8, 12, 1}, 9250 {114, 92, 10, 12, 1}, 9251 {116, 93, 0, 12, 1}, 9252 {118, 93, 2, 12, 1}, 9253 {120, 93, 4, 12, 1}, 9254 {122, 93, 6, 12, 1}, 9255 {124, 93, 8, 12, 1}, 9256 {126, 93, 10, 12, 1}, 9257 {128, 94, 0, 12, 1}, 9258 {130, 94, 2, 12, 1}, 9259 {132, 94, 4, 12, 1}, 9260 {134, 94, 6, 12, 1}, 9261 {136, 94, 8, 12, 1}, 9262 {138, 94, 10, 12, 1}, 9263 {140, 95, 0, 12, 1}, 9264 {149, 95, 9, 12, 1}, 9265 {151, 95, 11, 12, 1}, 9266 {153, 96, 1, 12, 1}, 9267 {155, 96, 3, 12, 1}, 9268 {157, 96, 5, 12, 1}, 9269 {159, 96, 7, 12, 1}, 9270 {161, 96, 9, 12, 1}, 9271 {165, 97, 1, 12, 1}, 9272 {184, 82, 0, 12, 1}, 9273 {188, 82, 4, 12, 1}, 9274 {192, 82, 8, 12, 1}, 9275 {196, 83, 0, 12, 1}, 9276 }; 9277 9278 static const struct rf_channel rf_vals_7620[] = { 9279 {1, 0x50, 0x99, 0x99, 1}, 9280 {2, 0x50, 0x44, 0x44, 2}, 9281 {3, 0x50, 0xEE, 0xEE, 2}, 9282 {4, 0x50, 0x99, 0x99, 3}, 9283 {5, 0x51, 0x44, 0x44, 0}, 9284 {6, 0x51, 0xEE, 0xEE, 0}, 9285 {7, 0x51, 0x99, 0x99, 1}, 9286 {8, 0x51, 0x44, 0x44, 2}, 9287 {9, 0x51, 0xEE, 0xEE, 2}, 9288 {10, 0x51, 0x99, 0x99, 3}, 9289 {11, 0x52, 0x44, 0x44, 0}, 9290 {12, 0x52, 0xEE, 0xEE, 0}, 9291 {13, 0x52, 0x99, 0x99, 1}, 9292 {14, 0x52, 0x33, 0x33, 3}, 9293 }; 9294 9295 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 9296 { 9297 struct hw_mode_spec *spec = &rt2x00dev->spec; 9298 struct channel_info *info; 9299 char *default_power1; 9300 char *default_power2; 9301 char *default_power3; 9302 unsigned int i, tx_chains, rx_chains; 9303 u32 reg; 9304 9305 /* 9306 * Disable powersaving as default. 9307 */ 9308 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 9309 9310 /* 9311 * Change default retry settings to values corresponding more closely 9312 * to rate[0].count setting of minstrel rate control algorithm. 9313 */ 9314 rt2x00dev->hw->wiphy->retry_short = 2; 9315 rt2x00dev->hw->wiphy->retry_long = 2; 9316 9317 /* 9318 * Initialize all hw fields. 9319 */ 9320 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS); 9321 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION); 9322 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); 9323 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); 9324 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); 9325 9326 /* 9327 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices 9328 * unless we are capable of sending the buffered frames out after the 9329 * DTIM transmission using rt2x00lib_beacondone. This will send out 9330 * multicast and broadcast traffic immediately instead of buffering it 9331 * infinitly and thus dropping it after some time. 9332 */ 9333 if (!rt2x00_is_usb(rt2x00dev)) 9334 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); 9335 9336 /* Set MFP if HW crypto is disabled. */ 9337 if (rt2800_hwcrypt_disabled(rt2x00dev)) 9338 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE); 9339 9340 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 9341 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 9342 rt2800_eeprom_addr(rt2x00dev, 9343 EEPROM_MAC_ADDR_0)); 9344 9345 /* 9346 * As rt2800 has a global fallback table we cannot specify 9347 * more then one tx rate per frame but since the hw will 9348 * try several rates (based on the fallback table) we should 9349 * initialize max_report_rates to the maximum number of rates 9350 * we are going to try. Otherwise mac80211 will truncate our 9351 * reported tx rates and the rc algortihm will end up with 9352 * incorrect data. 9353 */ 9354 rt2x00dev->hw->max_rates = 1; 9355 rt2x00dev->hw->max_report_rates = 7; 9356 rt2x00dev->hw->max_rate_tries = 1; 9357 9358 /* 9359 * Initialize hw_mode information. 9360 */ 9361 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 9362 9363 switch (rt2x00dev->chip.rf) { 9364 case RF2720: 9365 case RF2820: 9366 spec->num_channels = 14; 9367 spec->channels = rf_vals; 9368 break; 9369 9370 case RF2750: 9371 case RF2850: 9372 spec->num_channels = ARRAY_SIZE(rf_vals); 9373 spec->channels = rf_vals; 9374 break; 9375 9376 case RF2020: 9377 case RF3020: 9378 case RF3021: 9379 case RF3022: 9380 case RF3070: 9381 case RF3290: 9382 case RF3320: 9383 case RF3322: 9384 case RF5350: 9385 case RF5360: 9386 case RF5362: 9387 case RF5370: 9388 case RF5372: 9389 case RF5390: 9390 case RF5392: 9391 spec->num_channels = 14; 9392 if (rt2800_clk_is_20mhz(rt2x00dev)) 9393 spec->channels = rf_vals_3x_xtal20; 9394 else 9395 spec->channels = rf_vals_3x; 9396 break; 9397 9398 case RF7620: 9399 spec->num_channels = ARRAY_SIZE(rf_vals_7620); 9400 spec->channels = rf_vals_7620; 9401 break; 9402 9403 case RF3052: 9404 case RF3053: 9405 spec->num_channels = ARRAY_SIZE(rf_vals_3x); 9406 spec->channels = rf_vals_3x; 9407 break; 9408 9409 case RF5592: 9410 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX); 9411 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { 9412 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); 9413 spec->channels = rf_vals_5592_xtal40; 9414 } else { 9415 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20); 9416 spec->channels = rf_vals_5592_xtal20; 9417 } 9418 break; 9419 } 9420 9421 if (WARN_ON_ONCE(!spec->channels)) 9422 return -ENODEV; 9423 9424 spec->supported_bands = SUPPORT_BAND_2GHZ; 9425 if (spec->num_channels > 14) 9426 spec->supported_bands |= SUPPORT_BAND_5GHZ; 9427 9428 /* 9429 * Initialize HT information. 9430 */ 9431 if (!rt2x00_rf(rt2x00dev, RF2020)) 9432 spec->ht.ht_supported = true; 9433 else 9434 spec->ht.ht_supported = false; 9435 9436 spec->ht.cap = 9437 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 9438 IEEE80211_HT_CAP_GRN_FLD | 9439 IEEE80211_HT_CAP_SGI_20 | 9440 IEEE80211_HT_CAP_SGI_40; 9441 9442 tx_chains = rt2x00dev->default_ant.tx_chain_num; 9443 rx_chains = rt2x00dev->default_ant.rx_chain_num; 9444 9445 if (tx_chains >= 2) 9446 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; 9447 9448 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT; 9449 9450 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2; 9451 spec->ht.ampdu_density = 4; 9452 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 9453 if (tx_chains != rx_chains) { 9454 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 9455 spec->ht.mcs.tx_params |= 9456 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; 9457 } 9458 9459 switch (rx_chains) { 9460 case 3: 9461 spec->ht.mcs.rx_mask[2] = 0xff; 9462 /* fall through */ 9463 case 2: 9464 spec->ht.mcs.rx_mask[1] = 0xff; 9465 /* fall through */ 9466 case 1: 9467 spec->ht.mcs.rx_mask[0] = 0xff; 9468 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ 9469 break; 9470 } 9471 9472 /* 9473 * Create channel information array 9474 */ 9475 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 9476 if (!info) 9477 return -ENOMEM; 9478 9479 spec->channels_info = info; 9480 9481 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 9482 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 9483 9484 if (rt2x00dev->default_ant.tx_chain_num > 2) 9485 default_power3 = rt2800_eeprom_addr(rt2x00dev, 9486 EEPROM_EXT_TXPOWER_BG3); 9487 else 9488 default_power3 = NULL; 9489 9490 for (i = 0; i < 14; i++) { 9491 info[i].default_power1 = default_power1[i]; 9492 info[i].default_power2 = default_power2[i]; 9493 if (default_power3) 9494 info[i].default_power3 = default_power3[i]; 9495 } 9496 9497 if (spec->num_channels > 14) { 9498 default_power1 = rt2800_eeprom_addr(rt2x00dev, 9499 EEPROM_TXPOWER_A1); 9500 default_power2 = rt2800_eeprom_addr(rt2x00dev, 9501 EEPROM_TXPOWER_A2); 9502 9503 if (rt2x00dev->default_ant.tx_chain_num > 2) 9504 default_power3 = 9505 rt2800_eeprom_addr(rt2x00dev, 9506 EEPROM_EXT_TXPOWER_A3); 9507 else 9508 default_power3 = NULL; 9509 9510 for (i = 14; i < spec->num_channels; i++) { 9511 info[i].default_power1 = default_power1[i - 14]; 9512 info[i].default_power2 = default_power2[i - 14]; 9513 if (default_power3) 9514 info[i].default_power3 = default_power3[i - 14]; 9515 } 9516 } 9517 9518 switch (rt2x00dev->chip.rf) { 9519 case RF2020: 9520 case RF3020: 9521 case RF3021: 9522 case RF3022: 9523 case RF3320: 9524 case RF3052: 9525 case RF3053: 9526 case RF3070: 9527 case RF3290: 9528 case RF5350: 9529 case RF5360: 9530 case RF5362: 9531 case RF5370: 9532 case RF5372: 9533 case RF5390: 9534 case RF5392: 9535 case RF5592: 9536 case RF7620: 9537 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags); 9538 break; 9539 } 9540 9541 return 0; 9542 } 9543 9544 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) 9545 { 9546 u32 reg; 9547 u32 rt; 9548 u32 rev; 9549 9550 if (rt2x00_rt(rt2x00dev, RT3290)) 9551 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290); 9552 else 9553 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 9554 9555 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); 9556 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); 9557 9558 switch (rt) { 9559 case RT2860: 9560 case RT2872: 9561 case RT2883: 9562 case RT3070: 9563 case RT3071: 9564 case RT3090: 9565 case RT3290: 9566 case RT3352: 9567 case RT3390: 9568 case RT3572: 9569 case RT3593: 9570 case RT5350: 9571 case RT5390: 9572 case RT5392: 9573 case RT5592: 9574 break; 9575 default: 9576 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n", 9577 rt, rev); 9578 return -ENODEV; 9579 } 9580 9581 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev)) 9582 rt = RT6352; 9583 9584 rt2x00_set_rt(rt2x00dev, rt, rev); 9585 9586 return 0; 9587 } 9588 9589 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) 9590 { 9591 int retval; 9592 u32 reg; 9593 9594 retval = rt2800_probe_rt(rt2x00dev); 9595 if (retval) 9596 return retval; 9597 9598 /* 9599 * Allocate eeprom data. 9600 */ 9601 retval = rt2800_validate_eeprom(rt2x00dev); 9602 if (retval) 9603 return retval; 9604 9605 retval = rt2800_init_eeprom(rt2x00dev); 9606 if (retval) 9607 return retval; 9608 9609 /* 9610 * Enable rfkill polling by setting GPIO direction of the 9611 * rfkill switch GPIO pin correctly. 9612 */ 9613 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 9614 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); 9615 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 9616 9617 /* 9618 * Initialize hw specifications. 9619 */ 9620 retval = rt2800_probe_hw_mode(rt2x00dev); 9621 if (retval) 9622 return retval; 9623 9624 /* 9625 * Set device capabilities. 9626 */ 9627 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); 9628 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags); 9629 if (!rt2x00_is_usb(rt2x00dev)) 9630 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags); 9631 9632 /* 9633 * Set device requirements. 9634 */ 9635 if (!rt2x00_is_soc(rt2x00dev)) 9636 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); 9637 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags); 9638 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags); 9639 if (!rt2800_hwcrypt_disabled(rt2x00dev)) 9640 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); 9641 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 9642 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags); 9643 if (rt2x00_is_usb(rt2x00dev)) 9644 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); 9645 else { 9646 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); 9647 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags); 9648 } 9649 9650 /* 9651 * Set the rssi offset. 9652 */ 9653 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 9654 9655 return 0; 9656 } 9657 EXPORT_SYMBOL_GPL(rt2800_probe_hw); 9658 9659 /* 9660 * IEEE80211 stack callback functions. 9661 */ 9662 void rt2800_get_key_seq(struct ieee80211_hw *hw, 9663 struct ieee80211_key_conf *key, 9664 struct ieee80211_key_seq *seq) 9665 { 9666 struct rt2x00_dev *rt2x00dev = hw->priv; 9667 struct mac_iveiv_entry iveiv_entry; 9668 u32 offset; 9669 9670 if (key->cipher != WLAN_CIPHER_SUITE_TKIP) 9671 return; 9672 9673 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 9674 rt2800_register_multiread(rt2x00dev, offset, 9675 &iveiv_entry, sizeof(iveiv_entry)); 9676 9677 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2); 9678 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4); 9679 } 9680 EXPORT_SYMBOL_GPL(rt2800_get_key_seq); 9681 9682 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) 9683 { 9684 struct rt2x00_dev *rt2x00dev = hw->priv; 9685 u32 reg; 9686 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); 9687 9688 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 9689 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); 9690 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 9691 9692 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 9693 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); 9694 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 9695 9696 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 9697 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); 9698 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 9699 9700 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 9701 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); 9702 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 9703 9704 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 9705 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); 9706 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 9707 9708 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 9709 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); 9710 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 9711 9712 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 9713 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); 9714 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 9715 9716 return 0; 9717 } 9718 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold); 9719 9720 int rt2800_conf_tx(struct ieee80211_hw *hw, 9721 struct ieee80211_vif *vif, u16 queue_idx, 9722 const struct ieee80211_tx_queue_params *params) 9723 { 9724 struct rt2x00_dev *rt2x00dev = hw->priv; 9725 struct data_queue *queue; 9726 struct rt2x00_field32 field; 9727 int retval; 9728 u32 reg; 9729 u32 offset; 9730 9731 /* 9732 * First pass the configuration through rt2x00lib, that will 9733 * update the queue settings and validate the input. After that 9734 * we are free to update the registers based on the value 9735 * in the queue parameter. 9736 */ 9737 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params); 9738 if (retval) 9739 return retval; 9740 9741 /* 9742 * We only need to perform additional register initialization 9743 * for WMM queues/ 9744 */ 9745 if (queue_idx >= 4) 9746 return 0; 9747 9748 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 9749 9750 /* Update WMM TXOP register */ 9751 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); 9752 field.bit_offset = (queue_idx & 1) * 16; 9753 field.bit_mask = 0xffff << field.bit_offset; 9754 9755 reg = rt2800_register_read(rt2x00dev, offset); 9756 rt2x00_set_field32(®, field, queue->txop); 9757 rt2800_register_write(rt2x00dev, offset, reg); 9758 9759 /* Update WMM registers */ 9760 field.bit_offset = queue_idx * 4; 9761 field.bit_mask = 0xf << field.bit_offset; 9762 9763 reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG); 9764 rt2x00_set_field32(®, field, queue->aifs); 9765 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); 9766 9767 reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG); 9768 rt2x00_set_field32(®, field, queue->cw_min); 9769 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); 9770 9771 reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG); 9772 rt2x00_set_field32(®, field, queue->cw_max); 9773 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); 9774 9775 /* Update EDCA registers */ 9776 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); 9777 9778 reg = rt2800_register_read(rt2x00dev, offset); 9779 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); 9780 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); 9781 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); 9782 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); 9783 rt2800_register_write(rt2x00dev, offset, reg); 9784 9785 return 0; 9786 } 9787 EXPORT_SYMBOL_GPL(rt2800_conf_tx); 9788 9789 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 9790 { 9791 struct rt2x00_dev *rt2x00dev = hw->priv; 9792 u64 tsf; 9793 u32 reg; 9794 9795 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1); 9796 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; 9797 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0); 9798 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); 9799 9800 return tsf; 9801 } 9802 EXPORT_SYMBOL_GPL(rt2800_get_tsf); 9803 9804 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 9805 struct ieee80211_ampdu_params *params) 9806 { 9807 struct ieee80211_sta *sta = params->sta; 9808 enum ieee80211_ampdu_mlme_action action = params->action; 9809 u16 tid = params->tid; 9810 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv; 9811 int ret = 0; 9812 9813 /* 9814 * Don't allow aggregation for stations the hardware isn't aware 9815 * of because tx status reports for frames to an unknown station 9816 * always contain wcid=WCID_END+1 and thus we can't distinguish 9817 * between multiple stations which leads to unwanted situations 9818 * when the hw reorders frames due to aggregation. 9819 */ 9820 if (sta_priv->wcid > WCID_END) 9821 return 1; 9822 9823 switch (action) { 9824 case IEEE80211_AMPDU_RX_START: 9825 case IEEE80211_AMPDU_RX_STOP: 9826 /* 9827 * The hw itself takes care of setting up BlockAck mechanisms. 9828 * So, we only have to allow mac80211 to nagotiate a BlockAck 9829 * agreement. Once that is done, the hw will BlockAck incoming 9830 * AMPDUs without further setup. 9831 */ 9832 break; 9833 case IEEE80211_AMPDU_TX_START: 9834 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 9835 break; 9836 case IEEE80211_AMPDU_TX_STOP_CONT: 9837 case IEEE80211_AMPDU_TX_STOP_FLUSH: 9838 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 9839 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 9840 break; 9841 case IEEE80211_AMPDU_TX_OPERATIONAL: 9842 break; 9843 default: 9844 rt2x00_warn((struct rt2x00_dev *)hw->priv, 9845 "Unknown AMPDU action\n"); 9846 } 9847 9848 return ret; 9849 } 9850 EXPORT_SYMBOL_GPL(rt2800_ampdu_action); 9851 9852 int rt2800_get_survey(struct ieee80211_hw *hw, int idx, 9853 struct survey_info *survey) 9854 { 9855 struct rt2x00_dev *rt2x00dev = hw->priv; 9856 struct ieee80211_conf *conf = &hw->conf; 9857 u32 idle, busy, busy_ext; 9858 9859 if (idx != 0) 9860 return -ENOENT; 9861 9862 survey->channel = conf->chandef.chan; 9863 9864 idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 9865 busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 9866 busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 9867 9868 if (idle || busy) { 9869 survey->filled = SURVEY_INFO_TIME | 9870 SURVEY_INFO_TIME_BUSY | 9871 SURVEY_INFO_TIME_EXT_BUSY; 9872 9873 survey->time = (idle + busy) / 1000; 9874 survey->time_busy = busy / 1000; 9875 survey->time_ext_busy = busy_ext / 1000; 9876 } 9877 9878 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 9879 survey->filled |= SURVEY_INFO_IN_USE; 9880 9881 return 0; 9882 9883 } 9884 EXPORT_SYMBOL_GPL(rt2800_get_survey); 9885 9886 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); 9887 MODULE_VERSION(DRV_VERSION); 9888 MODULE_DESCRIPTION("Ralink RT2800 library"); 9889 MODULE_LICENSE("GPL"); 9890