1 /* 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> 6 7 Based on the original rt2800pci.c and rt2800usb.c. 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 14 <http://rt2x00.serialmonkey.com> 15 16 This program is free software; you can redistribute it and/or modify 17 it under the terms of the GNU General Public License as published by 18 the Free Software Foundation; either version 2 of the License, or 19 (at your option) any later version. 20 21 This program is distributed in the hope that it will be useful, 22 but WITHOUT ANY WARRANTY; without even the implied warranty of 23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 GNU General Public License for more details. 25 26 You should have received a copy of the GNU General Public License 27 along with this program; if not, see <http://www.gnu.org/licenses/>. 28 */ 29 30 /* 31 Module: rt2800lib 32 Abstract: rt2800 generic device routines. 33 */ 34 35 #include <linux/crc-ccitt.h> 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/slab.h> 39 40 #include "rt2x00.h" 41 #include "rt2800lib.h" 42 #include "rt2800.h" 43 44 /* 45 * Register access. 46 * All access to the CSR registers will go through the methods 47 * rt2800_register_read and rt2800_register_write. 48 * BBP and RF register require indirect register access, 49 * and use the CSR registers BBPCSR and RFCSR to achieve this. 50 * These indirect registers work with busy bits, 51 * and we will try maximal REGISTER_BUSY_COUNT times to access 52 * the register while taking a REGISTER_BUSY_DELAY us delay 53 * between each attampt. When the busy bit is still set at that time, 54 * the access attempt is considered to have failed, 55 * and we will print an error. 56 * The _lock versions must be used if you already hold the csr_mutex 57 */ 58 #define WAIT_FOR_BBP(__dev, __reg) \ 59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) 60 #define WAIT_FOR_RFCSR(__dev, __reg) \ 61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) 62 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \ 63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \ 64 (__reg)) 65 #define WAIT_FOR_RF(__dev, __reg) \ 66 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) 67 #define WAIT_FOR_MCU(__dev, __reg) \ 68 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 69 H2M_MAILBOX_CSR_OWNER, (__reg)) 70 71 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) 72 { 73 /* check for rt2872 on SoC */ 74 if (!rt2x00_is_soc(rt2x00dev) || 75 !rt2x00_rt(rt2x00dev, RT2872)) 76 return false; 77 78 /* we know for sure that these rf chipsets are used on rt305x boards */ 79 if (rt2x00_rf(rt2x00dev, RF3020) || 80 rt2x00_rf(rt2x00dev, RF3021) || 81 rt2x00_rf(rt2x00dev, RF3022)) 82 return true; 83 84 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n"); 85 return false; 86 } 87 88 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, 89 const unsigned int word, const u8 value) 90 { 91 u32 reg; 92 93 mutex_lock(&rt2x00dev->csr_mutex); 94 95 /* 96 * Wait until the BBP becomes available, afterwards we 97 * can safely write the new data into the register. 98 */ 99 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 100 reg = 0; 101 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); 102 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 103 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 104 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); 105 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 106 107 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 108 } 109 110 mutex_unlock(&rt2x00dev->csr_mutex); 111 } 112 113 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word) 114 { 115 u32 reg; 116 u8 value; 117 118 mutex_lock(&rt2x00dev->csr_mutex); 119 120 /* 121 * Wait until the BBP becomes available, afterwards we 122 * can safely write the read request into the register. 123 * After the data has been written, we wait until hardware 124 * returns the correct value, if at any time the register 125 * doesn't become available in time, reg will be 0xffffffff 126 * which means we return 0xff to the caller. 127 */ 128 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 129 reg = 0; 130 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 131 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 132 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); 133 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 134 135 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 136 137 WAIT_FOR_BBP(rt2x00dev, ®); 138 } 139 140 value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); 141 142 mutex_unlock(&rt2x00dev->csr_mutex); 143 144 return value; 145 } 146 147 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, 148 const unsigned int word, const u8 value) 149 { 150 u32 reg; 151 152 mutex_lock(&rt2x00dev->csr_mutex); 153 154 /* 155 * Wait until the RFCSR becomes available, afterwards we 156 * can safely write the new data into the register. 157 */ 158 switch (rt2x00dev->chip.rt) { 159 case RT6352: 160 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 161 reg = 0; 162 rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value); 163 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 164 word); 165 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1); 166 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 167 168 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 169 } 170 break; 171 172 default: 173 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 174 reg = 0; 175 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); 176 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 177 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); 178 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 179 180 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 181 } 182 break; 183 } 184 185 mutex_unlock(&rt2x00dev->csr_mutex); 186 } 187 188 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 189 const unsigned int reg, const u8 value) 190 { 191 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value); 192 } 193 194 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev, 195 const unsigned int reg, const u8 value) 196 { 197 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value); 198 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value); 199 } 200 201 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev, 202 const unsigned int reg, const u8 value) 203 { 204 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value); 205 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value); 206 } 207 208 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, 209 const unsigned int word) 210 { 211 u32 reg; 212 u8 value; 213 214 mutex_lock(&rt2x00dev->csr_mutex); 215 216 /* 217 * Wait until the RFCSR becomes available, afterwards we 218 * can safely write the read request into the register. 219 * After the data has been written, we wait until hardware 220 * returns the correct value, if at any time the register 221 * doesn't become available in time, reg will be 0xffffffff 222 * which means we return 0xff to the caller. 223 */ 224 switch (rt2x00dev->chip.rt) { 225 case RT6352: 226 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 227 reg = 0; 228 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 229 word); 230 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0); 231 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 232 233 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 234 235 WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®); 236 } 237 238 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620); 239 break; 240 241 default: 242 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 243 reg = 0; 244 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 245 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); 246 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 247 248 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 249 250 WAIT_FOR_RFCSR(rt2x00dev, ®); 251 } 252 253 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); 254 break; 255 } 256 257 mutex_unlock(&rt2x00dev->csr_mutex); 258 259 return value; 260 } 261 262 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 263 const unsigned int reg) 264 { 265 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6))); 266 } 267 268 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, 269 const unsigned int word, const u32 value) 270 { 271 u32 reg; 272 273 mutex_lock(&rt2x00dev->csr_mutex); 274 275 /* 276 * Wait until the RF becomes available, afterwards we 277 * can safely write the new data into the register. 278 */ 279 if (WAIT_FOR_RF(rt2x00dev, ®)) { 280 reg = 0; 281 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); 282 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); 283 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); 284 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); 285 286 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); 287 rt2x00_rf_write(rt2x00dev, word, value); 288 } 289 290 mutex_unlock(&rt2x00dev->csr_mutex); 291 } 292 293 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { 294 [EEPROM_CHIP_ID] = 0x0000, 295 [EEPROM_VERSION] = 0x0001, 296 [EEPROM_MAC_ADDR_0] = 0x0002, 297 [EEPROM_MAC_ADDR_1] = 0x0003, 298 [EEPROM_MAC_ADDR_2] = 0x0004, 299 [EEPROM_NIC_CONF0] = 0x001a, 300 [EEPROM_NIC_CONF1] = 0x001b, 301 [EEPROM_FREQ] = 0x001d, 302 [EEPROM_LED_AG_CONF] = 0x001e, 303 [EEPROM_LED_ACT_CONF] = 0x001f, 304 [EEPROM_LED_POLARITY] = 0x0020, 305 [EEPROM_NIC_CONF2] = 0x0021, 306 [EEPROM_LNA] = 0x0022, 307 [EEPROM_RSSI_BG] = 0x0023, 308 [EEPROM_RSSI_BG2] = 0x0024, 309 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */ 310 [EEPROM_RSSI_A] = 0x0025, 311 [EEPROM_RSSI_A2] = 0x0026, 312 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */ 313 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027, 314 [EEPROM_TXPOWER_DELTA] = 0x0028, 315 [EEPROM_TXPOWER_BG1] = 0x0029, 316 [EEPROM_TXPOWER_BG2] = 0x0030, 317 [EEPROM_TSSI_BOUND_BG1] = 0x0037, 318 [EEPROM_TSSI_BOUND_BG2] = 0x0038, 319 [EEPROM_TSSI_BOUND_BG3] = 0x0039, 320 [EEPROM_TSSI_BOUND_BG4] = 0x003a, 321 [EEPROM_TSSI_BOUND_BG5] = 0x003b, 322 [EEPROM_TXPOWER_A1] = 0x003c, 323 [EEPROM_TXPOWER_A2] = 0x0053, 324 [EEPROM_TXPOWER_INIT] = 0x0068, 325 [EEPROM_TSSI_BOUND_A1] = 0x006a, 326 [EEPROM_TSSI_BOUND_A2] = 0x006b, 327 [EEPROM_TSSI_BOUND_A3] = 0x006c, 328 [EEPROM_TSSI_BOUND_A4] = 0x006d, 329 [EEPROM_TSSI_BOUND_A5] = 0x006e, 330 [EEPROM_TXPOWER_BYRATE] = 0x006f, 331 [EEPROM_BBP_START] = 0x0078, 332 }; 333 334 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = { 335 [EEPROM_CHIP_ID] = 0x0000, 336 [EEPROM_VERSION] = 0x0001, 337 [EEPROM_MAC_ADDR_0] = 0x0002, 338 [EEPROM_MAC_ADDR_1] = 0x0003, 339 [EEPROM_MAC_ADDR_2] = 0x0004, 340 [EEPROM_NIC_CONF0] = 0x001a, 341 [EEPROM_NIC_CONF1] = 0x001b, 342 [EEPROM_NIC_CONF2] = 0x001c, 343 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020, 344 [EEPROM_FREQ] = 0x0022, 345 [EEPROM_LED_AG_CONF] = 0x0023, 346 [EEPROM_LED_ACT_CONF] = 0x0024, 347 [EEPROM_LED_POLARITY] = 0x0025, 348 [EEPROM_LNA] = 0x0026, 349 [EEPROM_EXT_LNA2] = 0x0027, 350 [EEPROM_RSSI_BG] = 0x0028, 351 [EEPROM_RSSI_BG2] = 0x0029, 352 [EEPROM_RSSI_A] = 0x002a, 353 [EEPROM_RSSI_A2] = 0x002b, 354 [EEPROM_TXPOWER_BG1] = 0x0030, 355 [EEPROM_TXPOWER_BG2] = 0x0037, 356 [EEPROM_EXT_TXPOWER_BG3] = 0x003e, 357 [EEPROM_TSSI_BOUND_BG1] = 0x0045, 358 [EEPROM_TSSI_BOUND_BG2] = 0x0046, 359 [EEPROM_TSSI_BOUND_BG3] = 0x0047, 360 [EEPROM_TSSI_BOUND_BG4] = 0x0048, 361 [EEPROM_TSSI_BOUND_BG5] = 0x0049, 362 [EEPROM_TXPOWER_A1] = 0x004b, 363 [EEPROM_TXPOWER_A2] = 0x0065, 364 [EEPROM_EXT_TXPOWER_A3] = 0x007f, 365 [EEPROM_TSSI_BOUND_A1] = 0x009a, 366 [EEPROM_TSSI_BOUND_A2] = 0x009b, 367 [EEPROM_TSSI_BOUND_A3] = 0x009c, 368 [EEPROM_TSSI_BOUND_A4] = 0x009d, 369 [EEPROM_TSSI_BOUND_A5] = 0x009e, 370 [EEPROM_TXPOWER_BYRATE] = 0x00a0, 371 }; 372 373 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev, 374 const enum rt2800_eeprom_word word) 375 { 376 const unsigned int *map; 377 unsigned int index; 378 379 if (WARN_ONCE(word >= EEPROM_WORD_COUNT, 380 "%s: invalid EEPROM word %d\n", 381 wiphy_name(rt2x00dev->hw->wiphy), word)) 382 return 0; 383 384 if (rt2x00_rt(rt2x00dev, RT3593)) 385 map = rt2800_eeprom_map_ext; 386 else 387 map = rt2800_eeprom_map; 388 389 index = map[word]; 390 391 /* Index 0 is valid only for EEPROM_CHIP_ID. 392 * Otherwise it means that the offset of the 393 * given word is not initialized in the map, 394 * or that the field is not usable on the 395 * actual chipset. 396 */ 397 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0, 398 "%s: invalid access of EEPROM word %d\n", 399 wiphy_name(rt2x00dev->hw->wiphy), word); 400 401 return index; 402 } 403 404 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev, 405 const enum rt2800_eeprom_word word) 406 { 407 unsigned int index; 408 409 index = rt2800_eeprom_word_index(rt2x00dev, word); 410 return rt2x00_eeprom_addr(rt2x00dev, index); 411 } 412 413 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, 414 const enum rt2800_eeprom_word word) 415 { 416 unsigned int index; 417 418 index = rt2800_eeprom_word_index(rt2x00dev, word); 419 return rt2x00_eeprom_read(rt2x00dev, index); 420 } 421 422 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, 423 const enum rt2800_eeprom_word word, u16 data) 424 { 425 unsigned int index; 426 427 index = rt2800_eeprom_word_index(rt2x00dev, word); 428 rt2x00_eeprom_write(rt2x00dev, index, data); 429 } 430 431 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, 432 const enum rt2800_eeprom_word array, 433 unsigned int offset) 434 { 435 unsigned int index; 436 437 index = rt2800_eeprom_word_index(rt2x00dev, array); 438 return rt2x00_eeprom_read(rt2x00dev, index + offset); 439 } 440 441 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) 442 { 443 u32 reg; 444 int i, count; 445 446 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 447 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); 448 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); 449 rt2x00_set_field32(®, WLAN_CLK_EN, 0); 450 rt2x00_set_field32(®, WLAN_EN, 1); 451 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 452 453 udelay(REGISTER_BUSY_DELAY); 454 455 count = 0; 456 do { 457 /* 458 * Check PLL_LD & XTAL_RDY. 459 */ 460 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 461 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 462 if (rt2x00_get_field32(reg, PLL_LD) && 463 rt2x00_get_field32(reg, XTAL_RDY)) 464 break; 465 udelay(REGISTER_BUSY_DELAY); 466 } 467 468 if (i >= REGISTER_BUSY_COUNT) { 469 470 if (count >= 10) 471 return -EIO; 472 473 rt2800_register_write(rt2x00dev, 0x58, 0x018); 474 udelay(REGISTER_BUSY_DELAY); 475 rt2800_register_write(rt2x00dev, 0x58, 0x418); 476 udelay(REGISTER_BUSY_DELAY); 477 rt2800_register_write(rt2x00dev, 0x58, 0x618); 478 udelay(REGISTER_BUSY_DELAY); 479 count++; 480 } else { 481 count = 0; 482 } 483 484 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 485 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); 486 rt2x00_set_field32(®, WLAN_CLK_EN, 1); 487 rt2x00_set_field32(®, WLAN_RESET, 1); 488 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 489 udelay(10); 490 rt2x00_set_field32(®, WLAN_RESET, 0); 491 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 492 udelay(10); 493 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff); 494 } while (count != 0); 495 496 return 0; 497 } 498 499 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 500 const u8 command, const u8 token, 501 const u8 arg0, const u8 arg1) 502 { 503 u32 reg; 504 505 /* 506 * SOC devices don't support MCU requests. 507 */ 508 if (rt2x00_is_soc(rt2x00dev)) 509 return; 510 511 mutex_lock(&rt2x00dev->csr_mutex); 512 513 /* 514 * Wait until the MCU becomes available, afterwards we 515 * can safely write the new data into the register. 516 */ 517 if (WAIT_FOR_MCU(rt2x00dev, ®)) { 518 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); 519 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); 520 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); 521 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); 522 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); 523 524 reg = 0; 525 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); 526 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); 527 } 528 529 mutex_unlock(&rt2x00dev->csr_mutex); 530 } 531 EXPORT_SYMBOL_GPL(rt2800_mcu_request); 532 533 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) 534 { 535 unsigned int i = 0; 536 u32 reg; 537 538 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 539 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 540 if (reg && reg != ~0) 541 return 0; 542 msleep(1); 543 } 544 545 rt2x00_err(rt2x00dev, "Unstable hardware\n"); 546 return -EBUSY; 547 } 548 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); 549 550 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 551 { 552 unsigned int i; 553 u32 reg; 554 555 /* 556 * Some devices are really slow to respond here. Wait a whole second 557 * before timing out. 558 */ 559 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 560 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 561 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 562 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 563 return 0; 564 565 msleep(10); 566 } 567 568 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); 569 return -EACCES; 570 } 571 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); 572 573 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) 574 { 575 u32 reg; 576 577 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 578 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 579 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 580 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 581 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 582 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 583 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 584 } 585 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma); 586 587 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev, 588 unsigned short *txwi_size, 589 unsigned short *rxwi_size) 590 { 591 switch (rt2x00dev->chip.rt) { 592 case RT3593: 593 *txwi_size = TXWI_DESC_SIZE_4WORDS; 594 *rxwi_size = RXWI_DESC_SIZE_5WORDS; 595 break; 596 597 case RT5592: 598 case RT6352: 599 *txwi_size = TXWI_DESC_SIZE_5WORDS; 600 *rxwi_size = RXWI_DESC_SIZE_6WORDS; 601 break; 602 603 default: 604 *txwi_size = TXWI_DESC_SIZE_4WORDS; 605 *rxwi_size = RXWI_DESC_SIZE_4WORDS; 606 break; 607 } 608 } 609 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size); 610 611 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) 612 { 613 u16 fw_crc; 614 u16 crc; 615 616 /* 617 * The last 2 bytes in the firmware array are the crc checksum itself, 618 * this means that we should never pass those 2 bytes to the crc 619 * algorithm. 620 */ 621 fw_crc = (data[len - 2] << 8 | data[len - 1]); 622 623 /* 624 * Use the crc ccitt algorithm. 625 * This will return the same value as the legacy driver which 626 * used bit ordering reversion on the both the firmware bytes 627 * before input input as well as on the final output. 628 * Obviously using crc ccitt directly is much more efficient. 629 */ 630 crc = crc_ccitt(~0, data, len - 2); 631 632 /* 633 * There is a small difference between the crc-itu-t + bitrev and 634 * the crc-ccitt crc calculation. In the latter method the 2 bytes 635 * will be swapped, use swab16 to convert the crc to the correct 636 * value. 637 */ 638 crc = swab16(crc); 639 640 return fw_crc == crc; 641 } 642 643 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, 644 const u8 *data, const size_t len) 645 { 646 size_t offset = 0; 647 size_t fw_len; 648 bool multiple; 649 650 /* 651 * PCI(e) & SOC devices require firmware with a length 652 * of 8kb. USB devices require firmware files with a length 653 * of 4kb. Certain USB chipsets however require different firmware, 654 * which Ralink only provides attached to the original firmware 655 * file. Thus for USB devices, firmware files have a length 656 * which is a multiple of 4kb. The firmware for rt3290 chip also 657 * have a length which is a multiple of 4kb. 658 */ 659 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290)) 660 fw_len = 4096; 661 else 662 fw_len = 8192; 663 664 multiple = true; 665 /* 666 * Validate the firmware length 667 */ 668 if (len != fw_len && (!multiple || (len % fw_len) != 0)) 669 return FW_BAD_LENGTH; 670 671 /* 672 * Check if the chipset requires one of the upper parts 673 * of the firmware. 674 */ 675 if (rt2x00_is_usb(rt2x00dev) && 676 !rt2x00_rt(rt2x00dev, RT2860) && 677 !rt2x00_rt(rt2x00dev, RT2872) && 678 !rt2x00_rt(rt2x00dev, RT3070) && 679 ((len / fw_len) == 1)) 680 return FW_BAD_VERSION; 681 682 /* 683 * 8kb firmware files must be checked as if it were 684 * 2 separate firmware files. 685 */ 686 while (offset < len) { 687 if (!rt2800_check_firmware_crc(data + offset, fw_len)) 688 return FW_BAD_CRC; 689 690 offset += fw_len; 691 } 692 693 return FW_OK; 694 } 695 EXPORT_SYMBOL_GPL(rt2800_check_firmware); 696 697 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, 698 const u8 *data, const size_t len) 699 { 700 unsigned int i; 701 u32 reg; 702 int retval; 703 704 if (rt2x00_rt(rt2x00dev, RT3290)) { 705 retval = rt2800_enable_wlan_rt3290(rt2x00dev); 706 if (retval) 707 return -EBUSY; 708 } 709 710 /* 711 * If driver doesn't wake up firmware here, 712 * rt2800_load_firmware will hang forever when interface is up again. 713 */ 714 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 715 716 /* 717 * Wait for stable hardware. 718 */ 719 if (rt2800_wait_csr_ready(rt2x00dev)) 720 return -EBUSY; 721 722 if (rt2x00_is_pci(rt2x00dev)) { 723 if (rt2x00_rt(rt2x00dev, RT3290) || 724 rt2x00_rt(rt2x00dev, RT3572) || 725 rt2x00_rt(rt2x00dev, RT5390) || 726 rt2x00_rt(rt2x00dev, RT5392)) { 727 reg = rt2800_register_read(rt2x00dev, AUX_CTRL); 728 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); 729 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); 730 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); 731 } 732 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 733 } 734 735 rt2800_disable_wpdma(rt2x00dev); 736 737 /* 738 * Write firmware to the device. 739 */ 740 rt2800_drv_write_firmware(rt2x00dev, data, len); 741 742 /* 743 * Wait for device to stabilize. 744 */ 745 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 746 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL); 747 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 748 break; 749 msleep(1); 750 } 751 752 if (i == REGISTER_BUSY_COUNT) { 753 rt2x00_err(rt2x00dev, "PBF system register not ready\n"); 754 return -EBUSY; 755 } 756 757 /* 758 * Disable DMA, will be reenabled later when enabling 759 * the radio. 760 */ 761 rt2800_disable_wpdma(rt2x00dev); 762 763 /* 764 * Initialize firmware. 765 */ 766 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 767 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 768 if (rt2x00_is_usb(rt2x00dev)) { 769 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 770 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 771 } 772 msleep(1); 773 774 return 0; 775 } 776 EXPORT_SYMBOL_GPL(rt2800_load_firmware); 777 778 void rt2800_write_tx_data(struct queue_entry *entry, 779 struct txentry_desc *txdesc) 780 { 781 __le32 *txwi = rt2800_drv_get_txwi(entry); 782 u32 word; 783 int i; 784 785 /* 786 * Initialize TX Info descriptor 787 */ 788 word = rt2x00_desc_read(txwi, 0); 789 rt2x00_set_field32(&word, TXWI_W0_FRAG, 790 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 791 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 792 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); 793 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); 794 rt2x00_set_field32(&word, TXWI_W0_TS, 795 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 796 rt2x00_set_field32(&word, TXWI_W0_AMPDU, 797 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); 798 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, 799 txdesc->u.ht.mpdu_density); 800 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); 801 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); 802 rt2x00_set_field32(&word, TXWI_W0_BW, 803 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); 804 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, 805 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); 806 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); 807 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); 808 rt2x00_desc_write(txwi, 0, word); 809 810 word = rt2x00_desc_read(txwi, 1); 811 rt2x00_set_field32(&word, TXWI_W1_ACK, 812 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 813 rt2x00_set_field32(&word, TXWI_W1_NSEQ, 814 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 815 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); 816 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 817 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 818 txdesc->key_idx : txdesc->u.ht.wcid); 819 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 820 txdesc->length); 821 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); 822 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); 823 rt2x00_desc_write(txwi, 1, word); 824 825 /* 826 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert 827 * the IV from the IVEIV register when TXD_W3_WIV is set to 0. 828 * When TXD_W3_WIV is set to 1 it will use the IV data 829 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 830 * crypto entry in the registers should be used to encrypt the frame. 831 * 832 * Nulify all remaining words as well, we don't know how to program them. 833 */ 834 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++) 835 _rt2x00_desc_write(txwi, i, 0); 836 } 837 EXPORT_SYMBOL_GPL(rt2800_write_tx_data); 838 839 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) 840 { 841 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); 842 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); 843 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); 844 u16 eeprom; 845 u8 offset0; 846 u8 offset1; 847 u8 offset2; 848 849 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 850 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 851 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); 852 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); 853 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 854 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); 855 } else { 856 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 857 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); 858 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); 859 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 860 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); 861 } 862 863 /* 864 * Convert the value from the descriptor into the RSSI value 865 * If the value in the descriptor is 0, it is considered invalid 866 * and the default (extremely low) rssi value is assumed 867 */ 868 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128; 869 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128; 870 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128; 871 872 /* 873 * mac80211 only accepts a single RSSI value. Calculating the 874 * average doesn't deliver a fair answer either since -60:-60 would 875 * be considered equally good as -50:-70 while the second is the one 876 * which gives less energy... 877 */ 878 rssi0 = max(rssi0, rssi1); 879 return (int)max(rssi0, rssi2); 880 } 881 882 void rt2800_process_rxwi(struct queue_entry *entry, 883 struct rxdone_entry_desc *rxdesc) 884 { 885 __le32 *rxwi = (__le32 *) entry->skb->data; 886 u32 word; 887 888 word = rt2x00_desc_read(rxwi, 0); 889 890 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); 891 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); 892 893 word = rt2x00_desc_read(rxwi, 1); 894 895 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) 896 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI; 897 898 if (rt2x00_get_field32(word, RXWI_W1_BW)) 899 rxdesc->bw = RATE_INFO_BW_40; 900 901 /* 902 * Detect RX rate, always use MCS as signal type. 903 */ 904 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; 905 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); 906 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); 907 908 /* 909 * Mask of 0x8 bit to remove the short preamble flag. 910 */ 911 if (rxdesc->rate_mode == RATE_MODE_CCK) 912 rxdesc->signal &= ~0x8; 913 914 word = rt2x00_desc_read(rxwi, 2); 915 916 /* 917 * Convert descriptor AGC value to RSSI value. 918 */ 919 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); 920 /* 921 * Remove RXWI descriptor from start of the buffer. 922 */ 923 skb_pull(entry->skb, entry->queue->winfo_size); 924 } 925 EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 926 927 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc, 928 u32 status, enum nl80211_band band) 929 { 930 u8 flags = 0; 931 u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 932 933 switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) { 934 case RATE_MODE_HT_GREENFIELD: 935 flags |= IEEE80211_TX_RC_GREEN_FIELD; 936 /* fall through */ 937 case RATE_MODE_HT_MIX: 938 flags |= IEEE80211_TX_RC_MCS; 939 break; 940 case RATE_MODE_OFDM: 941 if (band == NL80211_BAND_2GHZ) 942 idx += 4; 943 break; 944 case RATE_MODE_CCK: 945 if (idx >= 8) 946 idx -= 8; 947 break; 948 } 949 950 if (rt2x00_get_field32(status, TX_STA_FIFO_BW)) 951 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 952 953 if (rt2x00_get_field32(status, TX_STA_FIFO_SGI)) 954 flags |= IEEE80211_TX_RC_SHORT_GI; 955 956 skbdesc->tx_rate_idx = idx; 957 skbdesc->tx_rate_flags = flags; 958 } 959 960 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg) 961 { 962 __le32 *txwi; 963 u32 word; 964 int wcid, ack, pid; 965 int tx_wcid, tx_ack, tx_pid, is_agg; 966 967 /* 968 * This frames has returned with an IO error, 969 * so the status report is not intended for this 970 * frame. 971 */ 972 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) 973 return false; 974 975 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID); 976 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED); 977 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE); 978 is_agg = rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE); 979 980 /* 981 * Validate if this TX status report is intended for 982 * this entry by comparing the WCID/ACK/PID fields. 983 */ 984 txwi = rt2800_drv_get_txwi(entry); 985 986 word = rt2x00_desc_read(txwi, 1); 987 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID); 988 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK); 989 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID); 990 991 if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) { 992 rt2x00_dbg(entry->queue->rt2x00dev, 993 "TX status report missed for queue %d entry %d\n", 994 entry->queue->qid, entry->entry_idx); 995 return false; 996 } 997 998 return true; 999 } 1000 1001 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi, 1002 bool match) 1003 { 1004 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1005 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1006 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1007 struct txdone_entry_desc txdesc; 1008 u32 word; 1009 u16 mcs, real_mcs; 1010 int aggr, ampdu, wcid, ack_req; 1011 1012 /* 1013 * Obtain the status about this packet. 1014 */ 1015 txdesc.flags = 0; 1016 word = rt2x00_desc_read(txwi, 0); 1017 1018 mcs = rt2x00_get_field32(word, TXWI_W0_MCS); 1019 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); 1020 1021 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 1022 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); 1023 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID); 1024 ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED); 1025 1026 /* 1027 * If a frame was meant to be sent as a single non-aggregated MPDU 1028 * but ended up in an aggregate the used tx rate doesn't correlate 1029 * with the one specified in the TXWI as the whole aggregate is sent 1030 * with the same rate. 1031 * 1032 * For example: two frames are sent to rt2x00, the first one sets 1033 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 1034 * and requests MCS15. If the hw aggregates both frames into one 1035 * AMDPU the tx status for both frames will contain MCS7 although 1036 * the frame was sent successfully. 1037 * 1038 * Hence, replace the requested rate with the real tx rate to not 1039 * confuse the rate control algortihm by providing clearly wrong 1040 * data. 1041 * 1042 * FIXME: if we do not find matching entry, we tell that frame was 1043 * posted without any retries. We need to find a way to fix that 1044 * and provide retry count. 1045 */ 1046 if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) { 1047 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band); 1048 mcs = real_mcs; 1049 } 1050 1051 if (aggr == 1 || ampdu == 1) 1052 __set_bit(TXDONE_AMPDU, &txdesc.flags); 1053 1054 if (!ack_req) 1055 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags); 1056 1057 /* 1058 * Ralink has a retry mechanism using a global fallback 1059 * table. We setup this fallback table to try the immediate 1060 * lower rate for all rates. In the TX_STA_FIFO, the MCS field 1061 * always contains the MCS used for the last transmission, be 1062 * it successful or not. 1063 */ 1064 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { 1065 /* 1066 * Transmission succeeded. The number of retries is 1067 * mcs - real_mcs 1068 */ 1069 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 1070 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); 1071 } else { 1072 /* 1073 * Transmission failed. The number of retries is 1074 * always 7 in this case (for a total number of 8 1075 * frames sent). 1076 */ 1077 __set_bit(TXDONE_FAILURE, &txdesc.flags); 1078 txdesc.retry = rt2x00dev->long_retry; 1079 } 1080 1081 /* 1082 * the frame was retried at least once 1083 * -> hw used fallback rates 1084 */ 1085 if (txdesc.retry) 1086 __set_bit(TXDONE_FALLBACK, &txdesc.flags); 1087 1088 if (!match) { 1089 /* RCU assures non-null sta will not be freed by mac80211. */ 1090 rcu_read_lock(); 1091 if (likely(wcid >= WCID_START && wcid <= WCID_END)) 1092 skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START]; 1093 else 1094 skbdesc->sta = NULL; 1095 rt2x00lib_txdone_nomatch(entry, &txdesc); 1096 rcu_read_unlock(); 1097 } else { 1098 rt2x00lib_txdone(entry, &txdesc); 1099 } 1100 } 1101 EXPORT_SYMBOL_GPL(rt2800_txdone_entry); 1102 1103 void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota) 1104 { 1105 struct data_queue *queue; 1106 struct queue_entry *entry; 1107 u32 reg; 1108 u8 qid; 1109 bool match; 1110 1111 while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, ®)) { 1112 /* 1113 * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is 1114 * guaranteed to be one of the TX QIDs . 1115 */ 1116 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE); 1117 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid); 1118 1119 if (unlikely(rt2x00queue_empty(queue))) { 1120 rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n", 1121 qid); 1122 break; 1123 } 1124 1125 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1126 1127 if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1128 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) { 1129 rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n", 1130 entry->entry_idx, qid); 1131 break; 1132 } 1133 1134 match = rt2800_txdone_entry_check(entry, reg); 1135 rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match); 1136 } 1137 } 1138 EXPORT_SYMBOL_GPL(rt2800_txdone); 1139 1140 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev, 1141 struct queue_entry *entry) 1142 { 1143 bool ret; 1144 unsigned long tout; 1145 1146 if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1147 return false; 1148 1149 if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags)) 1150 tout = msecs_to_jiffies(50); 1151 else 1152 tout = msecs_to_jiffies(2000); 1153 1154 ret = time_after(jiffies, entry->last_action + tout); 1155 if (unlikely(ret)) 1156 rt2x00_dbg(entry->queue->rt2x00dev, 1157 "TX status timeout for entry %d in queue %d\n", 1158 entry->entry_idx, entry->queue->qid); 1159 return ret; 1160 } 1161 1162 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev) 1163 { 1164 struct data_queue *queue; 1165 struct queue_entry *entry; 1166 1167 tx_queue_for_each(rt2x00dev, queue) { 1168 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1169 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1170 return true; 1171 } 1172 1173 return false; 1174 } 1175 EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout); 1176 1177 /* 1178 * test if there is an entry in any TX queue for which DMA is done 1179 * but the TX status has not been returned yet 1180 */ 1181 bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev) 1182 { 1183 struct data_queue *queue; 1184 1185 tx_queue_for_each(rt2x00dev, queue) { 1186 if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) != 1187 rt2x00queue_get_entry(queue, Q_INDEX_DONE)) 1188 return true; 1189 } 1190 return false; 1191 } 1192 EXPORT_SYMBOL_GPL(rt2800_txstatus_pending); 1193 1194 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev) 1195 { 1196 struct data_queue *queue; 1197 struct queue_entry *entry; 1198 1199 /* 1200 * Process any trailing TX status reports for IO failures, 1201 * we loop until we find the first non-IO error entry. This 1202 * can either be a frame which is free, is being uploaded, 1203 * or has completed the upload but didn't have an entry 1204 * in the TX_STAT_FIFO register yet. 1205 */ 1206 tx_queue_for_each(rt2x00dev, queue) { 1207 while (!rt2x00queue_empty(queue)) { 1208 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1209 1210 if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1211 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1212 break; 1213 1214 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) || 1215 rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1216 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE); 1217 else 1218 break; 1219 } 1220 } 1221 } 1222 EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus); 1223 1224 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev, 1225 unsigned int index) 1226 { 1227 return HW_BEACON_BASE(index); 1228 } 1229 1230 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev, 1231 unsigned int index) 1232 { 1233 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index)); 1234 } 1235 1236 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev) 1237 { 1238 struct data_queue *queue = rt2x00dev->bcn; 1239 struct queue_entry *entry; 1240 int i, bcn_num = 0; 1241 u64 off, reg = 0; 1242 u32 bssid_dw1; 1243 1244 /* 1245 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers. 1246 */ 1247 for (i = 0; i < queue->limit; i++) { 1248 entry = &queue->entries[i]; 1249 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags)) 1250 continue; 1251 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx); 1252 reg |= off << (8 * bcn_num); 1253 bcn_num++; 1254 } 1255 1256 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); 1257 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); 1258 1259 /* 1260 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons. 1261 */ 1262 bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1); 1263 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, 1264 bcn_num > 0 ? bcn_num - 1 : 0); 1265 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1); 1266 } 1267 1268 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) 1269 { 1270 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1271 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1272 unsigned int beacon_base; 1273 unsigned int padding_len; 1274 u32 orig_reg, reg; 1275 const int txwi_desc_size = entry->queue->winfo_size; 1276 1277 /* 1278 * Disable beaconing while we are reloading the beacon data, 1279 * otherwise we might be sending out invalid data. 1280 */ 1281 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1282 orig_reg = reg; 1283 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1284 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1285 1286 /* 1287 * Add space for the TXWI in front of the skb. 1288 */ 1289 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size); 1290 1291 /* 1292 * Register descriptor details in skb frame descriptor. 1293 */ 1294 skbdesc->flags |= SKBDESC_DESC_IN_SKB; 1295 skbdesc->desc = entry->skb->data; 1296 skbdesc->desc_len = txwi_desc_size; 1297 1298 /* 1299 * Add the TXWI for the beacon to the skb. 1300 */ 1301 rt2800_write_tx_data(entry, txdesc); 1302 1303 /* 1304 * Dump beacon to userspace through debugfs. 1305 */ 1306 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); 1307 1308 /* 1309 * Write entire beacon with TXWI and padding to register. 1310 */ 1311 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 1312 if (padding_len && skb_pad(entry->skb, padding_len)) { 1313 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); 1314 /* skb freed by skb_pad() on failure */ 1315 entry->skb = NULL; 1316 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1317 return; 1318 } 1319 1320 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx); 1321 1322 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, 1323 entry->skb->len + padding_len); 1324 __set_bit(ENTRY_BCN_ENABLED, &entry->flags); 1325 1326 /* 1327 * Change global beacons settings. 1328 */ 1329 rt2800_update_beacons_setup(rt2x00dev); 1330 1331 /* 1332 * Restore beaconing state. 1333 */ 1334 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1335 1336 /* 1337 * Clean up beacon skb. 1338 */ 1339 dev_kfree_skb_any(entry->skb); 1340 entry->skb = NULL; 1341 } 1342 EXPORT_SYMBOL_GPL(rt2800_write_beacon); 1343 1344 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, 1345 unsigned int index) 1346 { 1347 int i; 1348 const int txwi_desc_size = rt2x00dev->bcn->winfo_size; 1349 unsigned int beacon_base; 1350 1351 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index); 1352 1353 /* 1354 * For the Beacon base registers we only need to clear 1355 * the whole TXWI which (when set to 0) will invalidate 1356 * the entire beacon. 1357 */ 1358 for (i = 0; i < txwi_desc_size; i += sizeof(__le32)) 1359 rt2800_register_write(rt2x00dev, beacon_base + i, 0); 1360 } 1361 1362 void rt2800_clear_beacon(struct queue_entry *entry) 1363 { 1364 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1365 u32 orig_reg, reg; 1366 1367 /* 1368 * Disable beaconing while we are reloading the beacon data, 1369 * otherwise we might be sending out invalid data. 1370 */ 1371 orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1372 reg = orig_reg; 1373 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1374 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1375 1376 /* 1377 * Clear beacon. 1378 */ 1379 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx); 1380 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags); 1381 1382 /* 1383 * Change global beacons settings. 1384 */ 1385 rt2800_update_beacons_setup(rt2x00dev); 1386 /* 1387 * Restore beaconing state. 1388 */ 1389 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1390 } 1391 EXPORT_SYMBOL_GPL(rt2800_clear_beacon); 1392 1393 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 1394 const struct rt2x00debug rt2800_rt2x00debug = { 1395 .owner = THIS_MODULE, 1396 .csr = { 1397 .read = rt2800_register_read, 1398 .write = rt2800_register_write, 1399 .flags = RT2X00DEBUGFS_OFFSET, 1400 .word_base = CSR_REG_BASE, 1401 .word_size = sizeof(u32), 1402 .word_count = CSR_REG_SIZE / sizeof(u32), 1403 }, 1404 .eeprom = { 1405 /* NOTE: The local EEPROM access functions can't 1406 * be used here, use the generic versions instead. 1407 */ 1408 .read = rt2x00_eeprom_read, 1409 .write = rt2x00_eeprom_write, 1410 .word_base = EEPROM_BASE, 1411 .word_size = sizeof(u16), 1412 .word_count = EEPROM_SIZE / sizeof(u16), 1413 }, 1414 .bbp = { 1415 .read = rt2800_bbp_read, 1416 .write = rt2800_bbp_write, 1417 .word_base = BBP_BASE, 1418 .word_size = sizeof(u8), 1419 .word_count = BBP_SIZE / sizeof(u8), 1420 }, 1421 .rf = { 1422 .read = rt2x00_rf_read, 1423 .write = rt2800_rf_write, 1424 .word_base = RF_BASE, 1425 .word_size = sizeof(u32), 1426 .word_count = RF_SIZE / sizeof(u32), 1427 }, 1428 .rfcsr = { 1429 .read = rt2800_rfcsr_read, 1430 .write = rt2800_rfcsr_write, 1431 .word_base = RFCSR_BASE, 1432 .word_size = sizeof(u8), 1433 .word_count = RFCSR_SIZE / sizeof(u8), 1434 }, 1435 }; 1436 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); 1437 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1438 1439 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) 1440 { 1441 u32 reg; 1442 1443 if (rt2x00_rt(rt2x00dev, RT3290)) { 1444 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 1445 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); 1446 } else { 1447 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 1448 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); 1449 } 1450 } 1451 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 1452 1453 #ifdef CONFIG_RT2X00_LIB_LEDS 1454 static void rt2800_brightness_set(struct led_classdev *led_cdev, 1455 enum led_brightness brightness) 1456 { 1457 struct rt2x00_led *led = 1458 container_of(led_cdev, struct rt2x00_led, led_dev); 1459 unsigned int enabled = brightness != LED_OFF; 1460 unsigned int bg_mode = 1461 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); 1462 unsigned int polarity = 1463 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1464 EEPROM_FREQ_LED_POLARITY); 1465 unsigned int ledmode = 1466 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1467 EEPROM_FREQ_LED_MODE); 1468 u32 reg; 1469 1470 /* Check for SoC (SOC devices don't support MCU requests) */ 1471 if (rt2x00_is_soc(led->rt2x00dev)) { 1472 reg = rt2800_register_read(led->rt2x00dev, LED_CFG); 1473 1474 /* Set LED Polarity */ 1475 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); 1476 1477 /* Set LED Mode */ 1478 if (led->type == LED_TYPE_RADIO) { 1479 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 1480 enabled ? 3 : 0); 1481 } else if (led->type == LED_TYPE_ASSOC) { 1482 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 1483 enabled ? 3 : 0); 1484 } else if (led->type == LED_TYPE_QUALITY) { 1485 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 1486 enabled ? 3 : 0); 1487 } 1488 1489 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 1490 1491 } else { 1492 if (led->type == LED_TYPE_RADIO) { 1493 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1494 enabled ? 0x20 : 0); 1495 } else if (led->type == LED_TYPE_ASSOC) { 1496 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1497 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); 1498 } else if (led->type == LED_TYPE_QUALITY) { 1499 /* 1500 * The brightness is divided into 6 levels (0 - 5), 1501 * The specs tell us the following levels: 1502 * 0, 1 ,3, 7, 15, 31 1503 * to determine the level in a simple way we can simply 1504 * work with bitshifting: 1505 * (1 << level) - 1 1506 */ 1507 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 1508 (1 << brightness / (LED_FULL / 6)) - 1, 1509 polarity); 1510 } 1511 } 1512 } 1513 1514 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, 1515 struct rt2x00_led *led, enum led_type type) 1516 { 1517 led->rt2x00dev = rt2x00dev; 1518 led->type = type; 1519 led->led_dev.brightness_set = rt2800_brightness_set; 1520 led->flags = LED_INITIALIZED; 1521 } 1522 #endif /* CONFIG_RT2X00_LIB_LEDS */ 1523 1524 /* 1525 * Configuration handlers. 1526 */ 1527 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, 1528 const u8 *address, 1529 int wcid) 1530 { 1531 struct mac_wcid_entry wcid_entry; 1532 u32 offset; 1533 1534 offset = MAC_WCID_ENTRY(wcid); 1535 1536 memset(&wcid_entry, 0xff, sizeof(wcid_entry)); 1537 if (address) 1538 memcpy(wcid_entry.mac, address, ETH_ALEN); 1539 1540 rt2800_register_multiwrite(rt2x00dev, offset, 1541 &wcid_entry, sizeof(wcid_entry)); 1542 } 1543 1544 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) 1545 { 1546 u32 offset; 1547 offset = MAC_WCID_ATTR_ENTRY(wcid); 1548 rt2800_register_write(rt2x00dev, offset, 0); 1549 } 1550 1551 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, 1552 int wcid, u32 bssidx) 1553 { 1554 u32 offset = MAC_WCID_ATTR_ENTRY(wcid); 1555 u32 reg; 1556 1557 /* 1558 * The BSS Idx numbers is split in a main value of 3 bits, 1559 * and a extended field for adding one additional bit to the value. 1560 */ 1561 reg = rt2800_register_read(rt2x00dev, offset); 1562 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); 1563 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, 1564 (bssidx & 0x8) >> 3); 1565 rt2800_register_write(rt2x00dev, offset, reg); 1566 } 1567 1568 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, 1569 struct rt2x00lib_crypto *crypto, 1570 struct ieee80211_key_conf *key) 1571 { 1572 struct mac_iveiv_entry iveiv_entry; 1573 u32 offset; 1574 u32 reg; 1575 1576 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); 1577 1578 if (crypto->cmd == SET_KEY) { 1579 reg = rt2800_register_read(rt2x00dev, offset); 1580 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 1581 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 1582 /* 1583 * Both the cipher as the BSS Idx numbers are split in a main 1584 * value of 3 bits, and a extended field for adding one additional 1585 * bit to the value. 1586 */ 1587 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 1588 (crypto->cipher & 0x7)); 1589 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 1590 (crypto->cipher & 0x8) >> 3); 1591 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); 1592 rt2800_register_write(rt2x00dev, offset, reg); 1593 } else { 1594 /* Delete the cipher without touching the bssidx */ 1595 reg = rt2800_register_read(rt2x00dev, offset); 1596 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); 1597 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); 1598 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); 1599 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); 1600 rt2800_register_write(rt2x00dev, offset, reg); 1601 } 1602 1603 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 1604 1605 memset(&iveiv_entry, 0, sizeof(iveiv_entry)); 1606 if ((crypto->cipher == CIPHER_TKIP) || 1607 (crypto->cipher == CIPHER_TKIP_NO_MIC) || 1608 (crypto->cipher == CIPHER_AES)) 1609 iveiv_entry.iv[3] |= 0x20; 1610 iveiv_entry.iv[3] |= key->keyidx << 6; 1611 rt2800_register_multiwrite(rt2x00dev, offset, 1612 &iveiv_entry, sizeof(iveiv_entry)); 1613 } 1614 1615 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, 1616 struct rt2x00lib_crypto *crypto, 1617 struct ieee80211_key_conf *key) 1618 { 1619 struct hw_key_entry key_entry; 1620 struct rt2x00_field32 field; 1621 u32 offset; 1622 u32 reg; 1623 1624 if (crypto->cmd == SET_KEY) { 1625 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; 1626 1627 memcpy(key_entry.key, crypto->key, 1628 sizeof(key_entry.key)); 1629 memcpy(key_entry.tx_mic, crypto->tx_mic, 1630 sizeof(key_entry.tx_mic)); 1631 memcpy(key_entry.rx_mic, crypto->rx_mic, 1632 sizeof(key_entry.rx_mic)); 1633 1634 offset = SHARED_KEY_ENTRY(key->hw_key_idx); 1635 rt2800_register_multiwrite(rt2x00dev, offset, 1636 &key_entry, sizeof(key_entry)); 1637 } 1638 1639 /* 1640 * The cipher types are stored over multiple registers 1641 * starting with SHARED_KEY_MODE_BASE each word will have 1642 * 32 bits and contains the cipher types for 2 bssidx each. 1643 * Using the correct defines correctly will cause overhead, 1644 * so just calculate the correct offset. 1645 */ 1646 field.bit_offset = 4 * (key->hw_key_idx % 8); 1647 field.bit_mask = 0x7 << field.bit_offset; 1648 1649 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); 1650 1651 reg = rt2800_register_read(rt2x00dev, offset); 1652 rt2x00_set_field32(®, field, 1653 (crypto->cmd == SET_KEY) * crypto->cipher); 1654 rt2800_register_write(rt2x00dev, offset, reg); 1655 1656 /* 1657 * Update WCID information 1658 */ 1659 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); 1660 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, 1661 crypto->bssidx); 1662 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1663 1664 return 0; 1665 } 1666 EXPORT_SYMBOL_GPL(rt2800_config_shared_key); 1667 1668 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 1669 struct rt2x00lib_crypto *crypto, 1670 struct ieee80211_key_conf *key) 1671 { 1672 struct hw_key_entry key_entry; 1673 u32 offset; 1674 1675 if (crypto->cmd == SET_KEY) { 1676 /* 1677 * Allow key configuration only for STAs that are 1678 * known by the hw. 1679 */ 1680 if (crypto->wcid > WCID_END) 1681 return -ENOSPC; 1682 key->hw_key_idx = crypto->wcid; 1683 1684 memcpy(key_entry.key, crypto->key, 1685 sizeof(key_entry.key)); 1686 memcpy(key_entry.tx_mic, crypto->tx_mic, 1687 sizeof(key_entry.tx_mic)); 1688 memcpy(key_entry.rx_mic, crypto->rx_mic, 1689 sizeof(key_entry.rx_mic)); 1690 1691 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 1692 rt2800_register_multiwrite(rt2x00dev, offset, 1693 &key_entry, sizeof(key_entry)); 1694 } 1695 1696 /* 1697 * Update WCID information 1698 */ 1699 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1700 1701 return 0; 1702 } 1703 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); 1704 1705 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev) 1706 { 1707 u8 i, max_psdu; 1708 u32 reg; 1709 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1710 1711 for (i = 0; i < 3; i++) 1712 if (drv_data->ampdu_factor_cnt[i] > 0) 1713 break; 1714 1715 max_psdu = min(drv_data->max_psdu, i); 1716 1717 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 1718 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); 1719 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1720 } 1721 1722 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1723 struct ieee80211_sta *sta) 1724 { 1725 struct rt2x00_dev *rt2x00dev = hw->priv; 1726 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1727 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1728 int wcid; 1729 1730 /* 1731 * Limit global maximum TX AMPDU length to smallest value of all 1732 * connected stations. In AP mode this can be suboptimal, but we 1733 * do not have a choice if some connected STA is not capable to 1734 * receive the same amount of data like the others. 1735 */ 1736 if (sta->ht_cap.ht_supported) { 1737 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++; 1738 rt2800_set_max_psdu_len(rt2x00dev); 1739 } 1740 1741 /* 1742 * Search for the first free WCID entry and return the corresponding 1743 * index. 1744 */ 1745 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START; 1746 1747 /* 1748 * Store selected wcid even if it is invalid so that we can 1749 * later decide if the STA is uploaded into the hw. 1750 */ 1751 sta_priv->wcid = wcid; 1752 1753 /* 1754 * No space left in the device, however, we can still communicate 1755 * with the STA -> No error. 1756 */ 1757 if (wcid > WCID_END) 1758 return 0; 1759 1760 __set_bit(wcid - WCID_START, drv_data->sta_ids); 1761 drv_data->wcid_to_sta[wcid - WCID_START] = sta; 1762 1763 /* 1764 * Clean up WCID attributes and write STA address to the device. 1765 */ 1766 rt2800_delete_wcid_attr(rt2x00dev, wcid); 1767 rt2800_config_wcid(rt2x00dev, sta->addr, wcid); 1768 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, 1769 rt2x00lib_get_bssidx(rt2x00dev, vif)); 1770 return 0; 1771 } 1772 EXPORT_SYMBOL_GPL(rt2800_sta_add); 1773 1774 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1775 struct ieee80211_sta *sta) 1776 { 1777 struct rt2x00_dev *rt2x00dev = hw->priv; 1778 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1779 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1780 int wcid = sta_priv->wcid; 1781 1782 if (sta->ht_cap.ht_supported) { 1783 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--; 1784 rt2800_set_max_psdu_len(rt2x00dev); 1785 } 1786 1787 if (wcid > WCID_END) 1788 return 0; 1789 /* 1790 * Remove WCID entry, no need to clean the attributes as they will 1791 * get renewed when the WCID is reused. 1792 */ 1793 rt2800_config_wcid(rt2x00dev, NULL, wcid); 1794 drv_data->wcid_to_sta[wcid - WCID_START] = NULL; 1795 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1796 1797 return 0; 1798 } 1799 EXPORT_SYMBOL_GPL(rt2800_sta_remove); 1800 1801 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, 1802 const unsigned int filter_flags) 1803 { 1804 u32 reg; 1805 1806 /* 1807 * Start configuration steps. 1808 * Note that the version error will always be dropped 1809 * and broadcast frames will always be accepted since 1810 * there is no filter for it at this time. 1811 */ 1812 reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG); 1813 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, 1814 !(filter_flags & FIF_FCSFAIL)); 1815 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, 1816 !(filter_flags & FIF_PLCPFAIL)); 1817 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, 1818 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); 1819 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); 1820 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); 1821 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, 1822 !(filter_flags & FIF_ALLMULTI)); 1823 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); 1824 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); 1825 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, 1826 !(filter_flags & FIF_CONTROL)); 1827 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, 1828 !(filter_flags & FIF_CONTROL)); 1829 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, 1830 !(filter_flags & FIF_CONTROL)); 1831 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, 1832 !(filter_flags & FIF_CONTROL)); 1833 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, 1834 !(filter_flags & FIF_CONTROL)); 1835 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, 1836 !(filter_flags & FIF_PSPOLL)); 1837 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); 1838 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 1839 !(filter_flags & FIF_CONTROL)); 1840 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, 1841 !(filter_flags & FIF_CONTROL)); 1842 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); 1843 } 1844 EXPORT_SYMBOL_GPL(rt2800_config_filter); 1845 1846 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, 1847 struct rt2x00intf_conf *conf, const unsigned int flags) 1848 { 1849 u32 reg; 1850 bool update_bssid = false; 1851 1852 if (flags & CONFIG_UPDATE_TYPE) { 1853 /* 1854 * Enable synchronisation. 1855 */ 1856 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1857 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); 1858 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1859 1860 if (conf->sync == TSF_SYNC_AP_NONE) { 1861 /* 1862 * Tune beacon queue transmit parameters for AP mode 1863 */ 1864 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1865 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); 1866 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); 1867 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1868 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); 1869 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1870 } else { 1871 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1872 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); 1873 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); 1874 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1875 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); 1876 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1877 } 1878 } 1879 1880 if (flags & CONFIG_UPDATE_MAC) { 1881 if (flags & CONFIG_UPDATE_TYPE && 1882 conf->sync == TSF_SYNC_AP_NONE) { 1883 /* 1884 * The BSSID register has to be set to our own mac 1885 * address in AP mode. 1886 */ 1887 memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); 1888 update_bssid = true; 1889 } 1890 1891 if (!is_zero_ether_addr((const u8 *)conf->mac)) { 1892 reg = le32_to_cpu(conf->mac[1]); 1893 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); 1894 conf->mac[1] = cpu_to_le32(reg); 1895 } 1896 1897 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, 1898 conf->mac, sizeof(conf->mac)); 1899 } 1900 1901 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { 1902 if (!is_zero_ether_addr((const u8 *)conf->bssid)) { 1903 reg = le32_to_cpu(conf->bssid[1]); 1904 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); 1905 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); 1906 conf->bssid[1] = cpu_to_le32(reg); 1907 } 1908 1909 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, 1910 conf->bssid, sizeof(conf->bssid)); 1911 } 1912 } 1913 EXPORT_SYMBOL_GPL(rt2800_config_intf); 1914 1915 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, 1916 struct rt2x00lib_erp *erp) 1917 { 1918 bool any_sta_nongf = !!(erp->ht_opmode & 1919 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 1920 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; 1921 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; 1922 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; 1923 u32 reg; 1924 1925 /* default protection rate for HT20: OFDM 24M */ 1926 mm20_rate = gf20_rate = 0x4004; 1927 1928 /* default protection rate for HT40: duplicate OFDM 24M */ 1929 mm40_rate = gf40_rate = 0x4084; 1930 1931 switch (protection) { 1932 case IEEE80211_HT_OP_MODE_PROTECTION_NONE: 1933 /* 1934 * All STAs in this BSS are HT20/40 but there might be 1935 * STAs not supporting greenfield mode. 1936 * => Disable protection for HT transmissions. 1937 */ 1938 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; 1939 1940 break; 1941 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 1942 /* 1943 * All STAs in this BSS are HT20 or HT20/40 but there 1944 * might be STAs not supporting greenfield mode. 1945 * => Protect all HT40 transmissions. 1946 */ 1947 mm20_mode = gf20_mode = 0; 1948 mm40_mode = gf40_mode = 1; 1949 1950 break; 1951 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 1952 /* 1953 * Nonmember protection: 1954 * According to 802.11n we _should_ protect all 1955 * HT transmissions (but we don't have to). 1956 * 1957 * But if cts_protection is enabled we _shall_ protect 1958 * all HT transmissions using a CCK rate. 1959 * 1960 * And if any station is non GF we _shall_ protect 1961 * GF transmissions. 1962 * 1963 * We decide to protect everything 1964 * -> fall through to mixed mode. 1965 */ 1966 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 1967 /* 1968 * Legacy STAs are present 1969 * => Protect all HT transmissions. 1970 */ 1971 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1; 1972 1973 /* 1974 * If erp protection is needed we have to protect HT 1975 * transmissions with CCK 11M long preamble. 1976 */ 1977 if (erp->cts_protection) { 1978 /* don't duplicate RTS/CTS in CCK mode */ 1979 mm20_rate = mm40_rate = 0x0003; 1980 gf20_rate = gf40_rate = 0x0003; 1981 } 1982 break; 1983 } 1984 1985 /* check for STAs not supporting greenfield mode */ 1986 if (any_sta_nongf) 1987 gf20_mode = gf40_mode = 1; 1988 1989 /* Update HT protection config */ 1990 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 1991 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); 1992 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); 1993 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 1994 1995 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 1996 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); 1997 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); 1998 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 1999 2000 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 2001 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); 2002 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); 2003 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 2004 2005 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 2006 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); 2007 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); 2008 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 2009 } 2010 2011 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, 2012 u32 changed) 2013 { 2014 u32 reg; 2015 2016 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 2017 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 2018 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 2019 !!erp->short_preamble); 2020 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 2021 } 2022 2023 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 2024 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 2025 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 2026 erp->cts_protection ? 2 : 0); 2027 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 2028 } 2029 2030 if (changed & BSS_CHANGED_BASIC_RATES) { 2031 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 2032 0xff0 | erp->basic_rates); 2033 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 2034 } 2035 2036 if (changed & BSS_CHANGED_ERP_SLOT) { 2037 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 2038 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 2039 erp->slot_time); 2040 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 2041 2042 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 2043 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); 2044 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 2045 } 2046 2047 if (changed & BSS_CHANGED_BEACON_INT) { 2048 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 2049 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 2050 erp->beacon_int * 16); 2051 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 2052 } 2053 2054 if (changed & BSS_CHANGED_HT) 2055 rt2800_config_ht_opmode(rt2x00dev, erp); 2056 } 2057 EXPORT_SYMBOL_GPL(rt2800_config_erp); 2058 2059 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) 2060 { 2061 u32 reg; 2062 u16 eeprom; 2063 u8 led_ctrl, led_g_mode, led_r_mode; 2064 2065 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 2066 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { 2067 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); 2068 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); 2069 } else { 2070 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); 2071 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); 2072 } 2073 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 2074 2075 reg = rt2800_register_read(rt2x00dev, LED_CFG); 2076 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; 2077 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; 2078 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || 2079 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { 2080 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 2081 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); 2082 if (led_ctrl == 0 || led_ctrl > 0x40) { 2083 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); 2084 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); 2085 rt2800_register_write(rt2x00dev, LED_CFG, reg); 2086 } else { 2087 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, 2088 (led_g_mode << 2) | led_r_mode, 1); 2089 } 2090 } 2091 } 2092 2093 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, 2094 enum antenna ant) 2095 { 2096 u32 reg; 2097 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; 2098 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; 2099 2100 if (rt2x00_is_pci(rt2x00dev)) { 2101 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR); 2102 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); 2103 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); 2104 } else if (rt2x00_is_usb(rt2x00dev)) 2105 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, 2106 eesk_pin, 0); 2107 2108 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2109 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 2110 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); 2111 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2112 } 2113 2114 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 2115 { 2116 u8 r1; 2117 u8 r3; 2118 u16 eeprom; 2119 2120 r1 = rt2800_bbp_read(rt2x00dev, 1); 2121 r3 = rt2800_bbp_read(rt2x00dev, 3); 2122 2123 if (rt2x00_rt(rt2x00dev, RT3572) && 2124 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2125 rt2800_config_3572bt_ant(rt2x00dev); 2126 2127 /* 2128 * Configure the TX antenna. 2129 */ 2130 switch (ant->tx_chain_num) { 2131 case 1: 2132 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 2133 break; 2134 case 2: 2135 if (rt2x00_rt(rt2x00dev, RT3572) && 2136 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2137 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); 2138 else 2139 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2140 break; 2141 case 3: 2142 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2143 break; 2144 } 2145 2146 /* 2147 * Configure the RX antenna. 2148 */ 2149 switch (ant->rx_chain_num) { 2150 case 1: 2151 if (rt2x00_rt(rt2x00dev, RT3070) || 2152 rt2x00_rt(rt2x00dev, RT3090) || 2153 rt2x00_rt(rt2x00dev, RT3352) || 2154 rt2x00_rt(rt2x00dev, RT3390)) { 2155 eeprom = rt2800_eeprom_read(rt2x00dev, 2156 EEPROM_NIC_CONF1); 2157 if (rt2x00_get_field16(eeprom, 2158 EEPROM_NIC_CONF1_ANT_DIVERSITY)) 2159 rt2800_set_ant_diversity(rt2x00dev, 2160 rt2x00dev->default_ant.rx); 2161 } 2162 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 2163 break; 2164 case 2: 2165 if (rt2x00_rt(rt2x00dev, RT3572) && 2166 rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2167 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); 2168 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2169 rt2x00dev->curr_band == NL80211_BAND_5GHZ); 2170 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); 2171 } else { 2172 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); 2173 } 2174 break; 2175 case 3: 2176 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); 2177 break; 2178 } 2179 2180 rt2800_bbp_write(rt2x00dev, 3, r3); 2181 rt2800_bbp_write(rt2x00dev, 1, r1); 2182 2183 if (rt2x00_rt(rt2x00dev, RT3593)) { 2184 if (ant->rx_chain_num == 1) 2185 rt2800_bbp_write(rt2x00dev, 86, 0x00); 2186 else 2187 rt2800_bbp_write(rt2x00dev, 86, 0x46); 2188 } 2189 } 2190 EXPORT_SYMBOL_GPL(rt2800_config_ant); 2191 2192 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, 2193 struct rt2x00lib_conf *libconf) 2194 { 2195 u16 eeprom; 2196 short lna_gain; 2197 2198 if (libconf->rf.channel <= 14) { 2199 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2200 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); 2201 } else if (libconf->rf.channel <= 64) { 2202 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2203 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); 2204 } else if (libconf->rf.channel <= 128) { 2205 if (rt2x00_rt(rt2x00dev, RT3593)) { 2206 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2207 lna_gain = rt2x00_get_field16(eeprom, 2208 EEPROM_EXT_LNA2_A1); 2209 } else { 2210 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 2211 lna_gain = rt2x00_get_field16(eeprom, 2212 EEPROM_RSSI_BG2_LNA_A1); 2213 } 2214 } else { 2215 if (rt2x00_rt(rt2x00dev, RT3593)) { 2216 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2217 lna_gain = rt2x00_get_field16(eeprom, 2218 EEPROM_EXT_LNA2_A2); 2219 } else { 2220 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 2221 lna_gain = rt2x00_get_field16(eeprom, 2222 EEPROM_RSSI_A2_LNA_A2); 2223 } 2224 } 2225 2226 rt2x00dev->lna_gain = lna_gain; 2227 } 2228 2229 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev) 2230 { 2231 return clk_get_rate(rt2x00dev->clk) == 20000000; 2232 } 2233 2234 #define FREQ_OFFSET_BOUND 0x5f 2235 2236 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev) 2237 { 2238 u8 freq_offset, prev_freq_offset; 2239 u8 rfcsr, prev_rfcsr; 2240 2241 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE); 2242 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND); 2243 2244 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 2245 prev_rfcsr = rfcsr; 2246 2247 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset); 2248 if (rfcsr == prev_rfcsr) 2249 return; 2250 2251 if (rt2x00_is_usb(rt2x00dev)) { 2252 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff, 2253 freq_offset, prev_rfcsr); 2254 return; 2255 } 2256 2257 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE); 2258 while (prev_freq_offset != freq_offset) { 2259 if (prev_freq_offset < freq_offset) 2260 prev_freq_offset++; 2261 else 2262 prev_freq_offset--; 2263 2264 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset); 2265 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 2266 2267 usleep_range(1000, 1500); 2268 } 2269 } 2270 2271 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, 2272 struct ieee80211_conf *conf, 2273 struct rf_channel *rf, 2274 struct channel_info *info) 2275 { 2276 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 2277 2278 if (rt2x00dev->default_ant.tx_chain_num == 1) 2279 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); 2280 2281 if (rt2x00dev->default_ant.rx_chain_num == 1) { 2282 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); 2283 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2284 } else if (rt2x00dev->default_ant.rx_chain_num == 2) 2285 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2286 2287 if (rf->channel > 14) { 2288 /* 2289 * When TX power is below 0, we should increase it by 7 to 2290 * make it a positive value (Minimum value is -7). 2291 * However this means that values between 0 and 7 have 2292 * double meaning, and we should set a 7DBm boost flag. 2293 */ 2294 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, 2295 (info->default_power1 >= 0)); 2296 2297 if (info->default_power1 < 0) 2298 info->default_power1 += 7; 2299 2300 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); 2301 2302 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, 2303 (info->default_power2 >= 0)); 2304 2305 if (info->default_power2 < 0) 2306 info->default_power2 += 7; 2307 2308 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); 2309 } else { 2310 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); 2311 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); 2312 } 2313 2314 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); 2315 2316 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2317 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2318 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2319 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2320 2321 udelay(200); 2322 2323 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2324 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2325 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 2326 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2327 2328 udelay(200); 2329 2330 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2331 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2332 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2333 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2334 } 2335 2336 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, 2337 struct ieee80211_conf *conf, 2338 struct rf_channel *rf, 2339 struct channel_info *info) 2340 { 2341 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2342 u8 rfcsr, calib_tx, calib_rx; 2343 2344 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2345 2346 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2347 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3); 2348 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2349 2350 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2351 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2352 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2353 2354 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2355 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); 2356 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2357 2358 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2359 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); 2360 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2361 2362 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2363 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2364 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 2365 rt2x00dev->default_ant.rx_chain_num <= 1); 2366 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 2367 rt2x00dev->default_ant.rx_chain_num <= 2); 2368 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2369 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 2370 rt2x00dev->default_ant.tx_chain_num <= 1); 2371 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 2372 rt2x00dev->default_ant.tx_chain_num <= 2); 2373 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2374 2375 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2376 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2377 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2378 2379 if (rt2x00_rt(rt2x00dev, RT3390)) { 2380 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f; 2381 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f; 2382 } else { 2383 if (conf_is_ht40(conf)) { 2384 calib_tx = drv_data->calibration_bw40; 2385 calib_rx = drv_data->calibration_bw40; 2386 } else { 2387 calib_tx = drv_data->calibration_bw20; 2388 calib_rx = drv_data->calibration_bw20; 2389 } 2390 } 2391 2392 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24); 2393 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx); 2394 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr); 2395 2396 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 2397 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx); 2398 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2399 2400 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2401 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2402 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2403 2404 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2405 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 2406 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2407 2408 usleep_range(1000, 1500); 2409 2410 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 2411 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2412 } 2413 2414 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, 2415 struct ieee80211_conf *conf, 2416 struct rf_channel *rf, 2417 struct channel_info *info) 2418 { 2419 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2420 u8 rfcsr; 2421 u32 reg; 2422 2423 if (rf->channel <= 14) { 2424 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2425 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2426 } else { 2427 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2428 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2429 } 2430 2431 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2432 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 2433 2434 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2435 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2436 if (rf->channel <= 14) 2437 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); 2438 else 2439 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); 2440 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2441 2442 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5); 2443 if (rf->channel <= 14) 2444 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); 2445 else 2446 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); 2447 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); 2448 2449 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2450 if (rf->channel <= 14) { 2451 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); 2452 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2453 info->default_power1); 2454 } else { 2455 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); 2456 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2457 (info->default_power1 & 0x3) | 2458 ((info->default_power1 & 0xC) << 1)); 2459 } 2460 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2461 2462 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2463 if (rf->channel <= 14) { 2464 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); 2465 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2466 info->default_power2); 2467 } else { 2468 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); 2469 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2470 (info->default_power2 & 0x3) | 2471 ((info->default_power2 & 0xC) << 1)); 2472 } 2473 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2474 2475 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2476 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2477 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2478 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2479 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2480 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2481 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2482 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2483 if (rf->channel <= 14) { 2484 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2485 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2486 } 2487 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2488 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2489 } else { 2490 switch (rt2x00dev->default_ant.tx_chain_num) { 2491 case 1: 2492 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2493 /* fall through */ 2494 case 2: 2495 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2496 break; 2497 } 2498 2499 switch (rt2x00dev->default_ant.rx_chain_num) { 2500 case 1: 2501 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2502 /* fall through */ 2503 case 2: 2504 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2505 break; 2506 } 2507 } 2508 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2509 2510 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2511 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2512 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2513 2514 if (conf_is_ht40(conf)) { 2515 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40); 2516 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40); 2517 } else { 2518 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20); 2519 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20); 2520 } 2521 2522 if (rf->channel <= 14) { 2523 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 2524 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 2525 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2526 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 2527 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 2528 rfcsr = 0x4c; 2529 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2530 drv_data->txmixer_gain_24g); 2531 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2532 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2533 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 2534 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 2535 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 2536 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 2537 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 2538 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 2539 } else { 2540 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2541 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1); 2542 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0); 2543 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1); 2544 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0); 2545 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2546 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 2547 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2548 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 2549 rt2800_rfcsr_write(rt2x00dev, 15, 0x43); 2550 rfcsr = 0x7a; 2551 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2552 drv_data->txmixer_gain_5g); 2553 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2554 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2555 if (rf->channel <= 64) { 2556 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7); 2557 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6); 2558 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 2559 } else if (rf->channel <= 128) { 2560 rt2800_rfcsr_write(rt2x00dev, 19, 0x74); 2561 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4); 2562 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2563 } else { 2564 rt2800_rfcsr_write(rt2x00dev, 19, 0x72); 2565 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3); 2566 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2567 } 2568 rt2800_rfcsr_write(rt2x00dev, 26, 0x87); 2569 rt2800_rfcsr_write(rt2x00dev, 27, 0x01); 2570 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); 2571 } 2572 2573 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2574 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 2575 if (rf->channel <= 14) 2576 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 2577 else 2578 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); 2579 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2580 2581 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2582 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2583 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2584 } 2585 2586 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, 2587 struct ieee80211_conf *conf, 2588 struct rf_channel *rf, 2589 struct channel_info *info) 2590 { 2591 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2592 u8 txrx_agc_fc; 2593 u8 txrx_h20m; 2594 u8 rfcsr; 2595 u8 bbp; 2596 const bool txbf_enabled = false; /* TODO */ 2597 2598 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */ 2599 bbp = rt2800_bbp_read(rt2x00dev, 109); 2600 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0); 2601 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0); 2602 rt2800_bbp_write(rt2x00dev, 109, bbp); 2603 2604 bbp = rt2800_bbp_read(rt2x00dev, 110); 2605 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0); 2606 rt2800_bbp_write(rt2x00dev, 110, bbp); 2607 2608 if (rf->channel <= 14) { 2609 /* Restore BBP 25 & 26 for 2.4 GHz */ 2610 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2611 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2612 } else { 2613 /* Hard code BBP 25 & 26 for 5GHz */ 2614 2615 /* Enable IQ Phase correction */ 2616 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2617 /* Setup IQ Phase correction value */ 2618 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2619 } 2620 2621 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2622 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf); 2623 2624 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2625 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3)); 2626 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2627 2628 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2629 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1); 2630 if (rf->channel <= 14) 2631 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1); 2632 else 2633 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2); 2634 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2635 2636 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53); 2637 if (rf->channel <= 14) { 2638 rfcsr = 0; 2639 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2640 info->default_power1 & 0x1f); 2641 } else { 2642 if (rt2x00_is_usb(rt2x00dev)) 2643 rfcsr = 0x40; 2644 2645 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2646 ((info->default_power1 & 0x18) << 1) | 2647 (info->default_power1 & 7)); 2648 } 2649 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr); 2650 2651 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55); 2652 if (rf->channel <= 14) { 2653 rfcsr = 0; 2654 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2655 info->default_power2 & 0x1f); 2656 } else { 2657 if (rt2x00_is_usb(rt2x00dev)) 2658 rfcsr = 0x40; 2659 2660 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2661 ((info->default_power2 & 0x18) << 1) | 2662 (info->default_power2 & 7)); 2663 } 2664 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr); 2665 2666 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54); 2667 if (rf->channel <= 14) { 2668 rfcsr = 0; 2669 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2670 info->default_power3 & 0x1f); 2671 } else { 2672 if (rt2x00_is_usb(rt2x00dev)) 2673 rfcsr = 0x40; 2674 2675 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2676 ((info->default_power3 & 0x18) << 1) | 2677 (info->default_power3 & 7)); 2678 } 2679 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr); 2680 2681 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2682 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2683 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2684 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2685 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2686 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2687 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2688 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2689 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2690 2691 switch (rt2x00dev->default_ant.tx_chain_num) { 2692 case 3: 2693 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2694 /* fallthrough */ 2695 case 2: 2696 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2697 /* fallthrough */ 2698 case 1: 2699 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2700 break; 2701 } 2702 2703 switch (rt2x00dev->default_ant.rx_chain_num) { 2704 case 3: 2705 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2706 /* fallthrough */ 2707 case 2: 2708 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2709 /* fallthrough */ 2710 case 1: 2711 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2712 break; 2713 } 2714 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2715 2716 rt2800_freq_cal_mode1(rt2x00dev); 2717 2718 if (conf_is_ht40(conf)) { 2719 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40, 2720 RFCSR24_TX_AGC_FC); 2721 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40, 2722 RFCSR24_TX_H20M); 2723 } else { 2724 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20, 2725 RFCSR24_TX_AGC_FC); 2726 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20, 2727 RFCSR24_TX_H20M); 2728 } 2729 2730 /* NOTE: the reference driver does not writes the new value 2731 * back to RFCSR 32 2732 */ 2733 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32); 2734 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc); 2735 2736 if (rf->channel <= 14) 2737 rfcsr = 0xa0; 2738 else 2739 rfcsr = 0x80; 2740 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2741 2742 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2743 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m); 2744 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m); 2745 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2746 2747 /* Band selection */ 2748 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 2749 if (rf->channel <= 14) 2750 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 2751 else 2752 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 2753 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 2754 2755 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34); 2756 if (rf->channel <= 14) 2757 rfcsr = 0x3c; 2758 else 2759 rfcsr = 0x20; 2760 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 2761 2762 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2763 if (rf->channel <= 14) 2764 rfcsr = 0x1a; 2765 else 2766 rfcsr = 0x12; 2767 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2768 2769 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2770 if (rf->channel >= 1 && rf->channel <= 14) 2771 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2772 else if (rf->channel >= 36 && rf->channel <= 64) 2773 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2774 else if (rf->channel >= 100 && rf->channel <= 128) 2775 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2776 else 2777 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2778 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2779 2780 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2781 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 2782 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2783 2784 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 2785 2786 if (rf->channel <= 14) { 2787 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 2788 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 2789 } else { 2790 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8); 2791 rt2800_rfcsr_write(rt2x00dev, 13, 0x23); 2792 } 2793 2794 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2795 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1); 2796 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2797 2798 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2799 if (rf->channel <= 14) { 2800 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5); 2801 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3); 2802 } else { 2803 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4); 2804 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2); 2805 } 2806 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2807 2808 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2809 if (rf->channel <= 14) 2810 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3); 2811 else 2812 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2); 2813 2814 if (txbf_enabled) 2815 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1); 2816 2817 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2818 2819 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 2820 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0); 2821 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2822 2823 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 2824 if (rf->channel <= 14) 2825 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b); 2826 else 2827 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f); 2828 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr); 2829 2830 if (rf->channel <= 14) { 2831 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 2832 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 2833 } else { 2834 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 2835 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 2836 } 2837 2838 /* Initiate VCO calibration */ 2839 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2840 if (rf->channel <= 14) { 2841 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2842 } else { 2843 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1); 2844 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1); 2845 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1); 2846 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1); 2847 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1); 2848 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2849 } 2850 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2851 2852 if (rf->channel >= 1 && rf->channel <= 14) { 2853 rfcsr = 0x23; 2854 if (txbf_enabled) 2855 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2856 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2857 2858 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 2859 } else if (rf->channel >= 36 && rf->channel <= 64) { 2860 rfcsr = 0x36; 2861 if (txbf_enabled) 2862 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2863 rt2800_rfcsr_write(rt2x00dev, 39, 0x36); 2864 2865 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb); 2866 } else if (rf->channel >= 100 && rf->channel <= 128) { 2867 rfcsr = 0x32; 2868 if (txbf_enabled) 2869 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2870 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2871 2872 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3); 2873 } else { 2874 rfcsr = 0x30; 2875 if (txbf_enabled) 2876 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2877 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2878 2879 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b); 2880 } 2881 } 2882 2883 #define POWER_BOUND 0x27 2884 #define POWER_BOUND_5G 0x2b 2885 2886 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev, 2887 struct ieee80211_conf *conf, 2888 struct rf_channel *rf, 2889 struct channel_info *info) 2890 { 2891 u8 rfcsr; 2892 2893 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2894 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2895 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2896 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 2897 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2898 2899 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2900 if (info->default_power1 > POWER_BOUND) 2901 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 2902 else 2903 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2904 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2905 2906 rt2800_freq_cal_mode1(rt2x00dev); 2907 2908 if (rf->channel <= 14) { 2909 if (rf->channel == 6) 2910 rt2800_bbp_write(rt2x00dev, 68, 0x0c); 2911 else 2912 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 2913 2914 if (rf->channel >= 1 && rf->channel <= 6) 2915 rt2800_bbp_write(rt2x00dev, 59, 0x0f); 2916 else if (rf->channel >= 7 && rf->channel <= 11) 2917 rt2800_bbp_write(rt2x00dev, 59, 0x0e); 2918 else if (rf->channel >= 12 && rf->channel <= 14) 2919 rt2800_bbp_write(rt2x00dev, 59, 0x0d); 2920 } 2921 } 2922 2923 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev, 2924 struct ieee80211_conf *conf, 2925 struct rf_channel *rf, 2926 struct channel_info *info) 2927 { 2928 u8 rfcsr; 2929 2930 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2931 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2932 2933 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 2934 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 2935 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 2936 2937 if (info->default_power1 > POWER_BOUND) 2938 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND); 2939 else 2940 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1); 2941 2942 if (info->default_power2 > POWER_BOUND) 2943 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND); 2944 else 2945 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2); 2946 2947 rt2800_freq_cal_mode1(rt2x00dev); 2948 2949 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2950 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2951 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2952 2953 if ( rt2x00dev->default_ant.tx_chain_num == 2 ) 2954 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2955 else 2956 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2957 2958 if ( rt2x00dev->default_ant.rx_chain_num == 2 ) 2959 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2960 else 2961 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2962 2963 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2964 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2965 2966 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2967 2968 rt2800_rfcsr_write(rt2x00dev, 31, 80); 2969 } 2970 2971 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 2972 struct ieee80211_conf *conf, 2973 struct rf_channel *rf, 2974 struct channel_info *info) 2975 { 2976 u8 rfcsr; 2977 int idx = rf->channel-1; 2978 2979 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2980 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2981 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2982 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 2983 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2984 2985 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2986 if (info->default_power1 > POWER_BOUND) 2987 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 2988 else 2989 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2990 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2991 2992 if (rt2x00_rt(rt2x00dev, RT5392)) { 2993 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 2994 if (info->default_power2 > POWER_BOUND) 2995 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND); 2996 else 2997 rt2x00_set_field8(&rfcsr, RFCSR50_TX, 2998 info->default_power2); 2999 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3000 } 3001 3002 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3003 if (rt2x00_rt(rt2x00dev, RT5392)) { 3004 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3005 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3006 } 3007 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3008 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3009 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3010 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3011 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3012 3013 rt2800_freq_cal_mode1(rt2x00dev); 3014 3015 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 3016 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3017 /* r55/r59 value array of channel 1~14 */ 3018 static const char r55_bt_rev[] = {0x83, 0x83, 3019 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, 3020 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; 3021 static const char r59_bt_rev[] = {0x0e, 0x0e, 3022 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, 3023 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; 3024 3025 rt2800_rfcsr_write(rt2x00dev, 55, 3026 r55_bt_rev[idx]); 3027 rt2800_rfcsr_write(rt2x00dev, 59, 3028 r59_bt_rev[idx]); 3029 } else { 3030 static const char r59_bt[] = {0x8b, 0x8b, 0x8b, 3031 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, 3032 0x88, 0x88, 0x86, 0x85, 0x84}; 3033 3034 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); 3035 } 3036 } else { 3037 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3038 static const char r55_nonbt_rev[] = {0x23, 0x23, 3039 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, 3040 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; 3041 static const char r59_nonbt_rev[] = {0x07, 0x07, 3042 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 3043 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; 3044 3045 rt2800_rfcsr_write(rt2x00dev, 55, 3046 r55_nonbt_rev[idx]); 3047 rt2800_rfcsr_write(rt2x00dev, 59, 3048 r59_nonbt_rev[idx]); 3049 } else if (rt2x00_rt(rt2x00dev, RT5390) || 3050 rt2x00_rt(rt2x00dev, RT5392) || 3051 rt2x00_rt(rt2x00dev, RT6352)) { 3052 static const char r59_non_bt[] = {0x8f, 0x8f, 3053 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, 3054 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; 3055 3056 rt2800_rfcsr_write(rt2x00dev, 59, 3057 r59_non_bt[idx]); 3058 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 3059 static const char r59_non_bt[] = {0x0b, 0x0b, 3060 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a, 3061 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06}; 3062 3063 rt2800_rfcsr_write(rt2x00dev, 59, 3064 r59_non_bt[idx]); 3065 } 3066 } 3067 } 3068 3069 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, 3070 struct ieee80211_conf *conf, 3071 struct rf_channel *rf, 3072 struct channel_info *info) 3073 { 3074 u8 rfcsr, ep_reg; 3075 u32 reg; 3076 int power_bound; 3077 3078 /* TODO */ 3079 const bool is_11b = false; 3080 const bool is_type_ep = false; 3081 3082 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 3083 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3084 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0); 3085 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 3086 3087 /* Order of values on rf_channel entry: N, K, mod, R */ 3088 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff); 3089 3090 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9); 3091 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf); 3092 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8); 3093 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2); 3094 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr); 3095 3096 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3097 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1); 3098 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3); 3099 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3100 3101 if (rf->channel <= 14) { 3102 rt2800_rfcsr_write(rt2x00dev, 10, 0x90); 3103 /* FIXME: RF11 owerwrite ? */ 3104 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A); 3105 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 3106 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3107 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3108 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A); 3109 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 3110 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3111 rt2800_rfcsr_write(rt2x00dev, 36, 0x80); 3112 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 3113 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 3114 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B); 3115 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D); 3116 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B); 3117 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5); 3118 rt2800_rfcsr_write(rt2x00dev, 43, 0x72); 3119 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E); 3120 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2); 3121 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B); 3122 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 3123 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E); 3124 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 3125 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 3126 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1); 3127 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 3128 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 3129 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 3130 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 3131 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 3132 3133 /* TODO RF27 <- tssi */ 3134 3135 rfcsr = rf->channel <= 10 ? 0x07 : 0x06; 3136 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 3137 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr); 3138 3139 if (is_11b) { 3140 /* CCK */ 3141 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8); 3142 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0); 3143 if (is_type_ep) 3144 rt2800_rfcsr_write(rt2x00dev, 55, 0x06); 3145 else 3146 rt2800_rfcsr_write(rt2x00dev, 55, 0x47); 3147 } else { 3148 /* OFDM */ 3149 if (is_type_ep) 3150 rt2800_rfcsr_write(rt2x00dev, 55, 0x03); 3151 else 3152 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 3153 } 3154 3155 power_bound = POWER_BOUND; 3156 ep_reg = 0x2; 3157 } else { 3158 rt2800_rfcsr_write(rt2x00dev, 10, 0x97); 3159 /* FIMXE: RF11 overwrite */ 3160 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 3161 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF); 3162 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3163 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 3164 rt2800_rfcsr_write(rt2x00dev, 37, 0x04); 3165 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 3166 rt2800_rfcsr_write(rt2x00dev, 40, 0x42); 3167 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB); 3168 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7); 3169 rt2800_rfcsr_write(rt2x00dev, 45, 0x41); 3170 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 3171 rt2800_rfcsr_write(rt2x00dev, 57, 0x77); 3172 rt2800_rfcsr_write(rt2x00dev, 60, 0x05); 3173 rt2800_rfcsr_write(rt2x00dev, 61, 0x01); 3174 3175 /* TODO RF27 <- tssi */ 3176 3177 if (rf->channel >= 36 && rf->channel <= 64) { 3178 3179 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E); 3180 rt2800_rfcsr_write(rt2x00dev, 13, 0x22); 3181 rt2800_rfcsr_write(rt2x00dev, 22, 0x60); 3182 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F); 3183 if (rf->channel <= 50) 3184 rt2800_rfcsr_write(rt2x00dev, 24, 0x09); 3185 else if (rf->channel >= 52) 3186 rt2800_rfcsr_write(rt2x00dev, 24, 0x07); 3187 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C); 3188 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B); 3189 rt2800_rfcsr_write(rt2x00dev, 44, 0X40); 3190 rt2800_rfcsr_write(rt2x00dev, 46, 0X00); 3191 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE); 3192 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C); 3193 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8); 3194 if (rf->channel <= 50) { 3195 rt2800_rfcsr_write(rt2x00dev, 55, 0x06), 3196 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3); 3197 } else if (rf->channel >= 52) { 3198 rt2800_rfcsr_write(rt2x00dev, 55, 0x04); 3199 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3200 } 3201 3202 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3203 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F); 3204 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3205 3206 } else if (rf->channel >= 100 && rf->channel <= 165) { 3207 3208 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E); 3209 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3210 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3211 if (rf->channel <= 153) { 3212 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C); 3213 rt2800_rfcsr_write(rt2x00dev, 24, 0x06); 3214 } else if (rf->channel >= 155) { 3215 rt2800_rfcsr_write(rt2x00dev, 23, 0x38); 3216 rt2800_rfcsr_write(rt2x00dev, 24, 0x05); 3217 } 3218 if (rf->channel <= 138) { 3219 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A); 3220 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B); 3221 rt2800_rfcsr_write(rt2x00dev, 44, 0x20); 3222 rt2800_rfcsr_write(rt2x00dev, 46, 0x18); 3223 } else if (rf->channel >= 140) { 3224 rt2800_rfcsr_write(rt2x00dev, 39, 0x18); 3225 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B); 3226 rt2800_rfcsr_write(rt2x00dev, 44, 0x10); 3227 rt2800_rfcsr_write(rt2x00dev, 46, 0X08); 3228 } 3229 if (rf->channel <= 124) 3230 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC); 3231 else if (rf->channel >= 126) 3232 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC); 3233 if (rf->channel <= 138) 3234 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3235 else if (rf->channel >= 140) 3236 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3237 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB); 3238 if (rf->channel <= 138) 3239 rt2800_rfcsr_write(rt2x00dev, 55, 0x01); 3240 else if (rf->channel >= 140) 3241 rt2800_rfcsr_write(rt2x00dev, 55, 0x00); 3242 if (rf->channel <= 128) 3243 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3244 else if (rf->channel >= 130) 3245 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB); 3246 if (rf->channel <= 116) 3247 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D); 3248 else if (rf->channel >= 118) 3249 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3250 if (rf->channel <= 138) 3251 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F); 3252 else if (rf->channel >= 140) 3253 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C); 3254 if (rf->channel <= 116) 3255 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D); 3256 else if (rf->channel >= 118) 3257 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3258 } 3259 3260 power_bound = POWER_BOUND_5G; 3261 ep_reg = 0x3; 3262 } 3263 3264 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3265 if (info->default_power1 > power_bound) 3266 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound); 3267 else 3268 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3269 if (is_type_ep) 3270 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg); 3271 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3272 3273 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3274 if (info->default_power2 > power_bound) 3275 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound); 3276 else 3277 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2); 3278 if (is_type_ep) 3279 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg); 3280 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3281 3282 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3283 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3284 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3285 3286 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 3287 rt2x00dev->default_ant.tx_chain_num >= 1); 3288 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 3289 rt2x00dev->default_ant.tx_chain_num == 2); 3290 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3291 3292 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 3293 rt2x00dev->default_ant.rx_chain_num >= 1); 3294 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 3295 rt2x00dev->default_ant.rx_chain_num == 2); 3296 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3297 3298 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3299 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4); 3300 3301 if (conf_is_ht40(conf)) 3302 rt2800_rfcsr_write(rt2x00dev, 30, 0x16); 3303 else 3304 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 3305 3306 if (!is_11b) { 3307 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3308 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3309 } 3310 3311 /* TODO proper frequency adjustment */ 3312 rt2800_freq_cal_mode1(rt2x00dev); 3313 3314 /* TODO merge with others */ 3315 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3316 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3317 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3318 3319 /* BBP settings */ 3320 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3321 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3322 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3323 3324 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18); 3325 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08); 3326 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38); 3327 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92); 3328 3329 /* GLRT band configuration */ 3330 rt2800_bbp_write(rt2x00dev, 195, 128); 3331 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0); 3332 rt2800_bbp_write(rt2x00dev, 195, 129); 3333 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E); 3334 rt2800_bbp_write(rt2x00dev, 195, 130); 3335 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28); 3336 rt2800_bbp_write(rt2x00dev, 195, 131); 3337 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20); 3338 rt2800_bbp_write(rt2x00dev, 195, 133); 3339 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F); 3340 rt2800_bbp_write(rt2x00dev, 195, 124); 3341 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F); 3342 } 3343 3344 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev, 3345 struct ieee80211_conf *conf, 3346 struct rf_channel *rf, 3347 struct channel_info *info) 3348 { 3349 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 3350 u8 rx_agc_fc, tx_agc_fc; 3351 u8 rfcsr; 3352 3353 /* Frequeny plan setting */ 3354 /* Rdiv setting (set 0x03 if Xtal==20) 3355 * R13[1:0] 3356 */ 3357 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 3358 rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620, 3359 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0); 3360 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 3361 3362 /* N setting 3363 * R20[7:0] in rf->rf1 3364 * R21[0] always 0 3365 */ 3366 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 3367 rfcsr = (rf->rf1 & 0x00ff); 3368 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 3369 3370 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3371 rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0); 3372 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3373 3374 /* K setting (always 0) 3375 * R16[3:0] (RF PLL freq selection) 3376 */ 3377 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3378 rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0); 3379 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3380 3381 /* D setting (always 0) 3382 * R22[2:0] (D=15, R22[2:0]=<111>) 3383 */ 3384 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 3385 rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0); 3386 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 3387 3388 /* Ksd setting 3389 * Ksd: R17<7:0> in rf->rf2 3390 * R18<7:0> in rf->rf3 3391 * R19<1:0> in rf->rf4 3392 */ 3393 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 3394 rfcsr = rf->rf2; 3395 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 3396 3397 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 3398 rfcsr = rf->rf3; 3399 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 3400 3401 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19); 3402 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4); 3403 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr); 3404 3405 /* Default: XO=20MHz , SDM mode */ 3406 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3407 rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80); 3408 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3409 3410 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3411 rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1); 3412 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3413 3414 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3415 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620, 3416 rt2x00dev->default_ant.tx_chain_num != 1); 3417 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3418 3419 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 3420 rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620, 3421 rt2x00dev->default_ant.tx_chain_num != 1); 3422 rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620, 3423 rt2x00dev->default_ant.rx_chain_num != 1); 3424 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 3425 3426 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42); 3427 rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620, 3428 rt2x00dev->default_ant.tx_chain_num != 1); 3429 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 3430 3431 /* RF for DC Cal BW */ 3432 if (conf_is_ht40(conf)) { 3433 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 3434 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 3435 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 3436 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 3437 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 3438 } else { 3439 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20); 3440 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20); 3441 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00); 3442 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20); 3443 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20); 3444 } 3445 3446 if (conf_is_ht40(conf)) { 3447 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08); 3448 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08); 3449 } else { 3450 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28); 3451 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28); 3452 } 3453 3454 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28); 3455 rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40, 3456 conf_is_ht40(conf) && (rf->channel == 11)); 3457 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr); 3458 3459 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) { 3460 if (conf_is_ht40(conf)) { 3461 rx_agc_fc = drv_data->rx_calibration_bw40; 3462 tx_agc_fc = drv_data->tx_calibration_bw40; 3463 } else { 3464 rx_agc_fc = drv_data->rx_calibration_bw20; 3465 tx_agc_fc = drv_data->tx_calibration_bw20; 3466 } 3467 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 3468 rfcsr &= (~0x3F); 3469 rfcsr |= rx_agc_fc; 3470 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr); 3471 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 3472 rfcsr &= (~0x3F); 3473 rfcsr |= rx_agc_fc; 3474 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr); 3475 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6); 3476 rfcsr &= (~0x3F); 3477 rfcsr |= rx_agc_fc; 3478 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr); 3479 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7); 3480 rfcsr &= (~0x3F); 3481 rfcsr |= rx_agc_fc; 3482 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr); 3483 3484 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 3485 rfcsr &= (~0x3F); 3486 rfcsr |= tx_agc_fc; 3487 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr); 3488 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 3489 rfcsr &= (~0x3F); 3490 rfcsr |= tx_agc_fc; 3491 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr); 3492 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58); 3493 rfcsr &= (~0x3F); 3494 rfcsr |= tx_agc_fc; 3495 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr); 3496 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59); 3497 rfcsr &= (~0x3F); 3498 rfcsr |= tx_agc_fc; 3499 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr); 3500 } 3501 } 3502 3503 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev, 3504 struct ieee80211_channel *chan, 3505 int power_level) { 3506 u16 eeprom, target_power, max_power; 3507 u32 mac_sys_ctrl, mac_status; 3508 u32 reg; 3509 u8 bbp; 3510 int i; 3511 3512 /* hardware unit is 0.5dBm, limited to 23.5dBm */ 3513 power_level *= 2; 3514 if (power_level > 0x2f) 3515 power_level = 0x2f; 3516 3517 max_power = chan->max_power * 2; 3518 if (max_power > 0x2f) 3519 max_power = 0x2f; 3520 3521 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0); 3522 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, power_level); 3523 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, power_level); 3524 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, max_power); 3525 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, max_power); 3526 3527 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 3528 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) { 3529 /* init base power by eeprom target power */ 3530 target_power = rt2800_eeprom_read(rt2x00dev, 3531 EEPROM_TXPOWER_INIT); 3532 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power); 3533 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power); 3534 } 3535 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg); 3536 3537 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 3538 rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0); 3539 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 3540 3541 /* Save MAC SYS CTRL registers */ 3542 mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 3543 /* Disable Tx/Rx */ 3544 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 3545 /* Check MAC Tx/Rx idle */ 3546 for (i = 0; i < 10000; i++) { 3547 mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 3548 if (mac_status & 0x3) 3549 usleep_range(50, 200); 3550 else 3551 break; 3552 } 3553 3554 if (i == 10000) 3555 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n"); 3556 3557 if (chan->center_freq > 2457) { 3558 bbp = rt2800_bbp_read(rt2x00dev, 30); 3559 bbp = 0x40; 3560 rt2800_bbp_write(rt2x00dev, 30, bbp); 3561 rt2800_rfcsr_write(rt2x00dev, 39, 0); 3562 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3563 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb); 3564 else 3565 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b); 3566 } else { 3567 bbp = rt2800_bbp_read(rt2x00dev, 30); 3568 bbp = 0x1f; 3569 rt2800_bbp_write(rt2x00dev, 30, bbp); 3570 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 3571 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3572 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb); 3573 else 3574 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); 3575 } 3576 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl); 3577 3578 rt2800_vco_calibration(rt2x00dev); 3579 } 3580 3581 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, 3582 const unsigned int word, 3583 const u8 value) 3584 { 3585 u8 chain, reg; 3586 3587 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) { 3588 reg = rt2800_bbp_read(rt2x00dev, 27); 3589 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); 3590 rt2800_bbp_write(rt2x00dev, 27, reg); 3591 3592 rt2800_bbp_write(rt2x00dev, word, value); 3593 } 3594 } 3595 3596 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel) 3597 { 3598 u8 cal; 3599 3600 /* TX0 IQ Gain */ 3601 rt2800_bbp_write(rt2x00dev, 158, 0x2c); 3602 if (channel <= 14) 3603 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G); 3604 else if (channel >= 36 && channel <= 64) 3605 cal = rt2x00_eeprom_byte(rt2x00dev, 3606 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G); 3607 else if (channel >= 100 && channel <= 138) 3608 cal = rt2x00_eeprom_byte(rt2x00dev, 3609 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G); 3610 else if (channel >= 140 && channel <= 165) 3611 cal = rt2x00_eeprom_byte(rt2x00dev, 3612 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G); 3613 else 3614 cal = 0; 3615 rt2800_bbp_write(rt2x00dev, 159, cal); 3616 3617 /* TX0 IQ Phase */ 3618 rt2800_bbp_write(rt2x00dev, 158, 0x2d); 3619 if (channel <= 14) 3620 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G); 3621 else if (channel >= 36 && channel <= 64) 3622 cal = rt2x00_eeprom_byte(rt2x00dev, 3623 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G); 3624 else if (channel >= 100 && channel <= 138) 3625 cal = rt2x00_eeprom_byte(rt2x00dev, 3626 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G); 3627 else if (channel >= 140 && channel <= 165) 3628 cal = rt2x00_eeprom_byte(rt2x00dev, 3629 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G); 3630 else 3631 cal = 0; 3632 rt2800_bbp_write(rt2x00dev, 159, cal); 3633 3634 /* TX1 IQ Gain */ 3635 rt2800_bbp_write(rt2x00dev, 158, 0x4a); 3636 if (channel <= 14) 3637 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G); 3638 else if (channel >= 36 && channel <= 64) 3639 cal = rt2x00_eeprom_byte(rt2x00dev, 3640 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G); 3641 else if (channel >= 100 && channel <= 138) 3642 cal = rt2x00_eeprom_byte(rt2x00dev, 3643 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G); 3644 else if (channel >= 140 && channel <= 165) 3645 cal = rt2x00_eeprom_byte(rt2x00dev, 3646 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G); 3647 else 3648 cal = 0; 3649 rt2800_bbp_write(rt2x00dev, 159, cal); 3650 3651 /* TX1 IQ Phase */ 3652 rt2800_bbp_write(rt2x00dev, 158, 0x4b); 3653 if (channel <= 14) 3654 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G); 3655 else if (channel >= 36 && channel <= 64) 3656 cal = rt2x00_eeprom_byte(rt2x00dev, 3657 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G); 3658 else if (channel >= 100 && channel <= 138) 3659 cal = rt2x00_eeprom_byte(rt2x00dev, 3660 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G); 3661 else if (channel >= 140 && channel <= 165) 3662 cal = rt2x00_eeprom_byte(rt2x00dev, 3663 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G); 3664 else 3665 cal = 0; 3666 rt2800_bbp_write(rt2x00dev, 159, cal); 3667 3668 /* FIXME: possible RX0, RX1 callibration ? */ 3669 3670 /* RF IQ compensation control */ 3671 rt2800_bbp_write(rt2x00dev, 158, 0x04); 3672 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL); 3673 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3674 3675 /* RF IQ imbalance compensation control */ 3676 rt2800_bbp_write(rt2x00dev, 158, 0x03); 3677 cal = rt2x00_eeprom_byte(rt2x00dev, 3678 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL); 3679 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3680 } 3681 3682 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev, 3683 unsigned int channel, 3684 char txpower) 3685 { 3686 if (rt2x00_rt(rt2x00dev, RT3593)) 3687 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC); 3688 3689 if (channel <= 14) 3690 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER); 3691 3692 if (rt2x00_rt(rt2x00dev, RT3593)) 3693 return clamp_t(char, txpower, MIN_A_TXPOWER_3593, 3694 MAX_A_TXPOWER_3593); 3695 else 3696 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER); 3697 } 3698 3699 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 3700 struct ieee80211_conf *conf, 3701 struct rf_channel *rf, 3702 struct channel_info *info) 3703 { 3704 u32 reg; 3705 u32 tx_pin; 3706 u8 bbp, rfcsr; 3707 3708 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3709 info->default_power1); 3710 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3711 info->default_power2); 3712 if (rt2x00dev->default_ant.tx_chain_num > 2) 3713 info->default_power3 = 3714 rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3715 info->default_power3); 3716 3717 switch (rt2x00dev->chip.rf) { 3718 case RF2020: 3719 case RF3020: 3720 case RF3021: 3721 case RF3022: 3722 case RF3320: 3723 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 3724 break; 3725 case RF3052: 3726 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); 3727 break; 3728 case RF3053: 3729 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info); 3730 break; 3731 case RF3290: 3732 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info); 3733 break; 3734 case RF3322: 3735 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); 3736 break; 3737 case RF3070: 3738 case RF5350: 3739 case RF5360: 3740 case RF5362: 3741 case RF5370: 3742 case RF5372: 3743 case RF5390: 3744 case RF5392: 3745 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); 3746 break; 3747 case RF5592: 3748 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info); 3749 break; 3750 case RF7620: 3751 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info); 3752 break; 3753 default: 3754 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 3755 } 3756 3757 if (rt2x00_rf(rt2x00dev, RF3070) || 3758 rt2x00_rf(rt2x00dev, RF3290) || 3759 rt2x00_rf(rt2x00dev, RF3322) || 3760 rt2x00_rf(rt2x00dev, RF5350) || 3761 rt2x00_rf(rt2x00dev, RF5360) || 3762 rt2x00_rf(rt2x00dev, RF5362) || 3763 rt2x00_rf(rt2x00dev, RF5370) || 3764 rt2x00_rf(rt2x00dev, RF5372) || 3765 rt2x00_rf(rt2x00dev, RF5390) || 3766 rt2x00_rf(rt2x00dev, RF5392)) { 3767 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 3768 if (rt2x00_rf(rt2x00dev, RF3322)) { 3769 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M, 3770 conf_is_ht40(conf)); 3771 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M, 3772 conf_is_ht40(conf)); 3773 } else { 3774 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 3775 conf_is_ht40(conf)); 3776 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 3777 conf_is_ht40(conf)); 3778 } 3779 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 3780 3781 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3782 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3783 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3784 } 3785 3786 /* 3787 * Change BBP settings 3788 */ 3789 3790 if (rt2x00_rt(rt2x00dev, RT3352)) { 3791 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3792 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3793 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3794 3795 rt2800_bbp_write(rt2x00dev, 27, 0x0); 3796 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 3797 rt2800_bbp_write(rt2x00dev, 27, 0x20); 3798 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 3799 rt2800_bbp_write(rt2x00dev, 86, 0x38); 3800 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 3801 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 3802 if (rf->channel > 14) { 3803 /* Disable CCK Packet detection on 5GHz */ 3804 rt2800_bbp_write(rt2x00dev, 70, 0x00); 3805 } else { 3806 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 3807 } 3808 3809 if (conf_is_ht40(conf)) 3810 rt2800_bbp_write(rt2x00dev, 105, 0x04); 3811 else 3812 rt2800_bbp_write(rt2x00dev, 105, 0x34); 3813 3814 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3815 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3816 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3817 rt2800_bbp_write(rt2x00dev, 77, 0x98); 3818 } else { 3819 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3820 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3821 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3822 rt2800_bbp_write(rt2x00dev, 86, 0); 3823 } 3824 3825 if (rf->channel <= 14) { 3826 if (!rt2x00_rt(rt2x00dev, RT5390) && 3827 !rt2x00_rt(rt2x00dev, RT5392) && 3828 !rt2x00_rt(rt2x00dev, RT6352)) { 3829 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 3830 rt2800_bbp_write(rt2x00dev, 82, 0x62); 3831 rt2800_bbp_write(rt2x00dev, 75, 0x46); 3832 } else { 3833 if (rt2x00_rt(rt2x00dev, RT3593)) 3834 rt2800_bbp_write(rt2x00dev, 82, 0x62); 3835 else 3836 rt2800_bbp_write(rt2x00dev, 82, 0x84); 3837 rt2800_bbp_write(rt2x00dev, 75, 0x50); 3838 } 3839 if (rt2x00_rt(rt2x00dev, RT3593)) 3840 rt2800_bbp_write(rt2x00dev, 83, 0x8a); 3841 } 3842 3843 } else { 3844 if (rt2x00_rt(rt2x00dev, RT3572)) 3845 rt2800_bbp_write(rt2x00dev, 82, 0x94); 3846 else if (rt2x00_rt(rt2x00dev, RT3593)) 3847 rt2800_bbp_write(rt2x00dev, 82, 0x82); 3848 else if (!rt2x00_rt(rt2x00dev, RT6352)) 3849 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 3850 3851 if (rt2x00_rt(rt2x00dev, RT3593)) 3852 rt2800_bbp_write(rt2x00dev, 83, 0x9a); 3853 3854 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) 3855 rt2800_bbp_write(rt2x00dev, 75, 0x46); 3856 else 3857 rt2800_bbp_write(rt2x00dev, 75, 0x50); 3858 } 3859 3860 reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG); 3861 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); 3862 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); 3863 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); 3864 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); 3865 3866 if (rt2x00_rt(rt2x00dev, RT3572)) 3867 rt2800_rfcsr_write(rt2x00dev, 8, 0); 3868 3869 if (rt2x00_rt(rt2x00dev, RT6352)) { 3870 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 3871 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); 3872 } else { 3873 tx_pin = 0; 3874 } 3875 3876 switch (rt2x00dev->default_ant.tx_chain_num) { 3877 case 3: 3878 /* Turn on tertiary PAs */ 3879 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 3880 rf->channel > 14); 3881 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 3882 rf->channel <= 14); 3883 /* fall-through */ 3884 case 2: 3885 /* Turn on secondary PAs */ 3886 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 3887 rf->channel > 14); 3888 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 3889 rf->channel <= 14); 3890 /* fall-through */ 3891 case 1: 3892 /* Turn on primary PAs */ 3893 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 3894 rf->channel > 14); 3895 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) 3896 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 3897 else 3898 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 3899 rf->channel <= 14); 3900 break; 3901 } 3902 3903 switch (rt2x00dev->default_ant.rx_chain_num) { 3904 case 3: 3905 /* Turn on tertiary LNAs */ 3906 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 3907 rf->channel > 14); 3908 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 3909 rf->channel <= 14); 3910 /* fall-through */ 3911 case 2: 3912 /* Turn on secondary LNAs */ 3913 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 3914 rf->channel > 14); 3915 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 3916 rf->channel <= 14); 3917 /* fall-through */ 3918 case 1: 3919 /* Turn on primary LNAs */ 3920 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 3921 rf->channel > 14); 3922 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 3923 rf->channel <= 14); 3924 break; 3925 } 3926 3927 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); 3928 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); 3929 3930 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 3931 3932 if (rt2x00_rt(rt2x00dev, RT3572)) { 3933 rt2800_rfcsr_write(rt2x00dev, 8, 0x80); 3934 3935 /* AGC init */ 3936 if (rf->channel <= 14) 3937 reg = 0x1c + (2 * rt2x00dev->lna_gain); 3938 else 3939 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 3940 3941 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3942 } 3943 3944 if (rt2x00_rt(rt2x00dev, RT3593)) { 3945 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 3946 3947 /* Band selection */ 3948 if (rt2x00_is_usb(rt2x00dev) || 3949 rt2x00_is_pcie(rt2x00dev)) { 3950 /* GPIO #8 controls all paths */ 3951 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); 3952 if (rf->channel <= 14) 3953 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); 3954 else 3955 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); 3956 } 3957 3958 /* LNA PE control. */ 3959 if (rt2x00_is_usb(rt2x00dev)) { 3960 /* GPIO #4 controls PE0 and PE1, 3961 * GPIO #7 controls PE2 3962 */ 3963 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 3964 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 3965 3966 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 3967 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 3968 } else if (rt2x00_is_pcie(rt2x00dev)) { 3969 /* GPIO #4 controls PE0, PE1 and PE2 */ 3970 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 3971 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 3972 } 3973 3974 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 3975 3976 /* AGC init */ 3977 if (rf->channel <= 14) 3978 reg = 0x1c + 2 * rt2x00dev->lna_gain; 3979 else 3980 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 3981 3982 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3983 3984 usleep_range(1000, 1500); 3985 } 3986 3987 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) { 3988 reg = 0x10; 3989 if (!conf_is_ht40(conf)) { 3990 if (rt2x00_rt(rt2x00dev, RT6352) && 3991 rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 3992 reg |= 0x5; 3993 } else { 3994 reg |= 0xa; 3995 } 3996 } 3997 rt2800_bbp_write(rt2x00dev, 195, 141); 3998 rt2800_bbp_write(rt2x00dev, 196, reg); 3999 4000 /* AGC init. 4001 * Despite the vendor driver using different values here for 4002 * RT6352 chip, we use 0x1c for now. This may have to be changed 4003 * once TSSI got implemented. 4004 */ 4005 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain; 4006 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4007 4008 rt2800_iq_calibrate(rt2x00dev, rf->channel); 4009 } 4010 4011 bbp = rt2800_bbp_read(rt2x00dev, 4); 4012 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 4013 rt2800_bbp_write(rt2x00dev, 4, bbp); 4014 4015 bbp = rt2800_bbp_read(rt2x00dev, 3); 4016 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); 4017 rt2800_bbp_write(rt2x00dev, 3, bbp); 4018 4019 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 4020 if (conf_is_ht40(conf)) { 4021 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 4022 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4023 rt2800_bbp_write(rt2x00dev, 73, 0x16); 4024 } else { 4025 rt2800_bbp_write(rt2x00dev, 69, 0x16); 4026 rt2800_bbp_write(rt2x00dev, 70, 0x08); 4027 rt2800_bbp_write(rt2x00dev, 73, 0x11); 4028 } 4029 } 4030 4031 usleep_range(1000, 1500); 4032 4033 /* 4034 * Clear channel statistic counters 4035 */ 4036 reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 4037 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 4038 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 4039 4040 /* 4041 * Clear update flag 4042 */ 4043 if (rt2x00_rt(rt2x00dev, RT3352) || 4044 rt2x00_rt(rt2x00dev, RT5350)) { 4045 bbp = rt2800_bbp_read(rt2x00dev, 49); 4046 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0); 4047 rt2800_bbp_write(rt2x00dev, 49, bbp); 4048 } 4049 } 4050 4051 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) 4052 { 4053 u8 tssi_bounds[9]; 4054 u8 current_tssi; 4055 u16 eeprom; 4056 u8 step; 4057 int i; 4058 4059 /* 4060 * First check if temperature compensation is supported. 4061 */ 4062 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 4063 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC)) 4064 return 0; 4065 4066 /* 4067 * Read TSSI boundaries for temperature compensation from 4068 * the EEPROM. 4069 * 4070 * Array idx 0 1 2 3 4 5 6 7 8 4071 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4 4072 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 4073 */ 4074 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 4075 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1); 4076 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4077 EEPROM_TSSI_BOUND_BG1_MINUS4); 4078 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4079 EEPROM_TSSI_BOUND_BG1_MINUS3); 4080 4081 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2); 4082 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4083 EEPROM_TSSI_BOUND_BG2_MINUS2); 4084 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4085 EEPROM_TSSI_BOUND_BG2_MINUS1); 4086 4087 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3); 4088 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4089 EEPROM_TSSI_BOUND_BG3_REF); 4090 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4091 EEPROM_TSSI_BOUND_BG3_PLUS1); 4092 4093 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4); 4094 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4095 EEPROM_TSSI_BOUND_BG4_PLUS2); 4096 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4097 EEPROM_TSSI_BOUND_BG4_PLUS3); 4098 4099 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5); 4100 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4101 EEPROM_TSSI_BOUND_BG5_PLUS4); 4102 4103 step = rt2x00_get_field16(eeprom, 4104 EEPROM_TSSI_BOUND_BG5_AGC_STEP); 4105 } else { 4106 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1); 4107 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4108 EEPROM_TSSI_BOUND_A1_MINUS4); 4109 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4110 EEPROM_TSSI_BOUND_A1_MINUS3); 4111 4112 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2); 4113 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4114 EEPROM_TSSI_BOUND_A2_MINUS2); 4115 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4116 EEPROM_TSSI_BOUND_A2_MINUS1); 4117 4118 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3); 4119 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4120 EEPROM_TSSI_BOUND_A3_REF); 4121 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4122 EEPROM_TSSI_BOUND_A3_PLUS1); 4123 4124 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4); 4125 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4126 EEPROM_TSSI_BOUND_A4_PLUS2); 4127 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4128 EEPROM_TSSI_BOUND_A4_PLUS3); 4129 4130 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5); 4131 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4132 EEPROM_TSSI_BOUND_A5_PLUS4); 4133 4134 step = rt2x00_get_field16(eeprom, 4135 EEPROM_TSSI_BOUND_A5_AGC_STEP); 4136 } 4137 4138 /* 4139 * Check if temperature compensation is supported. 4140 */ 4141 if (tssi_bounds[4] == 0xff || step == 0xff) 4142 return 0; 4143 4144 /* 4145 * Read current TSSI (BBP 49). 4146 */ 4147 current_tssi = rt2800_bbp_read(rt2x00dev, 49); 4148 4149 /* 4150 * Compare TSSI value (BBP49) with the compensation boundaries 4151 * from the EEPROM and increase or decrease tx power. 4152 */ 4153 for (i = 0; i <= 3; i++) { 4154 if (current_tssi > tssi_bounds[i]) 4155 break; 4156 } 4157 4158 if (i == 4) { 4159 for (i = 8; i >= 5; i--) { 4160 if (current_tssi < tssi_bounds[i]) 4161 break; 4162 } 4163 } 4164 4165 return (i - 4) * step; 4166 } 4167 4168 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, 4169 enum nl80211_band band) 4170 { 4171 u16 eeprom; 4172 u8 comp_en; 4173 u8 comp_type; 4174 int comp_value = 0; 4175 4176 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA); 4177 4178 /* 4179 * HT40 compensation not required. 4180 */ 4181 if (eeprom == 0xffff || 4182 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4183 return 0; 4184 4185 if (band == NL80211_BAND_2GHZ) { 4186 comp_en = rt2x00_get_field16(eeprom, 4187 EEPROM_TXPOWER_DELTA_ENABLE_2G); 4188 if (comp_en) { 4189 comp_type = rt2x00_get_field16(eeprom, 4190 EEPROM_TXPOWER_DELTA_TYPE_2G); 4191 comp_value = rt2x00_get_field16(eeprom, 4192 EEPROM_TXPOWER_DELTA_VALUE_2G); 4193 if (!comp_type) 4194 comp_value = -comp_value; 4195 } 4196 } else { 4197 comp_en = rt2x00_get_field16(eeprom, 4198 EEPROM_TXPOWER_DELTA_ENABLE_5G); 4199 if (comp_en) { 4200 comp_type = rt2x00_get_field16(eeprom, 4201 EEPROM_TXPOWER_DELTA_TYPE_5G); 4202 comp_value = rt2x00_get_field16(eeprom, 4203 EEPROM_TXPOWER_DELTA_VALUE_5G); 4204 if (!comp_type) 4205 comp_value = -comp_value; 4206 } 4207 } 4208 4209 return comp_value; 4210 } 4211 4212 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev, 4213 int power_level, int max_power) 4214 { 4215 int delta; 4216 4217 if (rt2x00_has_cap_power_limit(rt2x00dev)) 4218 return 0; 4219 4220 /* 4221 * XXX: We don't know the maximum transmit power of our hardware since 4222 * the EEPROM doesn't expose it. We only know that we are calibrated 4223 * to 100% tx power. 4224 * 4225 * Hence, we assume the regulatory limit that cfg80211 calulated for 4226 * the current channel is our maximum and if we are requested to lower 4227 * the value we just reduce our tx power accordingly. 4228 */ 4229 delta = power_level - max_power; 4230 return min(delta, 0); 4231 } 4232 4233 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, 4234 enum nl80211_band band, int power_level, 4235 u8 txpower, int delta) 4236 { 4237 u16 eeprom; 4238 u8 criterion; 4239 u8 eirp_txpower; 4240 u8 eirp_txpower_criterion; 4241 u8 reg_limit; 4242 4243 if (rt2x00_rt(rt2x00dev, RT3593)) 4244 return min_t(u8, txpower, 0xc); 4245 4246 if (rt2x00_has_cap_power_limit(rt2x00dev)) { 4247 /* 4248 * Check if eirp txpower exceed txpower_limit. 4249 * We use OFDM 6M as criterion and its eirp txpower 4250 * is stored at EEPROM_EIRP_MAX_TX_POWER. 4251 * .11b data rate need add additional 4dbm 4252 * when calculating eirp txpower. 4253 */ 4254 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4255 EEPROM_TXPOWER_BYRATE, 4256 1); 4257 criterion = rt2x00_get_field16(eeprom, 4258 EEPROM_TXPOWER_BYRATE_RATE0); 4259 4260 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 4261 4262 if (band == NL80211_BAND_2GHZ) 4263 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4264 EEPROM_EIRP_MAX_TX_POWER_2GHZ); 4265 else 4266 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4267 EEPROM_EIRP_MAX_TX_POWER_5GHZ); 4268 4269 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) + 4270 (is_rate_b ? 4 : 0) + delta; 4271 4272 reg_limit = (eirp_txpower > power_level) ? 4273 (eirp_txpower - power_level) : 0; 4274 } else 4275 reg_limit = 0; 4276 4277 txpower = max(0, txpower + delta - reg_limit); 4278 return min_t(u8, txpower, 0xc); 4279 } 4280 4281 4282 enum { 4283 TX_PWR_CFG_0_IDX, 4284 TX_PWR_CFG_1_IDX, 4285 TX_PWR_CFG_2_IDX, 4286 TX_PWR_CFG_3_IDX, 4287 TX_PWR_CFG_4_IDX, 4288 TX_PWR_CFG_5_IDX, 4289 TX_PWR_CFG_6_IDX, 4290 TX_PWR_CFG_7_IDX, 4291 TX_PWR_CFG_8_IDX, 4292 TX_PWR_CFG_9_IDX, 4293 TX_PWR_CFG_0_EXT_IDX, 4294 TX_PWR_CFG_1_EXT_IDX, 4295 TX_PWR_CFG_2_EXT_IDX, 4296 TX_PWR_CFG_3_EXT_IDX, 4297 TX_PWR_CFG_4_EXT_IDX, 4298 TX_PWR_CFG_IDX_COUNT, 4299 }; 4300 4301 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, 4302 struct ieee80211_channel *chan, 4303 int power_level) 4304 { 4305 u8 txpower; 4306 u16 eeprom; 4307 u32 regs[TX_PWR_CFG_IDX_COUNT]; 4308 unsigned int offset; 4309 enum nl80211_band band = chan->band; 4310 int delta; 4311 int i; 4312 4313 memset(regs, '\0', sizeof(regs)); 4314 4315 /* TODO: adapt TX power reduction from the rt28xx code */ 4316 4317 /* calculate temperature compensation delta */ 4318 delta = rt2800_get_gain_calibration_delta(rt2x00dev); 4319 4320 if (band == NL80211_BAND_5GHZ) 4321 offset = 16; 4322 else 4323 offset = 0; 4324 4325 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4326 offset += 8; 4327 4328 /* read the next four txpower values */ 4329 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4330 offset); 4331 4332 /* CCK 1MBS,2MBS */ 4333 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4334 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4335 txpower, delta); 4336 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4337 TX_PWR_CFG_0_CCK1_CH0, txpower); 4338 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4339 TX_PWR_CFG_0_CCK1_CH1, txpower); 4340 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4341 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower); 4342 4343 /* CCK 5.5MBS,11MBS */ 4344 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4345 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4346 txpower, delta); 4347 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4348 TX_PWR_CFG_0_CCK5_CH0, txpower); 4349 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4350 TX_PWR_CFG_0_CCK5_CH1, txpower); 4351 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4352 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower); 4353 4354 /* OFDM 6MBS,9MBS */ 4355 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4356 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4357 txpower, delta); 4358 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4359 TX_PWR_CFG_0_OFDM6_CH0, txpower); 4360 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4361 TX_PWR_CFG_0_OFDM6_CH1, txpower); 4362 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4363 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower); 4364 4365 /* OFDM 12MBS,18MBS */ 4366 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4367 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4368 txpower, delta); 4369 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4370 TX_PWR_CFG_0_OFDM12_CH0, txpower); 4371 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4372 TX_PWR_CFG_0_OFDM12_CH1, txpower); 4373 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4374 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower); 4375 4376 /* read the next four txpower values */ 4377 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4378 offset + 1); 4379 4380 /* OFDM 24MBS,36MBS */ 4381 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4382 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4383 txpower, delta); 4384 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4385 TX_PWR_CFG_1_OFDM24_CH0, txpower); 4386 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4387 TX_PWR_CFG_1_OFDM24_CH1, txpower); 4388 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4389 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower); 4390 4391 /* OFDM 48MBS */ 4392 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4393 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4394 txpower, delta); 4395 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4396 TX_PWR_CFG_1_OFDM48_CH0, txpower); 4397 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4398 TX_PWR_CFG_1_OFDM48_CH1, txpower); 4399 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4400 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower); 4401 4402 /* OFDM 54MBS */ 4403 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4404 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4405 txpower, delta); 4406 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4407 TX_PWR_CFG_7_OFDM54_CH0, txpower); 4408 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4409 TX_PWR_CFG_7_OFDM54_CH1, txpower); 4410 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4411 TX_PWR_CFG_7_OFDM54_CH2, txpower); 4412 4413 /* read the next four txpower values */ 4414 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4415 offset + 2); 4416 4417 /* MCS 0,1 */ 4418 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4419 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4420 txpower, delta); 4421 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4422 TX_PWR_CFG_1_MCS0_CH0, txpower); 4423 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4424 TX_PWR_CFG_1_MCS0_CH1, txpower); 4425 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4426 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower); 4427 4428 /* MCS 2,3 */ 4429 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4430 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4431 txpower, delta); 4432 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4433 TX_PWR_CFG_1_MCS2_CH0, txpower); 4434 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4435 TX_PWR_CFG_1_MCS2_CH1, txpower); 4436 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4437 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower); 4438 4439 /* MCS 4,5 */ 4440 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4441 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4442 txpower, delta); 4443 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4444 TX_PWR_CFG_2_MCS4_CH0, txpower); 4445 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4446 TX_PWR_CFG_2_MCS4_CH1, txpower); 4447 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4448 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower); 4449 4450 /* MCS 6 */ 4451 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4452 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4453 txpower, delta); 4454 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4455 TX_PWR_CFG_2_MCS6_CH0, txpower); 4456 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4457 TX_PWR_CFG_2_MCS6_CH1, txpower); 4458 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4459 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower); 4460 4461 /* read the next four txpower values */ 4462 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4463 offset + 3); 4464 4465 /* MCS 7 */ 4466 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4467 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4468 txpower, delta); 4469 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4470 TX_PWR_CFG_7_MCS7_CH0, txpower); 4471 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4472 TX_PWR_CFG_7_MCS7_CH1, txpower); 4473 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4474 TX_PWR_CFG_7_MCS7_CH2, txpower); 4475 4476 /* MCS 8,9 */ 4477 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4478 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4479 txpower, delta); 4480 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4481 TX_PWR_CFG_2_MCS8_CH0, txpower); 4482 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4483 TX_PWR_CFG_2_MCS8_CH1, txpower); 4484 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4485 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower); 4486 4487 /* MCS 10,11 */ 4488 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4489 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4490 txpower, delta); 4491 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4492 TX_PWR_CFG_2_MCS10_CH0, txpower); 4493 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4494 TX_PWR_CFG_2_MCS10_CH1, txpower); 4495 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4496 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower); 4497 4498 /* MCS 12,13 */ 4499 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4500 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4501 txpower, delta); 4502 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4503 TX_PWR_CFG_3_MCS12_CH0, txpower); 4504 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4505 TX_PWR_CFG_3_MCS12_CH1, txpower); 4506 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4507 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower); 4508 4509 /* read the next four txpower values */ 4510 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4511 offset + 4); 4512 4513 /* MCS 14 */ 4514 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4515 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4516 txpower, delta); 4517 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4518 TX_PWR_CFG_3_MCS14_CH0, txpower); 4519 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4520 TX_PWR_CFG_3_MCS14_CH1, txpower); 4521 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4522 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower); 4523 4524 /* MCS 15 */ 4525 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4526 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4527 txpower, delta); 4528 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4529 TX_PWR_CFG_8_MCS15_CH0, txpower); 4530 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4531 TX_PWR_CFG_8_MCS15_CH1, txpower); 4532 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4533 TX_PWR_CFG_8_MCS15_CH2, txpower); 4534 4535 /* MCS 16,17 */ 4536 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4537 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4538 txpower, delta); 4539 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4540 TX_PWR_CFG_5_MCS16_CH0, txpower); 4541 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4542 TX_PWR_CFG_5_MCS16_CH1, txpower); 4543 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4544 TX_PWR_CFG_5_MCS16_CH2, txpower); 4545 4546 /* MCS 18,19 */ 4547 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4548 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4549 txpower, delta); 4550 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4551 TX_PWR_CFG_5_MCS18_CH0, txpower); 4552 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4553 TX_PWR_CFG_5_MCS18_CH1, txpower); 4554 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4555 TX_PWR_CFG_5_MCS18_CH2, txpower); 4556 4557 /* read the next four txpower values */ 4558 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4559 offset + 5); 4560 4561 /* MCS 20,21 */ 4562 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4563 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4564 txpower, delta); 4565 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4566 TX_PWR_CFG_6_MCS20_CH0, txpower); 4567 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4568 TX_PWR_CFG_6_MCS20_CH1, txpower); 4569 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4570 TX_PWR_CFG_6_MCS20_CH2, txpower); 4571 4572 /* MCS 22 */ 4573 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4574 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4575 txpower, delta); 4576 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4577 TX_PWR_CFG_6_MCS22_CH0, txpower); 4578 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4579 TX_PWR_CFG_6_MCS22_CH1, txpower); 4580 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4581 TX_PWR_CFG_6_MCS22_CH2, txpower); 4582 4583 /* MCS 23 */ 4584 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4585 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4586 txpower, delta); 4587 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4588 TX_PWR_CFG_8_MCS23_CH0, txpower); 4589 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4590 TX_PWR_CFG_8_MCS23_CH1, txpower); 4591 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4592 TX_PWR_CFG_8_MCS23_CH2, txpower); 4593 4594 /* read the next four txpower values */ 4595 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4596 offset + 6); 4597 4598 /* STBC, MCS 0,1 */ 4599 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4600 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4601 txpower, delta); 4602 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4603 TX_PWR_CFG_3_STBC0_CH0, txpower); 4604 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4605 TX_PWR_CFG_3_STBC0_CH1, txpower); 4606 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4607 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower); 4608 4609 /* STBC, MCS 2,3 */ 4610 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4611 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4612 txpower, delta); 4613 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4614 TX_PWR_CFG_3_STBC2_CH0, txpower); 4615 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4616 TX_PWR_CFG_3_STBC2_CH1, txpower); 4617 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4618 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower); 4619 4620 /* STBC, MCS 4,5 */ 4621 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4622 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4623 txpower, delta); 4624 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); 4625 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); 4626 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, 4627 txpower); 4628 4629 /* STBC, MCS 6 */ 4630 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4631 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4632 txpower, delta); 4633 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); 4634 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); 4635 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, 4636 txpower); 4637 4638 /* read the next four txpower values */ 4639 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4640 offset + 7); 4641 4642 /* STBC, MCS 7 */ 4643 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4644 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4645 txpower, delta); 4646 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4647 TX_PWR_CFG_9_STBC7_CH0, txpower); 4648 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4649 TX_PWR_CFG_9_STBC7_CH1, txpower); 4650 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4651 TX_PWR_CFG_9_STBC7_CH2, txpower); 4652 4653 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]); 4654 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]); 4655 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]); 4656 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]); 4657 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]); 4658 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]); 4659 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]); 4660 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]); 4661 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]); 4662 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]); 4663 4664 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT, 4665 regs[TX_PWR_CFG_0_EXT_IDX]); 4666 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT, 4667 regs[TX_PWR_CFG_1_EXT_IDX]); 4668 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT, 4669 regs[TX_PWR_CFG_2_EXT_IDX]); 4670 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT, 4671 regs[TX_PWR_CFG_3_EXT_IDX]); 4672 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT, 4673 regs[TX_PWR_CFG_4_EXT_IDX]); 4674 4675 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++) 4676 rt2x00_dbg(rt2x00dev, 4677 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n", 4678 (band == NL80211_BAND_5GHZ) ? '5' : '2', 4679 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ? 4680 '4' : '2', 4681 (i > TX_PWR_CFG_9_IDX) ? 4682 (i - TX_PWR_CFG_9_IDX - 1) : i, 4683 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "", 4684 (unsigned long) regs[i]); 4685 } 4686 4687 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev, 4688 struct ieee80211_channel *chan, 4689 int power_level) 4690 { 4691 u32 reg, pwreg; 4692 u16 eeprom; 4693 u32 data, gdata; 4694 u8 t, i; 4695 enum nl80211_band band = chan->band; 4696 int delta; 4697 4698 /* Warn user if bw_comp is set in EEPROM */ 4699 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 4700 4701 if (delta) 4702 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n", 4703 delta); 4704 4705 /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit 4706 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor 4707 * driver does as well, though it looks kinda wrong. 4708 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe 4709 * the hardware has a problem handling 0x20, and as the code initially 4710 * used a fixed offset between HT20 and HT40 rates they had to work- 4711 * around that issue and most likely just forgot about it later on. 4712 * Maybe we should use rt2800_get_txpower_bw_comp() here as well, 4713 * however, the corresponding EEPROM value is not respected by the 4714 * vendor driver, so maybe this is rather being taken care of the 4715 * TXALC and the driver doesn't need to handle it...? 4716 * Though this is all very awkward, just do as they did, as that's what 4717 * board vendors expected when they populated the EEPROM... 4718 */ 4719 for (i = 0; i < 5; i++) { 4720 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4721 EEPROM_TXPOWER_BYRATE, 4722 i * 2); 4723 4724 data = eeprom; 4725 4726 t = eeprom & 0x3f; 4727 if (t == 32) 4728 t++; 4729 4730 gdata = t; 4731 4732 t = (eeprom & 0x3f00) >> 8; 4733 if (t == 32) 4734 t++; 4735 4736 gdata |= (t << 8); 4737 4738 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4739 EEPROM_TXPOWER_BYRATE, 4740 (i * 2) + 1); 4741 4742 t = eeprom & 0x3f; 4743 if (t == 32) 4744 t++; 4745 4746 gdata |= (t << 16); 4747 4748 t = (eeprom & 0x3f00) >> 8; 4749 if (t == 32) 4750 t++; 4751 4752 gdata |= (t << 24); 4753 data |= (eeprom << 16); 4754 4755 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) { 4756 /* HT20 */ 4757 if (data != 0xffffffff) 4758 rt2800_register_write(rt2x00dev, 4759 TX_PWR_CFG_0 + (i * 4), 4760 data); 4761 } else { 4762 /* HT40 */ 4763 if (gdata != 0xffffffff) 4764 rt2800_register_write(rt2x00dev, 4765 TX_PWR_CFG_0 + (i * 4), 4766 gdata); 4767 } 4768 } 4769 4770 /* Aparently Ralink ran out of space in the BYRATE calibration section 4771 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x 4772 * registers. As recent 2T chips use 8-bit instead of 4-bit values for 4773 * power-offsets more space would be needed. Ralink decided to keep the 4774 * EEPROM layout untouched and rather have some shared values covering 4775 * multiple bitrates. 4776 * Populate the registers not covered by the EEPROM in the same way the 4777 * vendor driver does. 4778 */ 4779 4780 /* For OFDM 54MBS use value from OFDM 48MBS */ 4781 pwreg = 0; 4782 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1); 4783 t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS); 4784 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t); 4785 4786 /* For MCS 7 use value from MCS 6 */ 4787 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2); 4788 t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7); 4789 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t); 4790 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg); 4791 4792 /* For MCS 15 use value from MCS 14 */ 4793 pwreg = 0; 4794 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3); 4795 t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14); 4796 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t); 4797 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg); 4798 4799 /* For STBC MCS 7 use value from STBC MCS 6 */ 4800 pwreg = 0; 4801 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4); 4802 t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6); 4803 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); 4804 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg); 4805 4806 rt2800_config_alc(rt2x00dev, chan, power_level); 4807 4808 /* TODO: temperature compensation code! */ 4809 } 4810 4811 /* 4812 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and 4813 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values, 4814 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power 4815 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm. 4816 * Reference per rate transmit power values are located in the EEPROM at 4817 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to 4818 * current conditions (i.e. band, bandwidth, temperature, user settings). 4819 */ 4820 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, 4821 struct ieee80211_channel *chan, 4822 int power_level) 4823 { 4824 u8 txpower, r1; 4825 u16 eeprom; 4826 u32 reg, offset; 4827 int i, is_rate_b, delta, power_ctrl; 4828 enum nl80211_band band = chan->band; 4829 4830 /* 4831 * Calculate HT40 compensation. For 40MHz we need to add or subtract 4832 * value read from EEPROM (different for 2GHz and for 5GHz). 4833 */ 4834 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 4835 4836 /* 4837 * Calculate temperature compensation. Depends on measurement of current 4838 * TSSI (Transmitter Signal Strength Indication) we know TX power (due 4839 * to temperature or maybe other factors) is smaller or bigger than 4840 * expected. We adjust it, based on TSSI reference and boundaries values 4841 * provided in EEPROM. 4842 */ 4843 switch (rt2x00dev->chip.rt) { 4844 case RT2860: 4845 case RT2872: 4846 case RT2883: 4847 case RT3070: 4848 case RT3071: 4849 case RT3090: 4850 case RT3572: 4851 delta += rt2800_get_gain_calibration_delta(rt2x00dev); 4852 break; 4853 default: 4854 /* TODO: temperature compensation code for other chips. */ 4855 break; 4856 } 4857 4858 /* 4859 * Decrease power according to user settings, on devices with unknown 4860 * maximum tx power. For other devices we take user power_level into 4861 * consideration on rt2800_compensate_txpower(). 4862 */ 4863 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level, 4864 chan->max_power); 4865 4866 /* 4867 * BBP_R1 controls TX power for all rates, it allow to set the following 4868 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively. 4869 * 4870 * TODO: we do not use +6 dBm option to do not increase power beyond 4871 * regulatory limit, however this could be utilized for devices with 4872 * CAPABILITY_POWER_LIMIT. 4873 */ 4874 if (delta <= -12) { 4875 power_ctrl = 2; 4876 delta += 12; 4877 } else if (delta <= -6) { 4878 power_ctrl = 1; 4879 delta += 6; 4880 } else { 4881 power_ctrl = 0; 4882 } 4883 r1 = rt2800_bbp_read(rt2x00dev, 1); 4884 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl); 4885 rt2800_bbp_write(rt2x00dev, 1, r1); 4886 4887 offset = TX_PWR_CFG_0; 4888 4889 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { 4890 /* just to be safe */ 4891 if (offset > TX_PWR_CFG_4) 4892 break; 4893 4894 reg = rt2800_register_read(rt2x00dev, offset); 4895 4896 /* read the next four txpower values */ 4897 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4898 EEPROM_TXPOWER_BYRATE, 4899 i); 4900 4901 is_rate_b = i ? 0 : 1; 4902 /* 4903 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, 4904 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, 4905 * TX_PWR_CFG_4: unknown 4906 */ 4907 txpower = rt2x00_get_field16(eeprom, 4908 EEPROM_TXPOWER_BYRATE_RATE0); 4909 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4910 power_level, txpower, delta); 4911 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); 4912 4913 /* 4914 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, 4915 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, 4916 * TX_PWR_CFG_4: unknown 4917 */ 4918 txpower = rt2x00_get_field16(eeprom, 4919 EEPROM_TXPOWER_BYRATE_RATE1); 4920 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4921 power_level, txpower, delta); 4922 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); 4923 4924 /* 4925 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS, 4926 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, 4927 * TX_PWR_CFG_4: unknown 4928 */ 4929 txpower = rt2x00_get_field16(eeprom, 4930 EEPROM_TXPOWER_BYRATE_RATE2); 4931 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4932 power_level, txpower, delta); 4933 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); 4934 4935 /* 4936 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, 4937 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, 4938 * TX_PWR_CFG_4: unknown 4939 */ 4940 txpower = rt2x00_get_field16(eeprom, 4941 EEPROM_TXPOWER_BYRATE_RATE3); 4942 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4943 power_level, txpower, delta); 4944 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); 4945 4946 /* read the next four txpower values */ 4947 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4948 EEPROM_TXPOWER_BYRATE, 4949 i + 1); 4950 4951 is_rate_b = 0; 4952 /* 4953 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, 4954 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, 4955 * TX_PWR_CFG_4: unknown 4956 */ 4957 txpower = rt2x00_get_field16(eeprom, 4958 EEPROM_TXPOWER_BYRATE_RATE0); 4959 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4960 power_level, txpower, delta); 4961 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); 4962 4963 /* 4964 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, 4965 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, 4966 * TX_PWR_CFG_4: unknown 4967 */ 4968 txpower = rt2x00_get_field16(eeprom, 4969 EEPROM_TXPOWER_BYRATE_RATE1); 4970 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4971 power_level, txpower, delta); 4972 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); 4973 4974 /* 4975 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, 4976 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, 4977 * TX_PWR_CFG_4: unknown 4978 */ 4979 txpower = rt2x00_get_field16(eeprom, 4980 EEPROM_TXPOWER_BYRATE_RATE2); 4981 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4982 power_level, txpower, delta); 4983 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); 4984 4985 /* 4986 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, 4987 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, 4988 * TX_PWR_CFG_4: unknown 4989 */ 4990 txpower = rt2x00_get_field16(eeprom, 4991 EEPROM_TXPOWER_BYRATE_RATE3); 4992 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4993 power_level, txpower, delta); 4994 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); 4995 4996 rt2800_register_write(rt2x00dev, offset, reg); 4997 4998 /* next TX_PWR_CFG register */ 4999 offset += 4; 5000 } 5001 } 5002 5003 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, 5004 struct ieee80211_channel *chan, 5005 int power_level) 5006 { 5007 if (rt2x00_rt(rt2x00dev, RT3593)) 5008 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level); 5009 else if (rt2x00_rt(rt2x00dev, RT6352)) 5010 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level); 5011 else 5012 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level); 5013 } 5014 5015 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) 5016 { 5017 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan, 5018 rt2x00dev->tx_power); 5019 } 5020 EXPORT_SYMBOL_GPL(rt2800_gain_calibration); 5021 5022 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) 5023 { 5024 u32 tx_pin; 5025 u8 rfcsr; 5026 unsigned long min_sleep = 0; 5027 5028 /* 5029 * A voltage-controlled oscillator(VCO) is an electronic oscillator 5030 * designed to be controlled in oscillation frequency by a voltage 5031 * input. Maybe the temperature will affect the frequency of 5032 * oscillation to be shifted. The VCO calibration will be called 5033 * periodically to adjust the frequency to be precision. 5034 */ 5035 5036 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5037 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE; 5038 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5039 5040 switch (rt2x00dev->chip.rf) { 5041 case RF2020: 5042 case RF3020: 5043 case RF3021: 5044 case RF3022: 5045 case RF3320: 5046 case RF3052: 5047 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 5048 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 5049 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 5050 break; 5051 case RF3053: 5052 case RF3070: 5053 case RF3290: 5054 case RF5350: 5055 case RF5360: 5056 case RF5362: 5057 case RF5370: 5058 case RF5372: 5059 case RF5390: 5060 case RF5392: 5061 case RF5592: 5062 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 5063 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 5064 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 5065 min_sleep = 1000; 5066 break; 5067 case RF7620: 5068 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 5069 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 5070 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4); 5071 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1); 5072 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr); 5073 min_sleep = 2000; 5074 break; 5075 default: 5076 WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration", 5077 rt2x00dev->chip.rf); 5078 return; 5079 } 5080 5081 if (min_sleep > 0) 5082 usleep_range(min_sleep, min_sleep * 2); 5083 5084 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5085 if (rt2x00dev->rf_channel <= 14) { 5086 switch (rt2x00dev->default_ant.tx_chain_num) { 5087 case 3: 5088 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); 5089 /* fall through */ 5090 case 2: 5091 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 5092 /* fall through */ 5093 case 1: 5094 default: 5095 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 5096 break; 5097 } 5098 } else { 5099 switch (rt2x00dev->default_ant.tx_chain_num) { 5100 case 3: 5101 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); 5102 /* fall through */ 5103 case 2: 5104 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 5105 /* fall through */ 5106 case 1: 5107 default: 5108 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); 5109 break; 5110 } 5111 } 5112 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5113 5114 if (rt2x00_rt(rt2x00dev, RT6352)) { 5115 if (rt2x00dev->default_ant.rx_chain_num == 1) { 5116 rt2800_bbp_write(rt2x00dev, 91, 0x07); 5117 rt2800_bbp_write(rt2x00dev, 95, 0x1A); 5118 rt2800_bbp_write(rt2x00dev, 195, 128); 5119 rt2800_bbp_write(rt2x00dev, 196, 0xA0); 5120 rt2800_bbp_write(rt2x00dev, 195, 170); 5121 rt2800_bbp_write(rt2x00dev, 196, 0x12); 5122 rt2800_bbp_write(rt2x00dev, 195, 171); 5123 rt2800_bbp_write(rt2x00dev, 196, 0x10); 5124 } else { 5125 rt2800_bbp_write(rt2x00dev, 91, 0x06); 5126 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 5127 rt2800_bbp_write(rt2x00dev, 195, 128); 5128 rt2800_bbp_write(rt2x00dev, 196, 0xE0); 5129 rt2800_bbp_write(rt2x00dev, 195, 170); 5130 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5131 rt2800_bbp_write(rt2x00dev, 195, 171); 5132 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5133 } 5134 5135 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 5136 rt2800_bbp_write(rt2x00dev, 75, 0x68); 5137 rt2800_bbp_write(rt2x00dev, 76, 0x4C); 5138 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 5139 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 5140 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 5141 } 5142 5143 /* On 11A, We should delay and wait RF/BBP to be stable 5144 * and the appropriate time should be 1000 micro seconds 5145 * 2005/06/05 - On 11G, we also need this delay time. 5146 * Otherwise it's difficult to pass the WHQL. 5147 */ 5148 usleep_range(1000, 1500); 5149 } 5150 } 5151 EXPORT_SYMBOL_GPL(rt2800_vco_calibration); 5152 5153 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, 5154 struct rt2x00lib_conf *libconf) 5155 { 5156 u32 reg; 5157 5158 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 5159 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 5160 libconf->conf->short_frame_max_tx_count); 5161 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 5162 libconf->conf->long_frame_max_tx_count); 5163 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5164 } 5165 5166 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, 5167 struct rt2x00lib_conf *libconf) 5168 { 5169 enum dev_state state = 5170 (libconf->conf->flags & IEEE80211_CONF_PS) ? 5171 STATE_SLEEP : STATE_AWAKE; 5172 u32 reg; 5173 5174 if (state == STATE_SLEEP) { 5175 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); 5176 5177 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5178 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); 5179 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 5180 libconf->conf->listen_interval - 1); 5181 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); 5182 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5183 5184 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5185 } else { 5186 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5187 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 5188 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 5189 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); 5190 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5191 5192 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5193 } 5194 } 5195 5196 void rt2800_config(struct rt2x00_dev *rt2x00dev, 5197 struct rt2x00lib_conf *libconf, 5198 const unsigned int flags) 5199 { 5200 /* Always recalculate LNA gain before changing configuration */ 5201 rt2800_config_lna_gain(rt2x00dev, libconf); 5202 5203 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { 5204 rt2800_config_channel(rt2x00dev, libconf->conf, 5205 &libconf->rf, &libconf->channel); 5206 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5207 libconf->conf->power_level); 5208 } 5209 if (flags & IEEE80211_CONF_CHANGE_POWER) 5210 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5211 libconf->conf->power_level); 5212 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 5213 rt2800_config_retry_limit(rt2x00dev, libconf); 5214 if (flags & IEEE80211_CONF_CHANGE_PS) 5215 rt2800_config_ps(rt2x00dev, libconf); 5216 } 5217 EXPORT_SYMBOL_GPL(rt2800_config); 5218 5219 /* 5220 * Link tuning 5221 */ 5222 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5223 { 5224 u32 reg; 5225 5226 /* 5227 * Update FCS error count from register. 5228 */ 5229 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 5230 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); 5231 } 5232 EXPORT_SYMBOL_GPL(rt2800_link_stats); 5233 5234 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 5235 { 5236 u8 vgc; 5237 5238 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 5239 if (rt2x00_rt(rt2x00dev, RT3070) || 5240 rt2x00_rt(rt2x00dev, RT3071) || 5241 rt2x00_rt(rt2x00dev, RT3090) || 5242 rt2x00_rt(rt2x00dev, RT3290) || 5243 rt2x00_rt(rt2x00dev, RT3390) || 5244 rt2x00_rt(rt2x00dev, RT3572) || 5245 rt2x00_rt(rt2x00dev, RT3593) || 5246 rt2x00_rt(rt2x00dev, RT5390) || 5247 rt2x00_rt(rt2x00dev, RT5392) || 5248 rt2x00_rt(rt2x00dev, RT5592) || 5249 rt2x00_rt(rt2x00dev, RT6352)) 5250 vgc = 0x1c + (2 * rt2x00dev->lna_gain); 5251 else 5252 vgc = 0x2e + rt2x00dev->lna_gain; 5253 } else { /* 5GHZ band */ 5254 if (rt2x00_rt(rt2x00dev, RT3593)) 5255 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3; 5256 else if (rt2x00_rt(rt2x00dev, RT5592)) 5257 vgc = 0x24 + (2 * rt2x00dev->lna_gain); 5258 else { 5259 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 5260 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3; 5261 else 5262 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3; 5263 } 5264 } 5265 5266 return vgc; 5267 } 5268 5269 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, 5270 struct link_qual *qual, u8 vgc_level) 5271 { 5272 if (qual->vgc_level != vgc_level) { 5273 if (rt2x00_rt(rt2x00dev, RT3572) || 5274 rt2x00_rt(rt2x00dev, RT3593)) { 5275 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, 5276 vgc_level); 5277 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5278 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a); 5279 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level); 5280 } else { 5281 rt2800_bbp_write(rt2x00dev, 66, vgc_level); 5282 } 5283 5284 qual->vgc_level = vgc_level; 5285 qual->vgc_level_reg = vgc_level; 5286 } 5287 } 5288 5289 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5290 { 5291 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); 5292 } 5293 EXPORT_SYMBOL_GPL(rt2800_reset_tuner); 5294 5295 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 5296 const u32 count) 5297 { 5298 u8 vgc; 5299 5300 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) 5301 return; 5302 5303 /* When RSSI is better than a certain threshold, increase VGC 5304 * with a chip specific value in order to improve the balance 5305 * between sensibility and noise isolation. 5306 */ 5307 5308 vgc = rt2800_get_default_vgc(rt2x00dev); 5309 5310 switch (rt2x00dev->chip.rt) { 5311 case RT3572: 5312 case RT3593: 5313 if (qual->rssi > -65) { 5314 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) 5315 vgc += 0x20; 5316 else 5317 vgc += 0x10; 5318 } 5319 break; 5320 5321 case RT5592: 5322 if (qual->rssi > -65) 5323 vgc += 0x20; 5324 break; 5325 5326 default: 5327 if (qual->rssi > -80) 5328 vgc += 0x10; 5329 break; 5330 } 5331 5332 rt2800_set_vgc(rt2x00dev, qual, vgc); 5333 } 5334 EXPORT_SYMBOL_GPL(rt2800_link_tuner); 5335 5336 /* 5337 * Initialization functions. 5338 */ 5339 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 5340 { 5341 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5342 u32 reg; 5343 u16 eeprom; 5344 unsigned int i; 5345 int ret; 5346 5347 rt2800_disable_wpdma(rt2x00dev); 5348 5349 ret = rt2800_drv_init_registers(rt2x00dev); 5350 if (ret) 5351 return ret; 5352 5353 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); 5354 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 5355 5356 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 5357 5358 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 5359 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); 5360 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); 5361 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); 5362 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); 5363 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 5364 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 5365 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 5366 5367 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); 5368 5369 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 5370 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); 5371 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 5372 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 5373 5374 if (rt2x00_rt(rt2x00dev, RT3290)) { 5375 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 5376 if (rt2x00_get_field32(reg, WLAN_EN) == 1) { 5377 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); 5378 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 5379 } 5380 5381 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 5382 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { 5383 rt2x00_set_field32(®, LDO0_EN, 1); 5384 rt2x00_set_field32(®, LDO_BGSEL, 3); 5385 rt2800_register_write(rt2x00dev, CMB_CTRL, reg); 5386 } 5387 5388 reg = rt2800_register_read(rt2x00dev, OSC_CTRL); 5389 rt2x00_set_field32(®, OSC_ROSC_EN, 1); 5390 rt2x00_set_field32(®, OSC_CAL_REQ, 1); 5391 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); 5392 rt2800_register_write(rt2x00dev, OSC_CTRL, reg); 5393 5394 reg = rt2800_register_read(rt2x00dev, COEX_CFG0); 5395 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); 5396 rt2800_register_write(rt2x00dev, COEX_CFG0, reg); 5397 5398 reg = rt2800_register_read(rt2x00dev, COEX_CFG2); 5399 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); 5400 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); 5401 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); 5402 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); 5403 rt2800_register_write(rt2x00dev, COEX_CFG2, reg); 5404 5405 reg = rt2800_register_read(rt2x00dev, PLL_CTRL); 5406 rt2x00_set_field32(®, PLL_CONTROL, 1); 5407 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); 5408 } 5409 5410 if (rt2x00_rt(rt2x00dev, RT3071) || 5411 rt2x00_rt(rt2x00dev, RT3090) || 5412 rt2x00_rt(rt2x00dev, RT3290) || 5413 rt2x00_rt(rt2x00dev, RT3390)) { 5414 5415 if (rt2x00_rt(rt2x00dev, RT3290)) 5416 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5417 0x00000404); 5418 else 5419 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5420 0x00000400); 5421 5422 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5423 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 5424 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 5425 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 5426 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5427 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 5428 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5429 0x0000002c); 5430 else 5431 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5432 0x0000000f); 5433 } else { 5434 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5435 } 5436 } else if (rt2x00_rt(rt2x00dev, RT3070)) { 5437 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5438 5439 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 5440 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5441 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); 5442 } else { 5443 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5444 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5445 } 5446 } else if (rt2800_is_305x_soc(rt2x00dev)) { 5447 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5448 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5449 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); 5450 } else if (rt2x00_rt(rt2x00dev, RT3352)) { 5451 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5452 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5453 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5454 } else if (rt2x00_rt(rt2x00dev, RT3572)) { 5455 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5456 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5457 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 5458 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5459 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5460 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) { 5461 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5462 if (rt2x00_get_field16(eeprom, 5463 EEPROM_NIC_CONF1_DAC_TEST)) 5464 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5465 0x0000001f); 5466 else 5467 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5468 0x0000000f); 5469 } else { 5470 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5471 0x00000000); 5472 } 5473 } else if (rt2x00_rt(rt2x00dev, RT5390) || 5474 rt2x00_rt(rt2x00dev, RT5392) || 5475 rt2x00_rt(rt2x00dev, RT6352)) { 5476 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5477 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5478 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5479 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5480 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5481 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5482 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5483 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 5484 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5485 } else if (rt2x00_rt(rt2x00dev, RT6352)) { 5486 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401); 5487 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000); 5488 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5489 rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002); 5490 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F); 5491 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000); 5492 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0); 5493 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0); 5494 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C); 5495 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C); 5496 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 5497 0x3630363A); 5498 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT, 5499 0x3630363A); 5500 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 5501 rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); 5502 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 5503 } else { 5504 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 5505 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5506 } 5507 5508 reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG); 5509 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); 5510 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); 5511 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); 5512 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); 5513 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); 5514 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); 5515 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); 5516 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); 5517 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); 5518 5519 reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG); 5520 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 5521 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); 5522 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 5523 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 5524 5525 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 5526 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 5527 if (rt2x00_is_usb(rt2x00dev)) { 5528 drv_data->max_psdu = 3; 5529 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || 5530 rt2x00_rt(rt2x00dev, RT2883) || 5531 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) { 5532 drv_data->max_psdu = 2; 5533 } else { 5534 drv_data->max_psdu = 1; 5535 } 5536 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu); 5537 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); 5538 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); 5539 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 5540 5541 reg = rt2800_register_read(rt2x00dev, LED_CFG); 5542 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); 5543 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); 5544 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); 5545 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); 5546 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); 5547 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); 5548 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); 5549 rt2800_register_write(rt2x00dev, LED_CFG, reg); 5550 5551 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 5552 5553 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 5554 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); 5555 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); 5556 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); 5557 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); 5558 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); 5559 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); 5560 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5561 5562 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 5563 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); 5564 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); 5565 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); 5566 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); 5567 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); 5568 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 5569 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 5570 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 5571 5572 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 5573 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); 5574 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); 5575 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); 5576 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 5577 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5578 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5579 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5580 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5581 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5582 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); 5583 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 5584 5585 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 5586 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); 5587 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); 5588 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); 5589 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 5590 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5591 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5592 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5593 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5594 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5595 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); 5596 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 5597 5598 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 5599 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 5600 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); 5601 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); 5602 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5603 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5604 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5605 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5606 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5607 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5608 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); 5609 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 5610 5611 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 5612 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 5613 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); 5614 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); 5615 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5616 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5617 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5618 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 5619 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5620 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 5621 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); 5622 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 5623 5624 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 5625 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 5626 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); 5627 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); 5628 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5629 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5630 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5631 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5632 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5633 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5634 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); 5635 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 5636 5637 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 5638 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 5639 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); 5640 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); 5641 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5642 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5643 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5644 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 5645 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5646 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 5647 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); 5648 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 5649 5650 if (rt2x00_is_usb(rt2x00dev)) { 5651 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); 5652 5653 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 5654 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 5655 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 5656 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 5657 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 5658 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); 5659 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); 5660 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); 5661 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); 5662 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); 5663 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 5664 } 5665 5666 /* 5667 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 5668 * although it is reserved. 5669 */ 5670 reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG); 5671 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); 5672 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); 5673 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); 5674 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); 5675 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); 5676 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); 5677 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); 5678 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); 5679 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); 5680 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); 5681 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); 5682 5683 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; 5684 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); 5685 5686 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 5687 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); 5688 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, 5689 IEEE80211_MAX_RTS_THRESHOLD); 5690 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1); 5691 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 5692 5693 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 5694 5695 /* 5696 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS 5697 * time should be set to 16. However, the original Ralink driver uses 5698 * 16 for both and indeed using a value of 10 for CCK SIFS results in 5699 * connection problems with 11g + CTS protection. Hence, use the same 5700 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. 5701 */ 5702 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 5703 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); 5704 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); 5705 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); 5706 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); 5707 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); 5708 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 5709 5710 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 5711 5712 /* 5713 * ASIC will keep garbage value after boot, clear encryption keys. 5714 */ 5715 for (i = 0; i < 4; i++) 5716 rt2800_register_write(rt2x00dev, 5717 SHARED_KEY_MODE_ENTRY(i), 0); 5718 5719 for (i = 0; i < 256; i++) { 5720 rt2800_config_wcid(rt2x00dev, NULL, i); 5721 rt2800_delete_wcid_attr(rt2x00dev, i); 5722 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 5723 } 5724 5725 /* 5726 * Clear all beacons 5727 */ 5728 for (i = 0; i < 8; i++) 5729 rt2800_clear_beacon_register(rt2x00dev, i); 5730 5731 if (rt2x00_is_usb(rt2x00dev)) { 5732 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 5733 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); 5734 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 5735 } else if (rt2x00_is_pcie(rt2x00dev)) { 5736 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 5737 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); 5738 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 5739 } 5740 5741 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0); 5742 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); 5743 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); 5744 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); 5745 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); 5746 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); 5747 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); 5748 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); 5749 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); 5750 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); 5751 5752 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1); 5753 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); 5754 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); 5755 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); 5756 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); 5757 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); 5758 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); 5759 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); 5760 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); 5761 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); 5762 5763 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0); 5764 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); 5765 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); 5766 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); 5767 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); 5768 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); 5769 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); 5770 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); 5771 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); 5772 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); 5773 5774 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1); 5775 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); 5776 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); 5777 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); 5778 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); 5779 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); 5780 5781 /* 5782 * Do not force the BA window size, we use the TXWI to set it 5783 */ 5784 reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE); 5785 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); 5786 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); 5787 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); 5788 5789 /* 5790 * We must clear the error counters. 5791 * These registers are cleared on read, 5792 * so we may pass a useless variable to store the value. 5793 */ 5794 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 5795 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1); 5796 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2); 5797 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0); 5798 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1); 5799 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2); 5800 5801 /* 5802 * Setup leadtime for pre tbtt interrupt to 6ms 5803 */ 5804 reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG); 5805 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); 5806 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); 5807 5808 /* 5809 * Set up channel statistics timer 5810 */ 5811 reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG); 5812 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); 5813 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); 5814 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); 5815 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); 5816 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); 5817 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); 5818 5819 return 0; 5820 } 5821 5822 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) 5823 { 5824 unsigned int i; 5825 u32 reg; 5826 5827 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 5828 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 5829 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) 5830 return 0; 5831 5832 udelay(REGISTER_BUSY_DELAY); 5833 } 5834 5835 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n"); 5836 return -EACCES; 5837 } 5838 5839 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 5840 { 5841 unsigned int i; 5842 u8 value; 5843 5844 /* 5845 * BBP was enabled after firmware was loaded, 5846 * but we need to reactivate it now. 5847 */ 5848 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 5849 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 5850 msleep(1); 5851 5852 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 5853 value = rt2800_bbp_read(rt2x00dev, 0); 5854 if ((value != 0xff) && (value != 0x00)) 5855 return 0; 5856 udelay(REGISTER_BUSY_DELAY); 5857 } 5858 5859 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 5860 return -EACCES; 5861 } 5862 5863 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev) 5864 { 5865 u8 value; 5866 5867 value = rt2800_bbp_read(rt2x00dev, 4); 5868 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); 5869 rt2800_bbp_write(rt2x00dev, 4, value); 5870 } 5871 5872 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev) 5873 { 5874 rt2800_bbp_write(rt2x00dev, 142, 1); 5875 rt2800_bbp_write(rt2x00dev, 143, 57); 5876 } 5877 5878 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev) 5879 { 5880 static const u8 glrt_table[] = { 5881 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */ 5882 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */ 5883 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */ 5884 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */ 5885 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */ 5886 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */ 5887 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */ 5888 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */ 5889 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */ 5890 }; 5891 int i; 5892 5893 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) { 5894 rt2800_bbp_write(rt2x00dev, 195, 128 + i); 5895 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]); 5896 } 5897 }; 5898 5899 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev) 5900 { 5901 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 5902 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5903 rt2800_bbp_write(rt2x00dev, 68, 0x0B); 5904 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5905 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5906 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5907 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5908 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5909 rt2800_bbp_write(rt2x00dev, 83, 0x6A); 5910 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5911 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5912 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5913 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5914 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5915 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5916 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5917 } 5918 5919 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev) 5920 { 5921 u16 eeprom; 5922 u8 value; 5923 5924 value = rt2800_bbp_read(rt2x00dev, 138); 5925 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 5926 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 5927 value |= 0x20; 5928 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 5929 value &= ~0x02; 5930 rt2800_bbp_write(rt2x00dev, 138, value); 5931 } 5932 5933 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev) 5934 { 5935 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5936 5937 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5938 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5939 5940 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5941 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5942 5943 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5944 5945 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 5946 rt2800_bbp_write(rt2x00dev, 80, 0x08); 5947 5948 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5949 5950 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5951 5952 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5953 5954 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5955 5956 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5957 5958 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5959 5960 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5961 5962 rt2800_bbp_write(rt2x00dev, 105, 0x01); 5963 5964 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5965 } 5966 5967 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev) 5968 { 5969 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5970 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5971 5972 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 5973 rt2800_bbp_write(rt2x00dev, 69, 0x16); 5974 rt2800_bbp_write(rt2x00dev, 73, 0x12); 5975 } else { 5976 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5977 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5978 } 5979 5980 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5981 5982 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5983 5984 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5985 5986 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5987 5988 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 5989 rt2800_bbp_write(rt2x00dev, 84, 0x19); 5990 else 5991 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5992 5993 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5994 5995 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5996 5997 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5998 5999 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6000 6001 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6002 6003 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6004 } 6005 6006 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev) 6007 { 6008 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6009 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6010 6011 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6012 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6013 6014 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6015 6016 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6017 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6018 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6019 6020 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6021 6022 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6023 6024 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6025 6026 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6027 6028 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6029 6030 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6031 6032 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 6033 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 6034 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E)) 6035 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6036 else 6037 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6038 6039 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6040 6041 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6042 6043 if (rt2x00_rt(rt2x00dev, RT3071) || 6044 rt2x00_rt(rt2x00dev, RT3090)) 6045 rt2800_disable_unused_dac_adc(rt2x00dev); 6046 } 6047 6048 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev) 6049 { 6050 u8 value; 6051 6052 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6053 6054 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6055 6056 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6057 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6058 6059 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6060 6061 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6062 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6063 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6064 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6065 6066 rt2800_bbp_write(rt2x00dev, 77, 0x58); 6067 6068 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6069 6070 rt2800_bbp_write(rt2x00dev, 74, 0x0b); 6071 rt2800_bbp_write(rt2x00dev, 79, 0x18); 6072 rt2800_bbp_write(rt2x00dev, 80, 0x09); 6073 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6074 6075 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6076 6077 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6078 6079 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6080 6081 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6082 6083 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6084 6085 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6086 6087 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6088 6089 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6090 6091 rt2800_bbp_write(rt2x00dev, 105, 0x1c); 6092 6093 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6094 6095 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6096 6097 rt2800_bbp_write(rt2x00dev, 67, 0x24); 6098 rt2800_bbp_write(rt2x00dev, 143, 0x04); 6099 rt2800_bbp_write(rt2x00dev, 142, 0x99); 6100 rt2800_bbp_write(rt2x00dev, 150, 0x30); 6101 rt2800_bbp_write(rt2x00dev, 151, 0x2e); 6102 rt2800_bbp_write(rt2x00dev, 152, 0x20); 6103 rt2800_bbp_write(rt2x00dev, 153, 0x34); 6104 rt2800_bbp_write(rt2x00dev, 154, 0x40); 6105 rt2800_bbp_write(rt2x00dev, 155, 0x3b); 6106 rt2800_bbp_write(rt2x00dev, 253, 0x04); 6107 6108 value = rt2800_bbp_read(rt2x00dev, 47); 6109 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1); 6110 rt2800_bbp_write(rt2x00dev, 47, value); 6111 6112 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */ 6113 value = rt2800_bbp_read(rt2x00dev, 3); 6114 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1); 6115 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1); 6116 rt2800_bbp_write(rt2x00dev, 3, value); 6117 } 6118 6119 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) 6120 { 6121 rt2800_bbp_write(rt2x00dev, 3, 0x00); 6122 rt2800_bbp_write(rt2x00dev, 4, 0x50); 6123 6124 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6125 6126 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6127 6128 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6129 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6130 6131 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6132 6133 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6134 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6135 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6136 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6137 6138 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6139 6140 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6141 6142 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 6143 rt2800_bbp_write(rt2x00dev, 80, 0x08); 6144 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6145 6146 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6147 6148 if (rt2x00_rt(rt2x00dev, RT5350)) { 6149 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6150 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6151 } else { 6152 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6153 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6154 } 6155 6156 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6157 6158 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6159 6160 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6161 6162 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6163 6164 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6165 6166 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6167 6168 if (rt2x00_rt(rt2x00dev, RT5350)) { 6169 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6170 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6171 } else { 6172 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6173 rt2800_bbp_write(rt2x00dev, 106, 0x05); 6174 } 6175 6176 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6177 6178 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6179 6180 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 6181 /* Set ITxBF timeout to 0x9c40=1000msec */ 6182 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6183 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6184 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6185 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6186 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6187 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6188 /* Reprogram the inband interface to put right values in RXWI */ 6189 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6190 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6191 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6192 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6193 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6194 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6195 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6196 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6197 6198 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6199 6200 if (rt2x00_rt(rt2x00dev, RT5350)) { 6201 /* Antenna Software OFDM */ 6202 rt2800_bbp_write(rt2x00dev, 150, 0x40); 6203 /* Antenna Software CCK */ 6204 rt2800_bbp_write(rt2x00dev, 151, 0x30); 6205 rt2800_bbp_write(rt2x00dev, 152, 0xa3); 6206 /* Clear previously selected antenna */ 6207 rt2800_bbp_write(rt2x00dev, 154, 0); 6208 } 6209 } 6210 6211 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev) 6212 { 6213 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6214 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6215 6216 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6217 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6218 6219 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6220 6221 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6222 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6223 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6224 6225 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6226 6227 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6228 6229 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6230 6231 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6232 6233 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6234 6235 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6236 6237 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E)) 6238 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6239 else 6240 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6241 6242 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6243 6244 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6245 6246 rt2800_disable_unused_dac_adc(rt2x00dev); 6247 } 6248 6249 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev) 6250 { 6251 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6252 6253 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6254 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6255 6256 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6257 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6258 6259 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6260 6261 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6262 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6263 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6264 6265 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6266 6267 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6268 6269 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6270 6271 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6272 6273 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6274 6275 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6276 6277 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6278 6279 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6280 6281 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6282 6283 rt2800_disable_unused_dac_adc(rt2x00dev); 6284 } 6285 6286 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev) 6287 { 6288 rt2800_init_bbp_early(rt2x00dev); 6289 6290 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6291 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6292 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6293 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6294 6295 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6296 6297 /* Enable DC filter */ 6298 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E)) 6299 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6300 } 6301 6302 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) 6303 { 6304 int ant, div_mode; 6305 u16 eeprom; 6306 u8 value; 6307 6308 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6309 6310 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6311 6312 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6313 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6314 6315 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6316 6317 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6318 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6319 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6320 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6321 6322 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6323 6324 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6325 6326 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6327 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6328 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6329 6330 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6331 6332 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6333 6334 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6335 6336 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6337 6338 if (rt2x00_rt(rt2x00dev, RT5392)) 6339 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6340 6341 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6342 6343 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6344 6345 if (rt2x00_rt(rt2x00dev, RT5392)) { 6346 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6347 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6348 } 6349 6350 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6351 6352 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6353 6354 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6355 6356 if (rt2x00_rt(rt2x00dev, RT5390)) 6357 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6358 else if (rt2x00_rt(rt2x00dev, RT5392)) 6359 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6360 else 6361 WARN_ON(1); 6362 6363 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6364 6365 if (rt2x00_rt(rt2x00dev, RT5392)) { 6366 rt2800_bbp_write(rt2x00dev, 134, 0xd0); 6367 rt2800_bbp_write(rt2x00dev, 135, 0xf6); 6368 } 6369 6370 rt2800_disable_unused_dac_adc(rt2x00dev); 6371 6372 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6373 div_mode = rt2x00_get_field16(eeprom, 6374 EEPROM_NIC_CONF1_ANT_DIVERSITY); 6375 ant = (div_mode == 3) ? 1 : 0; 6376 6377 /* check if this is a Bluetooth combo card */ 6378 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 6379 u32 reg; 6380 6381 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 6382 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 6383 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); 6384 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); 6385 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); 6386 if (ant == 0) 6387 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); 6388 else if (ant == 1) 6389 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); 6390 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 6391 } 6392 6393 /* These chips have hardware RX antenna diversity */ 6394 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 6395 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 6396 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */ 6397 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */ 6398 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */ 6399 } 6400 6401 value = rt2800_bbp_read(rt2x00dev, 152); 6402 if (ant == 0) 6403 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6404 else 6405 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6406 rt2800_bbp_write(rt2x00dev, 152, value); 6407 6408 rt2800_init_freq_calibration(rt2x00dev); 6409 } 6410 6411 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) 6412 { 6413 int ant, div_mode; 6414 u16 eeprom; 6415 u8 value; 6416 6417 rt2800_init_bbp_early(rt2x00dev); 6418 6419 value = rt2800_bbp_read(rt2x00dev, 105); 6420 rt2x00_set_field8(&value, BBP105_MLD, 6421 rt2x00dev->default_ant.rx_chain_num == 2); 6422 rt2800_bbp_write(rt2x00dev, 105, value); 6423 6424 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6425 6426 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6427 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6428 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6429 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6430 rt2800_bbp_write(rt2x00dev, 69, 0x1A); 6431 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6432 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6433 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6434 rt2800_bbp_write(rt2x00dev, 75, 0x4F); 6435 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6436 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6437 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 6438 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6439 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6440 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6441 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6442 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6443 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6444 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 6445 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6446 /* FIXME BBP105 owerwrite */ 6447 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 6448 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6449 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6450 rt2800_bbp_write(rt2x00dev, 134, 0xD0); 6451 rt2800_bbp_write(rt2x00dev, 135, 0xF6); 6452 rt2800_bbp_write(rt2x00dev, 137, 0x0F); 6453 6454 /* Initialize GLRT (Generalized Likehood Radio Test) */ 6455 rt2800_init_bbp_5592_glrt(rt2x00dev); 6456 6457 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6458 6459 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6460 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); 6461 ant = (div_mode == 3) ? 1 : 0; 6462 value = rt2800_bbp_read(rt2x00dev, 152); 6463 if (ant == 0) { 6464 /* Main antenna */ 6465 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6466 } else { 6467 /* Auxiliary antenna */ 6468 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6469 } 6470 rt2800_bbp_write(rt2x00dev, 152, value); 6471 6472 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) { 6473 value = rt2800_bbp_read(rt2x00dev, 254); 6474 rt2x00_set_field8(&value, BBP254_BIT7, 1); 6475 rt2800_bbp_write(rt2x00dev, 254, value); 6476 } 6477 6478 rt2800_init_freq_calibration(rt2x00dev); 6479 6480 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6481 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 6482 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6483 } 6484 6485 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev, 6486 const u8 reg, const u8 value) 6487 { 6488 rt2800_bbp_write(rt2x00dev, 195, reg); 6489 rt2800_bbp_write(rt2x00dev, 196, value); 6490 } 6491 6492 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev, 6493 const u8 reg, const u8 value) 6494 { 6495 rt2800_bbp_write(rt2x00dev, 158, reg); 6496 rt2800_bbp_write(rt2x00dev, 159, value); 6497 } 6498 6499 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg) 6500 { 6501 rt2800_bbp_write(rt2x00dev, 158, reg); 6502 return rt2800_bbp_read(rt2x00dev, 159); 6503 } 6504 6505 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev) 6506 { 6507 u8 bbp; 6508 6509 /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */ 6510 bbp = rt2800_bbp_read(rt2x00dev, 105); 6511 rt2x00_set_field8(&bbp, BBP105_MLD, 6512 rt2x00dev->default_ant.rx_chain_num == 2); 6513 rt2800_bbp_write(rt2x00dev, 105, bbp); 6514 6515 /* Avoid data loss and CRC errors */ 6516 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6517 6518 /* Fix I/Q swap issue */ 6519 bbp = rt2800_bbp_read(rt2x00dev, 1); 6520 bbp |= 0x04; 6521 rt2800_bbp_write(rt2x00dev, 1, bbp); 6522 6523 /* BBP for G band */ 6524 rt2800_bbp_write(rt2x00dev, 3, 0x08); 6525 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */ 6526 rt2800_bbp_write(rt2x00dev, 6, 0x08); 6527 rt2800_bbp_write(rt2x00dev, 14, 0x09); 6528 rt2800_bbp_write(rt2x00dev, 15, 0xFF); 6529 rt2800_bbp_write(rt2x00dev, 16, 0x01); 6530 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6531 rt2800_bbp_write(rt2x00dev, 21, 0x00); 6532 rt2800_bbp_write(rt2x00dev, 22, 0x00); 6533 rt2800_bbp_write(rt2x00dev, 27, 0x00); 6534 rt2800_bbp_write(rt2x00dev, 28, 0x00); 6535 rt2800_bbp_write(rt2x00dev, 30, 0x00); 6536 rt2800_bbp_write(rt2x00dev, 31, 0x48); 6537 rt2800_bbp_write(rt2x00dev, 47, 0x40); 6538 rt2800_bbp_write(rt2x00dev, 62, 0x00); 6539 rt2800_bbp_write(rt2x00dev, 63, 0x00); 6540 rt2800_bbp_write(rt2x00dev, 64, 0x00); 6541 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6542 rt2800_bbp_write(rt2x00dev, 66, 0x1C); 6543 rt2800_bbp_write(rt2x00dev, 67, 0x20); 6544 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6545 rt2800_bbp_write(rt2x00dev, 69, 0x10); 6546 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6547 rt2800_bbp_write(rt2x00dev, 73, 0x18); 6548 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6549 rt2800_bbp_write(rt2x00dev, 75, 0x60); 6550 rt2800_bbp_write(rt2x00dev, 76, 0x44); 6551 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6552 rt2800_bbp_write(rt2x00dev, 78, 0x1E); 6553 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 6554 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 6555 rt2800_bbp_write(rt2x00dev, 81, 0x3A); 6556 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 6557 rt2800_bbp_write(rt2x00dev, 83, 0x9A); 6558 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 6559 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6560 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6561 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6562 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6563 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 6564 rt2800_bbp_write(rt2x00dev, 96, 0x00); 6565 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 6566 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6567 /* FIXME BBP105 owerwrite */ 6568 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 6569 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6570 rt2800_bbp_write(rt2x00dev, 109, 0x00); 6571 rt2800_bbp_write(rt2x00dev, 134, 0x10); 6572 rt2800_bbp_write(rt2x00dev, 135, 0xA6); 6573 rt2800_bbp_write(rt2x00dev, 137, 0x04); 6574 rt2800_bbp_write(rt2x00dev, 142, 0x30); 6575 rt2800_bbp_write(rt2x00dev, 143, 0xF7); 6576 rt2800_bbp_write(rt2x00dev, 160, 0xEC); 6577 rt2800_bbp_write(rt2x00dev, 161, 0xC4); 6578 rt2800_bbp_write(rt2x00dev, 162, 0x77); 6579 rt2800_bbp_write(rt2x00dev, 163, 0xF9); 6580 rt2800_bbp_write(rt2x00dev, 164, 0x00); 6581 rt2800_bbp_write(rt2x00dev, 165, 0x00); 6582 rt2800_bbp_write(rt2x00dev, 186, 0x00); 6583 rt2800_bbp_write(rt2x00dev, 187, 0x00); 6584 rt2800_bbp_write(rt2x00dev, 188, 0x00); 6585 rt2800_bbp_write(rt2x00dev, 186, 0x00); 6586 rt2800_bbp_write(rt2x00dev, 187, 0x01); 6587 rt2800_bbp_write(rt2x00dev, 188, 0x00); 6588 rt2800_bbp_write(rt2x00dev, 189, 0x00); 6589 6590 rt2800_bbp_write(rt2x00dev, 91, 0x06); 6591 rt2800_bbp_write(rt2x00dev, 92, 0x04); 6592 rt2800_bbp_write(rt2x00dev, 93, 0x54); 6593 rt2800_bbp_write(rt2x00dev, 99, 0x50); 6594 rt2800_bbp_write(rt2x00dev, 148, 0x84); 6595 rt2800_bbp_write(rt2x00dev, 167, 0x80); 6596 rt2800_bbp_write(rt2x00dev, 178, 0xFF); 6597 rt2800_bbp_write(rt2x00dev, 106, 0x13); 6598 6599 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */ 6600 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00); 6601 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14); 6602 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20); 6603 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A); 6604 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16); 6605 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06); 6606 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02); 6607 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07); 6608 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05); 6609 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09); 6610 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20); 6611 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08); 6612 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A); 6613 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00); 6614 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00); 6615 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0); 6616 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F); 6617 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F); 6618 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32); 6619 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08); 6620 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28); 6621 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19); 6622 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A); 6623 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16); 6624 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10); 6625 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10); 6626 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A); 6627 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36); 6628 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C); 6629 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26); 6630 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24); 6631 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42); 6632 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40); 6633 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30); 6634 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29); 6635 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C); 6636 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46); 6637 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D); 6638 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40); 6639 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E); 6640 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38); 6641 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D); 6642 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F); 6643 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C); 6644 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34); 6645 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C); 6646 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F); 6647 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C); 6648 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35); 6649 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E); 6650 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F); 6651 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49); 6652 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41); 6653 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36); 6654 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39); 6655 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30); 6656 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30); 6657 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E); 6658 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D); 6659 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28); 6660 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21); 6661 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C); 6662 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16); 6663 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50); 6664 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A); 6665 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43); 6666 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50); 6667 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10); 6668 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10); 6669 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10); 6670 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10); 6671 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D); 6672 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14); 6673 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32); 6674 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C); 6675 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36); 6676 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C); 6677 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43); 6678 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C); 6679 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E); 6680 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36); 6681 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30); 6682 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E); 6683 6684 /* BBP for G band DCOC function */ 6685 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C); 6686 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00); 6687 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10); 6688 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10); 6689 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10); 6690 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10); 6691 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08); 6692 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40); 6693 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04); 6694 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04); 6695 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08); 6696 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08); 6697 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03); 6698 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03); 6699 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03); 6700 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02); 6701 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40); 6702 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40); 6703 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64); 6704 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64); 6705 6706 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6707 } 6708 6709 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) 6710 { 6711 unsigned int i; 6712 u16 eeprom; 6713 u8 reg_id; 6714 u8 value; 6715 6716 if (rt2800_is_305x_soc(rt2x00dev)) 6717 rt2800_init_bbp_305x_soc(rt2x00dev); 6718 6719 switch (rt2x00dev->chip.rt) { 6720 case RT2860: 6721 case RT2872: 6722 case RT2883: 6723 rt2800_init_bbp_28xx(rt2x00dev); 6724 break; 6725 case RT3070: 6726 case RT3071: 6727 case RT3090: 6728 rt2800_init_bbp_30xx(rt2x00dev); 6729 break; 6730 case RT3290: 6731 rt2800_init_bbp_3290(rt2x00dev); 6732 break; 6733 case RT3352: 6734 case RT5350: 6735 rt2800_init_bbp_3352(rt2x00dev); 6736 break; 6737 case RT3390: 6738 rt2800_init_bbp_3390(rt2x00dev); 6739 break; 6740 case RT3572: 6741 rt2800_init_bbp_3572(rt2x00dev); 6742 break; 6743 case RT3593: 6744 rt2800_init_bbp_3593(rt2x00dev); 6745 return; 6746 case RT5390: 6747 case RT5392: 6748 rt2800_init_bbp_53xx(rt2x00dev); 6749 break; 6750 case RT5592: 6751 rt2800_init_bbp_5592(rt2x00dev); 6752 return; 6753 case RT6352: 6754 rt2800_init_bbp_6352(rt2x00dev); 6755 break; 6756 } 6757 6758 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 6759 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 6760 EEPROM_BBP_START, i); 6761 6762 if (eeprom != 0xffff && eeprom != 0x0000) { 6763 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 6764 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 6765 rt2800_bbp_write(rt2x00dev, reg_id, value); 6766 } 6767 } 6768 } 6769 6770 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev) 6771 { 6772 u32 reg; 6773 6774 reg = rt2800_register_read(rt2x00dev, OPT_14_CSR); 6775 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); 6776 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 6777 } 6778 6779 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, 6780 u8 filter_target) 6781 { 6782 unsigned int i; 6783 u8 bbp; 6784 u8 rfcsr; 6785 u8 passband; 6786 u8 stopband; 6787 u8 overtuned = 0; 6788 u8 rfcsr24 = (bw40) ? 0x27 : 0x07; 6789 6790 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 6791 6792 bbp = rt2800_bbp_read(rt2x00dev, 4); 6793 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); 6794 rt2800_bbp_write(rt2x00dev, 4, bbp); 6795 6796 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 6797 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); 6798 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 6799 6800 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 6801 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); 6802 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 6803 6804 /* 6805 * Set power & frequency of passband test tone 6806 */ 6807 rt2800_bbp_write(rt2x00dev, 24, 0); 6808 6809 for (i = 0; i < 100; i++) { 6810 rt2800_bbp_write(rt2x00dev, 25, 0x90); 6811 msleep(1); 6812 6813 passband = rt2800_bbp_read(rt2x00dev, 55); 6814 if (passband) 6815 break; 6816 } 6817 6818 /* 6819 * Set power & frequency of stopband test tone 6820 */ 6821 rt2800_bbp_write(rt2x00dev, 24, 0x06); 6822 6823 for (i = 0; i < 100; i++) { 6824 rt2800_bbp_write(rt2x00dev, 25, 0x90); 6825 msleep(1); 6826 6827 stopband = rt2800_bbp_read(rt2x00dev, 55); 6828 6829 if ((passband - stopband) <= filter_target) { 6830 rfcsr24++; 6831 overtuned += ((passband - stopband) == filter_target); 6832 } else 6833 break; 6834 6835 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 6836 } 6837 6838 rfcsr24 -= !!overtuned; 6839 6840 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 6841 return rfcsr24; 6842 } 6843 6844 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev, 6845 const unsigned int rf_reg) 6846 { 6847 u8 rfcsr; 6848 6849 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg); 6850 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1); 6851 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 6852 msleep(1); 6853 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0); 6854 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 6855 } 6856 6857 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev) 6858 { 6859 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 6860 u8 filter_tgt_bw20; 6861 u8 filter_tgt_bw40; 6862 u8 rfcsr, bbp; 6863 6864 /* 6865 * TODO: sync filter_tgt values with vendor driver 6866 */ 6867 if (rt2x00_rt(rt2x00dev, RT3070)) { 6868 filter_tgt_bw20 = 0x16; 6869 filter_tgt_bw40 = 0x19; 6870 } else { 6871 filter_tgt_bw20 = 0x13; 6872 filter_tgt_bw40 = 0x15; 6873 } 6874 6875 drv_data->calibration_bw20 = 6876 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20); 6877 drv_data->calibration_bw40 = 6878 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40); 6879 6880 /* 6881 * Save BBP 25 & 26 values for later use in channel switching (for 3052) 6882 */ 6883 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 6884 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 6885 6886 /* 6887 * Set back to initial state 6888 */ 6889 rt2800_bbp_write(rt2x00dev, 24, 0); 6890 6891 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 6892 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 6893 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 6894 6895 /* 6896 * Set BBP back to BW20 6897 */ 6898 bbp = rt2800_bbp_read(rt2x00dev, 4); 6899 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 6900 rt2800_bbp_write(rt2x00dev, 4, bbp); 6901 } 6902 6903 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) 6904 { 6905 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 6906 u8 min_gain, rfcsr, bbp; 6907 u16 eeprom; 6908 6909 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 6910 6911 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 6912 if (rt2x00_rt(rt2x00dev, RT3070) || 6913 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 6914 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 6915 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 6916 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev)) 6917 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 6918 } 6919 6920 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2; 6921 if (drv_data->txmixer_gain_24g >= min_gain) { 6922 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 6923 drv_data->txmixer_gain_24g); 6924 } 6925 6926 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 6927 6928 if (rt2x00_rt(rt2x00dev, RT3090)) { 6929 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 6930 bbp = rt2800_bbp_read(rt2x00dev, 138); 6931 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 6932 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 6933 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); 6934 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 6935 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); 6936 rt2800_bbp_write(rt2x00dev, 138, bbp); 6937 } 6938 6939 if (rt2x00_rt(rt2x00dev, RT3070)) { 6940 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27); 6941 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) 6942 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); 6943 else 6944 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); 6945 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); 6946 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); 6947 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); 6948 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 6949 } else if (rt2x00_rt(rt2x00dev, RT3071) || 6950 rt2x00_rt(rt2x00dev, RT3090) || 6951 rt2x00_rt(rt2x00dev, RT3390)) { 6952 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 6953 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 6954 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 6955 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 6956 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 6957 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 6958 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 6959 6960 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15); 6961 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); 6962 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); 6963 6964 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 6965 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); 6966 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 6967 6968 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 6969 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); 6970 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 6971 } 6972 } 6973 6974 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev) 6975 { 6976 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 6977 u8 rfcsr; 6978 u8 tx_gain; 6979 6980 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 6981 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0); 6982 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 6983 6984 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 6985 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g, 6986 RFCSR17_TXMIXER_GAIN); 6987 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain); 6988 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 6989 6990 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38); 6991 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); 6992 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); 6993 6994 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39); 6995 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); 6996 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 6997 6998 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 6999 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 7000 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 7001 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 7002 7003 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 7004 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 7005 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 7006 7007 /* TODO: enable stream mode */ 7008 } 7009 7010 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev) 7011 { 7012 u8 reg; 7013 u16 eeprom; 7014 7015 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 7016 reg = rt2800_bbp_read(rt2x00dev, 138); 7017 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 7018 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 7019 rt2x00_set_field8(®, BBP138_RX_ADC1, 0); 7020 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 7021 rt2x00_set_field8(®, BBP138_TX_DAC1, 1); 7022 rt2800_bbp_write(rt2x00dev, 138, reg); 7023 7024 reg = rt2800_rfcsr_read(rt2x00dev, 38); 7025 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); 7026 rt2800_rfcsr_write(rt2x00dev, 38, reg); 7027 7028 reg = rt2800_rfcsr_read(rt2x00dev, 39); 7029 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); 7030 rt2800_rfcsr_write(rt2x00dev, 39, reg); 7031 7032 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7033 7034 reg = rt2800_rfcsr_read(rt2x00dev, 30); 7035 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); 7036 rt2800_rfcsr_write(rt2x00dev, 30, reg); 7037 } 7038 7039 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev) 7040 { 7041 rt2800_rf_init_calibration(rt2x00dev, 30); 7042 7043 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 7044 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 7045 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 7046 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 7047 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7048 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7049 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7050 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 7051 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 7052 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7053 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 7054 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7055 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 7056 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 7057 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7058 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7059 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7060 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7061 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7062 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7063 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7064 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7065 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7066 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 7067 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7068 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 7069 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 7070 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 7071 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 7072 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 7073 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 7074 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 7075 } 7076 7077 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) 7078 { 7079 u8 rfcsr; 7080 u16 eeprom; 7081 u32 reg; 7082 7083 /* XXX vendor driver do this only for 3070 */ 7084 rt2800_rf_init_calibration(rt2x00dev, 30); 7085 7086 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7087 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7088 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7089 rt2800_rfcsr_write(rt2x00dev, 7, 0x60); 7090 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7091 rt2800_rfcsr_write(rt2x00dev, 10, 0x41); 7092 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7093 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 7094 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7095 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7096 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7097 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7098 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7099 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7100 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7101 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7102 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7103 rt2800_rfcsr_write(rt2x00dev, 25, 0x03); 7104 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 7105 7106 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 7107 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7108 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7109 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7110 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7111 } else if (rt2x00_rt(rt2x00dev, RT3071) || 7112 rt2x00_rt(rt2x00dev, RT3090)) { 7113 rt2800_rfcsr_write(rt2x00dev, 31, 0x14); 7114 7115 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7116 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7117 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7118 7119 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7120 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7121 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7122 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { 7123 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 7124 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 7125 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7126 else 7127 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7128 } 7129 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7130 7131 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7132 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7133 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7134 } 7135 7136 rt2800_rx_filter_calibration(rt2x00dev); 7137 7138 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 7139 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7140 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) 7141 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7142 7143 rt2800_led_open_drain_enable(rt2x00dev); 7144 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7145 } 7146 7147 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) 7148 { 7149 u8 rfcsr; 7150 7151 rt2800_rf_init_calibration(rt2x00dev, 2); 7152 7153 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 7154 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7155 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7156 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7157 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 7158 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3); 7159 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7160 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7161 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7162 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7163 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7164 rt2800_rfcsr_write(rt2x00dev, 18, 0x02); 7165 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7166 rt2800_rfcsr_write(rt2x00dev, 25, 0x83); 7167 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7168 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7169 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7170 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7171 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7172 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7173 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7174 rt2800_rfcsr_write(rt2x00dev, 34, 0x05); 7175 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7176 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7177 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7178 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7179 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7180 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7181 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7182 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b); 7183 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7184 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7185 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7186 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7187 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7188 rt2800_rfcsr_write(rt2x00dev, 49, 0x98); 7189 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7190 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7191 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 7192 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7193 rt2800_rfcsr_write(rt2x00dev, 56, 0x02); 7194 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 7195 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 7196 rt2800_rfcsr_write(rt2x00dev, 59, 0x09); 7197 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7198 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); 7199 7200 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29); 7201 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3); 7202 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr); 7203 7204 rt2800_led_open_drain_enable(rt2x00dev); 7205 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7206 } 7207 7208 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) 7209 { 7210 int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0, 7211 &rt2x00dev->cap_flags); 7212 int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1, 7213 &rt2x00dev->cap_flags); 7214 u8 rfcsr; 7215 7216 rt2800_rf_init_calibration(rt2x00dev, 30); 7217 7218 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7219 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7220 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7221 rt2800_rfcsr_write(rt2x00dev, 3, 0x18); 7222 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7223 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7224 rt2800_rfcsr_write(rt2x00dev, 6, 0x33); 7225 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7226 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7227 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7228 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2); 7229 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 7230 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 7231 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 7232 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a); 7233 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7234 rt2800_rfcsr_write(rt2x00dev, 16, 0x01); 7235 rt2800_rfcsr_write(rt2x00dev, 18, 0x45); 7236 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7237 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7238 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7239 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7240 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7241 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7242 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7243 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7244 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7245 rt2800_rfcsr_write(rt2x00dev, 28, 0x03); 7246 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 7247 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7248 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7249 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7250 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7251 rfcsr = 0x01; 7252 if (tx0_ext_pa) 7253 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1); 7254 if (tx1_ext_pa) 7255 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1); 7256 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 7257 rt2800_rfcsr_write(rt2x00dev, 35, 0x03); 7258 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); 7259 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); 7260 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); 7261 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); 7262 rt2800_rfcsr_write(rt2x00dev, 40, 0x33); 7263 rfcsr = 0x52; 7264 if (!tx0_ext_pa) { 7265 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1); 7266 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1); 7267 } 7268 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr); 7269 rfcsr = 0x52; 7270 if (!tx1_ext_pa) { 7271 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1); 7272 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1); 7273 } 7274 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 7275 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); 7276 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); 7277 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); 7278 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd); 7279 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); 7280 rt2800_rfcsr_write(rt2x00dev, 48, 0x14); 7281 rt2800_rfcsr_write(rt2x00dev, 49, 0x00); 7282 rfcsr = 0x2d; 7283 if (tx0_ext_pa) 7284 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1); 7285 if (tx1_ext_pa) 7286 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1); 7287 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7288 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f)); 7289 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00)); 7290 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52)); 7291 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b)); 7292 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f)); 7293 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00)); 7294 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52)); 7295 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b)); 7296 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 7297 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 7298 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 7299 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7300 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7301 7302 rt2800_rx_filter_calibration(rt2x00dev); 7303 rt2800_led_open_drain_enable(rt2x00dev); 7304 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7305 } 7306 7307 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) 7308 { 7309 u32 reg; 7310 7311 rt2800_rf_init_calibration(rt2x00dev, 30); 7312 7313 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 7314 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 7315 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7316 rt2800_rfcsr_write(rt2x00dev, 3, 0x62); 7317 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7318 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); 7319 rt2800_rfcsr_write(rt2x00dev, 6, 0x42); 7320 rt2800_rfcsr_write(rt2x00dev, 7, 0x34); 7321 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 7322 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 7323 rt2800_rfcsr_write(rt2x00dev, 10, 0x61); 7324 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7325 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); 7326 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); 7327 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7328 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7329 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); 7330 rt2800_rfcsr_write(rt2x00dev, 17, 0x94); 7331 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); 7332 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); 7333 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); 7334 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); 7335 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7336 rt2800_rfcsr_write(rt2x00dev, 23, 0x14); 7337 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7338 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 7339 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7340 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7341 rt2800_rfcsr_write(rt2x00dev, 28, 0x41); 7342 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); 7343 rt2800_rfcsr_write(rt2x00dev, 30, 0x20); 7344 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); 7345 7346 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7347 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7348 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7349 7350 rt2800_rx_filter_calibration(rt2x00dev); 7351 7352 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) 7353 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7354 7355 rt2800_led_open_drain_enable(rt2x00dev); 7356 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7357 } 7358 7359 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) 7360 { 7361 u8 rfcsr; 7362 u32 reg; 7363 7364 rt2800_rf_init_calibration(rt2x00dev, 30); 7365 7366 rt2800_rfcsr_write(rt2x00dev, 0, 0x70); 7367 rt2800_rfcsr_write(rt2x00dev, 1, 0x81); 7368 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7369 rt2800_rfcsr_write(rt2x00dev, 3, 0x02); 7370 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); 7371 rt2800_rfcsr_write(rt2x00dev, 5, 0x05); 7372 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); 7373 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 7374 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 7375 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 7376 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 7377 rt2800_rfcsr_write(rt2x00dev, 12, 0x70); 7378 rt2800_rfcsr_write(rt2x00dev, 13, 0x65); 7379 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); 7380 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7381 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); 7382 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 7383 rt2800_rfcsr_write(rt2x00dev, 18, 0xac); 7384 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 7385 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 7386 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); 7387 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7388 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); 7389 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7390 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 7391 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7392 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7393 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7394 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 7395 rt2800_rfcsr_write(rt2x00dev, 30, 0x09); 7396 rt2800_rfcsr_write(rt2x00dev, 31, 0x10); 7397 7398 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7399 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7400 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7401 7402 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7403 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7404 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7405 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7406 msleep(1); 7407 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7408 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7409 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7410 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7411 7412 rt2800_rx_filter_calibration(rt2x00dev); 7413 rt2800_led_open_drain_enable(rt2x00dev); 7414 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7415 } 7416 7417 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev) 7418 { 7419 u8 bbp; 7420 bool txbf_enabled = false; /* FIXME */ 7421 7422 bbp = rt2800_bbp_read(rt2x00dev, 105); 7423 if (rt2x00dev->default_ant.rx_chain_num == 1) 7424 rt2x00_set_field8(&bbp, BBP105_MLD, 0); 7425 else 7426 rt2x00_set_field8(&bbp, BBP105_MLD, 1); 7427 rt2800_bbp_write(rt2x00dev, 105, bbp); 7428 7429 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7430 7431 rt2800_bbp_write(rt2x00dev, 92, 0x02); 7432 rt2800_bbp_write(rt2x00dev, 82, 0x82); 7433 rt2800_bbp_write(rt2x00dev, 106, 0x05); 7434 rt2800_bbp_write(rt2x00dev, 104, 0x92); 7435 rt2800_bbp_write(rt2x00dev, 88, 0x90); 7436 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 7437 rt2800_bbp_write(rt2x00dev, 47, 0x48); 7438 rt2800_bbp_write(rt2x00dev, 120, 0x50); 7439 7440 if (txbf_enabled) 7441 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 7442 else 7443 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 7444 7445 /* SNR mapping */ 7446 rt2800_bbp_write(rt2x00dev, 142, 6); 7447 rt2800_bbp_write(rt2x00dev, 143, 160); 7448 rt2800_bbp_write(rt2x00dev, 142, 7); 7449 rt2800_bbp_write(rt2x00dev, 143, 161); 7450 rt2800_bbp_write(rt2x00dev, 142, 8); 7451 rt2800_bbp_write(rt2x00dev, 143, 162); 7452 7453 /* ADC/DAC control */ 7454 rt2800_bbp_write(rt2x00dev, 31, 0x08); 7455 7456 /* RX AGC energy lower bound in log2 */ 7457 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 7458 7459 /* FIXME: BBP 105 owerwrite? */ 7460 rt2800_bbp_write(rt2x00dev, 105, 0x04); 7461 7462 } 7463 7464 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) 7465 { 7466 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7467 u32 reg; 7468 u8 rfcsr; 7469 7470 /* Disable GPIO #4 and #7 function for LAN PE control */ 7471 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7472 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); 7473 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); 7474 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7475 7476 /* Initialize default register values */ 7477 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 7478 rt2800_rfcsr_write(rt2x00dev, 3, 0x80); 7479 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7480 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 7481 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7482 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7483 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 7484 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 7485 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e); 7486 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 7487 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 7488 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7489 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7490 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7491 rt2800_rfcsr_write(rt2x00dev, 32, 0x78); 7492 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b); 7493 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 7494 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0); 7495 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 7496 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 7497 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3); 7498 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 7499 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 7500 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 7501 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 7502 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 7503 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 7504 rt2800_rfcsr_write(rt2x00dev, 53, 0x18); 7505 rt2800_rfcsr_write(rt2x00dev, 54, 0x18); 7506 rt2800_rfcsr_write(rt2x00dev, 55, 0x18); 7507 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 7508 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 7509 7510 /* Initiate calibration */ 7511 /* TODO: use rt2800_rf_init_calibration ? */ 7512 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 7513 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 7514 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 7515 7516 rt2800_freq_cal_mode1(rt2x00dev); 7517 7518 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 7519 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1); 7520 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 7521 7522 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7523 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7524 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7525 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7526 usleep_range(1000, 1500); 7527 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7528 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7529 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7530 7531 /* Set initial values for RX filter calibration */ 7532 drv_data->calibration_bw20 = 0x1f; 7533 drv_data->calibration_bw40 = 0x2f; 7534 7535 /* Save BBP 25 & 26 values for later use in channel switching */ 7536 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 7537 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 7538 7539 rt2800_led_open_drain_enable(rt2x00dev); 7540 rt2800_normal_mode_setup_3593(rt2x00dev); 7541 7542 rt3593_post_bbp_init(rt2x00dev); 7543 7544 /* TODO: enable stream mode support */ 7545 } 7546 7547 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev) 7548 { 7549 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7550 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7551 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7552 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7553 rt2800_rfcsr_write(rt2x00dev, 4, 0x49); 7554 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7555 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 7556 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7557 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7558 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7559 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7560 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7561 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7562 if (rt2800_clk_is_20mhz(rt2x00dev)) 7563 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f); 7564 else 7565 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7566 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7567 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7568 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0); 7569 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7570 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 7571 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7572 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7573 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7574 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7575 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7576 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7577 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7578 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7579 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7580 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0); 7581 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7582 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7583 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7584 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7585 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 7586 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7587 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7588 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 7589 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7590 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7591 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7592 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7593 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7594 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 7595 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c); 7596 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6); 7597 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7598 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7599 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7600 rt2800_rfcsr_write(rt2x00dev, 49, 0x80); 7601 rt2800_rfcsr_write(rt2x00dev, 50, 0x00); 7602 rt2800_rfcsr_write(rt2x00dev, 51, 0x00); 7603 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7604 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7605 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 7606 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7607 rt2800_rfcsr_write(rt2x00dev, 56, 0x82); 7608 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 7609 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 7610 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b); 7611 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7612 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 7613 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7614 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7615 } 7616 7617 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) 7618 { 7619 rt2800_rf_init_calibration(rt2x00dev, 2); 7620 7621 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 7622 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7623 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 7624 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7625 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7626 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 7627 else 7628 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 7629 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7630 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7631 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7632 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7633 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7634 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7635 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7636 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 7637 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7638 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 7639 7640 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7641 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7642 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7643 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7644 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7645 if (rt2x00_is_usb(rt2x00dev) && 7646 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7647 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7648 else 7649 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); 7650 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7651 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7652 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7653 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7654 7655 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7656 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7657 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7658 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7659 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 7660 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7661 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7662 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 7663 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7664 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7665 7666 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7667 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7668 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); 7669 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); 7670 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7671 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7672 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7673 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7674 else 7675 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); 7676 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7677 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7678 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 7679 7680 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7681 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7682 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7683 else 7684 rt2800_rfcsr_write(rt2x00dev, 53, 0x84); 7685 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 7686 rt2800_rfcsr_write(rt2x00dev, 55, 0x44); 7687 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 7688 rt2800_rfcsr_write(rt2x00dev, 56, 0x42); 7689 else 7690 rt2800_rfcsr_write(rt2x00dev, 56, 0x22); 7691 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 7692 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 7693 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f); 7694 7695 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7696 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 7697 if (rt2x00_is_usb(rt2x00dev)) 7698 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 7699 else 7700 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5); 7701 } else { 7702 if (rt2x00_is_usb(rt2x00dev)) 7703 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); 7704 else 7705 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5); 7706 } 7707 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7708 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7709 7710 rt2800_normal_mode_setup_5xxx(rt2x00dev); 7711 7712 rt2800_led_open_drain_enable(rt2x00dev); 7713 } 7714 7715 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) 7716 { 7717 rt2800_rf_init_calibration(rt2x00dev, 2); 7718 7719 rt2800_rfcsr_write(rt2x00dev, 1, 0x17); 7720 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 7721 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7722 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 7723 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7724 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7725 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7726 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7727 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7728 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7729 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7730 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 7731 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7732 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d); 7733 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7734 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d); 7735 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7736 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b); 7737 rt2800_rfcsr_write(rt2x00dev, 24, 0x44); 7738 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7739 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7740 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7741 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7742 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7743 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7744 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7745 rt2800_rfcsr_write(rt2x00dev, 32, 0x20); 7746 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 7747 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 7748 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7749 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7750 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 7751 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 7752 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7753 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f); 7754 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7755 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7756 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 7757 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7758 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7759 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7760 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c); 7761 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7762 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 7763 rt2800_rfcsr_write(rt2x00dev, 50, 0x94); 7764 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a); 7765 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 7766 rt2800_rfcsr_write(rt2x00dev, 53, 0x44); 7767 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 7768 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7769 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1); 7770 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 7771 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 7772 rt2800_rfcsr_write(rt2x00dev, 59, 0x07); 7773 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7774 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 7775 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 7776 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 7777 7778 rt2800_normal_mode_setup_5xxx(rt2x00dev); 7779 7780 rt2800_led_open_drain_enable(rt2x00dev); 7781 } 7782 7783 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev) 7784 { 7785 rt2800_rf_init_calibration(rt2x00dev, 30); 7786 7787 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F); 7788 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7789 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7790 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4); 7791 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7792 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7793 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7794 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 7795 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7796 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D); 7797 rt2800_rfcsr_write(rt2x00dev, 20, 0x10); 7798 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D); 7799 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7800 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7801 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7802 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 7803 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 7804 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7805 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C); 7806 rt2800_rfcsr_write(rt2x00dev, 53, 0x22); 7807 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 7808 7809 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7810 msleep(1); 7811 7812 rt2800_freq_cal_mode1(rt2x00dev); 7813 7814 /* Enable DC filter */ 7815 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 7816 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 7817 7818 rt2800_normal_mode_setup_5xxx(rt2x00dev); 7819 7820 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C)) 7821 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7822 7823 rt2800_led_open_drain_enable(rt2x00dev); 7824 } 7825 7826 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev, 7827 bool set_bw, bool is_ht40) 7828 { 7829 u8 bbp_val; 7830 7831 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 7832 bbp_val |= 0x1; 7833 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 7834 usleep_range(100, 200); 7835 7836 if (set_bw) { 7837 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 7838 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40); 7839 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 7840 usleep_range(100, 200); 7841 } 7842 7843 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 7844 bbp_val &= (~0x1); 7845 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 7846 usleep_range(100, 200); 7847 } 7848 7849 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal) 7850 { 7851 u8 rf_val; 7852 7853 if (btxcal) 7854 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 7855 else 7856 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02); 7857 7858 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06); 7859 7860 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 7861 rf_val |= 0x80; 7862 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val); 7863 7864 if (btxcal) { 7865 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1); 7866 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20); 7867 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 7868 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 7869 rf_val &= (~0x3F); 7870 rf_val |= 0x3F; 7871 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 7872 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 7873 rf_val &= (~0x3F); 7874 rf_val |= 0x3F; 7875 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 7876 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31); 7877 } else { 7878 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1); 7879 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18); 7880 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 7881 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 7882 rf_val &= (~0x3F); 7883 rf_val |= 0x34; 7884 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 7885 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 7886 rf_val &= (~0x3F); 7887 rf_val |= 0x34; 7888 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 7889 } 7890 7891 return 0; 7892 } 7893 7894 static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev) 7895 { 7896 unsigned int cnt; 7897 u8 bbp_val; 7898 char cal_val; 7899 7900 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82); 7901 7902 cnt = 0; 7903 do { 7904 usleep_range(500, 2000); 7905 bbp_val = rt2800_bbp_read(rt2x00dev, 159); 7906 if (bbp_val == 0x02 || cnt == 20) 7907 break; 7908 7909 cnt++; 7910 } while (cnt < 20); 7911 7912 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39); 7913 cal_val = bbp_val & 0x7F; 7914 if (cal_val >= 0x40) 7915 cal_val -= 128; 7916 7917 return cal_val; 7918 } 7919 7920 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev, 7921 bool btxcal) 7922 { 7923 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7924 u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc; 7925 u8 filter_target; 7926 u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02; 7927 u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31; 7928 int loop = 0, is_ht40, cnt; 7929 u8 bbp_val, rf_val; 7930 char cal_r32_init, cal_r32_val, cal_diff; 7931 u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05; 7932 u8 saverfb5r06, saverfb5r07; 7933 u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20; 7934 u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41; 7935 u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46; 7936 u8 saverfb5r58, saverfb5r59; 7937 u8 savebbp159r0, savebbp159r2, savebbpr23; 7938 u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0; 7939 7940 /* Save MAC registers */ 7941 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 7942 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 7943 7944 /* save BBP registers */ 7945 savebbpr23 = rt2800_bbp_read(rt2x00dev, 23); 7946 7947 savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0); 7948 savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2); 7949 7950 /* Save RF registers */ 7951 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 7952 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 7953 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 7954 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 7955 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5); 7956 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 7957 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 7958 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 7959 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 7960 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 7961 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 7962 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 7963 7964 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37); 7965 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38); 7966 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39); 7967 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40); 7968 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41); 7969 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42); 7970 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43); 7971 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44); 7972 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45); 7973 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46); 7974 7975 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 7976 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 7977 7978 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 7979 rf_val |= 0x3; 7980 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 7981 7982 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 7983 rf_val |= 0x1; 7984 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val); 7985 7986 cnt = 0; 7987 do { 7988 usleep_range(500, 2000); 7989 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 7990 if (((rf_val & 0x1) == 0x00) || (cnt == 40)) 7991 break; 7992 cnt++; 7993 } while (cnt < 40); 7994 7995 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 7996 rf_val &= (~0x3); 7997 rf_val |= 0x1; 7998 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 7999 8000 /* I-3 */ 8001 bbp_val = rt2800_bbp_read(rt2x00dev, 23); 8002 bbp_val &= (~0x1F); 8003 bbp_val |= 0x10; 8004 rt2800_bbp_write(rt2x00dev, 23, bbp_val); 8005 8006 do { 8007 /* I-4,5,6,7,8,9 */ 8008 if (loop == 0) { 8009 is_ht40 = false; 8010 8011 if (btxcal) 8012 filter_target = tx_filter_target_20m; 8013 else 8014 filter_target = rx_filter_target_20m; 8015 } else { 8016 is_ht40 = true; 8017 8018 if (btxcal) 8019 filter_target = tx_filter_target_40m; 8020 else 8021 filter_target = rx_filter_target_40m; 8022 } 8023 8024 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 8025 rf_val &= (~0x04); 8026 if (loop == 1) 8027 rf_val |= 0x4; 8028 8029 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val); 8030 8031 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40); 8032 8033 rt2800_rf_lp_config(rt2x00dev, btxcal); 8034 if (btxcal) { 8035 tx_agc_fc = 0; 8036 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 8037 rf_val &= (~0x7F); 8038 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 8039 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 8040 rf_val &= (~0x7F); 8041 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 8042 } else { 8043 rx_agc_fc = 0; 8044 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 8045 rf_val &= (~0x7F); 8046 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 8047 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 8048 rf_val &= (~0x7F); 8049 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 8050 } 8051 8052 usleep_range(1000, 2000); 8053 8054 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 8055 bbp_val &= (~0x6); 8056 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 8057 8058 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 8059 8060 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 8061 8062 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 8063 bbp_val |= 0x6; 8064 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 8065 do_cal: 8066 if (btxcal) { 8067 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 8068 rf_val &= (~0x7F); 8069 rf_val |= tx_agc_fc; 8070 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 8071 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 8072 rf_val &= (~0x7F); 8073 rf_val |= tx_agc_fc; 8074 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 8075 } else { 8076 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 8077 rf_val &= (~0x7F); 8078 rf_val |= rx_agc_fc; 8079 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 8080 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 8081 rf_val &= (~0x7F); 8082 rf_val |= rx_agc_fc; 8083 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 8084 } 8085 8086 usleep_range(500, 1000); 8087 8088 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 8089 8090 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 8091 8092 cal_diff = cal_r32_init - cal_r32_val; 8093 8094 if (btxcal) 8095 cmm_agc_fc = tx_agc_fc; 8096 else 8097 cmm_agc_fc = rx_agc_fc; 8098 8099 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) || 8100 ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) { 8101 if (btxcal) 8102 tx_agc_fc = 0; 8103 else 8104 rx_agc_fc = 0; 8105 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) { 8106 if (btxcal) 8107 tx_agc_fc++; 8108 else 8109 rx_agc_fc++; 8110 goto do_cal; 8111 } 8112 8113 if (btxcal) { 8114 if (loop == 0) 8115 drv_data->tx_calibration_bw20 = tx_agc_fc; 8116 else 8117 drv_data->tx_calibration_bw40 = tx_agc_fc; 8118 } else { 8119 if (loop == 0) 8120 drv_data->rx_calibration_bw20 = rx_agc_fc; 8121 else 8122 drv_data->rx_calibration_bw40 = rx_agc_fc; 8123 } 8124 8125 loop++; 8126 } while (loop <= 1); 8127 8128 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00); 8129 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01); 8130 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03); 8131 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04); 8132 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05); 8133 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06); 8134 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07); 8135 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08); 8136 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); 8137 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); 8138 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); 8139 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); 8140 8141 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37); 8142 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38); 8143 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39); 8144 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40); 8145 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41); 8146 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42); 8147 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43); 8148 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44); 8149 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45); 8150 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46); 8151 8152 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58); 8153 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59); 8154 8155 rt2800_bbp_write(rt2x00dev, 23, savebbpr23); 8156 8157 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0); 8158 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2); 8159 8160 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 8161 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 8162 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)); 8163 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 8164 8165 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); 8166 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); 8167 } 8168 8169 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev) 8170 { 8171 /* Initialize RF central register to default value */ 8172 rt2800_rfcsr_write(rt2x00dev, 0, 0x02); 8173 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 8174 rt2800_rfcsr_write(rt2x00dev, 2, 0x33); 8175 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF); 8176 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 8177 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 8178 rt2800_rfcsr_write(rt2x00dev, 6, 0x00); 8179 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8180 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 8181 rt2800_rfcsr_write(rt2x00dev, 9, 0x00); 8182 rt2800_rfcsr_write(rt2x00dev, 10, 0x00); 8183 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 8184 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset); 8185 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 8186 rt2800_rfcsr_write(rt2x00dev, 14, 0x40); 8187 rt2800_rfcsr_write(rt2x00dev, 15, 0x22); 8188 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C); 8189 rt2800_rfcsr_write(rt2x00dev, 17, 0x00); 8190 rt2800_rfcsr_write(rt2x00dev, 18, 0x00); 8191 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8192 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0); 8193 rt2800_rfcsr_write(rt2x00dev, 21, 0x12); 8194 rt2800_rfcsr_write(rt2x00dev, 22, 0x07); 8195 rt2800_rfcsr_write(rt2x00dev, 23, 0x13); 8196 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE); 8197 rt2800_rfcsr_write(rt2x00dev, 25, 0x24); 8198 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A); 8199 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8200 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8201 rt2800_rfcsr_write(rt2x00dev, 29, 0x05); 8202 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 8203 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 8204 rt2800_rfcsr_write(rt2x00dev, 32, 0x00); 8205 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8206 rt2800_rfcsr_write(rt2x00dev, 34, 0x00); 8207 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 8208 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8209 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 8210 rt2800_rfcsr_write(rt2x00dev, 38, 0x00); 8211 rt2800_rfcsr_write(rt2x00dev, 39, 0x00); 8212 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 8213 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0); 8214 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B); 8215 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 8216 8217 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 8218 if (rt2800_clk_is_20mhz(rt2x00dev)) 8219 rt2800_rfcsr_write(rt2x00dev, 13, 0x03); 8220 else 8221 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 8222 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C); 8223 rt2800_rfcsr_write(rt2x00dev, 16, 0x80); 8224 rt2800_rfcsr_write(rt2x00dev, 17, 0x99); 8225 rt2800_rfcsr_write(rt2x00dev, 18, 0x99); 8226 rt2800_rfcsr_write(rt2x00dev, 19, 0x09); 8227 rt2800_rfcsr_write(rt2x00dev, 20, 0x50); 8228 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0); 8229 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 8230 rt2800_rfcsr_write(rt2x00dev, 23, 0x06); 8231 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8232 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 8233 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D); 8234 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8235 rt2800_rfcsr_write(rt2x00dev, 28, 0x61); 8236 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5); 8237 rt2800_rfcsr_write(rt2x00dev, 43, 0x02); 8238 8239 rt2800_rfcsr_write(rt2x00dev, 28, 0x62); 8240 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD); 8241 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 8242 8243 /* Initialize RF channel register to default value */ 8244 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03); 8245 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00); 8246 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00); 8247 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00); 8248 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00); 8249 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08); 8250 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00); 8251 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51); 8252 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53); 8253 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16); 8254 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61); 8255 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 8256 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22); 8257 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D); 8258 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 8259 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13); 8260 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22); 8261 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27); 8262 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02); 8263 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 8264 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01); 8265 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52); 8266 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80); 8267 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3); 8268 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00); 8269 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00); 8270 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00); 8271 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00); 8272 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C); 8273 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B); 8274 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B); 8275 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31); 8276 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D); 8277 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00); 8278 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6); 8279 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55); 8280 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00); 8281 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB); 8282 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3); 8283 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3); 8284 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03); 8285 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00); 8286 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00); 8287 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3); 8288 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3); 8289 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 8290 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07); 8291 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68); 8292 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF); 8293 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C); 8294 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07); 8295 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8); 8296 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85); 8297 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10); 8298 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07); 8299 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A); 8300 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85); 8301 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10); 8302 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C); 8303 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00); 8304 8305 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5); 8306 8307 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47); 8308 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71); 8309 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33); 8310 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E); 8311 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23); 8312 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4); 8313 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02); 8314 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12); 8315 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C); 8316 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB); 8317 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D); 8318 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6); 8319 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08); 8320 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4); 8321 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 8322 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3); 8323 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 8324 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); 8325 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67); 8326 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69); 8327 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF); 8328 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27); 8329 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20); 8330 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 8331 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF); 8332 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C); 8333 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20); 8334 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 8335 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7); 8336 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09); 8337 8338 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51); 8339 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 8340 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 8341 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C); 8342 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64); 8343 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51); 8344 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36); 8345 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 8346 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16); 8347 8348 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C); 8349 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC); 8350 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F); 8351 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); 8352 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 8353 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 8354 8355 /* Initialize RF channel register for DRQFN */ 8356 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 8357 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3); 8358 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5); 8359 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28); 8360 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68); 8361 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7); 8362 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02); 8363 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7); 8364 8365 /* Initialize RF DC calibration register to default value */ 8366 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47); 8367 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00); 8368 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00); 8369 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00); 8370 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00); 8371 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 8372 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 8373 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 8374 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 8375 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00); 8376 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07); 8377 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01); 8378 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07); 8379 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07); 8380 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07); 8381 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20); 8382 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22); 8383 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00); 8384 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00); 8385 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00); 8386 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00); 8387 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1); 8388 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11); 8389 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02); 8390 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41); 8391 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20); 8392 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00); 8393 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7); 8394 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2); 8395 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20); 8396 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49); 8397 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20); 8398 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04); 8399 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1); 8400 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1); 8401 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01); 8402 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00); 8403 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00); 8404 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00); 8405 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00); 8406 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00); 8407 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00); 8408 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E); 8409 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D); 8410 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E); 8411 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D); 8412 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E); 8413 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D); 8414 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00); 8415 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00); 8416 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00); 8417 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00); 8418 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00); 8419 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 8420 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 8421 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A); 8422 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00); 8423 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00); 8424 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00); 8425 8426 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08); 8427 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04); 8428 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20); 8429 8430 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 8431 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C); 8432 8433 rt2800_bw_filter_calibration(rt2x00dev, true); 8434 rt2800_bw_filter_calibration(rt2x00dev, false); 8435 } 8436 8437 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) 8438 { 8439 if (rt2800_is_305x_soc(rt2x00dev)) { 8440 rt2800_init_rfcsr_305x_soc(rt2x00dev); 8441 return; 8442 } 8443 8444 switch (rt2x00dev->chip.rt) { 8445 case RT3070: 8446 case RT3071: 8447 case RT3090: 8448 rt2800_init_rfcsr_30xx(rt2x00dev); 8449 break; 8450 case RT3290: 8451 rt2800_init_rfcsr_3290(rt2x00dev); 8452 break; 8453 case RT3352: 8454 rt2800_init_rfcsr_3352(rt2x00dev); 8455 break; 8456 case RT3390: 8457 rt2800_init_rfcsr_3390(rt2x00dev); 8458 break; 8459 case RT3572: 8460 rt2800_init_rfcsr_3572(rt2x00dev); 8461 break; 8462 case RT3593: 8463 rt2800_init_rfcsr_3593(rt2x00dev); 8464 break; 8465 case RT5350: 8466 rt2800_init_rfcsr_5350(rt2x00dev); 8467 break; 8468 case RT5390: 8469 rt2800_init_rfcsr_5390(rt2x00dev); 8470 break; 8471 case RT5392: 8472 rt2800_init_rfcsr_5392(rt2x00dev); 8473 break; 8474 case RT5592: 8475 rt2800_init_rfcsr_5592(rt2x00dev); 8476 break; 8477 case RT6352: 8478 rt2800_init_rfcsr_6352(rt2x00dev); 8479 break; 8480 } 8481 } 8482 8483 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) 8484 { 8485 u32 reg; 8486 u16 word; 8487 8488 /* 8489 * Initialize MAC registers. 8490 */ 8491 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || 8492 rt2800_init_registers(rt2x00dev))) 8493 return -EIO; 8494 8495 /* 8496 * Wait BBP/RF to wake up. 8497 */ 8498 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev))) 8499 return -EIO; 8500 8501 /* 8502 * Send signal during boot time to initialize firmware. 8503 */ 8504 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 8505 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 8506 if (rt2x00_is_usb(rt2x00dev)) 8507 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 8508 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 8509 msleep(1); 8510 8511 /* 8512 * Make sure BBP is up and running. 8513 */ 8514 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev))) 8515 return -EIO; 8516 8517 /* 8518 * Initialize BBP/RF registers. 8519 */ 8520 rt2800_init_bbp(rt2x00dev); 8521 rt2800_init_rfcsr(rt2x00dev); 8522 8523 if (rt2x00_is_usb(rt2x00dev) && 8524 (rt2x00_rt(rt2x00dev, RT3070) || 8525 rt2x00_rt(rt2x00dev, RT3071) || 8526 rt2x00_rt(rt2x00dev, RT3572))) { 8527 udelay(200); 8528 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); 8529 udelay(10); 8530 } 8531 8532 /* 8533 * Enable RX. 8534 */ 8535 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8536 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 8537 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 8538 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 8539 8540 udelay(50); 8541 8542 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 8543 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 8544 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 8545 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 8546 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 8547 8548 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8549 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 8550 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); 8551 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 8552 8553 /* 8554 * Initialize LED control 8555 */ 8556 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF); 8557 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, 8558 word & 0xff, (word >> 8) & 0xff); 8559 8560 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF); 8561 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, 8562 word & 0xff, (word >> 8) & 0xff); 8563 8564 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY); 8565 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, 8566 word & 0xff, (word >> 8) & 0xff); 8567 8568 return 0; 8569 } 8570 EXPORT_SYMBOL_GPL(rt2800_enable_radio); 8571 8572 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) 8573 { 8574 u32 reg; 8575 8576 rt2800_disable_wpdma(rt2x00dev); 8577 8578 /* Wait for DMA, ignore error */ 8579 rt2800_wait_wpdma_ready(rt2x00dev); 8580 8581 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8582 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); 8583 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 8584 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 8585 } 8586 EXPORT_SYMBOL_GPL(rt2800_disable_radio); 8587 8588 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 8589 { 8590 u32 reg; 8591 u16 efuse_ctrl_reg; 8592 8593 if (rt2x00_rt(rt2x00dev, RT3290)) 8594 efuse_ctrl_reg = EFUSE_CTRL_3290; 8595 else 8596 efuse_ctrl_reg = EFUSE_CTRL; 8597 8598 reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg); 8599 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); 8600 } 8601 EXPORT_SYMBOL_GPL(rt2800_efuse_detect); 8602 8603 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) 8604 { 8605 u32 reg; 8606 u16 efuse_ctrl_reg; 8607 u16 efuse_data0_reg; 8608 u16 efuse_data1_reg; 8609 u16 efuse_data2_reg; 8610 u16 efuse_data3_reg; 8611 8612 if (rt2x00_rt(rt2x00dev, RT3290)) { 8613 efuse_ctrl_reg = EFUSE_CTRL_3290; 8614 efuse_data0_reg = EFUSE_DATA0_3290; 8615 efuse_data1_reg = EFUSE_DATA1_3290; 8616 efuse_data2_reg = EFUSE_DATA2_3290; 8617 efuse_data3_reg = EFUSE_DATA3_3290; 8618 } else { 8619 efuse_ctrl_reg = EFUSE_CTRL; 8620 efuse_data0_reg = EFUSE_DATA0; 8621 efuse_data1_reg = EFUSE_DATA1; 8622 efuse_data2_reg = EFUSE_DATA2; 8623 efuse_data3_reg = EFUSE_DATA3; 8624 } 8625 mutex_lock(&rt2x00dev->csr_mutex); 8626 8627 reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg); 8628 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); 8629 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); 8630 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); 8631 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); 8632 8633 /* Wait until the EEPROM has been loaded */ 8634 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); 8635 /* Apparently the data is read from end to start */ 8636 reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg); 8637 /* The returned value is in CPU order, but eeprom is le */ 8638 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); 8639 reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg); 8640 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); 8641 reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg); 8642 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); 8643 reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg); 8644 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); 8645 8646 mutex_unlock(&rt2x00dev->csr_mutex); 8647 } 8648 8649 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 8650 { 8651 unsigned int i; 8652 8653 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) 8654 rt2800_efuse_read(rt2x00dev, i); 8655 8656 return 0; 8657 } 8658 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); 8659 8660 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev) 8661 { 8662 u16 word; 8663 8664 if (rt2x00_rt(rt2x00dev, RT3593)) 8665 return 0; 8666 8667 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG); 8668 if ((word & 0x00ff) != 0x00ff) 8669 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL); 8670 8671 return 0; 8672 } 8673 8674 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev) 8675 { 8676 u16 word; 8677 8678 if (rt2x00_rt(rt2x00dev, RT3593)) 8679 return 0; 8680 8681 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A); 8682 if ((word & 0x00ff) != 0x00ff) 8683 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL); 8684 8685 return 0; 8686 } 8687 8688 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) 8689 { 8690 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 8691 u16 word; 8692 u8 *mac; 8693 u8 default_lna_gain; 8694 int retval; 8695 8696 /* 8697 * Read the EEPROM. 8698 */ 8699 retval = rt2800_read_eeprom(rt2x00dev); 8700 if (retval) 8701 return retval; 8702 8703 /* 8704 * Start validation of the data that has been read. 8705 */ 8706 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 8707 rt2x00lib_set_mac_address(rt2x00dev, mac); 8708 8709 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 8710 if (word == 0xffff) { 8711 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 8712 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); 8713 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); 8714 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 8715 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 8716 } else if (rt2x00_rt(rt2x00dev, RT2860) || 8717 rt2x00_rt(rt2x00dev, RT2872)) { 8718 /* 8719 * There is a max of 2 RX streams for RT28x0 series 8720 */ 8721 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2) 8722 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 8723 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 8724 } 8725 8726 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 8727 if (word == 0xffff) { 8728 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); 8729 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); 8730 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0); 8731 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0); 8732 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0); 8733 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0); 8734 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0); 8735 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0); 8736 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0); 8737 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0); 8738 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0); 8739 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0); 8740 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0); 8741 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); 8742 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); 8743 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); 8744 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 8745 } 8746 8747 word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 8748 if ((word & 0x00ff) == 0x00ff) { 8749 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 8750 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 8751 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); 8752 } 8753 if ((word & 0xff00) == 0xff00) { 8754 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, 8755 LED_MODE_TXRX_ACTIVITY); 8756 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); 8757 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 8758 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); 8759 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); 8760 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); 8761 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word); 8762 } 8763 8764 /* 8765 * During the LNA validation we are going to use 8766 * lna0 as correct value. Note that EEPROM_LNA 8767 * is never validated. 8768 */ 8769 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 8770 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); 8771 8772 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 8773 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) 8774 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); 8775 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) 8776 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); 8777 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); 8778 8779 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev); 8780 8781 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 8782 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) 8783 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); 8784 if (!rt2x00_rt(rt2x00dev, RT3593)) { 8785 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || 8786 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) 8787 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, 8788 default_lna_gain); 8789 } 8790 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); 8791 8792 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev); 8793 8794 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 8795 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) 8796 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); 8797 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) 8798 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); 8799 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); 8800 8801 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 8802 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) 8803 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); 8804 if (!rt2x00_rt(rt2x00dev, RT3593)) { 8805 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || 8806 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) 8807 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, 8808 default_lna_gain); 8809 } 8810 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); 8811 8812 if (rt2x00_rt(rt2x00dev, RT3593)) { 8813 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 8814 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 || 8815 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff) 8816 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 8817 default_lna_gain); 8818 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 || 8819 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff) 8820 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 8821 default_lna_gain); 8822 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word); 8823 } 8824 8825 return 0; 8826 } 8827 8828 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) 8829 { 8830 u16 value; 8831 u16 eeprom; 8832 u16 rf; 8833 8834 /* 8835 * Read EEPROM word for configuration. 8836 */ 8837 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 8838 8839 /* 8840 * Identify RF chipset by EEPROM value 8841 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 8842 * RT53xx: defined in "EEPROM_CHIP_ID" field 8843 */ 8844 if (rt2x00_rt(rt2x00dev, RT3290) || 8845 rt2x00_rt(rt2x00dev, RT5390) || 8846 rt2x00_rt(rt2x00dev, RT5392) || 8847 rt2x00_rt(rt2x00dev, RT6352)) 8848 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID); 8849 else if (rt2x00_rt(rt2x00dev, RT3352)) 8850 rf = RF3322; 8851 else if (rt2x00_rt(rt2x00dev, RT5350)) 8852 rf = RF5350; 8853 else 8854 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 8855 8856 switch (rf) { 8857 case RF2820: 8858 case RF2850: 8859 case RF2720: 8860 case RF2750: 8861 case RF3020: 8862 case RF2020: 8863 case RF3021: 8864 case RF3022: 8865 case RF3052: 8866 case RF3053: 8867 case RF3070: 8868 case RF3290: 8869 case RF3320: 8870 case RF3322: 8871 case RF5350: 8872 case RF5360: 8873 case RF5362: 8874 case RF5370: 8875 case RF5372: 8876 case RF5390: 8877 case RF5392: 8878 case RF5592: 8879 case RF7620: 8880 break; 8881 default: 8882 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n", 8883 rf); 8884 return -ENODEV; 8885 } 8886 8887 rt2x00_set_rf(rt2x00dev, rf); 8888 8889 /* 8890 * Identify default antenna configuration. 8891 */ 8892 rt2x00dev->default_ant.tx_chain_num = 8893 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); 8894 rt2x00dev->default_ant.rx_chain_num = 8895 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); 8896 8897 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 8898 8899 if (rt2x00_rt(rt2x00dev, RT3070) || 8900 rt2x00_rt(rt2x00dev, RT3090) || 8901 rt2x00_rt(rt2x00dev, RT3352) || 8902 rt2x00_rt(rt2x00dev, RT3390)) { 8903 value = rt2x00_get_field16(eeprom, 8904 EEPROM_NIC_CONF1_ANT_DIVERSITY); 8905 switch (value) { 8906 case 0: 8907 case 1: 8908 case 2: 8909 rt2x00dev->default_ant.tx = ANTENNA_A; 8910 rt2x00dev->default_ant.rx = ANTENNA_A; 8911 break; 8912 case 3: 8913 rt2x00dev->default_ant.tx = ANTENNA_A; 8914 rt2x00dev->default_ant.rx = ANTENNA_B; 8915 break; 8916 } 8917 } else { 8918 rt2x00dev->default_ant.tx = ANTENNA_A; 8919 rt2x00dev->default_ant.rx = ANTENNA_A; 8920 } 8921 8922 /* These chips have hardware RX antenna diversity */ 8923 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 8924 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 8925 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */ 8926 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */ 8927 } 8928 8929 /* 8930 * Determine external LNA informations. 8931 */ 8932 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G)) 8933 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); 8934 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G)) 8935 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); 8936 8937 /* 8938 * Detect if this device has an hardware controlled radio. 8939 */ 8940 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO)) 8941 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 8942 8943 /* 8944 * Detect if this device has Bluetooth co-existence. 8945 */ 8946 if (!rt2x00_rt(rt2x00dev, RT3352) && 8947 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) 8948 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); 8949 8950 /* 8951 * Read frequency offset and RF programming sequence. 8952 */ 8953 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 8954 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 8955 8956 /* 8957 * Store led settings, for correct led behaviour. 8958 */ 8959 #ifdef CONFIG_RT2X00_LIB_LEDS 8960 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 8961 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 8962 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 8963 8964 rt2x00dev->led_mcu_reg = eeprom; 8965 #endif /* CONFIG_RT2X00_LIB_LEDS */ 8966 8967 /* 8968 * Check if support EIRP tx power limit feature. 8969 */ 8970 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 8971 8972 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < 8973 EIRP_MAX_TX_POWER_LIMIT) 8974 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); 8975 8976 /* 8977 * Detect if device uses internal or external PA 8978 */ 8979 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 8980 8981 if (rt2x00_rt(rt2x00dev, RT3352)) { 8982 if (rt2x00_get_field16(eeprom, 8983 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352)) 8984 __set_bit(CAPABILITY_EXTERNAL_PA_TX0, 8985 &rt2x00dev->cap_flags); 8986 if (rt2x00_get_field16(eeprom, 8987 EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352)) 8988 __set_bit(CAPABILITY_EXTERNAL_PA_TX1, 8989 &rt2x00dev->cap_flags); 8990 } 8991 8992 return 0; 8993 } 8994 8995 /* 8996 * RF value list for rt28xx 8997 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) 8998 */ 8999 static const struct rf_channel rf_vals[] = { 9000 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, 9001 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, 9002 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, 9003 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, 9004 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, 9005 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, 9006 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, 9007 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, 9008 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, 9009 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, 9010 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, 9011 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, 9012 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, 9013 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, 9014 9015 /* 802.11 UNI / HyperLan 2 */ 9016 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, 9017 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, 9018 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, 9019 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, 9020 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, 9021 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, 9022 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, 9023 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, 9024 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, 9025 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, 9026 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, 9027 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, 9028 9029 /* 802.11 HyperLan 2 */ 9030 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, 9031 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, 9032 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, 9033 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, 9034 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, 9035 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, 9036 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, 9037 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, 9038 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, 9039 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, 9040 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, 9041 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, 9042 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, 9043 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, 9044 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, 9045 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, 9046 9047 /* 802.11 UNII */ 9048 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, 9049 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, 9050 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, 9051 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, 9052 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, 9053 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, 9054 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, 9055 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, 9056 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, 9057 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, 9058 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, 9059 9060 /* 802.11 Japan */ 9061 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, 9062 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, 9063 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, 9064 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, 9065 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, 9066 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, 9067 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, 9068 }; 9069 9070 /* 9071 * RF value list for rt3xxx 9072 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053) 9073 */ 9074 static const struct rf_channel rf_vals_3x[] = { 9075 {1, 241, 2, 2 }, 9076 {2, 241, 2, 7 }, 9077 {3, 242, 2, 2 }, 9078 {4, 242, 2, 7 }, 9079 {5, 243, 2, 2 }, 9080 {6, 243, 2, 7 }, 9081 {7, 244, 2, 2 }, 9082 {8, 244, 2, 7 }, 9083 {9, 245, 2, 2 }, 9084 {10, 245, 2, 7 }, 9085 {11, 246, 2, 2 }, 9086 {12, 246, 2, 7 }, 9087 {13, 247, 2, 2 }, 9088 {14, 248, 2, 4 }, 9089 9090 /* 802.11 UNI / HyperLan 2 */ 9091 {36, 0x56, 0, 4}, 9092 {38, 0x56, 0, 6}, 9093 {40, 0x56, 0, 8}, 9094 {44, 0x57, 0, 0}, 9095 {46, 0x57, 0, 2}, 9096 {48, 0x57, 0, 4}, 9097 {52, 0x57, 0, 8}, 9098 {54, 0x57, 0, 10}, 9099 {56, 0x58, 0, 0}, 9100 {60, 0x58, 0, 4}, 9101 {62, 0x58, 0, 6}, 9102 {64, 0x58, 0, 8}, 9103 9104 /* 802.11 HyperLan 2 */ 9105 {100, 0x5b, 0, 8}, 9106 {102, 0x5b, 0, 10}, 9107 {104, 0x5c, 0, 0}, 9108 {108, 0x5c, 0, 4}, 9109 {110, 0x5c, 0, 6}, 9110 {112, 0x5c, 0, 8}, 9111 {116, 0x5d, 0, 0}, 9112 {118, 0x5d, 0, 2}, 9113 {120, 0x5d, 0, 4}, 9114 {124, 0x5d, 0, 8}, 9115 {126, 0x5d, 0, 10}, 9116 {128, 0x5e, 0, 0}, 9117 {132, 0x5e, 0, 4}, 9118 {134, 0x5e, 0, 6}, 9119 {136, 0x5e, 0, 8}, 9120 {140, 0x5f, 0, 0}, 9121 9122 /* 802.11 UNII */ 9123 {149, 0x5f, 0, 9}, 9124 {151, 0x5f, 0, 11}, 9125 {153, 0x60, 0, 1}, 9126 {157, 0x60, 0, 5}, 9127 {159, 0x60, 0, 7}, 9128 {161, 0x60, 0, 9}, 9129 {165, 0x61, 0, 1}, 9130 {167, 0x61, 0, 3}, 9131 {169, 0x61, 0, 5}, 9132 {171, 0x61, 0, 7}, 9133 {173, 0x61, 0, 9}, 9134 }; 9135 9136 /* 9137 * RF value list for rt3xxx with Xtal20MHz 9138 * Supports: 2.4 GHz (all) (RF3322) 9139 */ 9140 static const struct rf_channel rf_vals_3x_xtal20[] = { 9141 {1, 0xE2, 2, 0x14}, 9142 {2, 0xE3, 2, 0x14}, 9143 {3, 0xE4, 2, 0x14}, 9144 {4, 0xE5, 2, 0x14}, 9145 {5, 0xE6, 2, 0x14}, 9146 {6, 0xE7, 2, 0x14}, 9147 {7, 0xE8, 2, 0x14}, 9148 {8, 0xE9, 2, 0x14}, 9149 {9, 0xEA, 2, 0x14}, 9150 {10, 0xEB, 2, 0x14}, 9151 {11, 0xEC, 2, 0x14}, 9152 {12, 0xED, 2, 0x14}, 9153 {13, 0xEE, 2, 0x14}, 9154 {14, 0xF0, 2, 0x18}, 9155 }; 9156 9157 static const struct rf_channel rf_vals_5592_xtal20[] = { 9158 /* Channel, N, K, mod, R */ 9159 {1, 482, 4, 10, 3}, 9160 {2, 483, 4, 10, 3}, 9161 {3, 484, 4, 10, 3}, 9162 {4, 485, 4, 10, 3}, 9163 {5, 486, 4, 10, 3}, 9164 {6, 487, 4, 10, 3}, 9165 {7, 488, 4, 10, 3}, 9166 {8, 489, 4, 10, 3}, 9167 {9, 490, 4, 10, 3}, 9168 {10, 491, 4, 10, 3}, 9169 {11, 492, 4, 10, 3}, 9170 {12, 493, 4, 10, 3}, 9171 {13, 494, 4, 10, 3}, 9172 {14, 496, 8, 10, 3}, 9173 {36, 172, 8, 12, 1}, 9174 {38, 173, 0, 12, 1}, 9175 {40, 173, 4, 12, 1}, 9176 {42, 173, 8, 12, 1}, 9177 {44, 174, 0, 12, 1}, 9178 {46, 174, 4, 12, 1}, 9179 {48, 174, 8, 12, 1}, 9180 {50, 175, 0, 12, 1}, 9181 {52, 175, 4, 12, 1}, 9182 {54, 175, 8, 12, 1}, 9183 {56, 176, 0, 12, 1}, 9184 {58, 176, 4, 12, 1}, 9185 {60, 176, 8, 12, 1}, 9186 {62, 177, 0, 12, 1}, 9187 {64, 177, 4, 12, 1}, 9188 {100, 183, 4, 12, 1}, 9189 {102, 183, 8, 12, 1}, 9190 {104, 184, 0, 12, 1}, 9191 {106, 184, 4, 12, 1}, 9192 {108, 184, 8, 12, 1}, 9193 {110, 185, 0, 12, 1}, 9194 {112, 185, 4, 12, 1}, 9195 {114, 185, 8, 12, 1}, 9196 {116, 186, 0, 12, 1}, 9197 {118, 186, 4, 12, 1}, 9198 {120, 186, 8, 12, 1}, 9199 {122, 187, 0, 12, 1}, 9200 {124, 187, 4, 12, 1}, 9201 {126, 187, 8, 12, 1}, 9202 {128, 188, 0, 12, 1}, 9203 {130, 188, 4, 12, 1}, 9204 {132, 188, 8, 12, 1}, 9205 {134, 189, 0, 12, 1}, 9206 {136, 189, 4, 12, 1}, 9207 {138, 189, 8, 12, 1}, 9208 {140, 190, 0, 12, 1}, 9209 {149, 191, 6, 12, 1}, 9210 {151, 191, 10, 12, 1}, 9211 {153, 192, 2, 12, 1}, 9212 {155, 192, 6, 12, 1}, 9213 {157, 192, 10, 12, 1}, 9214 {159, 193, 2, 12, 1}, 9215 {161, 193, 6, 12, 1}, 9216 {165, 194, 2, 12, 1}, 9217 {184, 164, 0, 12, 1}, 9218 {188, 164, 4, 12, 1}, 9219 {192, 165, 8, 12, 1}, 9220 {196, 166, 0, 12, 1}, 9221 }; 9222 9223 static const struct rf_channel rf_vals_5592_xtal40[] = { 9224 /* Channel, N, K, mod, R */ 9225 {1, 241, 2, 10, 3}, 9226 {2, 241, 7, 10, 3}, 9227 {3, 242, 2, 10, 3}, 9228 {4, 242, 7, 10, 3}, 9229 {5, 243, 2, 10, 3}, 9230 {6, 243, 7, 10, 3}, 9231 {7, 244, 2, 10, 3}, 9232 {8, 244, 7, 10, 3}, 9233 {9, 245, 2, 10, 3}, 9234 {10, 245, 7, 10, 3}, 9235 {11, 246, 2, 10, 3}, 9236 {12, 246, 7, 10, 3}, 9237 {13, 247, 2, 10, 3}, 9238 {14, 248, 4, 10, 3}, 9239 {36, 86, 4, 12, 1}, 9240 {38, 86, 6, 12, 1}, 9241 {40, 86, 8, 12, 1}, 9242 {42, 86, 10, 12, 1}, 9243 {44, 87, 0, 12, 1}, 9244 {46, 87, 2, 12, 1}, 9245 {48, 87, 4, 12, 1}, 9246 {50, 87, 6, 12, 1}, 9247 {52, 87, 8, 12, 1}, 9248 {54, 87, 10, 12, 1}, 9249 {56, 88, 0, 12, 1}, 9250 {58, 88, 2, 12, 1}, 9251 {60, 88, 4, 12, 1}, 9252 {62, 88, 6, 12, 1}, 9253 {64, 88, 8, 12, 1}, 9254 {100, 91, 8, 12, 1}, 9255 {102, 91, 10, 12, 1}, 9256 {104, 92, 0, 12, 1}, 9257 {106, 92, 2, 12, 1}, 9258 {108, 92, 4, 12, 1}, 9259 {110, 92, 6, 12, 1}, 9260 {112, 92, 8, 12, 1}, 9261 {114, 92, 10, 12, 1}, 9262 {116, 93, 0, 12, 1}, 9263 {118, 93, 2, 12, 1}, 9264 {120, 93, 4, 12, 1}, 9265 {122, 93, 6, 12, 1}, 9266 {124, 93, 8, 12, 1}, 9267 {126, 93, 10, 12, 1}, 9268 {128, 94, 0, 12, 1}, 9269 {130, 94, 2, 12, 1}, 9270 {132, 94, 4, 12, 1}, 9271 {134, 94, 6, 12, 1}, 9272 {136, 94, 8, 12, 1}, 9273 {138, 94, 10, 12, 1}, 9274 {140, 95, 0, 12, 1}, 9275 {149, 95, 9, 12, 1}, 9276 {151, 95, 11, 12, 1}, 9277 {153, 96, 1, 12, 1}, 9278 {155, 96, 3, 12, 1}, 9279 {157, 96, 5, 12, 1}, 9280 {159, 96, 7, 12, 1}, 9281 {161, 96, 9, 12, 1}, 9282 {165, 97, 1, 12, 1}, 9283 {184, 82, 0, 12, 1}, 9284 {188, 82, 4, 12, 1}, 9285 {192, 82, 8, 12, 1}, 9286 {196, 83, 0, 12, 1}, 9287 }; 9288 9289 static const struct rf_channel rf_vals_7620[] = { 9290 {1, 0x50, 0x99, 0x99, 1}, 9291 {2, 0x50, 0x44, 0x44, 2}, 9292 {3, 0x50, 0xEE, 0xEE, 2}, 9293 {4, 0x50, 0x99, 0x99, 3}, 9294 {5, 0x51, 0x44, 0x44, 0}, 9295 {6, 0x51, 0xEE, 0xEE, 0}, 9296 {7, 0x51, 0x99, 0x99, 1}, 9297 {8, 0x51, 0x44, 0x44, 2}, 9298 {9, 0x51, 0xEE, 0xEE, 2}, 9299 {10, 0x51, 0x99, 0x99, 3}, 9300 {11, 0x52, 0x44, 0x44, 0}, 9301 {12, 0x52, 0xEE, 0xEE, 0}, 9302 {13, 0x52, 0x99, 0x99, 1}, 9303 {14, 0x52, 0x33, 0x33, 3}, 9304 }; 9305 9306 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 9307 { 9308 struct hw_mode_spec *spec = &rt2x00dev->spec; 9309 struct channel_info *info; 9310 char *default_power1; 9311 char *default_power2; 9312 char *default_power3; 9313 unsigned int i, tx_chains, rx_chains; 9314 u32 reg; 9315 9316 /* 9317 * Disable powersaving as default. 9318 */ 9319 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 9320 9321 /* 9322 * Change default retry settings to values corresponding more closely 9323 * to rate[0].count setting of minstrel rate control algorithm. 9324 */ 9325 rt2x00dev->hw->wiphy->retry_short = 2; 9326 rt2x00dev->hw->wiphy->retry_long = 2; 9327 9328 /* 9329 * Initialize all hw fields. 9330 */ 9331 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS); 9332 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION); 9333 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); 9334 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); 9335 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); 9336 9337 /* 9338 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices 9339 * unless we are capable of sending the buffered frames out after the 9340 * DTIM transmission using rt2x00lib_beacondone. This will send out 9341 * multicast and broadcast traffic immediately instead of buffering it 9342 * infinitly and thus dropping it after some time. 9343 */ 9344 if (!rt2x00_is_usb(rt2x00dev)) 9345 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); 9346 9347 /* Set MFP if HW crypto is disabled. */ 9348 if (rt2800_hwcrypt_disabled(rt2x00dev)) 9349 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE); 9350 9351 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 9352 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 9353 rt2800_eeprom_addr(rt2x00dev, 9354 EEPROM_MAC_ADDR_0)); 9355 9356 /* 9357 * As rt2800 has a global fallback table we cannot specify 9358 * more then one tx rate per frame but since the hw will 9359 * try several rates (based on the fallback table) we should 9360 * initialize max_report_rates to the maximum number of rates 9361 * we are going to try. Otherwise mac80211 will truncate our 9362 * reported tx rates and the rc algortihm will end up with 9363 * incorrect data. 9364 */ 9365 rt2x00dev->hw->max_rates = 1; 9366 rt2x00dev->hw->max_report_rates = 7; 9367 rt2x00dev->hw->max_rate_tries = 1; 9368 9369 /* 9370 * Initialize hw_mode information. 9371 */ 9372 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 9373 9374 switch (rt2x00dev->chip.rf) { 9375 case RF2720: 9376 case RF2820: 9377 spec->num_channels = 14; 9378 spec->channels = rf_vals; 9379 break; 9380 9381 case RF2750: 9382 case RF2850: 9383 spec->num_channels = ARRAY_SIZE(rf_vals); 9384 spec->channels = rf_vals; 9385 break; 9386 9387 case RF2020: 9388 case RF3020: 9389 case RF3021: 9390 case RF3022: 9391 case RF3070: 9392 case RF3290: 9393 case RF3320: 9394 case RF3322: 9395 case RF5350: 9396 case RF5360: 9397 case RF5362: 9398 case RF5370: 9399 case RF5372: 9400 case RF5390: 9401 case RF5392: 9402 spec->num_channels = 14; 9403 if (rt2800_clk_is_20mhz(rt2x00dev)) 9404 spec->channels = rf_vals_3x_xtal20; 9405 else 9406 spec->channels = rf_vals_3x; 9407 break; 9408 9409 case RF7620: 9410 spec->num_channels = ARRAY_SIZE(rf_vals_7620); 9411 spec->channels = rf_vals_7620; 9412 break; 9413 9414 case RF3052: 9415 case RF3053: 9416 spec->num_channels = ARRAY_SIZE(rf_vals_3x); 9417 spec->channels = rf_vals_3x; 9418 break; 9419 9420 case RF5592: 9421 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX); 9422 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { 9423 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); 9424 spec->channels = rf_vals_5592_xtal40; 9425 } else { 9426 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20); 9427 spec->channels = rf_vals_5592_xtal20; 9428 } 9429 break; 9430 } 9431 9432 if (WARN_ON_ONCE(!spec->channels)) 9433 return -ENODEV; 9434 9435 spec->supported_bands = SUPPORT_BAND_2GHZ; 9436 if (spec->num_channels > 14) 9437 spec->supported_bands |= SUPPORT_BAND_5GHZ; 9438 9439 /* 9440 * Initialize HT information. 9441 */ 9442 if (!rt2x00_rf(rt2x00dev, RF2020)) 9443 spec->ht.ht_supported = true; 9444 else 9445 spec->ht.ht_supported = false; 9446 9447 spec->ht.cap = 9448 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 9449 IEEE80211_HT_CAP_GRN_FLD | 9450 IEEE80211_HT_CAP_SGI_20 | 9451 IEEE80211_HT_CAP_SGI_40; 9452 9453 tx_chains = rt2x00dev->default_ant.tx_chain_num; 9454 rx_chains = rt2x00dev->default_ant.rx_chain_num; 9455 9456 if (tx_chains >= 2) 9457 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; 9458 9459 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT; 9460 9461 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2; 9462 spec->ht.ampdu_density = 4; 9463 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 9464 if (tx_chains != rx_chains) { 9465 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 9466 spec->ht.mcs.tx_params |= 9467 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; 9468 } 9469 9470 switch (rx_chains) { 9471 case 3: 9472 spec->ht.mcs.rx_mask[2] = 0xff; 9473 /* fall through */ 9474 case 2: 9475 spec->ht.mcs.rx_mask[1] = 0xff; 9476 /* fall through */ 9477 case 1: 9478 spec->ht.mcs.rx_mask[0] = 0xff; 9479 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ 9480 break; 9481 } 9482 9483 /* 9484 * Create channel information array 9485 */ 9486 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 9487 if (!info) 9488 return -ENOMEM; 9489 9490 spec->channels_info = info; 9491 9492 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 9493 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 9494 9495 if (rt2x00dev->default_ant.tx_chain_num > 2) 9496 default_power3 = rt2800_eeprom_addr(rt2x00dev, 9497 EEPROM_EXT_TXPOWER_BG3); 9498 else 9499 default_power3 = NULL; 9500 9501 for (i = 0; i < 14; i++) { 9502 info[i].default_power1 = default_power1[i]; 9503 info[i].default_power2 = default_power2[i]; 9504 if (default_power3) 9505 info[i].default_power3 = default_power3[i]; 9506 } 9507 9508 if (spec->num_channels > 14) { 9509 default_power1 = rt2800_eeprom_addr(rt2x00dev, 9510 EEPROM_TXPOWER_A1); 9511 default_power2 = rt2800_eeprom_addr(rt2x00dev, 9512 EEPROM_TXPOWER_A2); 9513 9514 if (rt2x00dev->default_ant.tx_chain_num > 2) 9515 default_power3 = 9516 rt2800_eeprom_addr(rt2x00dev, 9517 EEPROM_EXT_TXPOWER_A3); 9518 else 9519 default_power3 = NULL; 9520 9521 for (i = 14; i < spec->num_channels; i++) { 9522 info[i].default_power1 = default_power1[i - 14]; 9523 info[i].default_power2 = default_power2[i - 14]; 9524 if (default_power3) 9525 info[i].default_power3 = default_power3[i - 14]; 9526 } 9527 } 9528 9529 switch (rt2x00dev->chip.rf) { 9530 case RF2020: 9531 case RF3020: 9532 case RF3021: 9533 case RF3022: 9534 case RF3320: 9535 case RF3052: 9536 case RF3053: 9537 case RF3070: 9538 case RF3290: 9539 case RF5350: 9540 case RF5360: 9541 case RF5362: 9542 case RF5370: 9543 case RF5372: 9544 case RF5390: 9545 case RF5392: 9546 case RF5592: 9547 case RF7620: 9548 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags); 9549 break; 9550 } 9551 9552 return 0; 9553 } 9554 9555 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) 9556 { 9557 u32 reg; 9558 u32 rt; 9559 u32 rev; 9560 9561 if (rt2x00_rt(rt2x00dev, RT3290)) 9562 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290); 9563 else 9564 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 9565 9566 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); 9567 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); 9568 9569 switch (rt) { 9570 case RT2860: 9571 case RT2872: 9572 case RT2883: 9573 case RT3070: 9574 case RT3071: 9575 case RT3090: 9576 case RT3290: 9577 case RT3352: 9578 case RT3390: 9579 case RT3572: 9580 case RT3593: 9581 case RT5350: 9582 case RT5390: 9583 case RT5392: 9584 case RT5592: 9585 break; 9586 default: 9587 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n", 9588 rt, rev); 9589 return -ENODEV; 9590 } 9591 9592 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev)) 9593 rt = RT6352; 9594 9595 rt2x00_set_rt(rt2x00dev, rt, rev); 9596 9597 return 0; 9598 } 9599 9600 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) 9601 { 9602 int retval; 9603 u32 reg; 9604 9605 retval = rt2800_probe_rt(rt2x00dev); 9606 if (retval) 9607 return retval; 9608 9609 /* 9610 * Allocate eeprom data. 9611 */ 9612 retval = rt2800_validate_eeprom(rt2x00dev); 9613 if (retval) 9614 return retval; 9615 9616 retval = rt2800_init_eeprom(rt2x00dev); 9617 if (retval) 9618 return retval; 9619 9620 /* 9621 * Enable rfkill polling by setting GPIO direction of the 9622 * rfkill switch GPIO pin correctly. 9623 */ 9624 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 9625 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); 9626 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 9627 9628 /* 9629 * Initialize hw specifications. 9630 */ 9631 retval = rt2800_probe_hw_mode(rt2x00dev); 9632 if (retval) 9633 return retval; 9634 9635 /* 9636 * Set device capabilities. 9637 */ 9638 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); 9639 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags); 9640 if (!rt2x00_is_usb(rt2x00dev)) 9641 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags); 9642 9643 /* 9644 * Set device requirements. 9645 */ 9646 if (!rt2x00_is_soc(rt2x00dev)) 9647 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); 9648 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags); 9649 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags); 9650 if (!rt2800_hwcrypt_disabled(rt2x00dev)) 9651 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); 9652 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 9653 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags); 9654 if (rt2x00_is_usb(rt2x00dev)) 9655 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); 9656 else { 9657 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); 9658 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags); 9659 } 9660 9661 /* 9662 * Set the rssi offset. 9663 */ 9664 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 9665 9666 return 0; 9667 } 9668 EXPORT_SYMBOL_GPL(rt2800_probe_hw); 9669 9670 /* 9671 * IEEE80211 stack callback functions. 9672 */ 9673 void rt2800_get_key_seq(struct ieee80211_hw *hw, 9674 struct ieee80211_key_conf *key, 9675 struct ieee80211_key_seq *seq) 9676 { 9677 struct rt2x00_dev *rt2x00dev = hw->priv; 9678 struct mac_iveiv_entry iveiv_entry; 9679 u32 offset; 9680 9681 if (key->cipher != WLAN_CIPHER_SUITE_TKIP) 9682 return; 9683 9684 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 9685 rt2800_register_multiread(rt2x00dev, offset, 9686 &iveiv_entry, sizeof(iveiv_entry)); 9687 9688 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2); 9689 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4); 9690 } 9691 EXPORT_SYMBOL_GPL(rt2800_get_key_seq); 9692 9693 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) 9694 { 9695 struct rt2x00_dev *rt2x00dev = hw->priv; 9696 u32 reg; 9697 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); 9698 9699 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 9700 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); 9701 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 9702 9703 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 9704 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); 9705 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 9706 9707 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 9708 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); 9709 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 9710 9711 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 9712 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); 9713 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 9714 9715 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 9716 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); 9717 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 9718 9719 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 9720 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); 9721 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 9722 9723 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 9724 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); 9725 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 9726 9727 return 0; 9728 } 9729 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold); 9730 9731 int rt2800_conf_tx(struct ieee80211_hw *hw, 9732 struct ieee80211_vif *vif, u16 queue_idx, 9733 const struct ieee80211_tx_queue_params *params) 9734 { 9735 struct rt2x00_dev *rt2x00dev = hw->priv; 9736 struct data_queue *queue; 9737 struct rt2x00_field32 field; 9738 int retval; 9739 u32 reg; 9740 u32 offset; 9741 9742 /* 9743 * First pass the configuration through rt2x00lib, that will 9744 * update the queue settings and validate the input. After that 9745 * we are free to update the registers based on the value 9746 * in the queue parameter. 9747 */ 9748 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params); 9749 if (retval) 9750 return retval; 9751 9752 /* 9753 * We only need to perform additional register initialization 9754 * for WMM queues/ 9755 */ 9756 if (queue_idx >= 4) 9757 return 0; 9758 9759 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 9760 9761 /* Update WMM TXOP register */ 9762 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); 9763 field.bit_offset = (queue_idx & 1) * 16; 9764 field.bit_mask = 0xffff << field.bit_offset; 9765 9766 reg = rt2800_register_read(rt2x00dev, offset); 9767 rt2x00_set_field32(®, field, queue->txop); 9768 rt2800_register_write(rt2x00dev, offset, reg); 9769 9770 /* Update WMM registers */ 9771 field.bit_offset = queue_idx * 4; 9772 field.bit_mask = 0xf << field.bit_offset; 9773 9774 reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG); 9775 rt2x00_set_field32(®, field, queue->aifs); 9776 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); 9777 9778 reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG); 9779 rt2x00_set_field32(®, field, queue->cw_min); 9780 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); 9781 9782 reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG); 9783 rt2x00_set_field32(®, field, queue->cw_max); 9784 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); 9785 9786 /* Update EDCA registers */ 9787 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); 9788 9789 reg = rt2800_register_read(rt2x00dev, offset); 9790 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); 9791 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); 9792 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); 9793 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); 9794 rt2800_register_write(rt2x00dev, offset, reg); 9795 9796 return 0; 9797 } 9798 EXPORT_SYMBOL_GPL(rt2800_conf_tx); 9799 9800 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 9801 { 9802 struct rt2x00_dev *rt2x00dev = hw->priv; 9803 u64 tsf; 9804 u32 reg; 9805 9806 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1); 9807 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; 9808 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0); 9809 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); 9810 9811 return tsf; 9812 } 9813 EXPORT_SYMBOL_GPL(rt2800_get_tsf); 9814 9815 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 9816 struct ieee80211_ampdu_params *params) 9817 { 9818 struct ieee80211_sta *sta = params->sta; 9819 enum ieee80211_ampdu_mlme_action action = params->action; 9820 u16 tid = params->tid; 9821 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv; 9822 int ret = 0; 9823 9824 /* 9825 * Don't allow aggregation for stations the hardware isn't aware 9826 * of because tx status reports for frames to an unknown station 9827 * always contain wcid=WCID_END+1 and thus we can't distinguish 9828 * between multiple stations which leads to unwanted situations 9829 * when the hw reorders frames due to aggregation. 9830 */ 9831 if (sta_priv->wcid > WCID_END) 9832 return 1; 9833 9834 switch (action) { 9835 case IEEE80211_AMPDU_RX_START: 9836 case IEEE80211_AMPDU_RX_STOP: 9837 /* 9838 * The hw itself takes care of setting up BlockAck mechanisms. 9839 * So, we only have to allow mac80211 to nagotiate a BlockAck 9840 * agreement. Once that is done, the hw will BlockAck incoming 9841 * AMPDUs without further setup. 9842 */ 9843 break; 9844 case IEEE80211_AMPDU_TX_START: 9845 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 9846 break; 9847 case IEEE80211_AMPDU_TX_STOP_CONT: 9848 case IEEE80211_AMPDU_TX_STOP_FLUSH: 9849 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 9850 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 9851 break; 9852 case IEEE80211_AMPDU_TX_OPERATIONAL: 9853 break; 9854 default: 9855 rt2x00_warn((struct rt2x00_dev *)hw->priv, 9856 "Unknown AMPDU action\n"); 9857 } 9858 9859 return ret; 9860 } 9861 EXPORT_SYMBOL_GPL(rt2800_ampdu_action); 9862 9863 int rt2800_get_survey(struct ieee80211_hw *hw, int idx, 9864 struct survey_info *survey) 9865 { 9866 struct rt2x00_dev *rt2x00dev = hw->priv; 9867 struct ieee80211_conf *conf = &hw->conf; 9868 u32 idle, busy, busy_ext; 9869 9870 if (idx != 0) 9871 return -ENOENT; 9872 9873 survey->channel = conf->chandef.chan; 9874 9875 idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 9876 busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 9877 busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 9878 9879 if (idle || busy) { 9880 survey->filled = SURVEY_INFO_TIME | 9881 SURVEY_INFO_TIME_BUSY | 9882 SURVEY_INFO_TIME_EXT_BUSY; 9883 9884 survey->time = (idle + busy) / 1000; 9885 survey->time_busy = busy / 1000; 9886 survey->time_ext_busy = busy_ext / 1000; 9887 } 9888 9889 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 9890 survey->filled |= SURVEY_INFO_IN_USE; 9891 9892 return 0; 9893 9894 } 9895 EXPORT_SYMBOL_GPL(rt2800_get_survey); 9896 9897 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); 9898 MODULE_VERSION(DRV_VERSION); 9899 MODULE_DESCRIPTION("Ralink RT2800 library"); 9900 MODULE_LICENSE("GPL"); 9901