1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 	Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
4 	Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
5 	Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
6 	Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 
8 	Based on the original rt2800pci.c and rt2800usb.c.
9 	  Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
10 	  Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
11 	  Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
12 	  Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
13 	  Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
14 	  Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
15 	  <http://rt2x00.serialmonkey.com>
16 
17  */
18 
19 /*
20 	Module: rt2800lib
21 	Abstract: rt2800 generic device routines.
22  */
23 
24 #include <linux/crc-ccitt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28 
29 #include "rt2x00.h"
30 #include "rt2800lib.h"
31 #include "rt2800.h"
32 
33 static bool modparam_watchdog;
34 module_param_named(watchdog, modparam_watchdog, bool, S_IRUGO);
35 MODULE_PARM_DESC(watchdog, "Enable watchdog to detect tx/rx hangs and reset hardware if detected");
36 
37 /*
38  * Register access.
39  * All access to the CSR registers will go through the methods
40  * rt2800_register_read and rt2800_register_write.
41  * BBP and RF register require indirect register access,
42  * and use the CSR registers BBPCSR and RFCSR to achieve this.
43  * These indirect registers work with busy bits,
44  * and we will try maximal REGISTER_BUSY_COUNT times to access
45  * the register while taking a REGISTER_BUSY_DELAY us delay
46  * between each attampt. When the busy bit is still set at that time,
47  * the access attempt is considered to have failed,
48  * and we will print an error.
49  * The _lock versions must be used if you already hold the csr_mutex
50  */
51 #define WAIT_FOR_BBP(__dev, __reg) \
52 	rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
53 #define WAIT_FOR_RFCSR(__dev, __reg) \
54 	rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
55 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
56 	rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
57 			    (__reg))
58 #define WAIT_FOR_RF(__dev, __reg) \
59 	rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
60 #define WAIT_FOR_MCU(__dev, __reg) \
61 	rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
62 			    H2M_MAILBOX_CSR_OWNER, (__reg))
63 
64 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
65 {
66 	/* check for rt2872 on SoC */
67 	if (!rt2x00_is_soc(rt2x00dev) ||
68 	    !rt2x00_rt(rt2x00dev, RT2872))
69 		return false;
70 
71 	/* we know for sure that these rf chipsets are used on rt305x boards */
72 	if (rt2x00_rf(rt2x00dev, RF3020) ||
73 	    rt2x00_rf(rt2x00dev, RF3021) ||
74 	    rt2x00_rf(rt2x00dev, RF3022))
75 		return true;
76 
77 	rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
78 	return false;
79 }
80 
81 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
82 			     const unsigned int word, const u8 value)
83 {
84 	u32 reg;
85 
86 	mutex_lock(&rt2x00dev->csr_mutex);
87 
88 	/*
89 	 * Wait until the BBP becomes available, afterwards we
90 	 * can safely write the new data into the register.
91 	 */
92 	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
93 		reg = 0;
94 		rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
95 		rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
96 		rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
97 		rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
98 		rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
99 
100 		rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
101 	}
102 
103 	mutex_unlock(&rt2x00dev->csr_mutex);
104 }
105 
106 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word)
107 {
108 	u32 reg;
109 	u8 value;
110 
111 	mutex_lock(&rt2x00dev->csr_mutex);
112 
113 	/*
114 	 * Wait until the BBP becomes available, afterwards we
115 	 * can safely write the read request into the register.
116 	 * After the data has been written, we wait until hardware
117 	 * returns the correct value, if at any time the register
118 	 * doesn't become available in time, reg will be 0xffffffff
119 	 * which means we return 0xff to the caller.
120 	 */
121 	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
122 		reg = 0;
123 		rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
124 		rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
125 		rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
126 		rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
127 
128 		rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
129 
130 		WAIT_FOR_BBP(rt2x00dev, &reg);
131 	}
132 
133 	value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
134 
135 	mutex_unlock(&rt2x00dev->csr_mutex);
136 
137 	return value;
138 }
139 
140 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
141 			       const unsigned int word, const u8 value)
142 {
143 	u32 reg;
144 
145 	mutex_lock(&rt2x00dev->csr_mutex);
146 
147 	/*
148 	 * Wait until the RFCSR becomes available, afterwards we
149 	 * can safely write the new data into the register.
150 	 */
151 	switch (rt2x00dev->chip.rt) {
152 	case RT6352:
153 		if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
154 			reg = 0;
155 			rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
156 			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
157 					   word);
158 			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
159 			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
160 
161 			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
162 		}
163 		break;
164 
165 	default:
166 		if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
167 			reg = 0;
168 			rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
169 			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
170 			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
171 			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
172 
173 			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
174 		}
175 		break;
176 	}
177 
178 	mutex_unlock(&rt2x00dev->csr_mutex);
179 }
180 
181 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
182 				    const unsigned int reg, const u8 value)
183 {
184 	rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
185 }
186 
187 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
188 				       const unsigned int reg, const u8 value)
189 {
190 	rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
191 	rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
192 }
193 
194 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
195 				     const unsigned int reg, const u8 value)
196 {
197 	rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
198 	rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
199 }
200 
201 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
202 				  const u8 reg, const u8 value)
203 {
204 	rt2800_bbp_write(rt2x00dev, 158, reg);
205 	rt2800_bbp_write(rt2x00dev, 159, value);
206 }
207 
208 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg)
209 {
210 	rt2800_bbp_write(rt2x00dev, 158, reg);
211 	return rt2800_bbp_read(rt2x00dev, 159);
212 }
213 
214 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
215 				  const u8 reg, const u8 value)
216 {
217 	rt2800_bbp_write(rt2x00dev, 195, reg);
218 	rt2800_bbp_write(rt2x00dev, 196, value);
219 }
220 
221 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
222 			    const unsigned int word)
223 {
224 	u32 reg;
225 	u8 value;
226 
227 	mutex_lock(&rt2x00dev->csr_mutex);
228 
229 	/*
230 	 * Wait until the RFCSR becomes available, afterwards we
231 	 * can safely write the read request into the register.
232 	 * After the data has been written, we wait until hardware
233 	 * returns the correct value, if at any time the register
234 	 * doesn't become available in time, reg will be 0xffffffff
235 	 * which means we return 0xff to the caller.
236 	 */
237 	switch (rt2x00dev->chip.rt) {
238 	case RT6352:
239 		if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
240 			reg = 0;
241 			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
242 					   word);
243 			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
244 			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
245 
246 			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
247 
248 			WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
249 		}
250 
251 		value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
252 		break;
253 
254 	default:
255 		if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
256 			reg = 0;
257 			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
258 			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
259 			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
260 
261 			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
262 
263 			WAIT_FOR_RFCSR(rt2x00dev, &reg);
264 		}
265 
266 		value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
267 		break;
268 	}
269 
270 	mutex_unlock(&rt2x00dev->csr_mutex);
271 
272 	return value;
273 }
274 
275 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
276 				 const unsigned int reg)
277 {
278 	return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)));
279 }
280 
281 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
282 			    const unsigned int word, const u32 value)
283 {
284 	u32 reg;
285 
286 	mutex_lock(&rt2x00dev->csr_mutex);
287 
288 	/*
289 	 * Wait until the RF becomes available, afterwards we
290 	 * can safely write the new data into the register.
291 	 */
292 	if (WAIT_FOR_RF(rt2x00dev, &reg)) {
293 		reg = 0;
294 		rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
295 		rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
296 		rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
297 		rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
298 
299 		rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
300 		rt2x00_rf_write(rt2x00dev, word, value);
301 	}
302 
303 	mutex_unlock(&rt2x00dev->csr_mutex);
304 }
305 
306 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
307 	[EEPROM_CHIP_ID]		= 0x0000,
308 	[EEPROM_VERSION]		= 0x0001,
309 	[EEPROM_MAC_ADDR_0]		= 0x0002,
310 	[EEPROM_MAC_ADDR_1]		= 0x0003,
311 	[EEPROM_MAC_ADDR_2]		= 0x0004,
312 	[EEPROM_NIC_CONF0]		= 0x001a,
313 	[EEPROM_NIC_CONF1]		= 0x001b,
314 	[EEPROM_FREQ]			= 0x001d,
315 	[EEPROM_LED_AG_CONF]		= 0x001e,
316 	[EEPROM_LED_ACT_CONF]		= 0x001f,
317 	[EEPROM_LED_POLARITY]		= 0x0020,
318 	[EEPROM_NIC_CONF2]		= 0x0021,
319 	[EEPROM_LNA]			= 0x0022,
320 	[EEPROM_RSSI_BG]		= 0x0023,
321 	[EEPROM_RSSI_BG2]		= 0x0024,
322 	[EEPROM_TXMIXER_GAIN_BG]	= 0x0024, /* overlaps with RSSI_BG2 */
323 	[EEPROM_RSSI_A]			= 0x0025,
324 	[EEPROM_RSSI_A2]		= 0x0026,
325 	[EEPROM_TXMIXER_GAIN_A]		= 0x0026, /* overlaps with RSSI_A2 */
326 	[EEPROM_EIRP_MAX_TX_POWER]	= 0x0027,
327 	[EEPROM_TXPOWER_DELTA]		= 0x0028,
328 	[EEPROM_TXPOWER_BG1]		= 0x0029,
329 	[EEPROM_TXPOWER_BG2]		= 0x0030,
330 	[EEPROM_TSSI_BOUND_BG1]		= 0x0037,
331 	[EEPROM_TSSI_BOUND_BG2]		= 0x0038,
332 	[EEPROM_TSSI_BOUND_BG3]		= 0x0039,
333 	[EEPROM_TSSI_BOUND_BG4]		= 0x003a,
334 	[EEPROM_TSSI_BOUND_BG5]		= 0x003b,
335 	[EEPROM_TXPOWER_A1]		= 0x003c,
336 	[EEPROM_TXPOWER_A2]		= 0x0053,
337 	[EEPROM_TXPOWER_INIT]		= 0x0068,
338 	[EEPROM_TSSI_BOUND_A1]		= 0x006a,
339 	[EEPROM_TSSI_BOUND_A2]		= 0x006b,
340 	[EEPROM_TSSI_BOUND_A3]		= 0x006c,
341 	[EEPROM_TSSI_BOUND_A4]		= 0x006d,
342 	[EEPROM_TSSI_BOUND_A5]		= 0x006e,
343 	[EEPROM_TXPOWER_BYRATE]		= 0x006f,
344 	[EEPROM_BBP_START]		= 0x0078,
345 };
346 
347 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
348 	[EEPROM_CHIP_ID]		= 0x0000,
349 	[EEPROM_VERSION]		= 0x0001,
350 	[EEPROM_MAC_ADDR_0]		= 0x0002,
351 	[EEPROM_MAC_ADDR_1]		= 0x0003,
352 	[EEPROM_MAC_ADDR_2]		= 0x0004,
353 	[EEPROM_NIC_CONF0]		= 0x001a,
354 	[EEPROM_NIC_CONF1]		= 0x001b,
355 	[EEPROM_NIC_CONF2]		= 0x001c,
356 	[EEPROM_EIRP_MAX_TX_POWER]	= 0x0020,
357 	[EEPROM_FREQ]			= 0x0022,
358 	[EEPROM_LED_AG_CONF]		= 0x0023,
359 	[EEPROM_LED_ACT_CONF]		= 0x0024,
360 	[EEPROM_LED_POLARITY]		= 0x0025,
361 	[EEPROM_LNA]			= 0x0026,
362 	[EEPROM_EXT_LNA2]		= 0x0027,
363 	[EEPROM_RSSI_BG]		= 0x0028,
364 	[EEPROM_RSSI_BG2]		= 0x0029,
365 	[EEPROM_RSSI_A]			= 0x002a,
366 	[EEPROM_RSSI_A2]		= 0x002b,
367 	[EEPROM_TXPOWER_BG1]		= 0x0030,
368 	[EEPROM_TXPOWER_BG2]		= 0x0037,
369 	[EEPROM_EXT_TXPOWER_BG3]	= 0x003e,
370 	[EEPROM_TSSI_BOUND_BG1]		= 0x0045,
371 	[EEPROM_TSSI_BOUND_BG2]		= 0x0046,
372 	[EEPROM_TSSI_BOUND_BG3]		= 0x0047,
373 	[EEPROM_TSSI_BOUND_BG4]		= 0x0048,
374 	[EEPROM_TSSI_BOUND_BG5]		= 0x0049,
375 	[EEPROM_TXPOWER_A1]		= 0x004b,
376 	[EEPROM_TXPOWER_A2]		= 0x0065,
377 	[EEPROM_EXT_TXPOWER_A3]		= 0x007f,
378 	[EEPROM_TSSI_BOUND_A1]		= 0x009a,
379 	[EEPROM_TSSI_BOUND_A2]		= 0x009b,
380 	[EEPROM_TSSI_BOUND_A3]		= 0x009c,
381 	[EEPROM_TSSI_BOUND_A4]		= 0x009d,
382 	[EEPROM_TSSI_BOUND_A5]		= 0x009e,
383 	[EEPROM_TXPOWER_BYRATE]		= 0x00a0,
384 };
385 
386 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
387 					     const enum rt2800_eeprom_word word)
388 {
389 	const unsigned int *map;
390 	unsigned int index;
391 
392 	if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
393 		      "%s: invalid EEPROM word %d\n",
394 		      wiphy_name(rt2x00dev->hw->wiphy), word))
395 		return 0;
396 
397 	if (rt2x00_rt(rt2x00dev, RT3593) ||
398 	    rt2x00_rt(rt2x00dev, RT3883))
399 		map = rt2800_eeprom_map_ext;
400 	else
401 		map = rt2800_eeprom_map;
402 
403 	index = map[word];
404 
405 	/* Index 0 is valid only for EEPROM_CHIP_ID.
406 	 * Otherwise it means that the offset of the
407 	 * given word is not initialized in the map,
408 	 * or that the field is not usable on the
409 	 * actual chipset.
410 	 */
411 	WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
412 		  "%s: invalid access of EEPROM word %d\n",
413 		  wiphy_name(rt2x00dev->hw->wiphy), word);
414 
415 	return index;
416 }
417 
418 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
419 				const enum rt2800_eeprom_word word)
420 {
421 	unsigned int index;
422 
423 	index = rt2800_eeprom_word_index(rt2x00dev, word);
424 	return rt2x00_eeprom_addr(rt2x00dev, index);
425 }
426 
427 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
428 			      const enum rt2800_eeprom_word word)
429 {
430 	unsigned int index;
431 
432 	index = rt2800_eeprom_word_index(rt2x00dev, word);
433 	return rt2x00_eeprom_read(rt2x00dev, index);
434 }
435 
436 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
437 				const enum rt2800_eeprom_word word, u16 data)
438 {
439 	unsigned int index;
440 
441 	index = rt2800_eeprom_word_index(rt2x00dev, word);
442 	rt2x00_eeprom_write(rt2x00dev, index, data);
443 }
444 
445 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
446 					 const enum rt2800_eeprom_word array,
447 					 unsigned int offset)
448 {
449 	unsigned int index;
450 
451 	index = rt2800_eeprom_word_index(rt2x00dev, array);
452 	return rt2x00_eeprom_read(rt2x00dev, index + offset);
453 }
454 
455 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
456 {
457 	u32 reg;
458 	int i, count;
459 
460 	reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
461 	rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
462 	rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
463 	rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
464 	rt2x00_set_field32(&reg, WLAN_EN, 1);
465 	rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
466 
467 	udelay(REGISTER_BUSY_DELAY);
468 
469 	count = 0;
470 	do {
471 		/*
472 		 * Check PLL_LD & XTAL_RDY.
473 		 */
474 		for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
475 			reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
476 			if (rt2x00_get_field32(reg, PLL_LD) &&
477 			    rt2x00_get_field32(reg, XTAL_RDY))
478 				break;
479 			udelay(REGISTER_BUSY_DELAY);
480 		}
481 
482 		if (i >= REGISTER_BUSY_COUNT) {
483 
484 			if (count >= 10)
485 				return -EIO;
486 
487 			rt2800_register_write(rt2x00dev, 0x58, 0x018);
488 			udelay(REGISTER_BUSY_DELAY);
489 			rt2800_register_write(rt2x00dev, 0x58, 0x418);
490 			udelay(REGISTER_BUSY_DELAY);
491 			rt2800_register_write(rt2x00dev, 0x58, 0x618);
492 			udelay(REGISTER_BUSY_DELAY);
493 			count++;
494 		} else {
495 			count = 0;
496 		}
497 
498 		reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
499 		rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
500 		rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
501 		rt2x00_set_field32(&reg, WLAN_RESET, 1);
502 		rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
503 		udelay(10);
504 		rt2x00_set_field32(&reg, WLAN_RESET, 0);
505 		rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
506 		udelay(10);
507 		rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
508 	} while (count != 0);
509 
510 	return 0;
511 }
512 
513 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
514 			const u8 command, const u8 token,
515 			const u8 arg0, const u8 arg1)
516 {
517 	u32 reg;
518 
519 	/*
520 	 * SOC devices don't support MCU requests.
521 	 */
522 	if (rt2x00_is_soc(rt2x00dev))
523 		return;
524 
525 	mutex_lock(&rt2x00dev->csr_mutex);
526 
527 	/*
528 	 * Wait until the MCU becomes available, afterwards we
529 	 * can safely write the new data into the register.
530 	 */
531 	if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
532 		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
533 		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
534 		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
535 		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
536 		rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
537 
538 		reg = 0;
539 		rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
540 		rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
541 	}
542 
543 	mutex_unlock(&rt2x00dev->csr_mutex);
544 }
545 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
546 
547 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
548 {
549 	unsigned int i = 0;
550 	u32 reg;
551 
552 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
553 		reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
554 		if (reg && reg != ~0)
555 			return 0;
556 		msleep(1);
557 	}
558 
559 	rt2x00_err(rt2x00dev, "Unstable hardware\n");
560 	return -EBUSY;
561 }
562 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
563 
564 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
565 {
566 	unsigned int i;
567 	u32 reg;
568 
569 	/*
570 	 * Some devices are really slow to respond here. Wait a whole second
571 	 * before timing out.
572 	 */
573 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
574 		reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
575 		if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
576 		    !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
577 			return 0;
578 
579 		msleep(10);
580 	}
581 
582 	rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
583 	return -EACCES;
584 }
585 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
586 
587 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
588 {
589 	u32 reg;
590 
591 	reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
592 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
593 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
594 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
595 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
596 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
597 	rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
598 }
599 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
600 
601 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
602 			       unsigned short *txwi_size,
603 			       unsigned short *rxwi_size)
604 {
605 	switch (rt2x00dev->chip.rt) {
606 	case RT3593:
607 	case RT3883:
608 		*txwi_size = TXWI_DESC_SIZE_4WORDS;
609 		*rxwi_size = RXWI_DESC_SIZE_5WORDS;
610 		break;
611 
612 	case RT5592:
613 	case RT6352:
614 		*txwi_size = TXWI_DESC_SIZE_5WORDS;
615 		*rxwi_size = RXWI_DESC_SIZE_6WORDS;
616 		break;
617 
618 	default:
619 		*txwi_size = TXWI_DESC_SIZE_4WORDS;
620 		*rxwi_size = RXWI_DESC_SIZE_4WORDS;
621 		break;
622 	}
623 }
624 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
625 
626 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
627 {
628 	u16 fw_crc;
629 	u16 crc;
630 
631 	/*
632 	 * The last 2 bytes in the firmware array are the crc checksum itself,
633 	 * this means that we should never pass those 2 bytes to the crc
634 	 * algorithm.
635 	 */
636 	fw_crc = (data[len - 2] << 8 | data[len - 1]);
637 
638 	/*
639 	 * Use the crc ccitt algorithm.
640 	 * This will return the same value as the legacy driver which
641 	 * used bit ordering reversion on the both the firmware bytes
642 	 * before input input as well as on the final output.
643 	 * Obviously using crc ccitt directly is much more efficient.
644 	 */
645 	crc = crc_ccitt(~0, data, len - 2);
646 
647 	/*
648 	 * There is a small difference between the crc-itu-t + bitrev and
649 	 * the crc-ccitt crc calculation. In the latter method the 2 bytes
650 	 * will be swapped, use swab16 to convert the crc to the correct
651 	 * value.
652 	 */
653 	crc = swab16(crc);
654 
655 	return fw_crc == crc;
656 }
657 
658 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
659 			  const u8 *data, const size_t len)
660 {
661 	size_t offset = 0;
662 	size_t fw_len;
663 	bool multiple;
664 
665 	/*
666 	 * PCI(e) & SOC devices require firmware with a length
667 	 * of 8kb. USB devices require firmware files with a length
668 	 * of 4kb. Certain USB chipsets however require different firmware,
669 	 * which Ralink only provides attached to the original firmware
670 	 * file. Thus for USB devices, firmware files have a length
671 	 * which is a multiple of 4kb. The firmware for rt3290 chip also
672 	 * have a length which is a multiple of 4kb.
673 	 */
674 	if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
675 		fw_len = 4096;
676 	else
677 		fw_len = 8192;
678 
679 	multiple = true;
680 	/*
681 	 * Validate the firmware length
682 	 */
683 	if (len != fw_len && (!multiple || (len % fw_len) != 0))
684 		return FW_BAD_LENGTH;
685 
686 	/*
687 	 * Check if the chipset requires one of the upper parts
688 	 * of the firmware.
689 	 */
690 	if (rt2x00_is_usb(rt2x00dev) &&
691 	    !rt2x00_rt(rt2x00dev, RT2860) &&
692 	    !rt2x00_rt(rt2x00dev, RT2872) &&
693 	    !rt2x00_rt(rt2x00dev, RT3070) &&
694 	    ((len / fw_len) == 1))
695 		return FW_BAD_VERSION;
696 
697 	/*
698 	 * 8kb firmware files must be checked as if it were
699 	 * 2 separate firmware files.
700 	 */
701 	while (offset < len) {
702 		if (!rt2800_check_firmware_crc(data + offset, fw_len))
703 			return FW_BAD_CRC;
704 
705 		offset += fw_len;
706 	}
707 
708 	return FW_OK;
709 }
710 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
711 
712 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
713 			 const u8 *data, const size_t len)
714 {
715 	unsigned int i;
716 	u32 reg;
717 	int retval;
718 
719 	if (rt2x00_rt(rt2x00dev, RT3290)) {
720 		retval = rt2800_enable_wlan_rt3290(rt2x00dev);
721 		if (retval)
722 			return -EBUSY;
723 	}
724 
725 	/*
726 	 * If driver doesn't wake up firmware here,
727 	 * rt2800_load_firmware will hang forever when interface is up again.
728 	 */
729 	rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
730 
731 	/*
732 	 * Wait for stable hardware.
733 	 */
734 	if (rt2800_wait_csr_ready(rt2x00dev))
735 		return -EBUSY;
736 
737 	if (rt2x00_is_pci(rt2x00dev)) {
738 		if (rt2x00_rt(rt2x00dev, RT3290) ||
739 		    rt2x00_rt(rt2x00dev, RT3572) ||
740 		    rt2x00_rt(rt2x00dev, RT5390) ||
741 		    rt2x00_rt(rt2x00dev, RT5392)) {
742 			reg = rt2800_register_read(rt2x00dev, AUX_CTRL);
743 			rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
744 			rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
745 			rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
746 		}
747 		rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
748 	}
749 
750 	rt2800_disable_wpdma(rt2x00dev);
751 
752 	/*
753 	 * Write firmware to the device.
754 	 */
755 	rt2800_drv_write_firmware(rt2x00dev, data, len);
756 
757 	/*
758 	 * Wait for device to stabilize.
759 	 */
760 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
761 		reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL);
762 		if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
763 			break;
764 		msleep(1);
765 	}
766 
767 	if (i == REGISTER_BUSY_COUNT) {
768 		rt2x00_err(rt2x00dev, "PBF system register not ready\n");
769 		return -EBUSY;
770 	}
771 
772 	/*
773 	 * Disable DMA, will be reenabled later when enabling
774 	 * the radio.
775 	 */
776 	rt2800_disable_wpdma(rt2x00dev);
777 
778 	/*
779 	 * Initialize firmware.
780 	 */
781 	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
782 	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
783 	if (rt2x00_is_usb(rt2x00dev)) {
784 		rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
785 		rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
786 	}
787 	msleep(1);
788 
789 	return 0;
790 }
791 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
792 
793 void rt2800_write_tx_data(struct queue_entry *entry,
794 			  struct txentry_desc *txdesc)
795 {
796 	__le32 *txwi = rt2800_drv_get_txwi(entry);
797 	u32 word;
798 	int i;
799 
800 	/*
801 	 * Initialize TX Info descriptor
802 	 */
803 	word = rt2x00_desc_read(txwi, 0);
804 	rt2x00_set_field32(&word, TXWI_W0_FRAG,
805 			   test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
806 	rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
807 			   test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
808 	rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
809 	rt2x00_set_field32(&word, TXWI_W0_TS,
810 			   test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
811 	rt2x00_set_field32(&word, TXWI_W0_AMPDU,
812 			   test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
813 	rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
814 			   txdesc->u.ht.mpdu_density);
815 	rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
816 	rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
817 	rt2x00_set_field32(&word, TXWI_W0_BW,
818 			   test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
819 	rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
820 			   test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
821 	rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
822 	rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
823 	rt2x00_desc_write(txwi, 0, word);
824 
825 	word = rt2x00_desc_read(txwi, 1);
826 	rt2x00_set_field32(&word, TXWI_W1_ACK,
827 			   test_bit(ENTRY_TXD_ACK, &txdesc->flags));
828 	rt2x00_set_field32(&word, TXWI_W1_NSEQ,
829 			   test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
830 	rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
831 	rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
832 			   test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
833 			   txdesc->key_idx : txdesc->u.ht.wcid);
834 	rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
835 			   txdesc->length);
836 	rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
837 	rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
838 	rt2x00_desc_write(txwi, 1, word);
839 
840 	/*
841 	 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
842 	 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
843 	 * When TXD_W3_WIV is set to 1 it will use the IV data
844 	 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
845 	 * crypto entry in the registers should be used to encrypt the frame.
846 	 *
847 	 * Nulify all remaining words as well, we don't know how to program them.
848 	 */
849 	for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
850 		_rt2x00_desc_write(txwi, i, 0);
851 }
852 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
853 
854 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
855 {
856 	s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
857 	s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
858 	s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
859 	u16 eeprom;
860 	u8 offset0;
861 	u8 offset1;
862 	u8 offset2;
863 
864 	if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
865 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
866 		offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
867 		offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
868 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
869 		offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
870 	} else {
871 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
872 		offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
873 		offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
874 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
875 		offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
876 	}
877 
878 	/*
879 	 * Convert the value from the descriptor into the RSSI value
880 	 * If the value in the descriptor is 0, it is considered invalid
881 	 * and the default (extremely low) rssi value is assumed
882 	 */
883 	rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
884 	rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
885 	rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
886 
887 	/*
888 	 * mac80211 only accepts a single RSSI value. Calculating the
889 	 * average doesn't deliver a fair answer either since -60:-60 would
890 	 * be considered equally good as -50:-70 while the second is the one
891 	 * which gives less energy...
892 	 */
893 	rssi0 = max(rssi0, rssi1);
894 	return (int)max(rssi0, rssi2);
895 }
896 
897 void rt2800_process_rxwi(struct queue_entry *entry,
898 			 struct rxdone_entry_desc *rxdesc)
899 {
900 	__le32 *rxwi = (__le32 *) entry->skb->data;
901 	u32 word;
902 
903 	word = rt2x00_desc_read(rxwi, 0);
904 
905 	rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
906 	rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
907 
908 	word = rt2x00_desc_read(rxwi, 1);
909 
910 	if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
911 		rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI;
912 
913 	if (rt2x00_get_field32(word, RXWI_W1_BW))
914 		rxdesc->bw = RATE_INFO_BW_40;
915 
916 	/*
917 	 * Detect RX rate, always use MCS as signal type.
918 	 */
919 	rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
920 	rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
921 	rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
922 
923 	/*
924 	 * Mask of 0x8 bit to remove the short preamble flag.
925 	 */
926 	if (rxdesc->rate_mode == RATE_MODE_CCK)
927 		rxdesc->signal &= ~0x8;
928 
929 	word = rt2x00_desc_read(rxwi, 2);
930 
931 	/*
932 	 * Convert descriptor AGC value to RSSI value.
933 	 */
934 	rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
935 	/*
936 	 * Remove RXWI descriptor from start of the buffer.
937 	 */
938 	skb_pull(entry->skb, entry->queue->winfo_size);
939 }
940 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
941 
942 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc,
943 				    u32 status, enum nl80211_band band)
944 {
945 	u8 flags = 0;
946 	u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
947 
948 	switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) {
949 	case RATE_MODE_HT_GREENFIELD:
950 		flags |= IEEE80211_TX_RC_GREEN_FIELD;
951 		fallthrough;
952 	case RATE_MODE_HT_MIX:
953 		flags |= IEEE80211_TX_RC_MCS;
954 		break;
955 	case RATE_MODE_OFDM:
956 		if (band == NL80211_BAND_2GHZ)
957 			idx += 4;
958 		break;
959 	case RATE_MODE_CCK:
960 		if (idx >= 8)
961 			idx -= 8;
962 		break;
963 	}
964 
965 	if (rt2x00_get_field32(status, TX_STA_FIFO_BW))
966 		flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
967 
968 	if (rt2x00_get_field32(status, TX_STA_FIFO_SGI))
969 		flags |= IEEE80211_TX_RC_SHORT_GI;
970 
971 	skbdesc->tx_rate_idx = idx;
972 	skbdesc->tx_rate_flags = flags;
973 }
974 
975 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
976 {
977 	__le32 *txwi;
978 	u32 word;
979 	int wcid, ack, pid;
980 	int tx_wcid, tx_ack, tx_pid, is_agg;
981 
982 	/*
983 	 * This frames has returned with an IO error,
984 	 * so the status report is not intended for this
985 	 * frame.
986 	 */
987 	if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags))
988 		return false;
989 
990 	wcid	= rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
991 	ack	= rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
992 	pid	= rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
993 	is_agg	= rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE);
994 
995 	/*
996 	 * Validate if this TX status report is intended for
997 	 * this entry by comparing the WCID/ACK/PID fields.
998 	 */
999 	txwi = rt2800_drv_get_txwi(entry);
1000 
1001 	word = rt2x00_desc_read(txwi, 1);
1002 	tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
1003 	tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
1004 	tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
1005 
1006 	if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) {
1007 		rt2x00_dbg(entry->queue->rt2x00dev,
1008 			   "TX status report missed for queue %d entry %d\n",
1009 			   entry->queue->qid, entry->entry_idx);
1010 		return false;
1011 	}
1012 
1013 	return true;
1014 }
1015 
1016 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi,
1017 			 bool match)
1018 {
1019 	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1020 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1021 	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1022 	struct txdone_entry_desc txdesc;
1023 	u32 word;
1024 	u16 mcs, real_mcs;
1025 	int aggr, ampdu, wcid, ack_req;
1026 
1027 	/*
1028 	 * Obtain the status about this packet.
1029 	 */
1030 	txdesc.flags = 0;
1031 	word = rt2x00_desc_read(txwi, 0);
1032 
1033 	mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1034 	ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
1035 
1036 	real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
1037 	aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
1038 	wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
1039 	ack_req	= rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED);
1040 
1041 	/*
1042 	 * If a frame was meant to be sent as a single non-aggregated MPDU
1043 	 * but ended up in an aggregate the used tx rate doesn't correlate
1044 	 * with the one specified in the TXWI as the whole aggregate is sent
1045 	 * with the same rate.
1046 	 *
1047 	 * For example: two frames are sent to rt2x00, the first one sets
1048 	 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
1049 	 * and requests MCS15. If the hw aggregates both frames into one
1050 	 * AMDPU the tx status for both frames will contain MCS7 although
1051 	 * the frame was sent successfully.
1052 	 *
1053 	 * Hence, replace the requested rate with the real tx rate to not
1054 	 * confuse the rate control algortihm by providing clearly wrong
1055 	 * data.
1056 	 *
1057 	 * FIXME: if we do not find matching entry, we tell that frame was
1058 	 * posted without any retries. We need to find a way to fix that
1059 	 * and provide retry count.
1060 	 */
1061 	if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) {
1062 		rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
1063 		mcs = real_mcs;
1064 	}
1065 
1066 	if (aggr == 1 || ampdu == 1)
1067 		__set_bit(TXDONE_AMPDU, &txdesc.flags);
1068 
1069 	if (!ack_req)
1070 		__set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags);
1071 
1072 	/*
1073 	 * Ralink has a retry mechanism using a global fallback
1074 	 * table. We setup this fallback table to try the immediate
1075 	 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
1076 	 * always contains the MCS used for the last transmission, be
1077 	 * it successful or not.
1078 	 */
1079 	if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
1080 		/*
1081 		 * Transmission succeeded. The number of retries is
1082 		 * mcs - real_mcs
1083 		 */
1084 		__set_bit(TXDONE_SUCCESS, &txdesc.flags);
1085 		txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
1086 	} else {
1087 		/*
1088 		 * Transmission failed. The number of retries is
1089 		 * always 7 in this case (for a total number of 8
1090 		 * frames sent).
1091 		 */
1092 		__set_bit(TXDONE_FAILURE, &txdesc.flags);
1093 		txdesc.retry = rt2x00dev->long_retry;
1094 	}
1095 
1096 	/*
1097 	 * the frame was retried at least once
1098 	 * -> hw used fallback rates
1099 	 */
1100 	if (txdesc.retry)
1101 		__set_bit(TXDONE_FALLBACK, &txdesc.flags);
1102 
1103 	if (!match) {
1104 		/* RCU assures non-null sta will not be freed by mac80211. */
1105 		rcu_read_lock();
1106 		if (likely(wcid >= WCID_START && wcid <= WCID_END))
1107 			skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START];
1108 		else
1109 			skbdesc->sta = NULL;
1110 		rt2x00lib_txdone_nomatch(entry, &txdesc);
1111 		rcu_read_unlock();
1112 	} else {
1113 		rt2x00lib_txdone(entry, &txdesc);
1114 	}
1115 }
1116 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
1117 
1118 void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota)
1119 {
1120 	struct data_queue *queue;
1121 	struct queue_entry *entry;
1122 	u32 reg;
1123 	u8 qid;
1124 	bool match;
1125 
1126 	while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, &reg)) {
1127 		/*
1128 		 * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is
1129 		 * guaranteed to be one of the TX QIDs .
1130 		 */
1131 		qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
1132 		queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
1133 
1134 		if (unlikely(rt2x00queue_empty(queue))) {
1135 			rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
1136 				   qid);
1137 			break;
1138 		}
1139 
1140 		entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1141 
1142 		if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1143 			     !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) {
1144 			rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n",
1145 				    entry->entry_idx, qid);
1146 			break;
1147 		}
1148 
1149 		match = rt2800_txdone_entry_check(entry, reg);
1150 		rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match);
1151 	}
1152 }
1153 EXPORT_SYMBOL_GPL(rt2800_txdone);
1154 
1155 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev,
1156 						 struct queue_entry *entry)
1157 {
1158 	bool ret;
1159 	unsigned long tout;
1160 
1161 	if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1162 		return false;
1163 
1164 	if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags))
1165 		tout = msecs_to_jiffies(50);
1166 	else
1167 		tout = msecs_to_jiffies(2000);
1168 
1169 	ret = time_after(jiffies, entry->last_action + tout);
1170 	if (unlikely(ret))
1171 		rt2x00_dbg(entry->queue->rt2x00dev,
1172 			   "TX status timeout for entry %d in queue %d\n",
1173 			   entry->entry_idx, entry->queue->qid);
1174 	return ret;
1175 }
1176 
1177 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev)
1178 {
1179 	struct data_queue *queue;
1180 	struct queue_entry *entry;
1181 
1182 	tx_queue_for_each(rt2x00dev, queue) {
1183 		entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1184 		if (rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1185 			return true;
1186 	}
1187 
1188 	return false;
1189 }
1190 EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout);
1191 
1192 /*
1193  * test if there is an entry in any TX queue for which DMA is done
1194  * but the TX status has not been returned yet
1195  */
1196 bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev)
1197 {
1198 	struct data_queue *queue;
1199 
1200 	tx_queue_for_each(rt2x00dev, queue) {
1201 		if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) !=
1202 		    rt2x00queue_get_entry(queue, Q_INDEX_DONE))
1203 			return true;
1204 	}
1205 	return false;
1206 }
1207 EXPORT_SYMBOL_GPL(rt2800_txstatus_pending);
1208 
1209 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev)
1210 {
1211 	struct data_queue *queue;
1212 	struct queue_entry *entry;
1213 
1214 	/*
1215 	 * Process any trailing TX status reports for IO failures,
1216 	 * we loop until we find the first non-IO error entry. This
1217 	 * can either be a frame which is free, is being uploaded,
1218 	 * or has completed the upload but didn't have an entry
1219 	 * in the TX_STAT_FIFO register yet.
1220 	 */
1221 	tx_queue_for_each(rt2x00dev, queue) {
1222 		while (!rt2x00queue_empty(queue)) {
1223 			entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1224 
1225 			if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1226 			    !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1227 				break;
1228 
1229 			if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) ||
1230 			    rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1231 				rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
1232 			else
1233 				break;
1234 		}
1235 	}
1236 }
1237 EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus);
1238 
1239 static int rt2800_check_hung(struct data_queue *queue)
1240 {
1241 	unsigned int cur_idx = rt2800_drv_get_dma_done(queue);
1242 
1243 	if (queue->wd_idx != cur_idx)
1244 		queue->wd_count = 0;
1245 	else
1246 		queue->wd_count++;
1247 
1248 	return queue->wd_count > 16;
1249 }
1250 
1251 static void rt2800_update_survey(struct rt2x00_dev *rt2x00dev)
1252 {
1253 	struct ieee80211_channel *chan = rt2x00dev->hw->conf.chandef.chan;
1254 	struct rt2x00_chan_survey *chan_survey =
1255 		   &rt2x00dev->chan_survey[chan->hw_value];
1256 
1257 	chan_survey->time_idle += rt2800_register_read(rt2x00dev, CH_IDLE_STA);
1258 	chan_survey->time_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA);
1259 	chan_survey->time_ext_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
1260 }
1261 
1262 void rt2800_watchdog(struct rt2x00_dev *rt2x00dev)
1263 {
1264 	struct data_queue *queue;
1265 	bool hung_tx = false;
1266 	bool hung_rx = false;
1267 
1268 	if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags))
1269 		return;
1270 
1271 	rt2800_update_survey(rt2x00dev);
1272 
1273 	queue_for_each(rt2x00dev, queue) {
1274 		switch (queue->qid) {
1275 		case QID_AC_VO:
1276 		case QID_AC_VI:
1277 		case QID_AC_BE:
1278 		case QID_AC_BK:
1279 		case QID_MGMT:
1280 			if (rt2x00queue_empty(queue))
1281 				continue;
1282 			hung_tx = rt2800_check_hung(queue);
1283 			break;
1284 		case QID_RX:
1285 			/* For station mode we should reactive at least
1286 			 * beacons. TODO: need to find good way detect
1287 			 * RX hung for AP mode.
1288 			 */
1289 			if (rt2x00dev->intf_sta_count == 0)
1290 				continue;
1291 			hung_rx = rt2800_check_hung(queue);
1292 			break;
1293 		default:
1294 			break;
1295 		}
1296 	}
1297 
1298 	if (hung_tx)
1299 		rt2x00_warn(rt2x00dev, "Watchdog TX hung detected\n");
1300 
1301 	if (hung_rx)
1302 		rt2x00_warn(rt2x00dev, "Watchdog RX hung detected\n");
1303 
1304 	if (hung_tx || hung_rx)
1305 		ieee80211_restart_hw(rt2x00dev->hw);
1306 }
1307 EXPORT_SYMBOL_GPL(rt2800_watchdog);
1308 
1309 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
1310 					  unsigned int index)
1311 {
1312 	return HW_BEACON_BASE(index);
1313 }
1314 
1315 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
1316 					  unsigned int index)
1317 {
1318 	return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
1319 }
1320 
1321 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
1322 {
1323 	struct data_queue *queue = rt2x00dev->bcn;
1324 	struct queue_entry *entry;
1325 	int i, bcn_num = 0;
1326 	u64 off, reg = 0;
1327 	u32 bssid_dw1;
1328 
1329 	/*
1330 	 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
1331 	 */
1332 	for (i = 0; i < queue->limit; i++) {
1333 		entry = &queue->entries[i];
1334 		if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
1335 			continue;
1336 		off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
1337 		reg |= off << (8 * bcn_num);
1338 		bcn_num++;
1339 	}
1340 
1341 	rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
1342 	rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
1343 
1344 	/*
1345 	 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
1346 	 */
1347 	bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1);
1348 	rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
1349 			   bcn_num > 0 ? bcn_num - 1 : 0);
1350 	rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
1351 }
1352 
1353 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
1354 {
1355 	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1356 	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1357 	unsigned int beacon_base;
1358 	unsigned int padding_len;
1359 	u32 orig_reg, reg;
1360 	const int txwi_desc_size = entry->queue->winfo_size;
1361 
1362 	/*
1363 	 * Disable beaconing while we are reloading the beacon data,
1364 	 * otherwise we might be sending out invalid data.
1365 	 */
1366 	reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1367 	orig_reg = reg;
1368 	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1369 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1370 
1371 	/*
1372 	 * Add space for the TXWI in front of the skb.
1373 	 */
1374 	memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
1375 
1376 	/*
1377 	 * Register descriptor details in skb frame descriptor.
1378 	 */
1379 	skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1380 	skbdesc->desc = entry->skb->data;
1381 	skbdesc->desc_len = txwi_desc_size;
1382 
1383 	/*
1384 	 * Add the TXWI for the beacon to the skb.
1385 	 */
1386 	rt2800_write_tx_data(entry, txdesc);
1387 
1388 	/*
1389 	 * Dump beacon to userspace through debugfs.
1390 	 */
1391 	rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1392 
1393 	/*
1394 	 * Write entire beacon with TXWI and padding to register.
1395 	 */
1396 	padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1397 	if (padding_len && skb_pad(entry->skb, padding_len)) {
1398 		rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1399 		/* skb freed by skb_pad() on failure */
1400 		entry->skb = NULL;
1401 		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1402 		return;
1403 	}
1404 
1405 	beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1406 
1407 	rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1408 				   entry->skb->len + padding_len);
1409 	__set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1410 
1411 	/*
1412 	 * Change global beacons settings.
1413 	 */
1414 	rt2800_update_beacons_setup(rt2x00dev);
1415 
1416 	/*
1417 	 * Restore beaconing state.
1418 	 */
1419 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1420 
1421 	/*
1422 	 * Clean up beacon skb.
1423 	 */
1424 	dev_kfree_skb_any(entry->skb);
1425 	entry->skb = NULL;
1426 }
1427 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1428 
1429 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1430 						unsigned int index)
1431 {
1432 	int i;
1433 	const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1434 	unsigned int beacon_base;
1435 
1436 	beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1437 
1438 	/*
1439 	 * For the Beacon base registers we only need to clear
1440 	 * the whole TXWI which (when set to 0) will invalidate
1441 	 * the entire beacon.
1442 	 */
1443 	for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1444 		rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1445 }
1446 
1447 void rt2800_clear_beacon(struct queue_entry *entry)
1448 {
1449 	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1450 	u32 orig_reg, reg;
1451 
1452 	/*
1453 	 * Disable beaconing while we are reloading the beacon data,
1454 	 * otherwise we might be sending out invalid data.
1455 	 */
1456 	orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1457 	reg = orig_reg;
1458 	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1459 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1460 
1461 	/*
1462 	 * Clear beacon.
1463 	 */
1464 	rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1465 	__clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
1466 
1467 	/*
1468 	 * Change global beacons settings.
1469 	 */
1470 	rt2800_update_beacons_setup(rt2x00dev);
1471 	/*
1472 	 * Restore beaconing state.
1473 	 */
1474 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1475 }
1476 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1477 
1478 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1479 const struct rt2x00debug rt2800_rt2x00debug = {
1480 	.owner	= THIS_MODULE,
1481 	.csr	= {
1482 		.read		= rt2800_register_read,
1483 		.write		= rt2800_register_write,
1484 		.flags		= RT2X00DEBUGFS_OFFSET,
1485 		.word_base	= CSR_REG_BASE,
1486 		.word_size	= sizeof(u32),
1487 		.word_count	= CSR_REG_SIZE / sizeof(u32),
1488 	},
1489 	.eeprom	= {
1490 		/* NOTE: The local EEPROM access functions can't
1491 		 * be used here, use the generic versions instead.
1492 		 */
1493 		.read		= rt2x00_eeprom_read,
1494 		.write		= rt2x00_eeprom_write,
1495 		.word_base	= EEPROM_BASE,
1496 		.word_size	= sizeof(u16),
1497 		.word_count	= EEPROM_SIZE / sizeof(u16),
1498 	},
1499 	.bbp	= {
1500 		.read		= rt2800_bbp_read,
1501 		.write		= rt2800_bbp_write,
1502 		.word_base	= BBP_BASE,
1503 		.word_size	= sizeof(u8),
1504 		.word_count	= BBP_SIZE / sizeof(u8),
1505 	},
1506 	.rf	= {
1507 		.read		= rt2x00_rf_read,
1508 		.write		= rt2800_rf_write,
1509 		.word_base	= RF_BASE,
1510 		.word_size	= sizeof(u32),
1511 		.word_count	= RF_SIZE / sizeof(u32),
1512 	},
1513 	.rfcsr	= {
1514 		.read		= rt2800_rfcsr_read,
1515 		.write		= rt2800_rfcsr_write,
1516 		.word_base	= RFCSR_BASE,
1517 		.word_size	= sizeof(u8),
1518 		.word_count	= RFCSR_SIZE / sizeof(u8),
1519 	},
1520 };
1521 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1522 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1523 
1524 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1525 {
1526 	u32 reg;
1527 
1528 	if (rt2x00_rt(rt2x00dev, RT3290)) {
1529 		reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
1530 		return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1531 	} else {
1532 		reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
1533 		return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1534 	}
1535 }
1536 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1537 
1538 #ifdef CONFIG_RT2X00_LIB_LEDS
1539 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1540 				  enum led_brightness brightness)
1541 {
1542 	struct rt2x00_led *led =
1543 	    container_of(led_cdev, struct rt2x00_led, led_dev);
1544 	unsigned int enabled = brightness != LED_OFF;
1545 	unsigned int bg_mode =
1546 	    (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
1547 	unsigned int polarity =
1548 		rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1549 				   EEPROM_FREQ_LED_POLARITY);
1550 	unsigned int ledmode =
1551 		rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1552 				   EEPROM_FREQ_LED_MODE);
1553 	u32 reg;
1554 
1555 	/* Check for SoC (SOC devices don't support MCU requests) */
1556 	if (rt2x00_is_soc(led->rt2x00dev)) {
1557 		reg = rt2800_register_read(led->rt2x00dev, LED_CFG);
1558 
1559 		/* Set LED Polarity */
1560 		rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1561 
1562 		/* Set LED Mode */
1563 		if (led->type == LED_TYPE_RADIO) {
1564 			rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1565 					   enabled ? 3 : 0);
1566 		} else if (led->type == LED_TYPE_ASSOC) {
1567 			rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1568 					   enabled ? 3 : 0);
1569 		} else if (led->type == LED_TYPE_QUALITY) {
1570 			rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1571 					   enabled ? 3 : 0);
1572 		}
1573 
1574 		rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1575 
1576 	} else {
1577 		if (led->type == LED_TYPE_RADIO) {
1578 			rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1579 					      enabled ? 0x20 : 0);
1580 		} else if (led->type == LED_TYPE_ASSOC) {
1581 			rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1582 					      enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1583 		} else if (led->type == LED_TYPE_QUALITY) {
1584 			/*
1585 			 * The brightness is divided into 6 levels (0 - 5),
1586 			 * The specs tell us the following levels:
1587 			 *	0, 1 ,3, 7, 15, 31
1588 			 * to determine the level in a simple way we can simply
1589 			 * work with bitshifting:
1590 			 *	(1 << level) - 1
1591 			 */
1592 			rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1593 					      (1 << brightness / (LED_FULL / 6)) - 1,
1594 					      polarity);
1595 		}
1596 	}
1597 }
1598 
1599 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1600 		     struct rt2x00_led *led, enum led_type type)
1601 {
1602 	led->rt2x00dev = rt2x00dev;
1603 	led->type = type;
1604 	led->led_dev.brightness_set = rt2800_brightness_set;
1605 	led->flags = LED_INITIALIZED;
1606 }
1607 #endif /* CONFIG_RT2X00_LIB_LEDS */
1608 
1609 /*
1610  * Configuration handlers.
1611  */
1612 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1613 			       const u8 *address,
1614 			       int wcid)
1615 {
1616 	struct mac_wcid_entry wcid_entry;
1617 	u32 offset;
1618 
1619 	offset = MAC_WCID_ENTRY(wcid);
1620 
1621 	memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1622 	if (address)
1623 		memcpy(wcid_entry.mac, address, ETH_ALEN);
1624 
1625 	rt2800_register_multiwrite(rt2x00dev, offset,
1626 				      &wcid_entry, sizeof(wcid_entry));
1627 }
1628 
1629 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1630 {
1631 	u32 offset;
1632 	offset = MAC_WCID_ATTR_ENTRY(wcid);
1633 	rt2800_register_write(rt2x00dev, offset, 0);
1634 }
1635 
1636 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1637 					   int wcid, u32 bssidx)
1638 {
1639 	u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1640 	u32 reg;
1641 
1642 	/*
1643 	 * The BSS Idx numbers is split in a main value of 3 bits,
1644 	 * and a extended field for adding one additional bit to the value.
1645 	 */
1646 	reg = rt2800_register_read(rt2x00dev, offset);
1647 	rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1648 	rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1649 			   (bssidx & 0x8) >> 3);
1650 	rt2800_register_write(rt2x00dev, offset, reg);
1651 }
1652 
1653 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1654 					   struct rt2x00lib_crypto *crypto,
1655 					   struct ieee80211_key_conf *key)
1656 {
1657 	struct mac_iveiv_entry iveiv_entry;
1658 	u32 offset;
1659 	u32 reg;
1660 
1661 	offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1662 
1663 	if (crypto->cmd == SET_KEY) {
1664 		reg = rt2800_register_read(rt2x00dev, offset);
1665 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1666 				   !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1667 		/*
1668 		 * Both the cipher as the BSS Idx numbers are split in a main
1669 		 * value of 3 bits, and a extended field for adding one additional
1670 		 * bit to the value.
1671 		 */
1672 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1673 				   (crypto->cipher & 0x7));
1674 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1675 				   (crypto->cipher & 0x8) >> 3);
1676 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1677 		rt2800_register_write(rt2x00dev, offset, reg);
1678 	} else {
1679 		/* Delete the cipher without touching the bssidx */
1680 		reg = rt2800_register_read(rt2x00dev, offset);
1681 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1682 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1683 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1684 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1685 		rt2800_register_write(rt2x00dev, offset, reg);
1686 	}
1687 
1688 	if (test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
1689 		return;
1690 
1691 	offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1692 
1693 	memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1694 	if ((crypto->cipher == CIPHER_TKIP) ||
1695 	    (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1696 	    (crypto->cipher == CIPHER_AES))
1697 		iveiv_entry.iv[3] |= 0x20;
1698 	iveiv_entry.iv[3] |= key->keyidx << 6;
1699 	rt2800_register_multiwrite(rt2x00dev, offset,
1700 				   &iveiv_entry, sizeof(iveiv_entry));
1701 }
1702 
1703 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1704 			     struct rt2x00lib_crypto *crypto,
1705 			     struct ieee80211_key_conf *key)
1706 {
1707 	struct hw_key_entry key_entry;
1708 	struct rt2x00_field32 field;
1709 	u32 offset;
1710 	u32 reg;
1711 
1712 	if (crypto->cmd == SET_KEY) {
1713 		key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1714 
1715 		memcpy(key_entry.key, crypto->key,
1716 		       sizeof(key_entry.key));
1717 		memcpy(key_entry.tx_mic, crypto->tx_mic,
1718 		       sizeof(key_entry.tx_mic));
1719 		memcpy(key_entry.rx_mic, crypto->rx_mic,
1720 		       sizeof(key_entry.rx_mic));
1721 
1722 		offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1723 		rt2800_register_multiwrite(rt2x00dev, offset,
1724 					      &key_entry, sizeof(key_entry));
1725 	}
1726 
1727 	/*
1728 	 * The cipher types are stored over multiple registers
1729 	 * starting with SHARED_KEY_MODE_BASE each word will have
1730 	 * 32 bits and contains the cipher types for 2 bssidx each.
1731 	 * Using the correct defines correctly will cause overhead,
1732 	 * so just calculate the correct offset.
1733 	 */
1734 	field.bit_offset = 4 * (key->hw_key_idx % 8);
1735 	field.bit_mask = 0x7 << field.bit_offset;
1736 
1737 	offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1738 
1739 	reg = rt2800_register_read(rt2x00dev, offset);
1740 	rt2x00_set_field32(&reg, field,
1741 			   (crypto->cmd == SET_KEY) * crypto->cipher);
1742 	rt2800_register_write(rt2x00dev, offset, reg);
1743 
1744 	/*
1745 	 * Update WCID information
1746 	 */
1747 	rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1748 	rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1749 				       crypto->bssidx);
1750 	rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1751 
1752 	return 0;
1753 }
1754 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1755 
1756 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1757 			       struct rt2x00lib_crypto *crypto,
1758 			       struct ieee80211_key_conf *key)
1759 {
1760 	struct hw_key_entry key_entry;
1761 	u32 offset;
1762 
1763 	if (crypto->cmd == SET_KEY) {
1764 		/*
1765 		 * Allow key configuration only for STAs that are
1766 		 * known by the hw.
1767 		 */
1768 		if (crypto->wcid > WCID_END)
1769 			return -ENOSPC;
1770 		key->hw_key_idx = crypto->wcid;
1771 
1772 		memcpy(key_entry.key, crypto->key,
1773 		       sizeof(key_entry.key));
1774 		memcpy(key_entry.tx_mic, crypto->tx_mic,
1775 		       sizeof(key_entry.tx_mic));
1776 		memcpy(key_entry.rx_mic, crypto->rx_mic,
1777 		       sizeof(key_entry.rx_mic));
1778 
1779 		offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1780 		rt2800_register_multiwrite(rt2x00dev, offset,
1781 					      &key_entry, sizeof(key_entry));
1782 	}
1783 
1784 	/*
1785 	 * Update WCID information
1786 	 */
1787 	rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1788 
1789 	return 0;
1790 }
1791 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1792 
1793 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
1794 {
1795 	u8 i, max_psdu;
1796 	u32 reg;
1797 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1798 
1799 	for (i = 0; i < 3; i++)
1800 		if (drv_data->ampdu_factor_cnt[i] > 0)
1801 			break;
1802 
1803 	max_psdu = min(drv_data->max_psdu, i);
1804 
1805 	reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
1806 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, max_psdu);
1807 	rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1808 }
1809 
1810 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1811 		   struct ieee80211_sta *sta)
1812 {
1813 	struct rt2x00_dev *rt2x00dev = hw->priv;
1814 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1815 	struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1816 	int wcid;
1817 
1818 	/*
1819 	 * Limit global maximum TX AMPDU length to smallest value of all
1820 	 * connected stations. In AP mode this can be suboptimal, but we
1821 	 * do not have a choice if some connected STA is not capable to
1822 	 * receive the same amount of data like the others.
1823 	 */
1824 	if (sta->deflink.ht_cap.ht_supported) {
1825 		drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]++;
1826 		rt2800_set_max_psdu_len(rt2x00dev);
1827 	}
1828 
1829 	/*
1830 	 * Search for the first free WCID entry and return the corresponding
1831 	 * index.
1832 	 */
1833 	wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
1834 
1835 	/*
1836 	 * Store selected wcid even if it is invalid so that we can
1837 	 * later decide if the STA is uploaded into the hw.
1838 	 */
1839 	sta_priv->wcid = wcid;
1840 
1841 	/*
1842 	 * No space left in the device, however, we can still communicate
1843 	 * with the STA -> No error.
1844 	 */
1845 	if (wcid > WCID_END)
1846 		return 0;
1847 
1848 	__set_bit(wcid - WCID_START, drv_data->sta_ids);
1849 	drv_data->wcid_to_sta[wcid - WCID_START] = sta;
1850 
1851 	/*
1852 	 * Clean up WCID attributes and write STA address to the device.
1853 	 */
1854 	rt2800_delete_wcid_attr(rt2x00dev, wcid);
1855 	rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1856 	rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1857 				       rt2x00lib_get_bssidx(rt2x00dev, vif));
1858 	return 0;
1859 }
1860 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1861 
1862 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1863 		      struct ieee80211_sta *sta)
1864 {
1865 	struct rt2x00_dev *rt2x00dev = hw->priv;
1866 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1867 	struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1868 	int wcid = sta_priv->wcid;
1869 
1870 	if (sta->deflink.ht_cap.ht_supported) {
1871 		drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]--;
1872 		rt2800_set_max_psdu_len(rt2x00dev);
1873 	}
1874 
1875 	if (wcid > WCID_END)
1876 		return 0;
1877 	/*
1878 	 * Remove WCID entry, no need to clean the attributes as they will
1879 	 * get renewed when the WCID is reused.
1880 	 */
1881 	rt2800_config_wcid(rt2x00dev, NULL, wcid);
1882 	drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1883 	__clear_bit(wcid - WCID_START, drv_data->sta_ids);
1884 
1885 	return 0;
1886 }
1887 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1888 
1889 void rt2800_pre_reset_hw(struct rt2x00_dev *rt2x00dev)
1890 {
1891 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1892 	struct data_queue *queue = rt2x00dev->bcn;
1893 	struct queue_entry *entry;
1894 	int i, wcid;
1895 
1896 	for (wcid = WCID_START; wcid < WCID_END; wcid++) {
1897 		drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1898 		__clear_bit(wcid - WCID_START, drv_data->sta_ids);
1899 	}
1900 
1901 	for (i = 0; i < queue->limit; i++) {
1902 		entry = &queue->entries[i];
1903 		clear_bit(ENTRY_BCN_ASSIGNED, &entry->flags);
1904 	}
1905 }
1906 EXPORT_SYMBOL_GPL(rt2800_pre_reset_hw);
1907 
1908 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1909 			  const unsigned int filter_flags)
1910 {
1911 	u32 reg;
1912 
1913 	/*
1914 	 * Start configuration steps.
1915 	 * Note that the version error will always be dropped
1916 	 * and broadcast frames will always be accepted since
1917 	 * there is no filter for it at this time.
1918 	 */
1919 	reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG);
1920 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1921 			   !(filter_flags & FIF_FCSFAIL));
1922 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1923 			   !(filter_flags & FIF_PLCPFAIL));
1924 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1925 			   !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
1926 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1927 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1928 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1929 			   !(filter_flags & FIF_ALLMULTI));
1930 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1931 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1932 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1933 			   !(filter_flags & FIF_CONTROL));
1934 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1935 			   !(filter_flags & FIF_CONTROL));
1936 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1937 			   !(filter_flags & FIF_CONTROL));
1938 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1939 			   !(filter_flags & FIF_CONTROL));
1940 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1941 			   !(filter_flags & FIF_CONTROL));
1942 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1943 			   !(filter_flags & FIF_PSPOLL));
1944 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1945 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1946 			   !(filter_flags & FIF_CONTROL));
1947 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1948 			   !(filter_flags & FIF_CONTROL));
1949 	rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1950 }
1951 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1952 
1953 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1954 			struct rt2x00intf_conf *conf, const unsigned int flags)
1955 {
1956 	u32 reg;
1957 	bool update_bssid = false;
1958 
1959 	if (flags & CONFIG_UPDATE_TYPE) {
1960 		/*
1961 		 * Enable synchronisation.
1962 		 */
1963 		reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1964 		rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1965 		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1966 
1967 		if (conf->sync == TSF_SYNC_AP_NONE) {
1968 			/*
1969 			 * Tune beacon queue transmit parameters for AP mode
1970 			 */
1971 			reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1972 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1973 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1974 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1975 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1976 			rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1977 		} else {
1978 			reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1979 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1980 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1981 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1982 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1983 			rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1984 		}
1985 	}
1986 
1987 	if (flags & CONFIG_UPDATE_MAC) {
1988 		if (flags & CONFIG_UPDATE_TYPE &&
1989 		    conf->sync == TSF_SYNC_AP_NONE) {
1990 			/*
1991 			 * The BSSID register has to be set to our own mac
1992 			 * address in AP mode.
1993 			 */
1994 			memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1995 			update_bssid = true;
1996 		}
1997 
1998 		if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1999 			reg = le32_to_cpu(conf->mac[1]);
2000 			rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
2001 			conf->mac[1] = cpu_to_le32(reg);
2002 		}
2003 
2004 		rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
2005 					      conf->mac, sizeof(conf->mac));
2006 	}
2007 
2008 	if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
2009 		if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
2010 			reg = le32_to_cpu(conf->bssid[1]);
2011 			rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
2012 			rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
2013 			conf->bssid[1] = cpu_to_le32(reg);
2014 		}
2015 
2016 		rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
2017 					      conf->bssid, sizeof(conf->bssid));
2018 	}
2019 }
2020 EXPORT_SYMBOL_GPL(rt2800_config_intf);
2021 
2022 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
2023 				    struct rt2x00lib_erp *erp)
2024 {
2025 	bool any_sta_nongf = !!(erp->ht_opmode &
2026 				IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
2027 	u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
2028 	u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
2029 	u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
2030 	u32 reg;
2031 
2032 	/* default protection rate for HT20: OFDM 24M */
2033 	mm20_rate = gf20_rate = 0x4004;
2034 
2035 	/* default protection rate for HT40: duplicate OFDM 24M */
2036 	mm40_rate = gf40_rate = 0x4084;
2037 
2038 	switch (protection) {
2039 	case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
2040 		/*
2041 		 * All STAs in this BSS are HT20/40 but there might be
2042 		 * STAs not supporting greenfield mode.
2043 		 * => Disable protection for HT transmissions.
2044 		 */
2045 		mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
2046 
2047 		break;
2048 	case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2049 		/*
2050 		 * All STAs in this BSS are HT20 or HT20/40 but there
2051 		 * might be STAs not supporting greenfield mode.
2052 		 * => Protect all HT40 transmissions.
2053 		 */
2054 		mm20_mode = gf20_mode = 0;
2055 		mm40_mode = gf40_mode = 1;
2056 
2057 		break;
2058 	case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
2059 		/*
2060 		 * Nonmember protection:
2061 		 * According to 802.11n we _should_ protect all
2062 		 * HT transmissions (but we don't have to).
2063 		 *
2064 		 * But if cts_protection is enabled we _shall_ protect
2065 		 * all HT transmissions using a CCK rate.
2066 		 *
2067 		 * And if any station is non GF we _shall_ protect
2068 		 * GF transmissions.
2069 		 *
2070 		 * We decide to protect everything
2071 		 * -> fall through to mixed mode.
2072 		 */
2073 	case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2074 		/*
2075 		 * Legacy STAs are present
2076 		 * => Protect all HT transmissions.
2077 		 */
2078 		mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1;
2079 
2080 		/*
2081 		 * If erp protection is needed we have to protect HT
2082 		 * transmissions with CCK 11M long preamble.
2083 		 */
2084 		if (erp->cts_protection) {
2085 			/* don't duplicate RTS/CTS in CCK mode */
2086 			mm20_rate = mm40_rate = 0x0003;
2087 			gf20_rate = gf40_rate = 0x0003;
2088 		}
2089 		break;
2090 	}
2091 
2092 	/* check for STAs not supporting greenfield mode */
2093 	if (any_sta_nongf)
2094 		gf20_mode = gf40_mode = 1;
2095 
2096 	/* Update HT protection config */
2097 	reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
2098 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
2099 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
2100 	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2101 
2102 	reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
2103 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
2104 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
2105 	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2106 
2107 	reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
2108 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
2109 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
2110 	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2111 
2112 	reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
2113 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
2114 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
2115 	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2116 }
2117 
2118 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
2119 		       u32 changed)
2120 {
2121 	u32 reg;
2122 
2123 	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2124 		reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
2125 		rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
2126 				   !!erp->short_preamble);
2127 		rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2128 	}
2129 
2130 	if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2131 		reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
2132 		rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
2133 				   erp->cts_protection ? 2 : 0);
2134 		rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2135 	}
2136 
2137 	if (changed & BSS_CHANGED_BASIC_RATES) {
2138 		rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
2139 				      0xff0 | erp->basic_rates);
2140 		rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2141 	}
2142 
2143 	if (changed & BSS_CHANGED_ERP_SLOT) {
2144 		reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
2145 		rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
2146 				   erp->slot_time);
2147 		rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2148 
2149 		reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
2150 		rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
2151 		rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2152 	}
2153 
2154 	if (changed & BSS_CHANGED_BEACON_INT) {
2155 		reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
2156 		rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
2157 				   erp->beacon_int * 16);
2158 		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2159 	}
2160 
2161 	if (changed & BSS_CHANGED_HT)
2162 		rt2800_config_ht_opmode(rt2x00dev, erp);
2163 }
2164 EXPORT_SYMBOL_GPL(rt2800_config_erp);
2165 
2166 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev,
2167 				    const struct rt2x00_field32 mask)
2168 {
2169 	unsigned int i;
2170 	u32 reg;
2171 
2172 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2173 		reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
2174 		if (!rt2x00_get_field32(reg, mask))
2175 			return 0;
2176 
2177 		udelay(REGISTER_BUSY_DELAY);
2178 	}
2179 
2180 	rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
2181 	return -EACCES;
2182 }
2183 
2184 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2185 {
2186 	unsigned int i;
2187 	u8 value;
2188 
2189 	/*
2190 	 * BBP was enabled after firmware was loaded,
2191 	 * but we need to reactivate it now.
2192 	 */
2193 	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2194 	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2195 	msleep(1);
2196 
2197 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2198 		value = rt2800_bbp_read(rt2x00dev, 0);
2199 		if ((value != 0xff) && (value != 0x00))
2200 			return 0;
2201 		udelay(REGISTER_BUSY_DELAY);
2202 	}
2203 
2204 	rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
2205 	return -EACCES;
2206 }
2207 
2208 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
2209 {
2210 	u32 reg;
2211 	u16 eeprom;
2212 	u8 led_ctrl, led_g_mode, led_r_mode;
2213 
2214 	reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
2215 	if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
2216 		rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
2217 		rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
2218 	} else {
2219 		rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
2220 		rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
2221 	}
2222 	rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2223 
2224 	reg = rt2800_register_read(rt2x00dev, LED_CFG);
2225 	led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
2226 	led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
2227 	if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
2228 	    led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
2229 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
2230 		led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
2231 		if (led_ctrl == 0 || led_ctrl > 0x40) {
2232 			rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
2233 			rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
2234 			rt2800_register_write(rt2x00dev, LED_CFG, reg);
2235 		} else {
2236 			rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
2237 					   (led_g_mode << 2) | led_r_mode, 1);
2238 		}
2239 	}
2240 }
2241 
2242 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
2243 				     enum antenna ant)
2244 {
2245 	u32 reg;
2246 	u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
2247 	u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
2248 
2249 	if (rt2x00_is_pci(rt2x00dev)) {
2250 		reg = rt2800_register_read(rt2x00dev, E2PROM_CSR);
2251 		rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
2252 		rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
2253 	} else if (rt2x00_is_usb(rt2x00dev))
2254 		rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
2255 				   eesk_pin, 0);
2256 
2257 	reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2258 	rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
2259 	rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
2260 	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2261 }
2262 
2263 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
2264 {
2265 	u8 r1;
2266 	u8 r3;
2267 	u16 eeprom;
2268 
2269 	r1 = rt2800_bbp_read(rt2x00dev, 1);
2270 	r3 = rt2800_bbp_read(rt2x00dev, 3);
2271 
2272 	if (rt2x00_rt(rt2x00dev, RT3572) &&
2273 	    rt2x00_has_cap_bt_coexist(rt2x00dev))
2274 		rt2800_config_3572bt_ant(rt2x00dev);
2275 
2276 	/*
2277 	 * Configure the TX antenna.
2278 	 */
2279 	switch (ant->tx_chain_num) {
2280 	case 1:
2281 		rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
2282 		break;
2283 	case 2:
2284 		if (rt2x00_rt(rt2x00dev, RT3572) &&
2285 		    rt2x00_has_cap_bt_coexist(rt2x00dev))
2286 			rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
2287 		else
2288 			rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
2289 		break;
2290 	case 3:
2291 		rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
2292 		break;
2293 	}
2294 
2295 	/*
2296 	 * Configure the RX antenna.
2297 	 */
2298 	switch (ant->rx_chain_num) {
2299 	case 1:
2300 		if (rt2x00_rt(rt2x00dev, RT3070) ||
2301 		    rt2x00_rt(rt2x00dev, RT3090) ||
2302 		    rt2x00_rt(rt2x00dev, RT3352) ||
2303 		    rt2x00_rt(rt2x00dev, RT3390)) {
2304 			eeprom = rt2800_eeprom_read(rt2x00dev,
2305 						    EEPROM_NIC_CONF1);
2306 			if (rt2x00_get_field16(eeprom,
2307 						EEPROM_NIC_CONF1_ANT_DIVERSITY))
2308 				rt2800_set_ant_diversity(rt2x00dev,
2309 						rt2x00dev->default_ant.rx);
2310 		}
2311 		rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
2312 		break;
2313 	case 2:
2314 		if (rt2x00_rt(rt2x00dev, RT3572) &&
2315 		    rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2316 			rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
2317 			rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
2318 				rt2x00dev->curr_band == NL80211_BAND_5GHZ);
2319 			rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
2320 		} else {
2321 			rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
2322 		}
2323 		break;
2324 	case 3:
2325 		rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
2326 		break;
2327 	}
2328 
2329 	rt2800_bbp_write(rt2x00dev, 3, r3);
2330 	rt2800_bbp_write(rt2x00dev, 1, r1);
2331 
2332 	if (rt2x00_rt(rt2x00dev, RT3593) ||
2333 	    rt2x00_rt(rt2x00dev, RT3883)) {
2334 		if (ant->rx_chain_num == 1)
2335 			rt2800_bbp_write(rt2x00dev, 86, 0x00);
2336 		else
2337 			rt2800_bbp_write(rt2x00dev, 86, 0x46);
2338 	}
2339 }
2340 EXPORT_SYMBOL_GPL(rt2800_config_ant);
2341 
2342 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
2343 				   struct rt2x00lib_conf *libconf)
2344 {
2345 	u16 eeprom;
2346 	short lna_gain;
2347 
2348 	if (libconf->rf.channel <= 14) {
2349 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2350 		lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
2351 	} else if (libconf->rf.channel <= 64) {
2352 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2353 		lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
2354 	} else if (libconf->rf.channel <= 128) {
2355 		if (rt2x00_rt(rt2x00dev, RT3593) ||
2356 		    rt2x00_rt(rt2x00dev, RT3883)) {
2357 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2358 			lna_gain = rt2x00_get_field16(eeprom,
2359 						      EEPROM_EXT_LNA2_A1);
2360 		} else {
2361 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
2362 			lna_gain = rt2x00_get_field16(eeprom,
2363 						      EEPROM_RSSI_BG2_LNA_A1);
2364 		}
2365 	} else {
2366 		if (rt2x00_rt(rt2x00dev, RT3593) ||
2367 		    rt2x00_rt(rt2x00dev, RT3883)) {
2368 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2369 			lna_gain = rt2x00_get_field16(eeprom,
2370 						      EEPROM_EXT_LNA2_A2);
2371 		} else {
2372 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
2373 			lna_gain = rt2x00_get_field16(eeprom,
2374 						      EEPROM_RSSI_A2_LNA_A2);
2375 		}
2376 	}
2377 
2378 	rt2x00dev->lna_gain = lna_gain;
2379 }
2380 
2381 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)
2382 {
2383 	return clk_get_rate(rt2x00dev->clk) == 20000000;
2384 }
2385 
2386 #define FREQ_OFFSET_BOUND	0x5f
2387 
2388 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
2389 {
2390 	u8 freq_offset, prev_freq_offset;
2391 	u8 rfcsr, prev_rfcsr;
2392 
2393 	freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2394 	freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
2395 
2396 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
2397 	prev_rfcsr = rfcsr;
2398 
2399 	rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
2400 	if (rfcsr == prev_rfcsr)
2401 		return;
2402 
2403 	if (rt2x00_is_usb(rt2x00dev)) {
2404 		rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
2405 				   freq_offset, prev_rfcsr);
2406 		return;
2407 	}
2408 
2409 	prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
2410 	while (prev_freq_offset != freq_offset) {
2411 		if (prev_freq_offset < freq_offset)
2412 			prev_freq_offset++;
2413 		else
2414 			prev_freq_offset--;
2415 
2416 		rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
2417 		rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2418 
2419 		usleep_range(1000, 1500);
2420 	}
2421 }
2422 
2423 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
2424 					 struct ieee80211_conf *conf,
2425 					 struct rf_channel *rf,
2426 					 struct channel_info *info)
2427 {
2428 	rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
2429 
2430 	if (rt2x00dev->default_ant.tx_chain_num == 1)
2431 		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
2432 
2433 	if (rt2x00dev->default_ant.rx_chain_num == 1) {
2434 		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
2435 		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2436 	} else if (rt2x00dev->default_ant.rx_chain_num == 2)
2437 		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2438 
2439 	if (rf->channel > 14) {
2440 		/*
2441 		 * When TX power is below 0, we should increase it by 7 to
2442 		 * make it a positive value (Minimum value is -7).
2443 		 * However this means that values between 0 and 7 have
2444 		 * double meaning, and we should set a 7DBm boost flag.
2445 		 */
2446 		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
2447 				   (info->default_power1 >= 0));
2448 
2449 		if (info->default_power1 < 0)
2450 			info->default_power1 += 7;
2451 
2452 		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
2453 
2454 		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
2455 				   (info->default_power2 >= 0));
2456 
2457 		if (info->default_power2 < 0)
2458 			info->default_power2 += 7;
2459 
2460 		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
2461 	} else {
2462 		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2463 		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
2464 	}
2465 
2466 	rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2467 
2468 	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2469 	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2470 	rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2471 	rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2472 
2473 	udelay(200);
2474 
2475 	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2476 	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2477 	rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2478 	rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2479 
2480 	udelay(200);
2481 
2482 	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2483 	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2484 	rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2485 	rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2486 }
2487 
2488 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2489 					 struct ieee80211_conf *conf,
2490 					 struct rf_channel *rf,
2491 					 struct channel_info *info)
2492 {
2493 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2494 	u8 rfcsr, calib_tx, calib_rx;
2495 
2496 	rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2497 
2498 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2499 	rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2500 	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2501 
2502 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2503 	rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2504 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2505 
2506 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2507 	rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2508 	rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2509 
2510 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2511 	rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2512 	rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2513 
2514 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2515 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2516 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2517 			  rt2x00dev->default_ant.rx_chain_num <= 1);
2518 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2519 			  rt2x00dev->default_ant.rx_chain_num <= 2);
2520 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2521 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2522 			  rt2x00dev->default_ant.tx_chain_num <= 1);
2523 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2524 			  rt2x00dev->default_ant.tx_chain_num <= 2);
2525 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2526 
2527 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2528 	rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2529 	rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2530 
2531 	if (rt2x00_rt(rt2x00dev, RT3390)) {
2532 		calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2533 		calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2534 	} else {
2535 		if (conf_is_ht40(conf)) {
2536 			calib_tx = drv_data->calibration_bw40;
2537 			calib_rx = drv_data->calibration_bw40;
2538 		} else {
2539 			calib_tx = drv_data->calibration_bw20;
2540 			calib_rx = drv_data->calibration_bw20;
2541 		}
2542 	}
2543 
2544 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 24);
2545 	rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2546 	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2547 
2548 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
2549 	rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2550 	rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2551 
2552 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2553 	rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2554 	rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2555 
2556 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2557 	rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2558 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2559 
2560 	usleep_range(1000, 1500);
2561 
2562 	rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2563 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2564 }
2565 
2566 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2567 					 struct ieee80211_conf *conf,
2568 					 struct rf_channel *rf,
2569 					 struct channel_info *info)
2570 {
2571 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2572 	u8 rfcsr;
2573 	u32 reg;
2574 
2575 	if (rf->channel <= 14) {
2576 		rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2577 		rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2578 	} else {
2579 		rt2800_bbp_write(rt2x00dev, 25, 0x09);
2580 		rt2800_bbp_write(rt2x00dev, 26, 0xff);
2581 	}
2582 
2583 	rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2584 	rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2585 
2586 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2587 	rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2588 	if (rf->channel <= 14)
2589 		rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2590 	else
2591 		rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2592 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2593 
2594 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 5);
2595 	if (rf->channel <= 14)
2596 		rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2597 	else
2598 		rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2599 	rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2600 
2601 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2602 	if (rf->channel <= 14) {
2603 		rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2604 		rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2605 				  info->default_power1);
2606 	} else {
2607 		rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2608 		rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2609 				(info->default_power1 & 0x3) |
2610 				((info->default_power1 & 0xC) << 1));
2611 	}
2612 	rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2613 
2614 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2615 	if (rf->channel <= 14) {
2616 		rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2617 		rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2618 				  info->default_power2);
2619 	} else {
2620 		rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2621 		rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2622 				(info->default_power2 & 0x3) |
2623 				((info->default_power2 & 0xC) << 1));
2624 	}
2625 	rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2626 
2627 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2628 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2629 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2630 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2631 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2632 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2633 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2634 	if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2635 		if (rf->channel <= 14) {
2636 			rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2637 			rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2638 		}
2639 		rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2640 		rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2641 	} else {
2642 		switch (rt2x00dev->default_ant.tx_chain_num) {
2643 		case 1:
2644 			rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2645 			fallthrough;
2646 		case 2:
2647 			rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2648 			break;
2649 		}
2650 
2651 		switch (rt2x00dev->default_ant.rx_chain_num) {
2652 		case 1:
2653 			rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2654 			fallthrough;
2655 		case 2:
2656 			rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2657 			break;
2658 		}
2659 	}
2660 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2661 
2662 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2663 	rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2664 	rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2665 
2666 	if (conf_is_ht40(conf)) {
2667 		rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2668 		rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2669 	} else {
2670 		rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2671 		rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2672 	}
2673 
2674 	if (rf->channel <= 14) {
2675 		rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2676 		rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2677 		rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2678 		rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2679 		rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2680 		rfcsr = 0x4c;
2681 		rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2682 				  drv_data->txmixer_gain_24g);
2683 		rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2684 		rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2685 		rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2686 		rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2687 		rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2688 		rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2689 		rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2690 		rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2691 	} else {
2692 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2693 		rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2694 		rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2695 		rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2696 		rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2697 		rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2698 		rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2699 		rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2700 		rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2701 		rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2702 		rfcsr = 0x7a;
2703 		rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2704 				  drv_data->txmixer_gain_5g);
2705 		rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2706 		rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2707 		if (rf->channel <= 64) {
2708 			rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2709 			rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2710 			rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2711 		} else if (rf->channel <= 128) {
2712 			rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2713 			rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2714 			rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2715 		} else {
2716 			rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2717 			rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2718 			rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2719 		}
2720 		rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2721 		rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2722 		rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2723 	}
2724 
2725 	reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2726 	rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2727 	if (rf->channel <= 14)
2728 		rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2729 	else
2730 		rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2731 	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2732 
2733 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2734 	rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2735 	rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2736 }
2737 
2738 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2739 					 struct ieee80211_conf *conf,
2740 					 struct rf_channel *rf,
2741 					 struct channel_info *info)
2742 {
2743 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2744 	u8 txrx_agc_fc;
2745 	u8 txrx_h20m;
2746 	u8 rfcsr;
2747 	u8 bbp;
2748 	const bool txbf_enabled = false; /* TODO */
2749 
2750 	/* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2751 	bbp = rt2800_bbp_read(rt2x00dev, 109);
2752 	rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2753 	rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2754 	rt2800_bbp_write(rt2x00dev, 109, bbp);
2755 
2756 	bbp = rt2800_bbp_read(rt2x00dev, 110);
2757 	rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2758 	rt2800_bbp_write(rt2x00dev, 110, bbp);
2759 
2760 	if (rf->channel <= 14) {
2761 		/* Restore BBP 25 & 26 for 2.4 GHz */
2762 		rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2763 		rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2764 	} else {
2765 		/* Hard code BBP 25 & 26 for 5GHz */
2766 
2767 		/* Enable IQ Phase correction */
2768 		rt2800_bbp_write(rt2x00dev, 25, 0x09);
2769 		/* Setup IQ Phase correction value */
2770 		rt2800_bbp_write(rt2x00dev, 26, 0xff);
2771 	}
2772 
2773 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2774 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2775 
2776 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2777 	rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2778 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2779 
2780 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2781 	rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2782 	if (rf->channel <= 14)
2783 		rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2784 	else
2785 		rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2786 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2787 
2788 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 53);
2789 	if (rf->channel <= 14) {
2790 		rfcsr = 0;
2791 		rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2792 				  info->default_power1 & 0x1f);
2793 	} else {
2794 		if (rt2x00_is_usb(rt2x00dev))
2795 			rfcsr = 0x40;
2796 
2797 		rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2798 				  ((info->default_power1 & 0x18) << 1) |
2799 				  (info->default_power1 & 7));
2800 	}
2801 	rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2802 
2803 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 55);
2804 	if (rf->channel <= 14) {
2805 		rfcsr = 0;
2806 		rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2807 				  info->default_power2 & 0x1f);
2808 	} else {
2809 		if (rt2x00_is_usb(rt2x00dev))
2810 			rfcsr = 0x40;
2811 
2812 		rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2813 				  ((info->default_power2 & 0x18) << 1) |
2814 				  (info->default_power2 & 7));
2815 	}
2816 	rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2817 
2818 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 54);
2819 	if (rf->channel <= 14) {
2820 		rfcsr = 0;
2821 		rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2822 				  info->default_power3 & 0x1f);
2823 	} else {
2824 		if (rt2x00_is_usb(rt2x00dev))
2825 			rfcsr = 0x40;
2826 
2827 		rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2828 				  ((info->default_power3 & 0x18) << 1) |
2829 				  (info->default_power3 & 7));
2830 	}
2831 	rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2832 
2833 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2834 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2835 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2836 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2837 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2838 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2839 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2840 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2841 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2842 
2843 	switch (rt2x00dev->default_ant.tx_chain_num) {
2844 	case 3:
2845 		rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2846 		fallthrough;
2847 	case 2:
2848 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2849 		fallthrough;
2850 	case 1:
2851 		rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2852 		break;
2853 	}
2854 
2855 	switch (rt2x00dev->default_ant.rx_chain_num) {
2856 	case 3:
2857 		rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2858 		fallthrough;
2859 	case 2:
2860 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2861 		fallthrough;
2862 	case 1:
2863 		rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2864 		break;
2865 	}
2866 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2867 
2868 	rt2800_freq_cal_mode1(rt2x00dev);
2869 
2870 	if (conf_is_ht40(conf)) {
2871 		txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2872 						RFCSR24_TX_AGC_FC);
2873 		txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2874 					      RFCSR24_TX_H20M);
2875 	} else {
2876 		txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2877 						RFCSR24_TX_AGC_FC);
2878 		txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2879 					      RFCSR24_TX_H20M);
2880 	}
2881 
2882 	/* NOTE: the reference driver does not writes the new value
2883 	 * back to RFCSR 32
2884 	 */
2885 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 32);
2886 	rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2887 
2888 	if (rf->channel <= 14)
2889 		rfcsr = 0xa0;
2890 	else
2891 		rfcsr = 0x80;
2892 	rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2893 
2894 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2895 	rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2896 	rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2897 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2898 
2899 	/* Band selection */
2900 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
2901 	if (rf->channel <= 14)
2902 		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2903 	else
2904 		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2905 	rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2906 
2907 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 34);
2908 	if (rf->channel <= 14)
2909 		rfcsr = 0x3c;
2910 	else
2911 		rfcsr = 0x20;
2912 	rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2913 
2914 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2915 	if (rf->channel <= 14)
2916 		rfcsr = 0x1a;
2917 	else
2918 		rfcsr = 0x12;
2919 	rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2920 
2921 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2922 	if (rf->channel >= 1 && rf->channel <= 14)
2923 		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2924 	else if (rf->channel >= 36 && rf->channel <= 64)
2925 		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2926 	else if (rf->channel >= 100 && rf->channel <= 128)
2927 		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2928 	else
2929 		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2930 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2931 
2932 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2933 	rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2934 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2935 
2936 	rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2937 
2938 	if (rf->channel <= 14) {
2939 		rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2940 		rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2941 	} else {
2942 		rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2943 		rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2944 	}
2945 
2946 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2947 	rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2948 	rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2949 
2950 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2951 	if (rf->channel <= 14) {
2952 		rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2953 		rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2954 	} else {
2955 		rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2956 		rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2957 	}
2958 	rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2959 
2960 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2961 	if (rf->channel <= 14)
2962 		rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2963 	else
2964 		rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2965 
2966 	if (txbf_enabled)
2967 		rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2968 
2969 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2970 
2971 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
2972 	rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2973 	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2974 
2975 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
2976 	if (rf->channel <= 14)
2977 		rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2978 	else
2979 		rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2980 	rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2981 
2982 	if (rf->channel <= 14) {
2983 		rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2984 		rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2985 	} else {
2986 		rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2987 		rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2988 	}
2989 
2990 	/* Initiate VCO calibration */
2991 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2992 	if (rf->channel <= 14) {
2993 		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2994 	} else {
2995 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2996 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2997 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2998 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2999 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
3000 		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3001 	}
3002 	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3003 
3004 	if (rf->channel >= 1 && rf->channel <= 14) {
3005 		rfcsr = 0x23;
3006 		if (txbf_enabled)
3007 			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
3008 		rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3009 
3010 		rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
3011 	} else if (rf->channel >= 36 && rf->channel <= 64) {
3012 		rfcsr = 0x36;
3013 		if (txbf_enabled)
3014 			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
3015 		rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
3016 
3017 		rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
3018 	} else if (rf->channel >= 100 && rf->channel <= 128) {
3019 		rfcsr = 0x32;
3020 		if (txbf_enabled)
3021 			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
3022 		rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3023 
3024 		rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
3025 	} else {
3026 		rfcsr = 0x30;
3027 		if (txbf_enabled)
3028 			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
3029 		rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3030 
3031 		rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
3032 	}
3033 }
3034 
3035 static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev,
3036 					 struct ieee80211_conf *conf,
3037 					 struct rf_channel *rf,
3038 					 struct channel_info *info)
3039 {
3040 	u8 rfcsr;
3041 	u8 bbp;
3042 	u8 pwr1, pwr2, pwr3;
3043 
3044 	const bool txbf_enabled = false; /* TODO */
3045 
3046 	/* TODO: add band selection */
3047 
3048 	if (rf->channel <= 14)
3049 		rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
3050 	else if (rf->channel < 132)
3051 		rt2800_rfcsr_write(rt2x00dev, 6, 0x80);
3052 	else
3053 		rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
3054 
3055 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3056 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3057 
3058 	if (rf->channel <= 14)
3059 		rt2800_rfcsr_write(rt2x00dev, 11, 0x46);
3060 	else
3061 		rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
3062 
3063 	if (rf->channel <= 14)
3064 		rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
3065 	else
3066 		rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
3067 
3068 	rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
3069 
3070 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3071 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3072 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3073 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
3074 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
3075 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3076 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3077 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3078 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3079 
3080 	switch (rt2x00dev->default_ant.tx_chain_num) {
3081 	case 3:
3082 		rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
3083 		fallthrough;
3084 	case 2:
3085 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3086 		fallthrough;
3087 	case 1:
3088 		rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3089 		break;
3090 	}
3091 
3092 	switch (rt2x00dev->default_ant.rx_chain_num) {
3093 	case 3:
3094 		rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
3095 		fallthrough;
3096 	case 2:
3097 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3098 		fallthrough;
3099 	case 1:
3100 		rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3101 		break;
3102 	}
3103 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3104 
3105 	rt2800_freq_cal_mode1(rt2x00dev);
3106 
3107 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
3108 	if (!conf_is_ht40(conf))
3109 		rfcsr &= ~(0x06);
3110 	else
3111 		rfcsr |= 0x06;
3112 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3113 
3114 	if (rf->channel <= 14)
3115 		rt2800_rfcsr_write(rt2x00dev, 31, 0xa0);
3116 	else
3117 		rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3118 
3119 	if (conf_is_ht40(conf))
3120 		rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3121 	else
3122 		rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
3123 
3124 	if (rf->channel <= 14)
3125 		rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
3126 	else
3127 		rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
3128 
3129 	/* loopback RF_BS */
3130 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
3131 	if (rf->channel <= 14)
3132 		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
3133 	else
3134 		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
3135 	rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
3136 
3137 	if (rf->channel <= 14)
3138 		rfcsr = 0x23;
3139 	else if (rf->channel < 100)
3140 		rfcsr = 0x36;
3141 	else if (rf->channel < 132)
3142 		rfcsr = 0x32;
3143 	else
3144 		rfcsr = 0x30;
3145 
3146 	if (txbf_enabled)
3147 		rfcsr |= 0x40;
3148 
3149 	rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3150 
3151 	if (rf->channel <= 14)
3152 		rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
3153 	else
3154 		rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
3155 
3156 	if (rf->channel <= 14)
3157 		rfcsr = 0xbb;
3158 	else if (rf->channel < 100)
3159 		rfcsr = 0xeb;
3160 	else if (rf->channel < 132)
3161 		rfcsr = 0xb3;
3162 	else
3163 		rfcsr = 0x9b;
3164 	rt2800_rfcsr_write(rt2x00dev, 45, rfcsr);
3165 
3166 	if (rf->channel <= 14)
3167 		rfcsr = 0x8e;
3168 	else
3169 		rfcsr = 0x8a;
3170 
3171 	if (txbf_enabled)
3172 		rfcsr |= 0x20;
3173 
3174 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3175 
3176 	rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
3177 
3178 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
3179 	if (rf->channel <= 14)
3180 		rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
3181 	else
3182 		rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
3183 
3184 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 52);
3185 	if (rf->channel <= 14)
3186 		rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
3187 	else
3188 		rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
3189 
3190 	if (rf->channel <= 14) {
3191 		pwr1 = info->default_power1 & 0x1f;
3192 		pwr2 = info->default_power2 & 0x1f;
3193 		pwr3 = info->default_power3 & 0x1f;
3194 	} else {
3195 		pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) |
3196 			(info->default_power1 & 0x7);
3197 		pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) |
3198 			(info->default_power2 & 0x7);
3199 		pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) |
3200 			(info->default_power3 & 0x7);
3201 	}
3202 
3203 	rt2800_rfcsr_write(rt2x00dev, 53, pwr1);
3204 	rt2800_rfcsr_write(rt2x00dev, 54, pwr2);
3205 	rt2800_rfcsr_write(rt2x00dev, 55, pwr3);
3206 
3207 	rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n",
3208 		   rf->channel, pwr1, pwr2, pwr3);
3209 
3210 	bbp = (info->default_power1 >> 5) |
3211 	      ((info->default_power2 & 0xe0) >> 1);
3212 	rt2800_bbp_write(rt2x00dev, 109, bbp);
3213 
3214 	bbp = rt2800_bbp_read(rt2x00dev, 110);
3215 	bbp &= 0x0f;
3216 	bbp |= (info->default_power3 & 0xe0) >> 1;
3217 	rt2800_bbp_write(rt2x00dev, 110, bbp);
3218 
3219 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
3220 	if (rf->channel <= 14)
3221 		rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
3222 	else
3223 		rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
3224 
3225 	/* Enable RF tuning */
3226 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3227 	rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3228 	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3229 
3230 	udelay(2000);
3231 
3232 	bbp = rt2800_bbp_read(rt2x00dev, 49);
3233 	/* clear update flag */
3234 	rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe);
3235 	rt2800_bbp_write(rt2x00dev, 49, bbp);
3236 
3237 	/* TODO: add calibration for TxBF */
3238 }
3239 
3240 #define POWER_BOUND		0x27
3241 #define POWER_BOUND_5G		0x2b
3242 
3243 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
3244 					 struct ieee80211_conf *conf,
3245 					 struct rf_channel *rf,
3246 					 struct channel_info *info)
3247 {
3248 	u8 rfcsr;
3249 
3250 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3251 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3252 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3253 	rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3254 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3255 
3256 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3257 	if (info->default_power1 > POWER_BOUND)
3258 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
3259 	else
3260 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3261 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3262 
3263 	rt2800_freq_cal_mode1(rt2x00dev);
3264 
3265 	if (rf->channel <= 14) {
3266 		if (rf->channel == 6)
3267 			rt2800_bbp_write(rt2x00dev, 68, 0x0c);
3268 		else
3269 			rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3270 
3271 		if (rf->channel >= 1 && rf->channel <= 6)
3272 			rt2800_bbp_write(rt2x00dev, 59, 0x0f);
3273 		else if (rf->channel >= 7 && rf->channel <= 11)
3274 			rt2800_bbp_write(rt2x00dev, 59, 0x0e);
3275 		else if (rf->channel >= 12 && rf->channel <= 14)
3276 			rt2800_bbp_write(rt2x00dev, 59, 0x0d);
3277 	}
3278 }
3279 
3280 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
3281 					 struct ieee80211_conf *conf,
3282 					 struct rf_channel *rf,
3283 					 struct channel_info *info)
3284 {
3285 	u8 rfcsr;
3286 
3287 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3288 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3289 
3290 	rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
3291 	rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
3292 	rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
3293 
3294 	if (info->default_power1 > POWER_BOUND)
3295 		rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
3296 	else
3297 		rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
3298 
3299 	if (info->default_power2 > POWER_BOUND)
3300 		rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
3301 	else
3302 		rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
3303 
3304 	rt2800_freq_cal_mode1(rt2x00dev);
3305 
3306 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3307 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3308 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3309 
3310 	if ( rt2x00dev->default_ant.tx_chain_num == 2 )
3311 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3312 	else
3313 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
3314 
3315 	if ( rt2x00dev->default_ant.rx_chain_num == 2 )
3316 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3317 	else
3318 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
3319 
3320 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3321 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3322 
3323 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3324 
3325 	rt2800_rfcsr_write(rt2x00dev, 31, 80);
3326 }
3327 
3328 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
3329 					 struct ieee80211_conf *conf,
3330 					 struct rf_channel *rf,
3331 					 struct channel_info *info)
3332 {
3333 	u8 rfcsr;
3334 	int idx = rf->channel-1;
3335 
3336 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3337 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3338 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3339 	rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3340 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3341 
3342 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3343 	if (info->default_power1 > POWER_BOUND)
3344 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
3345 	else
3346 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3347 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3348 
3349 	if (rt2x00_rt(rt2x00dev, RT5392)) {
3350 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3351 		if (info->default_power2 > POWER_BOUND)
3352 			rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
3353 		else
3354 			rt2x00_set_field8(&rfcsr, RFCSR50_TX,
3355 					  info->default_power2);
3356 		rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3357 	}
3358 
3359 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3360 	if (rt2x00_rt(rt2x00dev, RT5392)) {
3361 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3362 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3363 	}
3364 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3365 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3366 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3367 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3368 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3369 
3370 	rt2800_freq_cal_mode1(rt2x00dev);
3371 
3372 	if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
3373 		if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3374 			/* r55/r59 value array of channel 1~14 */
3375 			static const u8 r55_bt_rev[] = {0x83, 0x83,
3376 				0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
3377 				0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
3378 			static const u8 r59_bt_rev[] = {0x0e, 0x0e,
3379 				0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
3380 				0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
3381 
3382 			rt2800_rfcsr_write(rt2x00dev, 55,
3383 					   r55_bt_rev[idx]);
3384 			rt2800_rfcsr_write(rt2x00dev, 59,
3385 					   r59_bt_rev[idx]);
3386 		} else {
3387 			static const u8 r59_bt[] = {0x8b, 0x8b, 0x8b,
3388 				0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
3389 				0x88, 0x88, 0x86, 0x85, 0x84};
3390 
3391 			rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
3392 		}
3393 	} else {
3394 		if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3395 			static const u8 r55_nonbt_rev[] = {0x23, 0x23,
3396 				0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
3397 				0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
3398 			static const u8 r59_nonbt_rev[] = {0x07, 0x07,
3399 				0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
3400 				0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
3401 
3402 			rt2800_rfcsr_write(rt2x00dev, 55,
3403 					   r55_nonbt_rev[idx]);
3404 			rt2800_rfcsr_write(rt2x00dev, 59,
3405 					   r59_nonbt_rev[idx]);
3406 		} else if (rt2x00_rt(rt2x00dev, RT5390) ||
3407 			   rt2x00_rt(rt2x00dev, RT5392) ||
3408 			   rt2x00_rt(rt2x00dev, RT6352)) {
3409 			static const u8 r59_non_bt[] = {0x8f, 0x8f,
3410 				0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
3411 				0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
3412 
3413 			rt2800_rfcsr_write(rt2x00dev, 59,
3414 					   r59_non_bt[idx]);
3415 		} else if (rt2x00_rt(rt2x00dev, RT5350)) {
3416 			static const u8 r59_non_bt[] = {0x0b, 0x0b,
3417 				0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
3418 				0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
3419 
3420 			rt2800_rfcsr_write(rt2x00dev, 59,
3421 					   r59_non_bt[idx]);
3422 		}
3423 	}
3424 }
3425 
3426 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
3427 					 struct ieee80211_conf *conf,
3428 					 struct rf_channel *rf,
3429 					 struct channel_info *info)
3430 {
3431 	u8 rfcsr, ep_reg;
3432 	u32 reg;
3433 	int power_bound;
3434 
3435 	/* TODO */
3436 	const bool is_11b = false;
3437 	const bool is_type_ep = false;
3438 
3439 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
3440 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
3441 			   (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
3442 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3443 
3444 	/* Order of values on rf_channel entry: N, K, mod, R */
3445 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
3446 
3447 	rfcsr = rt2800_rfcsr_read(rt2x00dev,  9);
3448 	rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
3449 	rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
3450 	rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
3451 	rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
3452 
3453 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3454 	rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
3455 	rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
3456 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3457 
3458 	if (rf->channel <= 14) {
3459 		rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
3460 		/* FIXME: RF11 owerwrite ? */
3461 		rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
3462 		rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
3463 		rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3464 		rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3465 		rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
3466 		rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3467 		rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3468 		rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
3469 		rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3470 		rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3471 		rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
3472 		rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
3473 		rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
3474 		rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
3475 		rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
3476 		rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
3477 		rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
3478 		rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
3479 		rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3480 		rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
3481 		rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3482 		rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3483 		rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
3484 		rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3485 		rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3486 		rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3487 		rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3488 		rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3489 
3490 		/* TODO RF27 <- tssi */
3491 
3492 		rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
3493 		rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
3494 		rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
3495 
3496 		if (is_11b) {
3497 			/* CCK */
3498 			rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
3499 			rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
3500 			if (is_type_ep)
3501 				rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
3502 			else
3503 				rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
3504 		} else {
3505 			/* OFDM */
3506 			if (is_type_ep)
3507 				rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
3508 			else
3509 				rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3510 		}
3511 
3512 		power_bound = POWER_BOUND;
3513 		ep_reg = 0x2;
3514 	} else {
3515 		rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
3516 		/* FIMXE: RF11 overwrite */
3517 		rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
3518 		rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
3519 		rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3520 		rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3521 		rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
3522 		rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3523 		rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
3524 		rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
3525 		rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
3526 		rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
3527 		rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
3528 		rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
3529 		rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
3530 		rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
3531 
3532 		/* TODO RF27 <- tssi */
3533 
3534 		if (rf->channel >= 36 && rf->channel <= 64) {
3535 
3536 			rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
3537 			rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
3538 			rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
3539 			rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
3540 			if (rf->channel <= 50)
3541 				rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
3542 			else if (rf->channel >= 52)
3543 				rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
3544 			rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
3545 			rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
3546 			rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
3547 			rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
3548 			rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
3549 			rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
3550 			rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
3551 			if (rf->channel <= 50) {
3552 				rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
3553 				rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
3554 			} else if (rf->channel >= 52) {
3555 				rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
3556 				rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3557 			}
3558 
3559 			rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3560 			rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
3561 			rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3562 
3563 		} else if (rf->channel >= 100 && rf->channel <= 165) {
3564 
3565 			rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
3566 			rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3567 			rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3568 			if (rf->channel <= 153) {
3569 				rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
3570 				rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
3571 			} else if (rf->channel >= 155) {
3572 				rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
3573 				rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
3574 			}
3575 			if (rf->channel <= 138) {
3576 				rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
3577 				rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
3578 				rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
3579 				rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
3580 			} else if (rf->channel >= 140) {
3581 				rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
3582 				rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
3583 				rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
3584 				rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
3585 			}
3586 			if (rf->channel <= 124)
3587 				rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
3588 			else if (rf->channel >= 126)
3589 				rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
3590 			if (rf->channel <= 138)
3591 				rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3592 			else if (rf->channel >= 140)
3593 				rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3594 			rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
3595 			if (rf->channel <= 138)
3596 				rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
3597 			else if (rf->channel >= 140)
3598 				rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
3599 			if (rf->channel <= 128)
3600 				rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3601 			else if (rf->channel >= 130)
3602 				rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
3603 			if (rf->channel <= 116)
3604 				rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
3605 			else if (rf->channel >= 118)
3606 				rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3607 			if (rf->channel <= 138)
3608 				rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
3609 			else if (rf->channel >= 140)
3610 				rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
3611 			if (rf->channel <= 116)
3612 				rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
3613 			else if (rf->channel >= 118)
3614 				rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3615 		}
3616 
3617 		power_bound = POWER_BOUND_5G;
3618 		ep_reg = 0x3;
3619 	}
3620 
3621 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3622 	if (info->default_power1 > power_bound)
3623 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
3624 	else
3625 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3626 	if (is_type_ep)
3627 		rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
3628 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3629 
3630 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3631 	if (info->default_power2 > power_bound)
3632 		rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
3633 	else
3634 		rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
3635 	if (is_type_ep)
3636 		rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
3637 	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3638 
3639 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3640 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3641 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3642 
3643 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
3644 			  rt2x00dev->default_ant.tx_chain_num >= 1);
3645 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
3646 			  rt2x00dev->default_ant.tx_chain_num == 2);
3647 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3648 
3649 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
3650 			  rt2x00dev->default_ant.rx_chain_num >= 1);
3651 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
3652 			  rt2x00dev->default_ant.rx_chain_num == 2);
3653 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3654 
3655 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3656 	rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
3657 
3658 	if (conf_is_ht40(conf))
3659 		rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
3660 	else
3661 		rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3662 
3663 	if (!is_11b) {
3664 		rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3665 		rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3666 	}
3667 
3668 	/* TODO proper frequency adjustment */
3669 	rt2800_freq_cal_mode1(rt2x00dev);
3670 
3671 	/* TODO merge with others */
3672 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3673 	rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3674 	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3675 
3676 	/* BBP settings */
3677 	rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3678 	rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3679 	rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3680 
3681 	rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3682 	rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3683 	rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3684 	rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3685 
3686 	/* GLRT band configuration */
3687 	rt2800_bbp_write(rt2x00dev, 195, 128);
3688 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3689 	rt2800_bbp_write(rt2x00dev, 195, 129);
3690 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3691 	rt2800_bbp_write(rt2x00dev, 195, 130);
3692 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3693 	rt2800_bbp_write(rt2x00dev, 195, 131);
3694 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3695 	rt2800_bbp_write(rt2x00dev, 195, 133);
3696 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3697 	rt2800_bbp_write(rt2x00dev, 195, 124);
3698 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
3699 }
3700 
3701 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
3702 					 struct ieee80211_conf *conf,
3703 					 struct rf_channel *rf,
3704 					 struct channel_info *info)
3705 {
3706 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3707 	u8 rx_agc_fc, tx_agc_fc;
3708 	u8 rfcsr;
3709 
3710 	/* Frequeny plan setting */
3711 	/* Rdiv setting (set 0x03 if Xtal==20)
3712 	 * R13[1:0]
3713 	 */
3714 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
3715 	rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
3716 			  rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
3717 	rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
3718 
3719 	/* N setting
3720 	 * R20[7:0] in rf->rf1
3721 	 * R21[0] always 0
3722 	 */
3723 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
3724 	rfcsr = (rf->rf1 & 0x00ff);
3725 	rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3726 
3727 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3728 	rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
3729 	rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3730 
3731 	/* K setting (always 0)
3732 	 * R16[3:0] (RF PLL freq selection)
3733 	 */
3734 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3735 	rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
3736 	rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3737 
3738 	/* D setting (always 0)
3739 	 * R22[2:0] (D=15, R22[2:0]=<111>)
3740 	 */
3741 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
3742 	rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
3743 	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3744 
3745 	/* Ksd setting
3746 	 * Ksd: R17<7:0> in rf->rf2
3747 	 *      R18<7:0> in rf->rf3
3748 	 *      R19<1:0> in rf->rf4
3749 	 */
3750 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
3751 	rfcsr = rf->rf2;
3752 	rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3753 
3754 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
3755 	rfcsr = rf->rf3;
3756 	rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
3757 
3758 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 19);
3759 	rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
3760 	rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
3761 
3762 	/* Default: XO=20MHz , SDM mode */
3763 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3764 	rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
3765 	rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3766 
3767 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3768 	rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
3769 	rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3770 
3771 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3772 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
3773 			  rt2x00dev->default_ant.tx_chain_num != 1);
3774 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3775 
3776 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
3777 	rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
3778 			  rt2x00dev->default_ant.tx_chain_num != 1);
3779 	rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
3780 			  rt2x00dev->default_ant.rx_chain_num != 1);
3781 	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3782 
3783 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 42);
3784 	rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
3785 			  rt2x00dev->default_ant.tx_chain_num != 1);
3786 	rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
3787 
3788 	/* RF for DC Cal BW */
3789 	if (conf_is_ht40(conf)) {
3790 		rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
3791 		rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
3792 		rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
3793 		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
3794 		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
3795 	} else {
3796 		rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
3797 		rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
3798 		rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
3799 		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
3800 		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
3801 	}
3802 
3803 	if (conf_is_ht40(conf)) {
3804 		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
3805 		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
3806 	} else {
3807 		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
3808 		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
3809 	}
3810 
3811 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
3812 	rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
3813 			  conf_is_ht40(conf) && (rf->channel == 11));
3814 	rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
3815 
3816 	if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
3817 		if (conf_is_ht40(conf)) {
3818 			rx_agc_fc = drv_data->rx_calibration_bw40;
3819 			tx_agc_fc = drv_data->tx_calibration_bw40;
3820 		} else {
3821 			rx_agc_fc = drv_data->rx_calibration_bw20;
3822 			tx_agc_fc = drv_data->tx_calibration_bw20;
3823 		}
3824 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
3825 		rfcsr &= (~0x3F);
3826 		rfcsr |= rx_agc_fc;
3827 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
3828 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
3829 		rfcsr &= (~0x3F);
3830 		rfcsr |= rx_agc_fc;
3831 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
3832 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6);
3833 		rfcsr &= (~0x3F);
3834 		rfcsr |= rx_agc_fc;
3835 		rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
3836 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7);
3837 		rfcsr &= (~0x3F);
3838 		rfcsr |= rx_agc_fc;
3839 		rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
3840 
3841 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
3842 		rfcsr &= (~0x3F);
3843 		rfcsr |= tx_agc_fc;
3844 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
3845 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
3846 		rfcsr &= (~0x3F);
3847 		rfcsr |= tx_agc_fc;
3848 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
3849 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58);
3850 		rfcsr &= (~0x3F);
3851 		rfcsr |= tx_agc_fc;
3852 		rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
3853 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59);
3854 		rfcsr &= (~0x3F);
3855 		rfcsr |= tx_agc_fc;
3856 		rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
3857 	}
3858 
3859 	if (conf_is_ht40(conf)) {
3860 		rt2800_bbp_glrt_write(rt2x00dev, 141, 0x10);
3861 		rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2f);
3862 	} else {
3863 		rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1a);
3864 		rt2800_bbp_glrt_write(rt2x00dev, 157, 0x40);
3865 	}
3866 }
3867 
3868 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
3869 			      struct ieee80211_channel *chan,
3870 			      int power_level) {
3871 	u16 eeprom, target_power, max_power;
3872 	u32 mac_sys_ctrl;
3873 	u32 reg;
3874 	u8 bbp;
3875 
3876 	/* hardware unit is 0.5dBm, limited to 23.5dBm */
3877 	power_level *= 2;
3878 	if (power_level > 0x2f)
3879 		power_level = 0x2f;
3880 
3881 	max_power = chan->max_power * 2;
3882 	if (max_power > 0x2f)
3883 		max_power = 0x2f;
3884 
3885 	reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0);
3886 	rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, power_level);
3887 	rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, power_level);
3888 	rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, max_power);
3889 	rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, max_power);
3890 
3891 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
3892 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
3893 		/* init base power by eeprom target power */
3894 		target_power = rt2800_eeprom_read(rt2x00dev,
3895 						  EEPROM_TXPOWER_INIT);
3896 		rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, target_power);
3897 		rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, target_power);
3898 	}
3899 	rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
3900 
3901 	reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
3902 	rt2x00_set_field32(&reg, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
3903 	rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
3904 
3905 	/* Save MAC SYS CTRL registers */
3906 	mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
3907 	/* Disable Tx/Rx */
3908 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
3909 	/* Check MAC Tx/Rx idle */
3910 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
3911 		rt2x00_warn(rt2x00dev, "RF busy while configuring ALC\n");
3912 
3913 	if (chan->center_freq > 2457) {
3914 		bbp = rt2800_bbp_read(rt2x00dev, 30);
3915 		bbp = 0x40;
3916 		rt2800_bbp_write(rt2x00dev, 30, bbp);
3917 		rt2800_rfcsr_write(rt2x00dev, 39, 0);
3918 		if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3919 			rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
3920 		else
3921 			rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
3922 	} else {
3923 		bbp = rt2800_bbp_read(rt2x00dev, 30);
3924 		bbp = 0x1f;
3925 		rt2800_bbp_write(rt2x00dev, 30, bbp);
3926 		rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
3927 		if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3928 			rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
3929 		else
3930 			rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
3931 	}
3932 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
3933 
3934 	rt2800_vco_calibration(rt2x00dev);
3935 }
3936 
3937 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3938 					   const unsigned int word,
3939 					   const u8 value)
3940 {
3941 	u8 chain, reg;
3942 
3943 	for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3944 		reg = rt2800_bbp_read(rt2x00dev, 27);
3945 		rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
3946 		rt2800_bbp_write(rt2x00dev, 27, reg);
3947 
3948 		rt2800_bbp_write(rt2x00dev, word, value);
3949 	}
3950 }
3951 
3952 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3953 {
3954 	u8 cal;
3955 
3956 	/* TX0 IQ Gain */
3957 	rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3958 	if (channel <= 14)
3959 		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3960 	else if (channel >= 36 && channel <= 64)
3961 		cal = rt2x00_eeprom_byte(rt2x00dev,
3962 					 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3963 	else if (channel >= 100 && channel <= 138)
3964 		cal = rt2x00_eeprom_byte(rt2x00dev,
3965 					 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3966 	else if (channel >= 140 && channel <= 165)
3967 		cal = rt2x00_eeprom_byte(rt2x00dev,
3968 					 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3969 	else
3970 		cal = 0;
3971 	rt2800_bbp_write(rt2x00dev, 159, cal);
3972 
3973 	/* TX0 IQ Phase */
3974 	rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3975 	if (channel <= 14)
3976 		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3977 	else if (channel >= 36 && channel <= 64)
3978 		cal = rt2x00_eeprom_byte(rt2x00dev,
3979 					 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3980 	else if (channel >= 100 && channel <= 138)
3981 		cal = rt2x00_eeprom_byte(rt2x00dev,
3982 					 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3983 	else if (channel >= 140 && channel <= 165)
3984 		cal = rt2x00_eeprom_byte(rt2x00dev,
3985 					 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3986 	else
3987 		cal = 0;
3988 	rt2800_bbp_write(rt2x00dev, 159, cal);
3989 
3990 	/* TX1 IQ Gain */
3991 	rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3992 	if (channel <= 14)
3993 		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3994 	else if (channel >= 36 && channel <= 64)
3995 		cal = rt2x00_eeprom_byte(rt2x00dev,
3996 					 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3997 	else if (channel >= 100 && channel <= 138)
3998 		cal = rt2x00_eeprom_byte(rt2x00dev,
3999 					 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
4000 	else if (channel >= 140 && channel <= 165)
4001 		cal = rt2x00_eeprom_byte(rt2x00dev,
4002 					 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
4003 	else
4004 		cal = 0;
4005 	rt2800_bbp_write(rt2x00dev, 159, cal);
4006 
4007 	/* TX1 IQ Phase */
4008 	rt2800_bbp_write(rt2x00dev, 158, 0x4b);
4009 	if (channel <= 14)
4010 		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
4011 	else if (channel >= 36 && channel <= 64)
4012 		cal = rt2x00_eeprom_byte(rt2x00dev,
4013 					 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
4014 	else if (channel >= 100 && channel <= 138)
4015 		cal = rt2x00_eeprom_byte(rt2x00dev,
4016 					 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
4017 	else if (channel >= 140 && channel <= 165)
4018 		cal = rt2x00_eeprom_byte(rt2x00dev,
4019 					 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
4020 	else
4021 		cal = 0;
4022 	rt2800_bbp_write(rt2x00dev, 159, cal);
4023 
4024 	/* FIXME: possible RX0, RX1 callibration ? */
4025 
4026 	/* RF IQ compensation control */
4027 	rt2800_bbp_write(rt2x00dev, 158, 0x04);
4028 	cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
4029 	rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
4030 
4031 	/* RF IQ imbalance compensation control */
4032 	rt2800_bbp_write(rt2x00dev, 158, 0x03);
4033 	cal = rt2x00_eeprom_byte(rt2x00dev,
4034 				 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
4035 	rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
4036 }
4037 
4038 static s8 rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
4039 				  unsigned int channel,
4040 				  s8 txpower)
4041 {
4042 	if (rt2x00_rt(rt2x00dev, RT3593) ||
4043 	    rt2x00_rt(rt2x00dev, RT3883))
4044 		txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
4045 
4046 	if (channel <= 14)
4047 		return clamp_t(s8, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
4048 
4049 	if (rt2x00_rt(rt2x00dev, RT3593) ||
4050 	    rt2x00_rt(rt2x00dev, RT3883))
4051 		return clamp_t(s8, txpower, MIN_A_TXPOWER_3593,
4052 			       MAX_A_TXPOWER_3593);
4053 	else
4054 		return clamp_t(s8, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
4055 }
4056 
4057 static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev,
4058 			      struct rf_channel *rf)
4059 {
4060 	u8 bbp;
4061 
4062 	bbp = (rf->channel > 14) ? 0x48 : 0x38;
4063 	rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
4064 
4065 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
4066 
4067 	if (rf->channel <= 14) {
4068 		rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4069 	} else {
4070 		/* Disable CCK packet detection */
4071 		rt2800_bbp_write(rt2x00dev, 70, 0x00);
4072 	}
4073 
4074 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
4075 
4076 	if (rf->channel > 14) {
4077 		rt2800_bbp_write(rt2x00dev, 62, 0x1d);
4078 		rt2800_bbp_write(rt2x00dev, 63, 0x1d);
4079 		rt2800_bbp_write(rt2x00dev, 64, 0x1d);
4080 	} else {
4081 		rt2800_bbp_write(rt2x00dev, 62, 0x2d);
4082 		rt2800_bbp_write(rt2x00dev, 63, 0x2d);
4083 		rt2800_bbp_write(rt2x00dev, 64, 0x2d);
4084 	}
4085 }
4086 
4087 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
4088 				  struct ieee80211_conf *conf,
4089 				  struct rf_channel *rf,
4090 				  struct channel_info *info)
4091 {
4092 	u32 reg;
4093 	u32 tx_pin;
4094 	u8 bbp, rfcsr;
4095 
4096 	info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4097 						     info->default_power1);
4098 	info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4099 						     info->default_power2);
4100 	if (rt2x00dev->default_ant.tx_chain_num > 2)
4101 		info->default_power3 =
4102 			rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4103 					      info->default_power3);
4104 
4105 	switch (rt2x00dev->chip.rt) {
4106 	case RT3883:
4107 		rt3883_bbp_adjust(rt2x00dev, rf);
4108 		break;
4109 	}
4110 
4111 	switch (rt2x00dev->chip.rf) {
4112 	case RF2020:
4113 	case RF3020:
4114 	case RF3021:
4115 	case RF3022:
4116 	case RF3320:
4117 		rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
4118 		break;
4119 	case RF3052:
4120 		rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
4121 		break;
4122 	case RF3053:
4123 		rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
4124 		break;
4125 	case RF3290:
4126 		rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
4127 		break;
4128 	case RF3322:
4129 		rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
4130 		break;
4131 	case RF3853:
4132 		rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info);
4133 		break;
4134 	case RF3070:
4135 	case RF5350:
4136 	case RF5360:
4137 	case RF5362:
4138 	case RF5370:
4139 	case RF5372:
4140 	case RF5390:
4141 	case RF5392:
4142 		rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
4143 		break;
4144 	case RF5592:
4145 		rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
4146 		break;
4147 	case RF7620:
4148 		rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
4149 		break;
4150 	default:
4151 		rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
4152 	}
4153 
4154 	if (rt2x00_rf(rt2x00dev, RF3070) ||
4155 	    rt2x00_rf(rt2x00dev, RF3290) ||
4156 	    rt2x00_rf(rt2x00dev, RF3322) ||
4157 	    rt2x00_rf(rt2x00dev, RF5350) ||
4158 	    rt2x00_rf(rt2x00dev, RF5360) ||
4159 	    rt2x00_rf(rt2x00dev, RF5362) ||
4160 	    rt2x00_rf(rt2x00dev, RF5370) ||
4161 	    rt2x00_rf(rt2x00dev, RF5372) ||
4162 	    rt2x00_rf(rt2x00dev, RF5390) ||
4163 	    rt2x00_rf(rt2x00dev, RF5392)) {
4164 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
4165 		if (rt2x00_rf(rt2x00dev, RF3322)) {
4166 			rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M,
4167 					  conf_is_ht40(conf));
4168 			rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M,
4169 					  conf_is_ht40(conf));
4170 		} else {
4171 			rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M,
4172 					  conf_is_ht40(conf));
4173 			rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M,
4174 					  conf_is_ht40(conf));
4175 		}
4176 		rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4177 
4178 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
4179 		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4180 		rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4181 	}
4182 
4183 	/*
4184 	 * Change BBP settings
4185 	 */
4186 
4187 	if (rt2x00_rt(rt2x00dev, RT3352)) {
4188 		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4189 		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4190 		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4191 
4192 		rt2800_bbp_write(rt2x00dev, 27, 0x0);
4193 		rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4194 		rt2800_bbp_write(rt2x00dev, 27, 0x20);
4195 		rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4196 		rt2800_bbp_write(rt2x00dev, 86, 0x38);
4197 		rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4198 	} else if (rt2x00_rt(rt2x00dev, RT3593)) {
4199 		if (rf->channel > 14) {
4200 			/* Disable CCK Packet detection on 5GHz */
4201 			rt2800_bbp_write(rt2x00dev, 70, 0x00);
4202 		} else {
4203 			rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4204 		}
4205 
4206 		if (conf_is_ht40(conf))
4207 			rt2800_bbp_write(rt2x00dev, 105, 0x04);
4208 		else
4209 			rt2800_bbp_write(rt2x00dev, 105, 0x34);
4210 
4211 		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4212 		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4213 		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4214 		rt2800_bbp_write(rt2x00dev, 77, 0x98);
4215 	} else if (rt2x00_rt(rt2x00dev, RT3883)) {
4216 		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4217 		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4218 		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4219 
4220 		if (rt2x00dev->default_ant.rx_chain_num > 1)
4221 			rt2800_bbp_write(rt2x00dev, 86, 0x46);
4222 		else
4223 			rt2800_bbp_write(rt2x00dev, 86, 0);
4224 	} else {
4225 		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4226 		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4227 		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4228 		if (rt2x00_rt(rt2x00dev, RT6352))
4229 			rt2800_bbp_write(rt2x00dev, 86, 0x38);
4230 		else
4231 			rt2800_bbp_write(rt2x00dev, 86, 0);
4232 	}
4233 
4234 	if (rf->channel <= 14) {
4235 		if (!rt2x00_rt(rt2x00dev, RT5390) &&
4236 		    !rt2x00_rt(rt2x00dev, RT5392) &&
4237 		    !rt2x00_rt(rt2x00dev, RT6352)) {
4238 			if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4239 				rt2800_bbp_write(rt2x00dev, 82, 0x62);
4240 				rt2800_bbp_write(rt2x00dev, 82, 0x62);
4241 				rt2800_bbp_write(rt2x00dev, 75, 0x46);
4242 			} else {
4243 				if (rt2x00_rt(rt2x00dev, RT3593))
4244 					rt2800_bbp_write(rt2x00dev, 82, 0x62);
4245 				else
4246 					rt2800_bbp_write(rt2x00dev, 82, 0x84);
4247 				rt2800_bbp_write(rt2x00dev, 75, 0x50);
4248 			}
4249 			if (rt2x00_rt(rt2x00dev, RT3593) ||
4250 			    rt2x00_rt(rt2x00dev, RT3883))
4251 				rt2800_bbp_write(rt2x00dev, 83, 0x8a);
4252 		}
4253 
4254 	} else {
4255 		if (rt2x00_rt(rt2x00dev, RT3572))
4256 			rt2800_bbp_write(rt2x00dev, 82, 0x94);
4257 		else if (rt2x00_rt(rt2x00dev, RT3593) ||
4258 			 rt2x00_rt(rt2x00dev, RT3883))
4259 			rt2800_bbp_write(rt2x00dev, 82, 0x82);
4260 		else if (!rt2x00_rt(rt2x00dev, RT6352))
4261 			rt2800_bbp_write(rt2x00dev, 82, 0xf2);
4262 
4263 		if (rt2x00_rt(rt2x00dev, RT3593) ||
4264 		    rt2x00_rt(rt2x00dev, RT3883))
4265 			rt2800_bbp_write(rt2x00dev, 83, 0x9a);
4266 
4267 		if (rt2x00_has_cap_external_lna_a(rt2x00dev))
4268 			rt2800_bbp_write(rt2x00dev, 75, 0x46);
4269 		else
4270 			rt2800_bbp_write(rt2x00dev, 75, 0x50);
4271 	}
4272 
4273 	reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG);
4274 	rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
4275 	rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
4276 	rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
4277 	rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
4278 
4279 	if (rt2x00_rt(rt2x00dev, RT3572))
4280 		rt2800_rfcsr_write(rt2x00dev, 8, 0);
4281 
4282 	if (rt2x00_rt(rt2x00dev, RT6352)) {
4283 		tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
4284 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1);
4285 	} else {
4286 		tx_pin = 0;
4287 	}
4288 
4289 	switch (rt2x00dev->default_ant.tx_chain_num) {
4290 	case 3:
4291 		/* Turn on tertiary PAs */
4292 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
4293 				   rf->channel > 14);
4294 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
4295 				   rf->channel <= 14);
4296 		fallthrough;
4297 	case 2:
4298 		/* Turn on secondary PAs */
4299 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
4300 				   rf->channel > 14);
4301 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
4302 				   rf->channel <= 14);
4303 		fallthrough;
4304 	case 1:
4305 		/* Turn on primary PAs */
4306 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
4307 				   rf->channel > 14);
4308 		if (rt2x00_has_cap_bt_coexist(rt2x00dev))
4309 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4310 		else
4311 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
4312 					   rf->channel <= 14);
4313 		break;
4314 	}
4315 
4316 	switch (rt2x00dev->default_ant.rx_chain_num) {
4317 	case 3:
4318 		/* Turn on tertiary LNAs */
4319 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
4320 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
4321 		fallthrough;
4322 	case 2:
4323 		/* Turn on secondary LNAs */
4324 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
4325 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
4326 		fallthrough;
4327 	case 1:
4328 		/* Turn on primary LNAs */
4329 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
4330 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
4331 		break;
4332 	}
4333 
4334 	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
4335 	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
4336 
4337 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4338 
4339 	if (rt2x00_rt(rt2x00dev, RT3572)) {
4340 		rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
4341 
4342 		/* AGC init */
4343 		if (rf->channel <= 14)
4344 			reg = 0x1c + (2 * rt2x00dev->lna_gain);
4345 		else
4346 			reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4347 
4348 		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4349 	}
4350 
4351 	if (rt2x00_rt(rt2x00dev, RT3593)) {
4352 		reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
4353 
4354 		/* Band selection */
4355 		if (rt2x00_is_usb(rt2x00dev) ||
4356 		    rt2x00_is_pcie(rt2x00dev)) {
4357 			/* GPIO #8 controls all paths */
4358 			rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
4359 			if (rf->channel <= 14)
4360 				rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
4361 			else
4362 				rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
4363 		}
4364 
4365 		/* LNA PE control. */
4366 		if (rt2x00_is_usb(rt2x00dev)) {
4367 			/* GPIO #4 controls PE0 and PE1,
4368 			 * GPIO #7 controls PE2
4369 			 */
4370 			rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
4371 			rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
4372 
4373 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
4374 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
4375 		} else if (rt2x00_is_pcie(rt2x00dev)) {
4376 			/* GPIO #4 controls PE0, PE1 and PE2 */
4377 			rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
4378 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
4379 		}
4380 
4381 		rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4382 
4383 		/* AGC init */
4384 		if (rf->channel <= 14)
4385 			reg = 0x1c + 2 * rt2x00dev->lna_gain;
4386 		else
4387 			reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4388 
4389 		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4390 
4391 		usleep_range(1000, 1500);
4392 	}
4393 
4394 	if (rt2x00_rt(rt2x00dev, RT3883)) {
4395 		if (!conf_is_ht40(conf))
4396 			rt2800_bbp_write(rt2x00dev, 105, 0x34);
4397 		else
4398 			rt2800_bbp_write(rt2x00dev, 105, 0x04);
4399 
4400 		/* AGC init */
4401 		if (rf->channel <= 14)
4402 			reg = 0x2e + rt2x00dev->lna_gain;
4403 		else
4404 			reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3);
4405 
4406 		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4407 
4408 		usleep_range(1000, 1500);
4409 	}
4410 
4411 	if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
4412 		reg = 0x10;
4413 		if (!conf_is_ht40(conf)) {
4414 			if (rt2x00_rt(rt2x00dev, RT6352) &&
4415 			    rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4416 				reg |= 0x5;
4417 			} else {
4418 				reg |= 0xa;
4419 			}
4420 		}
4421 		rt2800_bbp_write(rt2x00dev, 195, 141);
4422 		rt2800_bbp_write(rt2x00dev, 196, reg);
4423 
4424 		/* AGC init.
4425 		 * Despite the vendor driver using different values here for
4426 		 * RT6352 chip, we use 0x1c for now. This may have to be changed
4427 		 * once TSSI got implemented.
4428 		 */
4429 		reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain;
4430 		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4431 
4432 		if (rt2x00_rt(rt2x00dev, RT5592))
4433 			rt2800_iq_calibrate(rt2x00dev, rf->channel);
4434 	}
4435 
4436 	if (rt2x00_rt(rt2x00dev, RT6352)) {
4437 		if (test_bit(CAPABILITY_EXTERNAL_PA_TX0,
4438 			     &rt2x00dev->cap_flags)) {
4439 			reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
4440 			reg |= 0x00000101;
4441 			rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
4442 
4443 			reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
4444 			reg |= 0x00000101;
4445 			rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
4446 
4447 			rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);
4448 			rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);
4449 			rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);
4450 			rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
4451 			rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8);
4452 			rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4);
4453 			rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);
4454 			rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
4455 			rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8);
4456 			rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4);
4457 			rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);
4458 			rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
4459 			rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8);
4460 			rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4);
4461 			rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);
4462 			rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);
4463 
4464 			rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
4465 					      0x36303636);
4466 			rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
4467 					      0x6C6C6B6C);
4468 			rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
4469 					      0x6C6C6B6C);
4470 		}
4471 	}
4472 
4473 	bbp = rt2800_bbp_read(rt2x00dev, 4);
4474 	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
4475 	rt2800_bbp_write(rt2x00dev, 4, bbp);
4476 
4477 	bbp = rt2800_bbp_read(rt2x00dev, 3);
4478 	rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
4479 	rt2800_bbp_write(rt2x00dev, 3, bbp);
4480 
4481 	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4482 		if (conf_is_ht40(conf)) {
4483 			rt2800_bbp_write(rt2x00dev, 69, 0x1a);
4484 			rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4485 			rt2800_bbp_write(rt2x00dev, 73, 0x16);
4486 		} else {
4487 			rt2800_bbp_write(rt2x00dev, 69, 0x16);
4488 			rt2800_bbp_write(rt2x00dev, 70, 0x08);
4489 			rt2800_bbp_write(rt2x00dev, 73, 0x11);
4490 		}
4491 	}
4492 
4493 	usleep_range(1000, 1500);
4494 
4495 	/*
4496 	 * Clear channel statistic counters
4497 	 */
4498 	reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
4499 	reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
4500 	reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
4501 
4502 	/*
4503 	 * Clear update flag
4504 	 */
4505 	if (rt2x00_rt(rt2x00dev, RT3352) ||
4506 	    rt2x00_rt(rt2x00dev, RT5350)) {
4507 		bbp = rt2800_bbp_read(rt2x00dev, 49);
4508 		rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
4509 		rt2800_bbp_write(rt2x00dev, 49, bbp);
4510 	}
4511 }
4512 
4513 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
4514 {
4515 	u8 tssi_bounds[9];
4516 	u8 current_tssi;
4517 	u16 eeprom;
4518 	u8 step;
4519 	int i;
4520 
4521 	/*
4522 	 * First check if temperature compensation is supported.
4523 	 */
4524 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
4525 	if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
4526 		return 0;
4527 
4528 	/*
4529 	 * Read TSSI boundaries for temperature compensation from
4530 	 * the EEPROM.
4531 	 *
4532 	 * Array idx               0    1    2    3    4    5    6    7    8
4533 	 * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
4534 	 * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
4535 	 */
4536 	if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
4537 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1);
4538 		tssi_bounds[0] = rt2x00_get_field16(eeprom,
4539 					EEPROM_TSSI_BOUND_BG1_MINUS4);
4540 		tssi_bounds[1] = rt2x00_get_field16(eeprom,
4541 					EEPROM_TSSI_BOUND_BG1_MINUS3);
4542 
4543 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2);
4544 		tssi_bounds[2] = rt2x00_get_field16(eeprom,
4545 					EEPROM_TSSI_BOUND_BG2_MINUS2);
4546 		tssi_bounds[3] = rt2x00_get_field16(eeprom,
4547 					EEPROM_TSSI_BOUND_BG2_MINUS1);
4548 
4549 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3);
4550 		tssi_bounds[4] = rt2x00_get_field16(eeprom,
4551 					EEPROM_TSSI_BOUND_BG3_REF);
4552 		tssi_bounds[5] = rt2x00_get_field16(eeprom,
4553 					EEPROM_TSSI_BOUND_BG3_PLUS1);
4554 
4555 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4);
4556 		tssi_bounds[6] = rt2x00_get_field16(eeprom,
4557 					EEPROM_TSSI_BOUND_BG4_PLUS2);
4558 		tssi_bounds[7] = rt2x00_get_field16(eeprom,
4559 					EEPROM_TSSI_BOUND_BG4_PLUS3);
4560 
4561 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5);
4562 		tssi_bounds[8] = rt2x00_get_field16(eeprom,
4563 					EEPROM_TSSI_BOUND_BG5_PLUS4);
4564 
4565 		step = rt2x00_get_field16(eeprom,
4566 					  EEPROM_TSSI_BOUND_BG5_AGC_STEP);
4567 	} else {
4568 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1);
4569 		tssi_bounds[0] = rt2x00_get_field16(eeprom,
4570 					EEPROM_TSSI_BOUND_A1_MINUS4);
4571 		tssi_bounds[1] = rt2x00_get_field16(eeprom,
4572 					EEPROM_TSSI_BOUND_A1_MINUS3);
4573 
4574 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2);
4575 		tssi_bounds[2] = rt2x00_get_field16(eeprom,
4576 					EEPROM_TSSI_BOUND_A2_MINUS2);
4577 		tssi_bounds[3] = rt2x00_get_field16(eeprom,
4578 					EEPROM_TSSI_BOUND_A2_MINUS1);
4579 
4580 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3);
4581 		tssi_bounds[4] = rt2x00_get_field16(eeprom,
4582 					EEPROM_TSSI_BOUND_A3_REF);
4583 		tssi_bounds[5] = rt2x00_get_field16(eeprom,
4584 					EEPROM_TSSI_BOUND_A3_PLUS1);
4585 
4586 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4);
4587 		tssi_bounds[6] = rt2x00_get_field16(eeprom,
4588 					EEPROM_TSSI_BOUND_A4_PLUS2);
4589 		tssi_bounds[7] = rt2x00_get_field16(eeprom,
4590 					EEPROM_TSSI_BOUND_A4_PLUS3);
4591 
4592 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5);
4593 		tssi_bounds[8] = rt2x00_get_field16(eeprom,
4594 					EEPROM_TSSI_BOUND_A5_PLUS4);
4595 
4596 		step = rt2x00_get_field16(eeprom,
4597 					  EEPROM_TSSI_BOUND_A5_AGC_STEP);
4598 	}
4599 
4600 	/*
4601 	 * Check if temperature compensation is supported.
4602 	 */
4603 	if (tssi_bounds[4] == 0xff || step == 0xff)
4604 		return 0;
4605 
4606 	/*
4607 	 * Read current TSSI (BBP 49).
4608 	 */
4609 	current_tssi = rt2800_bbp_read(rt2x00dev, 49);
4610 
4611 	/*
4612 	 * Compare TSSI value (BBP49) with the compensation boundaries
4613 	 * from the EEPROM and increase or decrease tx power.
4614 	 */
4615 	for (i = 0; i <= 3; i++) {
4616 		if (current_tssi > tssi_bounds[i])
4617 			break;
4618 	}
4619 
4620 	if (i == 4) {
4621 		for (i = 8; i >= 5; i--) {
4622 			if (current_tssi < tssi_bounds[i])
4623 				break;
4624 		}
4625 	}
4626 
4627 	return (i - 4) * step;
4628 }
4629 
4630 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
4631 				      enum nl80211_band band)
4632 {
4633 	u16 eeprom;
4634 	u8 comp_en;
4635 	u8 comp_type;
4636 	int comp_value = 0;
4637 
4638 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA);
4639 
4640 	/*
4641 	 * HT40 compensation not required.
4642 	 */
4643 	if (eeprom == 0xffff ||
4644 	    !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4645 		return 0;
4646 
4647 	if (band == NL80211_BAND_2GHZ) {
4648 		comp_en = rt2x00_get_field16(eeprom,
4649 				 EEPROM_TXPOWER_DELTA_ENABLE_2G);
4650 		if (comp_en) {
4651 			comp_type = rt2x00_get_field16(eeprom,
4652 					   EEPROM_TXPOWER_DELTA_TYPE_2G);
4653 			comp_value = rt2x00_get_field16(eeprom,
4654 					    EEPROM_TXPOWER_DELTA_VALUE_2G);
4655 			if (!comp_type)
4656 				comp_value = -comp_value;
4657 		}
4658 	} else {
4659 		comp_en = rt2x00_get_field16(eeprom,
4660 				 EEPROM_TXPOWER_DELTA_ENABLE_5G);
4661 		if (comp_en) {
4662 			comp_type = rt2x00_get_field16(eeprom,
4663 					   EEPROM_TXPOWER_DELTA_TYPE_5G);
4664 			comp_value = rt2x00_get_field16(eeprom,
4665 					    EEPROM_TXPOWER_DELTA_VALUE_5G);
4666 			if (!comp_type)
4667 				comp_value = -comp_value;
4668 		}
4669 	}
4670 
4671 	return comp_value;
4672 }
4673 
4674 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
4675 					int power_level, int max_power)
4676 {
4677 	int delta;
4678 
4679 	if (rt2x00_has_cap_power_limit(rt2x00dev))
4680 		return 0;
4681 
4682 	/*
4683 	 * XXX: We don't know the maximum transmit power of our hardware since
4684 	 * the EEPROM doesn't expose it. We only know that we are calibrated
4685 	 * to 100% tx power.
4686 	 *
4687 	 * Hence, we assume the regulatory limit that cfg80211 calulated for
4688 	 * the current channel is our maximum and if we are requested to lower
4689 	 * the value we just reduce our tx power accordingly.
4690 	 */
4691 	delta = power_level - max_power;
4692 	return min(delta, 0);
4693 }
4694 
4695 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
4696 				   enum nl80211_band band, int power_level,
4697 				   u8 txpower, int delta)
4698 {
4699 	u16 eeprom;
4700 	u8 criterion;
4701 	u8 eirp_txpower;
4702 	u8 eirp_txpower_criterion;
4703 	u8 reg_limit;
4704 
4705 	if (rt2x00_rt(rt2x00dev, RT3593))
4706 		return min_t(u8, txpower, 0xc);
4707 
4708 	if (rt2x00_rt(rt2x00dev, RT3883))
4709 		return min_t(u8, txpower, 0xf);
4710 
4711 	if (rt2x00_has_cap_power_limit(rt2x00dev)) {
4712 		/*
4713 		 * Check if eirp txpower exceed txpower_limit.
4714 		 * We use OFDM 6M as criterion and its eirp txpower
4715 		 * is stored at EEPROM_EIRP_MAX_TX_POWER.
4716 		 * .11b data rate need add additional 4dbm
4717 		 * when calculating eirp txpower.
4718 		 */
4719 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4720 						       EEPROM_TXPOWER_BYRATE,
4721 						       1);
4722 		criterion = rt2x00_get_field16(eeprom,
4723 					       EEPROM_TXPOWER_BYRATE_RATE0);
4724 
4725 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
4726 
4727 		if (band == NL80211_BAND_2GHZ)
4728 			eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4729 						 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
4730 		else
4731 			eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4732 						 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
4733 
4734 		eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
4735 			       (is_rate_b ? 4 : 0) + delta;
4736 
4737 		reg_limit = (eirp_txpower > power_level) ?
4738 					(eirp_txpower - power_level) : 0;
4739 	} else
4740 		reg_limit = 0;
4741 
4742 	txpower = max(0, txpower + delta - reg_limit);
4743 	return min_t(u8, txpower, 0xc);
4744 }
4745 
4746 
4747 enum {
4748 	TX_PWR_CFG_0_IDX,
4749 	TX_PWR_CFG_1_IDX,
4750 	TX_PWR_CFG_2_IDX,
4751 	TX_PWR_CFG_3_IDX,
4752 	TX_PWR_CFG_4_IDX,
4753 	TX_PWR_CFG_5_IDX,
4754 	TX_PWR_CFG_6_IDX,
4755 	TX_PWR_CFG_7_IDX,
4756 	TX_PWR_CFG_8_IDX,
4757 	TX_PWR_CFG_9_IDX,
4758 	TX_PWR_CFG_0_EXT_IDX,
4759 	TX_PWR_CFG_1_EXT_IDX,
4760 	TX_PWR_CFG_2_EXT_IDX,
4761 	TX_PWR_CFG_3_EXT_IDX,
4762 	TX_PWR_CFG_4_EXT_IDX,
4763 	TX_PWR_CFG_IDX_COUNT,
4764 };
4765 
4766 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
4767 					 struct ieee80211_channel *chan,
4768 					 int power_level)
4769 {
4770 	u8 txpower;
4771 	u16 eeprom;
4772 	u32 regs[TX_PWR_CFG_IDX_COUNT];
4773 	unsigned int offset;
4774 	enum nl80211_band band = chan->band;
4775 	int delta;
4776 	int i;
4777 
4778 	memset(regs, '\0', sizeof(regs));
4779 
4780 	/* TODO: adapt TX power reduction from the rt28xx code */
4781 
4782 	/* calculate temperature compensation delta */
4783 	delta = rt2800_get_gain_calibration_delta(rt2x00dev);
4784 
4785 	if (band == NL80211_BAND_5GHZ)
4786 		offset = 16;
4787 	else
4788 		offset = 0;
4789 
4790 	if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4791 		offset += 8;
4792 
4793 	/* read the next four txpower values */
4794 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4795 					       offset);
4796 
4797 	/* CCK 1MBS,2MBS */
4798 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4799 	txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4800 					    txpower, delta);
4801 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4802 			   TX_PWR_CFG_0_CCK1_CH0, txpower);
4803 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4804 			   TX_PWR_CFG_0_CCK1_CH1, txpower);
4805 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4806 			   TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
4807 
4808 	/* CCK 5.5MBS,11MBS */
4809 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4810 	txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4811 					    txpower, delta);
4812 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4813 			   TX_PWR_CFG_0_CCK5_CH0, txpower);
4814 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4815 			   TX_PWR_CFG_0_CCK5_CH1, txpower);
4816 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4817 			   TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
4818 
4819 	/* OFDM 6MBS,9MBS */
4820 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4821 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4822 					    txpower, delta);
4823 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4824 			   TX_PWR_CFG_0_OFDM6_CH0, txpower);
4825 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4826 			   TX_PWR_CFG_0_OFDM6_CH1, txpower);
4827 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4828 			   TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
4829 
4830 	/* OFDM 12MBS,18MBS */
4831 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4832 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4833 					    txpower, delta);
4834 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4835 			   TX_PWR_CFG_0_OFDM12_CH0, txpower);
4836 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4837 			   TX_PWR_CFG_0_OFDM12_CH1, txpower);
4838 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4839 			   TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
4840 
4841 	/* read the next four txpower values */
4842 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4843 					       offset + 1);
4844 
4845 	/* OFDM 24MBS,36MBS */
4846 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4847 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4848 					    txpower, delta);
4849 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4850 			   TX_PWR_CFG_1_OFDM24_CH0, txpower);
4851 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4852 			   TX_PWR_CFG_1_OFDM24_CH1, txpower);
4853 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4854 			   TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
4855 
4856 	/* OFDM 48MBS */
4857 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4858 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4859 					    txpower, delta);
4860 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4861 			   TX_PWR_CFG_1_OFDM48_CH0, txpower);
4862 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4863 			   TX_PWR_CFG_1_OFDM48_CH1, txpower);
4864 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4865 			   TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
4866 
4867 	/* OFDM 54MBS */
4868 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4869 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4870 					    txpower, delta);
4871 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4872 			   TX_PWR_CFG_7_OFDM54_CH0, txpower);
4873 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4874 			   TX_PWR_CFG_7_OFDM54_CH1, txpower);
4875 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4876 			   TX_PWR_CFG_7_OFDM54_CH2, txpower);
4877 
4878 	/* read the next four txpower values */
4879 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4880 					       offset + 2);
4881 
4882 	/* MCS 0,1 */
4883 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4884 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4885 					    txpower, delta);
4886 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4887 			   TX_PWR_CFG_1_MCS0_CH0, txpower);
4888 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4889 			   TX_PWR_CFG_1_MCS0_CH1, txpower);
4890 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4891 			   TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
4892 
4893 	/* MCS 2,3 */
4894 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4895 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4896 					    txpower, delta);
4897 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4898 			   TX_PWR_CFG_1_MCS2_CH0, txpower);
4899 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4900 			   TX_PWR_CFG_1_MCS2_CH1, txpower);
4901 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4902 			   TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
4903 
4904 	/* MCS 4,5 */
4905 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4906 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4907 					    txpower, delta);
4908 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4909 			   TX_PWR_CFG_2_MCS4_CH0, txpower);
4910 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4911 			   TX_PWR_CFG_2_MCS4_CH1, txpower);
4912 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4913 			   TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
4914 
4915 	/* MCS 6 */
4916 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4917 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4918 					    txpower, delta);
4919 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4920 			   TX_PWR_CFG_2_MCS6_CH0, txpower);
4921 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4922 			   TX_PWR_CFG_2_MCS6_CH1, txpower);
4923 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4924 			   TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
4925 
4926 	/* read the next four txpower values */
4927 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4928 					       offset + 3);
4929 
4930 	/* MCS 7 */
4931 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4932 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4933 					    txpower, delta);
4934 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4935 			   TX_PWR_CFG_7_MCS7_CH0, txpower);
4936 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4937 			   TX_PWR_CFG_7_MCS7_CH1, txpower);
4938 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4939 			   TX_PWR_CFG_7_MCS7_CH2, txpower);
4940 
4941 	/* MCS 8,9 */
4942 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4943 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4944 					    txpower, delta);
4945 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4946 			   TX_PWR_CFG_2_MCS8_CH0, txpower);
4947 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4948 			   TX_PWR_CFG_2_MCS8_CH1, txpower);
4949 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4950 			   TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
4951 
4952 	/* MCS 10,11 */
4953 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4954 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4955 					    txpower, delta);
4956 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4957 			   TX_PWR_CFG_2_MCS10_CH0, txpower);
4958 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4959 			   TX_PWR_CFG_2_MCS10_CH1, txpower);
4960 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4961 			   TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
4962 
4963 	/* MCS 12,13 */
4964 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4965 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4966 					    txpower, delta);
4967 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4968 			   TX_PWR_CFG_3_MCS12_CH0, txpower);
4969 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4970 			   TX_PWR_CFG_3_MCS12_CH1, txpower);
4971 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4972 			   TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
4973 
4974 	/* read the next four txpower values */
4975 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4976 					       offset + 4);
4977 
4978 	/* MCS 14 */
4979 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4980 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4981 					    txpower, delta);
4982 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4983 			   TX_PWR_CFG_3_MCS14_CH0, txpower);
4984 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4985 			   TX_PWR_CFG_3_MCS14_CH1, txpower);
4986 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4987 			   TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
4988 
4989 	/* MCS 15 */
4990 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4991 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4992 					    txpower, delta);
4993 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4994 			   TX_PWR_CFG_8_MCS15_CH0, txpower);
4995 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4996 			   TX_PWR_CFG_8_MCS15_CH1, txpower);
4997 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4998 			   TX_PWR_CFG_8_MCS15_CH2, txpower);
4999 
5000 	/* MCS 16,17 */
5001 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
5002 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5003 					    txpower, delta);
5004 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
5005 			   TX_PWR_CFG_5_MCS16_CH0, txpower);
5006 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
5007 			   TX_PWR_CFG_5_MCS16_CH1, txpower);
5008 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
5009 			   TX_PWR_CFG_5_MCS16_CH2, txpower);
5010 
5011 	/* MCS 18,19 */
5012 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
5013 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5014 					    txpower, delta);
5015 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
5016 			   TX_PWR_CFG_5_MCS18_CH0, txpower);
5017 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
5018 			   TX_PWR_CFG_5_MCS18_CH1, txpower);
5019 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
5020 			   TX_PWR_CFG_5_MCS18_CH2, txpower);
5021 
5022 	/* read the next four txpower values */
5023 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
5024 					       offset + 5);
5025 
5026 	/* MCS 20,21 */
5027 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
5028 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5029 					    txpower, delta);
5030 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
5031 			   TX_PWR_CFG_6_MCS20_CH0, txpower);
5032 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
5033 			   TX_PWR_CFG_6_MCS20_CH1, txpower);
5034 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
5035 			   TX_PWR_CFG_6_MCS20_CH2, txpower);
5036 
5037 	/* MCS 22 */
5038 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
5039 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5040 					    txpower, delta);
5041 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
5042 			   TX_PWR_CFG_6_MCS22_CH0, txpower);
5043 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
5044 			   TX_PWR_CFG_6_MCS22_CH1, txpower);
5045 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
5046 			   TX_PWR_CFG_6_MCS22_CH2, txpower);
5047 
5048 	/* MCS 23 */
5049 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
5050 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5051 					    txpower, delta);
5052 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
5053 			   TX_PWR_CFG_8_MCS23_CH0, txpower);
5054 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
5055 			   TX_PWR_CFG_8_MCS23_CH1, txpower);
5056 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
5057 			   TX_PWR_CFG_8_MCS23_CH2, txpower);
5058 
5059 	/* read the next four txpower values */
5060 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
5061 					       offset + 6);
5062 
5063 	/* STBC, MCS 0,1 */
5064 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
5065 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5066 					    txpower, delta);
5067 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
5068 			   TX_PWR_CFG_3_STBC0_CH0, txpower);
5069 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
5070 			   TX_PWR_CFG_3_STBC0_CH1, txpower);
5071 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
5072 			   TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
5073 
5074 	/* STBC, MCS 2,3 */
5075 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
5076 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5077 					    txpower, delta);
5078 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
5079 			   TX_PWR_CFG_3_STBC2_CH0, txpower);
5080 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
5081 			   TX_PWR_CFG_3_STBC2_CH1, txpower);
5082 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
5083 			   TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
5084 
5085 	/* STBC, MCS 4,5 */
5086 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
5087 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5088 					    txpower, delta);
5089 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
5090 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
5091 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
5092 			   txpower);
5093 
5094 	/* STBC, MCS 6 */
5095 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
5096 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5097 					    txpower, delta);
5098 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
5099 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
5100 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
5101 			   txpower);
5102 
5103 	/* read the next four txpower values */
5104 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
5105 					       offset + 7);
5106 
5107 	/* STBC, MCS 7 */
5108 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
5109 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5110 					    txpower, delta);
5111 	rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
5112 			   TX_PWR_CFG_9_STBC7_CH0, txpower);
5113 	rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
5114 			   TX_PWR_CFG_9_STBC7_CH1, txpower);
5115 	rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
5116 			   TX_PWR_CFG_9_STBC7_CH2, txpower);
5117 
5118 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
5119 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
5120 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
5121 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
5122 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
5123 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
5124 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
5125 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
5126 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
5127 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
5128 
5129 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
5130 			      regs[TX_PWR_CFG_0_EXT_IDX]);
5131 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
5132 			      regs[TX_PWR_CFG_1_EXT_IDX]);
5133 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
5134 			      regs[TX_PWR_CFG_2_EXT_IDX]);
5135 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
5136 			      regs[TX_PWR_CFG_3_EXT_IDX]);
5137 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
5138 			      regs[TX_PWR_CFG_4_EXT_IDX]);
5139 
5140 	for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
5141 		rt2x00_dbg(rt2x00dev,
5142 			   "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
5143 			   (band == NL80211_BAND_5GHZ) ? '5' : '2',
5144 			   (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
5145 								'4' : '2',
5146 			   (i > TX_PWR_CFG_9_IDX) ?
5147 					(i - TX_PWR_CFG_9_IDX - 1) : i,
5148 			   (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
5149 			   (unsigned long) regs[i]);
5150 }
5151 
5152 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
5153 					 struct ieee80211_channel *chan,
5154 					 int power_level)
5155 {
5156 	u32 reg, pwreg;
5157 	u16 eeprom;
5158 	u32 data, gdata;
5159 	u8 t, i;
5160 	enum nl80211_band band = chan->band;
5161 	int delta;
5162 
5163 	/* Warn user if bw_comp is set in EEPROM */
5164 	delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5165 
5166 	if (delta)
5167 		rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
5168 			    delta);
5169 
5170 	/* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
5171 	 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
5172 	 * driver does as well, though it looks kinda wrong.
5173 	 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
5174 	 * the hardware has a problem handling 0x20, and as the code initially
5175 	 * used a fixed offset between HT20 and HT40 rates they had to work-
5176 	 * around that issue and most likely just forgot about it later on.
5177 	 * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
5178 	 * however, the corresponding EEPROM value is not respected by the
5179 	 * vendor driver, so maybe this is rather being taken care of the
5180 	 * TXALC and the driver doesn't need to handle it...?
5181 	 * Though this is all very awkward, just do as they did, as that's what
5182 	 * board vendors expected when they populated the EEPROM...
5183 	 */
5184 	for (i = 0; i < 5; i++) {
5185 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5186 						       EEPROM_TXPOWER_BYRATE,
5187 						       i * 2);
5188 
5189 		data = eeprom;
5190 
5191 		t = eeprom & 0x3f;
5192 		if (t == 32)
5193 			t++;
5194 
5195 		gdata = t;
5196 
5197 		t = (eeprom & 0x3f00) >> 8;
5198 		if (t == 32)
5199 			t++;
5200 
5201 		gdata |= (t << 8);
5202 
5203 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5204 						       EEPROM_TXPOWER_BYRATE,
5205 						       (i * 2) + 1);
5206 
5207 		t = eeprom & 0x3f;
5208 		if (t == 32)
5209 			t++;
5210 
5211 		gdata |= (t << 16);
5212 
5213 		t = (eeprom & 0x3f00) >> 8;
5214 		if (t == 32)
5215 			t++;
5216 
5217 		gdata |= (t << 24);
5218 		data |= (eeprom << 16);
5219 
5220 		if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
5221 			/* HT20 */
5222 			if (data != 0xffffffff)
5223 				rt2800_register_write(rt2x00dev,
5224 						      TX_PWR_CFG_0 + (i * 4),
5225 						      data);
5226 		} else {
5227 			/* HT40 */
5228 			if (gdata != 0xffffffff)
5229 				rt2800_register_write(rt2x00dev,
5230 						      TX_PWR_CFG_0 + (i * 4),
5231 						      gdata);
5232 		}
5233 	}
5234 
5235 	/* Aparently Ralink ran out of space in the BYRATE calibration section
5236 	 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
5237 	 * registers. As recent 2T chips use 8-bit instead of 4-bit values for
5238 	 * power-offsets more space would be needed. Ralink decided to keep the
5239 	 * EEPROM layout untouched and rather have some shared values covering
5240 	 * multiple bitrates.
5241 	 * Populate the registers not covered by the EEPROM in the same way the
5242 	 * vendor driver does.
5243 	 */
5244 
5245 	/* For OFDM 54MBS use value from OFDM 48MBS */
5246 	pwreg = 0;
5247 	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1);
5248 	t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
5249 	rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
5250 
5251 	/* For MCS 7 use value from MCS 6 */
5252 	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2);
5253 	t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
5254 	rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
5255 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
5256 
5257 	/* For MCS 15 use value from MCS 14 */
5258 	pwreg = 0;
5259 	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3);
5260 	t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
5261 	rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
5262 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
5263 
5264 	/* For STBC MCS 7 use value from STBC MCS 6 */
5265 	pwreg = 0;
5266 	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4);
5267 	t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
5268 	rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
5269 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
5270 
5271 	rt2800_config_alc(rt2x00dev, chan, power_level);
5272 
5273 	/* TODO: temperature compensation code! */
5274 }
5275 
5276 /*
5277  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
5278  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
5279  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
5280  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
5281  * Reference per rate transmit power values are located in the EEPROM at
5282  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
5283  * current conditions (i.e. band, bandwidth, temperature, user settings).
5284  */
5285 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
5286 					 struct ieee80211_channel *chan,
5287 					 int power_level)
5288 {
5289 	u8 txpower, r1;
5290 	u16 eeprom;
5291 	u32 reg, offset;
5292 	int i, is_rate_b, delta, power_ctrl;
5293 	enum nl80211_band band = chan->band;
5294 
5295 	/*
5296 	 * Calculate HT40 compensation. For 40MHz we need to add or subtract
5297 	 * value read from EEPROM (different for 2GHz and for 5GHz).
5298 	 */
5299 	delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5300 
5301 	/*
5302 	 * Calculate temperature compensation. Depends on measurement of current
5303 	 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
5304 	 * to temperature or maybe other factors) is smaller or bigger than
5305 	 * expected. We adjust it, based on TSSI reference and boundaries values
5306 	 * provided in EEPROM.
5307 	 */
5308 	switch (rt2x00dev->chip.rt) {
5309 	case RT2860:
5310 	case RT2872:
5311 	case RT2883:
5312 	case RT3070:
5313 	case RT3071:
5314 	case RT3090:
5315 	case RT3572:
5316 		delta += rt2800_get_gain_calibration_delta(rt2x00dev);
5317 		break;
5318 	default:
5319 		/* TODO: temperature compensation code for other chips. */
5320 		break;
5321 	}
5322 
5323 	/*
5324 	 * Decrease power according to user settings, on devices with unknown
5325 	 * maximum tx power. For other devices we take user power_level into
5326 	 * consideration on rt2800_compensate_txpower().
5327 	 */
5328 	delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
5329 					      chan->max_power);
5330 
5331 	/*
5332 	 * BBP_R1 controls TX power for all rates, it allow to set the following
5333 	 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
5334 	 *
5335 	 * TODO: we do not use +6 dBm option to do not increase power beyond
5336 	 * regulatory limit, however this could be utilized for devices with
5337 	 * CAPABILITY_POWER_LIMIT.
5338 	 */
5339 	if (delta <= -12) {
5340 		power_ctrl = 2;
5341 		delta += 12;
5342 	} else if (delta <= -6) {
5343 		power_ctrl = 1;
5344 		delta += 6;
5345 	} else {
5346 		power_ctrl = 0;
5347 	}
5348 	r1 = rt2800_bbp_read(rt2x00dev, 1);
5349 	rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
5350 	rt2800_bbp_write(rt2x00dev, 1, r1);
5351 
5352 	offset = TX_PWR_CFG_0;
5353 
5354 	for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
5355 		/* just to be safe */
5356 		if (offset > TX_PWR_CFG_4)
5357 			break;
5358 
5359 		reg = rt2800_register_read(rt2x00dev, offset);
5360 
5361 		/* read the next four txpower values */
5362 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5363 						       EEPROM_TXPOWER_BYRATE,
5364 						       i);
5365 
5366 		is_rate_b = i ? 0 : 1;
5367 		/*
5368 		 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5369 		 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
5370 		 * TX_PWR_CFG_4: unknown
5371 		 */
5372 		txpower = rt2x00_get_field16(eeprom,
5373 					     EEPROM_TXPOWER_BYRATE_RATE0);
5374 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5375 					     power_level, txpower, delta);
5376 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5377 
5378 		/*
5379 		 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5380 		 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
5381 		 * TX_PWR_CFG_4: unknown
5382 		 */
5383 		txpower = rt2x00_get_field16(eeprom,
5384 					     EEPROM_TXPOWER_BYRATE_RATE1);
5385 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5386 					     power_level, txpower, delta);
5387 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5388 
5389 		/*
5390 		 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5391 		 * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
5392 		 * TX_PWR_CFG_4: unknown
5393 		 */
5394 		txpower = rt2x00_get_field16(eeprom,
5395 					     EEPROM_TXPOWER_BYRATE_RATE2);
5396 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5397 					     power_level, txpower, delta);
5398 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5399 
5400 		/*
5401 		 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5402 		 * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
5403 		 * TX_PWR_CFG_4: unknown
5404 		 */
5405 		txpower = rt2x00_get_field16(eeprom,
5406 					     EEPROM_TXPOWER_BYRATE_RATE3);
5407 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5408 					     power_level, txpower, delta);
5409 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5410 
5411 		/* read the next four txpower values */
5412 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5413 						       EEPROM_TXPOWER_BYRATE,
5414 						       i + 1);
5415 
5416 		is_rate_b = 0;
5417 		/*
5418 		 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5419 		 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
5420 		 * TX_PWR_CFG_4: unknown
5421 		 */
5422 		txpower = rt2x00_get_field16(eeprom,
5423 					     EEPROM_TXPOWER_BYRATE_RATE0);
5424 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5425 					     power_level, txpower, delta);
5426 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5427 
5428 		/*
5429 		 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5430 		 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
5431 		 * TX_PWR_CFG_4: unknown
5432 		 */
5433 		txpower = rt2x00_get_field16(eeprom,
5434 					     EEPROM_TXPOWER_BYRATE_RATE1);
5435 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5436 					     power_level, txpower, delta);
5437 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5438 
5439 		/*
5440 		 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5441 		 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
5442 		 * TX_PWR_CFG_4: unknown
5443 		 */
5444 		txpower = rt2x00_get_field16(eeprom,
5445 					     EEPROM_TXPOWER_BYRATE_RATE2);
5446 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5447 					     power_level, txpower, delta);
5448 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5449 
5450 		/*
5451 		 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5452 		 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
5453 		 * TX_PWR_CFG_4: unknown
5454 		 */
5455 		txpower = rt2x00_get_field16(eeprom,
5456 					     EEPROM_TXPOWER_BYRATE_RATE3);
5457 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5458 					     power_level, txpower, delta);
5459 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5460 
5461 		rt2800_register_write(rt2x00dev, offset, reg);
5462 
5463 		/* next TX_PWR_CFG register */
5464 		offset += 4;
5465 	}
5466 }
5467 
5468 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5469 				  struct ieee80211_channel *chan,
5470 				  int power_level)
5471 {
5472 	if (rt2x00_rt(rt2x00dev, RT3593) ||
5473 	    rt2x00_rt(rt2x00dev, RT3883))
5474 		rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
5475 	else if (rt2x00_rt(rt2x00dev, RT6352))
5476 		rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
5477 	else
5478 		rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
5479 }
5480 
5481 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
5482 {
5483 	rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
5484 			      rt2x00dev->tx_power);
5485 }
5486 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
5487 
5488 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
5489 {
5490 	u32	tx_pin;
5491 	u8	rfcsr;
5492 	unsigned long min_sleep = 0;
5493 
5494 	/*
5495 	 * A voltage-controlled oscillator(VCO) is an electronic oscillator
5496 	 * designed to be controlled in oscillation frequency by a voltage
5497 	 * input. Maybe the temperature will affect the frequency of
5498 	 * oscillation to be shifted. The VCO calibration will be called
5499 	 * periodically to adjust the frequency to be precision.
5500 	*/
5501 
5502 	tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5503 	tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
5504 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5505 
5506 	switch (rt2x00dev->chip.rf) {
5507 	case RF2020:
5508 	case RF3020:
5509 	case RF3021:
5510 	case RF3022:
5511 	case RF3320:
5512 	case RF3052:
5513 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
5514 		rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
5515 		rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
5516 		break;
5517 	case RF3053:
5518 	case RF3070:
5519 	case RF3290:
5520 	case RF3853:
5521 	case RF5350:
5522 	case RF5360:
5523 	case RF5362:
5524 	case RF5370:
5525 	case RF5372:
5526 	case RF5390:
5527 	case RF5392:
5528 	case RF5592:
5529 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
5530 		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
5531 		rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
5532 		min_sleep = 1000;
5533 		break;
5534 	case RF7620:
5535 		rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
5536 		rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
5537 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 4);
5538 		rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
5539 		rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
5540 		min_sleep = 2000;
5541 		break;
5542 	default:
5543 		WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration",
5544 			  rt2x00dev->chip.rf);
5545 		return;
5546 	}
5547 
5548 	if (min_sleep > 0)
5549 		usleep_range(min_sleep, min_sleep * 2);
5550 
5551 	tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5552 	if (rt2x00dev->rf_channel <= 14) {
5553 		switch (rt2x00dev->default_ant.tx_chain_num) {
5554 		case 3:
5555 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
5556 			fallthrough;
5557 		case 2:
5558 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
5559 			fallthrough;
5560 		case 1:
5561 		default:
5562 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
5563 			break;
5564 		}
5565 	} else {
5566 		switch (rt2x00dev->default_ant.tx_chain_num) {
5567 		case 3:
5568 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
5569 			fallthrough;
5570 		case 2:
5571 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
5572 			fallthrough;
5573 		case 1:
5574 		default:
5575 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
5576 			break;
5577 		}
5578 	}
5579 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5580 
5581 	if (rt2x00_rt(rt2x00dev, RT6352)) {
5582 		if (rt2x00dev->default_ant.rx_chain_num == 1) {
5583 			rt2800_bbp_write(rt2x00dev, 91, 0x07);
5584 			rt2800_bbp_write(rt2x00dev, 95, 0x1A);
5585 			rt2800_bbp_write(rt2x00dev, 195, 128);
5586 			rt2800_bbp_write(rt2x00dev, 196, 0xA0);
5587 			rt2800_bbp_write(rt2x00dev, 195, 170);
5588 			rt2800_bbp_write(rt2x00dev, 196, 0x12);
5589 			rt2800_bbp_write(rt2x00dev, 195, 171);
5590 			rt2800_bbp_write(rt2x00dev, 196, 0x10);
5591 		} else {
5592 			rt2800_bbp_write(rt2x00dev, 91, 0x06);
5593 			rt2800_bbp_write(rt2x00dev, 95, 0x9A);
5594 			rt2800_bbp_write(rt2x00dev, 195, 128);
5595 			rt2800_bbp_write(rt2x00dev, 196, 0xE0);
5596 			rt2800_bbp_write(rt2x00dev, 195, 170);
5597 			rt2800_bbp_write(rt2x00dev, 196, 0x30);
5598 			rt2800_bbp_write(rt2x00dev, 195, 171);
5599 			rt2800_bbp_write(rt2x00dev, 196, 0x30);
5600 		}
5601 
5602 		if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
5603 			rt2800_bbp_write(rt2x00dev, 75, 0x68);
5604 			rt2800_bbp_write(rt2x00dev, 76, 0x4C);
5605 			rt2800_bbp_write(rt2x00dev, 79, 0x1C);
5606 			rt2800_bbp_write(rt2x00dev, 80, 0x0C);
5607 			rt2800_bbp_write(rt2x00dev, 82, 0xB6);
5608 		}
5609 
5610 		/* On 11A, We should delay and wait RF/BBP to be stable
5611 		 * and the appropriate time should be 1000 micro seconds
5612 		 * 2005/06/05 - On 11G, we also need this delay time.
5613 		 * Otherwise it's difficult to pass the WHQL.
5614 		 */
5615 		usleep_range(1000, 1500);
5616 	}
5617 }
5618 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
5619 
5620 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5621 				      struct rt2x00lib_conf *libconf)
5622 {
5623 	u32 reg;
5624 
5625 	reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5626 	rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
5627 			   libconf->conf->short_frame_max_tx_count);
5628 	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
5629 			   libconf->conf->long_frame_max_tx_count);
5630 	rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5631 }
5632 
5633 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
5634 			     struct rt2x00lib_conf *libconf)
5635 {
5636 	enum dev_state state =
5637 	    (libconf->conf->flags & IEEE80211_CONF_PS) ?
5638 		STATE_SLEEP : STATE_AWAKE;
5639 	u32 reg;
5640 
5641 	if (state == STATE_SLEEP) {
5642 		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
5643 
5644 		reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5645 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
5646 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
5647 				   libconf->conf->listen_interval - 1);
5648 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
5649 		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5650 
5651 		rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5652 	} else {
5653 		reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5654 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
5655 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
5656 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
5657 		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5658 
5659 		rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5660 	}
5661 }
5662 
5663 void rt2800_config(struct rt2x00_dev *rt2x00dev,
5664 		   struct rt2x00lib_conf *libconf,
5665 		   const unsigned int flags)
5666 {
5667 	/* Always recalculate LNA gain before changing configuration */
5668 	rt2800_config_lna_gain(rt2x00dev, libconf);
5669 
5670 	if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
5671 		/*
5672 		 * To provide correct survey data for survey-based ACS algorithm
5673 		 * we have to save survey data for current channel before switching.
5674 		 */
5675 		rt2800_update_survey(rt2x00dev);
5676 
5677 		rt2800_config_channel(rt2x00dev, libconf->conf,
5678 				      &libconf->rf, &libconf->channel);
5679 		rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5680 				      libconf->conf->power_level);
5681 	}
5682 	if (flags & IEEE80211_CONF_CHANGE_POWER)
5683 		rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5684 				      libconf->conf->power_level);
5685 	if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
5686 		rt2800_config_retry_limit(rt2x00dev, libconf);
5687 	if (flags & IEEE80211_CONF_CHANGE_PS)
5688 		rt2800_config_ps(rt2x00dev, libconf);
5689 }
5690 EXPORT_SYMBOL_GPL(rt2800_config);
5691 
5692 /*
5693  * Link tuning
5694  */
5695 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5696 {
5697 	u32 reg;
5698 
5699 	/*
5700 	 * Update FCS error count from register.
5701 	 */
5702 	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5703 	qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
5704 }
5705 EXPORT_SYMBOL_GPL(rt2800_link_stats);
5706 
5707 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
5708 {
5709 	u8 vgc;
5710 
5711 	if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
5712 		if (rt2x00_rt(rt2x00dev, RT3070) ||
5713 		    rt2x00_rt(rt2x00dev, RT3071) ||
5714 		    rt2x00_rt(rt2x00dev, RT3090) ||
5715 		    rt2x00_rt(rt2x00dev, RT3290) ||
5716 		    rt2x00_rt(rt2x00dev, RT3390) ||
5717 		    rt2x00_rt(rt2x00dev, RT3572) ||
5718 		    rt2x00_rt(rt2x00dev, RT3593) ||
5719 		    rt2x00_rt(rt2x00dev, RT5390) ||
5720 		    rt2x00_rt(rt2x00dev, RT5392) ||
5721 		    rt2x00_rt(rt2x00dev, RT5592) ||
5722 		    rt2x00_rt(rt2x00dev, RT6352))
5723 			vgc = 0x1c + (2 * rt2x00dev->lna_gain);
5724 		else
5725 			vgc = 0x2e + rt2x00dev->lna_gain;
5726 	} else { /* 5GHZ band */
5727 		if (rt2x00_rt(rt2x00dev, RT3593) ||
5728 		    rt2x00_rt(rt2x00dev, RT3883))
5729 			vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
5730 		else if (rt2x00_rt(rt2x00dev, RT5592))
5731 			vgc = 0x24 + (2 * rt2x00dev->lna_gain);
5732 		else {
5733 			if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5734 				vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5735 			else
5736 				vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5737 		}
5738 	}
5739 
5740 	return vgc;
5741 }
5742 
5743 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
5744 				  struct link_qual *qual, u8 vgc_level)
5745 {
5746 	if (qual->vgc_level != vgc_level) {
5747 		if (rt2x00_rt(rt2x00dev, RT3572) ||
5748 		    rt2x00_rt(rt2x00dev, RT3593) ||
5749 		    rt2x00_rt(rt2x00dev, RT3883) ||
5750 		    rt2x00_rt(rt2x00dev, RT6352)) {
5751 			rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
5752 						       vgc_level);
5753 		} else if (rt2x00_rt(rt2x00dev, RT5592)) {
5754 			rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
5755 			rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
5756 		} else {
5757 			rt2800_bbp_write(rt2x00dev, 66, vgc_level);
5758 		}
5759 
5760 		qual->vgc_level = vgc_level;
5761 		qual->vgc_level_reg = vgc_level;
5762 	}
5763 }
5764 
5765 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5766 {
5767 	rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
5768 }
5769 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
5770 
5771 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
5772 		       const u32 count)
5773 {
5774 	u8 vgc;
5775 
5776 	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
5777 		return;
5778 
5779 	/* When RSSI is better than a certain threshold, increase VGC
5780 	 * with a chip specific value in order to improve the balance
5781 	 * between sensibility and noise isolation.
5782 	 */
5783 
5784 	vgc = rt2800_get_default_vgc(rt2x00dev);
5785 
5786 	switch (rt2x00dev->chip.rt) {
5787 	case RT3572:
5788 	case RT3593:
5789 		if (qual->rssi > -65) {
5790 			if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
5791 				vgc += 0x20;
5792 			else
5793 				vgc += 0x10;
5794 		}
5795 		break;
5796 
5797 	case RT3883:
5798 		if (qual->rssi > -65)
5799 			vgc += 0x10;
5800 		break;
5801 
5802 	case RT5592:
5803 		if (qual->rssi > -65)
5804 			vgc += 0x20;
5805 		break;
5806 
5807 	default:
5808 		if (qual->rssi > -80)
5809 			vgc += 0x10;
5810 		break;
5811 	}
5812 
5813 	rt2800_set_vgc(rt2x00dev, qual, vgc);
5814 }
5815 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
5816 
5817 /*
5818  * Initialization functions.
5819  */
5820 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
5821 {
5822 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5823 	u32 reg;
5824 	u16 eeprom;
5825 	unsigned int i;
5826 	int ret;
5827 
5828 	rt2800_disable_wpdma(rt2x00dev);
5829 
5830 	ret = rt2800_drv_init_registers(rt2x00dev);
5831 	if (ret)
5832 		return ret;
5833 
5834 	rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5835 	rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5836 
5837 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5838 
5839 	reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
5840 	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
5841 	rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
5842 	rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
5843 	rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
5844 	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
5845 	rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
5846 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5847 
5848 	rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
5849 
5850 	reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
5851 	rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
5852 	rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
5853 	rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5854 
5855 	if (rt2x00_rt(rt2x00dev, RT3290)) {
5856 		reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
5857 		if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
5858 			rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
5859 			rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
5860 		}
5861 
5862 		reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
5863 		if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
5864 			rt2x00_set_field32(&reg, LDO0_EN, 1);
5865 			rt2x00_set_field32(&reg, LDO_BGSEL, 3);
5866 			rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
5867 		}
5868 
5869 		reg = rt2800_register_read(rt2x00dev, OSC_CTRL);
5870 		rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
5871 		rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
5872 		rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
5873 		rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
5874 
5875 		reg = rt2800_register_read(rt2x00dev, COEX_CFG0);
5876 		rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
5877 		rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
5878 
5879 		reg = rt2800_register_read(rt2x00dev, COEX_CFG2);
5880 		rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
5881 		rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
5882 		rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
5883 		rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
5884 		rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
5885 
5886 		reg = rt2800_register_read(rt2x00dev, PLL_CTRL);
5887 		rt2x00_set_field32(&reg, PLL_CONTROL, 1);
5888 		rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
5889 	}
5890 
5891 	if (rt2x00_rt(rt2x00dev, RT3071) ||
5892 	    rt2x00_rt(rt2x00dev, RT3090) ||
5893 	    rt2x00_rt(rt2x00dev, RT3290) ||
5894 	    rt2x00_rt(rt2x00dev, RT3390)) {
5895 
5896 		if (rt2x00_rt(rt2x00dev, RT3290))
5897 			rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5898 					      0x00000404);
5899 		else
5900 			rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5901 					      0x00000400);
5902 
5903 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5904 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5905 		    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5906 		    rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5907 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5908 			if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
5909 				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5910 						      0x0000002c);
5911 			else
5912 				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5913 						      0x0000000f);
5914 		} else {
5915 			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5916 		}
5917 	} else if (rt2x00_rt(rt2x00dev, RT3070)) {
5918 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5919 
5920 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5921 			rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5922 			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
5923 		} else {
5924 			rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5925 			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5926 		}
5927 	} else if (rt2800_is_305x_soc(rt2x00dev)) {
5928 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5929 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5930 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
5931 	} else if (rt2x00_rt(rt2x00dev, RT3352)) {
5932 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5933 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5934 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5935 	} else if (rt2x00_rt(rt2x00dev, RT3572)) {
5936 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5937 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5938 	} else if (rt2x00_rt(rt2x00dev, RT3593)) {
5939 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5940 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5941 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
5942 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5943 			if (rt2x00_get_field16(eeprom,
5944 					       EEPROM_NIC_CONF1_DAC_TEST))
5945 				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5946 						      0x0000001f);
5947 			else
5948 				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5949 						      0x0000000f);
5950 		} else {
5951 			rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5952 					      0x00000000);
5953 		}
5954 	} else if (rt2x00_rt(rt2x00dev, RT3883)) {
5955 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5956 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5957 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000);
5958 		rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21);
5959 		rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40);
5960 	} else if (rt2x00_rt(rt2x00dev, RT5390) ||
5961 		   rt2x00_rt(rt2x00dev, RT5392)) {
5962 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5963 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5964 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5965 	} else if (rt2x00_rt(rt2x00dev, RT5592)) {
5966 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5967 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5968 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5969 	} else if (rt2x00_rt(rt2x00dev, RT5350)) {
5970 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5971 	} else if (rt2x00_rt(rt2x00dev, RT6352)) {
5972 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
5973 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
5974 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5975 		rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
5976 		rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
5977 		rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
5978 		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
5979 		rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
5980 		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
5981 				      0x3630363A);
5982 		rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
5983 				      0x3630363A);
5984 		reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
5985 		rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
5986 		rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
5987 	} else {
5988 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
5989 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5990 	}
5991 
5992 	reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG);
5993 	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
5994 	rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
5995 	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
5996 	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
5997 	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
5998 	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
5999 	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
6000 	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
6001 	rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
6002 
6003 	reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG);
6004 	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
6005 	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
6006 	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
6007 	rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
6008 
6009 	reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
6010 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
6011 	if (rt2x00_is_usb(rt2x00dev)) {
6012 		drv_data->max_psdu = 3;
6013 	} else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
6014 		   rt2x00_rt(rt2x00dev, RT2883) ||
6015 		   rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
6016 		drv_data->max_psdu = 2;
6017 	} else {
6018 		drv_data->max_psdu = 1;
6019 	}
6020 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu);
6021 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 10);
6022 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 10);
6023 	rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
6024 
6025 	reg = rt2800_register_read(rt2x00dev, LED_CFG);
6026 	rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
6027 	rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
6028 	rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
6029 	rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
6030 	rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
6031 	rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
6032 	rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
6033 	rt2800_register_write(rt2x00dev, LED_CFG, reg);
6034 
6035 	rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
6036 
6037 	reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
6038 	rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 2);
6039 	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 2);
6040 	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
6041 	rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
6042 	rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
6043 	rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
6044 	rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
6045 
6046 	reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
6047 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
6048 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
6049 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 1);
6050 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
6051 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 0);
6052 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
6053 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
6054 	rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
6055 
6056 	reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
6057 	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
6058 	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6059 	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
6060 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
6061 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
6062 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6063 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
6064 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6065 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
6066 	rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
6067 	rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
6068 
6069 	reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
6070 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
6071 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6072 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
6073 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
6074 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
6075 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6076 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
6077 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6078 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
6079 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
6080 	rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
6081 
6082 	reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
6083 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
6084 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 1);
6085 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
6086 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
6087 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
6088 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6089 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
6090 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6091 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
6092 	rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
6093 	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
6094 
6095 	reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
6096 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
6097 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 1);
6098 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
6099 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
6100 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
6101 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6102 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
6103 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6104 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
6105 	rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
6106 	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
6107 
6108 	reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
6109 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
6110 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 1);
6111 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
6112 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
6113 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
6114 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6115 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
6116 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6117 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
6118 	rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
6119 	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6120 
6121 	reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
6122 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
6123 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 1);
6124 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
6125 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
6126 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
6127 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6128 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
6129 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6130 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
6131 	rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
6132 	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6133 
6134 	if (rt2x00_is_usb(rt2x00dev)) {
6135 		rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
6136 
6137 		reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
6138 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
6139 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
6140 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
6141 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
6142 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
6143 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
6144 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
6145 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
6146 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
6147 		rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6148 	}
6149 
6150 	/*
6151 	 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
6152 	 * although it is reserved.
6153 	 */
6154 	reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG);
6155 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
6156 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
6157 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
6158 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
6159 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
6160 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
6161 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
6162 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
6163 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
6164 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
6165 	rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
6166 
6167 	reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
6168 	rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
6169 
6170 	if (rt2x00_rt(rt2x00dev, RT3883)) {
6171 		rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008);
6172 		rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413);
6173 	}
6174 
6175 	reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
6176 	rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7);
6177 	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
6178 			   IEEE80211_MAX_RTS_THRESHOLD);
6179 	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 1);
6180 	rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6181 
6182 	rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
6183 
6184 	/*
6185 	 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
6186 	 * time should be set to 16. However, the original Ralink driver uses
6187 	 * 16 for both and indeed using a value of 10 for CCK SIFS results in
6188 	 * connection problems with 11g + CTS protection. Hence, use the same
6189 	 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
6190 	 */
6191 	reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
6192 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
6193 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
6194 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
6195 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
6196 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
6197 	rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
6198 
6199 	rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
6200 
6201 	/*
6202 	 * ASIC will keep garbage value after boot, clear encryption keys.
6203 	 */
6204 	for (i = 0; i < 4; i++)
6205 		rt2800_register_write(rt2x00dev, SHARED_KEY_MODE_ENTRY(i), 0);
6206 
6207 	for (i = 0; i < 256; i++) {
6208 		rt2800_config_wcid(rt2x00dev, NULL, i);
6209 		rt2800_delete_wcid_attr(rt2x00dev, i);
6210 	}
6211 
6212 	/*
6213 	 * Clear encryption initialization vectors on start, but keep them
6214 	 * for watchdog reset. Otherwise we will have wrong IVs and not be
6215 	 * able to keep connections after reset.
6216 	 */
6217 	if (!test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
6218 		for (i = 0; i < 256; i++)
6219 			rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
6220 
6221 	/*
6222 	 * Clear all beacons
6223 	 */
6224 	for (i = 0; i < 8; i++)
6225 		rt2800_clear_beacon_register(rt2x00dev, i);
6226 
6227 	if (rt2x00_is_usb(rt2x00dev)) {
6228 		reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6229 		rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
6230 		rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6231 	} else if (rt2x00_is_pcie(rt2x00dev)) {
6232 		reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6233 		rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
6234 		rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6235 	} else if (rt2x00_is_soc(rt2x00dev)) {
6236 		struct clk *clk = clk_get_sys("bus", NULL);
6237 		int rate;
6238 
6239 		if (IS_ERR(clk)) {
6240 			clk = clk_get_sys("cpu", NULL);
6241 
6242 			if (IS_ERR(clk)) {
6243 				rate = 125;
6244 			} else {
6245 				rate = clk_get_rate(clk) / 3000000;
6246 				clk_put(clk);
6247 			}
6248 		} else {
6249 			rate = clk_get_rate(clk) / 1000000;
6250 			clk_put(clk);
6251 		}
6252 
6253 		reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6254 		rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, rate);
6255 		rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6256 	}
6257 
6258 	reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
6259 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
6260 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
6261 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
6262 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
6263 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
6264 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
6265 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
6266 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
6267 	rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
6268 
6269 	reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1);
6270 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
6271 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
6272 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
6273 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
6274 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
6275 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
6276 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
6277 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
6278 	rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
6279 
6280 	reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0);
6281 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
6282 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
6283 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
6284 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
6285 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
6286 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
6287 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
6288 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
6289 	rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
6290 
6291 	reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1);
6292 	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
6293 	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
6294 	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
6295 	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
6296 	rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
6297 
6298 	/*
6299 	 * Do not force the BA window size, we use the TXWI to set it
6300 	 */
6301 	reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE);
6302 	rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
6303 	rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
6304 	rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
6305 
6306 	/*
6307 	 * We must clear the error counters.
6308 	 * These registers are cleared on read,
6309 	 * so we may pass a useless variable to store the value.
6310 	 */
6311 	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
6312 	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1);
6313 	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2);
6314 	reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0);
6315 	reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1);
6316 	reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2);
6317 
6318 	/*
6319 	 * Setup leadtime for pre tbtt interrupt to 6ms
6320 	 */
6321 	reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG);
6322 	rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
6323 	rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
6324 
6325 	/*
6326 	 * Set up channel statistics timer
6327 	 */
6328 	reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG);
6329 	rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
6330 	rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
6331 	rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
6332 	rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
6333 	rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
6334 	rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
6335 
6336 	return 0;
6337 }
6338 
6339 
6340 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
6341 {
6342 	u8 value;
6343 
6344 	value = rt2800_bbp_read(rt2x00dev, 4);
6345 	rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
6346 	rt2800_bbp_write(rt2x00dev, 4, value);
6347 }
6348 
6349 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
6350 {
6351 	rt2800_bbp_write(rt2x00dev, 142, 1);
6352 	rt2800_bbp_write(rt2x00dev, 143, 57);
6353 }
6354 
6355 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
6356 {
6357 	static const u8 glrt_table[] = {
6358 		0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
6359 		0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
6360 		0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
6361 		0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
6362 		0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
6363 		0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
6364 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
6365 		0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
6366 		0x2E, 0x36, 0x30, 0x6E,					    /* 208 ~ 211 */
6367 	};
6368 	int i;
6369 
6370 	for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
6371 		rt2800_bbp_write(rt2x00dev, 195, 128 + i);
6372 		rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
6373 	}
6374 };
6375 
6376 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
6377 {
6378 	rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6379 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6380 	rt2800_bbp_write(rt2x00dev, 68, 0x0B);
6381 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6382 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6383 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
6384 	rt2800_bbp_write(rt2x00dev, 81, 0x37);
6385 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6386 	rt2800_bbp_write(rt2x00dev, 83, 0x6A);
6387 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
6388 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6389 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6390 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6391 	rt2800_bbp_write(rt2x00dev, 103, 0x00);
6392 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
6393 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6394 }
6395 
6396 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
6397 {
6398 	u16 eeprom;
6399 	u8 value;
6400 
6401 	value = rt2800_bbp_read(rt2x00dev, 138);
6402 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
6403 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6404 		value |= 0x20;
6405 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6406 		value &= ~0x02;
6407 	rt2800_bbp_write(rt2x00dev, 138, value);
6408 }
6409 
6410 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
6411 {
6412 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6413 
6414 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6415 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6416 
6417 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6418 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
6419 
6420 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6421 
6422 	rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6423 	rt2800_bbp_write(rt2x00dev, 80, 0x08);
6424 
6425 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6426 
6427 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6428 
6429 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
6430 
6431 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6432 
6433 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6434 
6435 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6436 
6437 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6438 
6439 	rt2800_bbp_write(rt2x00dev, 105, 0x01);
6440 
6441 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6442 }
6443 
6444 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
6445 {
6446 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6447 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6448 
6449 	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
6450 		rt2800_bbp_write(rt2x00dev, 69, 0x16);
6451 		rt2800_bbp_write(rt2x00dev, 73, 0x12);
6452 	} else {
6453 		rt2800_bbp_write(rt2x00dev, 69, 0x12);
6454 		rt2800_bbp_write(rt2x00dev, 73, 0x10);
6455 	}
6456 
6457 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6458 
6459 	rt2800_bbp_write(rt2x00dev, 81, 0x37);
6460 
6461 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6462 
6463 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6464 
6465 	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
6466 		rt2800_bbp_write(rt2x00dev, 84, 0x19);
6467 	else
6468 		rt2800_bbp_write(rt2x00dev, 84, 0x99);
6469 
6470 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6471 
6472 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6473 
6474 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6475 
6476 	rt2800_bbp_write(rt2x00dev, 103, 0x00);
6477 
6478 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
6479 
6480 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6481 }
6482 
6483 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
6484 {
6485 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6486 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6487 
6488 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6489 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
6490 
6491 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6492 
6493 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6494 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6495 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6496 
6497 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6498 
6499 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6500 
6501 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
6502 
6503 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6504 
6505 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6506 
6507 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6508 
6509 	if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
6510 	    rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
6511 	    rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
6512 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6513 	else
6514 		rt2800_bbp_write(rt2x00dev, 103, 0x00);
6515 
6516 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
6517 
6518 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6519 
6520 	if (rt2x00_rt(rt2x00dev, RT3071) ||
6521 	    rt2x00_rt(rt2x00dev, RT3090))
6522 		rt2800_disable_unused_dac_adc(rt2x00dev);
6523 }
6524 
6525 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
6526 {
6527 	u8 value;
6528 
6529 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6530 
6531 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6532 
6533 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6534 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6535 
6536 	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6537 
6538 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6539 	rt2800_bbp_write(rt2x00dev, 73, 0x13);
6540 	rt2800_bbp_write(rt2x00dev, 75, 0x46);
6541 	rt2800_bbp_write(rt2x00dev, 76, 0x28);
6542 
6543 	rt2800_bbp_write(rt2x00dev, 77, 0x58);
6544 
6545 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6546 
6547 	rt2800_bbp_write(rt2x00dev, 74, 0x0b);
6548 	rt2800_bbp_write(rt2x00dev, 79, 0x18);
6549 	rt2800_bbp_write(rt2x00dev, 80, 0x09);
6550 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6551 
6552 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6553 
6554 	rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6555 
6556 	rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6557 
6558 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
6559 
6560 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6561 
6562 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6563 
6564 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6565 
6566 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
6567 
6568 	rt2800_bbp_write(rt2x00dev, 105, 0x1c);
6569 
6570 	rt2800_bbp_write(rt2x00dev, 106, 0x03);
6571 
6572 	rt2800_bbp_write(rt2x00dev, 128, 0x12);
6573 
6574 	rt2800_bbp_write(rt2x00dev, 67, 0x24);
6575 	rt2800_bbp_write(rt2x00dev, 143, 0x04);
6576 	rt2800_bbp_write(rt2x00dev, 142, 0x99);
6577 	rt2800_bbp_write(rt2x00dev, 150, 0x30);
6578 	rt2800_bbp_write(rt2x00dev, 151, 0x2e);
6579 	rt2800_bbp_write(rt2x00dev, 152, 0x20);
6580 	rt2800_bbp_write(rt2x00dev, 153, 0x34);
6581 	rt2800_bbp_write(rt2x00dev, 154, 0x40);
6582 	rt2800_bbp_write(rt2x00dev, 155, 0x3b);
6583 	rt2800_bbp_write(rt2x00dev, 253, 0x04);
6584 
6585 	value = rt2800_bbp_read(rt2x00dev, 47);
6586 	rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
6587 	rt2800_bbp_write(rt2x00dev, 47, value);
6588 
6589 	/* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
6590 	value = rt2800_bbp_read(rt2x00dev, 3);
6591 	rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
6592 	rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
6593 	rt2800_bbp_write(rt2x00dev, 3, value);
6594 }
6595 
6596 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
6597 {
6598 	rt2800_bbp_write(rt2x00dev, 3, 0x00);
6599 	rt2800_bbp_write(rt2x00dev, 4, 0x50);
6600 
6601 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6602 
6603 	rt2800_bbp_write(rt2x00dev, 47, 0x48);
6604 
6605 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6606 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6607 
6608 	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6609 
6610 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6611 	rt2800_bbp_write(rt2x00dev, 73, 0x13);
6612 	rt2800_bbp_write(rt2x00dev, 75, 0x46);
6613 	rt2800_bbp_write(rt2x00dev, 76, 0x28);
6614 
6615 	rt2800_bbp_write(rt2x00dev, 77, 0x59);
6616 
6617 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6618 
6619 	rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6620 	rt2800_bbp_write(rt2x00dev, 80, 0x08);
6621 	rt2800_bbp_write(rt2x00dev, 81, 0x37);
6622 
6623 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6624 
6625 	if (rt2x00_rt(rt2x00dev, RT5350)) {
6626 		rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6627 		rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6628 	} else {
6629 		rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6630 		rt2800_bbp_write(rt2x00dev, 84, 0x99);
6631 	}
6632 
6633 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
6634 
6635 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
6636 
6637 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6638 
6639 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6640 
6641 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6642 
6643 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
6644 
6645 	if (rt2x00_rt(rt2x00dev, RT5350)) {
6646 		rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6647 		rt2800_bbp_write(rt2x00dev, 106, 0x03);
6648 	} else {
6649 		rt2800_bbp_write(rt2x00dev, 105, 0x34);
6650 		rt2800_bbp_write(rt2x00dev, 106, 0x05);
6651 	}
6652 
6653 	rt2800_bbp_write(rt2x00dev, 120, 0x50);
6654 
6655 	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6656 
6657 	rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6658 	/* Set ITxBF timeout to 0x9c40=1000msec */
6659 	rt2800_bbp_write(rt2x00dev, 179, 0x02);
6660 	rt2800_bbp_write(rt2x00dev, 180, 0x00);
6661 	rt2800_bbp_write(rt2x00dev, 182, 0x40);
6662 	rt2800_bbp_write(rt2x00dev, 180, 0x01);
6663 	rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6664 	rt2800_bbp_write(rt2x00dev, 179, 0x00);
6665 	/* Reprogram the inband interface to put right values in RXWI */
6666 	rt2800_bbp_write(rt2x00dev, 142, 0x04);
6667 	rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6668 	rt2800_bbp_write(rt2x00dev, 142, 0x06);
6669 	rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6670 	rt2800_bbp_write(rt2x00dev, 142, 0x07);
6671 	rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6672 	rt2800_bbp_write(rt2x00dev, 142, 0x08);
6673 	rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6674 
6675 	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6676 
6677 	if (rt2x00_rt(rt2x00dev, RT5350)) {
6678 		/* Antenna Software OFDM */
6679 		rt2800_bbp_write(rt2x00dev, 150, 0x40);
6680 		/* Antenna Software CCK */
6681 		rt2800_bbp_write(rt2x00dev, 151, 0x30);
6682 		rt2800_bbp_write(rt2x00dev, 152, 0xa3);
6683 		/* Clear previously selected antenna */
6684 		rt2800_bbp_write(rt2x00dev, 154, 0);
6685 	}
6686 }
6687 
6688 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
6689 {
6690 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6691 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6692 
6693 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6694 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
6695 
6696 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6697 
6698 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6699 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6700 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6701 
6702 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6703 
6704 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6705 
6706 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
6707 
6708 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6709 
6710 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6711 
6712 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6713 
6714 	if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
6715 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6716 	else
6717 		rt2800_bbp_write(rt2x00dev, 103, 0x00);
6718 
6719 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
6720 
6721 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6722 
6723 	rt2800_disable_unused_dac_adc(rt2x00dev);
6724 }
6725 
6726 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
6727 {
6728 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6729 
6730 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6731 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6732 
6733 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6734 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
6735 
6736 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6737 
6738 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6739 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6740 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6741 
6742 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6743 
6744 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6745 
6746 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
6747 
6748 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6749 
6750 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6751 
6752 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6753 
6754 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6755 
6756 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
6757 
6758 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6759 
6760 	rt2800_disable_unused_dac_adc(rt2x00dev);
6761 }
6762 
6763 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
6764 {
6765 	rt2800_init_bbp_early(rt2x00dev);
6766 
6767 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6768 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6769 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6770 	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6771 
6772 	rt2800_bbp_write(rt2x00dev, 84, 0x19);
6773 
6774 	/* Enable DC filter */
6775 	if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
6776 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6777 }
6778 
6779 static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev)
6780 {
6781 	rt2800_init_bbp_early(rt2x00dev);
6782 
6783 	rt2800_bbp_write(rt2x00dev, 4, 0x50);
6784 	rt2800_bbp_write(rt2x00dev, 47, 0x48);
6785 
6786 	rt2800_bbp_write(rt2x00dev, 86, 0x46);
6787 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
6788 
6789 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6790 
6791 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6792 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
6793 	rt2800_bbp_write(rt2x00dev, 105, 0x34);
6794 	rt2800_bbp_write(rt2x00dev, 106, 0x12);
6795 	rt2800_bbp_write(rt2x00dev, 120, 0x50);
6796 	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6797 	rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6798 
6799 	/* Set ITxBF timeout to 0x9C40=1000msec */
6800 	rt2800_bbp_write(rt2x00dev, 179, 0x02);
6801 	rt2800_bbp_write(rt2x00dev, 180, 0x00);
6802 	rt2800_bbp_write(rt2x00dev, 182, 0x40);
6803 	rt2800_bbp_write(rt2x00dev, 180, 0x01);
6804 	rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6805 
6806 	rt2800_bbp_write(rt2x00dev, 179, 0x00);
6807 
6808 	/* Reprogram the inband interface to put right values in RXWI */
6809 	rt2800_bbp_write(rt2x00dev, 142, 0x04);
6810 	rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6811 	rt2800_bbp_write(rt2x00dev, 142, 0x06);
6812 	rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6813 	rt2800_bbp_write(rt2x00dev, 142, 0x07);
6814 	rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6815 	rt2800_bbp_write(rt2x00dev, 142, 0x08);
6816 	rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6817 	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6818 }
6819 
6820 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
6821 {
6822 	int ant, div_mode;
6823 	u16 eeprom;
6824 	u8 value;
6825 
6826 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6827 
6828 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6829 
6830 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6831 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6832 
6833 	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6834 
6835 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6836 	rt2800_bbp_write(rt2x00dev, 73, 0x13);
6837 	rt2800_bbp_write(rt2x00dev, 75, 0x46);
6838 	rt2800_bbp_write(rt2x00dev, 76, 0x28);
6839 
6840 	rt2800_bbp_write(rt2x00dev, 77, 0x59);
6841 
6842 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6843 
6844 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6845 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6846 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6847 
6848 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6849 
6850 	rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6851 
6852 	rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6853 
6854 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
6855 
6856 	if (rt2x00_rt(rt2x00dev, RT5392))
6857 		rt2800_bbp_write(rt2x00dev, 88, 0x90);
6858 
6859 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6860 
6861 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6862 
6863 	if (rt2x00_rt(rt2x00dev, RT5392)) {
6864 		rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6865 		rt2800_bbp_write(rt2x00dev, 98, 0x12);
6866 	}
6867 
6868 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6869 
6870 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
6871 
6872 	rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6873 
6874 	if (rt2x00_rt(rt2x00dev, RT5390))
6875 		rt2800_bbp_write(rt2x00dev, 106, 0x03);
6876 	else if (rt2x00_rt(rt2x00dev, RT5392))
6877 		rt2800_bbp_write(rt2x00dev, 106, 0x12);
6878 	else
6879 		WARN_ON(1);
6880 
6881 	rt2800_bbp_write(rt2x00dev, 128, 0x12);
6882 
6883 	if (rt2x00_rt(rt2x00dev, RT5392)) {
6884 		rt2800_bbp_write(rt2x00dev, 134, 0xd0);
6885 		rt2800_bbp_write(rt2x00dev, 135, 0xf6);
6886 	}
6887 
6888 	rt2800_disable_unused_dac_adc(rt2x00dev);
6889 
6890 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6891 	div_mode = rt2x00_get_field16(eeprom,
6892 				      EEPROM_NIC_CONF1_ANT_DIVERSITY);
6893 	ant = (div_mode == 3) ? 1 : 0;
6894 
6895 	/* check if this is a Bluetooth combo card */
6896 	if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
6897 		u32 reg;
6898 
6899 		reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
6900 		rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
6901 		rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
6902 		rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
6903 		rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
6904 		if (ant == 0)
6905 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
6906 		else if (ant == 1)
6907 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
6908 		rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6909 	}
6910 
6911 	/* These chips have hardware RX antenna diversity */
6912 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
6913 	    rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
6914 		rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
6915 		rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
6916 		rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
6917 	}
6918 
6919 	value = rt2800_bbp_read(rt2x00dev, 152);
6920 	if (ant == 0)
6921 		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6922 	else
6923 		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6924 	rt2800_bbp_write(rt2x00dev, 152, value);
6925 
6926 	rt2800_init_freq_calibration(rt2x00dev);
6927 }
6928 
6929 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
6930 {
6931 	int ant, div_mode;
6932 	u16 eeprom;
6933 	u8 value;
6934 
6935 	rt2800_init_bbp_early(rt2x00dev);
6936 
6937 	value = rt2800_bbp_read(rt2x00dev, 105);
6938 	rt2x00_set_field8(&value, BBP105_MLD,
6939 			  rt2x00dev->default_ant.rx_chain_num == 2);
6940 	rt2800_bbp_write(rt2x00dev, 105, value);
6941 
6942 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6943 
6944 	rt2800_bbp_write(rt2x00dev, 20, 0x06);
6945 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6946 	rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6947 	rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6948 	rt2800_bbp_write(rt2x00dev, 69, 0x1A);
6949 	rt2800_bbp_write(rt2x00dev, 70, 0x05);
6950 	rt2800_bbp_write(rt2x00dev, 73, 0x13);
6951 	rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6952 	rt2800_bbp_write(rt2x00dev, 75, 0x4F);
6953 	rt2800_bbp_write(rt2x00dev, 76, 0x28);
6954 	rt2800_bbp_write(rt2x00dev, 77, 0x59);
6955 	rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6956 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
6957 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
6958 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6959 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6960 	rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6961 	rt2800_bbp_write(rt2x00dev, 98, 0x12);
6962 	rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6963 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
6964 	/* FIXME BBP105 owerwrite */
6965 	rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6966 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6967 	rt2800_bbp_write(rt2x00dev, 128, 0x12);
6968 	rt2800_bbp_write(rt2x00dev, 134, 0xD0);
6969 	rt2800_bbp_write(rt2x00dev, 135, 0xF6);
6970 	rt2800_bbp_write(rt2x00dev, 137, 0x0F);
6971 
6972 	/* Initialize GLRT (Generalized Likehood Radio Test) */
6973 	rt2800_init_bbp_5592_glrt(rt2x00dev);
6974 
6975 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6976 
6977 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6978 	div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
6979 	ant = (div_mode == 3) ? 1 : 0;
6980 	value = rt2800_bbp_read(rt2x00dev, 152);
6981 	if (ant == 0) {
6982 		/* Main antenna */
6983 		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6984 	} else {
6985 		/* Auxiliary antenna */
6986 		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6987 	}
6988 	rt2800_bbp_write(rt2x00dev, 152, value);
6989 
6990 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
6991 		value = rt2800_bbp_read(rt2x00dev, 254);
6992 		rt2x00_set_field8(&value, BBP254_BIT7, 1);
6993 		rt2800_bbp_write(rt2x00dev, 254, value);
6994 	}
6995 
6996 	rt2800_init_freq_calibration(rt2x00dev);
6997 
6998 	rt2800_bbp_write(rt2x00dev, 84, 0x19);
6999 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
7000 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
7001 }
7002 
7003 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
7004 {
7005 	u8 bbp;
7006 
7007 	/* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
7008 	bbp = rt2800_bbp_read(rt2x00dev, 105);
7009 	rt2x00_set_field8(&bbp, BBP105_MLD,
7010 			  rt2x00dev->default_ant.rx_chain_num == 2);
7011 	rt2800_bbp_write(rt2x00dev, 105, bbp);
7012 
7013 	/* Avoid data loss and CRC errors */
7014 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7015 
7016 	/* Fix I/Q swap issue */
7017 	bbp = rt2800_bbp_read(rt2x00dev, 1);
7018 	bbp |= 0x04;
7019 	rt2800_bbp_write(rt2x00dev, 1, bbp);
7020 
7021 	/* BBP for G band */
7022 	rt2800_bbp_write(rt2x00dev, 3, 0x08);
7023 	rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
7024 	rt2800_bbp_write(rt2x00dev, 6, 0x08);
7025 	rt2800_bbp_write(rt2x00dev, 14, 0x09);
7026 	rt2800_bbp_write(rt2x00dev, 15, 0xFF);
7027 	rt2800_bbp_write(rt2x00dev, 16, 0x01);
7028 	rt2800_bbp_write(rt2x00dev, 20, 0x06);
7029 	rt2800_bbp_write(rt2x00dev, 21, 0x00);
7030 	rt2800_bbp_write(rt2x00dev, 22, 0x00);
7031 	rt2800_bbp_write(rt2x00dev, 27, 0x00);
7032 	rt2800_bbp_write(rt2x00dev, 28, 0x00);
7033 	rt2800_bbp_write(rt2x00dev, 30, 0x00);
7034 	rt2800_bbp_write(rt2x00dev, 31, 0x48);
7035 	rt2800_bbp_write(rt2x00dev, 47, 0x40);
7036 	rt2800_bbp_write(rt2x00dev, 62, 0x00);
7037 	rt2800_bbp_write(rt2x00dev, 63, 0x00);
7038 	rt2800_bbp_write(rt2x00dev, 64, 0x00);
7039 	rt2800_bbp_write(rt2x00dev, 65, 0x2C);
7040 	rt2800_bbp_write(rt2x00dev, 66, 0x1C);
7041 	rt2800_bbp_write(rt2x00dev, 67, 0x20);
7042 	rt2800_bbp_write(rt2x00dev, 68, 0xDD);
7043 	rt2800_bbp_write(rt2x00dev, 69, 0x10);
7044 	rt2800_bbp_write(rt2x00dev, 70, 0x05);
7045 	rt2800_bbp_write(rt2x00dev, 73, 0x18);
7046 	rt2800_bbp_write(rt2x00dev, 74, 0x0F);
7047 	rt2800_bbp_write(rt2x00dev, 75, 0x60);
7048 	rt2800_bbp_write(rt2x00dev, 76, 0x44);
7049 	rt2800_bbp_write(rt2x00dev, 77, 0x59);
7050 	rt2800_bbp_write(rt2x00dev, 78, 0x1E);
7051 	rt2800_bbp_write(rt2x00dev, 79, 0x1C);
7052 	rt2800_bbp_write(rt2x00dev, 80, 0x0C);
7053 	rt2800_bbp_write(rt2x00dev, 81, 0x3A);
7054 	rt2800_bbp_write(rt2x00dev, 82, 0xB6);
7055 	rt2800_bbp_write(rt2x00dev, 83, 0x9A);
7056 	rt2800_bbp_write(rt2x00dev, 84, 0x9A);
7057 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
7058 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
7059 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
7060 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
7061 	rt2800_bbp_write(rt2x00dev, 95, 0x9A);
7062 	rt2800_bbp_write(rt2x00dev, 96, 0x00);
7063 	rt2800_bbp_write(rt2x00dev, 103, 0xC0);
7064 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
7065 	/* FIXME BBP105 owerwrite */
7066 	rt2800_bbp_write(rt2x00dev, 105, 0x3C);
7067 	rt2800_bbp_write(rt2x00dev, 106, 0x12);
7068 	rt2800_bbp_write(rt2x00dev, 109, 0x00);
7069 	rt2800_bbp_write(rt2x00dev, 134, 0x10);
7070 	rt2800_bbp_write(rt2x00dev, 135, 0xA6);
7071 	rt2800_bbp_write(rt2x00dev, 137, 0x04);
7072 	rt2800_bbp_write(rt2x00dev, 142, 0x30);
7073 	rt2800_bbp_write(rt2x00dev, 143, 0xF7);
7074 	rt2800_bbp_write(rt2x00dev, 160, 0xEC);
7075 	rt2800_bbp_write(rt2x00dev, 161, 0xC4);
7076 	rt2800_bbp_write(rt2x00dev, 162, 0x77);
7077 	rt2800_bbp_write(rt2x00dev, 163, 0xF9);
7078 	rt2800_bbp_write(rt2x00dev, 164, 0x00);
7079 	rt2800_bbp_write(rt2x00dev, 165, 0x00);
7080 	rt2800_bbp_write(rt2x00dev, 186, 0x00);
7081 	rt2800_bbp_write(rt2x00dev, 187, 0x00);
7082 	rt2800_bbp_write(rt2x00dev, 188, 0x00);
7083 	rt2800_bbp_write(rt2x00dev, 186, 0x00);
7084 	rt2800_bbp_write(rt2x00dev, 187, 0x01);
7085 	rt2800_bbp_write(rt2x00dev, 188, 0x00);
7086 	rt2800_bbp_write(rt2x00dev, 189, 0x00);
7087 
7088 	rt2800_bbp_write(rt2x00dev, 91, 0x06);
7089 	rt2800_bbp_write(rt2x00dev, 92, 0x04);
7090 	rt2800_bbp_write(rt2x00dev, 93, 0x54);
7091 	rt2800_bbp_write(rt2x00dev, 99, 0x50);
7092 	rt2800_bbp_write(rt2x00dev, 148, 0x84);
7093 	rt2800_bbp_write(rt2x00dev, 167, 0x80);
7094 	rt2800_bbp_write(rt2x00dev, 178, 0xFF);
7095 	rt2800_bbp_write(rt2x00dev, 106, 0x13);
7096 
7097 	/* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
7098 	rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
7099 	rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
7100 	rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
7101 	rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
7102 	rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
7103 	rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
7104 	rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
7105 	rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
7106 	rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
7107 	rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
7108 	rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
7109 	rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
7110 	rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
7111 	rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
7112 	rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
7113 	rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
7114 	rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
7115 	rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
7116 	rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
7117 	rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
7118 	rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
7119 	rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
7120 	rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
7121 	rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
7122 	rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
7123 	rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
7124 	rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
7125 	rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
7126 	rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
7127 	rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
7128 	rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
7129 	rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
7130 	rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
7131 	rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
7132 	rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
7133 	rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
7134 	rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
7135 	rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
7136 	rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
7137 	rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
7138 	rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
7139 	rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
7140 	rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
7141 	rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
7142 	rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
7143 	rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
7144 	rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
7145 	rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
7146 	rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
7147 	rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
7148 	rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
7149 	rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
7150 	rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
7151 	rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
7152 	rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
7153 	rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
7154 	rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
7155 	rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
7156 	rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
7157 	rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
7158 	rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
7159 	rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
7160 	rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
7161 	rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
7162 	rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
7163 	rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
7164 	rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
7165 	rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
7166 	rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
7167 	rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
7168 	rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
7169 	rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
7170 	rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
7171 	rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
7172 	rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
7173 	rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
7174 	rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
7175 	rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
7176 	rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
7177 	rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
7178 	rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
7179 	rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
7180 	rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
7181 
7182 	/* BBP for G band DCOC function */
7183 	rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
7184 	rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
7185 	rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
7186 	rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
7187 	rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
7188 	rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
7189 	rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
7190 	rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
7191 	rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
7192 	rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
7193 	rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
7194 	rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
7195 	rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
7196 	rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
7197 	rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
7198 	rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
7199 	rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
7200 	rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
7201 	rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
7202 	rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
7203 
7204 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7205 }
7206 
7207 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
7208 {
7209 	unsigned int i;
7210 	u16 eeprom;
7211 	u8 reg_id;
7212 	u8 value;
7213 
7214 	if (rt2800_is_305x_soc(rt2x00dev))
7215 		rt2800_init_bbp_305x_soc(rt2x00dev);
7216 
7217 	switch (rt2x00dev->chip.rt) {
7218 	case RT2860:
7219 	case RT2872:
7220 	case RT2883:
7221 		rt2800_init_bbp_28xx(rt2x00dev);
7222 		break;
7223 	case RT3070:
7224 	case RT3071:
7225 	case RT3090:
7226 		rt2800_init_bbp_30xx(rt2x00dev);
7227 		break;
7228 	case RT3290:
7229 		rt2800_init_bbp_3290(rt2x00dev);
7230 		break;
7231 	case RT3352:
7232 	case RT5350:
7233 		rt2800_init_bbp_3352(rt2x00dev);
7234 		break;
7235 	case RT3390:
7236 		rt2800_init_bbp_3390(rt2x00dev);
7237 		break;
7238 	case RT3572:
7239 		rt2800_init_bbp_3572(rt2x00dev);
7240 		break;
7241 	case RT3593:
7242 		rt2800_init_bbp_3593(rt2x00dev);
7243 		return;
7244 	case RT3883:
7245 		rt2800_init_bbp_3883(rt2x00dev);
7246 		return;
7247 	case RT5390:
7248 	case RT5392:
7249 		rt2800_init_bbp_53xx(rt2x00dev);
7250 		break;
7251 	case RT5592:
7252 		rt2800_init_bbp_5592(rt2x00dev);
7253 		return;
7254 	case RT6352:
7255 		rt2800_init_bbp_6352(rt2x00dev);
7256 		break;
7257 	}
7258 
7259 	for (i = 0; i < EEPROM_BBP_SIZE; i++) {
7260 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
7261 						       EEPROM_BBP_START, i);
7262 
7263 		if (eeprom != 0xffff && eeprom != 0x0000) {
7264 			reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
7265 			value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
7266 			rt2800_bbp_write(rt2x00dev, reg_id, value);
7267 		}
7268 	}
7269 }
7270 
7271 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
7272 {
7273 	u32 reg;
7274 
7275 	reg = rt2800_register_read(rt2x00dev, OPT_14_CSR);
7276 	rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
7277 	rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
7278 }
7279 
7280 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
7281 				u8 filter_target)
7282 {
7283 	unsigned int i;
7284 	u8 bbp;
7285 	u8 rfcsr;
7286 	u8 passband;
7287 	u8 stopband;
7288 	u8 overtuned = 0;
7289 	u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
7290 
7291 	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7292 
7293 	bbp = rt2800_bbp_read(rt2x00dev, 4);
7294 	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
7295 	rt2800_bbp_write(rt2x00dev, 4, bbp);
7296 
7297 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
7298 	rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
7299 	rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
7300 
7301 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7302 	rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
7303 	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7304 
7305 	/*
7306 	 * Set power & frequency of passband test tone
7307 	 */
7308 	rt2800_bbp_write(rt2x00dev, 24, 0);
7309 
7310 	for (i = 0; i < 100; i++) {
7311 		rt2800_bbp_write(rt2x00dev, 25, 0x90);
7312 		msleep(1);
7313 
7314 		passband = rt2800_bbp_read(rt2x00dev, 55);
7315 		if (passband)
7316 			break;
7317 	}
7318 
7319 	/*
7320 	 * Set power & frequency of stopband test tone
7321 	 */
7322 	rt2800_bbp_write(rt2x00dev, 24, 0x06);
7323 
7324 	for (i = 0; i < 100; i++) {
7325 		rt2800_bbp_write(rt2x00dev, 25, 0x90);
7326 		msleep(1);
7327 
7328 		stopband = rt2800_bbp_read(rt2x00dev, 55);
7329 
7330 		if ((passband - stopband) <= filter_target) {
7331 			rfcsr24++;
7332 			overtuned += ((passband - stopband) == filter_target);
7333 		} else
7334 			break;
7335 
7336 		rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7337 	}
7338 
7339 	rfcsr24 -= !!overtuned;
7340 
7341 	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7342 	return rfcsr24;
7343 }
7344 
7345 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
7346 				       const unsigned int rf_reg)
7347 {
7348 	u8 rfcsr;
7349 
7350 	rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg);
7351 	rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
7352 	rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7353 	msleep(1);
7354 	rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
7355 	rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7356 }
7357 
7358 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
7359 {
7360 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7361 	u8 filter_tgt_bw20;
7362 	u8 filter_tgt_bw40;
7363 	u8 rfcsr, bbp;
7364 
7365 	/*
7366 	 * TODO: sync filter_tgt values with vendor driver
7367 	 */
7368 	if (rt2x00_rt(rt2x00dev, RT3070)) {
7369 		filter_tgt_bw20 = 0x16;
7370 		filter_tgt_bw40 = 0x19;
7371 	} else {
7372 		filter_tgt_bw20 = 0x13;
7373 		filter_tgt_bw40 = 0x15;
7374 	}
7375 
7376 	drv_data->calibration_bw20 =
7377 		rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
7378 	drv_data->calibration_bw40 =
7379 		rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
7380 
7381 	/*
7382 	 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
7383 	 */
7384 	drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7385 	drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7386 
7387 	/*
7388 	 * Set back to initial state
7389 	 */
7390 	rt2800_bbp_write(rt2x00dev, 24, 0);
7391 
7392 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7393 	rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
7394 	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7395 
7396 	/*
7397 	 * Set BBP back to BW20
7398 	 */
7399 	bbp = rt2800_bbp_read(rt2x00dev, 4);
7400 	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
7401 	rt2800_bbp_write(rt2x00dev, 4, bbp);
7402 }
7403 
7404 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
7405 {
7406 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7407 	u8 min_gain, rfcsr, bbp;
7408 	u16 eeprom;
7409 
7410 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
7411 
7412 	rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
7413 	if (rt2x00_rt(rt2x00dev, RT3070) ||
7414 	    rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7415 	    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
7416 	    rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7417 		if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
7418 			rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
7419 	}
7420 
7421 	min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
7422 	if (drv_data->txmixer_gain_24g >= min_gain) {
7423 		rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
7424 				  drv_data->txmixer_gain_24g);
7425 	}
7426 
7427 	rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
7428 
7429 	if (rt2x00_rt(rt2x00dev, RT3090)) {
7430 		/*  Turn off unused DAC1 and ADC1 to reduce power consumption */
7431 		bbp = rt2800_bbp_read(rt2x00dev, 138);
7432 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7433 		if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
7434 			rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
7435 		if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
7436 			rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
7437 		rt2800_bbp_write(rt2x00dev, 138, bbp);
7438 	}
7439 
7440 	if (rt2x00_rt(rt2x00dev, RT3070)) {
7441 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 27);
7442 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
7443 			rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
7444 		else
7445 			rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
7446 		rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
7447 		rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
7448 		rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
7449 		rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
7450 	} else if (rt2x00_rt(rt2x00dev, RT3071) ||
7451 		   rt2x00_rt(rt2x00dev, RT3090) ||
7452 		   rt2x00_rt(rt2x00dev, RT3390)) {
7453 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7454 		rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
7455 		rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7456 		rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7457 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
7458 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
7459 		rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7460 
7461 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 15);
7462 		rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
7463 		rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
7464 
7465 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
7466 		rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
7467 		rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
7468 
7469 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
7470 		rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
7471 		rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
7472 	}
7473 }
7474 
7475 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
7476 {
7477 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7478 	u8 rfcsr;
7479 	u8 tx_gain;
7480 
7481 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
7482 	rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
7483 	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7484 
7485 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
7486 	tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
7487 				    RFCSR17_TXMIXER_GAIN);
7488 	rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
7489 	rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
7490 
7491 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 38);
7492 	rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
7493 	rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
7494 
7495 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 39);
7496 	rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
7497 	rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
7498 
7499 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7500 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
7501 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
7502 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7503 
7504 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
7505 	rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
7506 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
7507 
7508 	/* TODO: enable stream mode */
7509 }
7510 
7511 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
7512 {
7513 	u8 reg;
7514 	u16 eeprom;
7515 
7516 	/*  Turn off unused DAC1 and ADC1 to reduce power consumption */
7517 	reg = rt2800_bbp_read(rt2x00dev, 138);
7518 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7519 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
7520 		rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
7521 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
7522 		rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
7523 	rt2800_bbp_write(rt2x00dev, 138, reg);
7524 
7525 	reg = rt2800_rfcsr_read(rt2x00dev, 38);
7526 	rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
7527 	rt2800_rfcsr_write(rt2x00dev, 38, reg);
7528 
7529 	reg = rt2800_rfcsr_read(rt2x00dev, 39);
7530 	rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
7531 	rt2800_rfcsr_write(rt2x00dev, 39, reg);
7532 
7533 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7534 
7535 	reg = rt2800_rfcsr_read(rt2x00dev, 30);
7536 	rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
7537 	rt2800_rfcsr_write(rt2x00dev, 30, reg);
7538 }
7539 
7540 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
7541 {
7542 	rt2800_rf_init_calibration(rt2x00dev, 30);
7543 
7544 	rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
7545 	rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
7546 	rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
7547 	rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
7548 	rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7549 	rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7550 	rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7551 	rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
7552 	rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
7553 	rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7554 	rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
7555 	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7556 	rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
7557 	rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
7558 	rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7559 	rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7560 	rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7561 	rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7562 	rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7563 	rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7564 	rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7565 	rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7566 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7567 	rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
7568 	rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7569 	rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
7570 	rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
7571 	rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
7572 	rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
7573 	rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
7574 	rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
7575 	rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
7576 }
7577 
7578 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
7579 {
7580 	u8 rfcsr;
7581 	u16 eeprom;
7582 	u32 reg;
7583 
7584 	/* XXX vendor driver do this only for 3070 */
7585 	rt2800_rf_init_calibration(rt2x00dev, 30);
7586 
7587 	rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7588 	rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7589 	rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7590 	rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
7591 	rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7592 	rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
7593 	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7594 	rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
7595 	rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7596 	rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7597 	rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7598 	rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7599 	rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7600 	rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7601 	rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7602 	rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7603 	rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7604 	rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
7605 	rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
7606 
7607 	if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
7608 		reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7609 		rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7610 		rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7611 		rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7612 	} else if (rt2x00_rt(rt2x00dev, RT3071) ||
7613 		   rt2x00_rt(rt2x00dev, RT3090)) {
7614 		rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
7615 
7616 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7617 		rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7618 		rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7619 
7620 		reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7621 		rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7622 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7623 		    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
7624 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
7625 			if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
7626 				rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7627 			else
7628 				rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7629 		}
7630 		rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7631 
7632 		reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7633 		rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7634 		rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7635 	}
7636 
7637 	rt2800_rx_filter_calibration(rt2x00dev);
7638 
7639 	if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
7640 	    rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7641 	    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
7642 		rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7643 
7644 	rt2800_led_open_drain_enable(rt2x00dev);
7645 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7646 }
7647 
7648 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
7649 {
7650 	u8 rfcsr;
7651 
7652 	rt2800_rf_init_calibration(rt2x00dev, 2);
7653 
7654 	rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7655 	rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7656 	rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7657 	rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7658 	rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7659 	rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
7660 	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7661 	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7662 	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7663 	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7664 	rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7665 	rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
7666 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7667 	rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
7668 	rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7669 	rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7670 	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7671 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7672 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7673 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7674 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7675 	rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
7676 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7677 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7678 	rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7679 	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7680 	rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7681 	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7682 	rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7683 	rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
7684 	rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7685 	rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7686 	rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7687 	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7688 	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7689 	rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
7690 	rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7691 	rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7692 	rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7693 	rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7694 	rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
7695 	rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7696 	rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7697 	rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
7698 	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7699 	rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
7700 
7701 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 29);
7702 	rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
7703 	rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
7704 
7705 	rt2800_led_open_drain_enable(rt2x00dev);
7706 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7707 }
7708 
7709 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
7710 {
7711 	int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0,
7712 				  &rt2x00dev->cap_flags);
7713 	int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1,
7714 				  &rt2x00dev->cap_flags);
7715 	u8 rfcsr;
7716 
7717 	rt2800_rf_init_calibration(rt2x00dev, 30);
7718 
7719 	rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7720 	rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7721 	rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7722 	rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
7723 	rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7724 	rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7725 	rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
7726 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7727 	rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7728 	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7729 	rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
7730 	rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
7731 	rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
7732 	rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
7733 	rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
7734 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7735 	rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
7736 	rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
7737 	rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7738 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7739 	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7740 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7741 	rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7742 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7743 	rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7744 	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7745 	rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7746 	rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
7747 	rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
7748 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7749 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7750 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7751 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7752 	rfcsr = 0x01;
7753 	if (tx0_ext_pa)
7754 		rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1);
7755 	if (tx1_ext_pa)
7756 		rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1);
7757 	rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
7758 	rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
7759 	rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
7760 	rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
7761 	rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
7762 	rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
7763 	rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
7764 	rfcsr = 0x52;
7765 	if (!tx0_ext_pa) {
7766 		rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1);
7767 		rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1);
7768 	}
7769 	rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
7770 	rfcsr = 0x52;
7771 	if (!tx1_ext_pa) {
7772 		rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1);
7773 		rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1);
7774 	}
7775 	rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
7776 	rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
7777 	rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
7778 	rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
7779 	rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
7780 	rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
7781 	rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
7782 	rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
7783 	rfcsr = 0x2d;
7784 	if (tx0_ext_pa)
7785 		rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1);
7786 	if (tx1_ext_pa)
7787 		rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1);
7788 	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7789 	rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f));
7790 	rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00));
7791 	rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52));
7792 	rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b));
7793 	rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f));
7794 	rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00));
7795 	rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52));
7796 	rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b));
7797 	rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
7798 	rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
7799 	rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
7800 	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7801 	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7802 
7803 	rt2800_rx_filter_calibration(rt2x00dev);
7804 	rt2800_led_open_drain_enable(rt2x00dev);
7805 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7806 }
7807 
7808 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
7809 {
7810 	u32 reg;
7811 
7812 	rt2800_rf_init_calibration(rt2x00dev, 30);
7813 
7814 	rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
7815 	rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
7816 	rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7817 	rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
7818 	rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7819 	rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
7820 	rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
7821 	rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
7822 	rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
7823 	rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
7824 	rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
7825 	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7826 	rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
7827 	rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
7828 	rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7829 	rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7830 	rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
7831 	rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
7832 	rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
7833 	rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
7834 	rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
7835 	rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
7836 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7837 	rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
7838 	rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7839 	rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
7840 	rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7841 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7842 	rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
7843 	rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
7844 	rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
7845 	rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
7846 
7847 	reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7848 	rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7849 	rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7850 
7851 	rt2800_rx_filter_calibration(rt2x00dev);
7852 
7853 	if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
7854 		rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7855 
7856 	rt2800_led_open_drain_enable(rt2x00dev);
7857 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7858 }
7859 
7860 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
7861 {
7862 	u8 rfcsr;
7863 	u32 reg;
7864 
7865 	rt2800_rf_init_calibration(rt2x00dev, 30);
7866 
7867 	rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
7868 	rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
7869 	rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7870 	rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
7871 	rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
7872 	rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
7873 	rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
7874 	rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
7875 	rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
7876 	rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
7877 	rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
7878 	rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
7879 	rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
7880 	rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
7881 	rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7882 	rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
7883 	rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
7884 	rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
7885 	rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
7886 	rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
7887 	rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
7888 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7889 	rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
7890 	rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7891 	rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
7892 	rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7893 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7894 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7895 	rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
7896 	rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
7897 	rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
7898 
7899 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7900 	rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7901 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7902 
7903 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7904 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7905 	rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7906 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7907 	msleep(1);
7908 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7909 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7910 	rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7911 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7912 
7913 	rt2800_rx_filter_calibration(rt2x00dev);
7914 	rt2800_led_open_drain_enable(rt2x00dev);
7915 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7916 }
7917 
7918 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
7919 {
7920 	u8 bbp;
7921 	bool txbf_enabled = false; /* FIXME */
7922 
7923 	bbp = rt2800_bbp_read(rt2x00dev, 105);
7924 	if (rt2x00dev->default_ant.rx_chain_num == 1)
7925 		rt2x00_set_field8(&bbp, BBP105_MLD, 0);
7926 	else
7927 		rt2x00_set_field8(&bbp, BBP105_MLD, 1);
7928 	rt2800_bbp_write(rt2x00dev, 105, bbp);
7929 
7930 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7931 
7932 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
7933 	rt2800_bbp_write(rt2x00dev, 82, 0x82);
7934 	rt2800_bbp_write(rt2x00dev, 106, 0x05);
7935 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
7936 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
7937 	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
7938 	rt2800_bbp_write(rt2x00dev, 47, 0x48);
7939 	rt2800_bbp_write(rt2x00dev, 120, 0x50);
7940 
7941 	if (txbf_enabled)
7942 		rt2800_bbp_write(rt2x00dev, 163, 0xbd);
7943 	else
7944 		rt2800_bbp_write(rt2x00dev, 163, 0x9d);
7945 
7946 	/* SNR mapping */
7947 	rt2800_bbp_write(rt2x00dev, 142, 6);
7948 	rt2800_bbp_write(rt2x00dev, 143, 160);
7949 	rt2800_bbp_write(rt2x00dev, 142, 7);
7950 	rt2800_bbp_write(rt2x00dev, 143, 161);
7951 	rt2800_bbp_write(rt2x00dev, 142, 8);
7952 	rt2800_bbp_write(rt2x00dev, 143, 162);
7953 
7954 	/* ADC/DAC control */
7955 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
7956 
7957 	/* RX AGC energy lower bound in log2 */
7958 	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
7959 
7960 	/* FIXME: BBP 105 owerwrite? */
7961 	rt2800_bbp_write(rt2x00dev, 105, 0x04);
7962 
7963 }
7964 
7965 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
7966 {
7967 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7968 	u32 reg;
7969 	u8 rfcsr;
7970 
7971 	/* Disable GPIO #4 and #7 function for LAN PE control */
7972 	reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7973 	rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
7974 	rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
7975 	rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7976 
7977 	/* Initialize default register values */
7978 	rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
7979 	rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
7980 	rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7981 	rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
7982 	rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7983 	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7984 	rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
7985 	rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
7986 	rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
7987 	rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
7988 	rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
7989 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7990 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7991 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7992 	rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
7993 	rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
7994 	rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
7995 	rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
7996 	rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
7997 	rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
7998 	rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
7999 	rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
8000 	rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
8001 	rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
8002 	rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
8003 	rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
8004 	rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
8005 	rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
8006 	rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
8007 	rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
8008 	rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
8009 	rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
8010 
8011 	/* Initiate calibration */
8012 	/* TODO: use rt2800_rf_init_calibration ? */
8013 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
8014 	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
8015 	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8016 
8017 	rt2800_freq_cal_mode1(rt2x00dev);
8018 
8019 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
8020 	rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
8021 	rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
8022 
8023 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
8024 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
8025 	rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
8026 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8027 	usleep_range(1000, 1500);
8028 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
8029 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
8030 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8031 
8032 	/* Set initial values for RX filter calibration */
8033 	drv_data->calibration_bw20 = 0x1f;
8034 	drv_data->calibration_bw40 = 0x2f;
8035 
8036 	/* Save BBP 25 & 26 values for later use in channel switching */
8037 	drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
8038 	drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
8039 
8040 	rt2800_led_open_drain_enable(rt2x00dev);
8041 	rt2800_normal_mode_setup_3593(rt2x00dev);
8042 
8043 	rt3593_post_bbp_init(rt2x00dev);
8044 
8045 	/* TODO: enable stream mode support */
8046 }
8047 
8048 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
8049 {
8050 	rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
8051 	rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
8052 	rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
8053 	rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
8054 	rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
8055 	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8056 	rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8057 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8058 	rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
8059 	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
8060 	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8061 	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8062 	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8063 	if (rt2800_clk_is_20mhz(rt2x00dev))
8064 		rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
8065 	else
8066 		rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8067 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8068 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8069 	rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
8070 	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8071 	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8072 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8073 	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8074 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8075 	rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
8076 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8077 	rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8078 	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8079 	rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8080 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8081 	rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
8082 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8083 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8084 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8085 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8086 	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8087 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8088 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8089 	rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8090 	rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8091 	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8092 	rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8093 	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8094 	rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8095 	rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8096 	rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
8097 	rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
8098 	rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8099 	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8100 	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8101 	rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
8102 	rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
8103 	rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
8104 	rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8105 	rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8106 	rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8107 	rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8108 	rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
8109 	rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8110 	rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8111 	rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
8112 	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8113 	rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8114 	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8115 	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8116 }
8117 
8118 static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev)
8119 {
8120 	u8 rfcsr;
8121 
8122 	/* TODO: get the actual ECO value from the SoC */
8123 	const unsigned int eco = 5;
8124 
8125 	rt2800_rf_init_calibration(rt2x00dev, 2);
8126 
8127 	rt2800_rfcsr_write(rt2x00dev, 0, 0xe0);
8128 	rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8129 	rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
8130 	rt2800_rfcsr_write(rt2x00dev, 3, 0x20);
8131 	rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
8132 	rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
8133 	rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
8134 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8135 	rt2800_rfcsr_write(rt2x00dev, 8, 0x5b);
8136 	rt2800_rfcsr_write(rt2x00dev, 9, 0x08);
8137 	rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
8138 	rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
8139 	rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
8140 	rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
8141 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8142 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8143 	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8144 
8145 	/* RFCSR 17 will be initialized later based on the
8146 	 * frequency offset stored in the EEPROM
8147 	 */
8148 
8149 	rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
8150 	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8151 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8152 	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8153 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8154 	rt2800_rfcsr_write(rt2x00dev, 23, 0xc0);
8155 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8156 	rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8157 	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8158 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8159 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8160 	rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
8161 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8162 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8163 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8164 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8165 	rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
8166 	rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8167 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8168 	rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8169 	rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
8170 	rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
8171 	rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8172 	rt2800_rfcsr_write(rt2x00dev, 41, 0x00);
8173 	rt2800_rfcsr_write(rt2x00dev, 42, 0x00);
8174 	rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8175 	rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
8176 	rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
8177 	rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
8178 	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8179 	rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
8180 	rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
8181 	rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
8182 	rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
8183 	rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
8184 	rt2800_rfcsr_write(rt2x00dev, 53, 0x76);
8185 	rt2800_rfcsr_write(rt2x00dev, 54, 0x76);
8186 	rt2800_rfcsr_write(rt2x00dev, 55, 0x76);
8187 	rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
8188 	rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
8189 	rt2800_rfcsr_write(rt2x00dev, 58, 0x00);
8190 	rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
8191 	rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
8192 	rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
8193 	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8194 	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8195 
8196 	/* TODO: rx filter calibration? */
8197 
8198 	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
8199 
8200 	rt2800_bbp_write(rt2x00dev, 163, 0x9d);
8201 
8202 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
8203 
8204 	rt2800_bbp_write(rt2x00dev, 179, 0x02);
8205 	rt2800_bbp_write(rt2x00dev, 180, 0x00);
8206 	rt2800_bbp_write(rt2x00dev, 182, 0x40);
8207 	rt2800_bbp_write(rt2x00dev, 180, 0x01);
8208 	rt2800_bbp_write(rt2x00dev, 182, 0x9c);
8209 
8210 	rt2800_bbp_write(rt2x00dev, 179, 0x00);
8211 
8212 	rt2800_bbp_write(rt2x00dev, 142, 0x04);
8213 	rt2800_bbp_write(rt2x00dev, 143, 0x3b);
8214 	rt2800_bbp_write(rt2x00dev, 142, 0x06);
8215 	rt2800_bbp_write(rt2x00dev, 143, 0xa0);
8216 	rt2800_bbp_write(rt2x00dev, 142, 0x07);
8217 	rt2800_bbp_write(rt2x00dev, 143, 0xa1);
8218 	rt2800_bbp_write(rt2x00dev, 142, 0x08);
8219 	rt2800_bbp_write(rt2x00dev, 143, 0xa2);
8220 	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
8221 
8222 	if (eco == 5) {
8223 		rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
8224 		rt2800_rfcsr_write(rt2x00dev, 33, 0x32);
8225 	}
8226 
8227 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
8228 	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0);
8229 	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
8230 	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8231 	msleep(1);
8232 	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
8233 	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8234 
8235 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
8236 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
8237 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
8238 
8239 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
8240 	rfcsr |= 0xc0;
8241 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
8242 
8243 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
8244 	rfcsr |= 0x20;
8245 	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
8246 
8247 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 46);
8248 	rfcsr |= 0x20;
8249 	rt2800_rfcsr_write(rt2x00dev, 46, rfcsr);
8250 
8251 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
8252 	rfcsr &= ~0xee;
8253 	rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
8254 }
8255 
8256 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
8257 {
8258 	rt2800_rf_init_calibration(rt2x00dev, 2);
8259 
8260 	rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
8261 	rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8262 	rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8263 	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8264 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8265 		rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8266 	else
8267 		rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
8268 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8269 	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8270 	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8271 	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8272 	rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8273 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8274 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8275 	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8276 	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8277 	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8278 
8279 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8280 	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8281 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8282 	rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
8283 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8284 	if (rt2x00_is_usb(rt2x00dev) &&
8285 	    rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8286 		rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8287 	else
8288 		rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
8289 	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8290 	rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8291 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8292 	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8293 
8294 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8295 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8296 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8297 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8298 	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8299 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8300 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8301 	rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8302 	rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8303 	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8304 
8305 	rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8306 	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8307 	rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
8308 	rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
8309 	rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8310 	rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8311 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8312 		rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8313 	else
8314 		rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
8315 	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8316 	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8317 	rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8318 
8319 	rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8320 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8321 		rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8322 	else
8323 		rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
8324 	rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
8325 	rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
8326 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8327 		rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
8328 	else
8329 		rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
8330 	rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
8331 	rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
8332 	rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
8333 
8334 	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8335 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
8336 		if (rt2x00_is_usb(rt2x00dev))
8337 			rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8338 		else
8339 			rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
8340 	} else {
8341 		if (rt2x00_is_usb(rt2x00dev))
8342 			rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
8343 		else
8344 			rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
8345 	}
8346 	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8347 	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8348 
8349 	rt2800_normal_mode_setup_5xxx(rt2x00dev);
8350 
8351 	rt2800_led_open_drain_enable(rt2x00dev);
8352 }
8353 
8354 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
8355 {
8356 	rt2800_rf_init_calibration(rt2x00dev, 2);
8357 
8358 	rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
8359 	rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8360 	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8361 	rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8362 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8363 	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8364 	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8365 	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8366 	rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8367 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8368 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8369 	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8370 	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8371 	rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
8372 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8373 	rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
8374 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8375 	rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
8376 	rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
8377 	rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8378 	rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8379 	rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8380 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8381 	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8382 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8383 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8384 	rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
8385 	rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8386 	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8387 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8388 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8389 	rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8390 	rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
8391 	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8392 	rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
8393 	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8394 	rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8395 	rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8396 	rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8397 	rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8398 	rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8399 	rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
8400 	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8401 	rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8402 	rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
8403 	rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
8404 	rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
8405 	rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
8406 	rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8407 	rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8408 	rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
8409 	rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8410 	rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8411 	rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
8412 	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8413 	rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
8414 	rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
8415 	rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8416 
8417 	rt2800_normal_mode_setup_5xxx(rt2x00dev);
8418 
8419 	rt2800_led_open_drain_enable(rt2x00dev);
8420 }
8421 
8422 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
8423 {
8424 	rt2800_rf_init_calibration(rt2x00dev, 30);
8425 
8426 	rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
8427 	rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
8428 	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8429 	rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
8430 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8431 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8432 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8433 	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8434 	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8435 	rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
8436 	rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
8437 	rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
8438 	rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8439 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8440 	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8441 	rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8442 	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8443 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8444 	rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
8445 	rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
8446 	rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8447 
8448 	rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8449 	msleep(1);
8450 
8451 	rt2800_freq_cal_mode1(rt2x00dev);
8452 
8453 	/* Enable DC filter */
8454 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
8455 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
8456 
8457 	rt2800_normal_mode_setup_5xxx(rt2x00dev);
8458 
8459 	if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
8460 		rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8461 
8462 	rt2800_led_open_drain_enable(rt2x00dev);
8463 }
8464 
8465 static void rt2800_rf_self_txdc_cal(struct rt2x00_dev *rt2x00dev)
8466 {
8467 	u8 rfb5r1_org, rfb7r1_org, rfvalue;
8468 	u32 mac0518, mac051c, mac0528, mac052c;
8469 	u8 i;
8470 
8471 	mac0518 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8472 	mac051c = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8473 	mac0528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
8474 	mac052c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
8475 
8476 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0);
8477 	rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0);
8478 
8479 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0xC);
8480 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x3306);
8481 	rt2800_register_write(rt2x00dev, RF_CONTROL2, 0x3330);
8482 	rt2800_register_write(rt2x00dev, RF_BYPASS2, 0xfffff);
8483 	rfb5r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8484 	rfb7r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1);
8485 
8486 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, 0x4);
8487 	for (i = 0; i < 100; ++i) {
8488 		usleep_range(50, 100);
8489 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8490 		if ((rfvalue & 0x04) != 0x4)
8491 			break;
8492 	}
8493 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rfb5r1_org);
8494 
8495 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, 0x4);
8496 	for (i = 0; i < 100; ++i) {
8497 		usleep_range(50, 100);
8498 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1);
8499 		if ((rfvalue & 0x04) != 0x4)
8500 			break;
8501 	}
8502 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, rfb7r1_org);
8503 
8504 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0);
8505 	rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0);
8506 	rt2800_register_write(rt2x00dev, RF_CONTROL0, mac0518);
8507 	rt2800_register_write(rt2x00dev, RF_BYPASS0, mac051c);
8508 	rt2800_register_write(rt2x00dev, RF_CONTROL2, mac0528);
8509 	rt2800_register_write(rt2x00dev, RF_BYPASS2, mac052c);
8510 }
8511 
8512 static int rt2800_calcrcalibrationcode(struct rt2x00_dev *rt2x00dev, int d1, int d2)
8513 {
8514 	int calcode = ((d2 - d1) * 1000) / 43;
8515 
8516 	if ((calcode % 10) >= 5)
8517 		calcode += 10;
8518 	calcode = (calcode / 10);
8519 
8520 	return calcode;
8521 }
8522 
8523 static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev)
8524 {
8525 	u32 savemacsysctrl;
8526 	u8 saverfb0r1, saverfb0r34, saverfb0r35;
8527 	u8 saverfb5r4, saverfb5r17, saverfb5r18;
8528 	u8 saverfb5r19, saverfb5r20;
8529 	u8 savebbpr22, savebbpr47, savebbpr49;
8530 	u8 bytevalue = 0;
8531 	int rcalcode;
8532 	u8 r_cal_code = 0;
8533 	s8 d1 = 0, d2 = 0;
8534 	u8 rfvalue;
8535 	u32 MAC_RF_BYPASS0, MAC_RF_CONTROL0, MAC_PWR_PIN_CFG;
8536 	u32 maccfg;
8537 
8538 	saverfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
8539 	saverfb0r34 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 34);
8540 	saverfb0r35 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
8541 	saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8542 	saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8543 	saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
8544 	saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
8545 	saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
8546 
8547 	savebbpr22 = rt2800_bbp_read(rt2x00dev, 22);
8548 	savebbpr47 = rt2800_bbp_read(rt2x00dev, 47);
8549 	savebbpr49 = rt2800_bbp_read(rt2x00dev, 49);
8550 
8551 	savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8552 	MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8553 	MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8554 	MAC_PWR_PIN_CFG = rt2800_register_read(rt2x00dev, PWR_PIN_CFG);
8555 
8556 	maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8557 	maccfg &= (~0x04);
8558 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
8559 
8560 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
8561 		rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n");
8562 
8563 	maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8564 	maccfg &= (~0x04);
8565 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
8566 
8567 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
8568 		rt2x00_warn(rt2x00dev, "Wait MAC Rx Status to MAX !!!\n");
8569 
8570 	rfvalue = (MAC_RF_BYPASS0 | 0x3004);
8571 	rt2800_register_write(rt2x00dev, RF_BYPASS0, rfvalue);
8572 	rfvalue = (MAC_RF_CONTROL0 | (~0x3002));
8573 	rt2800_register_write(rt2x00dev, RF_CONTROL0, rfvalue);
8574 
8575 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x27);
8576 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
8577 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0x83);
8578 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x00);
8579 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
8580 
8581 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x00);
8582 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, 0x13);
8583 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
8584 
8585 	rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x1);
8586 
8587 	rt2800_bbp_write(rt2x00dev, 47, 0x04);
8588 	rt2800_bbp_write(rt2x00dev, 22, 0x80);
8589 	usleep_range(100, 200);
8590 	bytevalue = rt2800_bbp_read(rt2x00dev, 49);
8591 	if (bytevalue > 128)
8592 		d1 = bytevalue - 256;
8593 	else
8594 		d1 = (s8)bytevalue;
8595 	rt2800_bbp_write(rt2x00dev, 22, 0x0);
8596 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x01);
8597 
8598 	rt2800_bbp_write(rt2x00dev, 22, 0x80);
8599 	usleep_range(100, 200);
8600 	bytevalue = rt2800_bbp_read(rt2x00dev, 49);
8601 	if (bytevalue > 128)
8602 		d2 = bytevalue - 256;
8603 	else
8604 		d2 = (s8)bytevalue;
8605 	rt2800_bbp_write(rt2x00dev, 22, 0x0);
8606 
8607 	rcalcode = rt2800_calcrcalibrationcode(rt2x00dev, d1, d2);
8608 	if (rcalcode < 0)
8609 		r_cal_code = 256 + rcalcode;
8610 	else
8611 		r_cal_code = (u8)rcalcode;
8612 
8613 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 7, r_cal_code);
8614 
8615 	rt2800_bbp_write(rt2x00dev, 22, 0x0);
8616 
8617 	bytevalue = rt2800_bbp_read(rt2x00dev, 21);
8618 	bytevalue |= 0x1;
8619 	rt2800_bbp_write(rt2x00dev, 21, bytevalue);
8620 	bytevalue = rt2800_bbp_read(rt2x00dev, 21);
8621 	bytevalue &= (~0x1);
8622 	rt2800_bbp_write(rt2x00dev, 21, bytevalue);
8623 
8624 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, saverfb0r1);
8625 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, saverfb0r34);
8626 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, saverfb0r35);
8627 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4);
8628 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
8629 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
8630 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
8631 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
8632 
8633 	rt2800_bbp_write(rt2x00dev, 22, savebbpr22);
8634 	rt2800_bbp_write(rt2x00dev, 47, savebbpr47);
8635 	rt2800_bbp_write(rt2x00dev, 49, savebbpr49);
8636 
8637 	rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
8638 	rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
8639 
8640 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
8641 	rt2800_register_write(rt2x00dev, PWR_PIN_CFG, MAC_PWR_PIN_CFG);
8642 }
8643 
8644 static void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev)
8645 {
8646 	u8 bbpreg = 0;
8647 	u32 macvalue = 0;
8648 	u8 saverfb0r2, saverfb5r4, saverfb7r4, rfvalue;
8649 	int i;
8650 
8651 	saverfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
8652 	rfvalue = saverfb0r2;
8653 	rfvalue |= 0x03;
8654 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfvalue);
8655 
8656 	rt2800_bbp_write(rt2x00dev, 158, 141);
8657 	bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8658 	bbpreg |= 0x10;
8659 	rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8660 
8661 	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8662 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x8);
8663 
8664 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
8665 		rt2x00_warn(rt2x00dev, "RF TX busy in RX RXDCOC calibration\n");
8666 
8667 	saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8668 	saverfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
8669 	saverfb5r4 = saverfb5r4 & (~0x40);
8670 	saverfb7r4 = saverfb7r4 & (~0x40);
8671 	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x64);
8672 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4);
8673 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, saverfb7r4);
8674 
8675 	rt2800_bbp_write(rt2x00dev, 158, 141);
8676 	bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8677 	bbpreg = bbpreg & (~0x40);
8678 	rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8679 	bbpreg |= 0x48;
8680 	rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8681 
8682 	for (i = 0; i < 10000; i++) {
8683 		bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8684 		if ((bbpreg & 0x40) == 0)
8685 			break;
8686 		usleep_range(50, 100);
8687 	}
8688 
8689 	bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8690 	bbpreg = bbpreg & (~0x40);
8691 	rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8692 
8693 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
8694 
8695 	rt2800_bbp_write(rt2x00dev, 158, 141);
8696 	bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8697 	bbpreg &= (~0x10);
8698 	rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8699 
8700 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, saverfb0r2);
8701 }
8702 
8703 static u32 rt2800_do_sqrt_accumulation(u32 si)
8704 {
8705 	u32 root, root_pre, bit;
8706 	s8 i;
8707 
8708 	bit = 1 << 15;
8709 	root = 0;
8710 	for (i = 15; i >= 0; i = i - 1) {
8711 		root_pre = root + bit;
8712 		if ((root_pre * root_pre) <= si)
8713 			root = root_pre;
8714 		bit = bit >> 1;
8715 	}
8716 
8717 	return root;
8718 }
8719 
8720 static void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev)
8721 {
8722 	u8 rfb0r1, rfb0r2, rfb0r42;
8723 	u8 rfb4r0, rfb4r19;
8724 	u8 rfb5r3, rfb5r4, rfb5r17, rfb5r18, rfb5r19, rfb5r20;
8725 	u8 rfb6r0, rfb6r19;
8726 	u8 rfb7r3, rfb7r4, rfb7r17, rfb7r18, rfb7r19, rfb7r20;
8727 
8728 	u8 bbp1, bbp4;
8729 	u8 bbpr241, bbpr242;
8730 	u32 i;
8731 	u8 ch_idx;
8732 	u8 bbpval;
8733 	u8 rfval, vga_idx = 0;
8734 	int mi = 0, mq = 0, si = 0, sq = 0, riq = 0;
8735 	int sigma_i, sigma_q, r_iq, g_rx;
8736 	int g_imb;
8737 	int ph_rx;
8738 	u32 savemacsysctrl = 0;
8739 	u32 orig_RF_CONTROL0 = 0;
8740 	u32 orig_RF_BYPASS0 = 0;
8741 	u32 orig_RF_CONTROL1 = 0;
8742 	u32 orig_RF_BYPASS1 = 0;
8743 	u32 orig_RF_CONTROL3 = 0;
8744 	u32 orig_RF_BYPASS3 = 0;
8745 	u32 bbpval1 = 0;
8746 	static const u8 rf_vga_table[] = {0x20, 0x21, 0x22, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f};
8747 
8748 	savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8749 	orig_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8750 	orig_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8751 	orig_RF_CONTROL1 = rt2800_register_read(rt2x00dev, RF_CONTROL1);
8752 	orig_RF_BYPASS1 = rt2800_register_read(rt2x00dev, RF_BYPASS1);
8753 	orig_RF_CONTROL3 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
8754 	orig_RF_BYPASS3 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
8755 
8756 	bbp1 = rt2800_bbp_read(rt2x00dev, 1);
8757 	bbp4 = rt2800_bbp_read(rt2x00dev, 4);
8758 
8759 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x0);
8760 
8761 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
8762 		rt2x00_warn(rt2x00dev, "Timeout waiting for MAC status in RXIQ calibration\n");
8763 
8764 	bbpval = bbp4 & (~0x18);
8765 	bbpval = bbp4 | 0x00;
8766 	rt2800_bbp_write(rt2x00dev, 4, bbpval);
8767 
8768 	bbpval = rt2800_bbp_read(rt2x00dev, 21);
8769 	bbpval = bbpval | 1;
8770 	rt2800_bbp_write(rt2x00dev, 21, bbpval);
8771 	bbpval = bbpval & 0xfe;
8772 	rt2800_bbp_write(rt2x00dev, 21, bbpval);
8773 
8774 	rt2800_register_write(rt2x00dev, RF_CONTROL1, 0x00000202);
8775 	rt2800_register_write(rt2x00dev, RF_BYPASS1, 0x00000303);
8776 	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
8777 		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0101);
8778 	else
8779 		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0000);
8780 
8781 	rt2800_register_write(rt2x00dev, RF_BYPASS3, 0xf1f1);
8782 
8783 	rfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
8784 	rfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
8785 	rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
8786 	rfb4r0 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
8787 	rfb4r19 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 19);
8788 	rfb5r3 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8789 	rfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8790 	rfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8791 	rfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
8792 	rfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
8793 	rfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
8794 
8795 	rfb6r0 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
8796 	rfb6r19 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 19);
8797 	rfb7r3 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
8798 	rfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
8799 	rfb7r17 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
8800 	rfb7r18 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
8801 	rfb7r19 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
8802 	rfb7r20 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
8803 
8804 	rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x87);
8805 	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0x27);
8806 	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x38);
8807 	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x38);
8808 	rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x80);
8809 	rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0xC1);
8810 	rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x60);
8811 	rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
8812 
8813 	rt2800_bbp_write(rt2x00dev, 23, 0x0);
8814 	rt2800_bbp_write(rt2x00dev, 24, 0x0);
8815 
8816 	rt2800_bbp_dcoc_write(rt2x00dev, 5, 0x0);
8817 
8818 	bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
8819 	bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
8820 
8821 	rt2800_bbp_write(rt2x00dev, 241, 0x10);
8822 	rt2800_bbp_write(rt2x00dev, 242, 0x84);
8823 	rt2800_bbp_write(rt2x00dev, 244, 0x31);
8824 
8825 	bbpval = rt2800_bbp_dcoc_read(rt2x00dev, 3);
8826 	bbpval = bbpval & (~0x7);
8827 	rt2800_bbp_dcoc_write(rt2x00dev, 3, bbpval);
8828 
8829 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
8830 	udelay(1);
8831 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
8832 	usleep_range(1, 200);
8833 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003376);
8834 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
8835 	udelay(1);
8836 	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
8837 		rt2800_bbp_write(rt2x00dev, 23, 0x06);
8838 		rt2800_bbp_write(rt2x00dev, 24, 0x06);
8839 	} else {
8840 		rt2800_bbp_write(rt2x00dev, 23, 0x02);
8841 		rt2800_bbp_write(rt2x00dev, 24, 0x02);
8842 	}
8843 
8844 	for (ch_idx = 0; ch_idx < 2; ch_idx = ch_idx + 1) {
8845 		if (ch_idx == 0) {
8846 			rfval = rfb0r1 & (~0x3);
8847 			rfval = rfb0r1 | 0x1;
8848 			rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
8849 			rfval = rfb0r2 & (~0x33);
8850 			rfval = rfb0r2 | 0x11;
8851 			rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
8852 			rfval = rfb0r42 & (~0x50);
8853 			rfval = rfb0r42 | 0x10;
8854 			rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
8855 
8856 			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
8857 			udelay(1);
8858 
8859 			bbpval = bbp1 & (~0x18);
8860 			bbpval = bbpval | 0x00;
8861 			rt2800_bbp_write(rt2x00dev, 1, bbpval);
8862 
8863 			rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x00);
8864 		} else {
8865 			rfval = rfb0r1 & (~0x3);
8866 			rfval = rfb0r1 | 0x2;
8867 			rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
8868 			rfval = rfb0r2 & (~0x33);
8869 			rfval = rfb0r2 | 0x22;
8870 			rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
8871 			rfval = rfb0r42 & (~0x50);
8872 			rfval = rfb0r42 | 0x40;
8873 			rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
8874 
8875 			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002006);
8876 			udelay(1);
8877 
8878 			bbpval = bbp1 & (~0x18);
8879 			bbpval = bbpval | 0x08;
8880 			rt2800_bbp_write(rt2x00dev, 1, bbpval);
8881 
8882 			rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x01);
8883 		}
8884 		usleep_range(500, 1500);
8885 
8886 		vga_idx = 0;
8887 		while (vga_idx < 11) {
8888 			rt2800_rfcsr_write_dccal(rt2x00dev, 3, rf_vga_table[vga_idx]);
8889 			rt2800_rfcsr_write_dccal(rt2x00dev, 4, rf_vga_table[vga_idx]);
8890 
8891 			rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x93);
8892 
8893 			for (i = 0; i < 10000; i++) {
8894 				bbpval = rt2800_bbp_read(rt2x00dev, 159);
8895 				if ((bbpval & 0xff) == 0x93)
8896 					usleep_range(50, 100);
8897 				else
8898 					break;
8899 				}
8900 
8901 			if ((bbpval & 0xff) == 0x93) {
8902 				rt2x00_warn(rt2x00dev, "Fatal Error: Calibration doesn't finish");
8903 				goto restore_value;
8904 			}
8905 			for (i = 0; i < 5; i++) {
8906 				u32 bbptemp = 0;
8907 				u8 value = 0;
8908 				int result = 0;
8909 
8910 				rt2800_bbp_write(rt2x00dev, 158, 0x1e);
8911 				rt2800_bbp_write(rt2x00dev, 159, i);
8912 				rt2800_bbp_write(rt2x00dev, 158, 0x22);
8913 				value = rt2800_bbp_read(rt2x00dev, 159);
8914 				bbptemp = bbptemp + (value << 24);
8915 				rt2800_bbp_write(rt2x00dev, 158, 0x21);
8916 				value = rt2800_bbp_read(rt2x00dev, 159);
8917 				bbptemp = bbptemp + (value << 16);
8918 				rt2800_bbp_write(rt2x00dev, 158, 0x20);
8919 				value = rt2800_bbp_read(rt2x00dev, 159);
8920 				bbptemp = bbptemp + (value << 8);
8921 				rt2800_bbp_write(rt2x00dev, 158, 0x1f);
8922 				value = rt2800_bbp_read(rt2x00dev, 159);
8923 				bbptemp = bbptemp + value;
8924 
8925 				if (i < 2 && (bbptemp & 0x800000))
8926 					result = (bbptemp & 0xffffff) - 0x1000000;
8927 				else
8928 					result = bbptemp;
8929 
8930 				if (i == 0)
8931 					mi = result / 4096;
8932 				else if (i == 1)
8933 					mq = result / 4096;
8934 				else if (i == 2)
8935 					si = bbptemp / 4096;
8936 				else if (i == 3)
8937 					sq = bbptemp / 4096;
8938 				else
8939 					riq = result / 4096;
8940 			}
8941 
8942 			bbpval1 = si - mi * mi;
8943 			rt2x00_dbg(rt2x00dev,
8944 				   "RXIQ si=%d, sq=%d, riq=%d, bbpval %d, vga_idx %d",
8945 				   si, sq, riq, bbpval1, vga_idx);
8946 
8947 			if (bbpval1 >= (100 * 100))
8948 				break;
8949 
8950 			if (bbpval1 <= 100)
8951 				vga_idx = vga_idx + 9;
8952 			else if (bbpval1 <= 158)
8953 				vga_idx = vga_idx + 8;
8954 			else if (bbpval1 <= 251)
8955 				vga_idx = vga_idx + 7;
8956 			else if (bbpval1 <= 398)
8957 				vga_idx = vga_idx + 6;
8958 			else if (bbpval1 <= 630)
8959 				vga_idx = vga_idx + 5;
8960 			else if (bbpval1 <= 1000)
8961 				vga_idx = vga_idx + 4;
8962 			else if (bbpval1 <= 1584)
8963 				vga_idx = vga_idx + 3;
8964 			else if (bbpval1 <= 2511)
8965 				vga_idx = vga_idx + 2;
8966 			else
8967 				vga_idx = vga_idx + 1;
8968 		}
8969 
8970 		sigma_i = rt2800_do_sqrt_accumulation(100 * (si - mi * mi));
8971 		sigma_q = rt2800_do_sqrt_accumulation(100 * (sq - mq * mq));
8972 		r_iq = 10 * (riq - (mi * mq));
8973 
8974 		rt2x00_dbg(rt2x00dev, "Sigma_i=%d, Sigma_q=%d, R_iq=%d", sigma_i, sigma_q, r_iq);
8975 
8976 		if (sigma_i <= 1400 && sigma_i >= 1000 &&
8977 		    (sigma_i - sigma_q) <= 112 &&
8978 		    (sigma_i - sigma_q) >= -112 &&
8979 		    mi <= 32 && mi >= -32 &&
8980 		    mq <= 32 && mq >= -32) {
8981 			r_iq = 10 * (riq - (mi * mq));
8982 			rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n",
8983 				   sigma_i, sigma_q, r_iq);
8984 
8985 			g_rx = (1000 * sigma_q) / sigma_i;
8986 			g_imb = ((-2) * 128 * (1000 - g_rx)) / (1000 + g_rx);
8987 			ph_rx = (r_iq * 2292) / (sigma_i * sigma_q);
8988 
8989 			if (ph_rx > 20 || ph_rx < -20) {
8990 				ph_rx = 0;
8991 				rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
8992 			}
8993 
8994 			if (g_imb > 12 || g_imb < -12) {
8995 				g_imb = 0;
8996 				rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
8997 			}
8998 		} else {
8999 			g_imb = 0;
9000 			ph_rx = 0;
9001 			rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n",
9002 				   sigma_i, sigma_q, r_iq);
9003 			rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
9004 		}
9005 
9006 		if (ch_idx == 0) {
9007 			rt2800_bbp_write(rt2x00dev, 158, 0x37);
9008 			rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
9009 			rt2800_bbp_write(rt2x00dev, 158, 0x35);
9010 			rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
9011 		} else {
9012 			rt2800_bbp_write(rt2x00dev, 158, 0x55);
9013 			rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
9014 			rt2800_bbp_write(rt2x00dev, 158, 0x53);
9015 			rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
9016 		}
9017 	}
9018 
9019 restore_value:
9020 	rt2800_bbp_write(rt2x00dev, 158, 0x3);
9021 	bbpval = rt2800_bbp_read(rt2x00dev, 159);
9022 	rt2800_bbp_write(rt2x00dev, 159, (bbpval | 0x07));
9023 
9024 	rt2800_bbp_write(rt2x00dev, 158, 0x00);
9025 	rt2800_bbp_write(rt2x00dev, 159, 0x00);
9026 	rt2800_bbp_write(rt2x00dev, 1, bbp1);
9027 	rt2800_bbp_write(rt2x00dev, 4, bbp4);
9028 	rt2800_bbp_write(rt2x00dev, 241, bbpr241);
9029 	rt2800_bbp_write(rt2x00dev, 242, bbpr242);
9030 
9031 	rt2800_bbp_write(rt2x00dev, 244, 0x00);
9032 	bbpval = rt2800_bbp_read(rt2x00dev, 21);
9033 	bbpval |= 0x1;
9034 	rt2800_bbp_write(rt2x00dev, 21, bbpval);
9035 	usleep_range(10, 200);
9036 	bbpval &= 0xfe;
9037 	rt2800_bbp_write(rt2x00dev, 21, bbpval);
9038 
9039 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfb0r1);
9040 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfb0r2);
9041 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
9042 
9043 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, rfb4r0);
9044 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 19, rfb4r19);
9045 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rfb5r3);
9046 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rfb5r4);
9047 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rfb5r17);
9048 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, rfb5r18);
9049 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, rfb5r19);
9050 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, rfb5r20);
9051 
9052 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, rfb6r0);
9053 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 19, rfb6r19);
9054 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, rfb7r3);
9055 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, rfb7r4);
9056 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, rfb7r17);
9057 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, rfb7r18);
9058 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, rfb7r19);
9059 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, rfb7r20);
9060 
9061 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
9062 	udelay(1);
9063 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
9064 	udelay(1);
9065 	rt2800_register_write(rt2x00dev, RF_CONTROL0, orig_RF_CONTROL0);
9066 	udelay(1);
9067 	rt2800_register_write(rt2x00dev, RF_BYPASS0, orig_RF_BYPASS0);
9068 	rt2800_register_write(rt2x00dev, RF_CONTROL1, orig_RF_CONTROL1);
9069 	rt2800_register_write(rt2x00dev, RF_BYPASS1, orig_RF_BYPASS1);
9070 	rt2800_register_write(rt2x00dev, RF_CONTROL3, orig_RF_CONTROL3);
9071 	rt2800_register_write(rt2x00dev, RF_BYPASS3, orig_RF_BYPASS3);
9072 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
9073 }
9074 
9075 static void rt2800_rf_configstore(struct rt2x00_dev *rt2x00dev,
9076 				  struct rf_reg_pair rf_reg_record[][13], u8 chain)
9077 {
9078 	u8 rfvalue = 0;
9079 
9080 	if (chain == CHAIN_0) {
9081 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
9082 		rf_reg_record[CHAIN_0][0].bank = 0;
9083 		rf_reg_record[CHAIN_0][0].reg = 1;
9084 		rf_reg_record[CHAIN_0][0].value = rfvalue;
9085 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
9086 		rf_reg_record[CHAIN_0][1].bank = 0;
9087 		rf_reg_record[CHAIN_0][1].reg = 2;
9088 		rf_reg_record[CHAIN_0][1].value = rfvalue;
9089 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
9090 		rf_reg_record[CHAIN_0][2].bank = 0;
9091 		rf_reg_record[CHAIN_0][2].reg = 35;
9092 		rf_reg_record[CHAIN_0][2].value = rfvalue;
9093 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
9094 		rf_reg_record[CHAIN_0][3].bank = 0;
9095 		rf_reg_record[CHAIN_0][3].reg = 42;
9096 		rf_reg_record[CHAIN_0][3].value = rfvalue;
9097 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
9098 		rf_reg_record[CHAIN_0][4].bank = 4;
9099 		rf_reg_record[CHAIN_0][4].reg = 0;
9100 		rf_reg_record[CHAIN_0][4].value = rfvalue;
9101 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 2);
9102 		rf_reg_record[CHAIN_0][5].bank = 4;
9103 		rf_reg_record[CHAIN_0][5].reg = 2;
9104 		rf_reg_record[CHAIN_0][5].value = rfvalue;
9105 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 34);
9106 		rf_reg_record[CHAIN_0][6].bank = 4;
9107 		rf_reg_record[CHAIN_0][6].reg = 34;
9108 		rf_reg_record[CHAIN_0][6].value = rfvalue;
9109 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
9110 		rf_reg_record[CHAIN_0][7].bank = 5;
9111 		rf_reg_record[CHAIN_0][7].reg = 3;
9112 		rf_reg_record[CHAIN_0][7].value = rfvalue;
9113 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
9114 		rf_reg_record[CHAIN_0][8].bank = 5;
9115 		rf_reg_record[CHAIN_0][8].reg = 4;
9116 		rf_reg_record[CHAIN_0][8].value = rfvalue;
9117 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
9118 		rf_reg_record[CHAIN_0][9].bank = 5;
9119 		rf_reg_record[CHAIN_0][9].reg = 17;
9120 		rf_reg_record[CHAIN_0][9].value = rfvalue;
9121 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
9122 		rf_reg_record[CHAIN_0][10].bank = 5;
9123 		rf_reg_record[CHAIN_0][10].reg = 18;
9124 		rf_reg_record[CHAIN_0][10].value = rfvalue;
9125 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
9126 		rf_reg_record[CHAIN_0][11].bank = 5;
9127 		rf_reg_record[CHAIN_0][11].reg = 19;
9128 		rf_reg_record[CHAIN_0][11].value = rfvalue;
9129 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
9130 		rf_reg_record[CHAIN_0][12].bank = 5;
9131 		rf_reg_record[CHAIN_0][12].reg = 20;
9132 		rf_reg_record[CHAIN_0][12].value = rfvalue;
9133 	} else if (chain == CHAIN_1) {
9134 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
9135 		rf_reg_record[CHAIN_1][0].bank = 0;
9136 		rf_reg_record[CHAIN_1][0].reg = 1;
9137 		rf_reg_record[CHAIN_1][0].value = rfvalue;
9138 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
9139 		rf_reg_record[CHAIN_1][1].bank = 0;
9140 		rf_reg_record[CHAIN_1][1].reg = 2;
9141 		rf_reg_record[CHAIN_1][1].value = rfvalue;
9142 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
9143 		rf_reg_record[CHAIN_1][2].bank = 0;
9144 		rf_reg_record[CHAIN_1][2].reg = 35;
9145 		rf_reg_record[CHAIN_1][2].value = rfvalue;
9146 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
9147 		rf_reg_record[CHAIN_1][3].bank = 0;
9148 		rf_reg_record[CHAIN_1][3].reg = 42;
9149 		rf_reg_record[CHAIN_1][3].value = rfvalue;
9150 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
9151 		rf_reg_record[CHAIN_1][4].bank = 6;
9152 		rf_reg_record[CHAIN_1][4].reg = 0;
9153 		rf_reg_record[CHAIN_1][4].value = rfvalue;
9154 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 2);
9155 		rf_reg_record[CHAIN_1][5].bank = 6;
9156 		rf_reg_record[CHAIN_1][5].reg = 2;
9157 		rf_reg_record[CHAIN_1][5].value = rfvalue;
9158 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 34);
9159 		rf_reg_record[CHAIN_1][6].bank = 6;
9160 		rf_reg_record[CHAIN_1][6].reg = 34;
9161 		rf_reg_record[CHAIN_1][6].value = rfvalue;
9162 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
9163 		rf_reg_record[CHAIN_1][7].bank = 7;
9164 		rf_reg_record[CHAIN_1][7].reg = 3;
9165 		rf_reg_record[CHAIN_1][7].value = rfvalue;
9166 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
9167 		rf_reg_record[CHAIN_1][8].bank = 7;
9168 		rf_reg_record[CHAIN_1][8].reg = 4;
9169 		rf_reg_record[CHAIN_1][8].value = rfvalue;
9170 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
9171 		rf_reg_record[CHAIN_1][9].bank = 7;
9172 		rf_reg_record[CHAIN_1][9].reg = 17;
9173 		rf_reg_record[CHAIN_1][9].value = rfvalue;
9174 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
9175 		rf_reg_record[CHAIN_1][10].bank = 7;
9176 		rf_reg_record[CHAIN_1][10].reg = 18;
9177 		rf_reg_record[CHAIN_1][10].value = rfvalue;
9178 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
9179 		rf_reg_record[CHAIN_1][11].bank = 7;
9180 		rf_reg_record[CHAIN_1][11].reg = 19;
9181 		rf_reg_record[CHAIN_1][11].value = rfvalue;
9182 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
9183 		rf_reg_record[CHAIN_1][12].bank = 7;
9184 		rf_reg_record[CHAIN_1][12].reg = 20;
9185 		rf_reg_record[CHAIN_1][12].value = rfvalue;
9186 	} else {
9187 		rt2x00_warn(rt2x00dev, "Unknown chain = %u\n", chain);
9188 	}
9189 }
9190 
9191 static void rt2800_rf_configrecover(struct rt2x00_dev *rt2x00dev,
9192 				    struct rf_reg_pair rf_record[][13])
9193 {
9194 	u8 chain_index = 0, record_index = 0;
9195 	u8 bank = 0, rf_register = 0, value = 0;
9196 
9197 	for (chain_index = 0; chain_index < 2; chain_index++) {
9198 		for (record_index = 0; record_index < 13; record_index++) {
9199 			bank = rf_record[chain_index][record_index].bank;
9200 			rf_register = rf_record[chain_index][record_index].reg;
9201 			value = rf_record[chain_index][record_index].value;
9202 			rt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value);
9203 			rt2x00_dbg(rt2x00dev, "bank: %d, rf_register: %d, value: %x\n",
9204 				   bank, rf_register, value);
9205 		}
9206 	}
9207 }
9208 
9209 static void rt2800_setbbptonegenerator(struct rt2x00_dev *rt2x00dev)
9210 {
9211 	rt2800_bbp_write(rt2x00dev, 158, 0xAA);
9212 	rt2800_bbp_write(rt2x00dev, 159, 0x00);
9213 
9214 	rt2800_bbp_write(rt2x00dev, 158, 0xAB);
9215 	rt2800_bbp_write(rt2x00dev, 159, 0x0A);
9216 
9217 	rt2800_bbp_write(rt2x00dev, 158, 0xAC);
9218 	rt2800_bbp_write(rt2x00dev, 159, 0x3F);
9219 
9220 	rt2800_bbp_write(rt2x00dev, 158, 0xAD);
9221 	rt2800_bbp_write(rt2x00dev, 159, 0x3F);
9222 
9223 	rt2800_bbp_write(rt2x00dev, 244, 0x40);
9224 }
9225 
9226 static u32 rt2800_do_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx, u8 read_neg)
9227 {
9228 	u32 macvalue = 0;
9229 	int fftout_i = 0, fftout_q = 0;
9230 	u32 ptmp = 0, pint = 0;
9231 	u8 bbp = 0;
9232 	u8 tidxi;
9233 
9234 	rt2800_bbp_write(rt2x00dev, 158, 0x00);
9235 	rt2800_bbp_write(rt2x00dev, 159, 0x9b);
9236 
9237 	bbp = 0x9b;
9238 
9239 	while (bbp == 0x9b) {
9240 		usleep_range(10, 50);
9241 		bbp = rt2800_bbp_read(rt2x00dev, 159);
9242 		bbp = bbp & 0xff;
9243 	}
9244 
9245 	rt2800_bbp_write(rt2x00dev, 158, 0xba);
9246 	rt2800_bbp_write(rt2x00dev, 159, tidx);
9247 	rt2800_bbp_write(rt2x00dev, 159, tidx);
9248 	rt2800_bbp_write(rt2x00dev, 159, tidx);
9249 
9250 	macvalue = rt2800_register_read(rt2x00dev, 0x057C);
9251 
9252 	fftout_i = (macvalue >> 16);
9253 	fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
9254 	fftout_q = (macvalue & 0xffff);
9255 	fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
9256 	ptmp = (fftout_i * fftout_i);
9257 	ptmp = ptmp + (fftout_q * fftout_q);
9258 	pint = ptmp;
9259 	rt2x00_dbg(rt2x00dev, "I = %d,  Q = %d, power = %x\n", fftout_i, fftout_q, pint);
9260 	if (read_neg) {
9261 		pint = pint >> 1;
9262 		tidxi = 0x40 - tidx;
9263 		tidxi = tidxi & 0x3f;
9264 
9265 		rt2800_bbp_write(rt2x00dev, 158, 0xba);
9266 		rt2800_bbp_write(rt2x00dev, 159, tidxi);
9267 		rt2800_bbp_write(rt2x00dev, 159, tidxi);
9268 		rt2800_bbp_write(rt2x00dev, 159, tidxi);
9269 
9270 		macvalue = rt2800_register_read(rt2x00dev, 0x057C);
9271 
9272 		fftout_i = (macvalue >> 16);
9273 		fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
9274 		fftout_q = (macvalue & 0xffff);
9275 		fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
9276 		ptmp = (fftout_i * fftout_i);
9277 		ptmp = ptmp + (fftout_q * fftout_q);
9278 		ptmp = ptmp >> 1;
9279 		pint = pint + ptmp;
9280 	}
9281 
9282 	return pint;
9283 }
9284 
9285 static u32 rt2800_read_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx)
9286 {
9287 	u32 macvalue = 0;
9288 	int fftout_i = 0, fftout_q = 0;
9289 	u32 ptmp = 0, pint = 0;
9290 
9291 	rt2800_bbp_write(rt2x00dev, 158, 0xBA);
9292 	rt2800_bbp_write(rt2x00dev, 159, tidx);
9293 	rt2800_bbp_write(rt2x00dev, 159, tidx);
9294 	rt2800_bbp_write(rt2x00dev, 159, tidx);
9295 
9296 	macvalue = rt2800_register_read(rt2x00dev, 0x057C);
9297 
9298 	fftout_i = (macvalue >> 16);
9299 	fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
9300 	fftout_q = (macvalue & 0xffff);
9301 	fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
9302 	ptmp = (fftout_i * fftout_i);
9303 	ptmp = ptmp + (fftout_q * fftout_q);
9304 	pint = ptmp;
9305 
9306 	return pint;
9307 }
9308 
9309 static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc)
9310 {
9311 	u8 bbp = 0;
9312 
9313 	rt2800_bbp_write(rt2x00dev, 158, 0xb0);
9314 	bbp = alc | 0x80;
9315 	rt2800_bbp_write(rt2x00dev, 159, bbp);
9316 
9317 	if (ch_idx == 0)
9318 		bbp = (iorq == 0) ? 0xb1 : 0xb2;
9319 	else
9320 		bbp = (iorq == 0) ? 0xb8 : 0xb9;
9321 
9322 	rt2800_bbp_write(rt2x00dev, 158, bbp);
9323 	bbp = dc;
9324 	rt2800_bbp_write(rt2x00dev, 159, bbp);
9325 }
9326 
9327 static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx,
9328 			       u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2])
9329 {
9330 	u32 p0 = 0, p1 = 0, pf = 0;
9331 	s8 idx0 = 0, idx1 = 0;
9332 	u8 idxf[] = {0x00, 0x00};
9333 	u8 ibit = 0x20;
9334 	u8 iorq;
9335 	s8 bidx;
9336 
9337 	rt2800_bbp_write(rt2x00dev, 158, 0xb0);
9338 	rt2800_bbp_write(rt2x00dev, 159, 0x80);
9339 
9340 	for (bidx = 5; bidx >= 0; bidx--) {
9341 		for (iorq = 0; iorq <= 1; iorq++) {
9342 			if (idxf[iorq] == 0x20) {
9343 				idx0 = 0x20;
9344 				p0 = pf;
9345 			} else {
9346 				idx0 = idxf[iorq] - ibit;
9347 				idx0 = idx0 & 0x3F;
9348 				rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx0);
9349 				p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
9350 			}
9351 
9352 			idx1 = idxf[iorq] + (bidx == 5 ? 0 : ibit);
9353 			idx1 = idx1 & 0x3F;
9354 			rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx1);
9355 			p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
9356 
9357 			rt2x00_dbg(rt2x00dev, "alc=%u, IorQ=%u, idx_final=%2x\n",
9358 				   alc_idx, iorq, idxf[iorq]);
9359 			rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x\n",
9360 				   p0, p1, pf, idx0, idx1, ibit);
9361 
9362 			if (bidx != 5 && pf <= p0 && pf < p1) {
9363 				idxf[iorq] = idxf[iorq];
9364 			} else if (p0 < p1) {
9365 				pf = p0;
9366 				idxf[iorq] = idx0 & 0x3F;
9367 			} else {
9368 				pf = p1;
9369 				idxf[iorq] = idx1 & 0x3F;
9370 			}
9371 			rt2x00_dbg(rt2x00dev, "IorQ=%u, idx_final[%u]:%x, pf:%8x\n",
9372 				   iorq, iorq, idxf[iorq], pf);
9373 
9374 			rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idxf[iorq]);
9375 		}
9376 		ibit = ibit >> 1;
9377 	}
9378 	dc_result[ch_idx][alc_idx][0] = idxf[0];
9379 	dc_result[ch_idx][alc_idx][1] = idxf[1];
9380 }
9381 
9382 static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes)
9383 {
9384 	u32 p0 = 0, p1 = 0, pf = 0;
9385 	s8 perr = 0, gerr = 0, iq_err = 0;
9386 	s8 pef = 0, gef = 0;
9387 	s8 psta, pend;
9388 	s8 gsta, gend;
9389 
9390 	u8 ibit = 0x20;
9391 	u8 first_search = 0x00, touch_neg_max = 0x00;
9392 	s8 idx0 = 0, idx1 = 0;
9393 	u8 gop;
9394 	u8 bbp = 0;
9395 	s8 bidx;
9396 
9397 	for (bidx = 5; bidx >= 1; bidx--) {
9398 		for (gop = 0; gop < 2; gop++) {
9399 			if (gop == 1 || bidx < 4) {
9400 				if (gop == 0)
9401 					iq_err = gerr;
9402 				else
9403 					iq_err = perr;
9404 
9405 				first_search = (gop == 0) ? (bidx == 3) : (bidx == 5);
9406 				touch_neg_max = (gop) ? ((iq_err & 0x0F) == 0x08) :
9407 							((iq_err & 0x3F) == 0x20);
9408 
9409 				if (touch_neg_max) {
9410 					p0 = pf;
9411 					idx0 = iq_err;
9412 				} else {
9413 					idx0 = iq_err - ibit;
9414 					bbp = (ch_idx == 0) ? ((gop == 0) ? 0x28 : 0x29) :
9415 							      ((gop == 0) ? 0x46 : 0x47);
9416 
9417 					rt2800_bbp_write(rt2x00dev, 158, bbp);
9418 					rt2800_bbp_write(rt2x00dev, 159, idx0);
9419 
9420 					p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
9421 				}
9422 
9423 				idx1 = iq_err + (first_search ? 0 : ibit);
9424 				idx1 = (gop == 0) ? (idx1 & 0x0F) : (idx1 & 0x3F);
9425 
9426 				bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 :
9427 				      (gop == 0) ? 0x46 : 0x47;
9428 
9429 				rt2800_bbp_write(rt2x00dev, 158, bbp);
9430 				rt2800_bbp_write(rt2x00dev, 159, idx1);
9431 
9432 				p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
9433 
9434 				rt2x00_dbg(rt2x00dev,
9435 					   "p0=%x, p1=%x, pwer_final=%x, idx0=%x, idx1=%x, iq_err=%x, gop=%d, ibit=%x\n",
9436 					   p0, p1, pf, idx0, idx1, iq_err, gop, ibit);
9437 
9438 				if (!(!first_search && pf <= p0 && pf < p1)) {
9439 					if (p0 < p1) {
9440 						pf = p0;
9441 						iq_err = idx0;
9442 					} else {
9443 						pf = p1;
9444 						iq_err = idx1;
9445 					}
9446 				}
9447 
9448 				bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 :
9449 						      (gop == 0) ? 0x46 : 0x47;
9450 
9451 				rt2800_bbp_write(rt2x00dev, 158, bbp);
9452 				rt2800_bbp_write(rt2x00dev, 159, iq_err);
9453 
9454 				if (gop == 0)
9455 					gerr = iq_err;
9456 				else
9457 					perr = iq_err;
9458 
9459 				rt2x00_dbg(rt2x00dev, "IQCalibration pf=%8x (%2x, %2x) !\n",
9460 					   pf, gerr & 0x0F, perr & 0x3F);
9461 			}
9462 		}
9463 
9464 		if (bidx > 0)
9465 			ibit = (ibit >> 1);
9466 	}
9467 	gerr = (gerr & 0x08) ? (gerr & 0x0F) - 0x10 : (gerr & 0x0F);
9468 	perr = (perr & 0x20) ? (perr & 0x3F) - 0x40 : (perr & 0x3F);
9469 
9470 	gerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr;
9471 	gsta = gerr - 1;
9472 	gend = gerr + 2;
9473 
9474 	perr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr;
9475 	psta = perr - 1;
9476 	pend = perr + 2;
9477 
9478 	for (gef = gsta; gef <= gend; gef = gef + 1)
9479 		for (pef = psta; pef <= pend; pef = pef + 1) {
9480 			bbp = (ch_idx == 0) ? 0x28 : 0x46;
9481 			rt2800_bbp_write(rt2x00dev, 158, bbp);
9482 			rt2800_bbp_write(rt2x00dev, 159, gef & 0x0F);
9483 
9484 			bbp = (ch_idx == 0) ? 0x29 : 0x47;
9485 			rt2800_bbp_write(rt2x00dev, 158, bbp);
9486 			rt2800_bbp_write(rt2x00dev, 159, pef & 0x3F);
9487 
9488 			p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
9489 			if (gef == gsta && pef == psta) {
9490 				pf = p1;
9491 				gerr = gef;
9492 				perr = pef;
9493 			} else if (pf > p1) {
9494 				pf = p1;
9495 				gerr = gef;
9496 				perr = pef;
9497 			}
9498 			rt2x00_dbg(rt2x00dev, "Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n",
9499 				   p1, pf, gef & 0x0F, pef & 0x3F);
9500 		}
9501 
9502 	ges[ch_idx] = gerr & 0x0F;
9503 	pes[ch_idx] = perr & 0x3F;
9504 }
9505 
9506 static void rt2800_rf_aux_tx0_loopback(struct rt2x00_dev *rt2x00dev)
9507 {
9508 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x21);
9509 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x10);
9510 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
9511 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x1b);
9512 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, 0x81);
9513 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 2, 0x81);
9514 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 34, 0xee);
9515 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, 0x2d);
9516 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x2d);
9517 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
9518 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xd7);
9519 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0xa2);
9520 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
9521 }
9522 
9523 static void rt2800_rf_aux_tx1_loopback(struct rt2x00_dev *rt2x00dev)
9524 {
9525 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x22);
9526 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x20);
9527 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
9528 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x4b);
9529 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, 0x81);
9530 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 2, 0x81);
9531 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 34, 0xee);
9532 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, 0x2d);
9533 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, 0x2d);
9534 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, 0x80);
9535 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, 0xd7);
9536 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, 0xa2);
9537 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, 0x20);
9538 }
9539 
9540 static void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
9541 {
9542 	struct rf_reg_pair rf_store[CHAIN_NUM][13];
9543 	u32 macorg1 = 0;
9544 	u32 macorg2 = 0;
9545 	u32 macorg3 = 0;
9546 	u32 macorg4 = 0;
9547 	u32 macorg5 = 0;
9548 	u32 orig528 = 0;
9549 	u32 orig52c = 0;
9550 
9551 	u32 savemacsysctrl = 0;
9552 	u32 macvalue = 0;
9553 	u32 mac13b8 = 0;
9554 	u32 p0 = 0, p1 = 0;
9555 	u32 p0_idx10 = 0, p1_idx10 = 0;
9556 
9557 	u8 rfvalue;
9558 	u8 loft_dc_search_result[CHAIN_NUM][RF_ALC_NUM][2];
9559 	u8 ger[CHAIN_NUM], per[CHAIN_NUM];
9560 
9561 	u8 vga_gain[] = {14, 14};
9562 	u8 bbp = 0, ch_idx = 0, rf_alc_idx = 0, idx = 0;
9563 	u8 bbpr30, rfb0r39, rfb0r42;
9564 	u8 bbpr1;
9565 	u8 bbpr4;
9566 	u8 bbpr241, bbpr242;
9567 	u8 count_step;
9568 
9569 	static const u8 rf_gain[] = {0x00, 0x01, 0x02, 0x04, 0x08, 0x0c};
9570 	static const u8 rfvga_gain_table[] = {0x24, 0x25, 0x26, 0x27, 0x28, 0x2c, 0x2d, 0x2e, 0x2f, 0x30,
9571 					      0x31, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3F};
9572 	static const u8 bbp_2324gain[] = {0x16, 0x14, 0x12, 0x10, 0x0c, 0x08};
9573 
9574 	savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9575 	macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
9576 	macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
9577 	macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
9578 	macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
9579 	macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
9580 	mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
9581 	orig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
9582 	orig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
9583 
9584 	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9585 	macvalue &= (~0x04);
9586 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
9587 
9588 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
9589 		rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
9590 
9591 	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9592 	macvalue &= (~0x08);
9593 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
9594 
9595 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
9596 		rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
9597 
9598 	for (ch_idx = 0; ch_idx < 2; ch_idx++)
9599 		rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
9600 
9601 	bbpr30 = rt2800_bbp_read(rt2x00dev, 30);
9602 	rfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39);
9603 	rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
9604 
9605 	rt2800_bbp_write(rt2x00dev, 30, 0x1F);
9606 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80);
9607 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B);
9608 
9609 	rt2800_bbp_write(rt2x00dev, 23, 0x00);
9610 	rt2800_bbp_write(rt2x00dev, 24, 0x00);
9611 
9612 	rt2800_setbbptonegenerator(rt2x00dev);
9613 
9614 	for (ch_idx = 0; ch_idx < 2; ch_idx++) {
9615 		rt2800_bbp_write(rt2x00dev, 23, 0x00);
9616 		rt2800_bbp_write(rt2x00dev, 24, 0x00);
9617 		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
9618 		rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
9619 		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
9620 		rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
9621 		rt2800_register_write(rt2x00dev, 0x13b8, 0x10);
9622 		udelay(1);
9623 
9624 		if (ch_idx == 0)
9625 			rt2800_rf_aux_tx0_loopback(rt2x00dev);
9626 		else
9627 			rt2800_rf_aux_tx1_loopback(rt2x00dev);
9628 
9629 		udelay(1);
9630 
9631 		if (ch_idx == 0)
9632 			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
9633 		else
9634 			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
9635 
9636 		rt2800_bbp_write(rt2x00dev, 158, 0x05);
9637 		rt2800_bbp_write(rt2x00dev, 159, 0x00);
9638 
9639 		rt2800_bbp_write(rt2x00dev, 158, 0x01);
9640 		if (ch_idx == 0)
9641 			rt2800_bbp_write(rt2x00dev, 159, 0x00);
9642 		else
9643 			rt2800_bbp_write(rt2x00dev, 159, 0x01);
9644 
9645 		vga_gain[ch_idx] = 18;
9646 		for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
9647 			rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]);
9648 			rt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]);
9649 
9650 			macvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3);
9651 			macvalue &= (~0x0000F1F1);
9652 			macvalue |= (rf_gain[rf_alc_idx] << 4);
9653 			macvalue |= (rf_gain[rf_alc_idx] << 12);
9654 			rt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue);
9655 			macvalue = (0x0000F1F1);
9656 			rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue);
9657 
9658 			if (rf_alc_idx == 0) {
9659 				rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21);
9660 				for (; vga_gain[ch_idx] > 0;
9661 				     vga_gain[ch_idx] = vga_gain[ch_idx] - 2) {
9662 					rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
9663 					rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
9664 					rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
9665 					rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
9666 					rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
9667 					p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
9668 					rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21);
9669 					p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
9670 					rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1);
9671 					if ((p0 < 7000 * 7000) && (p1 < (7000 * 7000)))
9672 						break;
9673 				}
9674 
9675 				rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
9676 				rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
9677 
9678 				rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
9679 					   rfvga_gain_table[vga_gain[ch_idx]]);
9680 
9681 				if (vga_gain[ch_idx] < 0)
9682 					vga_gain[ch_idx] = 0;
9683 			}
9684 
9685 			rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
9686 
9687 			rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
9688 			rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
9689 
9690 			rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result);
9691 		}
9692 	}
9693 
9694 	for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
9695 		for (idx = 0; idx < 4; idx++) {
9696 			rt2800_bbp_write(rt2x00dev, 158, 0xB0);
9697 			bbp = (idx << 2) + rf_alc_idx;
9698 			rt2800_bbp_write(rt2x00dev, 159, bbp);
9699 			rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp);
9700 
9701 			rt2800_bbp_write(rt2x00dev, 158, 0xb1);
9702 			bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00];
9703 			bbp = bbp & 0x3F;
9704 			rt2800_bbp_write(rt2x00dev, 159, bbp);
9705 			rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp);
9706 
9707 			rt2800_bbp_write(rt2x00dev, 158, 0xb2);
9708 			bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01];
9709 			bbp = bbp & 0x3F;
9710 			rt2800_bbp_write(rt2x00dev, 159, bbp);
9711 			rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp);
9712 
9713 			rt2800_bbp_write(rt2x00dev, 158, 0xb8);
9714 			bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00];
9715 			bbp = bbp & 0x3F;
9716 			rt2800_bbp_write(rt2x00dev, 159, bbp);
9717 			rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp);
9718 
9719 			rt2800_bbp_write(rt2x00dev, 158, 0xb9);
9720 			bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01];
9721 			bbp = bbp & 0x3F;
9722 			rt2800_bbp_write(rt2x00dev, 159, bbp);
9723 			rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp);
9724 		}
9725 	}
9726 
9727 	rt2800_bbp_write(rt2x00dev, 23, 0x00);
9728 	rt2800_bbp_write(rt2x00dev, 24, 0x00);
9729 
9730 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
9731 
9732 	rt2800_bbp_write(rt2x00dev, 158, 0x00);
9733 	rt2800_bbp_write(rt2x00dev, 159, 0x00);
9734 
9735 	bbp = 0x00;
9736 	rt2800_bbp_write(rt2x00dev, 244, 0x00);
9737 
9738 	rt2800_bbp_write(rt2x00dev, 21, 0x01);
9739 	udelay(1);
9740 	rt2800_bbp_write(rt2x00dev, 21, 0x00);
9741 
9742 	rt2800_rf_configrecover(rt2x00dev, rf_store);
9743 
9744 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
9745 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
9746 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
9747 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
9748 	rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
9749 	udelay(1);
9750 	rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
9751 	rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
9752 	rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
9753 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
9754 	rt2800_register_write(rt2x00dev, RF_CONTROL2, orig528);
9755 	rt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c);
9756 	rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
9757 
9758 	savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9759 	macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
9760 	macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
9761 	macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
9762 	macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
9763 	macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
9764 
9765 	bbpr1 = rt2800_bbp_read(rt2x00dev, 1);
9766 	bbpr4 = rt2800_bbp_read(rt2x00dev, 4);
9767 	bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
9768 	bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
9769 	mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
9770 
9771 	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9772 	macvalue &= (~0x04);
9773 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
9774 
9775 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
9776 		rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
9777 
9778 	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9779 	macvalue &= (~0x08);
9780 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
9781 
9782 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
9783 		rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
9784 
9785 	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9786 		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101);
9787 		rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
9788 	}
9789 
9790 	rt2800_bbp_write(rt2x00dev, 23, 0x00);
9791 	rt2800_bbp_write(rt2x00dev, 24, 0x00);
9792 
9793 	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9794 		rt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18));
9795 		rt2800_bbp_write(rt2x00dev, 21, 0x01);
9796 		udelay(1);
9797 		rt2800_bbp_write(rt2x00dev, 21, 0x00);
9798 
9799 		rt2800_bbp_write(rt2x00dev, 241, 0x14);
9800 		rt2800_bbp_write(rt2x00dev, 242, 0x80);
9801 		rt2800_bbp_write(rt2x00dev, 244, 0x31);
9802 	} else {
9803 		rt2800_setbbptonegenerator(rt2x00dev);
9804 	}
9805 
9806 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
9807 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
9808 	udelay(1);
9809 
9810 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
9811 
9812 	if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9813 		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000);
9814 		rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
9815 	}
9816 
9817 	rt2800_register_write(rt2x00dev, 0x13b8, 0x00000010);
9818 
9819 	for (ch_idx = 0; ch_idx < 2; ch_idx++)
9820 		rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
9821 
9822 	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B);
9823 	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B);
9824 
9825 	rt2800_bbp_write(rt2x00dev, 158, 0x03);
9826 	rt2800_bbp_write(rt2x00dev, 159, 0x60);
9827 	rt2800_bbp_write(rt2x00dev, 158, 0xB0);
9828 	rt2800_bbp_write(rt2x00dev, 159, 0x80);
9829 
9830 	for (ch_idx = 0; ch_idx < 2; ch_idx++) {
9831 		rt2800_bbp_write(rt2x00dev, 23, 0x00);
9832 		rt2800_bbp_write(rt2x00dev, 24, 0x00);
9833 
9834 		if (ch_idx == 0) {
9835 			rt2800_bbp_write(rt2x00dev, 158, 0x01);
9836 			rt2800_bbp_write(rt2x00dev, 159, 0x00);
9837 			if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9838 				bbp = bbpr1 & (~0x18);
9839 				bbp = bbp | 0x00;
9840 				rt2800_bbp_write(rt2x00dev, 1, bbp);
9841 			}
9842 			rt2800_rf_aux_tx0_loopback(rt2x00dev);
9843 			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
9844 		} else {
9845 			rt2800_bbp_write(rt2x00dev, 158, 0x01);
9846 			rt2800_bbp_write(rt2x00dev, 159, 0x01);
9847 			if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
9848 				bbp = bbpr1 & (~0x18);
9849 				bbp = bbp | 0x08;
9850 				rt2800_bbp_write(rt2x00dev, 1, bbp);
9851 			}
9852 			rt2800_rf_aux_tx1_loopback(rt2x00dev);
9853 			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
9854 		}
9855 
9856 		rt2800_bbp_write(rt2x00dev, 158, 0x05);
9857 		rt2800_bbp_write(rt2x00dev, 159, 0x04);
9858 
9859 		bbp = (ch_idx == 0) ? 0x28 : 0x46;
9860 		rt2800_bbp_write(rt2x00dev, 158, bbp);
9861 		rt2800_bbp_write(rt2x00dev, 159, 0x00);
9862 
9863 		if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9864 			rt2800_bbp_write(rt2x00dev, 23, 0x06);
9865 			rt2800_bbp_write(rt2x00dev, 24, 0x06);
9866 			count_step = 1;
9867 		} else {
9868 			rt2800_bbp_write(rt2x00dev, 23, 0x1F);
9869 			rt2800_bbp_write(rt2x00dev, 24, 0x1F);
9870 			count_step = 2;
9871 		}
9872 
9873 		for (; vga_gain[ch_idx] < 19; vga_gain[ch_idx] = (vga_gain[ch_idx] + count_step)) {
9874 			rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
9875 			rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
9876 			rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
9877 
9878 			bbp = (ch_idx == 0) ? 0x29 : 0x47;
9879 			rt2800_bbp_write(rt2x00dev, 158, bbp);
9880 			rt2800_bbp_write(rt2x00dev, 159, 0x00);
9881 			p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
9882 			if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
9883 				p0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
9884 
9885 			bbp = (ch_idx == 0) ? 0x29 : 0x47;
9886 			rt2800_bbp_write(rt2x00dev, 158, bbp);
9887 			rt2800_bbp_write(rt2x00dev, 159, 0x21);
9888 			p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
9889 			if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags))
9890 				p1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
9891 
9892 			rt2x00_dbg(rt2x00dev, "IQ AGC %d %d\n", p0, p1);
9893 
9894 			if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9895 				rt2x00_dbg(rt2x00dev, "IQ AGC IDX 10 %d %d\n", p0_idx10, p1_idx10);
9896 				if ((p0_idx10 > 7000 * 7000) || (p1_idx10 > 7000 * 7000)) {
9897 					if (vga_gain[ch_idx] != 0)
9898 						vga_gain[ch_idx] = vga_gain[ch_idx] - 1;
9899 					break;
9900 				}
9901 			}
9902 
9903 			if ((p0 > 2500 * 2500) || (p1 > 2500 * 2500))
9904 				break;
9905 		}
9906 
9907 		if (vga_gain[ch_idx] > 18)
9908 			vga_gain[ch_idx] = 18;
9909 		rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
9910 			   rfvga_gain_table[vga_gain[ch_idx]]);
9911 
9912 		bbp = (ch_idx == 0) ? 0x29 : 0x47;
9913 		rt2800_bbp_write(rt2x00dev, 158, bbp);
9914 		rt2800_bbp_write(rt2x00dev, 159, 0x00);
9915 
9916 		rt2800_iq_search(rt2x00dev, ch_idx, ger, per);
9917 	}
9918 
9919 	rt2800_bbp_write(rt2x00dev, 23, 0x00);
9920 	rt2800_bbp_write(rt2x00dev, 24, 0x00);
9921 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
9922 
9923 	rt2800_bbp_write(rt2x00dev, 158, 0x28);
9924 	bbp = ger[CHAIN_0] & 0x0F;
9925 	rt2800_bbp_write(rt2x00dev, 159, bbp);
9926 
9927 	rt2800_bbp_write(rt2x00dev, 158, 0x29);
9928 	bbp = per[CHAIN_0] & 0x3F;
9929 	rt2800_bbp_write(rt2x00dev, 159, bbp);
9930 
9931 	rt2800_bbp_write(rt2x00dev, 158, 0x46);
9932 	bbp = ger[CHAIN_1] & 0x0F;
9933 	rt2800_bbp_write(rt2x00dev, 159, bbp);
9934 
9935 	rt2800_bbp_write(rt2x00dev, 158, 0x47);
9936 	bbp = per[CHAIN_1] & 0x3F;
9937 	rt2800_bbp_write(rt2x00dev, 159, bbp);
9938 
9939 	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9940 		rt2800_bbp_write(rt2x00dev, 1, bbpr1);
9941 		rt2800_bbp_write(rt2x00dev, 241, bbpr241);
9942 		rt2800_bbp_write(rt2x00dev, 242, bbpr242);
9943 	}
9944 	rt2800_bbp_write(rt2x00dev, 244, 0x00);
9945 
9946 	rt2800_bbp_write(rt2x00dev, 158, 0x00);
9947 	rt2800_bbp_write(rt2x00dev, 159, 0x00);
9948 	rt2800_bbp_write(rt2x00dev, 158, 0xB0);
9949 	rt2800_bbp_write(rt2x00dev, 159, 0x00);
9950 
9951 	rt2800_bbp_write(rt2x00dev, 30, bbpr30);
9952 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39);
9953 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
9954 
9955 	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
9956 		rt2800_bbp_write(rt2x00dev, 4, bbpr4);
9957 
9958 	rt2800_bbp_write(rt2x00dev, 21, 0x01);
9959 	udelay(1);
9960 	rt2800_bbp_write(rt2x00dev, 21, 0x00);
9961 
9962 	rt2800_rf_configrecover(rt2x00dev, rf_store);
9963 
9964 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
9965 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
9966 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
9967 	rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
9968 	udelay(1);
9969 	rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
9970 	rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
9971 	rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
9972 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
9973 	rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
9974 }
9975 
9976 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
9977 				       bool set_bw, bool is_ht40)
9978 {
9979 	u8 bbp_val;
9980 
9981 	bbp_val = rt2800_bbp_read(rt2x00dev, 21);
9982 	bbp_val |= 0x1;
9983 	rt2800_bbp_write(rt2x00dev, 21, bbp_val);
9984 	usleep_range(100, 200);
9985 
9986 	if (set_bw) {
9987 		bbp_val = rt2800_bbp_read(rt2x00dev, 4);
9988 		rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40);
9989 		rt2800_bbp_write(rt2x00dev, 4, bbp_val);
9990 		usleep_range(100, 200);
9991 	}
9992 
9993 	bbp_val = rt2800_bbp_read(rt2x00dev, 21);
9994 	bbp_val &= (~0x1);
9995 	rt2800_bbp_write(rt2x00dev, 21, bbp_val);
9996 	usleep_range(100, 200);
9997 }
9998 
9999 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
10000 {
10001 	u8 rf_val;
10002 
10003 	if (btxcal)
10004 		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
10005 	else
10006 		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
10007 
10008 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
10009 
10010 	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
10011 	rf_val |= 0x80;
10012 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
10013 
10014 	if (btxcal) {
10015 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
10016 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
10017 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
10018 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
10019 		rf_val &= (~0x3F);
10020 		rf_val |= 0x3F;
10021 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
10022 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
10023 		rf_val &= (~0x3F);
10024 		rf_val |= 0x3F;
10025 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
10026 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
10027 	} else {
10028 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
10029 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
10030 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
10031 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
10032 		rf_val &= (~0x3F);
10033 		rf_val |= 0x34;
10034 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
10035 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
10036 		rf_val &= (~0x3F);
10037 		rf_val |= 0x34;
10038 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
10039 	}
10040 
10041 	return 0;
10042 }
10043 
10044 static s8 rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
10045 {
10046 	unsigned int cnt;
10047 	u8 bbp_val;
10048 	s8 cal_val;
10049 
10050 	rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
10051 
10052 	cnt = 0;
10053 	do {
10054 		usleep_range(500, 2000);
10055 		bbp_val = rt2800_bbp_read(rt2x00dev, 159);
10056 		if (bbp_val == 0x02 || cnt == 20)
10057 			break;
10058 
10059 		cnt++;
10060 	} while (cnt < 20);
10061 
10062 	bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39);
10063 	cal_val = bbp_val & 0x7F;
10064 	if (cal_val >= 0x40)
10065 		cal_val -= 128;
10066 
10067 	return cal_val;
10068 }
10069 
10070 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
10071 					 bool btxcal)
10072 {
10073 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
10074 	u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc;
10075 	u8 filter_target;
10076 	u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02;
10077 	u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
10078 	int loop = 0, is_ht40, cnt;
10079 	u8 bbp_val, rf_val;
10080 	s8 cal_r32_init, cal_r32_val, cal_diff;
10081 	u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
10082 	u8 saverfb5r06, saverfb5r07;
10083 	u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
10084 	u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41;
10085 	u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46;
10086 	u8 saverfb5r58, saverfb5r59;
10087 	u8 savebbp159r0, savebbp159r2, savebbpr23;
10088 	u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0;
10089 
10090 	/* Save MAC registers */
10091 	MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
10092 	MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
10093 
10094 	/* save BBP registers */
10095 	savebbpr23 = rt2800_bbp_read(rt2x00dev, 23);
10096 
10097 	savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0);
10098 	savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2);
10099 
10100 	/* Save RF registers */
10101 	saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
10102 	saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
10103 	saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
10104 	saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
10105 	saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5);
10106 	saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
10107 	saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
10108 	saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
10109 	saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
10110 	saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
10111 	saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
10112 	saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
10113 
10114 	saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37);
10115 	saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38);
10116 	saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39);
10117 	saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40);
10118 	saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41);
10119 	saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42);
10120 	saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43);
10121 	saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44);
10122 	saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45);
10123 	saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46);
10124 
10125 	saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
10126 	saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
10127 
10128 	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
10129 	rf_val |= 0x3;
10130 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
10131 
10132 	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
10133 	rf_val |= 0x1;
10134 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
10135 
10136 	cnt = 0;
10137 	do {
10138 		usleep_range(500, 2000);
10139 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
10140 		if (((rf_val & 0x1) == 0x00) || (cnt == 40))
10141 			break;
10142 		cnt++;
10143 	} while (cnt < 40);
10144 
10145 	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
10146 	rf_val &= (~0x3);
10147 	rf_val |= 0x1;
10148 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
10149 
10150 	/* I-3 */
10151 	bbp_val = rt2800_bbp_read(rt2x00dev, 23);
10152 	bbp_val &= (~0x1F);
10153 	bbp_val |= 0x10;
10154 	rt2800_bbp_write(rt2x00dev, 23, bbp_val);
10155 
10156 	do {
10157 		/* I-4,5,6,7,8,9 */
10158 		if (loop == 0) {
10159 			is_ht40 = false;
10160 
10161 			if (btxcal)
10162 				filter_target = tx_filter_target_20m;
10163 			else
10164 				filter_target = rx_filter_target_20m;
10165 		} else {
10166 			is_ht40 = true;
10167 
10168 			if (btxcal)
10169 				filter_target = tx_filter_target_40m;
10170 			else
10171 				filter_target = rx_filter_target_40m;
10172 		}
10173 
10174 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
10175 		rf_val &= (~0x04);
10176 		if (loop == 1)
10177 			rf_val |= 0x4;
10178 
10179 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
10180 
10181 		rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
10182 
10183 		rt2800_rf_lp_config(rt2x00dev, btxcal);
10184 		if (btxcal) {
10185 			tx_agc_fc = 0;
10186 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
10187 			rf_val &= (~0x7F);
10188 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
10189 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
10190 			rf_val &= (~0x7F);
10191 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
10192 		} else {
10193 			rx_agc_fc = 0;
10194 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
10195 			rf_val &= (~0x7F);
10196 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
10197 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
10198 			rf_val &= (~0x7F);
10199 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
10200 		}
10201 
10202 		usleep_range(1000, 2000);
10203 
10204 		bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
10205 		bbp_val &= (~0x6);
10206 		rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
10207 
10208 		rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
10209 
10210 		cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
10211 
10212 		bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
10213 		bbp_val |= 0x6;
10214 		rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
10215 do_cal:
10216 		if (btxcal) {
10217 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
10218 			rf_val &= (~0x7F);
10219 			rf_val |= tx_agc_fc;
10220 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
10221 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
10222 			rf_val &= (~0x7F);
10223 			rf_val |= tx_agc_fc;
10224 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
10225 		} else {
10226 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
10227 			rf_val &= (~0x7F);
10228 			rf_val |= rx_agc_fc;
10229 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
10230 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
10231 			rf_val &= (~0x7F);
10232 			rf_val |= rx_agc_fc;
10233 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
10234 		}
10235 
10236 		usleep_range(500, 1000);
10237 
10238 		rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
10239 
10240 		cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
10241 
10242 		cal_diff = cal_r32_init - cal_r32_val;
10243 
10244 		if (btxcal)
10245 			cmm_agc_fc = tx_agc_fc;
10246 		else
10247 			cmm_agc_fc = rx_agc_fc;
10248 
10249 		if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) ||
10250 		    ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) {
10251 			if (btxcal)
10252 				tx_agc_fc = 0;
10253 			else
10254 				rx_agc_fc = 0;
10255 		} else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) {
10256 			if (btxcal)
10257 				tx_agc_fc++;
10258 			else
10259 				rx_agc_fc++;
10260 			goto do_cal;
10261 		}
10262 
10263 		if (btxcal) {
10264 			if (loop == 0)
10265 				drv_data->tx_calibration_bw20 = tx_agc_fc;
10266 			else
10267 				drv_data->tx_calibration_bw40 = tx_agc_fc;
10268 		} else {
10269 			if (loop == 0)
10270 				drv_data->rx_calibration_bw20 = rx_agc_fc;
10271 			else
10272 				drv_data->rx_calibration_bw40 = rx_agc_fc;
10273 		}
10274 
10275 		loop++;
10276 	} while (loop <= 1);
10277 
10278 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
10279 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
10280 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
10281 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
10282 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
10283 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
10284 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
10285 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
10286 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
10287 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
10288 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
10289 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
10290 
10291 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
10292 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
10293 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
10294 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
10295 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
10296 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
10297 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
10298 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
10299 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
10300 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
10301 
10302 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
10303 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
10304 
10305 	rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
10306 
10307 	rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
10308 	rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
10309 
10310 	bbp_val = rt2800_bbp_read(rt2x00dev, 4);
10311 	rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH,
10312 			  2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
10313 	rt2800_bbp_write(rt2x00dev, 4, bbp_val);
10314 
10315 	rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
10316 	rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
10317 }
10318 
10319 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
10320 {
10321 	/* Initialize RF central register to default value */
10322 	rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
10323 	rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
10324 	rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
10325 	rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
10326 	rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
10327 	rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
10328 	rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
10329 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
10330 	rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
10331 	rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
10332 	rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
10333 	rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
10334 	rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
10335 	rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
10336 	rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
10337 	rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
10338 	rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
10339 	rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
10340 	rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
10341 	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
10342 	rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
10343 	rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
10344 	rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
10345 	rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
10346 	rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
10347 	rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
10348 	rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
10349 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
10350 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
10351 	rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
10352 	rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
10353 	rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
10354 	rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
10355 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
10356 	rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
10357 	rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
10358 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
10359 	rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
10360 	rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
10361 	rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
10362 	rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
10363 	rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
10364 	rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
10365 	rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
10366 
10367 	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
10368 	if (rt2800_clk_is_20mhz(rt2x00dev))
10369 		rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
10370 	else
10371 		rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
10372 	rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
10373 	rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
10374 	rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
10375 	rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
10376 	rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
10377 	rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
10378 	rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
10379 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
10380 	rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
10381 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
10382 	rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
10383 	rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
10384 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
10385 	rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
10386 	rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
10387 	rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
10388 
10389 	rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
10390 	rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
10391 	rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
10392 
10393 	/* Initialize RF channel register to default value */
10394 	rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
10395 	rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
10396 	rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
10397 	rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
10398 	rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
10399 	rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
10400 	rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
10401 	rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
10402 	rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
10403 	rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
10404 	rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
10405 	rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
10406 	rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
10407 	rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
10408 	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
10409 	rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
10410 	rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
10411 	rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
10412 	rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
10413 	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
10414 	rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
10415 	rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
10416 	rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
10417 	rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
10418 	rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
10419 	rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
10420 	rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
10421 	rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
10422 	rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
10423 	rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
10424 	rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
10425 	rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
10426 	rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
10427 	rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
10428 	rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
10429 	rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
10430 	rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
10431 	rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
10432 	rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
10433 	rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
10434 	rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
10435 	rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
10436 	rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
10437 	rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
10438 	rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
10439 	rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
10440 	rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
10441 	rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
10442 	rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
10443 	rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
10444 	rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
10445 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
10446 	rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
10447 	rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
10448 	rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
10449 	rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
10450 	rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
10451 	rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
10452 	rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
10453 	rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
10454 
10455 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
10456 
10457 	rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
10458 	rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
10459 	rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
10460 	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
10461 	rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
10462 	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
10463 	rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
10464 	rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
10465 	rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
10466 	rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
10467 	rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
10468 	rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
10469 	rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
10470 	rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
10471 	rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
10472 	rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
10473 	rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
10474 	rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
10475 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
10476 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
10477 	rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
10478 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
10479 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
10480 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
10481 	rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
10482 	rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
10483 	rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
10484 	rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
10485 	rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
10486 	rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
10487 
10488 	rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
10489 	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
10490 	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
10491 	rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
10492 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
10493 	rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
10494 	rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
10495 	rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
10496 	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
10497 
10498 	rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
10499 	rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
10500 	rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
10501 	rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
10502 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
10503 	rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
10504 
10505 	/* Initialize RF channel register for DRQFN */
10506 	rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
10507 	rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
10508 	rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
10509 	rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
10510 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
10511 	rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
10512 	rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
10513 	rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
10514 
10515 	/* Initialize RF DC calibration register to default value */
10516 	rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
10517 	rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
10518 	rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
10519 	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
10520 	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
10521 	rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
10522 	rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
10523 	rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
10524 	rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
10525 	rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
10526 	rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
10527 	rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
10528 	rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
10529 	rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
10530 	rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
10531 	rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
10532 	rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
10533 	rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
10534 	rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
10535 	rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
10536 	rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
10537 	rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
10538 	rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
10539 	rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
10540 	rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
10541 	rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
10542 	rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
10543 	rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
10544 	rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
10545 	rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
10546 	rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
10547 	rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
10548 	rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
10549 	rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
10550 	rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
10551 	rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
10552 	rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
10553 	rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
10554 	rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
10555 	rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
10556 	rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
10557 	rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
10558 	rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
10559 	rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
10560 	rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
10561 	rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
10562 	rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
10563 	rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
10564 	rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
10565 	rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
10566 	rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
10567 	rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
10568 	rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
10569 	rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
10570 	rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
10571 	rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
10572 	rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
10573 	rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
10574 	rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
10575 
10576 	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
10577 	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
10578 	rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
10579 
10580 	rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
10581 	rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
10582 
10583 	rt2800_r_calibration(rt2x00dev);
10584 	rt2800_rf_self_txdc_cal(rt2x00dev);
10585 	rt2800_rxdcoc_calibration(rt2x00dev);
10586 	rt2800_bw_filter_calibration(rt2x00dev, true);
10587 	rt2800_bw_filter_calibration(rt2x00dev, false);
10588 	rt2800_loft_iq_calibration(rt2x00dev);
10589 	rt2800_rxiq_calibration(rt2x00dev);
10590 }
10591 
10592 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
10593 {
10594 	if (rt2800_is_305x_soc(rt2x00dev)) {
10595 		rt2800_init_rfcsr_305x_soc(rt2x00dev);
10596 		return;
10597 	}
10598 
10599 	switch (rt2x00dev->chip.rt) {
10600 	case RT3070:
10601 	case RT3071:
10602 	case RT3090:
10603 		rt2800_init_rfcsr_30xx(rt2x00dev);
10604 		break;
10605 	case RT3290:
10606 		rt2800_init_rfcsr_3290(rt2x00dev);
10607 		break;
10608 	case RT3352:
10609 		rt2800_init_rfcsr_3352(rt2x00dev);
10610 		break;
10611 	case RT3390:
10612 		rt2800_init_rfcsr_3390(rt2x00dev);
10613 		break;
10614 	case RT3883:
10615 		rt2800_init_rfcsr_3883(rt2x00dev);
10616 		break;
10617 	case RT3572:
10618 		rt2800_init_rfcsr_3572(rt2x00dev);
10619 		break;
10620 	case RT3593:
10621 		rt2800_init_rfcsr_3593(rt2x00dev);
10622 		break;
10623 	case RT5350:
10624 		rt2800_init_rfcsr_5350(rt2x00dev);
10625 		break;
10626 	case RT5390:
10627 		rt2800_init_rfcsr_5390(rt2x00dev);
10628 		break;
10629 	case RT5392:
10630 		rt2800_init_rfcsr_5392(rt2x00dev);
10631 		break;
10632 	case RT5592:
10633 		rt2800_init_rfcsr_5592(rt2x00dev);
10634 		break;
10635 	case RT6352:
10636 		rt2800_init_rfcsr_6352(rt2x00dev);
10637 		break;
10638 	}
10639 }
10640 
10641 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
10642 {
10643 	u32 reg;
10644 	u16 word;
10645 
10646 	/*
10647 	 * Initialize MAC registers.
10648 	 */
10649 	if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
10650 		     rt2800_init_registers(rt2x00dev)))
10651 		return -EIO;
10652 
10653 	/*
10654 	 * Wait BBP/RF to wake up.
10655 	 */
10656 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
10657 		return -EIO;
10658 
10659 	/*
10660 	 * Send signal during boot time to initialize firmware.
10661 	 */
10662 	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
10663 	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
10664 	if (rt2x00_is_usb(rt2x00dev))
10665 		rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
10666 	rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
10667 	msleep(1);
10668 
10669 	/*
10670 	 * Make sure BBP is up and running.
10671 	 */
10672 	if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
10673 		return -EIO;
10674 
10675 	/*
10676 	 * Initialize BBP/RF registers.
10677 	 */
10678 	rt2800_init_bbp(rt2x00dev);
10679 	rt2800_init_rfcsr(rt2x00dev);
10680 
10681 	if (rt2x00_is_usb(rt2x00dev) &&
10682 	    (rt2x00_rt(rt2x00dev, RT3070) ||
10683 	     rt2x00_rt(rt2x00dev, RT3071) ||
10684 	     rt2x00_rt(rt2x00dev, RT3572))) {
10685 		udelay(200);
10686 		rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
10687 		udelay(10);
10688 	}
10689 
10690 	/*
10691 	 * Enable RX.
10692 	 */
10693 	reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
10694 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
10695 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
10696 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
10697 
10698 	udelay(50);
10699 
10700 	reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
10701 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
10702 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
10703 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
10704 	rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
10705 
10706 	reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
10707 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
10708 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
10709 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
10710 
10711 	/*
10712 	 * Initialize LED control
10713 	 */
10714 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF);
10715 	rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
10716 			   word & 0xff, (word >> 8) & 0xff);
10717 
10718 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF);
10719 	rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
10720 			   word & 0xff, (word >> 8) & 0xff);
10721 
10722 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY);
10723 	rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
10724 			   word & 0xff, (word >> 8) & 0xff);
10725 
10726 	return 0;
10727 }
10728 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
10729 
10730 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
10731 {
10732 	u32 reg;
10733 
10734 	rt2800_disable_wpdma(rt2x00dev);
10735 
10736 	/* Wait for DMA, ignore error */
10737 	rt2800_wait_wpdma_ready(rt2x00dev);
10738 
10739 	reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
10740 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
10741 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
10742 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
10743 }
10744 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
10745 
10746 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
10747 {
10748 	u32 reg;
10749 	u16 efuse_ctrl_reg;
10750 
10751 	if (rt2x00_rt(rt2x00dev, RT3290))
10752 		efuse_ctrl_reg = EFUSE_CTRL_3290;
10753 	else
10754 		efuse_ctrl_reg = EFUSE_CTRL;
10755 
10756 	reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg);
10757 	return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
10758 }
10759 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
10760 
10761 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
10762 {
10763 	u32 reg;
10764 	u16 efuse_ctrl_reg;
10765 	u16 efuse_data0_reg;
10766 	u16 efuse_data1_reg;
10767 	u16 efuse_data2_reg;
10768 	u16 efuse_data3_reg;
10769 
10770 	if (rt2x00_rt(rt2x00dev, RT3290)) {
10771 		efuse_ctrl_reg = EFUSE_CTRL_3290;
10772 		efuse_data0_reg = EFUSE_DATA0_3290;
10773 		efuse_data1_reg = EFUSE_DATA1_3290;
10774 		efuse_data2_reg = EFUSE_DATA2_3290;
10775 		efuse_data3_reg = EFUSE_DATA3_3290;
10776 	} else {
10777 		efuse_ctrl_reg = EFUSE_CTRL;
10778 		efuse_data0_reg = EFUSE_DATA0;
10779 		efuse_data1_reg = EFUSE_DATA1;
10780 		efuse_data2_reg = EFUSE_DATA2;
10781 		efuse_data3_reg = EFUSE_DATA3;
10782 	}
10783 	mutex_lock(&rt2x00dev->csr_mutex);
10784 
10785 	reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg);
10786 	rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
10787 	rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
10788 	rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
10789 	rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
10790 
10791 	/* Wait until the EEPROM has been loaded */
10792 	rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
10793 	/* Apparently the data is read from end to start */
10794 	reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg);
10795 	/* The returned value is in CPU order, but eeprom is le */
10796 	*(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
10797 	reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg);
10798 	*(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
10799 	reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg);
10800 	*(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
10801 	reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg);
10802 	*(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
10803 
10804 	mutex_unlock(&rt2x00dev->csr_mutex);
10805 }
10806 
10807 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
10808 {
10809 	unsigned int i;
10810 
10811 	for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
10812 		rt2800_efuse_read(rt2x00dev, i);
10813 
10814 	return 0;
10815 }
10816 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
10817 
10818 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
10819 {
10820 	u16 word;
10821 
10822 	if (rt2x00_rt(rt2x00dev, RT3593) ||
10823 	    rt2x00_rt(rt2x00dev, RT3883))
10824 		return 0;
10825 
10826 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG);
10827 	if ((word & 0x00ff) != 0x00ff)
10828 		return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
10829 
10830 	return 0;
10831 }
10832 
10833 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
10834 {
10835 	u16 word;
10836 
10837 	if (rt2x00_rt(rt2x00dev, RT3593) ||
10838 	    rt2x00_rt(rt2x00dev, RT3883))
10839 		return 0;
10840 
10841 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A);
10842 	if ((word & 0x00ff) != 0x00ff)
10843 		return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
10844 
10845 	return 0;
10846 }
10847 
10848 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
10849 {
10850 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
10851 	u16 word;
10852 	u8 *mac;
10853 	u8 default_lna_gain;
10854 	int retval;
10855 
10856 	/*
10857 	 * Read the EEPROM.
10858 	 */
10859 	retval = rt2800_read_eeprom(rt2x00dev);
10860 	if (retval)
10861 		return retval;
10862 
10863 	/*
10864 	 * Start validation of the data that has been read.
10865 	 */
10866 	mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
10867 	rt2x00lib_set_mac_address(rt2x00dev, mac);
10868 
10869 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
10870 	if (word == 0xffff) {
10871 		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
10872 		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
10873 		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
10874 		rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
10875 		rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
10876 	} else if (rt2x00_rt(rt2x00dev, RT2860) ||
10877 		   rt2x00_rt(rt2x00dev, RT2872)) {
10878 		/*
10879 		 * There is a max of 2 RX streams for RT28x0 series
10880 		 */
10881 		if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
10882 			rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
10883 		rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
10884 	}
10885 
10886 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
10887 	if (word == 0xffff) {
10888 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
10889 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
10890 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
10891 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
10892 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
10893 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
10894 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
10895 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
10896 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
10897 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
10898 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
10899 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
10900 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
10901 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
10902 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
10903 		rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
10904 		rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
10905 	}
10906 
10907 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
10908 	if ((word & 0x00ff) == 0x00ff) {
10909 		rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
10910 		rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
10911 		rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
10912 	}
10913 	if ((word & 0xff00) == 0xff00) {
10914 		rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
10915 				   LED_MODE_TXRX_ACTIVITY);
10916 		rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
10917 		rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
10918 		rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
10919 		rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
10920 		rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
10921 		rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
10922 	}
10923 
10924 	/*
10925 	 * During the LNA validation we are going to use
10926 	 * lna0 as correct value. Note that EEPROM_LNA
10927 	 * is never validated.
10928 	 */
10929 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
10930 	default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
10931 
10932 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
10933 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
10934 		rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
10935 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
10936 		rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
10937 	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
10938 
10939 	drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
10940 
10941 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
10942 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
10943 		rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
10944 	if (!rt2x00_rt(rt2x00dev, RT3593) &&
10945 	    !rt2x00_rt(rt2x00dev, RT3883)) {
10946 		if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
10947 		    rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
10948 			rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
10949 					   default_lna_gain);
10950 	}
10951 	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
10952 
10953 	drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
10954 
10955 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
10956 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
10957 		rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
10958 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
10959 		rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
10960 	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
10961 
10962 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
10963 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
10964 		rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
10965 	if (!rt2x00_rt(rt2x00dev, RT3593) &&
10966 	    !rt2x00_rt(rt2x00dev, RT3883)) {
10967 		if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
10968 		    rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
10969 			rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
10970 					   default_lna_gain);
10971 	}
10972 	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
10973 
10974 	if (rt2x00_rt(rt2x00dev, RT3593) ||
10975 	    rt2x00_rt(rt2x00dev, RT3883)) {
10976 		word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
10977 		if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
10978 		    rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
10979 			rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
10980 					   default_lna_gain);
10981 		if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
10982 		    rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
10983 			rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
10984 					   default_lna_gain);
10985 		rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
10986 	}
10987 
10988 	return 0;
10989 }
10990 
10991 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
10992 {
10993 	u16 value;
10994 	u16 eeprom;
10995 	u16 rf;
10996 
10997 	/*
10998 	 * Read EEPROM word for configuration.
10999 	 */
11000 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
11001 
11002 	/*
11003 	 * Identify RF chipset by EEPROM value
11004 	 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
11005 	 * RT53xx: defined in "EEPROM_CHIP_ID" field
11006 	 */
11007 	if (rt2x00_rt(rt2x00dev, RT3290) ||
11008 	    rt2x00_rt(rt2x00dev, RT5390) ||
11009 	    rt2x00_rt(rt2x00dev, RT5392) ||
11010 	    rt2x00_rt(rt2x00dev, RT6352))
11011 		rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID);
11012 	else if (rt2x00_rt(rt2x00dev, RT3352))
11013 		rf = RF3322;
11014 	else if (rt2x00_rt(rt2x00dev, RT3883))
11015 		rf = RF3853;
11016 	else if (rt2x00_rt(rt2x00dev, RT5350))
11017 		rf = RF5350;
11018 	else if (rt2x00_rt(rt2x00dev, RT5592))
11019 		rf = RF5592;
11020 	else
11021 		rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
11022 
11023 	switch (rf) {
11024 	case RF2820:
11025 	case RF2850:
11026 	case RF2720:
11027 	case RF2750:
11028 	case RF3020:
11029 	case RF2020:
11030 	case RF3021:
11031 	case RF3022:
11032 	case RF3052:
11033 	case RF3053:
11034 	case RF3070:
11035 	case RF3290:
11036 	case RF3320:
11037 	case RF3322:
11038 	case RF3853:
11039 	case RF5350:
11040 	case RF5360:
11041 	case RF5362:
11042 	case RF5370:
11043 	case RF5372:
11044 	case RF5390:
11045 	case RF5392:
11046 	case RF5592:
11047 	case RF7620:
11048 		break;
11049 	default:
11050 		rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
11051 			   rf);
11052 		return -ENODEV;
11053 	}
11054 
11055 	rt2x00_set_rf(rt2x00dev, rf);
11056 
11057 	/*
11058 	 * Identify default antenna configuration.
11059 	 */
11060 	rt2x00dev->default_ant.tx_chain_num =
11061 	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
11062 	rt2x00dev->default_ant.rx_chain_num =
11063 	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
11064 
11065 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
11066 
11067 	if (rt2x00_rt(rt2x00dev, RT3070) ||
11068 	    rt2x00_rt(rt2x00dev, RT3090) ||
11069 	    rt2x00_rt(rt2x00dev, RT3352) ||
11070 	    rt2x00_rt(rt2x00dev, RT3390)) {
11071 		value = rt2x00_get_field16(eeprom,
11072 				EEPROM_NIC_CONF1_ANT_DIVERSITY);
11073 		switch (value) {
11074 		case 0:
11075 		case 1:
11076 		case 2:
11077 			rt2x00dev->default_ant.tx = ANTENNA_A;
11078 			rt2x00dev->default_ant.rx = ANTENNA_A;
11079 			break;
11080 		case 3:
11081 			rt2x00dev->default_ant.tx = ANTENNA_A;
11082 			rt2x00dev->default_ant.rx = ANTENNA_B;
11083 			break;
11084 		}
11085 	} else {
11086 		rt2x00dev->default_ant.tx = ANTENNA_A;
11087 		rt2x00dev->default_ant.rx = ANTENNA_A;
11088 	}
11089 
11090 	/* These chips have hardware RX antenna diversity */
11091 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
11092 	    rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
11093 		rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
11094 		rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
11095 	}
11096 
11097 	/*
11098 	 * Determine external LNA informations.
11099 	 */
11100 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
11101 		__set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
11102 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
11103 		__set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
11104 
11105 	/*
11106 	 * Detect if this device has an hardware controlled radio.
11107 	 */
11108 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
11109 		__set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
11110 
11111 	/*
11112 	 * Detect if this device has Bluetooth co-existence.
11113 	 */
11114 	if (!rt2x00_rt(rt2x00dev, RT3352) &&
11115 	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
11116 		__set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
11117 
11118 	/*
11119 	 * Read frequency offset and RF programming sequence.
11120 	 */
11121 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
11122 	rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
11123 
11124 	/*
11125 	 * Store led settings, for correct led behaviour.
11126 	 */
11127 #ifdef CONFIG_RT2X00_LIB_LEDS
11128 	rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
11129 	rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
11130 	rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
11131 
11132 	rt2x00dev->led_mcu_reg = eeprom;
11133 #endif /* CONFIG_RT2X00_LIB_LEDS */
11134 
11135 	/*
11136 	 * Check if support EIRP tx power limit feature.
11137 	 */
11138 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
11139 
11140 	if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
11141 					EIRP_MAX_TX_POWER_LIMIT)
11142 		__set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
11143 
11144 	/*
11145 	 * Detect if device uses internal or external PA
11146 	 */
11147 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
11148 
11149 	if (rt2x00_rt(rt2x00dev, RT3352) ||
11150 	    rt2x00_rt(rt2x00dev, RT6352)) {
11151 		if (rt2x00_get_field16(eeprom,
11152 		    EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))
11153 		    __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
11154 			      &rt2x00dev->cap_flags);
11155 		if (rt2x00_get_field16(eeprom,
11156 		    EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352))
11157 		    __set_bit(CAPABILITY_EXTERNAL_PA_TX1,
11158 			      &rt2x00dev->cap_flags);
11159 	}
11160 
11161 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF2);
11162 
11163 	if (rt2x00_rt(rt2x00dev, RT6352) && eeprom != 0 && eeprom != 0xffff) {
11164 		if (!rt2x00_get_field16(eeprom,
11165 					EEPROM_NIC_CONF2_EXTERNAL_PA)) {
11166 			__clear_bit(CAPABILITY_EXTERNAL_PA_TX0,
11167 				    &rt2x00dev->cap_flags);
11168 			__clear_bit(CAPABILITY_EXTERNAL_PA_TX1,
11169 				    &rt2x00dev->cap_flags);
11170 		}
11171 	}
11172 
11173 	return 0;
11174 }
11175 
11176 /*
11177  * RF value list for rt28xx
11178  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
11179  */
11180 static const struct rf_channel rf_vals[] = {
11181 	{ 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
11182 	{ 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
11183 	{ 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
11184 	{ 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
11185 	{ 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
11186 	{ 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
11187 	{ 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
11188 	{ 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
11189 	{ 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
11190 	{ 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
11191 	{ 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
11192 	{ 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
11193 	{ 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
11194 	{ 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
11195 
11196 	/* 802.11 UNI / HyperLan 2 */
11197 	{ 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
11198 	{ 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
11199 	{ 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
11200 	{ 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
11201 	{ 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
11202 	{ 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
11203 	{ 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
11204 	{ 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
11205 	{ 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
11206 	{ 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
11207 	{ 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
11208 	{ 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
11209 
11210 	/* 802.11 HyperLan 2 */
11211 	{ 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
11212 	{ 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
11213 	{ 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
11214 	{ 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
11215 	{ 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
11216 	{ 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
11217 	{ 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
11218 	{ 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
11219 	{ 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
11220 	{ 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
11221 	{ 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
11222 	{ 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
11223 	{ 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
11224 	{ 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
11225 	{ 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
11226 	{ 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
11227 
11228 	/* 802.11 UNII */
11229 	{ 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
11230 	{ 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
11231 	{ 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
11232 	{ 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
11233 	{ 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
11234 	{ 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
11235 	{ 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
11236 	{ 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
11237 	{ 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
11238 	{ 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
11239 	{ 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
11240 
11241 	/* 802.11 Japan */
11242 	{ 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
11243 	{ 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
11244 	{ 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
11245 	{ 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
11246 	{ 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
11247 	{ 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
11248 	{ 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
11249 };
11250 
11251 /*
11252  * RF value list for rt3xxx
11253  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
11254  */
11255 static const struct rf_channel rf_vals_3x[] = {
11256 	{1,  241, 2, 2 },
11257 	{2,  241, 2, 7 },
11258 	{3,  242, 2, 2 },
11259 	{4,  242, 2, 7 },
11260 	{5,  243, 2, 2 },
11261 	{6,  243, 2, 7 },
11262 	{7,  244, 2, 2 },
11263 	{8,  244, 2, 7 },
11264 	{9,  245, 2, 2 },
11265 	{10, 245, 2, 7 },
11266 	{11, 246, 2, 2 },
11267 	{12, 246, 2, 7 },
11268 	{13, 247, 2, 2 },
11269 	{14, 248, 2, 4 },
11270 
11271 	/* 802.11 UNI / HyperLan 2 */
11272 	{36, 0x56, 0, 4},
11273 	{38, 0x56, 0, 6},
11274 	{40, 0x56, 0, 8},
11275 	{44, 0x57, 0, 0},
11276 	{46, 0x57, 0, 2},
11277 	{48, 0x57, 0, 4},
11278 	{52, 0x57, 0, 8},
11279 	{54, 0x57, 0, 10},
11280 	{56, 0x58, 0, 0},
11281 	{60, 0x58, 0, 4},
11282 	{62, 0x58, 0, 6},
11283 	{64, 0x58, 0, 8},
11284 
11285 	/* 802.11 HyperLan 2 */
11286 	{100, 0x5b, 0, 8},
11287 	{102, 0x5b, 0, 10},
11288 	{104, 0x5c, 0, 0},
11289 	{108, 0x5c, 0, 4},
11290 	{110, 0x5c, 0, 6},
11291 	{112, 0x5c, 0, 8},
11292 	{116, 0x5d, 0, 0},
11293 	{118, 0x5d, 0, 2},
11294 	{120, 0x5d, 0, 4},
11295 	{124, 0x5d, 0, 8},
11296 	{126, 0x5d, 0, 10},
11297 	{128, 0x5e, 0, 0},
11298 	{132, 0x5e, 0, 4},
11299 	{134, 0x5e, 0, 6},
11300 	{136, 0x5e, 0, 8},
11301 	{140, 0x5f, 0, 0},
11302 
11303 	/* 802.11 UNII */
11304 	{149, 0x5f, 0, 9},
11305 	{151, 0x5f, 0, 11},
11306 	{153, 0x60, 0, 1},
11307 	{157, 0x60, 0, 5},
11308 	{159, 0x60, 0, 7},
11309 	{161, 0x60, 0, 9},
11310 	{165, 0x61, 0, 1},
11311 	{167, 0x61, 0, 3},
11312 	{169, 0x61, 0, 5},
11313 	{171, 0x61, 0, 7},
11314 	{173, 0x61, 0, 9},
11315 };
11316 
11317 /*
11318  * RF value list for rt3xxx with Xtal20MHz
11319  * Supports: 2.4 GHz (all) (RF3322)
11320  */
11321 static const struct rf_channel rf_vals_3x_xtal20[] = {
11322 	{1,    0xE2,	 2,  0x14},
11323 	{2,    0xE3,	 2,  0x14},
11324 	{3,    0xE4,	 2,  0x14},
11325 	{4,    0xE5,	 2,  0x14},
11326 	{5,    0xE6,	 2,  0x14},
11327 	{6,    0xE7,	 2,  0x14},
11328 	{7,    0xE8,	 2,  0x14},
11329 	{8,    0xE9,	 2,  0x14},
11330 	{9,    0xEA,	 2,  0x14},
11331 	{10,   0xEB,	 2,  0x14},
11332 	{11,   0xEC,	 2,  0x14},
11333 	{12,   0xED,	 2,  0x14},
11334 	{13,   0xEE,	 2,  0x14},
11335 	{14,   0xF0,	 2,  0x18},
11336 };
11337 
11338 static const struct rf_channel rf_vals_3853[] = {
11339 	{1,  241, 6, 2},
11340 	{2,  241, 6, 7},
11341 	{3,  242, 6, 2},
11342 	{4,  242, 6, 7},
11343 	{5,  243, 6, 2},
11344 	{6,  243, 6, 7},
11345 	{7,  244, 6, 2},
11346 	{8,  244, 6, 7},
11347 	{9,  245, 6, 2},
11348 	{10, 245, 6, 7},
11349 	{11, 246, 6, 2},
11350 	{12, 246, 6, 7},
11351 	{13, 247, 6, 2},
11352 	{14, 248, 6, 4},
11353 
11354 	{36, 0x56, 8, 4},
11355 	{38, 0x56, 8, 6},
11356 	{40, 0x56, 8, 8},
11357 	{44, 0x57, 8, 0},
11358 	{46, 0x57, 8, 2},
11359 	{48, 0x57, 8, 4},
11360 	{52, 0x57, 8, 8},
11361 	{54, 0x57, 8, 10},
11362 	{56, 0x58, 8, 0},
11363 	{60, 0x58, 8, 4},
11364 	{62, 0x58, 8, 6},
11365 	{64, 0x58, 8, 8},
11366 
11367 	{100, 0x5b, 8, 8},
11368 	{102, 0x5b, 8, 10},
11369 	{104, 0x5c, 8, 0},
11370 	{108, 0x5c, 8, 4},
11371 	{110, 0x5c, 8, 6},
11372 	{112, 0x5c, 8, 8},
11373 	{114, 0x5c, 8, 10},
11374 	{116, 0x5d, 8, 0},
11375 	{118, 0x5d, 8, 2},
11376 	{120, 0x5d, 8, 4},
11377 	{124, 0x5d, 8, 8},
11378 	{126, 0x5d, 8, 10},
11379 	{128, 0x5e, 8, 0},
11380 	{132, 0x5e, 8, 4},
11381 	{134, 0x5e, 8, 6},
11382 	{136, 0x5e, 8, 8},
11383 	{140, 0x5f, 8, 0},
11384 
11385 	{149, 0x5f, 8, 9},
11386 	{151, 0x5f, 8, 11},
11387 	{153, 0x60, 8, 1},
11388 	{157, 0x60, 8, 5},
11389 	{159, 0x60, 8, 7},
11390 	{161, 0x60, 8, 9},
11391 	{165, 0x61, 8, 1},
11392 	{167, 0x61, 8, 3},
11393 	{169, 0x61, 8, 5},
11394 	{171, 0x61, 8, 7},
11395 	{173, 0x61, 8, 9},
11396 };
11397 
11398 static const struct rf_channel rf_vals_5592_xtal20[] = {
11399 	/* Channel, N, K, mod, R */
11400 	{1, 482, 4, 10, 3},
11401 	{2, 483, 4, 10, 3},
11402 	{3, 484, 4, 10, 3},
11403 	{4, 485, 4, 10, 3},
11404 	{5, 486, 4, 10, 3},
11405 	{6, 487, 4, 10, 3},
11406 	{7, 488, 4, 10, 3},
11407 	{8, 489, 4, 10, 3},
11408 	{9, 490, 4, 10, 3},
11409 	{10, 491, 4, 10, 3},
11410 	{11, 492, 4, 10, 3},
11411 	{12, 493, 4, 10, 3},
11412 	{13, 494, 4, 10, 3},
11413 	{14, 496, 8, 10, 3},
11414 	{36, 172, 8, 12, 1},
11415 	{38, 173, 0, 12, 1},
11416 	{40, 173, 4, 12, 1},
11417 	{42, 173, 8, 12, 1},
11418 	{44, 174, 0, 12, 1},
11419 	{46, 174, 4, 12, 1},
11420 	{48, 174, 8, 12, 1},
11421 	{50, 175, 0, 12, 1},
11422 	{52, 175, 4, 12, 1},
11423 	{54, 175, 8, 12, 1},
11424 	{56, 176, 0, 12, 1},
11425 	{58, 176, 4, 12, 1},
11426 	{60, 176, 8, 12, 1},
11427 	{62, 177, 0, 12, 1},
11428 	{64, 177, 4, 12, 1},
11429 	{100, 183, 4, 12, 1},
11430 	{102, 183, 8, 12, 1},
11431 	{104, 184, 0, 12, 1},
11432 	{106, 184, 4, 12, 1},
11433 	{108, 184, 8, 12, 1},
11434 	{110, 185, 0, 12, 1},
11435 	{112, 185, 4, 12, 1},
11436 	{114, 185, 8, 12, 1},
11437 	{116, 186, 0, 12, 1},
11438 	{118, 186, 4, 12, 1},
11439 	{120, 186, 8, 12, 1},
11440 	{122, 187, 0, 12, 1},
11441 	{124, 187, 4, 12, 1},
11442 	{126, 187, 8, 12, 1},
11443 	{128, 188, 0, 12, 1},
11444 	{130, 188, 4, 12, 1},
11445 	{132, 188, 8, 12, 1},
11446 	{134, 189, 0, 12, 1},
11447 	{136, 189, 4, 12, 1},
11448 	{138, 189, 8, 12, 1},
11449 	{140, 190, 0, 12, 1},
11450 	{149, 191, 6, 12, 1},
11451 	{151, 191, 10, 12, 1},
11452 	{153, 192, 2, 12, 1},
11453 	{155, 192, 6, 12, 1},
11454 	{157, 192, 10, 12, 1},
11455 	{159, 193, 2, 12, 1},
11456 	{161, 193, 6, 12, 1},
11457 	{165, 194, 2, 12, 1},
11458 	{184, 164, 0, 12, 1},
11459 	{188, 164, 4, 12, 1},
11460 	{192, 165, 8, 12, 1},
11461 	{196, 166, 0, 12, 1},
11462 };
11463 
11464 static const struct rf_channel rf_vals_5592_xtal40[] = {
11465 	/* Channel, N, K, mod, R */
11466 	{1, 241, 2, 10, 3},
11467 	{2, 241, 7, 10, 3},
11468 	{3, 242, 2, 10, 3},
11469 	{4, 242, 7, 10, 3},
11470 	{5, 243, 2, 10, 3},
11471 	{6, 243, 7, 10, 3},
11472 	{7, 244, 2, 10, 3},
11473 	{8, 244, 7, 10, 3},
11474 	{9, 245, 2, 10, 3},
11475 	{10, 245, 7, 10, 3},
11476 	{11, 246, 2, 10, 3},
11477 	{12, 246, 7, 10, 3},
11478 	{13, 247, 2, 10, 3},
11479 	{14, 248, 4, 10, 3},
11480 	{36, 86, 4, 12, 1},
11481 	{38, 86, 6, 12, 1},
11482 	{40, 86, 8, 12, 1},
11483 	{42, 86, 10, 12, 1},
11484 	{44, 87, 0, 12, 1},
11485 	{46, 87, 2, 12, 1},
11486 	{48, 87, 4, 12, 1},
11487 	{50, 87, 6, 12, 1},
11488 	{52, 87, 8, 12, 1},
11489 	{54, 87, 10, 12, 1},
11490 	{56, 88, 0, 12, 1},
11491 	{58, 88, 2, 12, 1},
11492 	{60, 88, 4, 12, 1},
11493 	{62, 88, 6, 12, 1},
11494 	{64, 88, 8, 12, 1},
11495 	{100, 91, 8, 12, 1},
11496 	{102, 91, 10, 12, 1},
11497 	{104, 92, 0, 12, 1},
11498 	{106, 92, 2, 12, 1},
11499 	{108, 92, 4, 12, 1},
11500 	{110, 92, 6, 12, 1},
11501 	{112, 92, 8, 12, 1},
11502 	{114, 92, 10, 12, 1},
11503 	{116, 93, 0, 12, 1},
11504 	{118, 93, 2, 12, 1},
11505 	{120, 93, 4, 12, 1},
11506 	{122, 93, 6, 12, 1},
11507 	{124, 93, 8, 12, 1},
11508 	{126, 93, 10, 12, 1},
11509 	{128, 94, 0, 12, 1},
11510 	{130, 94, 2, 12, 1},
11511 	{132, 94, 4, 12, 1},
11512 	{134, 94, 6, 12, 1},
11513 	{136, 94, 8, 12, 1},
11514 	{138, 94, 10, 12, 1},
11515 	{140, 95, 0, 12, 1},
11516 	{149, 95, 9, 12, 1},
11517 	{151, 95, 11, 12, 1},
11518 	{153, 96, 1, 12, 1},
11519 	{155, 96, 3, 12, 1},
11520 	{157, 96, 5, 12, 1},
11521 	{159, 96, 7, 12, 1},
11522 	{161, 96, 9, 12, 1},
11523 	{165, 97, 1, 12, 1},
11524 	{184, 82, 0, 12, 1},
11525 	{188, 82, 4, 12, 1},
11526 	{192, 82, 8, 12, 1},
11527 	{196, 83, 0, 12, 1},
11528 };
11529 
11530 static const struct rf_channel rf_vals_7620[] = {
11531 	{1, 0x50, 0x99, 0x99, 1},
11532 	{2, 0x50, 0x44, 0x44, 2},
11533 	{3, 0x50, 0xEE, 0xEE, 2},
11534 	{4, 0x50, 0x99, 0x99, 3},
11535 	{5, 0x51, 0x44, 0x44, 0},
11536 	{6, 0x51, 0xEE, 0xEE, 0},
11537 	{7, 0x51, 0x99, 0x99, 1},
11538 	{8, 0x51, 0x44, 0x44, 2},
11539 	{9, 0x51, 0xEE, 0xEE, 2},
11540 	{10, 0x51, 0x99, 0x99, 3},
11541 	{11, 0x52, 0x44, 0x44, 0},
11542 	{12, 0x52, 0xEE, 0xEE, 0},
11543 	{13, 0x52, 0x99, 0x99, 1},
11544 	{14, 0x52, 0x33, 0x33, 3},
11545 };
11546 
11547 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
11548 {
11549 	struct hw_mode_spec *spec = &rt2x00dev->spec;
11550 	struct channel_info *info;
11551 	s8 *default_power1;
11552 	s8 *default_power2;
11553 	s8 *default_power3;
11554 	unsigned int i, tx_chains, rx_chains;
11555 	u32 reg;
11556 
11557 	/*
11558 	 * Disable powersaving as default.
11559 	 */
11560 	rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
11561 
11562 	/*
11563 	 * Change default retry settings to values corresponding more closely
11564 	 * to rate[0].count setting of minstrel rate control algorithm.
11565 	 */
11566 	rt2x00dev->hw->wiphy->retry_short = 2;
11567 	rt2x00dev->hw->wiphy->retry_long = 2;
11568 
11569 	/*
11570 	 * Initialize all hw fields.
11571 	 */
11572 	ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
11573 	ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
11574 	ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
11575 	ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
11576 	ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
11577 
11578 	/*
11579 	 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
11580 	 * unless we are capable of sending the buffered frames out after the
11581 	 * DTIM transmission using rt2x00lib_beacondone. This will send out
11582 	 * multicast and broadcast traffic immediately instead of buffering it
11583 	 * infinitly and thus dropping it after some time.
11584 	 */
11585 	if (!rt2x00_is_usb(rt2x00dev))
11586 		ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
11587 
11588 	ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
11589 
11590 	SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
11591 	SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
11592 				rt2800_eeprom_addr(rt2x00dev,
11593 						   EEPROM_MAC_ADDR_0));
11594 
11595 	/*
11596 	 * As rt2800 has a global fallback table we cannot specify
11597 	 * more then one tx rate per frame but since the hw will
11598 	 * try several rates (based on the fallback table) we should
11599 	 * initialize max_report_rates to the maximum number of rates
11600 	 * we are going to try. Otherwise mac80211 will truncate our
11601 	 * reported tx rates and the rc algortihm will end up with
11602 	 * incorrect data.
11603 	 */
11604 	rt2x00dev->hw->max_rates = 1;
11605 	rt2x00dev->hw->max_report_rates = 7;
11606 	rt2x00dev->hw->max_rate_tries = 1;
11607 
11608 	/*
11609 	 * Initialize hw_mode information.
11610 	 */
11611 	spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
11612 
11613 	switch (rt2x00dev->chip.rf) {
11614 	case RF2720:
11615 	case RF2820:
11616 		spec->num_channels = 14;
11617 		spec->channels = rf_vals;
11618 		break;
11619 
11620 	case RF2750:
11621 	case RF2850:
11622 		spec->num_channels = ARRAY_SIZE(rf_vals);
11623 		spec->channels = rf_vals;
11624 		break;
11625 
11626 	case RF2020:
11627 	case RF3020:
11628 	case RF3021:
11629 	case RF3022:
11630 	case RF3070:
11631 	case RF3290:
11632 	case RF3320:
11633 	case RF3322:
11634 	case RF5350:
11635 	case RF5360:
11636 	case RF5362:
11637 	case RF5370:
11638 	case RF5372:
11639 	case RF5390:
11640 	case RF5392:
11641 		spec->num_channels = 14;
11642 		if (rt2800_clk_is_20mhz(rt2x00dev))
11643 			spec->channels = rf_vals_3x_xtal20;
11644 		else
11645 			spec->channels = rf_vals_3x;
11646 		break;
11647 
11648 	case RF7620:
11649 		spec->num_channels = ARRAY_SIZE(rf_vals_7620);
11650 		spec->channels = rf_vals_7620;
11651 		break;
11652 
11653 	case RF3052:
11654 	case RF3053:
11655 		spec->num_channels = ARRAY_SIZE(rf_vals_3x);
11656 		spec->channels = rf_vals_3x;
11657 		break;
11658 
11659 	case RF3853:
11660 		spec->num_channels = ARRAY_SIZE(rf_vals_3853);
11661 		spec->channels = rf_vals_3853;
11662 		break;
11663 
11664 	case RF5592:
11665 		reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX);
11666 		if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
11667 			spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
11668 			spec->channels = rf_vals_5592_xtal40;
11669 		} else {
11670 			spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
11671 			spec->channels = rf_vals_5592_xtal20;
11672 		}
11673 		break;
11674 	}
11675 
11676 	if (WARN_ON_ONCE(!spec->channels))
11677 		return -ENODEV;
11678 
11679 	spec->supported_bands = SUPPORT_BAND_2GHZ;
11680 	if (spec->num_channels > 14)
11681 		spec->supported_bands |= SUPPORT_BAND_5GHZ;
11682 
11683 	/*
11684 	 * Initialize HT information.
11685 	 */
11686 	if (!rt2x00_rf(rt2x00dev, RF2020))
11687 		spec->ht.ht_supported = true;
11688 	else
11689 		spec->ht.ht_supported = false;
11690 
11691 	spec->ht.cap =
11692 	    IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
11693 	    IEEE80211_HT_CAP_GRN_FLD |
11694 	    IEEE80211_HT_CAP_SGI_20 |
11695 	    IEEE80211_HT_CAP_SGI_40;
11696 
11697 	tx_chains = rt2x00dev->default_ant.tx_chain_num;
11698 	rx_chains = rt2x00dev->default_ant.rx_chain_num;
11699 
11700 	if (tx_chains >= 2)
11701 		spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
11702 
11703 	spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT;
11704 
11705 	spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2;
11706 	spec->ht.ampdu_density = 4;
11707 	spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
11708 	if (tx_chains != rx_chains) {
11709 		spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
11710 		spec->ht.mcs.tx_params |=
11711 		    (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
11712 	}
11713 
11714 	switch (rx_chains) {
11715 	case 3:
11716 		spec->ht.mcs.rx_mask[2] = 0xff;
11717 		fallthrough;
11718 	case 2:
11719 		spec->ht.mcs.rx_mask[1] = 0xff;
11720 		fallthrough;
11721 	case 1:
11722 		spec->ht.mcs.rx_mask[0] = 0xff;
11723 		spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
11724 		break;
11725 	}
11726 
11727 	/*
11728 	 * Create channel information and survey arrays
11729 	 */
11730 	info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
11731 	if (!info)
11732 		return -ENOMEM;
11733 
11734 	rt2x00dev->chan_survey =
11735 		kcalloc(spec->num_channels, sizeof(struct rt2x00_chan_survey),
11736 			GFP_KERNEL);
11737 	if (!rt2x00dev->chan_survey) {
11738 		kfree(info);
11739 		return -ENOMEM;
11740 	}
11741 
11742 	spec->channels_info = info;
11743 
11744 	default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
11745 	default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
11746 
11747 	if (rt2x00dev->default_ant.tx_chain_num > 2)
11748 		default_power3 = rt2800_eeprom_addr(rt2x00dev,
11749 						    EEPROM_EXT_TXPOWER_BG3);
11750 	else
11751 		default_power3 = NULL;
11752 
11753 	for (i = 0; i < 14; i++) {
11754 		info[i].default_power1 = default_power1[i];
11755 		info[i].default_power2 = default_power2[i];
11756 		if (default_power3)
11757 			info[i].default_power3 = default_power3[i];
11758 	}
11759 
11760 	if (spec->num_channels > 14) {
11761 		default_power1 = rt2800_eeprom_addr(rt2x00dev,
11762 						    EEPROM_TXPOWER_A1);
11763 		default_power2 = rt2800_eeprom_addr(rt2x00dev,
11764 						    EEPROM_TXPOWER_A2);
11765 
11766 		if (rt2x00dev->default_ant.tx_chain_num > 2)
11767 			default_power3 =
11768 				rt2800_eeprom_addr(rt2x00dev,
11769 						   EEPROM_EXT_TXPOWER_A3);
11770 		else
11771 			default_power3 = NULL;
11772 
11773 		for (i = 14; i < spec->num_channels; i++) {
11774 			info[i].default_power1 = default_power1[i - 14];
11775 			info[i].default_power2 = default_power2[i - 14];
11776 			if (default_power3)
11777 				info[i].default_power3 = default_power3[i - 14];
11778 		}
11779 	}
11780 
11781 	switch (rt2x00dev->chip.rf) {
11782 	case RF2020:
11783 	case RF3020:
11784 	case RF3021:
11785 	case RF3022:
11786 	case RF3320:
11787 	case RF3052:
11788 	case RF3053:
11789 	case RF3070:
11790 	case RF3290:
11791 	case RF3853:
11792 	case RF5350:
11793 	case RF5360:
11794 	case RF5362:
11795 	case RF5370:
11796 	case RF5372:
11797 	case RF5390:
11798 	case RF5392:
11799 	case RF5592:
11800 	case RF7620:
11801 		__set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
11802 		break;
11803 	}
11804 
11805 	return 0;
11806 }
11807 
11808 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
11809 {
11810 	u32 reg;
11811 	u32 rt;
11812 	u32 rev;
11813 
11814 	if (rt2x00_rt(rt2x00dev, RT3290))
11815 		reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290);
11816 	else
11817 		reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
11818 
11819 	rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
11820 	rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
11821 
11822 	switch (rt) {
11823 	case RT2860:
11824 	case RT2872:
11825 	case RT2883:
11826 	case RT3070:
11827 	case RT3071:
11828 	case RT3090:
11829 	case RT3290:
11830 	case RT3352:
11831 	case RT3390:
11832 	case RT3572:
11833 	case RT3593:
11834 	case RT3883:
11835 	case RT5350:
11836 	case RT5390:
11837 	case RT5392:
11838 	case RT5592:
11839 		break;
11840 	default:
11841 		rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
11842 			   rt, rev);
11843 		return -ENODEV;
11844 	}
11845 
11846 	if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
11847 		rt = RT6352;
11848 
11849 	rt2x00_set_rt(rt2x00dev, rt, rev);
11850 
11851 	return 0;
11852 }
11853 
11854 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
11855 {
11856 	int retval;
11857 	u32 reg;
11858 
11859 	retval = rt2800_probe_rt(rt2x00dev);
11860 	if (retval)
11861 		return retval;
11862 
11863 	/*
11864 	 * Allocate eeprom data.
11865 	 */
11866 	retval = rt2800_validate_eeprom(rt2x00dev);
11867 	if (retval)
11868 		return retval;
11869 
11870 	retval = rt2800_init_eeprom(rt2x00dev);
11871 	if (retval)
11872 		return retval;
11873 
11874 	/*
11875 	 * Enable rfkill polling by setting GPIO direction of the
11876 	 * rfkill switch GPIO pin correctly.
11877 	 */
11878 	reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
11879 	rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
11880 	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
11881 
11882 	/*
11883 	 * Initialize hw specifications.
11884 	 */
11885 	retval = rt2800_probe_hw_mode(rt2x00dev);
11886 	if (retval)
11887 		return retval;
11888 
11889 	/*
11890 	 * Set device capabilities.
11891 	 */
11892 	__set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
11893 	__set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
11894 	if (!rt2x00_is_usb(rt2x00dev))
11895 		__set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
11896 
11897 	/*
11898 	 * Set device requirements.
11899 	 */
11900 	if (!rt2x00_is_soc(rt2x00dev))
11901 		__set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
11902 	__set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
11903 	__set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
11904 	if (!rt2800_hwcrypt_disabled(rt2x00dev))
11905 		__set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
11906 	__set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
11907 	__set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
11908 	if (rt2x00_is_usb(rt2x00dev))
11909 		__set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
11910 	else {
11911 		__set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
11912 		__set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
11913 	}
11914 
11915 	if (modparam_watchdog) {
11916 		__set_bit(CAPABILITY_RESTART_HW, &rt2x00dev->cap_flags);
11917 		rt2x00dev->link.watchdog_interval = msecs_to_jiffies(100);
11918 	} else {
11919 		rt2x00dev->link.watchdog_disabled = true;
11920 	}
11921 
11922 	/*
11923 	 * Set the rssi offset.
11924 	 */
11925 	rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
11926 
11927 	return 0;
11928 }
11929 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
11930 
11931 /*
11932  * IEEE80211 stack callback functions.
11933  */
11934 void rt2800_get_key_seq(struct ieee80211_hw *hw,
11935 			struct ieee80211_key_conf *key,
11936 			struct ieee80211_key_seq *seq)
11937 {
11938 	struct rt2x00_dev *rt2x00dev = hw->priv;
11939 	struct mac_iveiv_entry iveiv_entry;
11940 	u32 offset;
11941 
11942 	if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
11943 		return;
11944 
11945 	offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
11946 	rt2800_register_multiread(rt2x00dev, offset,
11947 				      &iveiv_entry, sizeof(iveiv_entry));
11948 
11949 	memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
11950 	memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
11951 }
11952 EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
11953 
11954 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
11955 {
11956 	struct rt2x00_dev *rt2x00dev = hw->priv;
11957 	u32 reg;
11958 	bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
11959 
11960 	reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
11961 	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
11962 	rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
11963 
11964 	reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
11965 	rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
11966 	rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
11967 
11968 	reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
11969 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
11970 	rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
11971 
11972 	reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
11973 	rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
11974 	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
11975 
11976 	reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
11977 	rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
11978 	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
11979 
11980 	reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
11981 	rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
11982 	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
11983 
11984 	reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
11985 	rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
11986 	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
11987 
11988 	return 0;
11989 }
11990 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
11991 
11992 int rt2800_conf_tx(struct ieee80211_hw *hw,
11993 		   struct ieee80211_vif *vif,
11994 		   unsigned int link_id, u16 queue_idx,
11995 		   const struct ieee80211_tx_queue_params *params)
11996 {
11997 	struct rt2x00_dev *rt2x00dev = hw->priv;
11998 	struct data_queue *queue;
11999 	struct rt2x00_field32 field;
12000 	int retval;
12001 	u32 reg;
12002 	u32 offset;
12003 
12004 	/*
12005 	 * First pass the configuration through rt2x00lib, that will
12006 	 * update the queue settings and validate the input. After that
12007 	 * we are free to update the registers based on the value
12008 	 * in the queue parameter.
12009 	 */
12010 	retval = rt2x00mac_conf_tx(hw, vif, link_id, queue_idx, params);
12011 	if (retval)
12012 		return retval;
12013 
12014 	/*
12015 	 * We only need to perform additional register initialization
12016 	 * for WMM queues/
12017 	 */
12018 	if (queue_idx >= 4)
12019 		return 0;
12020 
12021 	queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
12022 
12023 	/* Update WMM TXOP register */
12024 	offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
12025 	field.bit_offset = (queue_idx & 1) * 16;
12026 	field.bit_mask = 0xffff << field.bit_offset;
12027 
12028 	reg = rt2800_register_read(rt2x00dev, offset);
12029 	rt2x00_set_field32(&reg, field, queue->txop);
12030 	rt2800_register_write(rt2x00dev, offset, reg);
12031 
12032 	/* Update WMM registers */
12033 	field.bit_offset = queue_idx * 4;
12034 	field.bit_mask = 0xf << field.bit_offset;
12035 
12036 	reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG);
12037 	rt2x00_set_field32(&reg, field, queue->aifs);
12038 	rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
12039 
12040 	reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG);
12041 	rt2x00_set_field32(&reg, field, queue->cw_min);
12042 	rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
12043 
12044 	reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG);
12045 	rt2x00_set_field32(&reg, field, queue->cw_max);
12046 	rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
12047 
12048 	/* Update EDCA registers */
12049 	offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
12050 
12051 	reg = rt2800_register_read(rt2x00dev, offset);
12052 	rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
12053 	rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
12054 	rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
12055 	rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
12056 	rt2800_register_write(rt2x00dev, offset, reg);
12057 
12058 	return 0;
12059 }
12060 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
12061 
12062 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
12063 {
12064 	struct rt2x00_dev *rt2x00dev = hw->priv;
12065 	u64 tsf;
12066 	u32 reg;
12067 
12068 	reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1);
12069 	tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
12070 	reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0);
12071 	tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
12072 
12073 	return tsf;
12074 }
12075 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
12076 
12077 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
12078 			struct ieee80211_ampdu_params *params)
12079 {
12080 	struct ieee80211_sta *sta = params->sta;
12081 	enum ieee80211_ampdu_mlme_action action = params->action;
12082 	u16 tid = params->tid;
12083 	struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
12084 	int ret = 0;
12085 
12086 	/*
12087 	 * Don't allow aggregation for stations the hardware isn't aware
12088 	 * of because tx status reports for frames to an unknown station
12089 	 * always contain wcid=WCID_END+1 and thus we can't distinguish
12090 	 * between multiple stations which leads to unwanted situations
12091 	 * when the hw reorders frames due to aggregation.
12092 	 */
12093 	if (sta_priv->wcid > WCID_END)
12094 		return -ENOSPC;
12095 
12096 	switch (action) {
12097 	case IEEE80211_AMPDU_RX_START:
12098 	case IEEE80211_AMPDU_RX_STOP:
12099 		/*
12100 		 * The hw itself takes care of setting up BlockAck mechanisms.
12101 		 * So, we only have to allow mac80211 to nagotiate a BlockAck
12102 		 * agreement. Once that is done, the hw will BlockAck incoming
12103 		 * AMPDUs without further setup.
12104 		 */
12105 		break;
12106 	case IEEE80211_AMPDU_TX_START:
12107 		ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;
12108 		break;
12109 	case IEEE80211_AMPDU_TX_STOP_CONT:
12110 	case IEEE80211_AMPDU_TX_STOP_FLUSH:
12111 	case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
12112 		ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
12113 		break;
12114 	case IEEE80211_AMPDU_TX_OPERATIONAL:
12115 		break;
12116 	default:
12117 		rt2x00_warn((struct rt2x00_dev *)hw->priv,
12118 			    "Unknown AMPDU action\n");
12119 	}
12120 
12121 	return ret;
12122 }
12123 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
12124 
12125 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
12126 		      struct survey_info *survey)
12127 {
12128 	struct rt2x00_dev *rt2x00dev = hw->priv;
12129 	struct rt2x00_chan_survey *chan_survey =
12130 		   &rt2x00dev->chan_survey[idx];
12131 	enum nl80211_band band = NL80211_BAND_2GHZ;
12132 
12133 	if (idx >= rt2x00dev->bands[band].n_channels) {
12134 		idx -= rt2x00dev->bands[band].n_channels;
12135 		band = NL80211_BAND_5GHZ;
12136 	}
12137 
12138 	if (idx >= rt2x00dev->bands[band].n_channels)
12139 		return -ENOENT;
12140 
12141 	if (idx == 0)
12142 		rt2800_update_survey(rt2x00dev);
12143 
12144 	survey->channel = &rt2x00dev->bands[band].channels[idx];
12145 
12146 	survey->filled = SURVEY_INFO_TIME |
12147 			 SURVEY_INFO_TIME_BUSY |
12148 			 SURVEY_INFO_TIME_EXT_BUSY;
12149 
12150 	survey->time = div_u64(chan_survey->time_idle + chan_survey->time_busy, 1000);
12151 	survey->time_busy = div_u64(chan_survey->time_busy, 1000);
12152 	survey->time_ext_busy = div_u64(chan_survey->time_ext_busy, 1000);
12153 
12154 	if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
12155 		survey->filled |= SURVEY_INFO_IN_USE;
12156 
12157 	return 0;
12158 
12159 }
12160 EXPORT_SYMBOL_GPL(rt2800_get_survey);
12161 
12162 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
12163 MODULE_VERSION(DRV_VERSION);
12164 MODULE_DESCRIPTION("Ralink RT2800 library");
12165 MODULE_LICENSE("GPL");
12166