1 /* 2 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com> 3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 4 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 5 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 6 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 7 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 8 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 9 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 10 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com> 11 <http://rt2x00.serialmonkey.com> 12 13 This program is free software; you can redistribute it and/or modify 14 it under the terms of the GNU General Public License as published by 15 the Free Software Foundation; either version 2 of the License, or 16 (at your option) any later version. 17 18 This program is distributed in the hope that it will be useful, 19 but WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 GNU General Public License for more details. 22 23 You should have received a copy of the GNU General Public License 24 along with this program; if not, see <http://www.gnu.org/licenses/>. 25 */ 26 27 /* 28 Module: rt2800 29 Abstract: Data structures and registers for the rt2800 modules. 30 Supported chipsets: RT2800E, RT2800ED & RT2800U. 31 */ 32 33 #ifndef RT2800_H 34 #define RT2800_H 35 36 /* 37 * RF chip defines. 38 * 39 * RF2820 2.4G 2T3R 40 * RF2850 2.4G/5G 2T3R 41 * RF2720 2.4G 1T2R 42 * RF2750 2.4G/5G 1T2R 43 * RF3020 2.4G 1T1R 44 * RF2020 2.4G B/G 45 * RF3021 2.4G 1T2R 46 * RF3022 2.4G 2T2R 47 * RF3052 2.4G/5G 2T2R 48 * RF2853 2.4G/5G 3T3R 49 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390) 50 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392) 51 * RF3053 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662) 52 * RF5592 2.4G/5G 2T2R 53 * RF3070 2.4G 1T1R 54 * RF5360 2.4G 1T1R 55 * RF5362 2.4G 1T1R 56 * RF5370 2.4G 1T1R 57 * RF5390 2.4G 1T1R 58 */ 59 #define RF2820 0x0001 60 #define RF2850 0x0002 61 #define RF2720 0x0003 62 #define RF2750 0x0004 63 #define RF3020 0x0005 64 #define RF2020 0x0006 65 #define RF3021 0x0007 66 #define RF3022 0x0008 67 #define RF3052 0x0009 68 #define RF2853 0x000a 69 #define RF3320 0x000b 70 #define RF3322 0x000c 71 #define RF3053 0x000d 72 #define RF5592 0x000f 73 #define RF3070 0x3070 74 #define RF3290 0x3290 75 #define RF5350 0x5350 76 #define RF5360 0x5360 77 #define RF5362 0x5362 78 #define RF5370 0x5370 79 #define RF5372 0x5372 80 #define RF5390 0x5390 81 #define RF5392 0x5392 82 83 /* 84 * Chipset revisions. 85 */ 86 #define REV_RT2860C 0x0100 87 #define REV_RT2860D 0x0101 88 #define REV_RT2872E 0x0200 89 #define REV_RT3070E 0x0200 90 #define REV_RT3070F 0x0201 91 #define REV_RT3071E 0x0211 92 #define REV_RT3090E 0x0211 93 #define REV_RT3390E 0x0211 94 #define REV_RT3593E 0x0211 95 #define REV_RT5390F 0x0502 96 #define REV_RT5390R 0x1502 97 #define REV_RT5592C 0x0221 98 99 #define DEFAULT_RSSI_OFFSET 120 100 101 /* 102 * Register layout information. 103 */ 104 #define CSR_REG_BASE 0x1000 105 #define CSR_REG_SIZE 0x0800 106 #define EEPROM_BASE 0x0000 107 #define EEPROM_SIZE 0x0200 108 #define BBP_BASE 0x0000 109 #define BBP_SIZE 0x00ff 110 #define RF_BASE 0x0004 111 #define RF_SIZE 0x0010 112 #define RFCSR_BASE 0x0000 113 #define RFCSR_SIZE 0x0040 114 115 /* 116 * Number of TX queues. 117 */ 118 #define NUM_TX_QUEUES 4 119 120 /* 121 * Registers. 122 */ 123 124 125 /* 126 * MAC_CSR0_3290: MAC_CSR0 for RT3290 to identity MAC version number. 127 */ 128 #define MAC_CSR0_3290 0x0000 129 130 /* 131 * E2PROM_CSR: PCI EEPROM control register. 132 * RELOAD: Write 1 to reload eeprom content. 133 * TYPE: 0: 93c46, 1:93c66. 134 * LOAD_STATUS: 1:loading, 0:done. 135 */ 136 #define E2PROM_CSR 0x0004 137 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001) 138 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002) 139 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004) 140 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008) 141 #define E2PROM_CSR_TYPE FIELD32(0x00000030) 142 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040) 143 #define E2PROM_CSR_RELOAD FIELD32(0x00000080) 144 145 /* 146 * CMB_CTRL_CFG 147 */ 148 #define CMB_CTRL 0x0020 149 #define AUX_OPT_BIT0 FIELD32(0x00000001) 150 #define AUX_OPT_BIT1 FIELD32(0x00000002) 151 #define AUX_OPT_BIT2 FIELD32(0x00000004) 152 #define AUX_OPT_BIT3 FIELD32(0x00000008) 153 #define AUX_OPT_BIT4 FIELD32(0x00000010) 154 #define AUX_OPT_BIT5 FIELD32(0x00000020) 155 #define AUX_OPT_BIT6 FIELD32(0x00000040) 156 #define AUX_OPT_BIT7 FIELD32(0x00000080) 157 #define AUX_OPT_BIT8 FIELD32(0x00000100) 158 #define AUX_OPT_BIT9 FIELD32(0x00000200) 159 #define AUX_OPT_BIT10 FIELD32(0x00000400) 160 #define AUX_OPT_BIT11 FIELD32(0x00000800) 161 #define AUX_OPT_BIT12 FIELD32(0x00001000) 162 #define AUX_OPT_BIT13 FIELD32(0x00002000) 163 #define AUX_OPT_BIT14 FIELD32(0x00004000) 164 #define AUX_OPT_BIT15 FIELD32(0x00008000) 165 #define LDO25_LEVEL FIELD32(0x00030000) 166 #define LDO25_LARGEA FIELD32(0x00040000) 167 #define LDO25_FRC_ON FIELD32(0x00080000) 168 #define CMB_RSV FIELD32(0x00300000) 169 #define XTAL_RDY FIELD32(0x00400000) 170 #define PLL_LD FIELD32(0x00800000) 171 #define LDO_CORE_LEVEL FIELD32(0x0F000000) 172 #define LDO_BGSEL FIELD32(0x30000000) 173 #define LDO3_EN FIELD32(0x40000000) 174 #define LDO0_EN FIELD32(0x80000000) 175 176 /* 177 * EFUSE_CSR_3290: RT3290 EEPROM 178 */ 179 #define EFUSE_CTRL_3290 0x0024 180 181 /* 182 * EFUSE_DATA3 of 3290 183 */ 184 #define EFUSE_DATA3_3290 0x0028 185 186 /* 187 * EFUSE_DATA2 of 3290 188 */ 189 #define EFUSE_DATA2_3290 0x002c 190 191 /* 192 * EFUSE_DATA1 of 3290 193 */ 194 #define EFUSE_DATA1_3290 0x0030 195 196 /* 197 * EFUSE_DATA0 of 3290 198 */ 199 #define EFUSE_DATA0_3290 0x0034 200 201 /* 202 * OSC_CTRL_CFG 203 * Ring oscillator configuration 204 */ 205 #define OSC_CTRL 0x0038 206 #define OSC_REF_CYCLE FIELD32(0x00001fff) 207 #define OSC_RSV FIELD32(0x0000e000) 208 #define OSC_CAL_CNT FIELD32(0x0fff0000) 209 #define OSC_CAL_ACK FIELD32(0x10000000) 210 #define OSC_CLK_32K_VLD FIELD32(0x20000000) 211 #define OSC_CAL_REQ FIELD32(0x40000000) 212 #define OSC_ROSC_EN FIELD32(0x80000000) 213 214 /* 215 * COEX_CFG_0 216 */ 217 #define COEX_CFG0 0x0040 218 #define COEX_CFG_ANT FIELD32(0xff000000) 219 /* 220 * COEX_CFG_1 221 */ 222 #define COEX_CFG1 0x0044 223 224 /* 225 * COEX_CFG_2 226 */ 227 #define COEX_CFG2 0x0048 228 #define BT_COEX_CFG1 FIELD32(0xff000000) 229 #define BT_COEX_CFG0 FIELD32(0x00ff0000) 230 #define WL_COEX_CFG1 FIELD32(0x0000ff00) 231 #define WL_COEX_CFG0 FIELD32(0x000000ff) 232 /* 233 * PLL_CTRL_CFG 234 * PLL configuration register 235 */ 236 #define PLL_CTRL 0x0050 237 #define PLL_RESERVED_INPUT1 FIELD32(0x000000ff) 238 #define PLL_RESERVED_INPUT2 FIELD32(0x0000ff00) 239 #define PLL_CONTROL FIELD32(0x00070000) 240 #define PLL_LPF_R1 FIELD32(0x00080000) 241 #define PLL_LPF_C1_CTRL FIELD32(0x00300000) 242 #define PLL_LPF_C2_CTRL FIELD32(0x00c00000) 243 #define PLL_CP_CURRENT_CTRL FIELD32(0x03000000) 244 #define PLL_PFD_DELAY_CTRL FIELD32(0x0c000000) 245 #define PLL_LOCK_CTRL FIELD32(0x70000000) 246 #define PLL_VBGBK_EN FIELD32(0x80000000) 247 248 249 /* 250 * WLAN_CTRL_CFG 251 * RT3290 wlan configuration 252 */ 253 #define WLAN_FUN_CTRL 0x0080 254 #define WLAN_EN FIELD32(0x00000001) 255 #define WLAN_CLK_EN FIELD32(0x00000002) 256 #define WLAN_RSV1 FIELD32(0x00000004) 257 #define WLAN_RESET FIELD32(0x00000008) 258 #define PCIE_APP0_CLK_REQ FIELD32(0x00000010) 259 #define FRC_WL_ANT_SET FIELD32(0x00000020) 260 #define INV_TR_SW0 FIELD32(0x00000040) 261 #define WLAN_GPIO_IN_BIT0 FIELD32(0x00000100) 262 #define WLAN_GPIO_IN_BIT1 FIELD32(0x00000200) 263 #define WLAN_GPIO_IN_BIT2 FIELD32(0x00000400) 264 #define WLAN_GPIO_IN_BIT3 FIELD32(0x00000800) 265 #define WLAN_GPIO_IN_BIT4 FIELD32(0x00001000) 266 #define WLAN_GPIO_IN_BIT5 FIELD32(0x00002000) 267 #define WLAN_GPIO_IN_BIT6 FIELD32(0x00004000) 268 #define WLAN_GPIO_IN_BIT7 FIELD32(0x00008000) 269 #define WLAN_GPIO_IN_BIT_ALL FIELD32(0x0000ff00) 270 #define WLAN_GPIO_OUT_BIT0 FIELD32(0x00010000) 271 #define WLAN_GPIO_OUT_BIT1 FIELD32(0x00020000) 272 #define WLAN_GPIO_OUT_BIT2 FIELD32(0x00040000) 273 #define WLAN_GPIO_OUT_BIT3 FIELD32(0x00050000) 274 #define WLAN_GPIO_OUT_BIT4 FIELD32(0x00100000) 275 #define WLAN_GPIO_OUT_BIT5 FIELD32(0x00200000) 276 #define WLAN_GPIO_OUT_BIT6 FIELD32(0x00400000) 277 #define WLAN_GPIO_OUT_BIT7 FIELD32(0x00800000) 278 #define WLAN_GPIO_OUT_BIT_ALL FIELD32(0x00ff0000) 279 #define WLAN_GPIO_OUT_OE_BIT0 FIELD32(0x01000000) 280 #define WLAN_GPIO_OUT_OE_BIT1 FIELD32(0x02000000) 281 #define WLAN_GPIO_OUT_OE_BIT2 FIELD32(0x04000000) 282 #define WLAN_GPIO_OUT_OE_BIT3 FIELD32(0x08000000) 283 #define WLAN_GPIO_OUT_OE_BIT4 FIELD32(0x10000000) 284 #define WLAN_GPIO_OUT_OE_BIT5 FIELD32(0x20000000) 285 #define WLAN_GPIO_OUT_OE_BIT6 FIELD32(0x40000000) 286 #define WLAN_GPIO_OUT_OE_BIT7 FIELD32(0x80000000) 287 #define WLAN_GPIO_OUT_OE_BIT_ALL FIELD32(0xff000000) 288 289 /* 290 * AUX_CTRL: Aux/PCI-E related configuration 291 */ 292 #define AUX_CTRL 0x10c 293 #define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002) 294 #define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400) 295 296 /* 297 * OPT_14: Unknown register used by rt3xxx devices. 298 */ 299 #define OPT_14_CSR 0x0114 300 #define OPT_14_CSR_BIT0 FIELD32(0x00000001) 301 302 /* 303 * INT_SOURCE_CSR: Interrupt source register. 304 * Write one to clear corresponding bit. 305 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO 306 */ 307 #define INT_SOURCE_CSR 0x0200 308 #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001) 309 #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002) 310 #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004) 311 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008) 312 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010) 313 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020) 314 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040) 315 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080) 316 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100) 317 #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200) 318 #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400) 319 #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800) 320 #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000) 321 #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000) 322 #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000) 323 #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000) 324 #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000) 325 #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000) 326 327 /* 328 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF. 329 */ 330 #define INT_MASK_CSR 0x0204 331 #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001) 332 #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002) 333 #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004) 334 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008) 335 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010) 336 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020) 337 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040) 338 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080) 339 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100) 340 #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200) 341 #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400) 342 #define INT_MASK_CSR_TBTT FIELD32(0x00000800) 343 #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000) 344 #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000) 345 #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000) 346 #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000) 347 #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000) 348 #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000) 349 350 /* 351 * WPDMA_GLO_CFG 352 */ 353 #define WPDMA_GLO_CFG 0x0208 354 #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001) 355 #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002) 356 #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004) 357 #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008) 358 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030) 359 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040) 360 #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080) 361 #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00) 362 #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000) 363 364 /* 365 * WPDMA_RST_IDX 366 */ 367 #define WPDMA_RST_IDX 0x020c 368 #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001) 369 #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002) 370 #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004) 371 #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008) 372 #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010) 373 #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020) 374 #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000) 375 376 /* 377 * DELAY_INT_CFG 378 */ 379 #define DELAY_INT_CFG 0x0210 380 #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff) 381 #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00) 382 #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000) 383 #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000) 384 #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000) 385 #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000) 386 387 /* 388 * WMM_AIFSN_CFG: Aifsn for each EDCA AC 389 * AIFSN0: AC_VO 390 * AIFSN1: AC_VI 391 * AIFSN2: AC_BE 392 * AIFSN3: AC_BK 393 */ 394 #define WMM_AIFSN_CFG 0x0214 395 #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f) 396 #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0) 397 #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00) 398 #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000) 399 400 /* 401 * WMM_CWMIN_CSR: CWmin for each EDCA AC 402 * CWMIN0: AC_VO 403 * CWMIN1: AC_VI 404 * CWMIN2: AC_BE 405 * CWMIN3: AC_BK 406 */ 407 #define WMM_CWMIN_CFG 0x0218 408 #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f) 409 #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0) 410 #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00) 411 #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000) 412 413 /* 414 * WMM_CWMAX_CSR: CWmax for each EDCA AC 415 * CWMAX0: AC_VO 416 * CWMAX1: AC_VI 417 * CWMAX2: AC_BE 418 * CWMAX3: AC_BK 419 */ 420 #define WMM_CWMAX_CFG 0x021c 421 #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f) 422 #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0) 423 #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00) 424 #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000) 425 426 /* 427 * AC_TXOP0: AC_VO/AC_VI TXOP register 428 * AC0TXOP: AC_VO in unit of 32us 429 * AC1TXOP: AC_VI in unit of 32us 430 */ 431 #define WMM_TXOP0_CFG 0x0220 432 #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff) 433 #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000) 434 435 /* 436 * AC_TXOP1: AC_BE/AC_BK TXOP register 437 * AC2TXOP: AC_BE in unit of 32us 438 * AC3TXOP: AC_BK in unit of 32us 439 */ 440 #define WMM_TXOP1_CFG 0x0224 441 #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff) 442 #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000) 443 444 /* 445 * GPIO_CTRL: 446 * GPIO_CTRL_VALx: GPIO value 447 * GPIO_CTRL_DIRx: GPIO direction: 0 = output; 1 = input 448 */ 449 #define GPIO_CTRL 0x0228 450 #define GPIO_CTRL_VAL0 FIELD32(0x00000001) 451 #define GPIO_CTRL_VAL1 FIELD32(0x00000002) 452 #define GPIO_CTRL_VAL2 FIELD32(0x00000004) 453 #define GPIO_CTRL_VAL3 FIELD32(0x00000008) 454 #define GPIO_CTRL_VAL4 FIELD32(0x00000010) 455 #define GPIO_CTRL_VAL5 FIELD32(0x00000020) 456 #define GPIO_CTRL_VAL6 FIELD32(0x00000040) 457 #define GPIO_CTRL_VAL7 FIELD32(0x00000080) 458 #define GPIO_CTRL_DIR0 FIELD32(0x00000100) 459 #define GPIO_CTRL_DIR1 FIELD32(0x00000200) 460 #define GPIO_CTRL_DIR2 FIELD32(0x00000400) 461 #define GPIO_CTRL_DIR3 FIELD32(0x00000800) 462 #define GPIO_CTRL_DIR4 FIELD32(0x00001000) 463 #define GPIO_CTRL_DIR5 FIELD32(0x00002000) 464 #define GPIO_CTRL_DIR6 FIELD32(0x00004000) 465 #define GPIO_CTRL_DIR7 FIELD32(0x00008000) 466 #define GPIO_CTRL_VAL8 FIELD32(0x00010000) 467 #define GPIO_CTRL_VAL9 FIELD32(0x00020000) 468 #define GPIO_CTRL_VAL10 FIELD32(0x00040000) 469 #define GPIO_CTRL_DIR8 FIELD32(0x01000000) 470 #define GPIO_CTRL_DIR9 FIELD32(0x02000000) 471 #define GPIO_CTRL_DIR10 FIELD32(0x04000000) 472 473 /* 474 * MCU_CMD_CFG 475 */ 476 #define MCU_CMD_CFG 0x022c 477 478 /* 479 * AC_VO register offsets 480 */ 481 #define TX_BASE_PTR0 0x0230 482 #define TX_MAX_CNT0 0x0234 483 #define TX_CTX_IDX0 0x0238 484 #define TX_DTX_IDX0 0x023c 485 486 /* 487 * AC_VI register offsets 488 */ 489 #define TX_BASE_PTR1 0x0240 490 #define TX_MAX_CNT1 0x0244 491 #define TX_CTX_IDX1 0x0248 492 #define TX_DTX_IDX1 0x024c 493 494 /* 495 * AC_BE register offsets 496 */ 497 #define TX_BASE_PTR2 0x0250 498 #define TX_MAX_CNT2 0x0254 499 #define TX_CTX_IDX2 0x0258 500 #define TX_DTX_IDX2 0x025c 501 502 /* 503 * AC_BK register offsets 504 */ 505 #define TX_BASE_PTR3 0x0260 506 #define TX_MAX_CNT3 0x0264 507 #define TX_CTX_IDX3 0x0268 508 #define TX_DTX_IDX3 0x026c 509 510 /* 511 * HCCA register offsets 512 */ 513 #define TX_BASE_PTR4 0x0270 514 #define TX_MAX_CNT4 0x0274 515 #define TX_CTX_IDX4 0x0278 516 #define TX_DTX_IDX4 0x027c 517 518 /* 519 * MGMT register offsets 520 */ 521 #define TX_BASE_PTR5 0x0280 522 #define TX_MAX_CNT5 0x0284 523 #define TX_CTX_IDX5 0x0288 524 #define TX_DTX_IDX5 0x028c 525 526 /* 527 * RX register offsets 528 */ 529 #define RX_BASE_PTR 0x0290 530 #define RX_MAX_CNT 0x0294 531 #define RX_CRX_IDX 0x0298 532 #define RX_DRX_IDX 0x029c 533 534 /* 535 * USB_DMA_CFG 536 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns. 537 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes. 538 * PHY_CLEAR: phy watch dog enable. 539 * TX_CLEAR: Clear USB DMA TX path. 540 * TXOP_HALT: Halt TXOP count down when TX buffer is full. 541 * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation. 542 * RX_BULK_EN: Enable USB DMA Rx. 543 * TX_BULK_EN: Enable USB DMA Tx. 544 * EP_OUT_VALID: OUT endpoint data valid. 545 * RX_BUSY: USB DMA RX FSM busy. 546 * TX_BUSY: USB DMA TX FSM busy. 547 */ 548 #define USB_DMA_CFG 0x02a0 549 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff) 550 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00) 551 #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000) 552 #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000) 553 #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000) 554 #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000) 555 #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000) 556 #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000) 557 #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000) 558 #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000) 559 #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000) 560 561 /* 562 * US_CYC_CNT 563 * BT_MODE_EN: Bluetooth mode enable 564 * CLOCK CYCLE: Clock cycle count in 1us. 565 * PCI:0x21, PCIE:0x7d, USB:0x1e 566 */ 567 #define US_CYC_CNT 0x02a4 568 #define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100) 569 #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff) 570 571 /* 572 * PBF_SYS_CTRL 573 * HOST_RAM_WRITE: enable Host program ram write selection 574 */ 575 #define PBF_SYS_CTRL 0x0400 576 #define PBF_SYS_CTRL_READY FIELD32(0x00000080) 577 #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000) 578 579 /* 580 * HOST-MCU shared memory 581 */ 582 #define HOST_CMD_CSR 0x0404 583 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff) 584 585 /* 586 * PBF registers 587 * Most are for debug. Driver doesn't touch PBF register. 588 */ 589 #define PBF_CFG 0x0408 590 #define PBF_MAX_PCNT 0x040c 591 #define PBF_CTRL 0x0410 592 #define PBF_INT_STA 0x0414 593 #define PBF_INT_ENA 0x0418 594 595 /* 596 * BCN_OFFSET0: 597 */ 598 #define BCN_OFFSET0 0x042c 599 #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff) 600 #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00) 601 #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000) 602 #define BCN_OFFSET0_BCN3 FIELD32(0xff000000) 603 604 /* 605 * BCN_OFFSET1: 606 */ 607 #define BCN_OFFSET1 0x0430 608 #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff) 609 #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00) 610 #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000) 611 #define BCN_OFFSET1_BCN7 FIELD32(0xff000000) 612 613 /* 614 * TXRXQ_PCNT: PBF register 615 * PCNT_TX0Q: Page count for TX hardware queue 0 616 * PCNT_TX1Q: Page count for TX hardware queue 1 617 * PCNT_TX2Q: Page count for TX hardware queue 2 618 * PCNT_RX0Q: Page count for RX hardware queue 619 */ 620 #define TXRXQ_PCNT 0x0438 621 #define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff) 622 #define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00) 623 #define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000) 624 #define TXRXQ_PCNT_RX0Q FIELD32(0xff000000) 625 626 /* 627 * PBF register 628 * Debug. Driver doesn't touch PBF register. 629 */ 630 #define PBF_DBG 0x043c 631 632 /* 633 * RF registers 634 */ 635 #define RF_CSR_CFG 0x0500 636 #define RF_CSR_CFG_DATA FIELD32(0x000000ff) 637 #define RF_CSR_CFG_REGNUM FIELD32(0x00003f00) 638 #define RF_CSR_CFG_WRITE FIELD32(0x00010000) 639 #define RF_CSR_CFG_BUSY FIELD32(0x00020000) 640 641 /* 642 * EFUSE_CSR: RT30x0 EEPROM 643 */ 644 #define EFUSE_CTRL 0x0580 645 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000) 646 #define EFUSE_CTRL_MODE FIELD32(0x000000c0) 647 #define EFUSE_CTRL_KICK FIELD32(0x40000000) 648 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000) 649 650 /* 651 * EFUSE_DATA0 652 */ 653 #define EFUSE_DATA0 0x0590 654 655 /* 656 * EFUSE_DATA1 657 */ 658 #define EFUSE_DATA1 0x0594 659 660 /* 661 * EFUSE_DATA2 662 */ 663 #define EFUSE_DATA2 0x0598 664 665 /* 666 * EFUSE_DATA3 667 */ 668 #define EFUSE_DATA3 0x059c 669 670 /* 671 * LDO_CFG0 672 */ 673 #define LDO_CFG0 0x05d4 674 #define LDO_CFG0_DELAY3 FIELD32(0x000000ff) 675 #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00) 676 #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000) 677 #define LDO_CFG0_BGSEL FIELD32(0x03000000) 678 #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000) 679 #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000) 680 #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000) 681 682 /* 683 * GPIO_SWITCH 684 */ 685 #define GPIO_SWITCH 0x05dc 686 #define GPIO_SWITCH_0 FIELD32(0x00000001) 687 #define GPIO_SWITCH_1 FIELD32(0x00000002) 688 #define GPIO_SWITCH_2 FIELD32(0x00000004) 689 #define GPIO_SWITCH_3 FIELD32(0x00000008) 690 #define GPIO_SWITCH_4 FIELD32(0x00000010) 691 #define GPIO_SWITCH_5 FIELD32(0x00000020) 692 #define GPIO_SWITCH_6 FIELD32(0x00000040) 693 #define GPIO_SWITCH_7 FIELD32(0x00000080) 694 695 /* 696 * FIXME: where the DEBUG_INDEX name come from? 697 */ 698 #define MAC_DEBUG_INDEX 0x05e8 699 #define MAC_DEBUG_INDEX_XTAL FIELD32(0x80000000) 700 701 /* 702 * MAC Control/Status Registers(CSR). 703 * Some values are set in TU, whereas 1 TU == 1024 us. 704 */ 705 706 /* 707 * MAC_CSR0: ASIC revision number. 708 * ASIC_REV: 0 709 * ASIC_VER: 2860 or 2870 710 */ 711 #define MAC_CSR0 0x1000 712 #define MAC_CSR0_REVISION FIELD32(0x0000ffff) 713 #define MAC_CSR0_CHIPSET FIELD32(0xffff0000) 714 715 /* 716 * MAC_SYS_CTRL: 717 */ 718 #define MAC_SYS_CTRL 0x1004 719 #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001) 720 #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002) 721 #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004) 722 #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008) 723 #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010) 724 #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020) 725 #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040) 726 #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080) 727 728 /* 729 * MAC_ADDR_DW0: STA MAC register 0 730 */ 731 #define MAC_ADDR_DW0 0x1008 732 #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff) 733 #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00) 734 #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000) 735 #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000) 736 737 /* 738 * MAC_ADDR_DW1: STA MAC register 1 739 * UNICAST_TO_ME_MASK: 740 * Used to mask off bits from byte 5 of the MAC address 741 * to determine the UNICAST_TO_ME bit for RX frames. 742 * The full mask is complemented by BSS_ID_MASK: 743 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK 744 */ 745 #define MAC_ADDR_DW1 0x100c 746 #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff) 747 #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00) 748 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000) 749 750 /* 751 * MAC_BSSID_DW0: BSSID register 0 752 */ 753 #define MAC_BSSID_DW0 0x1010 754 #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff) 755 #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00) 756 #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000) 757 #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000) 758 759 /* 760 * MAC_BSSID_DW1: BSSID register 1 761 * BSS_ID_MASK: 762 * 0: 1-BSSID mode (BSS index = 0) 763 * 1: 2-BSSID mode (BSS index: Byte5, bit 0) 764 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1) 765 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2) 766 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the 767 * BSSID. This will make sure that those bits will be ignored 768 * when determining the MY_BSS of RX frames. 769 */ 770 #define MAC_BSSID_DW1 0x1014 771 #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff) 772 #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00) 773 #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000) 774 #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000) 775 776 /* 777 * MAX_LEN_CFG: Maximum frame length register. 778 * MAX_MPDU: rt2860b max 16k bytes 779 * MAX_PSDU: Maximum PSDU length 780 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16 781 */ 782 #define MAX_LEN_CFG 0x1018 783 #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff) 784 #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000) 785 #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000) 786 #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000) 787 788 /* 789 * BBP_CSR_CFG: BBP serial control register 790 * VALUE: Register value to program into BBP 791 * REG_NUM: Selected BBP register 792 * READ_CONTROL: 0 write BBP, 1 read BBP 793 * BUSY: ASIC is busy executing BBP commands 794 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks 795 * BBP_RW_MODE: 0 serial, 1 parallel 796 */ 797 #define BBP_CSR_CFG 0x101c 798 #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff) 799 #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00) 800 #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000) 801 #define BBP_CSR_CFG_BUSY FIELD32(0x00020000) 802 #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000) 803 #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000) 804 805 /* 806 * RF_CSR_CFG0: RF control register 807 * REGID_AND_VALUE: Register value to program into RF 808 * BITWIDTH: Selected RF register 809 * STANDBYMODE: 0 high when standby, 1 low when standby 810 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate 811 * BUSY: ASIC is busy executing RF commands 812 */ 813 #define RF_CSR_CFG0 0x1020 814 #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff) 815 #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000) 816 #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff) 817 #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000) 818 #define RF_CSR_CFG0_SEL FIELD32(0x40000000) 819 #define RF_CSR_CFG0_BUSY FIELD32(0x80000000) 820 821 /* 822 * RF_CSR_CFG1: RF control register 823 * REGID_AND_VALUE: Register value to program into RF 824 * RFGAP: Gap between BB_CONTROL_RF and RF_LE 825 * 0: 3 system clock cycle (37.5usec) 826 * 1: 5 system clock cycle (62.5usec) 827 */ 828 #define RF_CSR_CFG1 0x1024 829 #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff) 830 #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000) 831 832 /* 833 * RF_CSR_CFG2: RF control register 834 * VALUE: Register value to program into RF 835 */ 836 #define RF_CSR_CFG2 0x1028 837 #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff) 838 839 /* 840 * LED_CFG: LED control 841 * ON_PERIOD: LED active time (ms) during TX (only used for LED mode 1) 842 * OFF_PERIOD: LED inactive time (ms) during TX (only used for LED mode 1) 843 * SLOW_BLINK_PERIOD: LED blink interval in seconds (only used for LED mode 2) 844 * color LED's: 845 * 0: off 846 * 1: blinking upon TX2 847 * 2: periodic slow blinking 848 * 3: always on 849 * LED polarity: 850 * 0: active low 851 * 1: active high 852 */ 853 #define LED_CFG 0x102c 854 #define LED_CFG_ON_PERIOD FIELD32(0x000000ff) 855 #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00) 856 #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000) 857 #define LED_CFG_R_LED_MODE FIELD32(0x03000000) 858 #define LED_CFG_G_LED_MODE FIELD32(0x0c000000) 859 #define LED_CFG_Y_LED_MODE FIELD32(0x30000000) 860 #define LED_CFG_LED_POLAR FIELD32(0x40000000) 861 862 /* 863 * AMPDU_BA_WINSIZE: Force BlockAck window size 864 * FORCE_WINSIZE_ENABLE: 865 * 0: Disable forcing of BlockAck window size 866 * 1: Enable forcing of BlockAck window size, overwrites values BlockAck 867 * window size values in the TXWI 868 * FORCE_WINSIZE: BlockAck window size 869 */ 870 #define AMPDU_BA_WINSIZE 0x1040 871 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020) 872 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f) 873 874 /* 875 * XIFS_TIME_CFG: MAC timing 876 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX 877 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX 878 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX 879 * when MAC doesn't reference BBP signal BBRXEND 880 * EIFS: unit 1us 881 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer 882 * 883 */ 884 #define XIFS_TIME_CFG 0x1100 885 #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff) 886 #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00) 887 #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000) 888 #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000) 889 #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000) 890 891 /* 892 * BKOFF_SLOT_CFG: 893 */ 894 #define BKOFF_SLOT_CFG 0x1104 895 #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff) 896 #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00) 897 898 /* 899 * NAV_TIME_CFG: 900 */ 901 #define NAV_TIME_CFG 0x1108 902 #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff) 903 #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00) 904 #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000) 905 #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000) 906 907 /* 908 * CH_TIME_CFG: count as channel busy 909 * EIFS_BUSY: Count EIFS as channel busy 910 * NAV_BUSY: Count NAS as channel busy 911 * RX_BUSY: Count RX as channel busy 912 * TX_BUSY: Count TX as channel busy 913 * TMR_EN: Enable channel statistics timer 914 */ 915 #define CH_TIME_CFG 0x110c 916 #define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010) 917 #define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008) 918 #define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004) 919 #define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002) 920 #define CH_TIME_CFG_TMR_EN FIELD32(0x00000001) 921 922 /* 923 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us 924 */ 925 #define PBF_LIFE_TIMER 0x1110 926 927 /* 928 * BCN_TIME_CFG: 929 * BEACON_INTERVAL: in unit of 1/16 TU 930 * TSF_TICKING: Enable TSF auto counting 931 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode 932 * BEACON_GEN: Enable beacon generator 933 */ 934 #define BCN_TIME_CFG 0x1114 935 #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff) 936 #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000) 937 #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000) 938 #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000) 939 #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000) 940 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000) 941 942 /* 943 * TBTT_SYNC_CFG: 944 * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots 945 * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots 946 */ 947 #define TBTT_SYNC_CFG 0x1118 948 #define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff) 949 #define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00) 950 #define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000) 951 #define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000) 952 953 /* 954 * TSF_TIMER_DW0: Local lsb TSF timer, read-only 955 */ 956 #define TSF_TIMER_DW0 0x111c 957 #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff) 958 959 /* 960 * TSF_TIMER_DW1: Local msb TSF timer, read-only 961 */ 962 #define TSF_TIMER_DW1 0x1120 963 #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff) 964 965 /* 966 * TBTT_TIMER: TImer remains till next TBTT, read-only 967 */ 968 #define TBTT_TIMER 0x1124 969 970 /* 971 * INT_TIMER_CFG: timer configuration 972 * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU 973 * GP_TIMER: period of general purpose timer in units of 1/16 TU 974 */ 975 #define INT_TIMER_CFG 0x1128 976 #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff) 977 #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000) 978 979 /* 980 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable 981 */ 982 #define INT_TIMER_EN 0x112c 983 #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001) 984 #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002) 985 986 /* 987 * CH_IDLE_STA: channel idle time (in us) 988 */ 989 #define CH_IDLE_STA 0x1130 990 991 /* 992 * CH_BUSY_STA: channel busy time on primary channel (in us) 993 */ 994 #define CH_BUSY_STA 0x1134 995 996 /* 997 * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us) 998 */ 999 #define CH_BUSY_STA_SEC 0x1138 1000 1001 /* 1002 * MAC_STATUS_CFG: 1003 * BBP_RF_BUSY: When set to 0, BBP and RF are stable. 1004 * if 1 or higher one of the 2 registers is busy. 1005 */ 1006 #define MAC_STATUS_CFG 0x1200 1007 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003) 1008 1009 /* 1010 * PWR_PIN_CFG: 1011 */ 1012 #define PWR_PIN_CFG 0x1204 1013 1014 /* 1015 * AUTOWAKEUP_CFG: Manual power control / status register 1016 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set 1017 * AUTOWAKE: 0:sleep, 1:awake 1018 */ 1019 #define AUTOWAKEUP_CFG 0x1208 1020 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff) 1021 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00) 1022 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000) 1023 1024 /* 1025 * EDCA_AC0_CFG: 1026 */ 1027 #define EDCA_AC0_CFG 0x1300 1028 #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff) 1029 #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00) 1030 #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000) 1031 #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000) 1032 1033 /* 1034 * EDCA_AC1_CFG: 1035 */ 1036 #define EDCA_AC1_CFG 0x1304 1037 #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff) 1038 #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00) 1039 #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000) 1040 #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000) 1041 1042 /* 1043 * EDCA_AC2_CFG: 1044 */ 1045 #define EDCA_AC2_CFG 0x1308 1046 #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff) 1047 #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00) 1048 #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000) 1049 #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000) 1050 1051 /* 1052 * EDCA_AC3_CFG: 1053 */ 1054 #define EDCA_AC3_CFG 0x130c 1055 #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff) 1056 #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00) 1057 #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000) 1058 #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000) 1059 1060 /* 1061 * EDCA_TID_AC_MAP: 1062 */ 1063 #define EDCA_TID_AC_MAP 0x1310 1064 1065 /* 1066 * TX_PWR_CFG: 1067 */ 1068 #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f) 1069 #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0) 1070 #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00) 1071 #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000) 1072 #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000) 1073 #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000) 1074 #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000) 1075 #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000) 1076 1077 /* 1078 * TX_PWR_CFG_0: 1079 */ 1080 #define TX_PWR_CFG_0 0x1314 1081 #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f) 1082 #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0) 1083 #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00) 1084 #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000) 1085 #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000) 1086 #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000) 1087 #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000) 1088 #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000) 1089 /* bits for 3T devices */ 1090 #define TX_PWR_CFG_0_CCK1_CH0 FIELD32(0x0000000f) 1091 #define TX_PWR_CFG_0_CCK1_CH1 FIELD32(0x000000f0) 1092 #define TX_PWR_CFG_0_CCK5_CH0 FIELD32(0x00000f00) 1093 #define TX_PWR_CFG_0_CCK5_CH1 FIELD32(0x0000f000) 1094 #define TX_PWR_CFG_0_OFDM6_CH0 FIELD32(0x000f0000) 1095 #define TX_PWR_CFG_0_OFDM6_CH1 FIELD32(0x00f00000) 1096 #define TX_PWR_CFG_0_OFDM12_CH0 FIELD32(0x0f000000) 1097 #define TX_PWR_CFG_0_OFDM12_CH1 FIELD32(0xf0000000) 1098 1099 /* 1100 * TX_PWR_CFG_1: 1101 */ 1102 #define TX_PWR_CFG_1 0x1318 1103 #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f) 1104 #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0) 1105 #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00) 1106 #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000) 1107 #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000) 1108 #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000) 1109 #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000) 1110 #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000) 1111 /* bits for 3T devices */ 1112 #define TX_PWR_CFG_1_OFDM24_CH0 FIELD32(0x0000000f) 1113 #define TX_PWR_CFG_1_OFDM24_CH1 FIELD32(0x000000f0) 1114 #define TX_PWR_CFG_1_OFDM48_CH0 FIELD32(0x00000f00) 1115 #define TX_PWR_CFG_1_OFDM48_CH1 FIELD32(0x0000f000) 1116 #define TX_PWR_CFG_1_MCS0_CH0 FIELD32(0x000f0000) 1117 #define TX_PWR_CFG_1_MCS0_CH1 FIELD32(0x00f00000) 1118 #define TX_PWR_CFG_1_MCS2_CH0 FIELD32(0x0f000000) 1119 #define TX_PWR_CFG_1_MCS2_CH1 FIELD32(0xf0000000) 1120 1121 /* 1122 * TX_PWR_CFG_2: 1123 */ 1124 #define TX_PWR_CFG_2 0x131c 1125 #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f) 1126 #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0) 1127 #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00) 1128 #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000) 1129 #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000) 1130 #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000) 1131 #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000) 1132 #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000) 1133 /* bits for 3T devices */ 1134 #define TX_PWR_CFG_2_MCS4_CH0 FIELD32(0x0000000f) 1135 #define TX_PWR_CFG_2_MCS4_CH1 FIELD32(0x000000f0) 1136 #define TX_PWR_CFG_2_MCS6_CH0 FIELD32(0x00000f00) 1137 #define TX_PWR_CFG_2_MCS6_CH1 FIELD32(0x0000f000) 1138 #define TX_PWR_CFG_2_MCS8_CH0 FIELD32(0x000f0000) 1139 #define TX_PWR_CFG_2_MCS8_CH1 FIELD32(0x00f00000) 1140 #define TX_PWR_CFG_2_MCS10_CH0 FIELD32(0x0f000000) 1141 #define TX_PWR_CFG_2_MCS10_CH1 FIELD32(0xf0000000) 1142 1143 /* 1144 * TX_PWR_CFG_3: 1145 */ 1146 #define TX_PWR_CFG_3 0x1320 1147 #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f) 1148 #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0) 1149 #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00) 1150 #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000) 1151 #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000) 1152 #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000) 1153 #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000) 1154 #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000) 1155 /* bits for 3T devices */ 1156 #define TX_PWR_CFG_3_MCS12_CH0 FIELD32(0x0000000f) 1157 #define TX_PWR_CFG_3_MCS12_CH1 FIELD32(0x000000f0) 1158 #define TX_PWR_CFG_3_MCS14_CH0 FIELD32(0x00000f00) 1159 #define TX_PWR_CFG_3_MCS14_CH1 FIELD32(0x0000f000) 1160 #define TX_PWR_CFG_3_STBC0_CH0 FIELD32(0x000f0000) 1161 #define TX_PWR_CFG_3_STBC0_CH1 FIELD32(0x00f00000) 1162 #define TX_PWR_CFG_3_STBC2_CH0 FIELD32(0x0f000000) 1163 #define TX_PWR_CFG_3_STBC2_CH1 FIELD32(0xf0000000) 1164 1165 /* 1166 * TX_PWR_CFG_4: 1167 */ 1168 #define TX_PWR_CFG_4 0x1324 1169 #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f) 1170 #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0) 1171 #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00) 1172 #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000) 1173 /* bits for 3T devices */ 1174 #define TX_PWR_CFG_3_STBC4_CH0 FIELD32(0x0000000f) 1175 #define TX_PWR_CFG_3_STBC4_CH1 FIELD32(0x000000f0) 1176 #define TX_PWR_CFG_3_STBC6_CH0 FIELD32(0x00000f00) 1177 #define TX_PWR_CFG_3_STBC6_CH1 FIELD32(0x0000f000) 1178 1179 /* 1180 * TX_PIN_CFG: 1181 */ 1182 #define TX_PIN_CFG 0x1328 1183 #define TX_PIN_CFG_PA_PE_DISABLE 0xfcfffff0 1184 #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001) 1185 #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002) 1186 #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004) 1187 #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008) 1188 #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010) 1189 #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020) 1190 #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040) 1191 #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080) 1192 #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100) 1193 #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200) 1194 #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400) 1195 #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800) 1196 #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000) 1197 #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000) 1198 #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000) 1199 #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000) 1200 #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000) 1201 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000) 1202 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000) 1203 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000) 1204 #define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000) 1205 #define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000) 1206 #define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000) 1207 #define TX_PIN_CFG_PA_PE_G2_POL FIELD32(0x08000000) 1208 #define TX_PIN_CFG_LNA_PE_A2_EN FIELD32(0x10000000) 1209 #define TX_PIN_CFG_LNA_PE_G2_EN FIELD32(0x20000000) 1210 #define TX_PIN_CFG_LNA_PE_A2_POL FIELD32(0x40000000) 1211 #define TX_PIN_CFG_LNA_PE_G2_POL FIELD32(0x80000000) 1212 1213 /* 1214 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz 1215 */ 1216 #define TX_BAND_CFG 0x132c 1217 #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001) 1218 #define TX_BAND_CFG_A FIELD32(0x00000002) 1219 #define TX_BAND_CFG_BG FIELD32(0x00000004) 1220 1221 /* 1222 * TX_SW_CFG0: 1223 */ 1224 #define TX_SW_CFG0 0x1330 1225 1226 /* 1227 * TX_SW_CFG1: 1228 */ 1229 #define TX_SW_CFG1 0x1334 1230 1231 /* 1232 * TX_SW_CFG2: 1233 */ 1234 #define TX_SW_CFG2 0x1338 1235 1236 /* 1237 * TXOP_THRES_CFG: 1238 */ 1239 #define TXOP_THRES_CFG 0x133c 1240 1241 /* 1242 * TXOP_CTRL_CFG: 1243 * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation 1244 * AC_TRUN_EN: Enable/Disable truncation for AC change 1245 * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change 1246 * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode 1247 * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS 1248 * RESERVED_TRUN_EN: Reserved 1249 * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection 1250 * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz 1251 * transmissions if extension CCA is clear). 1252 * EXT_CCA_DLY: Extension CCA signal delay time (unit: us) 1253 * EXT_CWMIN: CwMin for extension channel backoff 1254 * 0: Disabled 1255 * 1256 */ 1257 #define TXOP_CTRL_CFG 0x1340 1258 #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001) 1259 #define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002) 1260 #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004) 1261 #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008) 1262 #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010) 1263 #define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020) 1264 #define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040) 1265 #define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080) 1266 #define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00) 1267 #define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000) 1268 1269 /* 1270 * TX_RTS_CFG: 1271 * RTS_THRES: unit:byte 1272 * RTS_FBK_EN: enable rts rate fallback 1273 */ 1274 #define TX_RTS_CFG 0x1344 1275 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff) 1276 #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00) 1277 #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000) 1278 1279 /* 1280 * TX_TIMEOUT_CFG: 1281 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us 1282 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure 1283 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation. 1284 * it is recommended that: 1285 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT) 1286 */ 1287 #define TX_TIMEOUT_CFG 0x1348 1288 #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0) 1289 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00) 1290 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000) 1291 1292 /* 1293 * TX_RTY_CFG: 1294 * SHORT_RTY_LIMIT: short retry limit 1295 * LONG_RTY_LIMIT: long retry limit 1296 * LONG_RTY_THRE: Long retry threshoold 1297 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode 1298 * 0:expired by retry limit, 1: expired by mpdu life timer 1299 * AGG_RTY_MODE: Aggregate MPDU retry mode 1300 * 0:expired by retry limit, 1: expired by mpdu life timer 1301 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable 1302 */ 1303 #define TX_RTY_CFG 0x134c 1304 #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff) 1305 #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00) 1306 #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000) 1307 #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000) 1308 #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000) 1309 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000) 1310 1311 /* 1312 * TX_LINK_CFG: 1313 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us 1314 * MFB_ENABLE: TX apply remote MFB 1:enable 1315 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable 1316 * 0: not apply remote remote unsolicit (MFS=7) 1317 * TX_MRQ_EN: MCS request TX enable 1318 * TX_RDG_EN: RDG TX enable 1319 * TX_CF_ACK_EN: Piggyback CF-ACK enable 1320 * REMOTE_MFB: remote MCS feedback 1321 * REMOTE_MFS: remote MCS feedback sequence number 1322 */ 1323 #define TX_LINK_CFG 0x1350 1324 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff) 1325 #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100) 1326 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200) 1327 #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400) 1328 #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800) 1329 #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000) 1330 #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000) 1331 #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000) 1332 1333 /* 1334 * HT_FBK_CFG0: 1335 */ 1336 #define HT_FBK_CFG0 0x1354 1337 #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f) 1338 #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0) 1339 #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00) 1340 #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000) 1341 #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000) 1342 #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000) 1343 #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000) 1344 #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000) 1345 1346 /* 1347 * HT_FBK_CFG1: 1348 */ 1349 #define HT_FBK_CFG1 0x1358 1350 #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f) 1351 #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0) 1352 #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00) 1353 #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000) 1354 #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000) 1355 #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000) 1356 #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000) 1357 #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000) 1358 1359 /* 1360 * LG_FBK_CFG0: 1361 */ 1362 #define LG_FBK_CFG0 0x135c 1363 #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f) 1364 #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0) 1365 #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00) 1366 #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000) 1367 #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000) 1368 #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000) 1369 #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000) 1370 #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000) 1371 1372 /* 1373 * LG_FBK_CFG1: 1374 */ 1375 #define LG_FBK_CFG1 0x1360 1376 #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f) 1377 #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0) 1378 #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00) 1379 #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000) 1380 1381 /* 1382 * CCK_PROT_CFG: CCK Protection 1383 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd) 1384 * PROTECT_CTRL: Protection control frame type for CCK TX 1385 * 0:none, 1:RTS/CTS, 2:CTS-to-self 1386 * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV 1387 * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV 1388 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow 1389 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow 1390 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow 1391 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow 1392 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow 1393 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow 1394 * RTS_TH_EN: RTS threshold enable on CCK TX 1395 */ 1396 #define CCK_PROT_CFG 0x1364 1397 #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1398 #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1399 #define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1400 #define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1401 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1402 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1403 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1404 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1405 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1406 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1407 #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1408 1409 /* 1410 * OFDM_PROT_CFG: OFDM Protection 1411 */ 1412 #define OFDM_PROT_CFG 0x1368 1413 #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1414 #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1415 #define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1416 #define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1417 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1418 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1419 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1420 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1421 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1422 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1423 #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1424 1425 /* 1426 * MM20_PROT_CFG: MM20 Protection 1427 */ 1428 #define MM20_PROT_CFG 0x136c 1429 #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1430 #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1431 #define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1432 #define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1433 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1434 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1435 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1436 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1437 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1438 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1439 #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1440 1441 /* 1442 * MM40_PROT_CFG: MM40 Protection 1443 */ 1444 #define MM40_PROT_CFG 0x1370 1445 #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1446 #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1447 #define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1448 #define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1449 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1450 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1451 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1452 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1453 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1454 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1455 #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1456 1457 /* 1458 * GF20_PROT_CFG: GF20 Protection 1459 */ 1460 #define GF20_PROT_CFG 0x1374 1461 #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1462 #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1463 #define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1464 #define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1465 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1466 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1467 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1468 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1469 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1470 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1471 #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1472 1473 /* 1474 * GF40_PROT_CFG: GF40 Protection 1475 */ 1476 #define GF40_PROT_CFG 0x1378 1477 #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1478 #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1479 #define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1480 #define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1481 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1482 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1483 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1484 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1485 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1486 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1487 #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1488 1489 /* 1490 * EXP_CTS_TIME: 1491 */ 1492 #define EXP_CTS_TIME 0x137c 1493 1494 /* 1495 * EXP_ACK_TIME: 1496 */ 1497 #define EXP_ACK_TIME 0x1380 1498 1499 /* TX_PWR_CFG_5 */ 1500 #define TX_PWR_CFG_5 0x1384 1501 #define TX_PWR_CFG_5_MCS16_CH0 FIELD32(0x0000000f) 1502 #define TX_PWR_CFG_5_MCS16_CH1 FIELD32(0x000000f0) 1503 #define TX_PWR_CFG_5_MCS16_CH2 FIELD32(0x00000f00) 1504 #define TX_PWR_CFG_5_MCS18_CH0 FIELD32(0x000f0000) 1505 #define TX_PWR_CFG_5_MCS18_CH1 FIELD32(0x00f00000) 1506 #define TX_PWR_CFG_5_MCS18_CH2 FIELD32(0x0f000000) 1507 1508 /* TX_PWR_CFG_6 */ 1509 #define TX_PWR_CFG_6 0x1388 1510 #define TX_PWR_CFG_6_MCS20_CH0 FIELD32(0x0000000f) 1511 #define TX_PWR_CFG_6_MCS20_CH1 FIELD32(0x000000f0) 1512 #define TX_PWR_CFG_6_MCS20_CH2 FIELD32(0x00000f00) 1513 #define TX_PWR_CFG_6_MCS22_CH0 FIELD32(0x000f0000) 1514 #define TX_PWR_CFG_6_MCS22_CH1 FIELD32(0x00f00000) 1515 #define TX_PWR_CFG_6_MCS22_CH2 FIELD32(0x0f000000) 1516 1517 /* TX_PWR_CFG_0_EXT */ 1518 #define TX_PWR_CFG_0_EXT 0x1390 1519 #define TX_PWR_CFG_0_EXT_CCK1_CH2 FIELD32(0x0000000f) 1520 #define TX_PWR_CFG_0_EXT_CCK5_CH2 FIELD32(0x00000f00) 1521 #define TX_PWR_CFG_0_EXT_OFDM6_CH2 FIELD32(0x000f0000) 1522 #define TX_PWR_CFG_0_EXT_OFDM12_CH2 FIELD32(0x0f000000) 1523 1524 /* TX_PWR_CFG_1_EXT */ 1525 #define TX_PWR_CFG_1_EXT 0x1394 1526 #define TX_PWR_CFG_1_EXT_OFDM24_CH2 FIELD32(0x0000000f) 1527 #define TX_PWR_CFG_1_EXT_OFDM48_CH2 FIELD32(0x00000f00) 1528 #define TX_PWR_CFG_1_EXT_MCS0_CH2 FIELD32(0x000f0000) 1529 #define TX_PWR_CFG_1_EXT_MCS2_CH2 FIELD32(0x0f000000) 1530 1531 /* TX_PWR_CFG_2_EXT */ 1532 #define TX_PWR_CFG_2_EXT 0x1398 1533 #define TX_PWR_CFG_2_EXT_MCS4_CH2 FIELD32(0x0000000f) 1534 #define TX_PWR_CFG_2_EXT_MCS6_CH2 FIELD32(0x00000f00) 1535 #define TX_PWR_CFG_2_EXT_MCS8_CH2 FIELD32(0x000f0000) 1536 #define TX_PWR_CFG_2_EXT_MCS10_CH2 FIELD32(0x0f000000) 1537 1538 /* TX_PWR_CFG_3_EXT */ 1539 #define TX_PWR_CFG_3_EXT 0x139c 1540 #define TX_PWR_CFG_3_EXT_MCS12_CH2 FIELD32(0x0000000f) 1541 #define TX_PWR_CFG_3_EXT_MCS14_CH2 FIELD32(0x00000f00) 1542 #define TX_PWR_CFG_3_EXT_STBC0_CH2 FIELD32(0x000f0000) 1543 #define TX_PWR_CFG_3_EXT_STBC2_CH2 FIELD32(0x0f000000) 1544 1545 /* TX_PWR_CFG_4_EXT */ 1546 #define TX_PWR_CFG_4_EXT 0x13a0 1547 #define TX_PWR_CFG_4_EXT_STBC4_CH2 FIELD32(0x0000000f) 1548 #define TX_PWR_CFG_4_EXT_STBC6_CH2 FIELD32(0x00000f00) 1549 1550 /* TX_PWR_CFG_7 */ 1551 #define TX_PWR_CFG_7 0x13d4 1552 #define TX_PWR_CFG_7_OFDM54_CH0 FIELD32(0x0000000f) 1553 #define TX_PWR_CFG_7_OFDM54_CH1 FIELD32(0x000000f0) 1554 #define TX_PWR_CFG_7_OFDM54_CH2 FIELD32(0x00000f00) 1555 #define TX_PWR_CFG_7_MCS7_CH0 FIELD32(0x000f0000) 1556 #define TX_PWR_CFG_7_MCS7_CH1 FIELD32(0x00f00000) 1557 #define TX_PWR_CFG_7_MCS7_CH2 FIELD32(0x0f000000) 1558 1559 /* TX_PWR_CFG_8 */ 1560 #define TX_PWR_CFG_8 0x13d8 1561 #define TX_PWR_CFG_8_MCS15_CH0 FIELD32(0x0000000f) 1562 #define TX_PWR_CFG_8_MCS15_CH1 FIELD32(0x000000f0) 1563 #define TX_PWR_CFG_8_MCS15_CH2 FIELD32(0x00000f00) 1564 #define TX_PWR_CFG_8_MCS23_CH0 FIELD32(0x000f0000) 1565 #define TX_PWR_CFG_8_MCS23_CH1 FIELD32(0x00f00000) 1566 #define TX_PWR_CFG_8_MCS23_CH2 FIELD32(0x0f000000) 1567 1568 /* TX_PWR_CFG_9 */ 1569 #define TX_PWR_CFG_9 0x13dc 1570 #define TX_PWR_CFG_9_STBC7_CH0 FIELD32(0x0000000f) 1571 #define TX_PWR_CFG_9_STBC7_CH1 FIELD32(0x000000f0) 1572 #define TX_PWR_CFG_9_STBC7_CH2 FIELD32(0x00000f00) 1573 1574 /* 1575 * RX_FILTER_CFG: RX configuration register. 1576 */ 1577 #define RX_FILTER_CFG 0x1400 1578 #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001) 1579 #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002) 1580 #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004) 1581 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008) 1582 #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010) 1583 #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020) 1584 #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040) 1585 #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080) 1586 #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100) 1587 #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200) 1588 #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400) 1589 #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800) 1590 #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000) 1591 #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000) 1592 #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000) 1593 #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000) 1594 #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000) 1595 1596 /* 1597 * AUTO_RSP_CFG: 1598 * AUTORESPONDER: 0: disable, 1: enable 1599 * BAC_ACK_POLICY: 0:long, 1:short preamble 1600 * CTS_40_MMODE: Response CTS 40MHz duplicate mode 1601 * CTS_40_MREF: Response CTS 40MHz duplicate mode 1602 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble 1603 * DUAL_CTS_EN: Power bit value in control frame 1604 * ACK_CTS_PSM_BIT:Power bit value in control frame 1605 */ 1606 #define AUTO_RSP_CFG 0x1404 1607 #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001) 1608 #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002) 1609 #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004) 1610 #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008) 1611 #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010) 1612 #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040) 1613 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080) 1614 1615 /* 1616 * LEGACY_BASIC_RATE: 1617 */ 1618 #define LEGACY_BASIC_RATE 0x1408 1619 1620 /* 1621 * HT_BASIC_RATE: 1622 */ 1623 #define HT_BASIC_RATE 0x140c 1624 1625 /* 1626 * HT_CTRL_CFG: 1627 */ 1628 #define HT_CTRL_CFG 0x1410 1629 1630 /* 1631 * SIFS_COST_CFG: 1632 */ 1633 #define SIFS_COST_CFG 0x1414 1634 1635 /* 1636 * RX_PARSER_CFG: 1637 * Set NAV for all received frames 1638 */ 1639 #define RX_PARSER_CFG 0x1418 1640 1641 /* 1642 * TX_SEC_CNT0: 1643 */ 1644 #define TX_SEC_CNT0 0x1500 1645 1646 /* 1647 * RX_SEC_CNT0: 1648 */ 1649 #define RX_SEC_CNT0 0x1504 1650 1651 /* 1652 * CCMP_FC_MUTE: 1653 */ 1654 #define CCMP_FC_MUTE 0x1508 1655 1656 /* 1657 * TXOP_HLDR_ADDR0: 1658 */ 1659 #define TXOP_HLDR_ADDR0 0x1600 1660 1661 /* 1662 * TXOP_HLDR_ADDR1: 1663 */ 1664 #define TXOP_HLDR_ADDR1 0x1604 1665 1666 /* 1667 * TXOP_HLDR_ET: 1668 */ 1669 #define TXOP_HLDR_ET 0x1608 1670 1671 /* 1672 * QOS_CFPOLL_RA_DW0: 1673 */ 1674 #define QOS_CFPOLL_RA_DW0 0x160c 1675 1676 /* 1677 * QOS_CFPOLL_RA_DW1: 1678 */ 1679 #define QOS_CFPOLL_RA_DW1 0x1610 1680 1681 /* 1682 * QOS_CFPOLL_QC: 1683 */ 1684 #define QOS_CFPOLL_QC 0x1614 1685 1686 /* 1687 * RX_STA_CNT0: RX PLCP error count & RX CRC error count 1688 */ 1689 #define RX_STA_CNT0 0x1700 1690 #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff) 1691 #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000) 1692 1693 /* 1694 * RX_STA_CNT1: RX False CCA count & RX LONG frame count 1695 */ 1696 #define RX_STA_CNT1 0x1704 1697 #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff) 1698 #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000) 1699 1700 /* 1701 * RX_STA_CNT2: 1702 */ 1703 #define RX_STA_CNT2 0x1708 1704 #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff) 1705 #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000) 1706 1707 /* 1708 * TX_STA_CNT0: TX Beacon count 1709 */ 1710 #define TX_STA_CNT0 0x170c 1711 #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff) 1712 #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000) 1713 1714 /* 1715 * TX_STA_CNT1: TX tx count 1716 */ 1717 #define TX_STA_CNT1 0x1710 1718 #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff) 1719 #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000) 1720 1721 /* 1722 * TX_STA_CNT2: TX tx count 1723 */ 1724 #define TX_STA_CNT2 0x1714 1725 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff) 1726 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000) 1727 1728 /* 1729 * TX_STA_FIFO: TX Result for specific PID status fifo register. 1730 * 1731 * This register is implemented as FIFO with 16 entries in the HW. Each 1732 * register read fetches the next tx result. If the FIFO is full because 1733 * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS) 1734 * triggered, the hw seems to simply drop further tx results. 1735 * 1736 * VALID: 1: this tx result is valid 1737 * 0: no valid tx result -> driver should stop reading 1738 * PID_TYPE: The PID latched from the PID field in the TXWI, can be used 1739 * to match a frame with its tx result (even though the PID is 1740 * only 4 bits wide). 1741 * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3) 1742 * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3) 1743 * This identification number is calculated by ((idx % 3) + 1). 1744 * TX_SUCCESS: Indicates tx success (1) or failure (0) 1745 * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0) 1746 * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0) 1747 * WCID: The wireless client ID. 1748 * MCS: The tx rate used during the last transmission of this frame, be it 1749 * successful or not. 1750 * PHYMODE: The phymode used for the transmission. 1751 */ 1752 #define TX_STA_FIFO 0x1718 1753 #define TX_STA_FIFO_VALID FIELD32(0x00000001) 1754 #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e) 1755 #define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006) 1756 #define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018) 1757 #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020) 1758 #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040) 1759 #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080) 1760 #define TX_STA_FIFO_WCID FIELD32(0x0000ff00) 1761 #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000) 1762 #define TX_STA_FIFO_MCS FIELD32(0x007f0000) 1763 #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000) 1764 1765 /* 1766 * TX_AGG_CNT: Debug counter 1767 */ 1768 #define TX_AGG_CNT 0x171c 1769 #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff) 1770 #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000) 1771 1772 /* 1773 * TX_AGG_CNT0: 1774 */ 1775 #define TX_AGG_CNT0 0x1720 1776 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff) 1777 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000) 1778 1779 /* 1780 * TX_AGG_CNT1: 1781 */ 1782 #define TX_AGG_CNT1 0x1724 1783 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff) 1784 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000) 1785 1786 /* 1787 * TX_AGG_CNT2: 1788 */ 1789 #define TX_AGG_CNT2 0x1728 1790 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff) 1791 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000) 1792 1793 /* 1794 * TX_AGG_CNT3: 1795 */ 1796 #define TX_AGG_CNT3 0x172c 1797 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff) 1798 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000) 1799 1800 /* 1801 * TX_AGG_CNT4: 1802 */ 1803 #define TX_AGG_CNT4 0x1730 1804 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff) 1805 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000) 1806 1807 /* 1808 * TX_AGG_CNT5: 1809 */ 1810 #define TX_AGG_CNT5 0x1734 1811 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff) 1812 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000) 1813 1814 /* 1815 * TX_AGG_CNT6: 1816 */ 1817 #define TX_AGG_CNT6 0x1738 1818 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff) 1819 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000) 1820 1821 /* 1822 * TX_AGG_CNT7: 1823 */ 1824 #define TX_AGG_CNT7 0x173c 1825 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff) 1826 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000) 1827 1828 /* 1829 * MPDU_DENSITY_CNT: 1830 * TX_ZERO_DEL: TX zero length delimiter count 1831 * RX_ZERO_DEL: RX zero length delimiter count 1832 */ 1833 #define MPDU_DENSITY_CNT 0x1740 1834 #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff) 1835 #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000) 1836 1837 /* 1838 * Security key table memory. 1839 * 1840 * The pairwise key table shares some memory with the beacon frame 1841 * buffers 6 and 7. That basically means that when beacon 6 & 7 1842 * are used we should only use the reduced pairwise key table which 1843 * has a maximum of 222 entries. 1844 * 1845 * --------------------------------------------- 1846 * |0x4000 | Pairwise Key | Reduced Pairwise | 1847 * | | Table | Key Table | 1848 * | | Size: 256 * 32 | Size: 222 * 32 | 1849 * |0x5BC0 | |------------------- 1850 * | | | Beacon 6 | 1851 * |0x5DC0 | |------------------- 1852 * | | | Beacon 7 | 1853 * |0x5FC0 | |------------------- 1854 * |0x5FFF | | 1855 * -------------------------- 1856 * 1857 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry 1858 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry 1859 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry 1860 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry 1861 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry 1862 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry 1863 */ 1864 #define MAC_WCID_BASE 0x1800 1865 #define PAIRWISE_KEY_TABLE_BASE 0x4000 1866 #define MAC_IVEIV_TABLE_BASE 0x6000 1867 #define MAC_WCID_ATTRIBUTE_BASE 0x6800 1868 #define SHARED_KEY_TABLE_BASE 0x6c00 1869 #define SHARED_KEY_MODE_BASE 0x7000 1870 1871 #define MAC_WCID_ENTRY(__idx) \ 1872 (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry))) 1873 #define PAIRWISE_KEY_ENTRY(__idx) \ 1874 (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry))) 1875 #define MAC_IVEIV_ENTRY(__idx) \ 1876 (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry))) 1877 #define MAC_WCID_ATTR_ENTRY(__idx) \ 1878 (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32))) 1879 #define SHARED_KEY_ENTRY(__idx) \ 1880 (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry))) 1881 #define SHARED_KEY_MODE_ENTRY(__idx) \ 1882 (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32))) 1883 1884 struct mac_wcid_entry { 1885 u8 mac[6]; 1886 u8 reserved[2]; 1887 } __packed; 1888 1889 struct hw_key_entry { 1890 u8 key[16]; 1891 u8 tx_mic[8]; 1892 u8 rx_mic[8]; 1893 } __packed; 1894 1895 struct mac_iveiv_entry { 1896 u8 iv[8]; 1897 } __packed; 1898 1899 /* 1900 * MAC_WCID_ATTRIBUTE: 1901 */ 1902 #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001) 1903 #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e) 1904 #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070) 1905 #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380) 1906 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400) 1907 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800) 1908 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000) 1909 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000) 1910 1911 /* 1912 * SHARED_KEY_MODE: 1913 */ 1914 #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007) 1915 #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070) 1916 #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700) 1917 #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000) 1918 #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000) 1919 #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000) 1920 #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000) 1921 #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000) 1922 1923 /* 1924 * HOST-MCU communication 1925 */ 1926 1927 /* 1928 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox. 1929 * CMD_TOKEN: Command id, 0xff disable status reporting. 1930 */ 1931 #define H2M_MAILBOX_CSR 0x7010 1932 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff) 1933 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00) 1934 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000) 1935 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000) 1936 1937 /* 1938 * H2M_MAILBOX_CID: 1939 * Free slots contain 0xff. MCU will store command's token to lowest free slot. 1940 * If all slots are occupied status will be dropped. 1941 */ 1942 #define H2M_MAILBOX_CID 0x7014 1943 #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff) 1944 #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00) 1945 #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000) 1946 #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000) 1947 1948 /* 1949 * H2M_MAILBOX_STATUS: 1950 * Command status will be saved to same slot as command id. 1951 */ 1952 #define H2M_MAILBOX_STATUS 0x701c 1953 1954 /* 1955 * H2M_INT_SRC: 1956 */ 1957 #define H2M_INT_SRC 0x7024 1958 1959 /* 1960 * H2M_BBP_AGENT: 1961 */ 1962 #define H2M_BBP_AGENT 0x7028 1963 1964 /* 1965 * MCU_LEDCS: LED control for MCU Mailbox. 1966 */ 1967 #define MCU_LEDCS_LED_MODE FIELD8(0x1f) 1968 #define MCU_LEDCS_POLARITY FIELD8(0x01) 1969 1970 /* 1971 * HW_CS_CTS_BASE: 1972 * Carrier-sense CTS frame base address. 1973 * It's where mac stores carrier-sense frame for carrier-sense function. 1974 */ 1975 #define HW_CS_CTS_BASE 0x7700 1976 1977 /* 1978 * HW_DFS_CTS_BASE: 1979 * DFS CTS frame base address. It's where mac stores CTS frame for DFS. 1980 */ 1981 #define HW_DFS_CTS_BASE 0x7780 1982 1983 /* 1984 * TXRX control registers - base address 0x3000 1985 */ 1986 1987 /* 1988 * TXRX_CSR1: 1989 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first.. 1990 */ 1991 #define TXRX_CSR1 0x77d0 1992 1993 /* 1994 * HW_DEBUG_SETTING_BASE: 1995 * since NULL frame won't be that long (256 byte) 1996 * We steal 16 tail bytes to save debugging settings 1997 */ 1998 #define HW_DEBUG_SETTING_BASE 0x77f0 1999 #define HW_DEBUG_SETTING_BASE2 0x7770 2000 2001 /* 2002 * HW_BEACON_BASE 2003 * In order to support maximum 8 MBSS and its maximum length 2004 * is 512 bytes for each beacon 2005 * Three section discontinue memory segments will be used. 2006 * 1. The original region for BCN 0~3 2007 * 2. Extract memory from FCE table for BCN 4~5 2008 * 3. Extract memory from Pair-wise key table for BCN 6~7 2009 * It occupied those memory of wcid 238~253 for BCN 6 2010 * and wcid 222~237 for BCN 7 (see Security key table memory 2011 * for more info). 2012 * 2013 * IMPORTANT NOTE: Not sure why legacy driver does this, 2014 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6. 2015 */ 2016 #define HW_BEACON_BASE0 0x7800 2017 #define HW_BEACON_BASE1 0x7a00 2018 #define HW_BEACON_BASE2 0x7c00 2019 #define HW_BEACON_BASE3 0x7e00 2020 #define HW_BEACON_BASE4 0x7200 2021 #define HW_BEACON_BASE5 0x7400 2022 #define HW_BEACON_BASE6 0x5dc0 2023 #define HW_BEACON_BASE7 0x5bc0 2024 2025 #define HW_BEACON_BASE(__index) \ 2026 (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \ 2027 (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \ 2028 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200)))) 2029 2030 #define BEACON_BASE_TO_OFFSET(_base) (((_base) - 0x4000) / 64) 2031 2032 /* 2033 * BBP registers. 2034 * The wordsize of the BBP is 8 bits. 2035 */ 2036 2037 /* 2038 * BBP 1: TX Antenna & Power Control 2039 * POWER_CTRL: 2040 * 0 - normal, 2041 * 1 - drop tx power by 6dBm, 2042 * 2 - drop tx power by 12dBm, 2043 * 3 - increase tx power by 6dBm 2044 */ 2045 #define BBP1_TX_POWER_CTRL FIELD8(0x03) 2046 #define BBP1_TX_ANTENNA FIELD8(0x18) 2047 2048 /* 2049 * BBP 3: RX Antenna 2050 */ 2051 #define BBP3_RX_ADC FIELD8(0x03) 2052 #define BBP3_RX_ANTENNA FIELD8(0x18) 2053 #define BBP3_HT40_MINUS FIELD8(0x20) 2054 #define BBP3_ADC_MODE_SWITCH FIELD8(0x40) 2055 #define BBP3_ADC_INIT_MODE FIELD8(0x80) 2056 2057 /* 2058 * BBP 4: Bandwidth 2059 */ 2060 #define BBP4_TX_BF FIELD8(0x01) 2061 #define BBP4_BANDWIDTH FIELD8(0x18) 2062 #define BBP4_MAC_IF_CTRL FIELD8(0x40) 2063 2064 /* BBP27 */ 2065 #define BBP27_RX_CHAIN_SEL FIELD8(0x60) 2066 2067 /* 2068 * BBP 47: Bandwidth 2069 */ 2070 #define BBP47_TSSI_REPORT_SEL FIELD8(0x03) 2071 #define BBP47_TSSI_UPDATE_REQ FIELD8(0x04) 2072 #define BBP47_TSSI_TSSI_MODE FIELD8(0x18) 2073 #define BBP47_TSSI_ADC6 FIELD8(0x80) 2074 2075 /* 2076 * BBP 49 2077 */ 2078 #define BBP49_UPDATE_FLAG FIELD8(0x01) 2079 2080 /* 2081 * BBP 105: 2082 * - bit0: detect SIG on primary channel only (on 40MHz bandwidth) 2083 * - bit1: FEQ (Feed Forward Compensation) for independend streams 2084 * - bit2: MLD (Maximum Likehood Detection) for 2 streams (reserved on single 2085 * stream) 2086 * - bit4: channel estimation updates based on remodulation of 2087 * L-SIG and HT-SIG symbols 2088 */ 2089 #define BBP105_DETECT_SIG_ON_PRIMARY FIELD8(0x01) 2090 #define BBP105_FEQ FIELD8(0x02) 2091 #define BBP105_MLD FIELD8(0x04) 2092 #define BBP105_SIG_REMODULATION FIELD8(0x08) 2093 2094 /* 2095 * BBP 109 2096 */ 2097 #define BBP109_TX0_POWER FIELD8(0x0f) 2098 #define BBP109_TX1_POWER FIELD8(0xf0) 2099 2100 /* BBP 110 */ 2101 #define BBP110_TX2_POWER FIELD8(0x0f) 2102 2103 2104 /* 2105 * BBP 138: Unknown 2106 */ 2107 #define BBP138_RX_ADC1 FIELD8(0x02) 2108 #define BBP138_RX_ADC2 FIELD8(0x04) 2109 #define BBP138_TX_DAC1 FIELD8(0x20) 2110 #define BBP138_TX_DAC2 FIELD8(0x40) 2111 2112 /* 2113 * BBP 152: Rx Ant 2114 */ 2115 #define BBP152_RX_DEFAULT_ANT FIELD8(0x80) 2116 2117 /* 2118 * BBP 254: unknown 2119 */ 2120 #define BBP254_BIT7 FIELD8(0x80) 2121 2122 /* 2123 * RFCSR registers 2124 * The wordsize of the RFCSR is 8 bits. 2125 */ 2126 2127 /* 2128 * RFCSR 1: 2129 */ 2130 #define RFCSR1_RF_BLOCK_EN FIELD8(0x01) 2131 #define RFCSR1_PLL_PD FIELD8(0x02) 2132 #define RFCSR1_RX0_PD FIELD8(0x04) 2133 #define RFCSR1_TX0_PD FIELD8(0x08) 2134 #define RFCSR1_RX1_PD FIELD8(0x10) 2135 #define RFCSR1_TX1_PD FIELD8(0x20) 2136 #define RFCSR1_RX2_PD FIELD8(0x40) 2137 #define RFCSR1_TX2_PD FIELD8(0x80) 2138 2139 /* 2140 * RFCSR 2: 2141 */ 2142 #define RFCSR2_RESCAL_EN FIELD8(0x80) 2143 2144 /* 2145 * RFCSR 3: 2146 */ 2147 #define RFCSR3_K FIELD8(0x0f) 2148 /* Bits [7-4] for RF3320 (RT3370/RT3390), on other chipsets reserved */ 2149 #define RFCSR3_PA1_BIAS_CCK FIELD8(0x70) 2150 #define RFCSR3_PA2_CASCODE_BIAS_CCKK FIELD8(0x80) 2151 /* Bits for RF3290/RF5360/RF5362/RF5370/RF5372/RF5390/RF5392 */ 2152 #define RFCSR3_VCOCAL_EN FIELD8(0x80) 2153 /* Bits for RF3050 */ 2154 #define RFCSR3_BIT1 FIELD8(0x02) 2155 #define RFCSR3_BIT2 FIELD8(0x04) 2156 #define RFCSR3_BIT3 FIELD8(0x08) 2157 #define RFCSR3_BIT4 FIELD8(0x10) 2158 #define RFCSR3_BIT5 FIELD8(0x20) 2159 2160 /* 2161 * FRCSR 5: 2162 */ 2163 #define RFCSR5_R1 FIELD8(0x0c) 2164 2165 /* 2166 * RFCSR 6: 2167 */ 2168 #define RFCSR6_R1 FIELD8(0x03) 2169 #define RFCSR6_R2 FIELD8(0x40) 2170 #define RFCSR6_TXDIV FIELD8(0x0c) 2171 /* bits for RF3053 */ 2172 #define RFCSR6_VCO_IC FIELD8(0xc0) 2173 2174 /* 2175 * RFCSR 7: 2176 */ 2177 #define RFCSR7_RF_TUNING FIELD8(0x01) 2178 #define RFCSR7_BIT1 FIELD8(0x02) 2179 #define RFCSR7_BIT2 FIELD8(0x04) 2180 #define RFCSR7_BIT3 FIELD8(0x08) 2181 #define RFCSR7_BIT4 FIELD8(0x10) 2182 #define RFCSR7_BIT5 FIELD8(0x20) 2183 #define RFCSR7_BITS67 FIELD8(0xc0) 2184 2185 /* 2186 * RFCSR 9: 2187 */ 2188 #define RFCSR9_K FIELD8(0x0f) 2189 #define RFCSR9_N FIELD8(0x10) 2190 #define RFCSR9_UNKNOWN FIELD8(0x60) 2191 #define RFCSR9_MOD FIELD8(0x80) 2192 2193 /* 2194 * RFCSR 11: 2195 */ 2196 #define RFCSR11_R FIELD8(0x03) 2197 #define RFCSR11_PLL_MOD FIELD8(0x0c) 2198 #define RFCSR11_MOD FIELD8(0xc0) 2199 /* bits for RF3053 */ 2200 /* TODO: verify RFCSR11_MOD usage on other chips */ 2201 #define RFCSR11_PLL_IDOH FIELD8(0x40) 2202 2203 2204 /* 2205 * RFCSR 12: 2206 */ 2207 #define RFCSR12_TX_POWER FIELD8(0x1f) 2208 #define RFCSR12_DR0 FIELD8(0xe0) 2209 2210 /* 2211 * RFCSR 13: 2212 */ 2213 #define RFCSR13_TX_POWER FIELD8(0x1f) 2214 #define RFCSR13_DR0 FIELD8(0xe0) 2215 2216 /* 2217 * RFCSR 15: 2218 */ 2219 #define RFCSR15_TX_LO2_EN FIELD8(0x08) 2220 2221 /* 2222 * RFCSR 16: 2223 */ 2224 #define RFCSR16_TXMIXER_GAIN FIELD8(0x07) 2225 2226 /* 2227 * RFCSR 17: 2228 */ 2229 #define RFCSR17_TXMIXER_GAIN FIELD8(0x07) 2230 #define RFCSR17_TX_LO1_EN FIELD8(0x08) 2231 #define RFCSR17_R FIELD8(0x20) 2232 #define RFCSR17_CODE FIELD8(0x7f) 2233 2234 /* RFCSR 18 */ 2235 #define RFCSR18_XO_TUNE_BYPASS FIELD8(0x40) 2236 2237 2238 /* 2239 * RFCSR 20: 2240 */ 2241 #define RFCSR20_RX_LO1_EN FIELD8(0x08) 2242 2243 /* 2244 * RFCSR 21: 2245 */ 2246 #define RFCSR21_RX_LO2_EN FIELD8(0x08) 2247 2248 /* 2249 * RFCSR 22: 2250 */ 2251 #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01) 2252 2253 /* 2254 * RFCSR 23: 2255 */ 2256 #define RFCSR23_FREQ_OFFSET FIELD8(0x7f) 2257 2258 /* 2259 * RFCSR 24: 2260 */ 2261 #define RFCSR24_TX_AGC_FC FIELD8(0x1f) 2262 #define RFCSR24_TX_H20M FIELD8(0x20) 2263 #define RFCSR24_TX_CALIB FIELD8(0x7f) 2264 2265 /* 2266 * RFCSR 27: 2267 */ 2268 #define RFCSR27_R1 FIELD8(0x03) 2269 #define RFCSR27_R2 FIELD8(0x04) 2270 #define RFCSR27_R3 FIELD8(0x30) 2271 #define RFCSR27_R4 FIELD8(0x40) 2272 2273 /* 2274 * RFCSR 29: 2275 */ 2276 #define RFCSR29_ADC6_TEST FIELD8(0x01) 2277 #define RFCSR29_ADC6_INT_TEST FIELD8(0x02) 2278 #define RFCSR29_RSSI_RESET FIELD8(0x04) 2279 #define RFCSR29_RSSI_ON FIELD8(0x08) 2280 #define RFCSR29_RSSI_RIP_CTRL FIELD8(0x30) 2281 #define RFCSR29_RSSI_GAIN FIELD8(0xc0) 2282 2283 /* 2284 * RFCSR 30: 2285 */ 2286 #define RFCSR30_TX_H20M FIELD8(0x02) 2287 #define RFCSR30_RX_H20M FIELD8(0x04) 2288 #define RFCSR30_RX_VCM FIELD8(0x18) 2289 #define RFCSR30_RF_CALIBRATION FIELD8(0x80) 2290 #define RF3322_RFCSR30_TX_H20M FIELD8(0x01) 2291 #define RF3322_RFCSR30_RX_H20M FIELD8(0x02) 2292 2293 /* 2294 * RFCSR 31: 2295 */ 2296 #define RFCSR31_RX_AGC_FC FIELD8(0x1f) 2297 #define RFCSR31_RX_H20M FIELD8(0x20) 2298 #define RFCSR31_RX_CALIB FIELD8(0x7f) 2299 2300 /* RFCSR 32 bits for RF3053 */ 2301 #define RFCSR32_TX_AGC_FC FIELD8(0xf8) 2302 2303 /* RFCSR 36 bits for RF3053 */ 2304 #define RFCSR36_RF_BS FIELD8(0x80) 2305 2306 /* 2307 * RFCSR 34: 2308 */ 2309 #define RFCSR34_TX0_EXT_PA FIELD8(0x04) 2310 #define RFCSR34_TX1_EXT_PA FIELD8(0x08) 2311 2312 /* 2313 * RFCSR 38: 2314 */ 2315 #define RFCSR38_RX_LO1_EN FIELD8(0x20) 2316 2317 /* 2318 * RFCSR 39: 2319 */ 2320 #define RFCSR39_RX_DIV FIELD8(0x40) 2321 #define RFCSR39_RX_LO2_EN FIELD8(0x80) 2322 2323 /* 2324 * RFCSR 41: 2325 */ 2326 #define RFCSR41_BIT1 FIELD8(0x01) 2327 #define RFCSR41_BIT4 FIELD8(0x08) 2328 2329 /* 2330 * RFCSR 42: 2331 */ 2332 #define RFCSR42_BIT1 FIELD8(0x01) 2333 #define RFCSR42_BIT4 FIELD8(0x08) 2334 2335 /* 2336 * RFCSR 49: 2337 */ 2338 #define RFCSR49_TX FIELD8(0x3f) 2339 #define RFCSR49_EP FIELD8(0xc0) 2340 /* bits for RT3593 */ 2341 #define RFCSR49_TX_LO1_IC FIELD8(0x1c) 2342 #define RFCSR49_TX_DIV FIELD8(0x20) 2343 2344 /* 2345 * RFCSR 50: 2346 */ 2347 #define RFCSR50_TX FIELD8(0x3f) 2348 #define RFCSR50_TX0_EXT_PA FIELD8(0x02) 2349 #define RFCSR50_TX1_EXT_PA FIELD8(0x10) 2350 #define RFCSR50_EP FIELD8(0xc0) 2351 /* bits for RT3593 */ 2352 #define RFCSR50_TX_LO1_EN FIELD8(0x20) 2353 #define RFCSR50_TX_LO2_EN FIELD8(0x10) 2354 2355 /* RFCSR 51 */ 2356 /* bits for RT3593 */ 2357 #define RFCSR51_BITS01 FIELD8(0x03) 2358 #define RFCSR51_BITS24 FIELD8(0x1c) 2359 #define RFCSR51_BITS57 FIELD8(0xe0) 2360 2361 #define RFCSR53_TX_POWER FIELD8(0x3f) 2362 #define RFCSR53_UNKNOWN FIELD8(0xc0) 2363 2364 #define RFCSR54_TX_POWER FIELD8(0x3f) 2365 #define RFCSR54_UNKNOWN FIELD8(0xc0) 2366 2367 #define RFCSR55_TX_POWER FIELD8(0x3f) 2368 #define RFCSR55_UNKNOWN FIELD8(0xc0) 2369 2370 #define RFCSR57_DRV_CC FIELD8(0xfc) 2371 2372 2373 /* 2374 * RF registers 2375 */ 2376 2377 /* 2378 * RF 2 2379 */ 2380 #define RF2_ANTENNA_RX2 FIELD32(0x00000040) 2381 #define RF2_ANTENNA_TX1 FIELD32(0x00004000) 2382 #define RF2_ANTENNA_RX1 FIELD32(0x00020000) 2383 2384 /* 2385 * RF 3 2386 */ 2387 #define RF3_TXPOWER_G FIELD32(0x00003e00) 2388 #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200) 2389 #define RF3_TXPOWER_A FIELD32(0x00003c00) 2390 2391 /* 2392 * RF 4 2393 */ 2394 #define RF4_TXPOWER_G FIELD32(0x000007c0) 2395 #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040) 2396 #define RF4_TXPOWER_A FIELD32(0x00000780) 2397 #define RF4_FREQ_OFFSET FIELD32(0x001f8000) 2398 #define RF4_HT40 FIELD32(0x00200000) 2399 2400 /* 2401 * EEPROM content. 2402 * The wordsize of the EEPROM is 16 bits. 2403 */ 2404 2405 enum rt2800_eeprom_word { 2406 EEPROM_CHIP_ID = 0, 2407 EEPROM_VERSION, 2408 EEPROM_MAC_ADDR_0, 2409 EEPROM_MAC_ADDR_1, 2410 EEPROM_MAC_ADDR_2, 2411 EEPROM_NIC_CONF0, 2412 EEPROM_NIC_CONF1, 2413 EEPROM_FREQ, 2414 EEPROM_LED_AG_CONF, 2415 EEPROM_LED_ACT_CONF, 2416 EEPROM_LED_POLARITY, 2417 EEPROM_NIC_CONF2, 2418 EEPROM_LNA, 2419 EEPROM_RSSI_BG, 2420 EEPROM_RSSI_BG2, 2421 EEPROM_TXMIXER_GAIN_BG, 2422 EEPROM_RSSI_A, 2423 EEPROM_RSSI_A2, 2424 EEPROM_TXMIXER_GAIN_A, 2425 EEPROM_EIRP_MAX_TX_POWER, 2426 EEPROM_TXPOWER_DELTA, 2427 EEPROM_TXPOWER_BG1, 2428 EEPROM_TXPOWER_BG2, 2429 EEPROM_TSSI_BOUND_BG1, 2430 EEPROM_TSSI_BOUND_BG2, 2431 EEPROM_TSSI_BOUND_BG3, 2432 EEPROM_TSSI_BOUND_BG4, 2433 EEPROM_TSSI_BOUND_BG5, 2434 EEPROM_TXPOWER_A1, 2435 EEPROM_TXPOWER_A2, 2436 EEPROM_TSSI_BOUND_A1, 2437 EEPROM_TSSI_BOUND_A2, 2438 EEPROM_TSSI_BOUND_A3, 2439 EEPROM_TSSI_BOUND_A4, 2440 EEPROM_TSSI_BOUND_A5, 2441 EEPROM_TXPOWER_BYRATE, 2442 EEPROM_BBP_START, 2443 2444 /* IDs for extended EEPROM format used by three-chain devices */ 2445 EEPROM_EXT_LNA2, 2446 EEPROM_EXT_TXPOWER_BG3, 2447 EEPROM_EXT_TXPOWER_A3, 2448 2449 /* New values must be added before this */ 2450 EEPROM_WORD_COUNT 2451 }; 2452 2453 /* 2454 * EEPROM Version 2455 */ 2456 #define EEPROM_VERSION_FAE FIELD16(0x00ff) 2457 #define EEPROM_VERSION_VERSION FIELD16(0xff00) 2458 2459 /* 2460 * HW MAC address. 2461 */ 2462 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) 2463 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) 2464 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) 2465 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) 2466 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) 2467 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) 2468 2469 /* 2470 * EEPROM NIC Configuration 0 2471 * RXPATH: 1: 1R, 2: 2R, 3: 3R 2472 * TXPATH: 1: 1T, 2: 2T, 3: 3T 2473 * RF_TYPE: RFIC type 2474 */ 2475 #define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f) 2476 #define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0) 2477 #define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00) 2478 2479 /* 2480 * EEPROM NIC Configuration 1 2481 * HW_RADIO: 0: disable, 1: enable 2482 * EXTERNAL_TX_ALC: 0: disable, 1: enable 2483 * EXTERNAL_LNA_2G: 0: disable, 1: enable 2484 * EXTERNAL_LNA_5G: 0: disable, 1: enable 2485 * CARDBUS_ACCEL: 0: enable, 1: disable 2486 * BW40M_SB_2G: 0: disable, 1: enable 2487 * BW40M_SB_5G: 0: disable, 1: enable 2488 * WPS_PBC: 0: disable, 1: enable 2489 * BW40M_2G: 0: enable, 1: disable 2490 * BW40M_5G: 0: enable, 1: disable 2491 * BROADBAND_EXT_LNA: 0: disable, 1: enable 2492 * ANT_DIVERSITY: 00: Disable, 01: Diversity, 2493 * 10: Main antenna, 11: Aux antenna 2494 * INTERNAL_TX_ALC: 0: disable, 1: enable 2495 * BT_COEXIST: 0: disable, 1: enable 2496 * DAC_TEST: 0: disable, 1: enable 2497 * EXTERNAL_TX0_PA: 0: disable, 1: enable (only on RT3352) 2498 * EXTERNAL_TX1_PA: 0: disable, 1: enable (only on RT3352) 2499 */ 2500 #define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001) 2501 #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002) 2502 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004) 2503 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008) 2504 #define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010) 2505 #define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020) 2506 #define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040) 2507 #define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080) 2508 #define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100) 2509 #define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200) 2510 #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400) 2511 #define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800) 2512 #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000) 2513 #define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000) 2514 #define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000) 2515 #define EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352 FIELD16(0x4000) 2516 #define EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352 FIELD16(0x8000) 2517 2518 /* 2519 * EEPROM frequency 2520 */ 2521 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff) 2522 #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00) 2523 #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000) 2524 2525 /* 2526 * EEPROM LED 2527 * POLARITY_RDY_G: Polarity RDY_G setting. 2528 * POLARITY_RDY_A: Polarity RDY_A setting. 2529 * POLARITY_ACT: Polarity ACT setting. 2530 * POLARITY_GPIO_0: Polarity GPIO0 setting. 2531 * POLARITY_GPIO_1: Polarity GPIO1 setting. 2532 * POLARITY_GPIO_2: Polarity GPIO2 setting. 2533 * POLARITY_GPIO_3: Polarity GPIO3 setting. 2534 * POLARITY_GPIO_4: Polarity GPIO4 setting. 2535 * LED_MODE: Led mode. 2536 */ 2537 #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001) 2538 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002) 2539 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004) 2540 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008) 2541 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010) 2542 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020) 2543 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040) 2544 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080) 2545 #define EEPROM_LED_LED_MODE FIELD16(0x1f00) 2546 2547 /* 2548 * EEPROM NIC Configuration 2 2549 * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream 2550 * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream 2551 * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved 2552 */ 2553 #define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f) 2554 #define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0) 2555 #define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600) 2556 2557 /* 2558 * EEPROM LNA 2559 */ 2560 #define EEPROM_LNA_BG FIELD16(0x00ff) 2561 #define EEPROM_LNA_A0 FIELD16(0xff00) 2562 2563 /* 2564 * EEPROM RSSI BG offset 2565 */ 2566 #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff) 2567 #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00) 2568 2569 /* 2570 * EEPROM RSSI BG2 offset 2571 */ 2572 #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff) 2573 #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00) 2574 2575 /* 2576 * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2). 2577 */ 2578 #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007) 2579 2580 /* 2581 * EEPROM RSSI A offset 2582 */ 2583 #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff) 2584 #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00) 2585 2586 /* 2587 * EEPROM RSSI A2 offset 2588 */ 2589 #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff) 2590 #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00) 2591 2592 /* 2593 * EEPROM TXMIXER GAIN A offset (note overlaps with EEPROM RSSI A2). 2594 */ 2595 #define EEPROM_TXMIXER_GAIN_A_VAL FIELD16(0x0007) 2596 2597 /* 2598 * EEPROM EIRP Maximum TX power values(unit: dbm) 2599 */ 2600 #define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff) 2601 #define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00) 2602 2603 /* 2604 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power. 2605 * This is delta in 40MHZ. 2606 * VALUE: Tx Power dalta value, MAX=4(unit: dbm) 2607 * TYPE: 1: Plus the delta value, 0: minus the delta value 2608 * ENABLE: enable tx power compensation for 40BW 2609 */ 2610 #define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f) 2611 #define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040) 2612 #define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080) 2613 #define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00) 2614 #define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000) 2615 #define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000) 2616 2617 /* 2618 * EEPROM TXPOWER 802.11BG 2619 */ 2620 #define EEPROM_TXPOWER_BG_SIZE 7 2621 #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff) 2622 #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00) 2623 2624 /* 2625 * EEPROM temperature compensation boundaries 802.11BG 2626 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be 2627 * reduced by (agc_step * -4) 2628 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be 2629 * reduced by (agc_step * -3) 2630 */ 2631 #define EEPROM_TSSI_BOUND_BG1_MINUS4 FIELD16(0x00ff) 2632 #define EEPROM_TSSI_BOUND_BG1_MINUS3 FIELD16(0xff00) 2633 2634 /* 2635 * EEPROM temperature compensation boundaries 802.11BG 2636 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be 2637 * reduced by (agc_step * -2) 2638 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be 2639 * reduced by (agc_step * -1) 2640 */ 2641 #define EEPROM_TSSI_BOUND_BG2_MINUS2 FIELD16(0x00ff) 2642 #define EEPROM_TSSI_BOUND_BG2_MINUS1 FIELD16(0xff00) 2643 2644 /* 2645 * EEPROM temperature compensation boundaries 802.11BG 2646 * REF: Reference TSSI value, no tx power changes needed 2647 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be 2648 * increased by (agc_step * 1) 2649 */ 2650 #define EEPROM_TSSI_BOUND_BG3_REF FIELD16(0x00ff) 2651 #define EEPROM_TSSI_BOUND_BG3_PLUS1 FIELD16(0xff00) 2652 2653 /* 2654 * EEPROM temperature compensation boundaries 802.11BG 2655 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be 2656 * increased by (agc_step * 2) 2657 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be 2658 * increased by (agc_step * 3) 2659 */ 2660 #define EEPROM_TSSI_BOUND_BG4_PLUS2 FIELD16(0x00ff) 2661 #define EEPROM_TSSI_BOUND_BG4_PLUS3 FIELD16(0xff00) 2662 2663 /* 2664 * EEPROM temperature compensation boundaries 802.11BG 2665 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be 2666 * increased by (agc_step * 4) 2667 * AGC_STEP: Temperature compensation step. 2668 */ 2669 #define EEPROM_TSSI_BOUND_BG5_PLUS4 FIELD16(0x00ff) 2670 #define EEPROM_TSSI_BOUND_BG5_AGC_STEP FIELD16(0xff00) 2671 2672 /* 2673 * EEPROM TXPOWER 802.11A 2674 */ 2675 #define EEPROM_TXPOWER_A_SIZE 6 2676 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff) 2677 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00) 2678 2679 /* EEPROM_TXPOWER_{A,G} fields for RT3593 */ 2680 #define EEPROM_TXPOWER_ALC FIELD8(0x1f) 2681 #define EEPROM_TXPOWER_FINE_CTRL FIELD8(0xe0) 2682 2683 /* 2684 * EEPROM temperature compensation boundaries 802.11A 2685 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be 2686 * reduced by (agc_step * -4) 2687 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be 2688 * reduced by (agc_step * -3) 2689 */ 2690 #define EEPROM_TSSI_BOUND_A1_MINUS4 FIELD16(0x00ff) 2691 #define EEPROM_TSSI_BOUND_A1_MINUS3 FIELD16(0xff00) 2692 2693 /* 2694 * EEPROM temperature compensation boundaries 802.11A 2695 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be 2696 * reduced by (agc_step * -2) 2697 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be 2698 * reduced by (agc_step * -1) 2699 */ 2700 #define EEPROM_TSSI_BOUND_A2_MINUS2 FIELD16(0x00ff) 2701 #define EEPROM_TSSI_BOUND_A2_MINUS1 FIELD16(0xff00) 2702 2703 /* 2704 * EEPROM temperature compensation boundaries 802.11A 2705 * REF: Reference TSSI value, no tx power changes needed 2706 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be 2707 * increased by (agc_step * 1) 2708 */ 2709 #define EEPROM_TSSI_BOUND_A3_REF FIELD16(0x00ff) 2710 #define EEPROM_TSSI_BOUND_A3_PLUS1 FIELD16(0xff00) 2711 2712 /* 2713 * EEPROM temperature compensation boundaries 802.11A 2714 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be 2715 * increased by (agc_step * 2) 2716 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be 2717 * increased by (agc_step * 3) 2718 */ 2719 #define EEPROM_TSSI_BOUND_A4_PLUS2 FIELD16(0x00ff) 2720 #define EEPROM_TSSI_BOUND_A4_PLUS3 FIELD16(0xff00) 2721 2722 /* 2723 * EEPROM temperature compensation boundaries 802.11A 2724 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be 2725 * increased by (agc_step * 4) 2726 * AGC_STEP: Temperature compensation step. 2727 */ 2728 #define EEPROM_TSSI_BOUND_A5_PLUS4 FIELD16(0x00ff) 2729 #define EEPROM_TSSI_BOUND_A5_AGC_STEP FIELD16(0xff00) 2730 2731 /* 2732 * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode 2733 */ 2734 #define EEPROM_TXPOWER_BYRATE_SIZE 9 2735 2736 #define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f) 2737 #define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0) 2738 #define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00) 2739 #define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000) 2740 2741 /* 2742 * EEPROM BBP. 2743 */ 2744 #define EEPROM_BBP_SIZE 16 2745 #define EEPROM_BBP_VALUE FIELD16(0x00ff) 2746 #define EEPROM_BBP_REG_ID FIELD16(0xff00) 2747 2748 /* EEPROM_EXT_LNA2 */ 2749 #define EEPROM_EXT_LNA2_A1 FIELD16(0x00ff) 2750 #define EEPROM_EXT_LNA2_A2 FIELD16(0xff00) 2751 2752 /* 2753 * EEPROM IQ Calibration, unlike other entries those are byte addresses. 2754 */ 2755 2756 #define EEPROM_IQ_GAIN_CAL_TX0_2G 0x130 2757 #define EEPROM_IQ_PHASE_CAL_TX0_2G 0x131 2758 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_2G 0x132 2759 #define EEPROM_IQ_GAIN_CAL_TX1_2G 0x133 2760 #define EEPROM_IQ_PHASE_CAL_TX1_2G 0x134 2761 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_2G 0x135 2762 #define EEPROM_IQ_GAIN_CAL_RX0_2G 0x136 2763 #define EEPROM_IQ_PHASE_CAL_RX0_2G 0x137 2764 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_2G 0x138 2765 #define EEPROM_IQ_GAIN_CAL_RX1_2G 0x139 2766 #define EEPROM_IQ_PHASE_CAL_RX1_2G 0x13A 2767 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_2G 0x13B 2768 #define EEPROM_RF_IQ_COMPENSATION_CONTROL 0x13C 2769 #define EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL 0x13D 2770 #define EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G 0x144 2771 #define EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G 0x145 2772 #define EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G 0X146 2773 #define EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G 0x147 2774 #define EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G 0x148 2775 #define EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G 0x149 2776 #define EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G 0x14A 2777 #define EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G 0x14B 2778 #define EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G 0X14C 2779 #define EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G 0x14D 2780 #define EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G 0x14E 2781 #define EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G 0x14F 2782 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH36_TO_CH64_5G 0x150 2783 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH36_TO_CH64_5G 0x151 2784 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH100_TO_CH138_5G 0x152 2785 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH100_TO_CH138_5G 0x153 2786 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH140_TO_CH165_5G 0x154 2787 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH140_TO_CH165_5G 0x155 2788 #define EEPROM_IQ_GAIN_CAL_RX0_CH36_TO_CH64_5G 0x156 2789 #define EEPROM_IQ_PHASE_CAL_RX0_CH36_TO_CH64_5G 0x157 2790 #define EEPROM_IQ_GAIN_CAL_RX0_CH100_TO_CH138_5G 0X158 2791 #define EEPROM_IQ_PHASE_CAL_RX0_CH100_TO_CH138_5G 0x159 2792 #define EEPROM_IQ_GAIN_CAL_RX0_CH140_TO_CH165_5G 0x15A 2793 #define EEPROM_IQ_PHASE_CAL_RX0_CH140_TO_CH165_5G 0x15B 2794 #define EEPROM_IQ_GAIN_CAL_RX1_CH36_TO_CH64_5G 0x15C 2795 #define EEPROM_IQ_PHASE_CAL_RX1_CH36_TO_CH64_5G 0x15D 2796 #define EEPROM_IQ_GAIN_CAL_RX1_CH100_TO_CH138_5G 0X15E 2797 #define EEPROM_IQ_PHASE_CAL_RX1_CH100_TO_CH138_5G 0x15F 2798 #define EEPROM_IQ_GAIN_CAL_RX1_CH140_TO_CH165_5G 0x160 2799 #define EEPROM_IQ_PHASE_CAL_RX1_CH140_TO_CH165_5G 0x161 2800 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH36_TO_CH64_5G 0x162 2801 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH36_TO_CH64_5G 0x163 2802 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH100_TO_CH138_5G 0x164 2803 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH100_TO_CH138_5G 0x165 2804 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH140_TO_CH165_5G 0x166 2805 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH140_TO_CH165_5G 0x167 2806 2807 /* 2808 * MCU mailbox commands. 2809 * MCU_SLEEP - go to power-save mode. 2810 * arg1: 1: save as much power as possible, 0: save less power. 2811 * status: 1: success, 2: already asleep, 2812 * 3: maybe MAC is busy so can't finish this task. 2813 * MCU_RADIO_OFF 2814 * arg0: 0: do power-saving, NOT turn off radio. 2815 */ 2816 #define MCU_SLEEP 0x30 2817 #define MCU_WAKEUP 0x31 2818 #define MCU_RADIO_OFF 0x35 2819 #define MCU_CURRENT 0x36 2820 #define MCU_LED 0x50 2821 #define MCU_LED_STRENGTH 0x51 2822 #define MCU_LED_AG_CONF 0x52 2823 #define MCU_LED_ACT_CONF 0x53 2824 #define MCU_LED_LED_POLARITY 0x54 2825 #define MCU_RADAR 0x60 2826 #define MCU_BOOT_SIGNAL 0x72 2827 #define MCU_ANT_SELECT 0X73 2828 #define MCU_FREQ_OFFSET 0x74 2829 #define MCU_BBP_SIGNAL 0x80 2830 #define MCU_POWER_SAVE 0x83 2831 #define MCU_BAND_SELECT 0x91 2832 2833 /* 2834 * MCU mailbox tokens 2835 */ 2836 #define TOKEN_SLEEP 1 2837 #define TOKEN_RADIO_OFF 2 2838 #define TOKEN_WAKEUP 3 2839 2840 2841 /* 2842 * DMA descriptor defines. 2843 */ 2844 2845 #define TXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32)) 2846 #define TXWI_DESC_SIZE_5WORDS (5 * sizeof(__le32)) 2847 2848 #define RXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32)) 2849 #define RXWI_DESC_SIZE_5WORDS (5 * sizeof(__le32)) 2850 #define RXWI_DESC_SIZE_6WORDS (6 * sizeof(__le32)) 2851 2852 /* 2853 * TX WI structure 2854 */ 2855 2856 /* 2857 * Word0 2858 * FRAG: 1 To inform TKIP engine this is a fragment. 2859 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode 2860 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs 2861 * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will 2862 * duplicate the frame to both channels). 2863 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED 2864 * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will 2865 * aggregate consecutive frames with the same RA and QoS TID. If 2866 * a frame A with the same RA and QoS TID but AMPDU=0 is queued 2867 * directly after a frame B with AMPDU=1, frame A might still 2868 * get aggregated into the AMPDU started by frame B. So, setting 2869 * AMPDU to 0 does _not_ necessarily mean the frame is sent as 2870 * MPDU, it can still end up in an AMPDU if the previous frame 2871 * was tagged as AMPDU. 2872 */ 2873 #define TXWI_W0_FRAG FIELD32(0x00000001) 2874 #define TXWI_W0_MIMO_PS FIELD32(0x00000002) 2875 #define TXWI_W0_CF_ACK FIELD32(0x00000004) 2876 #define TXWI_W0_TS FIELD32(0x00000008) 2877 #define TXWI_W0_AMPDU FIELD32(0x00000010) 2878 #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0) 2879 #define TXWI_W0_TX_OP FIELD32(0x00000300) 2880 #define TXWI_W0_MCS FIELD32(0x007f0000) 2881 #define TXWI_W0_BW FIELD32(0x00800000) 2882 #define TXWI_W0_SHORT_GI FIELD32(0x01000000) 2883 #define TXWI_W0_STBC FIELD32(0x06000000) 2884 #define TXWI_W0_IFS FIELD32(0x08000000) 2885 #define TXWI_W0_PHYMODE FIELD32(0xc0000000) 2886 2887 /* 2888 * Word1 2889 * ACK: 0: No Ack needed, 1: Ack needed 2890 * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number 2891 * BW_WIN_SIZE: BA windows size of the recipient 2892 * WIRELESS_CLI_ID: Client ID for WCID table access 2893 * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame 2894 * PACKETID: Will be latched into the TX_STA_FIFO register once the according 2895 * frame was processed. If multiple frames are aggregated together 2896 * (AMPDU==1) the reported tx status will always contain the packet 2897 * id of the first frame. 0: Don't report tx status for this frame. 2898 * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3) 2899 * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3) 2900 * This identification number is calculated by ((idx % 3) + 1). 2901 * The (+1) is required to prevent PACKETID to become 0. 2902 */ 2903 #define TXWI_W1_ACK FIELD32(0x00000001) 2904 #define TXWI_W1_NSEQ FIELD32(0x00000002) 2905 #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc) 2906 #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00) 2907 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) 2908 #define TXWI_W1_PACKETID FIELD32(0xf0000000) 2909 #define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000) 2910 #define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000) 2911 2912 /* 2913 * Word2 2914 */ 2915 #define TXWI_W2_IV FIELD32(0xffffffff) 2916 2917 /* 2918 * Word3 2919 */ 2920 #define TXWI_W3_EIV FIELD32(0xffffffff) 2921 2922 /* 2923 * RX WI structure 2924 */ 2925 2926 /* 2927 * Word0 2928 */ 2929 #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff) 2930 #define RXWI_W0_KEY_INDEX FIELD32(0x00000300) 2931 #define RXWI_W0_BSSID FIELD32(0x00001c00) 2932 #define RXWI_W0_UDF FIELD32(0x0000e000) 2933 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) 2934 #define RXWI_W0_TID FIELD32(0xf0000000) 2935 2936 /* 2937 * Word1 2938 */ 2939 #define RXWI_W1_FRAG FIELD32(0x0000000f) 2940 #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0) 2941 #define RXWI_W1_MCS FIELD32(0x007f0000) 2942 #define RXWI_W1_BW FIELD32(0x00800000) 2943 #define RXWI_W1_SHORT_GI FIELD32(0x01000000) 2944 #define RXWI_W1_STBC FIELD32(0x06000000) 2945 #define RXWI_W1_PHYMODE FIELD32(0xc0000000) 2946 2947 /* 2948 * Word2 2949 */ 2950 #define RXWI_W2_RSSI0 FIELD32(0x000000ff) 2951 #define RXWI_W2_RSSI1 FIELD32(0x0000ff00) 2952 #define RXWI_W2_RSSI2 FIELD32(0x00ff0000) 2953 2954 /* 2955 * Word3 2956 */ 2957 #define RXWI_W3_SNR0 FIELD32(0x000000ff) 2958 #define RXWI_W3_SNR1 FIELD32(0x0000ff00) 2959 2960 /* 2961 * Macros for converting txpower from EEPROM to mac80211 value 2962 * and from mac80211 value to register value. 2963 */ 2964 #define MIN_G_TXPOWER 0 2965 #define MIN_A_TXPOWER -7 2966 #define MAX_G_TXPOWER 31 2967 #define MAX_A_TXPOWER 15 2968 #define DEFAULT_TXPOWER 5 2969 2970 #define MIN_A_TXPOWER_3593 0 2971 #define MAX_A_TXPOWER_3593 31 2972 2973 #define TXPOWER_G_FROM_DEV(__txpower) \ 2974 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) 2975 2976 #define TXPOWER_A_FROM_DEV(__txpower) \ 2977 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) 2978 2979 /* 2980 * Board's maximun TX power limitation 2981 */ 2982 #define EIRP_MAX_TX_POWER_LIMIT 0x50 2983 2984 /* 2985 * Number of TBTT intervals after which we have to adjust 2986 * the hw beacon timer. 2987 */ 2988 #define BCN_TBTT_OFFSET 64 2989 2990 /* 2991 * Hardware has 255 WCID table entries. First 32 entries are reserved for 2992 * shared keys. Since parts of the pairwise key table might be shared with 2993 * the beacon frame buffers 6 & 7 we could only use the first 222 entries. 2994 */ 2995 #define WCID_START 33 2996 #define WCID_END 222 2997 #define STA_IDS_SIZE (WCID_END - WCID_START + 2) 2998 2999 /* 3000 * RT2800 driver data structure 3001 */ 3002 struct rt2800_drv_data { 3003 u8 calibration_bw20; 3004 u8 calibration_bw40; 3005 u8 bbp25; 3006 u8 bbp26; 3007 u8 txmixer_gain_24g; 3008 u8 txmixer_gain_5g; 3009 u8 max_psdu; 3010 unsigned int tbtt_tick; 3011 unsigned int ampdu_factor_cnt[4]; 3012 DECLARE_BITMAP(sta_ids, STA_IDS_SIZE); 3013 }; 3014 3015 #endif /* RT2800_H */ 3016